STM32L552ZEY6QXXX [STMICROELECTRONICS]
Ultra-low-power Arm® Cortex®-M33 32-bit MCUTrustZone®FPU, 165 DMIPS, up to 512 KB Flash memory, 256 KB SRAM, SMPS;
| 型号： | STM32L552ZEY6QXXX |
| 厂家： | 
ST |
| 描述： | Ultra-low-power Arm® Cortex®-M33 32-bit MCUTrustZone®FPU, 165 DMIPS, up to 512 KB Flash memory, 256 KB SRAM, SMPS 静态存储器 |
| 文件： | 总340页 (文件大小：6483K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
STM32L552xx
Ultra-low-power Arm® Cortex®-M33 32-bit MCU+TrustZone®+FPU,
165 DMIPS, up to 512 KB Flash memory, 256 KB SRAM, SMPS
Datasheet - production data
Features
Ultra-low-power with FlexPowerControl
• 1.71 V to 3.6 V power supply
UFQFPN48 (7 x 7 mm)
LQFP48 (7 x 7 mm)
LQFP64 (10 x 10 mm)
(*)
• -40 °C to 85/125 °C temperature range
• Batch acquisition mode (BAM)
LQFP100 (14 x14 mm)
LQFP144 (20 x 20mm)
FBGA
• 187 nA in VBAT mode: supply for RTC and
32x32-bit backup registers
• 17 nA Shutdown mode (5 wakeup pins)
• 108 nA Standby mode (5 wakeup pins)
• 222 nA Standby mode with RTC
• 3.16 μA Stop 2 with RTC
WLCSP81 (4.36 x 4.07 mm)
UFBGA132 (7 x 7 mm)
(*): Silhouette shown above.
Memories
• 106 μA/MHz Run mode (LDO mode)
• Up to 512-Kbyte Flash, two banks read-while-
• 62 μA/MHz Run mode @ 3 V
write
(SMPS step-down converter mode)
• 256 Kbytes of SRAM including 64 Kbytes with
• 5 µs wakeup from Stop mode
hardware parity check
• Brownout reset (BOR) in all modes except
• External memory interface supporting SRAM,
Shutdown
PSRAM, NOR, NAND and FRAM memories
• OCTOSPI memory interface
Core
®
®
• Arm 32-bit Cortex -M33 CPU with
Security
®
TrustZone and FPU
®
®
• Arm TrustZone and securable I/Os,
memories and peripherals
ART Accelerator
• Flexible life cycle scheme with RDP (readout
• 8-Kbyte instruction cache allowing 0-wait-state
execution from Flash memory and external
memories; frequency up to 110 MHz, MPU,
165 DMIPS and DSP instructions
protection)
• Root of trust thanks to unique boot entry and
hide protection area (HDP)
• SFI (secure firmware installation) thanks to
Performance benckmark
embedded RSS (root secure services)
• 1.5 DMIPS/MHz (Drystone 2.1)
• Secure firmware upgrade support with TF-M
• HASH hardware accelerator
®
®
• 442 CoreMark (4.02 CoreMark /MHz)
• Active tamper and protection against
Energy benchmark
temperature, voltage and frequency attacks
®
• 370 ULPMark-CP score
• True random number generator NIST SP800-
®
• 54 ULPMark-PP score
90B compliant
®
• 27400 SecureMark-TLS score
• 96-bit unique ID
October 2020
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This is information on a product in full production.
www.st.com
STM32L552xx
• 512-byte OTP (one-time programmable) for
Up to 19 communication peripherals
user data
• 1x USB Type-C™/ USB power delivery
controller
General-purpose input/outputs
• 1x USB 2.0 full-speed crystal less solution,
• Up to 114 fast I/Os with interrupt capability
most 5 V-tolerant and up to 14 I/Os with
independent supply down to 1.08 V
LPM and BCD
• 2x SAIs (serial audio interface)
• 4x I2C FM+(1 Mbit/s), SMBus/PMBus™
• 6x USARTs (ISO 7816, LIN, IrDA, modem)
Power management
• Embedded regulator (LDO) with three
configurable range output to supply the digital
circuitry
• 3x SPIs (7x SPIs with USART and OCTOSPI in
SPI mode)
• 1x FDCAN controller
• 1x SDMMC interface
• Embedded SMPS step-down converter
• External SMPS support
2 DMA controllers
Clock management
• 14 DMA channels
• 4 to 48 MHz crystal oscillator
Up to 22 capacitive sensing channels
• 32 kHz crystal oscillator for RTC (LSE)
• Internal 16 MHz factory-trimmed RC (±1%)
• Internal low-power 32 kHz RC (±5%)
• Support touch key, linear and rotary touch
sensors
• Internal multispeed 100 kHz to 48 MHz
oscillator, auto-trimmed by LSE (better than
±0.25% accuracy)
Rich analog peripherals (independent
supply)
• 2x 12-bit ADC 5 Msps, up to 16-bit with
• Internal 48 MHz with clock recovery
hardware oversampling, 200 µA/Msps
• 3 PLLs for system clock, USB, audio, ADC
• 2x 12-bit DAC outputs, low-power sample and
hold
Up to 16 timers and 2 watchdogs
• 2x operational amplifiers with built-in PGA
• 2x ultra-low-power comparators
• 16x timers: 2 x 16-bit advanced motor-control,
2 x 32-bit and 5 x 16-bit general purpose, 2x
16-bit basic, 3x low-power 16-bit timers
(available in Stop mode), 2x watchdogs, 2x
SysTick timer
• 4x digital filters for sigma delta modulator
CRC calculation unit
• RTC with hardware calendar, alarms and
Debug
calibration
• Development support: serial wire debug
(SWD), JTAG, Embedded Trace Macrocell™
(ETM)
Table 1. Device summary
Reference
Part numbers
STM32L552CC, STM32L552CE, STM32L552ME, STM32L552QC, STM32L552QE,
STM32L552RC, STM32L552RE, STM32L552VC, STM32L552VE, STM32L552ZC,
STM32L552ZE
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Contents
Contents
1
2
3
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.1
3.2
3.3
3.4
3.5
3.6
3.7
3.8
Arm® Cortex®-M33 core with TrustZone® and FPU . . . . . . . . . . . . . . . . . 20
Art Accelerator – instruction cache (ICACHE) . . . . . . . . . . . . . . . . . . . . . 20
Memory protection unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Embedded Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Embedded SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Global TrustZone controller (GTZC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
TrustZone security architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.8.1
TrustZone peripheral classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.9
Power supply management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
3.9.1
3.9.2
3.9.3
3.9.4
3.9.5
3.9.6
3.9.7
3.9.8
Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
SMPS step down converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Reset mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
VBAT operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
PWR TrustZone security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
3.10 Peripheral interconnect matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
3.11 Reset and clock controller (RCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
3.12 Clock recovery system (CRS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
3.13 General-purpose inputs/outputs (GPIOs) . . . . . . . . . . . . . . . . . . . . . . . . . 53
3.14 Multi-AHB bus matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
3.15 Direct memory access controller (DMA) . . . . . . . . . . . . . . . . . . . . . . . . . . 55
3.16 DMA request router (DMAMUX) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
3.17 Interrupts and events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
3.17.1 Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . 57
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3.17.2 Extended interrupt/event controller (EXTI) . . . . . . . . . . . . . . . . . . . . . . 57
3.18 Cyclic redundancy check calculation unit (CRC) . . . . . . . . . . . . . . . . . . . 58
3.19 Flexible static memory controller (FSMC) . . . . . . . . . . . . . . . . . . . . . . . . 58
3.20 Octo-SPI interface (OCTOSPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
3.21 Analog-to-digital converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
3.21.1 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
3.21.2 Internal voltage reference (VREFINT) . . . . . . . . . . . . . . . . . . . . . . . . . . 62
3.21.3 VBAT battery voltage monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
3.22 Digital to analog converter (DAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
3.23 Voltage reference buffer (VREFBUF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
3.24 Comparators (COMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
3.25 Operational amplifier (OPAMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
3.26 Digital filter for sigma-delta modulators (DFSDM) . . . . . . . . . . . . . . . . . . 64
3.27 Touch sensing controller (TSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
3.28 True random number generator (RNG) . . . . . . . . . . . . . . . . . . . . . . . . . . 67
3.29 HASH hardware accelerator (HASH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
3.30 Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
3.30.1 Advanced-control timer (TIM1, TIM8) . . . . . . . . . . . . . . . . . . . . . . . . . . 68
3.30.2 General-purpose timers (TIM2, TIM3, TIM4, TIM5, TIM15, TIM16,
TIM17) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
3.30.3 Basic timers (TIM6 and TIM7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
3.30.4 Low-power timers (LPTIM1, LPTIM2 and LPTIM3) . . . . . . . . . . . . . . . . 69
3.30.5 Independent watchdog (IWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
3.30.6 Window watchdog (WWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
3.30.7 SysTick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
3.31 Real-time clock (RTC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
3.32 Tamper and backup registers (TAMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
3.33 Inter-integrated circuit interface (I2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
3.34 Universal synchronous/asynchronous receiver transmitter (USART) . . . 74
3.35 Low-power universal asynchronous receiver transmitter (LPUART) . . . . 75
3.36 Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
3.37 Serial audio interfaces (SAI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
3.38 Secure digital input/output and MultiMediaCards Interface (SDMMC) . . . 76
3.39 Controller area network (FDCAN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
3.40 Universal serial bus (USB FS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
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3.41 USB Type-C™ / USB Power Delivery controller (UCPD) . . . . . . . . . . . . . 77
3.42 Development support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
3.42.1 Serial wire JTAG debug port (SWJ-DP) . . . . . . . . . . . . . . . . . . . . . . . . . 78
3.42.2 Embedded Trace Macrocell™ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
4
5
Pinouts and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
5.1
Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
5.1.1
5.1.2
5.1.3
5.1.4
5.1.5
5.1.6
5.1.7
Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . 142
5.2
5.3
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
5.3.1
5.3.2
5.3.3
5.3.4
5.3.5
5.3.6
5.3.7
General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
SMPS step-down converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . 148
Embedded reset and power control block characteristics . . . . . . . . . . 148
Embedded voltage reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
Wakeup time from low-power modes and voltage scaling
transition times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
5.3.8
5.3.9
External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 213
Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 218
5.3.10 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225
5.3.11 Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226
5.3.12 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227
5.3.13 Electrical sensitivity characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 228
5.3.14 I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 229
5.3.15 I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230
5.3.16 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236
5.3.17 Extended interrupt and event controller input (EXTI) characteristics . . 237
5.3.18 Analog switches booster . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238
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5.3.19 Analog-to-digital converter characteristics . . . . . . . . . . . . . . . . . . . . . . 239
5.3.20 Digital-to-Analog converter characteristics . . . . . . . . . . . . . . . . . . . . . 252
5.3.21 Voltage reference buffer characteristics . . . . . . . . . . . . . . . . . . . . . . . 257
5.3.22 Comparator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260
5.3.23 Operational amplifiers characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 261
5.3.24 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 265
5.3.25
V
monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265
BAT
5.3.26 Temperature and VDD thresholds monitoring . . . . . . . . . . . . . . . . . . . 266
5.3.27 DFSDM characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266
5.3.28 Timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268
5.3.29 Communication interfaces characteristics . . . . . . . . . . . . . . . . . . . . . . 270
5.3.30 FSMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279
5.3.31 OCTOSPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 298
5.3.32 SD/SDIO/MMC card host interfaces (SDMMC) . . . . . . . . . . . . . . . . . . 304
5.3.33 UCPD characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 307
6
Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
LQFP48 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308
UFQFPN48 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .311
LQFP64 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314
WLCSP81 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 317
LQFP100 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 320
UFBGA132 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 323
LQFP144 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 326
Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 330
6.8.1
6.8.2
Reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 331
Selecting the product temperature range . . . . . . . . . . . . . . . . . . . . . . 331
7
8
Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 334
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 335
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List of tables
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Device summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
STM32L552xx features and peripheral counts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Boot modes when TrustZone is disabled (TZEN=0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Boot modes when TrustZone is enabled (TZEN=1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Boot space versus RDP protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Example of memory map security attribution vs SAU configuration regions . . . . . . . . . . . 27
Securable peripherals by TZSC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
TrustZone-aware peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
SMPS external components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
STM32L552xx modes overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Functionalities depending on the working mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
STM32L552xx peripherals interconnect matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
DMA1 and DMA2 implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Temperature sensor calibration values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Internal voltage reference calibration values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Timer feature comparison. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
I2C implementation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
USART/UART/LPUART features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
SAI implementation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Legend/abbreviations used in the pinout table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
STM32L552xx pin definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Alternate function AF0 to AF7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
Alternate function AF8 to AF15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
SMPS modes summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
SMPS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
Embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . 148
Embedded internal voltage reference. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
Current consumption in Run and Low-power run modes, code with data processing
running from Flash in single Bank, ICACHE ON in 2-way . . . . . . . . . . . . . . . . . . . . . . . . 153
Current consumption in Run and Low-power run modes, code with data processing
running from Flash in single Bank, ICACHE ON in 1-way . . . . . . . . . . . . . . . . . . . . . . . . 154
Current consumption in Run and Low-power run modes, code with data processing
running from Flash in single Bank, ICACHE disabled. . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
Current consumption in Run mode, code with data processing
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
Table 26.
Table 27.
Table 28.
Table 29.
Table 30.
Table 31.
Table 32.
Table 33.
Table 34.
Table 35.
Table 36.
running from Flash in single bank, ICACHE ON in 2-way and power
supplied by internal SMPS step down converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
Current consumption in Run mode, code with data processing
running from Flash in single bank, ICACHE ON in 1-way and power
supplied by internal SMPS step down converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
Current consumption in Run mode, code with data processing
running from Flash in single bank, ICACHE disabled and power
Table 37.
Table 38.
Table 39.
supplied by internal SMPS step down converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
Current consumption in Run and Low-power run modes, code with data processing
DS12737 Rev 6
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List of tables
STM32L552xx
running from Flash in dual bank, ICACHE ON in 2-way . . . . . . . . . . . . . . . . . . . . . . . . . . 159
Current consumption in Run and Low-power run modes, code with data processing
running from Flash in dual bank, ICACHE ON in 1-way . . . . . . . . . . . . . . . . . . . . . . . . . . 160
Current consumption in Run and Low-power run modes, code with data processing
running from Flash in dual bank, ICACHE disabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
Current consumption in Run mode, code with data processing
Table 40.
Table 41.
Table 42.
running from Flash in dual bank, ICACHE ON in 2-way and power
supplied by internal SMPS step down converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
Current consumption in Run mode, code with data processing
running from Flash in dual bank, ICACHE ON in 1-way and power
supplied by internal SMPS step down converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
Current consumption in Run mode, code with data processing
Table 43.
Table 44.
running from Flash in dual bank, ICACHE disabled and power
supplied by internal SMPS step down converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
Current consumption in Run and Low-power run modes,
code with data processing running from SRAM1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
Current consumption in Run mode, code with data processing running
from SRAM1 and power supplied by internal SMPS step down converter. . . . . . . . . . . . 166
Current consumption in Run and Low-power run modes, code with data processing
running from SRAM2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
Current consumption in Run mode, code with data processing
running from SRAM2 and power supplied by internal SMPS step down converter . . . . . 168
Typical current consumption in Run and Low-power run modes,
with different codes running from Flash, ICACHE ON (2-way). . . . . . . . . . . . . . . . . . . . . 169
Typical current consumption in Run mode with SMPS,
with different codes running from Flash, ICACHE ON (2-way). . . . . . . . . . . . . . . . . . . . . 170
Typical current consumption in Run and Low-power run modes,
with different codes running from Flash, ICACHE ON (1-way). . . . . . . . . . . . . . . . . . . . . 171
Typical current consumption in Run mode with SMPS,
with different codes running from Flash, ICACHE ON (1-way). . . . . . . . . . . . . . . . . . . . . 172
Typical current consumption in Run and Low-power run modes,
with different codes running from Flash, ICACHE disabled . . . . . . . . . . . . . . . . . . . . . . . 173
Typical current consumption in Run mode with internal SMPS,
with different codes running from Flash, ICACHE disabled . . . . . . . . . . . . . . . . . . . . . . . 174
Typical current consumption in Run and Low-power run modes,
with different codes running from SRAM1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
Typical current consumption in Run mode with internal SMPS,
with different codes running from SRAM1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
Typical current consumption in Run and Low-power run modes,
Table 45.
Table 46.
Table 47.
Table 48.
Table 49.
Table 50.
Table 51.
Table 52.
Table 53.
Table 54.
Table 55.
Table 56.
Table 57.
Table 58.
with different codes running from SRAM2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
Typical current consumption in Run mode with internal SMPS,
with different codes running from SRAM2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
Current consumption in Sleep and Low-power sleep mode, Flash ON . . . . . . . . . . . . . . 179
Current consumption in Low-power sleep mode, Flash in power-down . . . . . . . . . . . . . . 180
Current consumption in Sleep mode,
Table 59.
Table 60.
Table 61.
Flash ON and power supplied by internal SMPS step down converter . . . . . . . . . . . . . . 181
Current consumption in Run mode, code with data processing running from Flash
in single bank, ICACHE ON in 2-way and power supplied by external SMPS . . . . . . . . . 182
Current consumption in Run mode, code with data processing running from Flash
in single bank, ICACHE ON in 1-way and power supplied by external SMPS . . . . . . . . . 183
Current consumption in Run mode, code with data processing running from Flash
in single bank, ICACHE disabled and power supplied by external SMPS . . . . . . . . . . . . 184
Table 62.
Table 63.
Table 64.
8/340
DS12737 Rev 6
STM32L552xx
List of tables
Table 65.
Table 66.
Table 67.
Table 68.
Table 69.
Current consumption in Run mode, code with data processing running from Flash
in dual bank, ICACHE on in 2-way and power supplied by external SMPS . . . . . . . . . . . 185
Current consumption in Run mode, code with data processing running from Flash
in dual bank, ICACHE on in 1-way and power supplied by external SMPS . . . . . . . . . . . 186
Current consumption in Run mode, code with data processing running from Flash
in dual bank, ICACHE disabled and power supplied by external SMPS. . . . . . . . . . . . . . 187
Current consumption in Run mode, code with data processing running from SRAM1,
and power supplied by external SMPS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
Current consumption in Run mode, code with data processing running from SRAM2,
and power supplied by external SMPS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
Current consumption in Sleep mode, Flash ON and power supplied by external SMPS . 190
Current consumption in Run mode, code with data processing running from Flash,
ICACHE on (2-way) and power supplied by external SMPS . . . . . . . . . . . . . . . . . . . . . . 191
Current consumption in Run mode, code with data processing running from Flash,
ICACHE on (1-way) and power supplied by external SMPS . . . . . . . . . . . . . . . . . . . . . . 192
Current consumption in Run mode, code with data processing running from Flash,
ICACHE disabled and power supplied by external SMPS . . . . . . . . . . . . . . . . . . . . . . . . 193
Current consumption in Run mode, code with data processing running from SRAM1,
and power supplied by external SMPS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
Current consumption in Run mode, code with data processing running from SRAM2,
and power supplied by external SMPS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
Current consumption in Stop 2 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
Current consumption in Stop 1 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198
Current consumption in Stop 0 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
Current consumption in Standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
Current consumption in Shutdown mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
Current consumption in VBAT mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205
Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
Low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
Regulator modes transition times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212
Wakeup time using USART/LPUART. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212
High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213
Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214
HSE oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
Table 70.
Table 71.
Table 72.
Table 73.
Table 74.
Table 75.
Table 76.
Table 77.
Table 78.
Table 79.
Table 80.
Table 81.
Table 82.
Table 83.
Table 84.
Table 85.
Table 86.
Table 87.
Table 88.
Table 89.
Table 90.
Table 91.
Table 92.
Table 93.
Table 94.
Table 95.
Table 96.
Table 97.
Table 98.
Table 99.
LSE oscillator characteristics (f
= 32.768 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217
LSE
HSI16 oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218
MSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .220
HSI48 oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223
LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224
PLL, PLLSAI1, PLLSAI2 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225
Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226
Flash memory endurance and data retention. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226
EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227
EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228
ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228
Table 100. Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229
Table 101. I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229
Table 102. I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230
Table 103. Output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233
Table 104. I/O AC characteristics (All I/Os except FT_c) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234
Table 105. FT_c I/O AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236
Table 106. NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237
DS12737 Rev 6
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List of tables
STM32L552xx
Table 107. EXTI input characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237
Table 108. Analog switches booster characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238
Table 109. ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239
Table 110. Maximum ADC RAIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241
Table 111. ADC accuracy - limited test conditions 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243
Table 112. ADC accuracy - limited test conditions 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245
Table 113. ADC accuracy - limited test conditions 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247
Table 114. ADC accuracy - limited test conditions 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249
Table 115. DAC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252
Table 116. DAC accuracy ranges 0/1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255
Table 117. VREFBUF characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257
Table 118. COMP characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260
Table 119. OPAMP characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261
Table 120. TS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265
Table 121. V
Table 122. V
monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265
charging characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265
BAT
BAT
Table 123. Temp and VDD monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266
Table 124. DFSDM measured timing 1.71 to 3.6 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267
Table 125. TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269
Table 126. IWDG min/max timeout period at 32 kHz (LSI). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269
Table 127. WWDG min/max timeout value at 110 MHz (PCLK). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269
Table 128. I2C analog filter characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270
Table 129. SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271
Table 130. SAI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275
Table 131. USART characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277
Table 132. Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings . . . . . . . . . . . . . . . . . 281
Table 133. Asynchronous non-multiplexed SRAM/PSRAM/NOR read-NWAIT timings . . . . . . . . . . . 281
Table 134. Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings . . . . . . . . . . . . . . . . . 282
Table 135. Asynchronous non-multiplexed SRAM/PSRAM/NOR write-NWAIT timings. . . . . . . . . . . 283
Table 136. Asynchronous multiplexed PSRAM/NOR read timings. . . . . . . . . . . . . . . . . . . . . . . . . . . 284
Table 137. Asynchronous multiplexed PSRAM/NOR read-NWAIT timings . . . . . . . . . . . . . . . . . . . . 284
Table 138. Asynchronous multiplexed PSRAM/NOR write timings . . . . . . . . . . . . . . . . . . . . . . . . . . 286
Table 139. Asynchronous multiplexed PSRAM/NOR write-NWAIT timings . . . . . . . . . . . . . . . . . . . . 286
Table 140. Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 288
Table 141. Synchronous multiplexed PSRAM write timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290
Table 142. Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . 292
Table 143. Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294
Table 144. Switching characteristics for NAND Flash read cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . 296
Table 145. Switching characteristics for NAND Flash write cycles. . . . . . . . . . . . . . . . . . . . . . . . . . . 297
Table 146. OCTOSPI characteristics in SDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 298
Table 147. OCTOSPI characteristics in DTR mode (no DQS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299
Table 148. OCTOSPI characteristics in DTR mode (with DQS)/Octal and HyperBus . . . . . . . . . . . . 300
Table 149. Dynamics characteristics: delay block characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 304
Table 150. Dynamics characteristics: SD / eMMC characteristics,
VDD=2.7V to 3.6 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 304
Table 151. Dynamics characteristics: eMMC characteristics VDD=1.71 V to 1.9 V. . . . . . . . . . . . . . 305
Table 152. UCPD characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 307
Table 153. LQFP48 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308
Table 154. UFQFPN48 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 311
Table 155. LQFP64 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314
Table 156. WLCSP81 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 317
Table 157. WLCSP81 recommended PCB design rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 319
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Table 158. LQPF100 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 320
Table 159. UFBGA132 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 323
Table 160. UFBGA132 recommended PCB design rules (0.5 mm pitch BGA) . . . . . . . . . . . . . . . . . 324
Table 161. LQFP144 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 327
Table 162. Package thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 330
Table 163. STM32L552xx ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 334
Table 164. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 335
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11
List of figures
STM32L552xx
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
STM32L552xx block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
STM32L552xx power supply overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
STM32L552xxxxP power supply overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
STM32L552xxxxQ power supply overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Power-up/down sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
SMPS step down converter power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
STM32L552xx clock tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Multi-AHB bus matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Voltage reference buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Figure 10. STM32L552xx LQFP48 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Figure 11. STM32L552xxxxP LQFP48 external SMPS pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Figure 12. STM32L552xx UFQFPN48 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Figure 13. STM32L552xxxxP UFQFPN48 external SMPS pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Figure 14. STM32L552xx LQFP64 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Figure 15. STM32L552xxxxQ LQFP64 SMPS step down converter pinout. . . . . . . . . . . . . . . . . . . . . 81
Figure 16. STM32L552xxxxP LQFP64 external SMPS pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Figure 17. STM32L552xxxxQ WLCSP81 SMPS step down converter ballout . . . . . . . . . . . . . . . . . . 82
Figure 18. STM32L552xxxxP WLCSP81 external SMPS ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Figure 19. STM32L552xx LQFP100 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Figure 20. STM32L552xxxxQ LQFP100 SMPS step down converter pinout. . . . . . . . . . . . . . . . . . . . 84
Figure 21. STM32L552xx UFBGA132 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Figure 22. STM32L552xxxxQ UFBGA132 SMPS step down converter ballout. . . . . . . . . . . . . . . . . . 85
Figure 23. STM32L552xx LQFP144 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Figure 24. STM32L552xxxxQ LQFP144 SMPS step down converter pinout. . . . . . . . . . . . . . . . . . . . 87
Figure 25. Pin loading conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
Figure 26. Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
Figure 27. STM32L552xx and STM32L562xx power supply overview . . . . . . . . . . . . . . . . . . . . . . . 139
Figure 28. STM32L552xxxP and STM32L562xxxP power supply overview . . . . . . . . . . . . . . . . . . . 140
Figure 29. STM32L552xxxQ and STM32L562xxxQ power supply overview. . . . . . . . . . . . . . . . . . . 141
Figure 30. Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
Figure 31. External components for SMPS step down converter . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
Figure 32. VREFINT versus temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
Figure 33. High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 213
Figure 34. Low-speed external clock source AC timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . 214
Figure 35. Typical application with an 8 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216
Figure 36. Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217
Figure 37. HSI16 frequency versus temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219
Figure 38. Typical current consumption versus MSI frequency. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222
Figure 39. HSI48 frequency versus temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224
Figure 40. I/O input characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232
(1)
Figure 41. I/O AC characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236
Figure 42. Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237
Figure 43. ADC accuracy characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251
Figure 44. Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251
Figure 45. 12-bit buffered / non-buffered DAC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254
Figure 46. VREFBUF in case VRS = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258
Figure 47. VREFBUF in case VRS = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259
Figure 48. SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273
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Figure 49. SPI timing diagram - slave mode and CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273
Figure 50. SPI timing diagram - master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274
Figure 51. SAI master timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276
Figure 52. SAI slave timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277
Figure 53. USART master mode timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278
Figure 54. USART slave mode timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279
Figure 55. Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms . . . . . . . . . . . . . . 280
Figure 56. Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms . . . . . . . . . . . . . . 282
Figure 57. Asynchronous multiplexed PSRAM/NOR read waveforms. . . . . . . . . . . . . . . . . . . . . . . . 283
Figure 58. Asynchronous multiplexed PSRAM/NOR write waveforms . . . . . . . . . . . . . . . . . . . . . . . 285
Figure 59. Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 287
Figure 60. Synchronous multiplexed PSRAM write timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289
Figure 61. Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . 291
Figure 62. Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293
Figure 63. NAND controller waveforms for read access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295
Figure 64. NAND controller waveforms for write access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295
Figure 65. NAND controller waveforms for common memory read access . . . . . . . . . . . . . . . . . . . . 296
Figure 66. NAND controller waveforms for common memory write access. . . . . . . . . . . . . . . . . . . . 296
Figure 67. OCTOSPI timing diagram - SDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302
Figure 68. OCTOSPI timing diagram - DDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302
Figure 69. OCTOSPI HyperBus clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302
Figure 70. OCTOSPI HyperBus read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303
Figure 71. OCTOSPI HyperBus read with double latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303
Figure 72. OCTOSPI HyperBus write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303
Figure 73. SDIO high-speed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306
Figure 74. SD default mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306
Figure 75. DDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306
Figure 76. LQFP48 outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308
Figure 77. LQFP48 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 309
Figure 78. Example of LQFP48 package marking (package top view) . . . . . . . . . . . . . . . . . . . . . . . 310
Figure 79. UFQFPN48 outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 311
Figure 80. UFQFPN48 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 312
Figure 81. Example of UFQFPN48 package marking (package top view). . . . . . . . . . . . . . . . . . . . . 313
Figure 82. LQFP64 outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314
Figure 83. LQFP64 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 315
Figure 84. Example of LQFP64 package marking (package top view) . . . . . . . . . . . . . . . . . . . . . . . 316
Figure 85. WLCSP81 outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 317
Figure 86. WLCSP 81 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 318
Figure 87. Example of WLCSP81 package marking (package top view). . . . . . . . . . . . . . . . . . . . . . 319
Figure 88. LQFP100 outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 320
Figure 89. LQFP100 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 321
Figure 90. Example of LQFP100 package marking (package top view) . . . . . . . . . . . . . . . . . . . . . . 322
Figure 91. UFBGA132 outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 323
Figure 92. UFBGA132 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 324
Figure 93. Example of UFBGA132 package marking (package top view) . . . . . . . . . . . . . . . . . . . . 325
Figure 94. LQFP144 outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 326
Figure 95. LQFP144 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 328
Figure 96. Example of LQFP144 package marking (package top view) . . . . . . . . . . . . . . . . . . . . . . 329
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13
Introduction
STM32L552xx
1
Introduction
This document provides the ordering information and mechanical device characteristics of
the STM32L552xx microcontrollers.
This document should be read in conjunction with the STM32L552xx and STM32L562xx
reference manual (RM0438).
®(a)
®
®
For information on the Arm
Cortex -M33 core, refer to the Cortex -M33 Technical
Reference Manual, available from the www.arm.com website.
a. Arm is a registered trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere.
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2
Description
The STM32L552xx devices are an ultra-low-power microcontrollers family (STM32L5
®
®
Series) based on the high-performance Arm Cortex -M33 32-bit RISC core. They operate
at a frequency of up to 110 MHz.
®
The Cortex -M33 core features a single-precision floating-point unit (FPU), which supports
®
all the Arm single-precision data-processing instructions and all the data types. The
®
Cortex -M33 core also implements a full set of DSP (digital signal processing) instructions
and a memory protection unit (MPU) which enhances the application’s security.
These devices embed high-speed memories (512 Kbytes of Flash memory and 256 Kbytes
of SRAM), a flexible external memory controller (FSMC) for static memories (for devices
with packages of 100 pins and more), an Octo-SPI Flash memories interface (available on
all packages) and an extensive range of enhanced I/Os and peripherals connected to two
APB buses, two AHB buses and a 32-bit multi-AHB bus matrix.
The STM32L5 Series devices offer security foundation compliant with the trusted based
security architecture (TBSA) requirements from Arm. They embed the necessary security
features to implement a secure boot, secure data storage, secure firmware installation and
secure firmware upgrade. Flexible life cycle is managed thanks to multiple levels of readout
protection. Firmware hardware isolation is supported thanks to securable peripherals,
memories and I/Os, and also to the possibility to configure the peripherals and memories as
“privilege”.
The STM32L552xx devices embed several protection mechanisms for embedded Flash
memory and SRAM: readout protection, write protection, secure and hidden protection
areas.
The STM32L552xx devices embed peripherals reinforcing security:
- One HASH hardware accelerator
- One true random number generator
The STM32L5 Series devices offer active tamper detection and protection against transient
and environmental perturbation attacks thanks to several internal monitoring which generate
secret data erase in case of attack. This helps to fit the PCI requirements for point of sales
applications. These devices offer two fast 12-bit ADC (5 Msps), two comparators, two
operational amplifiers, two DAC channels, an internal voltage reference buffer, a low-power
RTC, two general-purpose 32-bit timer, two 16-bit PWM timers dedicated to motor control,
seven general-purpose 16-bit timers, and two 16-bit low-power timers. The devices support
four digital filters for external sigma delta modulators (DFSDM). In addition, up to 22
capacitive sensing channels are available.
STM32L5 Series also feature standard and advanced communication interfaces such as:
- Four I2Cs
- Three SPIs
- Three USARTs, two UARTs and one low-power UART
- Two SAIs
- One SDMMC
- One FDCAN
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Description
STM32L552xx
- USB device FS
- USB Type-C / USB power delivery controller
The devices operate in the -40 to +85 °C (+105 °C junction) and -40 to +125 °C (+130 °C
junction) temperature ranges from a 1.71 to 3.6 V power supply. A comprehensive set of
power-saving modes allows the design of low-power applications.
Some independent power supplies are supported like an analog independent supply input
for ADC, DAC, OPAMPs and comparators, a 3.3 V dedicated supply input for USB and up to
14 I/Os, which can be supplied independently down to 1.08 V. A VBAT input allows the
backup of the RTC and the backup of the registers.
The STM32L552xx devices offer seven packages from 48-pin to 144-pin.
Table 2. STM32L552xx features and peripheral counts
Peripherals
Flash memory (Kbyte)
512/256
256 (192+64)
128
System (Kbyte)
Backup (byte)
SRAM
External memory controller for static
memories (FSMC)
No
Yes
OCTOSPI
1
Advanced control
2 (16-bit)
5 (16-bit)
2 (32-bit)
General purpose
Basic
2 (16-bit)
3 (16-bit)
1
Timers
Low power
SysTick timer
Watchdog timers
(independent,
window)
2
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Table 2. STM32L552xx features and peripheral counts (continued)
Peripherals
SPI
3
4
I2C
USART(1)/UART
UART
3/2 (2)
2
1
Communication
interfaces
LPUART
SAI
2
1
FDCAN
USB FS
SDMMC
Yes
No
Yes/No/Yes
Yes
Digital filters for sigma-
delta modulators
Yes (4 filters)
Number of channels
Real time clock (RTC)
Tamper pins
8
Yes
3
4/4/3
3
5/4
5
8/7
True random number generator
HASH (SHA-256)
Yes
Yes
GPIOs
38/36
52/50/47
4/3/3
0
54/51
83/79
5/4
0
115 /111
5/4
108/105
5
Wakeup pins
3
0
3
6
13/10
Nb of I/Os down to 1.08 V
14/13
Capacitive sensing
Number of channels
5
10/10/9
10
19/18
22
22/21
16/14
12-bit ADC
2
ADC
Number of
9
16/16/15
16/15
16/14
16
channels
12-bit DAC
1
2
DAC
Number of
channels
Internal voltage
reference buffer
Yes
Analog comparator
Operational amplifiers
Max. CPU frequency
2
2
110 MHz
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78
Description
STM32L552xx
Table 2. STM32L552xx features and peripheral counts (continued)
Peripherals
Operating voltage
1.71 to 3.6 V
Ambient operating temperature: -40 to 85 °C / -40 to 125 °C
Junction temperature: -40 to 105 °C / -40 to 130 °C
Operating temperature
LQFP48,
UFQFPN48
Package
LQFP64
WLCSP81 LQFP100(2) UFBGA132 LQFP144
1. USART3 is not available on STM32L552CExxP devices.
2. For the LQFP100 package, only FSMC Bank1 is available. Bank1 can only support a multiplexed NOR/PSRAM memory
using the NE1 Chip Select.
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Figure 1. STM32L552xx block diagram
CLK, NE[4:1], NL, NBL[1:0],
A[25:0], D[15:0], NOE, NWE,
NWAIT, NCE, INT as AF
Flexible static memory controller (FSMC):
SRAM, PSRAM, NOR Flash,FRAM, NAND Flash
NJTRST, JTDI,
JTCK/SWCLK
JTDO/SWD, JTDO
JTAG & SW
MPU
NVIC
IO[7:0],
CLK, NCLK, NCS. DQS
ETM
Octo SPI1 memory interface
TRACECLK
TRACED[3:0]
Arm Cortex-M33
110 MHz
TrustZone
FPU
RNG
C-BUS
Flash
up to
512KB
HASH
S-BUS
@ VDDUSB
SRAM 192 KB
SRAM 64 KB
DP
USB FS
DM
D[7:0], D[3:1]dir
CMD, CMDdir,CK, CKin
D0dir, D2dir
SDMMC1
Power management
VDD
AHB2 110 MHz
Voltage Regulator
LDO and SMPS
3.3 to 1.2 V
DMA2
VDD = 1.71 to 3.6 V
VSS
DMA1
@ VDD
@ VDD
Supply
supervision
reset
Int
MSI
DMAMUX1
VDDIO, VDDUSB
VDDA, VSSA
VDD, VSS, NRST
RC HSI
RC LSI
BOR
8 groups of sensing channels as AF
Touch sensing controller
PVD, PVM
@VDD
PLL 1&2&3
GTZC
OSC_IN
OSC_OUT
XTAL OSC
4- 16MHz
GPIO PORT A
GPIO PORT B
GPIO PORT C
GPIO PORT D
GPIO PORT E
GPIO PORT F
GPIO PORT G
GPIO PORT H
PA[15:0]
PB[15:0]
PC[15:0]
PD[15:0]
PE[15:0]
PF[15:0]
PG[15:0]
PH[1:0]
IWDG
Standby
interface
@VBAT
Reset & clock
control
OSC32_IN
XTAL 32 kHz
RTC
AWU
Backup register
OSC32_OUT
RTC_TS
RTC_TAMP[8:1]
RTC_OUT
VBAT = 1.55 to 3.6 V
4 channels, ETR as AF
TIM2
32b
114 AF
EXT. IT WKUP
TIM3
4 channels, ETR as AF
4 channels, ETR as AF
4 channels, ETR as AF
16b
CRC
TIM4
@ VDD
16b
Temperature sensor
TIM5
32b
@ VDDA
16xIN
smcard
irDA
ADC1
ADC2
USART2
RX, TX, CK, CTS, RTS as AF
RX, TX, CK, CTS, RTS as AF
ITF
smcard
irDA
USART3
UART4
RX, TX, CTS, RTS as AF
RX, TX, CTS, RTS as AF
AHB/APB1
AHB/APB2
3 compl. channels (TIM1_CH[1:3]N),
4 channels (TIM1_CH[1:4]),
ETR, BKIN, BKIN2 as AF
UART5
SPI2
16b
TIM1 / PWM
TIM8 / PWM
MOSI, MISO, SCK, NSS as AF
3 compl. Channels (TIM1_CH[1:3]N),
4 channels (TIM1_CH[1:4]),
ETR, BKIN, BKIN2 as AF
16b
SPI3
MOSI, MISO, SCK, NSS as AF
SCL, SDA, SMBA as AF
SCL, SDA, SMBA as AF
SCL, SDA, SMBA as AF
SCL, SDA, SMBA as AF
I2C1/SMBUS
I2C2/SMBUS
I2C3/SMBUS
I2C4/SMBUS
2 channels,
16b
16b
16b
TIM15
TIM16
1 compl. channel, BKIN as AF
WWDG
1 channel,
1 compl. channel, BKIN as AF
CRS
1 channel,
1 compl. channel, BKIN as AF
TIM17
RX, TX, CK,CTS,
RTS as AF
MOSI, MISO,
SCK, NSS as AF
smcard
irDA
USART1
SPI1
FDCAN1
TX, RX as AF
MCLK_A, SD_A, FS_A, SCK_A, EXTCLK
MCLK_B, SD_B, FS_B, SCK_B as AF
MCLK_A, SD_A, FS_A, SCK_A, EXTCLK
MCLK_B, SD_B, FS_B, SCK_B as AF
TIM6
TIM7
16b
16b
SAI1
SAI2
@VDDA
OUT, INN, INP
OUT, INN, INP
OpAmp1
OpAmp2
SDCKIN[7:0], SDDATIN[7:0],
SDCKOUT,SDTRIG as AF
DFSDM
SYSCFG
@ VDDUSB
DP
DM
UCPD1
@ VDDA
VREF Buffer
VREF+
LPUART1
@ VDDA
@ VDDA
LPTIM1
LPTIM2
LPTIM3
IN1, IN2, OUT, ETR as AF
RX, TX, CTS, RTS as AF
CH1
CH2
INP, INN, OUT
INP, INN, OUT
COMP1
COMP2
DAC1
IN1, OUT, ETR as AF
IN1, OUT, ETR as AF
OUT1
OUT2
32-bits AHB bus
32-bits APB bus
VBAT power domain
VDDIO2 power domain
VDDA power domain
VDDUSB power domain
VDD power domain
MSv49361V6
1. AF: alternate function on I/O pins.
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3
Functional overview
3.1
Arm® Cortex®-M33 core with TrustZone® and FPU
®
The Cortex -M33 with TrustZone and FPU is a highly energy efficient processor designed
for microcontrollers and deeply embedded applications, especially those requiring efficient
security.
®
The Cortex -M33 processor delivers a high computational performance with low-power
consumption and an advanced response to interrupts. it features:
®
®
•
Arm TrustZone technology, using the Armv8-M main extension supporting secure
and non-secure states
•
•
•
Memory protection units (MPUs), 8 regions for secure and 8 regions for non secure
Configurable secure attribute unit (SAU) supporting up to 8 memory regions
Floating-point arithmetic functionality with support for single precision arithmetic
The processor supports a set of DSP instructions that allows an efficient signal processing
and a complex algorithm execution.
®
The Cortex -M33 processor supports the following bus interfaces:
•
System AHB bus:
The System AHB (S-AHB) bus interface is used for any instruction fetch and data
access to the memory-mapped SRAM, peripheral, external RAM and external device,
or Vendor_SYS regions of the Armv8-M memory map.
•
Code AHB bus
The Code AHB (C-AHB) bus interface is used for any instruction fetch and data access
to the code region of the Armv8-M memory map.
Figure 1 shows the general block diagram of the STM32L552xx family devices.
3.2
Art Accelerator – instruction cache (ICACHE)
®
The instruction cache (ICACHE) is introduced on C-AHB code bus of Cortex -M33
processor to improve performance when fetching instruction (or data) from both internal and
external memories.
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ICACHE offers the following features:
•
Multi-bus interface:
®
–
slave port receiving the memory requests from the Cortex -M33 C-AHB code
execution port
–
–
master1 port performing refill requests to internal memories (FLASH and SRAMs)
master2 port performing refill requests to external memories (external
FLASH/RAMs through Octo-SPI/FMC interfaces)
–
a second slave port dedicated to ICACHE registers access.
•
Close to zero wait states instructions/data access performance:
–
–
0 wait-state on cache hit
hit-under-miss capability, allowing to serve new processor requests while a line
refill (due to a previous cache miss) is still ongoing
–
–
critical-word-first refill policy, minimizing processor stalls on cache miss
hit ratio improved by 2-ways set-associative architecture and pLRU-t replacement
policy (pseudo-least-recently-used, based on binary tree), algorithm with best
complexity/performance balance
–
dual master ports allowing to decouple internal and external memory traffics, on
Fast and Slow buses, respectively; also minimizing impact on interrupt latency
–
–
optimal cache line refill thanks to AHB burst transactions (of the cache line size).
performance monitoring by means of a hit counter and a miss counter.
•
•
Extension of cacheable region beyond Code memory space, by means of address
remapping logic that allows to define up to 4 cacheable external regions
Power consumption reduced intrinsically (most accesses to cache memory rather to
bigger main memories); even improved by configuring ICACHE as direct mapped
(rather than the default 2-ways set-associative mode)
®
•
•
•
TrustZone security support
Maintenance operation for software management of cache coherency
Error management: detection of unexpected cacheable write access, with optional
interrupt raising.
3.3
Memory protection unit
The memory protection unit (MPU) is used to manage the CPU accesses to the memory
and to prevent one task to accidentally corrupt the memory or the resources used by any
other active task. This memory area is organized into up to 8 regions for secure and 8
regions for non secure state.
The MPU is especially helpful for applications where some critical or certified code has to be
protected against the misbehavior of other tasks. It is usually managed by an RTOS (real-
time operating system). If a program accesses a memory location that is prohibited by the
MPU, the RTOS can detect it and take action. In an RTOS environment, the kernel can
dynamically update the MPU area setting based on the process to be executed.
The MPU is optional and can be bypassed for applications that do not need it.
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3.4
Embedded Flash memory
The devices feature 512 Kbytes of embedded Flash memory which is available for storing
programs and data.
The Flash interface features:
•
•
Single or dual bank operating modes
Read-while-write (RWW) in dual bank mode
This feature allows a read operation to be performed from one bank while an erase or
program operation is performed to the other bank. The dual bank boot is also supported.
Each bank contains 128 pages of 2 or 4 Kbytes (depending on the read access width). The
Flash memory also embeds 512 bytes OTP (one-time programmable) for user data.
Flexible protections can be configured thanks to the option bytes:
• Readout protection (RDP) to protect the whole memory. Four levels of protection are
available:
– Level 0: no readout protection
– Level 0.5: available only when TrustZone is enabled
All read/write operations (if no write protection is set) from/to the non-secure Flash
memory are possible. The Debug access to secure area is prohibited. Debug access
to non-secure area remains possible.
– Level 1: memory readout protection; the Flash memory cannot be read from or written
to if either the debug features are connected or the boot in RAM or bootloader are
selected. If TrustZone is enabled, the non-secure debug is possible and the boot in
SRAM is not possible.
®
– Level 2: chip readout protection; the debug features (Cortex -M33 JTAG and serial
wire), the boot in RAM and the bootloader selection are disabled (JTAG fuse). This
selection is irreversible.
•
Write protection (WRP): the protected area is protected against erasing and
programming:
–
–
In single bank mode, four areas can be selected with 4-Kbyte granularity.
In dual bank mode, two areas per bank can be selected with 2-Kbyte granularity.
The whole non-volatile memory embeds the error correction code (ECC) feature supporting:
•
•
•
Single error detection and correction
Double error detection
The address of the ECC fail can be read in the ECC register.
TrustZone security
When the TrustZone security is enabled, the whole Flash is secure after reset and the
following protections are available:
•
Non-volatile watermark-based secure Flash area: the secure area can be accessed
only in secure mode.
–
–
In single bank mode, four areas can be selected with a page granularity.
In dual bank mode, one area per bank can be selected with a page granularity.
•
Secure hidden protection area: it is part of the Flash secure area and it can be
protected to deny an access to this area by any data read, write and instruction fetch.
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Functional overview
For example, a software code in the secure Flash memory hidden protection area can
be executed only once and deny any further access to this area until next system reset.
•
Volatile block-based secure Flash area. In a block-based secure area, each page can
be programmed on-the-fly as secure or non-secure.
3.5
Embedded SRAM
The devices feature 256 Kbytes of embedded SRAM. This SRAM is split into three blocks:
•
•
192 Kbytes mapped at address 0x2000 0000 (SRAM1).
64 Kbytes located at address 0x0A03 0000 with hardware parity check (SRAM2).
This memory is also mapped at address 0x2003 0000 offering a contiguous address
space with the SRAM1.
This block is accessed through the C-bus for maximum performance. Either 64 Kbytes
or upper 4 Kbytes of SRAM2 can be retained in Standby mode.
The SRAM2 can be write-protected with 1 Kbyte granularity.
The memory can be accessed in read/write at CPU clock speed with 0 wait states.
TrustZone security
When the TrustZone security is enabled, all SRAMs are secure after reset. The SRAM can
be programmed as non-secure by block based using the MPCBB (memory protection
controller block based) in GTZC controller. The granularity of SRAM secure block based is a
page of 256 bytes.
3.6
Boot modes
At startup, a BOOT0 pin, nBOOT0 and NSBOOTADDx[24:0] / SECBOOTADD0[24:0] option
bytes are used to select the boot memory address which includes:
•
•
•
•
Boot from any address in user Flash
Boot from system memory bootloader
Boot from any address in embedded SRAM
Boot from Root Security service (RSS)
The BOOT0 value may come from the PH3-BOOT0 pin or from an option bit depending on
the value of a user option bit to free the GPIO pad if needed.
The boot loader is located in the system memory. It is used to reprogram the Flash memory
by using USART, I2C, SPI, FDCAN or USB FS in device mode through the DFU (device
firmware upgrade).
The bootloader is available on all devices. Refer to the application note STM32
microcontroller system memory boot mode (AN2606) for more details.
The root secure services (RSS) are embedded in a Flash memory area named secure
information block, programmed during ST production.
The RSS enables for example the secure firmware installation (SFI) thanks to the RSS
extension firmware (RSSe SFI).
This feature allows the customers to protect the confidentiality of the firmware to be
provisioned into the STM32 device when the production is subcontracted to a third party.
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The RSS is available on all devices, after enabling the TrustZone through the TZEN option
bit.
Refer to the application note Overview secure firmware install (SFI) (AN4992) for more
details.
Refer to Table 3 and Table 4 for boot modes when TrustZone is disabled and enabled
respectively.
Table 3. Boot modes when TrustZone is disabled (TZEN=0)
nSWBOOT0
nBOOT0
BOOT0
pin PH3
Boot address option-
bytes selection
ST programmed
default value
Boot area
FLASH_
OPTR[27]
FLASH_
OPTR[26]
Boot address defined by
-
-
0
1
-
1
1
0
0
NSBOOTADD0[24:0] user option bytes
NSBOOTADD0[24:0]
Flash: 0x0800 0000
Boot address defined by
NSBOOTADD1[24:0] user option bytes
NSBOOTADD1[24:0]
System bootloader:
0x0BF9 0000
Boot address defined by
NSBOOTADD0[24:0] user option bytes
NSBOOTADD0[24:0]
1
0
Flash: 0x0800 0000
Boot address defined by
NSBOOTADD1[24:0] user option bytes
NSBOOTADD1[24:0]
System bootloader:
0x0BF9 0000
-
When TrustZone is enabled by setting the TZEN option bit, the boot space must be in
secure area. The SECBOOTADD0[24:0] option bytes are used to select the boot secure
memory address.
A unique boot entry option can be selected by setting the BOOT_LOCK option bit, allowing
to boot always at the address selected by SECBOOTADD0[24:0] option bytes. All other boot
options are ignored.
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Table 4. Boot modes when TrustZone is enabled (TZEN=1)
nSWBOOT0
nBOOT0 BOOT0
Boot address
option-bytes
selection
ST
BOOT_
LOCK
RSS
command
FLASH_
pin
Boot area
programmed
default value
FLASH_
OPTR[26]
OPTR[27]
PH3
Secure boot address
defined by user option
bytes
SECBOOTAD
D0[24:0]
Flash:
0x0C00 0000
-
-
0
1
-
1
1
0
0
0
0
SECBOOTADD0[24:0]
RSS: 0x0FF8 0000
Secure boot address
RSS:
0x0FF8 0000
N/A
0
SECBOOTAD defined by user option Flash:
1
D0[24:0]
bytes
0x0C00 0000
SECBOOTADD0[24:0]
RSS: RSS:
0x0FF8 0000
RSS:
0x0FF8 0000
0
-
-
-
0
-
0
N/A
N/A
RSS: RSS:
0x0FF8 0000
RSS:
0x0FF8 0000
≠ 0
Secure boot address
SECBOOTAD defined by user option Flash:
1
-
-
-
-
D0[24:0]
bytes
0x0C00 0000
SECBOOTADD0[24:0]
The boot address option bytes enables the possibility to program any boot memory address.
However, the allowed address space depends on Flash read protection RDP level.
If the programmed boot memory address is out of the allowed memory mapped area when
RDP level is 0.5 or more, the default boot fetch address is forced to:
•
•
0x0800 0000 (when TZEN = 0)
RSS (when TZEN = 1)
Refer to Table 5.
Table 5. Boot space versus RDP protection
TZEN = 1 TZEN = 0
Any boot address Any boot address
RDP
0
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RDP
STM32L552xx
Table 5. Boot space versus RDP protection (continued)
TZEN = 1 TZEN = 0
0.5
1
N/A
Any boot address
If boot is configured for NSBOOTADD0 and
NSBOOTADD0 in the range 0x0800 0000 -
0x0807 FFFF: boot at the address stored in
NSBOOTADD0
Boot address only in:
– RSS
– or secure Flash: 0x0C00 0000 -
0x0C07 FFFF
If boot is configured for NSBOOTADD1 and
NSBOOTADD1 in the range 0x0800 0000 -
0x0807 FFFF: boot at the address stored in
NSBOOTADD1
2
Otherwise boot address forced to RSS
Otherwise boot address is forced at
0x0800 0000
3.7
Global TrustZone controller (GTZC)
The GTZC includes three different sub-blocks:
®
•
TZSC: TrustZone security controller
This sub-block defines the secure/privilege state of slave/master peripherals. It also
controls the non-secure area size for the watermark memory peripheral controller
(MPCWM). The TZSC block informs some peripherals (such as RCC or GPIOs) about
the secure status of each securable peripheral, by sharing with RCC and I/O logic.
1. MPCBB: block-based memory protection controller
This sub-block controls secure states of all blocks (256-byte pages) of the associated
SRAM.
2. TZIC: TrustZone illegal access controller
This sub-block gathers all illegal access events in the system and generates a secure
interrupt towards NVIC.
These sub-blocks are used to configure TrustZone and privileged attributes within the full
system.
The GTZC main features are:
•
•
•
•
3 independent 32-bit AHB interface for TZSC, MPCBB and TZIC
MPCBB and TZIC accessible only with secure transactions
Secure and non-secure access supported for priv/non-priv part of TZSC
Register set to define security settings:
–
–
–
Secure blocks for internal SRAM
Non-secure regions for external memories
Secure/privilege access mode for securable and TZ-aware peripherals
•
Secure/privilege access mode for securable legacy masters.
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Functional overview
3.8
TrustZone security architecture
®
®
The security architecture is based on Arm TrustZone with the Armv8-M Main Extension.
The TrustZone security is activated by the TZEN option bit in the FLASH_OPTR register.
When the TrustZone is enabled, the SAU (security attribution unit) and IDAU
(implementation defined attribution unit) defines the access permissions based on secure
and non-secure state.
•
•
SAU: Up to 8 SAU configurable regions are available for security attribution.
IDAU: It provides a first memory partition as non-secure or non-secure callable
attributes. It is then combined with the results from the SAU security attribution and the
higher security state is selected.
Based on IDAU security attribution, the Flash, system SRAMs and peripherals memory
space is aliased twice for secure and non-secure state. However, the external memories
space is not aliased.
Table 6 shows an example of typical SAU regions configuration based on IDAU regions.
The user can split and choose the secure, non-secure or NSC regions for external
memories as needed.
(1) (2)
Table 6. Example of memory map security attribution vs SAU configuration regions
SAU security
attribution typical
configuration
Region
description
IDAU security
attribution
Final security
attribution
Address range
0x0000_0000
0x07FF_FFFF
Code - external
memories
Secure or non-
secure or NSC
Secure or non-
secure or NSC
Non-secure
Non-secure
NSC
0x0800_0000
0x0BFF_FFFF
Non-secure
Non-secure
Code - Flash and
SRAM
0x0C00_0000
0x0FFF_FFFF
Secure or NSC
Secure or NSC
0x1000_0000
0x17FF_FFFF
Code - external
memories
Non-secure
0x1800_0000
0x1FFF_FFFF
Non-secure
0x2000_0000
0x2FFF_FFFF
Non-secure
NSC
SRAM
0x3000_0000
0x3FFF_FFFF
Secure or NSC
Non-secure
Secure or NSC
Non-secure
0x4000_0000
0x4FFF_FFFF
Non-secure
NSC
Peripherals
0x5000_0000
0x5FFF_FFFF
Secure or NSC
Secure or NSC
0x6000_0000
0xDFFF_FFFF
Secure or non-
secure or NSC
Secure or non-
secure or NSC
External memories
Non-secure
1. NSC = non-secure callable.
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2. Different colors highlights the different configurations
Pink: Non-secure
Green: NSC (non-secure callable)
Lighter green: Secure or non-secure or NSC
3.8.1
TrustZone peripheral classification
When the TrustZone security is active, a peripheral can be either Securable or TrustZone-
aware type as follows:
•
Securable: a peripheral is protected by an AHB/APB firewall gate that is controlled from
TZSC controller to define security properties.
•
TrustZone-aware: a peripheral connected directly to AHB or APB bus and is
implementing a specific TrustZone behavior such as a subset of registers being secure.
The tables below summarize the list of Securable and TrustZone aware peripherals within
the system.
Table 7. Securable peripherals by TZSC
Bus
Peripheral
OCTOSPI1 registers
FMC registers
SDMMC1
RNG
AHB3
AHB 2
AHB1
ADC
ICACHE registers
TSC
CRC
DFSDM1
SAI2
SAI1
TIM17
TIM16
TIM15
APB2
USART1
TIM8
SPI1
TIM1
COMP
VREFBUF
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Table 7. Securable peripherals by TZSC (continued)
Peripheral
Bus
UCPD1
USB FS
FDCAN1
LPTIM3
LPTIM2
I2C4
LPUART1
LPTIM1
OPAMP
DAC1
CRS
I2C3
I2C2
I2C1
APB1
UART5
UART4
USART3
USART2
SPI3
SPI2
IWDG
WWDG
TIM7
TIM6
TIM5
TIM4
TIM3
TIM2
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Table 8. TrustZone-aware peripherals
Peripheral
Bus
GPIOH
GPIOG
GPIOF
GPIOE
GPIOD
GPIOC
GPIOB
GPIOA
MPCBB2
MPCBB1
MPCWM2
MPCWM1
TZIC
AHB2
TZSC
AHB1
EXTI
Flash memory
RCC
DMAMUX1
DMA2
DMA1
APB2
APB1
SYSCFG
PWR
RTC
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Functional overview
Default TrustZone security state
The default system security state is:
•
•
•
CPU:
®
–
Cortex -M33 is in secure state after reset. The boot address must be in secure
address.
Memory map:
SAU: is fully secure after reset. Consequently, all memory map is fully secure. Up
to 8 SAU configurable regions are available for security attribution.
Flash:
–
–
–
Flash security area is defined by watermark user options.
Flash block based area is non-secure after reset.
•
•
•
SRAMs:
All SRAMs are secure after reset. MPCBB (memory protection block based
controller) is secure.
External memories:
–
–
FSMC, OCTOSPI banks are secure after reset. MPCWMx (memory protection
watermark based controller) are secure
Peripherals
–
–
Securable peripherals are non-secure after reset.
TrustZone-aware peripherals (except the GPIO) are non-secure after reset. Their
secure configuration registers are secure.
Note:
Refer to Table 7 and Table 8 for a list of Securable and TrustZone-aware peripherals.
•
•
All GPIO are secure after reset.
Interrupts:
–
NVIC: All interrupts are secure after reset. NVIC is banked for secure and non-
secure state.
–
TZIC: All illegal access interrupts are disabled after reset.
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3.9
Power supply management
The power controller (PWR) main features are:
•
Power supplies and supply domains
–
–
–
–
–
–
Core domains (VCORE)
VDD domain
Backup domain (VBAT)
Analog domain (VDDA)
VDDIO2 domain
VDDUSB for USB transceiver
•
•
System supply voltage regulation
–
–
SMPS step down converter
Voltage regulator (LDO)
Power supply supervision
–
–
–
–
–
–
POR/PDR monitor
BOR monitor
PVD monitor
PVM monitor (VDDA, VDDUSB, VDDIO2)
Temperature thresholds monitor
Upper VDD voltage threshold monitor
•
Power management
–
–
–
Operating modes
Voltage scaling control
Low-power modes
•
•
VBAT battery charging
TrustZone security
3.9.1
Power supply schemes
The devices require a 1.71 V to 3.6 V V operating voltage supply. Several independent
DD
supplies can be provided for specific peripherals:
•
V
V
= 1.71 V to 3.6 V
DD
is the external power supply for the I/Os, the internal regulator and the system
DD
analog such as reset, power management and internal clocks. It is provided externally
through the VDD pins.
•
V
V
= 1.62 V (ADCs/COMPs) / 1.8 V (DACs/OPAMPs) to 2.4 V (VREFBUF) to 3.6 V
is the external analog power supply for A/D converters, D/A converters, voltage
DDA
DDA
reference buffer, operational amplifiers and comparators. The V
voltage level is
DDA
independent from the V voltage and should preferably be connected to V when
DD
DD
these peripherals are not used.
32/340
DS12737 Rev 6
STM32L552xx
Functional overview
•
VDDSMPS = 1.71 V to 3.6 V
VDDSMPS is the external power supply for the SMPS step down converter. It is
provided externally through VDDSMPS supply pin, and shall be connected to the same
supply as VDD.
•
•
VLXSMPS is the switched SMPS step down converter output.
V15SMPS are the power supply for the system regulator. It is provided externally
through the SMPS step down converter VLXSMPS output.
Note:
The SMPS power supply pins are available only on a specific package with SMPS step
down converter option.
•
VDD12 = 1.05 to 1.32 V
VDD12 is the external power supply bypassing the internal regulator when connected
to an external SMPS. It is provided externally through VDD12 pins and only available
on packages with the external SMPS supply option. VDD12 does not require any
external decoupling capacitance and cannot support any external load.
•
VDDUSB = 3.0 V to 3.6 V
VDDUSB is the external independent power supply for USB transceivers. The
VDDUSB voltage level is independent from the VDD voltage and should preferably be
connected to VDD when the USB is not used.
•
•
VDDIO2 = 1.08 V to 3.6 V
VDDIO2 is the external power supply for 14 I/Os (port G[15:2]). The VDDIO2 voltage
level is independent from the VDD voltage and should preferably be connected to VDD
when PG[15:2] are not used.
•
•
V
= 1.55 V to 3.6 V
BAT
V
is the power supply for RTC, external clock 32 kHz oscillator and backup registers
BAT
(through power switch) when V is not present.
DD
VREF-, VREF+
V
is the input reference voltage for ADCs and DACs. It is also the output of the
REF+
internal voltage reference buffer when enabled.
When V
When V
< 2 V V
must be equal to V
.
DDA
DDA
DDA
REF+
REF+
≥ 2 V V
must be between 2 V and V
.
DDA
V
can be grounded when ADC and DAC are not active.
REF+
The internal voltage reference buffer supports two output voltages, which are
configured with VRS bit in the VREFBUF_CSR register:
–
–
V
V
around 2.048 V. This requires V
equal to or higher than 2.4 V.
REF+
REF+
DDA
around 2.5 V. This requires V
equal to or higher than 2.8 V.
DDA
VREF- and VREF+ pins are not available on all packages. When not available, they are
bonded to VSSA and VDDA, respectively.
When the VREF+ is double-bonded with VDDA in a package, the internal voltage
reference buffer is not available and must be kept disabled (refer to datasheet for
packages pinout description).
V
must always be equal to V
.
REF-
SSA
An embedded linear voltage-regulator is used to supply the internal digital power V
.
CORE
V
is the power supply for digital peripherals, SRAM1 and SRAM2. The Flash is
CORE
supplied by V
and V
.
CORE
DD
DS12737 Rev 6
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78
Functional overview
STM32L552xx
Figure 2. STM32L552xx power supply overview
VDDA domain
2 x A/D converters
VDDA
2 x comparators
2 x D/A converters
2 x operational amplifiers
VSSA
Voltage reference buffer
VDDUSB
USB transceivers
VSS
VDDIO2 domain
VDDIO2
VDDIO2
I/O ring
V
SS
PG[15:2]
VDD domain
VDDIO1
I/O ring
VCORE domain
Reset block
Temp. sensor
Core
3 x PLL, HSI, MSI
SRAM1
SRAM2
Standby circuitry
(Wakeup logic,
IWDG)
VSS
VDD
Digital
peripherals
VCORE
Voltage regulator
Flash memory
Low voltage detector
Backup domain
LSE crystal 32 K osc
BKP registers
RCC BDCR register
RTC
VBAT
MSv49301V1
34/340
DS12737 Rev 6
STM32L552xx
Functional overview
Figure 3. STM32L552xxxxP power supply overview
VDDA domain
2 x A/D converters
VDDA
VSSA
2 x comparators
2 x D/A converters
2 x operational amplifiers
Voltage reference buffer
VDDUSB
VSS
USB transceivers
VDDIO2 domain
VDDIO2
VDDIO2
VSS
I/O ring
PG[15:2]
VDD domain
VDDIO1
I/O ring
VCORE domain
Reset block
Temp. sensor
3 x PLL, HSI, MSI
Core
SRAM1
SRAM2
Standby circuitry
(Wakeup logic,
IWDG)
VSS
VDD
Digital
VCORE
peripherals
Voltage regulator
2x VDD12
Flash memory
Low voltage detector
Backup domain
LSE crystal 32 K osc
BKP registers
RCC BDCR register
RTC
VBAT
MSv49336V1
DS12737 Rev 6
35/340
78
Functional overview
STM32L552xx
Figure 4. STM32L552xxxxQ power supply overview
VDDA domain
2 x A/D converters
VDDA
2 x comparators
2 x D/A converters
2 x operational amplifiers
VSSA
Voltage reference buffer
VDDUSB
USB transceivers
VSS
VDDIO2 domain
VDDIO2
VDDIO2
VSS
I/O ring
VDD domain
VDDIO1
I/O ring
Reset block
Temp. sensor
3 x PLL, HSI, MSI
VCORE domain
Standby circuitry
(Wakeup logic,
IWDG)
VSS
Core
VDD
SRAM1
SRAM2
Voltage regulator
MR
2 x V15SMPS
VCORE
VLXSMPS
Digital
peripherals
VDDSMPS
SMPS
LPR
VSSSMPS
Flash memory
Low voltage detector
Backup domain
LSE crystal 32 K osc
BKP registers
RCC BDCR register
RTC
VBAT
MSv49332V1
During power-up and power-down phases, the following power sequence requirements
must be respected:
•
When V is below 1 V, other power supplies (V
below VDD +300 mV.
, V
and V
) must remain
DDUSB
DD
DDA DDIO2
•
•
When V is above 1 V, all power supplies are independent.
DD
During the power-down phase, V can temporarily become lower than other supplies
DD
only if the energy provided to the MCU remains below 1 mJ; this allows external
decoupling capacitors to be discharged with different time constants during the power-
down transient phase.
36/340
DS12737 Rev 6
STM32L552xx
Functional overview
Figure 5. Power-up/down sequence
V
3.6
(1)
VDDX
VDD
VBOR0
1
0.3
Power-on
Invalid supply area
Operating mode
Power-down
VDDX independent from VDD
time
VDDX < VDD + 300 mV
MSv47490V1
1. VDDX refers to any power supply among VDDA, VDDIO2 and VDDUSB.
3.9.2
Power supply supervisor
The devices have an integrated ultra-low-power Brownout reset (BOR) active in all modes
(except for Shutdown mode). The BOR ensures proper operation of the devices after power-
on and during power down. The devices remain in reset mode when the monitored supply
voltage V is below a specified threshold, without the need for an external reset circuit.
DD
The lowest BOR level is 1.71 V at power on, and other higher thresholds can be selected
through option bytes.The devices feature an embedded programmable voltage detector
(PVD) that monitors the V power supply and compares it to the VPVD threshold.
DD
An interrupt can be generated when V drops below the VPVD threshold and/or when V
DD
DD
is higher than the VPVD threshold. The interrupt service routine can then generate a
warning message and/or put the MCU into a safe state. The PVD is enabled by software.
In addition, the devices embed a peripheral voltage monitor which compares the
independent supply voltages V
, V
, V
with a fixed threshold in order to ensure
DDA DDUSB DDIO2
that the peripheral is in its functional supply range.
3.9.3
Voltage regulator
Two embedded linear voltage regulators supply most of the digital circuitries: the main
regulator (MR) and the low-power regulator (LPR).
•
•
The MR is used in the Run and Sleep modes and in the Stop 0 mode.
The LPR is used in Low-power run, Low-power sleep, Stop 1 and Stop 2 modes. It is
also used to supply the 64 Kbytes or only 4 Kbytes of SRAM2 in standby with SRAM2
retention.
•
Both regulators are in power-down while they are in standby and Shutdown modes: the
regulator output is in high impedance, and the kernel circuitry is powered down thus
inducing zero consumption.
DS12737 Rev 6
37/340
78
Functional overview
STM32L552xx
The ultra-low-power STM32L552xx devices support dynamic voltage scaling to optimize its
power consumption in Run mode. The voltage from the main regulator that supplies the
logic (VCORE) can be adjusted according to the system’s maximum operating frequency.
The main regulator operates in the following ranges:
•
•
•
Range 0 with the CPU running at up to 110 MHz.
Range 1 with the CPU running at up to 80 MHz.
Range 2 with a maximum CPU frequency of 26 MHz. All peripheral clocks are also
limited to 26 MHz.
The VCORE can be supplied by the low-power regulator, the main regulator being switched
off. The system is then in Low-power run mode.
•
Low-power run mode with the CPU running at up to 2 MHz. Peripherals with
independent clock can be clocked by the HSI16.
3.9.4
SMPS step down converter
The built-in SMPS step down converter is a highly power-efficient DC/DC non-linear
switching regulator that improves low-power performance when the VDD voltage is high
enough. This SMPS step down converter automatically enters in bypass mode when the
VDD voltage falls below 2 V in Range 0 and Range 1.
Note:
There is no automatic SMPS bypass in Range 2.
The SMPS step down converter can be configured in:
•
High-power mode (HPM): achieving a high efficiency at high current load. It is the
default selected mode after POR reset.
•
•
Low power mode achieving very high efficiency at low load
Bypass mode
The SMPS step down converter can be switched in bypass mode at any time by the
application software.
Note:
The SMPS step down converter is available only on specific package.
SMPS step down converter power supply scheme
The SMPS step down converter requires an external coil with typical value of 4.7 μH to be
connected between the VLXSMPS and the V15SMPS pins and a 4.7μF capacitor to be
connected between the V15SMPS to VSSSMPS pins. It can be switched OFF by selecting
the Bypass mode by software. Thus, only main regulator is used by the application.
38/340
DS12737 Rev 6
STM32L552xx
Functional overview
Figure 6. SMPS step down converter power supply scheme
VDDSMPS
VLXSMPS
VDD
SMPS
Step Down
Converter
V15SMPS
V15SMPS
VCORE
Main
regulator
VDD
VSS
VSSSMPS
MSv49346V1
If the selected package is with the SMPS step down converter option but it is never used by
the application, it is recommend to set the SMPS power supply pins as follows:
•
•
V
V
and V
connected to VSS
DDSMPS
15SMPS
LXSMPS
connected to VDD
Table 9. SMPS external components
Description
Component
Value
C
L
SMPS output capacitor(1)
SMPS inductance(2)
4.7 µF
4.7 µH
1. For example GRM155R60J475ME87J and GRM21BR71E475KA73L.
2. For example TDK MLP2016H4R7MT.
SMPS step down converter fast startup
After POR reset, the SMPS step down converter starts in High-power mode and in Low
startup mode. The low-startup feature is selected to limit the inrush current after power-on
reset.
However, it is possible to configure a faster startup on the fly and it is applied for next startup
either after a system reset or wakeup from low-power mode except Shutdown and VBAT
modes. The fast startup is selected by setting the SMPSFSTEN bit in the PWR_CR4
register.
DS12737 Rev 6
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78
3.9.5
Low-power modes
The ultra-low-power STM32L552xx devices support seven low-power modes to achieve the best compromise between low-power
consumption, short startup time, available peripherals and available wake-up sources. Table 11 shows the related STM32L552xx
modes overview.
Table 10. STM32L552xx modes overview
Regulator and SMPS
Mode
CPU
Yes
Yes
No
Flash
ON(3)
ON(3)
ON(3)
ON(3)
SRAM
Clocks
DMA and Peripherals(2)
Wakeup source
N/A
mode(1)
Ranges 0/1
All
SMPS HP mode
Run
LPRun
Sleep
ON
Any
Range 2
All except USB_FS, RNG
All except USB_FS, RNG
All
SMPS LP or HP mode
Any
LPR
ON
N/A
except PLL
Ranges 0/1
SMPS HP mode
ON(4)
ON(4)
Any
Any interrupt or event
Any interrupt or event
Range 2
All except USB_FS, RNG
All except USB_FS, RNG
SMPS LP or HP mode
Any
LPSleep
LPR
No
except PLL
BOR, PVD, PVM
RTC, IWDG
Reset pin, all I/Os
BOR, PVD, PVM
RTC, IWDG
COMPx (x=1,2)
DAC1
OPAMPx (x=1,2)
USARTx (x=1...5)(6)
LPUART1(6)
I2Cx (x=1...4)(7)
LPTIMx (x=1,2)
***
COMPx (x=1..2)
USARTx (x=1...5)(6)
LPUART1(6)
I2Cx (x=1...4)(7)
LPTIMx (x=1,2)
USB_FS(8)
LSE
LSI
Stop 0(5)
Ranges 0/1/2
No
Off
ON
All other peripherals are frozen
Table 10. STM32L552xx modes overview (continued)
Regulator and SMPS
mode(1)
Mode
CPU
Flash
SRAM
Clocks
DMA and Peripherals(2)
Wakeup source
BOR, PVD, PVM
RTC, IWDG
Reset pin, all I/Os
BOR, PVD, PVM
RTC, IWDG
COMPx (x=1,2)
DAC1
OPAMPx (x=1,2)
USARTx (x=1...5)(6)
LPUART1(6)
I2Cx (x=1...4)(7)
LPTIMx (x=1,2)
***
COMPx (x=1..2)
USARTx (x=1...5)(6)
LPUART1(6)
I2Cx (x=1...4)(7)
LPTIMx (x=1,2)
USB_FS(8)
LSE
LSI
Stop 1
LPR
No
Off
ON
All other peripherals are frozen
BOR, PVD, PVM
RTC, IWDG
Reset pin, all I/Os
BOR, PVD, PVM
RTC, IWDG
COMPx (x=1..2)
I2C3(7)
LPUART1(6)
LSE
LSI
Stop 2
LPR
No
Off
ON
COMPx (x=1..2)
I2C3(7)
LPUART1(6)
LPTIMx (x= 1,3)
***
LPTIMx (x= 1,3)
All other peripherals are frozen
Table 10. STM32L552xx modes overview (continued)
Regulator and SMPS
mode(1)
Mode
CPU
Flash
SRAM
Clocks
DMA and Peripherals(2)
Wakeup source
LPR
SRAM2 ON
BOR, RTC, IWDG
***
Reset pin
5 I/Os (WKUPx)(9)
All other peripherals are powered
off
LSE
LSI
Powered
Off
Standby
Off
Powered
Off
OFF
***
BOR, RTC, IWDG
I/O configuration can be floating,
pull-up or pull-down
RTC
***
Reset pin
5 I/Os (WKUPx)(9)
RTC
All other peripherals are powered
off
Powered
Off
Powered
Off
Shutdown
OFF
Off
LSE
***
I/O configuration can be floating,
pull-up or pull-down(10)
1. LPR means Main regulator is OFF and Low-power regulator is ON.
2. All peripherals can be active or clock gated to save power consumption.
3. The Flash memory can be put in power-down and its clock can be gated off when executing from SRAM.
4. The SRAM1 and SRAM2 clocks can be gated on or off independently.
5. SMPS mode can be used in Stop 0 mode, but no significant power gain can be expected.
6. U(S)ART and LPUART reception is functional in Stop mode, and generates a wakeup interrupt on Start, address match or received frame event.
7. I2C address detection is functional in Stop mode, and generates a wakeup interrupt in case of address match.
8. USB_FS wakeup by resume from suspend and attach detection protocol event.
9. The I/Os with wakeup from Standby/Shutdown capability are: PA0, PC13, PE6, PA2, PC5.
10. I/Os can be configured with internal pull-up, pull-down or floating in Shutdown mode but the configuration is lost when exiting the Shutdown mode.
STM32L552xx
Functional overview
By default, the microcontroller is in Run mode after a system or a power reset. It is up to the
user to select one of the low-power modes described below:
•
Sleep mode
In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can
wake up the CPU when an interrupt/event occurs.
•
Low-power run mode
This mode is achieved with VCORE supplied by the low-power regulator to minimize
the regulator's operating current. The code can be executed from SRAM or from Flash,
and the CPU frequency is limited to 2 MHz. The peripherals with independent clock can
be clocked by HSI16.
•
•
Low-power sleep mode
This mode is entered from the Low-power run mode. Only the CPU clock is stopped.
When wakeup is triggered by an event or an interrupt, the system reverts to the Low-
power run mode.
Stop 0, Stop 1 and Stop 2 modes
Stop mode achieves the lowest power consumption while retaining the content of
SRAM and registers. All clocks in the VCORE domain are stopped, the PLL, the MSI
RC, the HSI16 RC and the HSE crystal oscillators are disabled. The LSE or LSI is still
running.
The RTC can remain active (Stop mode with RTC, Stop mode without RTC).
Some peripherals with wake-up capability can enable the HSI16 RC during Stop mode
to detect their wake-up condition.
Three Stop modes are available: Stop 0, Stop 1 and Stop 2 modes. In Stop 2 mode,
most of the VCORE domain is put in a lower leakage mode.
Stop 1 offers the largest number of active peripherals and wakeup sources, a smaller
wakeup time but a higher consumption than Stop 2. In Stop 0 mode, the main regulator
remains ON, allowing a very fast wakeup time but with much higher consumption.
The system clock when exiting from Stop 0, Stop 1 or Stop 2 modes can be either MSI
up to 48 MHz or HSI16, depending on software configuration.
•
Standby mode
The Standby mode is used to achieve the lowest power consumption with BOR. The
internal regulator is switched off so that the VCORE domain is powered off. The PLL,
the MSI RC, the HSI16 RC and the HSE crystal oscillators are also switched off.
The RTC can remain active (Standby mode with RTC, Standby mode without RTC).
The Brownout reset (BOR) always remains active in Standby mode.
The state of each I/O during Standby mode can be selected by software: I/O with
internal pull-up, internal pull-down or floating.
After entering Standby mode, SRAM1 and register contents are lost except for registers
in the Backup domain and Standby circuitry. Optionally, the full SRAM2 or 4 Kbytes can
be retained in Standby mode, supplied by the low-power regulator (standby with RAM2
retention mode).
DS12737 Rev 6
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78
Functional overview
STM32L552xx
The BORL (brown out detector low) can be configured in ultra-low-power mode to
further reduce power consumption during standby mode.
The device exits Standby mode when an external reset (NRST pin), an IWDG reset,
WKUP pin event (configurable rising or falling edge), or an RTC event occurs (alarm,
periodic wakeup, timestamp, tamper) or a failure is detected on LSE (CSS on LSE).
The system clock after wakeup is MSI up to 8 MHz.
•
Shutdown mode
The Shutdown mode allows to achieve the lowest power consumption. The internal
regulator is switched off so that the VCORE domain is powered off. The PLL, the
HSI16, the MSI, the LSI and the HSE oscillators are also switched off.
The RTC can remain active (Shutdown mode with RTC, Shutdown mode without RTC).
The BOR is not available in Shutdown mode. No power voltage monitoring is possible
in this mode, therefore the switch to Backup domain is not supported.
SRAM1, SRAM2 and register contents are lost except for registers in the Backup
domain.
The device exits Shutdown mode when an external reset (NRST pin), a WKUP pin
event (configurable rising or falling edge), or an RTC event occurs (alarm, periodic
wakeup, timestamp, tamper).
The system clock after wakeup is MSI at 4 MHz.
44/340
DS12737 Rev 6
STM32L552xx
Functional overview
(1)
Table 11. Functionalities depending on the working mode
Stop 0/1 Stop 2 Standby Shutdown
Low-
Low-
Peripheral
Run
Sleep power power
VBAT
-
-
-
-
run
sleep
CPU
Y
-
Y
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Flash memory
(512 Kbyte)
O(2)
O(2)
O(2)
O(2)
SRAM1
(192 Kbytes)
Y
Y(3)
Y
Y(3)
Y
-
Y
-
-
-
-
-
-
SRAM2 (64 Kbytes)
FSMC
Y
O
O
Y
Y(3)
O
Y
O
O
Y
Y(3)
O
Y
-
-
-
-
-
Y
-
-
-
-
-
O(4)
-
-
-
-
-
-
-
-
-
-
-
-
-
-
OCTOSPI
O
O
-
-
-
-
Backup registers
Y
Y
Y
Y
Y
Y
Y
Brownout reset
(BOR)
Y
Y
Y
Y
Y
Y
Y
Y
Y
-
Y
-
-
-
-
-
-
-
Programmable
voltage detector
(PVD)
O
O
O
O
O
O
O
O
Peripheral voltage
monitor (PVMx;
x=1,2,3,4)
O
O
O
O
O
O
O
O
-
-
-
-
-
DMA
O
O
O
O
O
O
O
O
O
O
-
O
O
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
High speed internal
(HSI16)
(5)
(5)
-
Oscillator HSI48
-
-
High speed external
(HSE)
O
O
-
Low speed internal
(LSI)
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
-
-
-
O
O
-
-
-
O
O
-
-
-
-
O
-
-
-
-
-
-
-
O
-
Low speed external
(LSE)
Multi speed internal
(MSI)
-
-
-
Clock security
system (CSS)
-
-
-
-
-
-
-
-
Clock security
system on LSE
O
O
O
O
O
O
-
-
DS12737 Rev 6
45/340
78
Functional overview
STM32L552xx
(1)
Table 11. Functionalities depending on the working mode (continued)
Stop 0/1 Stop 2 Standby Shutdown
Low-
Low-
Peripheral
Run
Sleep power power
VBAT
-
-
-
-
run
sleep
VDD voltage
monitoring,
temperature
monitoring
O
O
O
O
O
O
O
O
O
O
-
-
-
RTC / TAMP
O
8
O
8
O
8
O
8
O
8
-
O
O
O
O
8
-
O
O
-
O
8
-
O
O
-
O
8
-
O
O
-
O
3
-
Number of RTC
Tamper pins
USB, UCPD
O(8)
O
O(8)
O
-
-
USARTx
(x=1,2,3,4,5)
O
O
O(6) O(6)
-
-
-
-
-
-
-
Low-power UART
(LPUART)
O
O
O
O
O(6) O(6) O(6) O(6)
O(7) O(7)
O(7) O(7) O(7) O(7)
-
-
-
-
-
I2Cx (x=1,2,4)
I2C3
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
SPIx (x=1,2,3)
FDCAN1
-
-
-
-
-
-
-
-
SDMMC1
-
-
-
-
SAIx (x=1,2)
DFSDM1
-
-
-
-
-
-
-
-
ADCx (x=1,2)
DAC1
-
-
-
-
O
O
O
O
-
-
-
-
VREFBUF
-
-
-
OPAMPx (x=1,2)
COMPx (x=1,2)
Temperature sensor
Timers (TIMx)
-
-
-
O
-
O
-
O
-
-
-
-
-
Low-power timer 1,
3 (LPTIM1 and
LPTIM3)
O
O
O
O
O
O
O
O
-
-
-
-
-
Low-power timer 2
(LPTIM2)
O
O
O
O
O
O
O
O
O
O
O
O
-
-
-
-
-
-
-
-
-
-
Independent
watchdog (IWDG)
O
O
O
O
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Functional overview
(1)
Table 11. Functionalities depending on the working mode (continued)
Stop 0/1 Stop 2 Standby Shutdown
Low-
Low-
Peripheral
Run
Sleep power power
VBAT
-
-
-
-
run
sleep
Window watchdog
(WWDG)
O
O
O
O
O
O
O
O
O
O
O
O
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
SysTick timer
Touch sensing
controller (TSC)
Random number
generator (RNG)
O(8)
O
O(8)
O
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
CRC calculation
unit
O
O
-
-
5
5
(9)
(11)
GPIOs
O
O
O
O
O
O
O
O
pins
pins
-
(10)
(10)
1. Legend: Y = yes (enable). O = optional (disable by default, can be enabled by software). - = not available.
Gray cells highlight the wakeup capability in each mode.
2. The Flash can be configured in Power-down mode. By default, it is not in Power-down mode.
3. The SRAM clock can be gated on or off.
4. 4 Kbytes or full SRAM2 content is preserved depending on RRS[1:0] bits configuration in PWR_CR3 register.
5. Some peripherals with wakeup from Stop capability can request HSI16 to be enabled. In this case, HSI16 is woken up by
the peripheral, and only feeds the peripheral which requested it. HSI16 is automatically put off when the peripheral does not
need it anymore.
6. UART and LPUART reception is functional in Stop mode, and generates a wakeup interrupt on Start, address match or
received frame event.
7. I2C address detection is functional in Stop mode, and generates a wakeup interrupt in case of address match.
8. Voltage scaling ranges 0 and 1 only.
9. I/Os can be configured with internal pull-up, pull-down or floating in Standby mode.
10. The I/Os with wakeup from standby/shutdown capability are: PA0, PC13, PE6, PA2, PC5.
11. I/Os can be configured with internal pull-up, pull-down or floating in Shutdown mode but the configuration is lost when
exiting the Shutdown mode.
3.9.6
3.9.7
Reset mode
In order to improve the consumption under reset, the I/Os state under and after reset is
“analog state” (the I/O schmitt trigger is disable). In addition, the internal reset pull-up is
deactivated when the reset source is internal.
VBAT operation
The VBAT pin allows the device VBAT domain to be powered from an external battery, an
external supercapacitor, or from V when there is no external battery and when an external
DD
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Functional overview
STM32L552xx
supercapacitor is present. The VBAT pin supplies the RTC with LSE and the backup
registers. Three anti-tamper detection pins are available in VBAT mode.
The VBAT operation is automatically activated when V is not present. An internal VBAT
DD
battery charging circuit is embedded and can be activated when V is present.
DD
Note:
When the microcontroller is supplied from VBAT, neither external interrupts nor RTC
alarm/events exit the microcontroller from the VBAT operation.
3.9.8
PWR TrustZone security
When the TrustZone security is activated by the TZEN option bit, the PWR is switched in
TrustZone security mode.
The PWR TrustZone security allows to secure the following configuration:
•
•
•
•
Low-power mode
Wake-up (WKUP) pins
Voltage detection and monitoring
VBAT mode
Other PWR configuration bits are secure when:
•
•
•
The system clock selection is secure in RCC, the voltage scaling (VOS) configuration is
secure
A GPIO is configured as secure, it's corresponding bit for Pull-up/Pull-down in standby
mode is secure
The RTC is secure, the backup domain write protection bit in PWR is secure.
3.10
Peripheral interconnect matrix
Several peripherals have direct connections between them, which allow autonomous
communication between them and support the saving of CPU resources (thus power supply
consumption). In addition, these hardware connections allow fast and predictable latency.
Depending on the peripherals, these interconnections can operate in Run, Sleep, Low-
power run and Sleep, Stop 0, Stop 1 and Stop 2 modes. See Table 12 for more details.
Table 12. STM32L552xx peripherals interconnect matrix
Interconnect
destination
Interconnect source
Interconnect action
TIMx
Timers synchronization or chaining
Conversion triggers
Y
Y
Y
Y
Y
Y
Y
Y
-
-
-
-
ADC
DAC1
TIMx
DFSDM1
DMA
Memory to memory transfer trigger
Comparator output blanking
Y
Y
Y
Y
Y
Y
Y
Y
-
-
-
-
COMPx
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Functional overview
Table 12. STM32L552xx peripherals interconnect matrix (continued)
Interconnect
destination
Interconnect source
Interconnect action
TIM1, 8
TIM2, 3
Timer input channel, trigger, break from
analog signals comparison
Y
Y
Y
Y
Y
Y
Y
Y
-
-
COMPx
Low-power timer triggered by analog
signals comparison
Y
LPTIMERx
Y
(1)
ADCx
RTC
TIM1, 8
TIM16
Timer triggered by analog watchdog
Timer input channel from RTC events
Y
Y
Y
Y
Y
Y
Y
Y
-
-
-
-
Low-power timer triggered by RTC alarms
or tampers
Y
LPTIMERx
Y
Y
Y
Y
Y
(1)
TIM2
All clocks sources (internal
and external)
Clock source used as input channel for
RC measurement and trimming
Y
Y
Y
Y
Y
-
Y
-
-
-
-
-
TIM15, 16, 17
USB
TIM2
Timer triggered by USB SOF
CSS
CPU (hard fault)
RAM (parity error)
Flash memory (ECC error)
COMPx
TIM1,8
Timer break
Y
Y
Y
Y
-
-
TIM15,16,17
PVD
DFSDM1 (analog
watchdog, short circuit
detection)
TIMx
External trigger
External trigger
Y
Y
Y
Y
Y
Y
Y
Y
-
-
Y
LPTIMERx
Y
(1)
GPIO
ADC
DAC1
Conversion external trigger
Y
Y
Y
Y
-
-
DFSDM1
1. LPTIM1 and LPTIM3 only.
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3.11
Reset and clock controller (RCC)
The clock controller (see Figure 7) distributes the clocks coming from the different
oscillators to the core and to the peripherals. It also manages the clock gating for low-power
modes and ensures the clock robustness. It features:
•
Clock prescaler: to get the best trade-off between speed and current consumption,
the clock frequency to the CPU and peripherals can be adjusted by a programmable
prescaler.
•
•
•
Clock security system: clock sources can be changed safely on the fly in Run mode
through a configuration register.
Clock management: to reduce the power consumption, the clock controller can stop
the clock to the core, individual peripherals or memory.
System clock source: four different clock sources can be used to drive the master
clock SYSCLK:
–
4 to 48 MHz high-speed external crystal or ceramic resonator (HSE), that can
supply a PLL. The HSE can also be configured in bypass mode for an external
clock.
–
–
16 MHz high-speed internal RC oscillator (HSI16), trimmable by software, that can
supply a PLL
Multispeed internal RC oscillator (MSI), trimmable by software, able to generate
12 frequencies from 100 kHz to 48 MHz. When a 32.768 kHz clock source is
available in the system (LSE), the MSI frequency can be automatically trimmed by
hardware to reach better than ±0.25% accuracy. In this mode the MSI can feed the
USB device, saving the need of an external high-speed crystal (HSE). The MSI
can supply a PLL.
–
System PLL which can be fed by HSE, HSI16 or MSI, with a maximum frequency
at 110 MHz.
•
RC48 with clock recovery system (HSI48): internal 48 MHz clock source (HSI48)can
be used to drive the USB, the SDMMC or the RNG peripherals. This clock can be
output on the MCO.
•
•
UCPD kernel clock: it is derived from HSI16 clock. The HSI16 RC oscillator must be
enabled prior to the UCPD kernel clock use.
Auxiliary clock source: two ultra-low-power clock sources that can be used to drive
the real-time clock:
–
–
32.768 kHz low-speed external crystal (LSE), supporting four drive capability
modes. The LSE can also be configured in bypass mode for an external clock.
32 kHz low-speed internal RC (LSI), also used to drive the independent watchdog.
The LSI clock accuracy is ±5% accuracy. The LSI clock can be divided by 128 to
output a 250 Hz as source clock.
•
Peripheral clock sources: several peripherals (USB, SDMMC, RNG, SAI, USARTs,
I2Cs, LPTimers, ADC) have their own independent clock whatever the system clock.
Three PLLs, each having three independent outputs allowing the highest flexibility, can
generate independent clocks for the ADC, the USB/SDMMC/RNG and the two SAIs.
•
•
Startup clock: after reset, the microcontroller restarts by default with an internal 4 MHz
clock (MSI). The prescaler ratio and clock source can be changed by the application
program as soon as the code execution starts.
Clock security system (CSS): this feature can be enabled by software. If a HSE clock
failure occurs, the master clock is automatically switched to HSI16 and a software
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Functional overview
interrupt is generated if enabled. LSE failure can also be detected and generated an
interrupt.
•
Clock-out capability:
–
MCO (microcontroller clock output): it outputs one of the internal clocks for
external use by the application
–
LSCO (low-speed clock output): it outputs LSI or LSE in all low-power modes
(except VBAT).
Several prescalers allow to configure the AHB frequency, the high speed APB (APB2) and
the low-speed APB (APB1) domains. The maximum frequency of the AHB and the APB
domains is 110 MHz.
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Figure 7. STM32L552xx clock tree
to IWDG
to RTC
LSI RC 32 kHz
LSCO
OSC32_OUT
LSE OSC
32.768 kHz
OSC32_IN
/32
to PWR
to AHB bus, core, memory and DMA
FCLK Cortex free running clock
to Cortex system timer
LSE
LSI
MSI
HSI16
HSE
SYSCLK
PLLCLK
HSI48
MCO
/ 1→16
HCLK
AHB PRESC
/ 1,2,..512
/ 8
Clock
source
control
PCLK1
to APB1 peripherals
APB1 PRESC
/ 1,2,4,8,16
OSC_OUT
OSC_IN
HSE OSC
4-48 MHz
HSE
x1 or x2
to TIMx
x=2..7
MSI
Clock
detector
SYSCLK
HSI16
LSE
HSI16
to USARTx
X=2..5
to LPUART1
SYSCLK
HSI RC
16 MHz
HSI16
MSI RC
to I2Cx
SYSCLK
100 kHz – 48 MHz
RC 48 MHz
x=1,2,3,4
LSI
LSE
to LPTIMx
x=1,2
HSI16
MSI
MSI
HSI16
HSE
PLL
/ M
OCTOSPI clock
CRS clock
PLLSAI3CLK
/ P
/ Q
/ R
PLL48M1CLK
PLLCLK
PCLK2
APB2 PRESC
/ 1,2,4,8,16
to APB2 peripherals
HSI16
MSI
x1 or x2
HSI16
HSE
/ M
to TIMx
PLLSAI1
x=1,8,15,16,17
PLLSAI1CLK
/ P
/ Q
/ R
PLL48M2CLK
PLLADC1CLK
LSE
HSI16
to
SYSCLK
USART1
SDMMC clock
48
MHz
MSI
HSI16
48 MHz clock to USB, RNG
SYSCLK
to ADC
HSI16
FDCAN
To UCPD1
MSI
HSI16
HSE
HSE
MSI
HSI16
/ M
PLLSAI2
PLLSAI2CLK
/ P
/ Q
/ R
DFSDM
audio clock
to SAI1
HSI16
SAI1_EXTCLK
SAI2_EXTCLK
to SAI2
MSv49302V2
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Functional overview
TrustZone security
When the TrustZone security is activated by the TZEN option bit, the RCC is switched in
TrustZone security mode.
The RCC TrustZone security allows to secure some RCC system configuration and
peripheral configuration clock from being read or modified by non-secure accesses:
•
RCC system security:
–
HSE, HSE-CSS, HSI, MSI, LSI, LSE, LSE-CSS, HSI48 configuration and status
bits
–
–
–
–
Main PLL, PLLSAI1, PLLSAI2, AHB prescaler configuration and status bits
System clock SYSCLK and HSI48 source clock selection and status bits
MCO clock output configuration and STOPWUCK bit
Reset flag RMVF configuration bit
•
•
RCC peripheral security:
–
When a peripheral is secure, the related peripheral clock, reset, clock source
selection and clock enable during low power modes control bits are secure.
A peripheral is in secure state when:
–
For securable peripherals, when it's corresponding SEC security bit is set in the
TZSC (TrustZone security controller)
–
For TrustZone-aware peripherals, a security feature of this peripheral is enabled
through its dedicated bits.
3.12
3.13
Clock recovery system (CRS)
The devices embed a special block which allows automatic trimming of the internal 48 MHz
oscillator to guarantee its optimal accuracy over the whole device operational range. This
automatic trimming is based on the external synchronization signal, which could be either
derived from USB SOF signalization, from LSE oscillator, from an external signal on
CRS_SYNC pin or generated by user software. For faster lock-in during startup it is also
possible to combine automatic trimming with manual trimming action.
General-purpose inputs/outputs (GPIOs)
Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as
input (with or without pull-up or pull-down) or as peripheral alternate function. Most of the
GPIO pins are shared with digital or analog alternate functions.
After reset, all GPIOs are in Analog mode to reduce power consumption.
The I/Os alternate function configuration can be locked if needed following a specific
sequence in order to avoid spurious writing to the I/Os registers.
GPIO TrustZone security
Each I/O pin of GPIO port can be individually configured as secure. When the selected I/O
pin is configured as secure, its corresponding configuration bits for alternate function, mode
selection, I/O data are secure against a non-secure access. The associated registers bit
access is restricted to a secure software only. After reset, all GPIO ports are secure.
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3.14
Multi-AHB bus matrix
The 32-bit multi-AHB bus matrix interconnects all the masters (CPU, DMAs, SDMMC1) and
the slaves (Flash memory, RAM, FMC, OCTOSPI, AHB and APB peripherals). It also
ensures a seamless and efficient operation even when several high-speed peripherals work
simultaneously.
Figure 8. Multi-AHB bus matrix
CORTEX®-M33
with TrustZone and FPU
Legend
DMA1 DMA2 SDMMC1
Master Interface
Bus multiplexer
Slave Interface
MPCBBx: Memory protection controller block based
MPCWMx: Memory protection controller Watermark
8 KB I-Cache
FLASH
512 KB
MPCBB1
MPCBB2
SRAM1
SRAM2
AHB1
peripherals
AHB2
peripherals
MPCWM1
OctoSPI1
FSMC
MPCWM2
MPCWM3
BusMatrix-S
MSv61198V1
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Functional overview
3.15
Direct memory access controller (DMA)
The device embeds 2 DMAs. Refer to Table 13: DMA1 and DMA2 implementation for the
features implementation.
Direct memory access (DMA) is used in order to provide a high-speed data transfer
between peripherals and memory as well as from memory to memory. Data can be quickly
moved by DMA without any CPU actions. This keeps the CPU resources free for other
operations.
The two DMA controllers have 16 channels in total, each one dedicated to manage memory
access requests from one or more peripherals. Each controller has an arbiter for handling
the priority between DMA requests.
The DMA supports 8 channels for each DMA1 and DMA2, independently configurable:
•
•
•
•
Each channel is associated either with a DMA request signal coming from a peripheral,
or with a software trigger in memory-to-memory transfers. This configuration is done by
software.
Priority between the requests is programmable by software (4 levels per channel: very
high, high, medium, low) or by hardware in case of equality (such as request 1 has
priority over request 2).
Transfer size of source and destination are independent (byte, half-word, word),
emulating packing and unpacking. Source and destination addresses must be aligned
on the data size.
Support of transfers from/to peripherals to/from memory with circular buffer
management.
18
•
•
Programmable number of data to be transferred: 0 to 2 - 1.
Generation of an interrupt request per channel. Each interrupt request is caused from
any of the three DMA events: transfer complete, half transfer, or transfer error.
•
TrustZone support:
–
Support for AHB secure and non-secure DMA transfers, independently at a first
channel level, and independently at a source and destination sub-level
–
TrustZone-aware AHB slave port, protecting any secure resource (register,
register field) from a non-secure software access
•
Privileged / unprivileged support:
–
Support for AHB privileged and unprivileged DMA transfers, independently at a
channel level
–
Privileged-aware AHB slave port.
Table 13. DMA1 and DMA2 implementation
Feature
DMA1
DMA2
Number of DMA channels
TrustZone
8
8
1 (supported)
1 (supported)
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3.16
DMA request router (DMAMUX)
When a peripheral indicates a request for DMA transfer by setting its DMA request line, the
DMA request is pending until it is served and the corresponding DMA request line is reset.
The DMA request router allows to route the DMA control lines between the peripherals and
the DMA controllers of the product.
An embedded multi-channel DMA request generator can be considered as one of such
peripherals. The routing function is ensured by a multi-channel DMA request line
multiplexer. Each channel selects a unique set of DMA control lines, unconditionally or
synchronously with events on synchronization inputs.
DMAMUX main features
•
•
•
•
•
16-channel programmable DMA request line multiplexer output
4-channel DMA request generator
23 trigger inputs to DMA request generator
23 synchronization inputs
Per DMA request generator channel:
–
–
–
DMA request trigger input selector
DMA request counter
Event overrun flag for selected DMA request trigger input
•
•
Per DMA request line multiplexer channel output:
–
–
–
–
–
–
90 input DMA request lines from peripherals
One DMA request line output
Synchronization input selector
DMA request counter
Event overrun flag for selected synchronization input
One event output, for DMA request chaining
TrustZone support:
–
Support for AHB secure and non-secure DMA transfers, independently at a
channel level.
–
TrustZone-aware AHB slave port, protecting any secure resource (register,
register field) from a non-secure software access, with configurable interrupt
event.
–
Two secure and non-secure interrupt requests, resulting from any of the
respectively secure and non-secure channels. Each channel event being caused
from any of the two DMAMUX input events: trigger or synchronization overrun,
associated with a respectively secure and non-secure channels.
•
Privileged / Unprivileged support:
–
Support for AHB privileged and unprivileged DMA transfers, independently, at a
channel level.
–
Privileged-aware AHB slave port.
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Functional overview
3.17
Interrupts and events
3.17.1
Nested vectored interrupt controller (NVIC)
The devices embed a nested vectored interrupt controller which is able to manage 8 priority
levels, and to handle up to 109 maskable interrupt channels plus the 16 interrupt lines of the
®
Cortex -M33.
The NVIC benefits are the following:
•
•
•
•
•
•
•
•
Closely coupled NVIC gives low latency interrupt processing
Interrupt entry vector table address passed directly to the core
Allows early processing of interrupts
Processing of late arriving higher priority interrupts
Support for tail chaining
Processor state automatically saved
Interrupt entry restored on interrupt exit with no instruction overhead
TrustZone support. The NVIC registers are banked across secure and non-secure
states
The NVIC hardware block provides flexible interrupt management features with minimal
interrupt latency.
3.17.2
Extended interrupt/event controller (EXTI)
The Extended interrupts and event controller (EXTI) manages the individual CPU and
system wakeup through configurable and direct event inputs. It provides wakeup requests to
the power control, and generates an interrupt request to the CPU NVIC and events to the
CPU event input. For the CPU an additional Event Generation block (EVG) is needed to
generate the CPU event signal.
The EXTI wakeup requests allow the system to be woken up from Stop modes.
The interrupt request and event request generation can also be used in RUN modes. The
EXTI also includes the EXTI mux IOport selection.
The EXTI main features are the following:
The EXTI main features are the following:
•
•
•
43 input events supported
All event inputs allow to wake up the system.
Events which do not have an associated wakeup flag in the peripheral, have a flag in
the EXTI and generate an interrupt to the CPU from the EXTI.
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Functional overview
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The asynchronous event inputs are classified in 2 groups:
•
Configurable events (signals from I/Os or peripherals able to generate a pulse)
–
Configurable events have the following features:
Selectable active trigger edge
Interrupt pending status register bit independent for the rising and falling edge.
Individual interrupt and event generation mask, used for conditioning the CPU
wakeup, interrupt and event generation.
SW trigger possibility
•
Direct events (interrupt and wakeup sources from peripherals having an associated
flag which requiring to be cleared in the peripheral)
–
Direct events have the following features:
Fixed rising edge active trigger
No interrupt pending status register bit in the EXTI. (The interrupt pending status
flag is provided by the peripheral generating the event.)
Individual interrupt and event generation mask, used for conditioning the CPU
wakeup and event generation.
No SW trigger possibility
•
•
TrustZone secure events
–
The access to control and configuration bits of secure input events can be made
secure.
EXTI IO port selection
3.18
Cyclic redundancy check calculation unit (CRC)
The CRC (cyclic redundancy check) calculation unit is used to get a CRC code using a
configurable generator with polynomial value and size.
Among other applications, the CRC-based techniques are used to verify data transmission
or storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a mean to verify
the Flash memory integrity.
The CRC calculation unit helps to compute a signature of the software during runtime, which
can be ulteriorly compared with a reference signature generated at link-time and which can
be stored at a given memory location.
3.19
Flexible static memory controller (FSMC)
The flexible static memory controller (FSMC) includes two memory controllers:
•
•
The NOR/PSRAM memory controller
The NAND/memory controller
This memory controller is also named flexible memory controller (FMC).
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Functional overview
The main features of the FSMC controller are the following:
•
Interface with static-memory mapped devices including:
–
–
–
–
–
Static random access memory (SRAM)
NOR Flash memory/OneNAND Flash memory
PSRAM (four memory banks)
NAND Flash memory with ECC hardware to check up to 8 Kbytes of data
Ferroelectric RAM (FRAM)
•
•
•
•
8-,16- bit data bus width
Independent chip select control for each memory bank
Independent configuration for each memory bank
Write FIFO
LCD parallel interface
The FMC can be configured to interface seamlessly with most graphic LCD controllers. It
supports the Intel 8080 and Motorola 6800 modes, and is flexible enough to adapt to
specific LCD interfaces. This LCD parallel interface capability makes it easy to build cost
effective graphic applications using LCD modules with embedded controllers or high-
performance solutions using external controllers with dedicated acceleration.
TrustZone security
When the TrustZone security is enabled, the whole FSMC banks are secure after reset.
Non-secure area can be configured using the TZSC MPCWMx controller.
•
The FSMC NOR/PSRAM bank:
–
Up to two non-secure area can be configured thought the TZSC MPCWM2
controller with a granularity of 64 Kbytes.
•
The FSMC NAND bank:
–
Can be either configured as fully secure or fully non-secure using the TZSC
MPCWM3 controller.
The FSMC registers can be configured as secure through the TZSC controller.
3.20
Octo-SPI interface (OCTOSPI)
The OCTOSPI is a specialized communication interface targetting single, dual, quad or octal
SPI memories. It can operate in any of the three following modes:
•
•
Indirect mode: all the operations are performed using the OCTOSPI registers
Status polling mode: the external memory status register is periodically read and an
interrupt can be generated in case of flag setting
•
Memory-mapped mode: the external memory is memory mapped and is seen by the
system as if it were an internal memory supporting read and write operation
The OCTOSPI supports two frame formats:
•
Classical frame format with command, address, alternate byte, dummy cycles and data
phase over 1, 2, 4 or 8 data pins
TM
•
HyperBus frame format
The OCTOSPI offers the following features:
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Functional overview
STM32L552xx
•
•
•
•
Three functional modes: indirect, status-polling, and memory-mapped
Read and write support in memory-mapped mode
Supports for single, dual, quad and octal communication
Dual-quad mode, where 8 bits can be sent/received simultaneously by accessing two
quad memories in parallel.
•
•
•
•
•
SDR and DTR support
Data strobe support
Fully programmable opcode for both indirect and memory mapped mode
Fully programmable frame format for both indirect and memory mapped mode
Each of the five following phases can be configured independently (enable, length,
single/dual/quad communication)
–
–
–
–
–
Instruction phase
Address phase
Alternate bytes phase
Dummy cycles phase
Data phase
TM
•
•
•
•
•
•
HyperBus support
Integrated FIFO for reception and transmission
8, 16, and 32-bit data accesses are allowed
DMA channel for indirect mode operations
Timeout management
Interrupt generation on FIFO threshold, timeout, status match, operation complete, and
access error
TrustZone security
When the TrustZone security is enabled, the whole OCTOSPI bank is secure after reset.
Up to two non-secure area can be configured thought the TZSC MPCWM1 controller with a
granularity of 64 Kbytes.
The OCTOSPI registers can be configured as secure through the TZSC controller.
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Functional overview
3.21
Analog-to-digital converter (ADC)
The device embeds two successive approximation analog-to-digital converters with the
following features:
•
•
12-bit native resolution, with built-in calibration
5.33 Msps maximum conversion rate with full resolution
–
–
Down to 18.75 ns sampling time
Increased conversion rate for lower resolution (up to 8.88 Msps for 6-bit
resolution)
•
•
Up to 16 external channels
5 internal channels: internal reference voltage, temperature sensor, VBAT/3 and DAC1
outputs
•
One external reference pin is available on some package, allowing the input voltage
range to be independent from the power supply
•
•
Single-ended and differential mode inputs
Low-power design
–
Capable of low-current operation at low conversion rate (consumption decreases
linearly with speed)
–
Dual clock domain architecture: ADC speed independent from CPU frequency
•
Highly versatile digital interface
–
Single-shot or continuous/discontinuous sequencer-based scan mode: 2 groups
of analog signals conversions can be programmed to differentiate background and
high-priority real-time conversions
–
Each ADC support multiple trigger inputs for synchronization with on-chip timers
and external signals
–
–
–
–
–
Results stored into a data register or in RAM with DMA controller support
Data pre-processing: left/right alignment and per channel offset compensation
Built-in oversampling unit for enhanced SNR
Channel-wise programmable sampling time
Analog watchdog for automatic voltage monitoring, generating interrupts and
trigger for selected timers
–
Hardware assistant to prepare the context of the injected channels to allow fast
context switching
3.21.1
Temperature sensor
The temperature sensor (TS) generates a voltage V that varies linearly with temperature.
TS
The temperature sensor is internally connected to the ADC1_IN17 input channels which is
used to convert the sensor output voltage into a digital value.
The sensor provides good linearity but it has to be calibrated to obtain good overall
accuracy of the temperature measurement. As the offset of the temperature sensor varies
from chip to chip due to process variation, the uncalibrated internal temperature sensor is
suitable for applications that detect temperature changes only.
To improve the accuracy of the temperature sensor measurement, each device is
individually factory-calibrated by ST. The temperature sensor factory calibration data are
stored by ST in the system memory area, accessible in read-only mode.
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Table 14. Temperature sensor calibration values
Calibration value name
Description
Memory address
TS ADC raw data acquired at a
temperature of 30 °C (± 5 °C),
TS_CAL1
TS_CAL2
0x0BFA 05A8 - 0x0BFA 05A9
0x0BFA 05CA- 0x0BFA 05CB
VDDA = VREF+ = 3.0 V (± 10 mV)
TS ADC raw data acquired at a
temperature of 130 °C (± 5 °C),
VDDA = VREF+ = 3.0 V (± 10 mV)
3.21.2
Internal voltage reference (V
)
REFINT
The internal voltage reference (VREFINT) provides a stable (bandgap) voltage output for
the ADC and the comparators. The VREFINT is internally connected to the ADC1_IN0 input
channel. The precise voltage of VREFINT is individually measured for each part by ST
during production test and stored in the system memory area. It is accessible in read-only
mode.
Table 15. Internal voltage reference calibration values
Calibration value name
Description
Memory address
Raw data acquired at a
VREFINT
temperature of 30 °C (± 5 °C),
0x0BFA 05AA - 0x0BFA 05AB
VDDA = VREF+ = 3.0 V (± 10 mV)
3.21.3
VBAT battery voltage monitoring
This embedded hardware enables the application to measure the V
battery voltage using
BAT
the internal ADC channel ADC1_IN18. As the V
voltage may be higher than the VDDA,
BAT
and thus outside the ADC input range, the VBAT pin is internally connected to a bridge
divider by 3. As a consequence, the converted digital value is one third of the V voltage.
BAT
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Functional overview
3.22
Digital to analog converter (DAC)
Two 12-bit buffered DAC channels can be used to convert digital signals into analog voltage
signal outputs. The chosen design structure is composed of integrated resistor strings and
an amplifier in inverting configuration.
This digital interface supports the following features:
•
•
•
•
•
•
•
•
•
•
•
Up to two DAC output channels
8-bit or 12-bit output mode
Buffer offset calibration (factory and user trimming)
Left or right data alignment in 12-bit mode
Synchronized update capability
Noise-wave generation
Triangular-wave generation
Dual DAC channel independent or simultaneous conversions
DMA capability for each channel
External triggers for conversion
Sample and hold low-power mode, with internal or external capacitor
The DAC channels are triggered through the timer update outputs that are also connected
to different DMA channels.
3.23
Voltage reference buffer (VREFBUF)
The devices embed a voltage reference buffer which can be used as voltage reference for
ADC, DACs and also as voltage reference for external components through the VREF+ pin.
The internal voltage reference buffer supports two voltages:
•
•
2.048 V
2.5 V
An external voltage reference can be provided through the VREF+ pin when the internal
voltage reference buffer is off.
The VREF+ pin is double-bonded with VDDA on some packages. In these packages the
internal voltage reference buffer is not available.
Figure 9. Voltage reference buffer
VREFBUF
VDDA DAC, ADC
Bandgap
+
-
VREF+
Low frequency
cut-off capacitor
100 nF
MSv40197V1
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3.24
Comparators (COMP)
The devices embed two rail-to-rail comparators with programmable reference voltage
(internal or external), hysteresis and speed (low speed for low-power) and with selectable
output polarity.
The reference voltage can be one of the following:
•
•
•
External I/O
DAC output channels
Internal reference voltage or submultiple (1/4, 1/2, 3/4).
All comparators can wake up from Stop mode, generate interrupts and breaks for the timers
and can also be combined into a window comparator.
3.25
Operational amplifier (OPAMP)
The devices embed two operational amplifiers with external or internal follower routing and
PGA capability.
The operational amplifier features:
•
•
•
•
Low input bias current
Low offset voltage
Low-power mode
Rail-to-rail input
3.26
Digital filter for sigma-delta modulators (DFSDM)
The devices embed one DFSDM with four digital filters modules and eight external input
serial channels (transceivers) or alternately eight internal parallel inputs support.
The DFSDM peripheral is dedicated to interface the external Σ∆ modulators to the
microcontroller and then to perform digital filtering of the received data streams (which
represent analog value on Σ∆ modulators inputs).
The DFSDM can also interface the PDM (pulse density modulation) microphones and
perform PDM to PCM conversion and filtering in hardware. The DFSDM features optional
parallel data stream inputs from microcontrollers memory (through DMA/CPU transfers into
DFSDM).
The DFSDM transceivers support several serial interface formats (to support various Σ∆
modulators) and the DFSDM digital filter modules perform digital processing according to
the user’s selected filter parameters with up to 24-bit final ADC resolution.
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Functional overview
The DFSDM peripheral supports:
•
Up to 4 multiplexed input digital serial channels:
–
–
–
Configurable SPI interface to connect various Σꢀ modulators
Configurable Manchester coded 1 wire interface support
Clock output for Σꢀ modulator(s)
•
•
•
Alternative inputs from up to 4 internal digital parallel channels:
–
–
Inputs with up to 16 bit resolution
Internal sources: ADCs data or memory (CPU/DMA write) data streams
Adjustable digital signal processing:
–
–
Sincx filter: filter order/type (1..5), oversampling ratio (up to 1..1024)
Integrator: oversampling ratio (1..256)
Up to 24-bit output data resolution:
Right bit-shifter on final data (0..31 bits)
–
•
•
•
•
Signed output data format
Automatic data offset correction (offset stored in register by user)
Continuous or single conversion
Start-of-conversion synchronization with:
–
–
–
–
Software trigger
Internal timers
External events
Start-of-conversion synchronously with first DFSDM filter (DFSDM_FLT0)
•
•
Analog watchdog feature:
–
–
–
–
Low value and high value data threshold registers
Own configurable Sincx digital filter (order = 1..3, oversampling ratio = 1..32)
Input from output data register or from one or more input digital serial channels
Continuous monitoring independently from standard conversion
Short-circuit detector to detect saturated analog input values (bottom and top ranges):
–
–
Up to 8-bit counter to detect 1..256 consecutive 0’s or 1’s on input data stream
Mnitoring continuously each channel (4 serial channel transceiver outputs)
•
•
Break generation on analog watchdog event or short-circuit detector event
Extremes detector:
–
–
Store minimum and maximum values of output data values
Refreshed by software
•
•
DMA may be used to read the conversion data
Interrupts: end of conversion, overrun, analog watchdog, short-circuit, channel clock
absence
•
“Regular” or “injected” conversions:
–
“Regular” conversions can be requested at any time or even in continuous mode
without having any impact on the timing of “injected” conversions.
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3.27
Touch sensing controller (TSC)
The touch sensing controller provides a simple solution to add capacitive sensing
functionality to any application. A capacitive sensing technology is able to detect finger
presence near an electrode that is protected from direct touch by a dielectric (glass, plastic
or other). The capacitive variation introduced by the finger (or any conductive object) is
measured using a proven implementation based on a surface charge transfer acquisition
principle.
The touch sensing controller is fully supported by the STMTouch touch sensing firmware
library which is free to use and allows touch sensing functionality to be implemented reliably
in the end application.
The main features of the touch sensing controller are the following:
•
•
•
Proven and robust surface charge transfer acquisition principle
Supports up to 22 capacitive sensing channels
Up to 3 capacitive sensing channels can be acquired in parallel offering a very good
response time
•
•
•
•
•
•
•
•
Spread spectrum feature to improve system robustness in noisy environments
Full hardware management of the charge transfer acquisition sequence
Programmable charge transfer frequency
Programmable sampling capacitor I/O pin
Programmable channel I/O pin
Programmable max count value to avoid long acquisition when a channel is faulty
Dedicated end of acquisition and max count error flags with interrupt capability
One sampling capacitor for up to 3 capacitive sensing channels to reduce the system
components
•
•
Compatible with proximity, touchkey, linear and rotary touch sensor implementation
Designed to operate with STMTouch touch sensing firmware library
Note:
The number of capacitive sensing channels is dependent on the size of the packages and
subject to I/O availability.
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Functional overview
3.28
True random number generator (RNG)
The RNG is a true random number generator that provides full entropy outputs to the
application as 32-bit samples. It is composed of a live entropy source (analog) and an
internal conditioning component.
The RNG is a NIST SP 800-90B compliant entropy source that can be used to construct a
non-deterministic random bit generator (NDRBG).
The true random number generator:
•
•
•
•
•
•
delivers 32-bit true random numbers, produced by an analog entropy source
conditioned by a NIST SP800-90B approved conditioning stage,
can be used as entropy source to construct a non-deterministic random bit generator
(NDRBG),
produces four 32-bit random samples every 412 AHB clock cycles if fAHB < 77 MHz
(256 RNG clock cycles otherwise),
embeds start-up and NIST SP800-90B approved continuous health tests (repetition
count and adaptive proportion tests), associated with specific error management,
can be disabled to reduce power consumption, or enabled with an automatic low-power
mode (default configuration),
has an AMBA AHB slave peripheral, accessible through 32-bit word single accesses
only (else an AHB bus error is generated, and the write accesses are ignored).
3.29
HASH hardware accelerator (HASH)
The hash processor is a fully compliant implementation of the secure hash algorithm (SHA-
1, SHA-224, SHA-256), the MD5 (message-digest algorithm 5) hash algorithm and the
HMAC (keyed-hash message authentication code) algorithm suitable for a variety of
applications.
It computes a message digest (160 bits for the SHA-1 algorithm, 256 bits for the SHA-256
algorithm and 224 bits for the SHA-224 algorithm,128 bits for the MD5 algorithm) for
messages of up to (264 - 1) bits, while the HMAC algorithms provide a way of authenticating
messages by means of hash functions. The HMAC algorithms consist in calling the SHA-1,
SHA-224, SHA-256 or MD5 hash function twice.
3.30
Timers and watchdogs
The devices include two advanced control timers, up to nine general-purpose timers, two
basic timers, two low-power timers, two watchdog timers and a SysTick timer.
Table 16 compares the features of the advanced control, general-purpose and basic timers.
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Table 16. Timer feature comparison
DMA
request
generation channels
Capture/
compare
Counter
resolution
Counter
type
Prescaler
factor
Complementary
outputs
Timer type
Timer
Any integer
between 1
and 65536
Advanced
control
Up, down,
Up/down
TIM1, TIM8
TIM2, TIM5
TIM3, TIM4
TIM15
16-bit
32-bit
16-bit
16-bit
16-bit
16-bit
Yes
Yes
Yes
Yes
Yes
Yes
4
4
4
2
1
0
3
No
No
1
Any integer
between 1
and 65536
General-
purpose
Up, down,
Up/down
Any integer
between 1
and 65536
General-
purpose
Up, down,
Up/down
Any integer
between 1
and 65536
General-
purpose
Up
Up
Up
Any integer
between 1
and 65536
General-
purpose
TIM16, TIM17
TIM6, TIM7
1
Any integer
between 1
and 65536
Basic
No
3.30.1
Advanced-control timer (TIM1, TIM8)
The advanced-control timers can each be seen as a three-phase PWM multiplexed on six
channels. They have complementary PWM outputs with programmable inserted dead-
times. They can also be seen as complete general-purpose timers.
The four independent channels can be used for:
•
•
•
Input capture
Output compare
PWM generation (edge or center-aligned modes) with full modulation capability (0-
100%)
•
One-pulse mode output
In debug mode, the advanced-control timer counter can be frozen and the PWM outputs
disabled in order to turn off any power switches driven by these outputs.
Many features are shared with the general-purpose TIMx timers (described in
Section 3.30.2) using the same architecture, so the advanced-control timers can work
together with the TIMx timers via the Timer Link feature for synchronization or event
chaining.
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Functional overview
3.30.2
General-purpose timers (TIM2, TIM3, TIM4, TIM5, TIM15, TIM16,
TIM17)
There are up to seven synchronizable general-purpose timers embedded in the
STM32L552xx devices (see Table 16 for differences).
Each general-purpose timer can be used to generate PWM outputs, or act as a simple time
base.
•
TIM2, TIM3, TIM4 and TIM5
They are full-featured general-purpose timers:
–
–
TIM2 and TIM5 have a 32-bit auto-reload up/downcounter and 32-bit prescaler
TIM3 and TIM4 have 16-bit auto-reload up/downcounter and 16-bit prescaler.
These timers feature four independent channels for input capture/output compare,
PWM or one-pulse mode output. They can work together, or with the other general-
purpose timers via the Timer Link feature for synchronization or event chaining.
The counters can be frozen in debug mode.
All have independent DMA request generation and support quadrature encoders.
TIM15, 16 and 17
•
They are general-purpose timers with mid-range features:
They have 16-bit auto-reload upcounters and 16-bit prescalers.
–
–
TIM15 has two channels and one complementary channel
TIM16 and TIM17 have one channel and one complementary channel
All channels can be used for input capture/output compare, PWM or one-pulse mode
output.
The timers can work together via the Timer Link feature for synchronization or event
chaining. The timers have independent DMA request generation.
The counters can be frozen in debug mode.
3.30.3
3.30.4
Basic timers (TIM6 and TIM7)
The basic timers are mainly used for DAC trigger generation. They can also be used as
generic 16-bit timebases.
Low-power timers (LPTIM1, LPTIM2 and LPTIM3)
The devices embed two low-power timers. These timers have an independent clock and are
running in Stop mode if they are clocked by LSE, LSI or an external clock. They are able to
wakeup the system from Stop mode.
LPTIM1 and LPTIM3 are active in Stop 0, Stop 1 and Stop 2 modes.
LPTIM2 is active in Stop 0 and Stop 1 mode.
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This low-power timer supports the following features:
•
•
•
•
•
•
16-bit up counter with 16-bit autoreload register
16-bit compare register
Configurable output: pulse, PWM
Continuous/ one shot mode
Selectable software/hardware input trigger
Selectable clock source
–
–
Internal clock sources: LSE, LSI, HSI16 or APB clock
External clock source over LPTIM input (working even with no internal clock
source running, used by pulse counter application).
•
•
Programmable digital glitch filter
Encoder mode (LPTIM1 only).
3.30.5
Independent watchdog (IWDG)
The independent watchdog is based on a 12-bit downcounter and an 8-bit prescaler. It is
clocked from an independent 32 kHz internal RC (LSI) and as it operates independently
from the main clock, it can operate in Stop and Standby modes. It can be used either as a
watchdog to reset the device when a problem occurs, or as a free running timer for
application timeout management. It is hardware or software configurable through the option
bytes. The counter can be frozen in debug mode.
3.30.6
3.30.7
Window watchdog (WWDG)
The window watchdog is based on a 7-bit downcounter that can be set as free running. It
can be used as a watchdog to reset the device when a problem occurs. It is clocked from
the main clock. It has an early warning interrupt capability and the counter can be frozen in
debug mode.
SysTick timer
®
The Cortex -M33 with TrustZone embeds two SysTick timers.
When TrustZone is activated, two SysTick timer are available:
•
•
SysTick, Secure instance.
SysTick, Non-secure instance.
When TrustZone is disabled, only one SysTick timer is available.
This timer (secure or non-secure) is dedicated to real-time operating systems, but could
also be used as a standard down counter. It features:
•
•
•
•
A 24-bit down counter
Autoreload capability
Maskable system interrupt generation when the counter reaches 0.
Programmable clock source
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Functional overview
3.31
Real-time clock (RTC)
The RTC supports the following features:
•
Calendar with subsecond, seconds, minutes, hours (12 or 24 format), week day, date,
month, year, in BCD (binary-coded decimal) format.
•
•
•
Automatic correction for 28, 29 (leap year), 30, and 31 days of the month.
Two programmable alarms.
On-the-fly correction from 1 to 32767 RTC clock pulses. This can be used to
synchronize it with a master clock.
•
•
•
Reference clock detection: a more precise second source clock (50 or 60 Hz) can be
used to enhance the calendar precision.
Digital calibration circuit with 0.95 ppm resolution, to compensate for quartz crystal
inaccuracy.
Timestamp feature which can be used to save the calendar content. This function can
be triggered by an event on the timestamp pin, or by a tamper event, or by a switch to
V
mode.
BAT
•
•
17-bit auto-reload wakeup timer (WUT) for periodic events with programmable
resolution and period.
TrustZone support:
–
–
RTC fully securable
Alarm A, alarm B, wakeup Timer and timestamp individual secure or non-secure
configuration
The RTC is supplied through a switch that takes power either from the V supply when
DD
present or from the V
pin.
BAT
The RTC clock sources can be:
•
•
•
•
A 32.768 kHz external crystal (LSE)
An external resonator or oscillator (LSE)
The internal low power RC oscillator (LSI, with typical frequency of 32 kHz)
The high-speed external clock (HSE), divided by a prescaler in the RCC.
The RTC is functional in VBAT mode and in all low-power modes when it is clocked by the
LSE. When clocked by the LSI, the RTC is not functional in VBAT mode, but is functional in
all low-power modes except Shutdown mode.
All RTC events (Alarm, WakeUp Timer, Timestamp) can generate an interrupt and wakeup
the device from the low-power modes.
3.32
Tamper and backup registers (TAMP)
32 32-bit backup registers are retained in all low-power modes and also in VBAT mode.
They can be used to store sensitive data as their content is protected by an tamper
detection circuit. 8 tamper pins and 7 internal tampers are available for anti-tamper
detection.
The external tamper pins can be configured for edge detection, or level detection with or
without filtering, or active tamper which increases the security level by auto checking that
the tamper pins are not externally opened or shorted.
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TAMP main features:
•
32 backup registers:
–
The backup registers (TAMP_BKPxR) are implemented in the RTC domain that
remains powered-on by VBAT when the VDD power is switched off
•
8 external tamper detection events
–
–
Each external event can be configured to be active or passive
External passive tampers with configurable filter and internal pull-up
•
•
•
•
5 internal tamper events
Any tamper detection can generate a RTC timestamp event
Any tamper detection can erase the backup registers
TrustZone support:
–
–
Tamper secure or non-secure configuration.
Backup registers configuration in 3 configurable-size areas:
1 read/write secure area
1 write secure/read non-secure area
1 read/write non-secure area
•
Monotonic counter.
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Functional overview
3.33
Inter-integrated circuit interface (I2C)
The device embeds four I2C. Refer to Table 17: I2C implementation for the features
implementation.
2
The I C bus interface handles communications between the microcontroller and the serial
2
2
I C bus. It controls all I C bus-specific sequencing, protocol, arbitration and timing.
The I2C peripheral supports:
•
I2C-bus specification and user manual rev. 5 compatibility:
–
–
–
–
–
–
–
Slave and master modes, multimaster capability
Standard-mode (Sm), with a bitrate up to 100 kbit/s
Fast-mode (Fm), with a bitrate up to 400 kbit/s
Fast-mode plus (Fm+), with a bitrate up to 1 Mbit/s and 20 mA output drive I/Os
7-bit and 10-bit addressing mode, multiple 7-bit slave addresses
Programmable setup and hold times
Optional clock stretching
•
System management bus (SMBus) specification rev 2.0 compatibility:
–
Hardware PEC (packet error checking) generation and verification with ACK
control
–
–
Address resolution protocol (ARP) support
SMBus alert
TM
•
•
Power system management protocol (PMBus ) specification rev 1.1 compatibility
Independent clock: a choice of independent clock sources allowing the I2C
communication speed to be independent from the PCLK reprogramming. Refer to
Figure 7: STM32L552xx clock tree
•
•
•
Wakeup from Stop mode on address match
Programmable analog and digital noise filters
1-byte buffer with DMA capability
Table 17. I2C implementation
I2C features(1)
I2C1
I2C2
I2C3
I2C4
Standard-mode (up to 100 kbit/s)
X
X
X
X
X
X
X
-
X
X
X
X
X
X
X
-
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
-
Fast-mode (up to 400 kbit/s)
Fast-mode Plus with 20 mA output drive I/Os (up to 1 Mbit/s)
Programmable analog and digital noise filters
SMBus/PMBus hardware support
Independent clock
Wakeup from Stop 0, Stop 1 mode on address match
Wakeup from Stop 2 mode on address match
1. X: supported
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3.34
Universal synchronous/asynchronous receiver transmitter
(USART)
The devices have three embedded universal synchronous receiver transmitters (USART1,
USART2 and USART3) and two universal asynchronous receiver transmitters (UART4,
UART5).
These interfaces provide asynchronous communication, IrDA SIR ENDEC support,
multiprocessor communication mode, single-wire half-duplex communication mode and
have LIN master/slave capability. They provide hardware management of the CTS and RTS
signals, and RS485 driver enable. They are able to communicate at speeds of up to
10 Mbit/s.
The USART1, USART2 and USART3 also provide a Smartcard mode (ISO 7816 compliant)
and an SPI-like communication capability.
All USART have a clock domain independent from the CPU clock, allowing the USARTx
(x=1,2,3,4,5) to wake up the MCU from Stop mode using baudrates up to 200 Kbaud. The
wake up events from Stop mode are programmable and can be:
•
•
•
Start bit detection
Any received data frame
A specific programmed data frame
All USART interfaces can be served by the DMA controller.
Table 18. USART/UART/LPUART features
USART modes/features(1)
USART1 USART2 USART3 UART4 UART5 LPUART1
Hardware flow control for modem
Continuous communication using DMA
Multiprocessor communication
Synchronous mode
X
X
X
X
X
X
X
X
X
X
-
X
X
X
X
X
X
X
X
X
X
-
X
X
X
X
-
X
X
X
-
X
X
X
-
X
X
X
Smartcard mode
X
-
-
-
Single-wire half-duplex communication
IrDA SIR ENDEC block
LIN mode
X
X
X
X
X
X
-
X
X
X
X
X
-
X
-
X
X
-
Dual clock domain
X
X
X
X
-
Wakeup from Stop 0 / Stop 1 modes
Wakeup from Stop 2 mode
Receiver timeout interrupt
Modbus communication
Auto baud rate detection
Driver enable
X
-
X
X
X
X
X
X
X
X
X
X
X (4 modes)
X
-
-
X
X
X
X
X
LPUART/USART data length
1. X = supported.
7, 8 and 9 bits
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DS12737 Rev 6
STM32L552xx
Functional overview
3.35
Low-power universal asynchronous receiver transmitter
(LPUART)
The devices embed one low-power UART. The LPUART supports asynchronous serial
communication with minimum power consumption. It supports half-duplex single-wire
communication and modem operations (CTS/RTS). It allows multiprocessor
communication.
The LPUART has a clock domain independent from the CPU clock, and can wakeup the
system from Stop mode using baudrates up to 220 Kbaud. The wake up events from Stop
mode are programmable and can be:
•
•
•
Start bit detection
Any received data frame
A specific programmed data frame
Only a 32.768 kHz clock (LSE) is needed to allow LPUART communication up to 9600
baud. Therefore, even in Stop mode, the LPUART can wait for an incoming frame while
having an extremely low energy consumption. Higher speed clock can be used to reach
higher baudrates.
The LPUART interface can be served by the DMA controller.
3.36
3.37
Serial peripheral interface (SPI)
Three SPI interfaces allow communication up to slave modes, in half-duplex, full-duplex and
simplex modes. The 3-bit prescaler gives eight master mode frequencies and the frame size
is configurable from 4 bits to 16 bits. The SPI interfaces support NSS pulse mode, TI mode
and hardware CRC calculation.
All SPI interfaces can be served by the DMA controller.
Serial audio interfaces (SAI)
The devices embed two SAI. Refer to Table 19: SAI implementation for the features
implementation. The SAI bus interface handles communications between the
microcontroller and the serial audio protocol.
The SAI peripheral supports:
•
Two independent audio sub-blocks which can be transmitters or receivers with their
respective FIFO.
•
•
•
•
8-word integrated FIFOs for each audio sub-block.
Synchronous or asynchronous mode between the audio sub-blocks.
Master or slave configuration independent for both audio sub-blocks.
Clock generator for each audio block to target independent audio frequency sampling
when both audio sub-blocks are configured in master mode.
•
•
Data size configurable: 8-, 10-, 16-, 20-, 24-, 32-bit.
Peripheral with large configurability and flexibility allowing to target as example the
following audio protocol: I2S, LSB or MSB-justified, PCM/DSP, TDM, AC’97 and SPDIF
out.
DS12737 Rev 6
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78
Functional overview
STM32L552xx
•
Up to 16 slots available with configurable size and with the possibility to select which
ones are active in the audio frame.
•
•
•
•
•
•
•
•
Number of bits by frame may be configurable.
Frame synchronization active level configurable (offset, bit length, level).
First active bit position in the slot is configurable.
LSB first or MSB first for data transfer.
Mute mode.
Stereo/Mono audio frame capability.
Communication clock strobing edge configurable (SCK).
Error flags with associated interrupts if enabled respectively.
–
–
–
–
Overrun and underrun detection.
Anticipated frame synchronization signal detection in slave mode.
Late frame synchronization signal detection in slave mode.
Codec not ready for the AC’97 mode in reception.
•
•
Interruption sources when enabled:
–
–
Errors.
FIFO requests.
DMA interface with two dedicated channels to handle access to the dedicated
integrated FIFO of each SAI audio sub-block.
Table 19. SAI implementation
SAI features(1)
SAI1
SAI2
I2S, LSB or MSB-justified, PCM/DSP, TDM, AC’97
X
X
Mute mode
X
X
Stereo/Mono audio frame capability.
X
X
16 slots
X
X
Data size configurable: 8-, 10-, 16-, 20-, 24-, 32-bit
X
X
FIFO size
SPDIF
X (8 Word)
X (8 Word)
X
X
X
-
PDM
1. X: supported
3.38
Secure digital input/output and MultiMediaCards Interface
(SDMMC)
The SD/SDIO, MultiMediaCard (MMC) host interface (SDMMC) provides an interface
between the AHB bus and SD memory cards, SDIO cards and MMC devices.
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DS12737 Rev 6
STM32L552xx
Functional overview
The SDMMC features include the following:
•
Full compliance with MultiMediaCard System Specification Version 4.51. Card support
for three different databus modes: 1-bit (default), 4-bit and 8-bit
•
•
Full compatibility with previous versions of MultiMediaCards (backward compatibility)
Full compliance with SD Memory Card Specifications Version 4.1. (SDR104
SDMMC_CK speed limited to maximum allowed IO speed, SPI mode and UHS-II mode
not supported)
•
Full compliance with SDIO Card Specification Version 4.0: card support for two different
databus modes: 1-bit (default) and 4-bit. (SDR104 SDMMC_CK speed limited to
maximum allowed IO speed, SPI mode and UHS-II mode not supported)
•
•
Data transfer up to 104 Mbyte/s for the 8-bit mode (depending maximum allowed IO
speed)
Data and command output enable signals to control external bidirectional drivers.
3.39
3.40
Controller area network (FDCAN)
The controller area network (CAN) subsystem consists of one CAN modules and message
RAM memory.
The CAN module (FDCAN) is compliant with ISO 11898-1 (CAN protocol specification
version 2.0 part A, B) and CAN FD protocol specification version 1.0.
A 1 Kbyte message RAM memory implements filters, receive FIFOs, receive buffers,
transmit event FIFOs, transmit buffers.
Universal serial bus (USB FS)
The devices embed a full-speed USB device peripheral compliant with the USB
specification version 2.0. The internal USB PHY supports USB FS signaling, embedded DP
pull-up and battery charging detection according to Battery Charging Specification Revision
1.2.
The USB interface implements a full-speed (12 Mbit/s) function interface with added support
for USB 2.0 link power management. It has software-configurable endpoint setting with
packet memory up-to 1 Kbyte and suspend/resume support.
This interface requires a precise 48 MHz clock which can be generated from the internal
main PLL (the clock source must use a HSE crystal oscillator) or by the internal 48 MHz
oscillator (HSI48) in automatic trimming mode. The synchronization for this oscillator can be
taken from the USB data stream itself (SOF signalization) which allows crystal less
operation.
3.41
USB Type-C™ / USB Power Delivery controller (UCPD)
The device embeds one controller (UCPD) compliant with USB Type-C Rev. 1.2 and USB
Power Delivery Rev. 3.0 specifications.
DS12737 Rev 6
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78
Functional overview
STM32L552xx
The controller uses specific I/Os supporting the USB Type-C and USB Power Delivery
requirements, featuring:
•
•
•
•
USB Type-C pull-up (Rp, all values) and pull-down (Rd) resistors
“Dead battery” support
USB Power Delivery message transmission and reception
FRS (fast role swap) support
The digital controller handles notably:
•
•
•
USB Type-C level detection with debounce, generating interrupts
FRS detection, generating an interrupt
Byte-level interface for USB Power Delivery payload, generating interrupts (DMA
compatible)
•
•
•
•
•
USB Power Delivery timing dividers (including a clock pre-scaler)
CRC generation/checking
4b5b encode/decode
Ordered sets (with a programmable ordered set mask at receive)
Frequency recovery in receiver during preamble
The interface offers low-power operation compatible with Stop mode, maintaining the
capacity to detect incoming USB Power Delivery messages and FRS signaling.
3.42
Development support
3.42.1
Serial wire JTAG debug port (SWJ-DP)
®
The Arm SWJ-DP interface is embedded, and is a combined JTAG and serial wire debug
port that enables either a serial wire debug or a JTAG probe to be connected to the target.
Debug is performed using two pins only instead of five required by the JTAG (JTAG pins
could be re-used as GPIO with alternate function): the JTAG TMS and TCK pins are shared
with SWDIO and SWCLK, respectively, and a specific sequence on the TMS pin is used to
switch between JTAG-DP and SW-DP.
3.42.2
Embedded Trace Macrocell™
®
The Arm Embedded Trace Macrocell provides a greater visibility of the instruction and data
flow inside the CPU core by streaming compressed data at a very high rate from the devices
through a small number of ETM pins to an external hardware trace port analyzer (TPA)
device. Real-time instruction and data flow activity be recorded and then formatted for
display on the host computer that runs the debugger software. TPA hardware is
commercially available from common development tool vendors.
The Embedded Trace Macrocell operates with third party debugger software tools.
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DS12737 Rev 6
STM32L552xx
Pinouts and pin description
4
Pinouts and pin description
Figure 10. STM32L552xx LQFP48 pinout
VBAT
PC13
1
36
35
34
33
32
31
30
29
28
27
26
25
VDD
VSS
2
PC14_OSC32_IN
PC15_OSC32_OUT
PH0-OSC_IN
PH1-OSC_OUT
NRST
3
PA13
PA12
PA11
PA10
PA9
4
5
6
LQFP48
7
VSSA/VREF-
VDDA/VREF+
PA0
8
PA8
9
PB15
PB14
PB13
PB12
10
11
12
PA1
PA2
MSv49322V1
1. The above figure shows the package top view.
Figure 11. STM32L552xxxxP LQFP48 external SMPS pinout
VBAT
PC13
1
36
35
34
33
32
31
30
29
28
27
26
25
VDD
VSS
2
PC14-OSC_IN
PC15-OSC_OUT
PH0-OSC_IN
PH1-OSC_OUT
NRST
3
PA13
PA12
PA11
PA10
PA9
4
5
6
LQFP48
7
VSSA/VREF-
VDDA/VREF+
PA0
8
PA8
9
PB15
PB14
PB13
PB12
10
11
12
PA1
PA2
MSv49311V1
1. The above figure shows the package top view.
DS12737 Rev 6
79/340
137
Pinouts and pin description
STM32L552xx
Figure 12. STM32L552xx UFQFPN48 pinout
VBAT
PC13
1
36
35
34
33
32
31
30
29
28
27
26
25
VDD
VSS
2
PC14-OSC32_IN
3
PA13
PA12
PA11
PA10
PA9
PC15-OSC32_OUT
PH0-OSC_IN
PH1-OSC_OUT
NRST
4
5
6
UFQFPN48
7
VSSA/VREF-
VDDA/VREF+
PA0
8
PA8
9
PB15
PB14
PB13
PB12
10
11
12
PA1
PA2
MSv49321V2
1. The above figure shows the package top view.
Figure 13. STM32L552xxxxP UFQFPN48 external SMPS pinout
VBAT
PC13
1
36
35
34
33
32
31
30
29
28
27
26
25
VDD
VSS
2
PC14-OSC_IN
PC15-OSC_OUT
PH0-OSC_IN
PH1-OSC_OUT
NRST
3
PA13
PA12
PA11
PA10
PA9
4
5
6
UFQFPN48
7
VSSA/VREF-
VDDA/VREF+
PA0
8
PA8
9
PB15
PB14
PB13
PB12
10
11
12
PA1
PA2
MSv49310V2
1. The above figure shows the package top view.
80/340
DS12737 Rev 6
STM32L552xx
Pinouts and pin description
Figure 14. STM32L552xx LQFP64 pinout
VBAT
PC13
1
2
3
4
5
6
7
8
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
VDDUSB
VSS
PC14-OSC32_IN
PC15-OSC32_OUT
PH0-OSC_IN
PH1-OSC_OUT
NRST
PA13
PA12
PA11
PA10
PA9
PA8
PC9
PC8
PC7
PC0
PC1
PC2
PC3
LQFP64
9
10
11
12
13
14
15
16
VSSA/VREF-
VDDA/VREF+
PA0
PC6
PB15
PB14
PB13
PB12
PA1
PA2
MSv49323V1
1. The above figure shows the package top view.
Figure 15. STM32L552xxxxQ LQFP64 SMPS step down converter pinout
VBAT
PC13
1
2
3
4
5
6
7
8
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
VDDUSB
VSS
PC14-OSC32_IN
PC15-OSC32_OUT
PH0-OSC_IN
PH1-OSC_OUT
NRST
PA13
PA12
PA11
PA10
PA9
PA8
PC9
PC8
PC7
PC0
PC1
PC2
PC3
LQFP64
9
10
11
12
13
14
15
16
VSSA/VREF-
VDDA/VREF+
PA0
PC6
PB15
PB14
PB13
VDD
PA1
PA2
MSv49316V1
1. The above figure shows the package top view.
DS12737 Rev 6
81/340
137
Pinouts and pin description
STM32L552xx
Figure 16. STM32L552xxxxP LQFP64 external SMPS pinout
VBAT
PC13
1
2
3
4
5
6
7
8
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
VDDUSB
VSS
PC14-OSC32_IN
PC15-OSC32_OUT
PH0-OSC_IN
PH1-OSC_OUT
NRST
PA13
PA12
PA11
PA10
PA9
PA8
PC9
PC8
PC7
PC0
PC1
PC2
PC3
LQFP64
9
10
11
12
13
14
15
16
VSSA/VREF-
VDDA/VREF+
PA0
PC6
PB15
PB14
PB13
PB12
PA1
PA2
MSv49312V2
1. The above figure shows the package top view.
Figure 17. STM32L552xxxxQ WLCSP81 SMPS step down converter ballout
1
2
PC10
VSS
3
4
5
6
7
8
9
A
B
C
D
E
F
VDD
PD2
PG13
PG12
PG10
PG9
VDDIO2
VSS
PB5
PB4
PB6
PB7
PB3
PA1
PA2
PA5
PB0
PB9
V15SMPS_2
VSS
VDD
VBAT
VDDUSB
PA11
PC12
PC13
PB8
PC15-
OSC32_OUT
PC14-
OSC32_IN
PA12
PA13
PC7
PC11
PG15
PG14
PG11
PA3
PH1-
OSC_OUT
PA9
PA14
PH3-BOOT0
PC0
PH0-OSC_IN
NRST
PC6
PA10
PA15
PA8
VSS
PC1
PB15
PB13
PB12
VSS
PC8
PC2
VDD
G
H
J
PB14
PC9
PC4
PA6
PC3
VREF+
PA0
VSSA/VREF-
VDDA
VDD
VLXSMPS
VDDSMPS
PB11
PB10
PB1
PA4
V15SMPS_1
VSSSMPS
PB2
PA7
VDD
VSS
MSv49317V1
1. The above figure shows the package top view.
82/340
DS12737 Rev 6
STM32L552xx
Pinouts and pin description
Figure 18. STM32L552xxxxP WLCSP81 external SMPS ballout
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
VDD
PC10
VSS
PD2
PG13
PG12
PG10
PG9
VDDIO2
VSS
PB5
PB4
PB6
PB7
PB3
PA1
PA2
PA5
PB0
PB9
VDD12_2
VSS
VDD
VBAT
VDDUSB
PA11
PC12
PC11
PA14
PA10
PC8
PC13
PB8
PC15-
OSC32_OUT
PC14-
OSC32_IN
PA12
PA13
PC7
PG15
PG14
PG11
PA3
PH1-
OSC_OUT
PA9
PH3-BOOT0
PC0
PH0-OSC_IN
NRST
PC6
PA15
PA8
VSS
PC1
PB15
PB14
VDD
PB13
PB12
VSS
PC2
VDD
G
H
J
PC9
PC4
PA6
PC3
VREF+
PA0
VSSA/VREF-
VDDA
PE15
PB10
PE14
PE13
PB1
PA4
VDD12_1
PB11
PB2
PA7
VDD
VSS
MSv49313V1
1. The above figure shows the package top view.
Figure 19. STM32L552xx LQFP100 pinout
PE2
PE3
PE4
PE5
PE6
1
2
3
4
5
6
7
8
75
VDD
VSS
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
VDDUSB
PA13
PA12
PA11
PA10
PA9
PA8
PC9
PC8
PC7
VBAT
PC13
PC14-OSC32_IN
PC15-OSC32_OUT
VSS
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
VDD
PH0-OSC_IN
PH1-OSC_OUT
NRST
PC6
LQFP100
PD15
PD14
PD13
PD12
PD11
PD10
PD9
PC0
PC1
PC2
PC3
VSSA
VREF-
VREF+
VDDA
PA0
PA1
PD8
PB15
PB14
PB13
PB12
PA2
MSv49324V1
1. The above figure shows the package top view.
DS12737 Rev 6
83/340
137
Pinouts and pin description
STM32L552xx
Figure 20. STM32L552xxxxQ LQFP100 SMPS step down converter pinout
PE2
PE3
PE4
PE5
PE6
1
2
3
4
5
6
7
8
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
VDD
VSS
VDDUSB
PA13
PA12
PA11
PA10
PA9
PA8
PC9
PC8
PC7
VBAT
PC13
PC14-OSC32_IN
PC15-OSC32_OUT
VSS
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
VDD
PH0-OSC_IN
PH1-OSC_OUT
NRST
PC6
LQFP100
PD15
PD14
PD13
PD12
PD11
PD10
PD9
PC0
PC1
PC2
PC3
VSSA/VREF-
VREF+
VDDA
PD8
PA0
PA1
PA2
PA3
PB15
PB14
PB13
VDD
MSv49318V1
1. The above figure shows the package top view.
84/340
DS12737 Rev 6
STM32L552xx
Pinouts and pin description
Figure 21. STM32L552xx UFBGA132 ballout
1
2
3
4
5
6
7
8
9
10
11
12
VDDUSB
PA12
PA11
PA8
A
B
C
D
E
F
PE5
VBAT
PE3
PE4
PE6
PF0
PF1
PF5
NRST
PC0
PA0
PA2
PA6
PE1
PE2
PC13
PF3
PF4
PC2
PC1
PB9
PG15
PE0
VDD
VSS
PC3
PA1
VSS
VDD
PB2
PB1
PB0
PB6
PG12
PB4
PB3
PB5
PD6
PG9
PG10
PD7
PD5
PD2
PD1
PD0
VDD
VSS
PG6
PG4
VSS
VDD
PB10
PB11
PG14
PC11
PC12
PA13
PA9
PA15
PC10
PA14
PA10
PC9
PH3-BOOT0
PB8
PD4
PC14-
OSC32_IN
PD3
PC15-
OSC32_OUT
PB7
VDDIO2
PF2
PC7
PC8
PH0-OSC_IN
VSS
VDD
VDD
VSS
PG7
PG2
PD14
PD9
PC6
PG8
PH1-
OSC_OUT
G
H
J
PG3
PG5
OPAMP1_VI
NM
VSSA/VREF-
VREF+
VDDA
PD13
PD11
PB14
PB12
PG11
PD15
PD12
PB15
PD8
PC5
PA7
PA4
PC4
PF14
PF11
PF12
PF13
PE8
PG1
PF15
PG0
PE10
PE7
PE12
PE14
PE15
PE13
K
L
PB13
VSS
PG13
PA3
PE11
PE9
OPAMP2_VI
NM
M
PA5
PD10
MSv49325V1
1. The above figure shows the package top view.
Figure 22. STM32L552xxxxQ UFBGA132 SMPS step down converter ballout
1
2
3
4
5
6
7
8
9
10
PC11
PC12
PA13
11
12
VDDUSB
PA12
PA11
PA8
A
B
C
D
E
F
PE5
VBAT
PE3
PE4
PE6
PF0
PF1
PF5
NRST
PC0
PA0
PA2
PA6
PE1
PE2
PC13
PF3
PF4
PC2
PC1
PB9
PB6
PG12
PB4
PB3
PB5
PD6
PG9
PG10
PD7
PD5
PD2
PA15
V15SMPS_2 PH3-BOOT0
PD4
PD1
PC10
PA14
PC14-
OSC32_IN
PE0
VDD
VSS
PC3
PA1
VSS
VDD
PB2
PB1
PB0
PB8
PB7
PD3
PD0
PC15-
OSC32_OUT
VDDIO2
VDD
PA9
PA10
PF2
VSS
PC7
PC9
PC8
PH0-OSC_IN
VSS
VDD
VDD
VSS
PG6
PG7
PC6
PG8
PH1-
OSC_OUT
G
H
J
PG4
PG2
PG3
PG5
OPAMP1_VI
NM
VSSA/VREF-
VREF+
VDDA
VSS
PD14
PD9
PD13
PD11
PB14
PB12
V15SMPS_1
PD15
PD12
PB15
PD8
PC5
PA7
PA4
PC4
PF14
PF11
PF12
PF13
PE8
PG1
PF15
PG0
PE10
PE7
PE12
PE14
PE15
PE13
VDD
K
L
PB10
PB11
VDDSMPS
PB13
VSSSMPS
VLXSMPS
PA3
PE11
PE9
OPAMP2_VI
NM
M
PA5
PD10
MSv49319V1
1. The above figure shows the package top view.
DS12737 Rev 6
85/340
137
Pinouts and pin description
STM32L552xx
Figure 23. STM32L552xx LQFP144 pinout
PE2
1
108
107
106
105
104
103
102
101
100
99
VDD
VSS
PE3
2
PE4
PE5
PE6
VBAT
3
4
5
6
7
8
9
10
11
12
VDDUSB
PA13
PA12
PA11
PA10
PA9
PA8
PC9
PC8
PC7
PC13
PC14-OSC32_IN
PC15-OSC32_OUT
PF0
PF1
PF2
98
97
PF3
PF4
PF5
VSS
VDD
PF6
PF7
PF8
PF9
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
PC6
VDDIO2
VSS
PG8
PG7
PG6
PG5
PG4
PG3
LQFP144
PF10
PG2
PH0-OSC_IN
PH1-OSC_OUT
NRST
PC0
PD15
PD14
VDD
VSS
PD13
PD12
PD11
PD10
PD9
PC1
PC2
PC3
VSSA
VREF-
VREF+
VDDA
PA0
PD8
PB15
PB14
PB13
PB12
PA1
PA2
MSv49326V1
1. The above figure shows the package top view.
86/340
DS12737 Rev 6
STM32L552xx
Pinouts and pin description
Figure 24. STM32L552xxxxQ LQFP144 SMPS step down converter pinout
PE2
1
108
107
106
105
104
103
102
101
100
99
VDD
VSS
PE3
2
PE4
PE5
PE6
VBAT
3
4
5
6
7
8
9
10
11
12
VDDUSB
PA13
PA12
PA11
PA10
PA9
PA8
PC9
PC8
PC7
PC13
PC14-OSC32_IN
PC15-OSC32_OUT
PF0
PF1
PF2
98
97
PF3
PF4
PF5
VSS
VDD
PF6
PF7
PF8
PF9
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
PC6
VDDIO2
VSS
PG8
PG7
PG6
PG5
PG4
PG3
LQFP144
PF10
PG2
PH0-OSC_IN
PH1-OSC_OUT
NRST
PC0
PD15
PD14
VDD
VSS
PD13
PD12
PD11
PD10
PD9
PC1
PC2
PC3
VSSA/VREF-
VREF+
VDDA
PA0
PD8
PB15
PB14
PB13
VDD
PA1
PA2
PA3
MSv49320V1
1. The above figure shows the package top view.
DS12737 Rev 6
87/340
137
Table 20. Legend/abbreviations used in the pinout table
Abbreviation Definition
Name
Pin name
Unless otherwise specified in brackets below the pin name, the pin function during and after reset is the same as the actual pin name
S
I
Supply pin
Pin type
Input only pin
I/O
FT
TT
B
Input / output pin
5 V tolerant I/O
3.6 V tolerant I/O
Dedicated BOOT0 pin
RST
Bidirectional reset pin with embedded weak pull-up resistor
Option for TT or FT I/Os
_f (1)
_u (2)
_a (3)(4)
_s (5)
_c
I/O, Fm+ capable
I/O structure
I/O, with USB function supplied by VDDUSB
I/O, with Analog switch function supplied by VDDA
I/O supplied only by VDDIO2
I/O, USB Type-C PD capable
_d
I/O, USB Type-C PD dead battery function
Notes
Alternate
Unless otherwise specified by a note, all I/Os are set as analog inputs during and after reset.
Functions selected through GPIOx_AFR registers
functions
Pin
functions
Additional
functions
Functions directly selected/enabled through peripheral registers
1. The related I/O structures in Table 21 are: FT_f, FT_fa.
2. The related I/O structures in Table 21 are: FT_u.
3. The related I/O structures in Table 21 are: FT_a, FT_fa, TT_a.
4. The analog switch for the TSC function is supplied by VDD
.
5. The related I/O structures in Table 21 are: FT_s, FT_fs.
Table 21. STM32L552xx pin definitions
STM32L552xx
Pin Number
STM32L552xxxxP
STM32L552xxxxQ
Additional
functions
Alternate functions
TRACECK, TIM3_ETR,
SAI1_CK1,
TSC_G7_IO1,
FMC_A23,
SAI1_MCLK_A,
EVENTOUT
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
1
2
3
B3
A2
B2
1
2
3
-
-
-
-
-
-
-
-
-
1
2
3
B3
A2
B2
1
2
3
PE2
PE3
PE4
I/O FT
I/O FT
I/O FT
-
-
-
-
-
-
TRACED0, TIM3_CH1,
OCTOSPI1_DQS,
TSC_G7_IO2,
FMC_A19,
SAI1_SD_B,
EVENTOUT
TRACED1, TIM3_CH2,
SAI1_D2,
DFSDM1_DATIN3,
TSC_G7_IO3,
FMC_A20, SAI1_FS_A,
EVENTOUT
TRACED2, TIM3_CH3,
SAI1_CK2,
DFSDM1_CKIN3,
TSC_G7_IO4,
FMC_A21,
-
-
-
-
-
-
4
A1
4
-
-
-
4
A1
4
PE5
I/O FT
-
-
SAI1_SCK_A,
EVENTOUT
Table 21. STM32L552xx pin definitions (continued)
Pin Number
STM32L552xxxxP
STM32L552xxxxQ
STM32L552xx
Additional
functions
Alternate functions
TRACED3, TIM3_CH4,
SAI1_D1, FMC_A22,
SAI1_SD_A,
WKUP3,
TAMP_IN3/TAMP_
OUT6
-
-
-
-
-
-
5
6
C2
B1
5
6
-
-
-
5
6
C2
B1
5
6
PE6
I/O FT
-
-
EVENTOUT
1
1
1
B9
1
B9
1
1
1
VBAT
S
-
-
-
WKUP2,
RTC_TS/RTC_
OUT1,
(1)
(2)
2
2
2
B7
2
B7
7
C3
7
2
2
2
7
C3
7
PC13 I/O FT
EVENTOUT
TAMP_IN1/TAMP_
OUT2
PC14-
OSC3
I/O FT
2_IN
(1)
(2)
3
4
3
4
3
4
C9
C8
3
4
C9
C8
8
9
C1
D1
8
9
3
4
3
4
3
4
8
9
C1
D1
8
9
EVENTOUT
EVENTOUT
OSC32_IN
(PC14)
PC15-
(1)
(2)
OSC3
I/O FT
2_OUT
OSC32_OUT
(PC15)
FT
_f
I2C2_SDA, FMC_A0,
EVENTOUT
-
-
-
-
-
-
-
-
-
-
-
-
-
-
D2 10
E2 11
-
-
-
-
-
-
-
-
D2 10
E2 11
PF0
PF1
I/O
I/O
-
-
-
-
FT
_f
I2C2_SCL, FMC_A1,
EVENTOUT
Table 21. STM32L552xx pin definitions (continued)
Pin Number
STM32L552xxxxP
STM32L552xxxxQ
STM32L552xx
Additional
functions
Alternate functions
I2C2_SMBA, FMC_A2,
EVENTOUT
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
E1 12
D3 13
E3 14
F2 15
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
E1 12
D3 13
E3 14
F2 15
PF2
PF3
PF4
PF5
I/O FT
I/O FT
I/O FT
I/O FT
-
-
-
-
-
-
-
-
LPTIM3_IN1, FMC_A3,
EVENTOUT
LPTIM3_ETR,
FMC_A4, EVENTOUT
LPTIM3_OUT,
FMC_A5, EVENTOUT
-
-
-
-
-
-
-
-
-
-
-
-
10 F6 16
11 F7 17
-
-
-
-
-
-
10 F6 16
11 F7 17
VSS
VDD
S
S
-
-
-
-
-
-
-
-
TIM5_ETR, TIM5_CH1,
OCTOSPI1_IO3,
SAI1_SD_B,
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
18
19
20
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
18
19
20
PF6
PF7
PF8
I/O FT
I/O FT
I/O FT
-
-
-
-
EVENTOUT
TIM5_CH2,
OCTOSPI1_IO2,
SAI1_MCLK_B,
EVENTOUT
TAMP_IN6/TAMP_
OUT3
TIM5_CH3,
OCTOSPI1_IO0,
SAI1_SCK_B,
EVENTOUT
TAMP_IN7/TAMP_
OUT8
Table 21. STM32L552xx pin definitions (continued)
Pin Number
STM32L552xxxxP
STM32L552xxxxQ
STM32L552xx
Additional
functions
Alternate functions
TIM5_CH4,
OCTOSPI1_IO1,
SAI1_FS_B,
TIM15_CH1,
EVENTOUT
TAMP_IN8/TAMP_
OUT7
-
-
-
-
-
-
-
-
-
-
-
21
22
-
-
-
-
-
-
-
21
PF9
I/O FT
-
OCTOSPI1_CLK,
DFSDM1_CKOUT,
SAI1_D3, TIM15_CH2,
EVENTOUT
-
-
-
-
-
-
-
-
22 PF10 I/O FT
-
-
-
PH0-
OSC_I
5
5
5
D9
5
D9 12 F1 23
5
5
5
12 F1 23
I/O FT
EVENTOUT
OSC_IN
N
(PH0)
PH1-
OSC_
OUT
6
7
6
7
6
7
D8
E9
6
7
D8 13 G1 24
E9 14 G2 25
6
7
6
7
6
7
13 G1 24
I/O FT
RS
-
-
EVENTOUT
-
OSC_OUT
-
(PH1)
14 G2 25 NRST I-O
T
Table 21. STM32L552xx pin definitions (continued)
Pin Number
STM32L552xxxxP
STM32L552xxxxQ
STM32L552xx
Additional
functions
Alternate functions
LPTIM1_IN1,
OCTOSPI1_IO7,
I2C3_SCL,
FT
_fa
LPUART1_RX,
SDMMC1_D5,
SAI2_FS_A,
-
-
8
E7
8
E7 15 H2 26
-
-
8
15 H2 26
PC0
I/O
-
ADC12_IN1
LPTIM2_IN1,
EVENTOUT
TRACED0,
LPTIM1_OUT,
SPI2_MOSI,
I2C3_SDA,
LPUART1_TX,
OCTOSPI1_IO4,
SAI1_SD_A,
EVENTOUT
FT
_fa
-
-
-
-
9
F8
9
F8 16 G3 27
-
-
-
-
9
16 G3 27
PC1
PC2
I/O
I/O
-
-
ADC12_IN2
ADC12_IN3
LPTIM1_IN2,
SPI2_MISO,
DFSDM1_CKOUT,
OCTOSPI1_IO5,
EVENTOUT
FT
_a
10 F7 10 F7 17 F3 28
10 17 F3 28
Table 21. STM32L552xx pin definitions (continued)
Pin Number
STM32L552xxxxP
STM32L552xxxxQ
STM32L552xx
Additional
functions
Alternate functions
LPTIM1_ETR,
LPTIM3_OUT,
SAI1_D1, SPI2_MOSI,
OCTOSPI1_IO6,
SAI1_SD_A,
FT
_a
-
-
11 G7 11 G7 18 F4 29
-
-
11
18 F4 29
PC3
I/O
-
ADC12_IN4
LPTIM2_ETR,
EVENTOUT
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
19
20
-
-
30 VSSA
31 VREF-
S
S
-
-
-
-
-
-
-
-
VSSA/
VREF-
8
8
12 G9 12 G9 19 H1 30
8
8
12
-
H1
-
S
-
-
-
-
VREF
+
-
-
-
-
-
-
G8
H9
-
-
G8 20 J1 31
H9 21 K1 32
-
-
-
-
-
-
21 J1 32
S
S
-
-
-
-
-
-
VREFBUF_OUT
-
22 K1 33 VDDA
VDDA/
9
9
13
-
13
-
-
-
-
9
9
13
-
-
-
VREF
+
S
-
-
-
-
Table 21. STM32L552xx pin definitions (continued)
Pin Number
STM32L552xxxxP
STM32L552xxxxQ
STM32L552xx
Additional
functions
Alternate functions
TIM2_CH1, TIM5_CH1,
TIM8_ETR,
USART2_CTS/USART
2_NSS, UART4_TX,
SAI1_EXTCLK,
TIM2_ETR,
OPAMP1_VINP,
ADC12_IN5,
WKUP1,
TAMP_IN2/TAMP_
OUT1
FT
_a
10
10 14 H8 14 H8 22 J2 33 10 10 14 23 J2 34
PA0
I/O
-
-
EVENTOUT
OPAM
P1_VI
NM
-
-
-
-
-
-
-
H3
-
-
-
-
-
H3
-
I
TT
-
-
TIM2_CH2, TIM5_CH2,
I2C1_SMBA,
SPI1_SCK,
OPAMP1_VINM,
ADC12_IN6,
TAMP_IN5/TAMP_
OUT4
FT
_a
USART2_RTS/USART
2_DE, UART4_RX,
OCTOSPI1_DQS,
TIM15_CH1N,
11
11
15 F6 15 F6 23 G4 34
11
11
15 24 G4 35
PA1
I/O
-
EVENTOUT
Table 21. STM32L552xx pin definitions (continued)
Pin Number
STM32L552xxxxP
STM32L552xxxxQ
STM32L552xx
Additional
functions
Alternate functions
TIM2_CH3, TIM5_CH3,
USART2_TX,
LPUART1_TX,
OCTOSPI1_NCS,
UCPD1_FRSTX1,
SAI2_EXTCLK,
TIM15_CH1,
ADC12_IN7,
WKUP4/LSCO,
COMP1_INP
FT
_a
12
12 16 G6 16 G6 24 K2 35 12 12 16 25 K2 36
PA2
PA3
I/O
-
EVENTOUT
TIM2_CH4, TIM5_CH4,
SAI1_CK1,
USART2_RX,
TT
_a
LPUART1_RX,
OCTOSPI1_CLK,
SAI1_MCLK_A,
TIM15_CH2,
OPAMP1_VOUT,
ADC12_IN8
13
13 17 F5 17 F5 25 L1 36 13 13 17 26 L1 37
I/O
-
EVENTOUT
-
-
-
-
18 H2 18 H2 26 G7 37
19 19 27 G6 38
-
-
-
-
18 27 G7 38
19 28 G6 39
VSS
VDD
S
S
-
-
-
-
-
-
-
-
-
-
OCTOSPI1_NCS,
SPI1_NSS, SPI3_NSS,
USART2_CK,
TT
_a
ADC12_IN9,
DAC1_OUT1
14
14 20 H7 20 H7 28 L3 39 14 14 20 29 L3 40
PA4
I/O
-
SAI1_FS_B,
LPTIM2_OUT,
EVENTOUT
Table 21. STM32L552xx pin definitions (continued)
Pin Number
STM32L552xxxxP
STM32L552xxxxQ
STM32L552xx
Additional
functions
Alternate functions
TIM2_CH1, TIM2_ETR,
TIM8_CH1N,
TT
_a
ADC12_IN10,
DAC1_OUT2
15
15 21 H6 21 H6 29 M1 40 15 15 21 30 M1 41
PA5
PA6
I/O
-
SPI1_SCK,
LPTIM2_ETR,
EVENTOUT
TIM1_BKIN,
TIM3_CH1,
TIM8_BKIN,
SPI1_MISO,
FT
_a
USART3_CTS/USART
3_NSS,
OPAMP2_VINP,
ADC12_IN11
16
16 22 G5 22 G5 30 L2 41 16 16 22 31 L2 42
I/O
-
-
LPUART1_CTS,
OCTOSPI1_IO3,
TIM16_CH1,
EVENTOUT
OPAM
P2_VI
NM
-
-
-
-
-
-
-
M2
-
-
-
-
-
M2
-
I
TT
-
-
Table 21. STM32L552xx pin definitions (continued)
Pin Number
STM32L552xxxxP
STM32L552xxxxQ
STM32L552xx
Additional
functions
Alternate functions
TIM1_CH1N,
TIM3_CH2,
TIM8_CH1N,
I2C3_SCL,
SPI1_MOSI,
OCTOSPI1_IO2,
TIM17_CH1,
EVENTOUT
FT
_fa
OPAMP2_VINM,
ADC12_IN12
17
17 23 J7 23 J7 31 K3 42 17 17 23 32 K3 43
PA7
I/O
-
USART3_TX,
OCTOSPI1_IO7,
EVENTOUT
FT
_a
COMP1_INM,
ADC12_IN13
-
-
-
-
24 G4
-
-
G4
-
-
-
M3
J3
-
-
-
-
-
-
24 33 M3 44
PC4
PC5
I/O
I/O
-
-
ADC12_IN14,
WKUP5,
TAMP_IN4/TAMP_
OUT5,
SAI1_D3,
USART3_RX,
EVENTOUT
FT
_a
-
-
25 34 J3 45
COMP1_INP
TIM1_CH2N,
TIM3_CH3,
TIM8_CH2N,
SPI1_NSS,
TT
_a
OPAMP2_VOUT,
ADC12_IN15
18
18 25 J6 24 J6 32 M4 43 18 18 26 35 M4 46
PB0
I/O
-
USART3_CK,
OCTOSPI1_IO1,
COMP1_OUT,
SAI1_EXTCLK,
EVENTOUT
Table 21. STM32L552xx pin definitions (continued)
Pin Number
STM32L552xxxxP
STM32L552xxxxQ
STM32L552xx
Additional
functions
Alternate functions
TIM1_CH3N,
TIM3_CH4,
TIM8_CH3N,
DFSDM1_DATIN0,
USART3_RTS/USART
3_DE,
LPUART1_RTS/LPUA
RT1_DE,
FT
_a
COMP1_INM,
ADC12_IN16
19
19 26 H5 25 H5 33 L4 44 19 19 27 36 L4 47
PB1
I/O
-
OCTOSPI1_IO0,
LPTIM2_IN1,
EVENTOUT
LPTIM1_OUT,
I2C3_SMBA,
FT
_a
DFSDM1_CKIN0,
OCTOSPI1_DQS,
UCPD1_FRSTX1,
EVENTOUT
RTC_OUT2,
COMP1_INP
20
-
20 27 J5 26 J5 34 K4 45 20 20 28 37 K4 48
PB2
I/O
-
-
OCTOSPI1_NCLK,
EVENTOUT
-
-
-
-
-
-
K5 46
L5 47
-
-
-
-
K5 49
PF11 I/O FT
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
L5 50 PF12 I/O FT
-
-
-
FMC_A6, EVENTOUT
-
-
-
J9
J8
J9
J8
-
-
48
49
-
-
51
52
VSS
VDD
S
S
-
-
-
-
I2C4_SMBA, FMC_A7,
EVENTOUT
-
-
-
-
-
-
-
M5 50
-
-
-
-
M5 53 PF13 I/O FT
-
-
Table 21. STM32L552xx pin definitions (continued)
Pin Number
STM32L552xxxxP
STM32L552xxxxQ
STM32L552xx
Additional
functions
Alternate functions
I2C4_SCL,
TSC_G8_IO1,
FMC_A8, EVENTOUT
FT
_f
-
-
-
-
-
-
-
-
-
-
-
-
-
-
J5 51
L6 52
-
-
-
-
-
-
-
-
J5 54 PF14 I/O
L6 55 PF15 I/O
-
-
-
-
I2C4_SDA,
TSC_G8_IO2,
FMC_A9, EVENTOUT
FT
_f
TSC_G8_IO3,
FMC_A10, EVENTOUT
-
-
-
-
-
-
-
-
-
-
-
-
-
-
M6 53
K6 54
-
-
-
-
-
-
-
-
M6 56
K6 57
PG0 I/O FT
PG1 I/O FT
-
-
-
-
TSC_G8_IO4,
FMC_A11, EVENTOUT
TIM1_ETR,
DFSDM1_DATIN2,
FMC_D4, SAI1_SD_B,
EVENTOUT
-
-
-
-
-
-
-
-
-
-
-
-
35 K7 55
-
-
-
-
-
-
38 K7 58
PE7
PE8
I/O FT
I/O FT
-
-
-
-
TIM1_CH1N,
DFSDM1_CKIN2,
FMC_D5,
36 J6 56
39 J6 59
SAI1_SCK_B,
EVENTOUT
TIM1_CH1,
DFSDM1_CKOUT,
OCTOSPI1_NCLK,
FMC_D6, SAI1_FS_B,
EVENTOUT
-
-
-
-
-
-
37 M7 57
-
-
-
40 M7 60
PE9
I/O FT
-
-
Table 21. STM32L552xx pin definitions (continued)
Pin Number
STM32L552xxxxP
STM32L552xxxxQ
STM32L552xx
Additional
functions
Alternate functions
-
-
-
-
-
-
-
-
-
-
-
-
-
58
-
-
-
-
-
-
-
-
L10 61
J4 62
VSS
VDD
S
S
-
-
-
-
-
-
-
-
H1
H1
J4 59
TIM1_CH2N,
TSC_G5_IO1,
OCTOSPI1_CLK,
FMC_D7,
-
-
-
-
-
-
38 J7 60
-
-
-
41 J7 63 PE10 I/O FT
-
-
SAI1_MCLK_B,
EVENTOUT
TIM1_CH2,
TSC_G5_IO2,
OCTOSPI1_NCS,
FMC_D8, EVENTOUT
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
39 L7 61
40 J8 62
41 M8 63
-
-
-
-
-
-
-
-
-
42 L7 64 PE11 I/O FT
43 J8 65 PE12 I/O FT
44 M8 66 PE13 I/O FT
-
-
-
-
-
-
TIM1_CH3N,
SPI1_NSS,
TSC_G5_IO3,
OCTOSPI1_IO0,
FMC_D9, EVENTOUT
TIM1_CH3, SPI1_SCK,
TSC_G5_IO4,
J4
OCTOSPI1_IO1,
FMC_D10, EVENTOUT
Table 21. STM32L552xx pin definitions (continued)
Pin Number
STM32L552xxxxP
STM32L552xxxxQ
STM32L552xx
Additional
functions
Alternate functions
TIM1_CH4,
TIM1_BKIN2,
-
-
-
-
-
-
H4
H3
-
-
-
-
42 K8 64
-
-
-
-
-
-
45 K8 67 PE14 I/O FT
-
-
SPI1_MISO,
OCTOSPI1_IO2,
FMC_D11, EVENTOUT
-
-
TIM1_BKIN,
SPI1_MOSI,
OCTOSPI1_IO3,
FMC_D12, EVENTOUT
43 L8 65
46 L8 68 PE15 I/O FT
TIM2_CH3,
LPTIM3_OUT,
I2C4_SCL, I2C2_SCL,
SPI2_SCK,
USART3_TX,
LPUART1_RX,
TSC_SYNC,
FT
_f
21
21 28 J3 27 J4 44 K9 66 21 21 29 47 K9 69 PB10 I/O
-
-
OCTOSPI1_CLK,
COMP1_OUT,
SAI1_SCK_A,
EVENTOUT
Table 21. STM32L552xx pin definitions (continued)
Pin Number
STM32L552xxxxP
STM32L552xxxxQ
STM32L552xx
Additional
functions
Alternate functions
TIM2_CH4, I2C4_SDA,
I2C2_SDA,
USART3_RX,
FT
_f
-
-
29 J2
-
H4 45 L9 67 22 22 30 48 L9 70 PB11 I/O
-
LPUART1_TX,
OCTOSPI1_NCS,
COMP2_OUT,
EVENTOUT
-
VDDS
MPS
-
-
-
-
-
-
-
-
-
-
-
-
28 J3 46 M9 68
M1
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
S
S
S
-
-
-
-
-
-
-
-
-
-
-
-
VLXS
MPS
29 H3 47
69
0
VSSS
MPS
30 J2 48 L10 70
VDD12
_1
22
23
22 30 J1
-
-
-
-
-
S
S
-
-
-
-
-
-
-
-
23 31 B2 31 B2 49 E9 71 23 23 31 49 E9 71
32 J1 50 M11 72
24 32 A1 33 A1 51 D4 73 24 24 32 50 D4 72
VSS
V15S
MPS_
1
-
-
-
-
-
-
-
-
-
-
S
S
-
-
-
-
-
-
-
-
24
VDD
Table 21. STM32L552xx pin definitions (continued)
Pin Number
STM32L552xxxxP
STM32L552xxxxQ
STM32L552xx
Additional
functions
Alternate functions
TIM1_BKIN,
I2C2_SMBA,
SPI2_NSS,
DFSDM1_DATIN1,
USART3_CK,
LPUART1_RTS/LPUA
RT1_DE,
25
25 33 G2
-
G2
-
L11
-
25 25 33 51 L11 73 PB12 I/O FT
-
-
TSC_G1_IO1,
OCTOSPI1_NCLK,
SAI2_FS_A,
TIM15_BKIN,
EVENTOUT
TIM1_CH1N,
LPTIM3_IN1,
I2C2_SCL, SPI2_SCK,
DFSDM1_CKIN1,
USART3_CTS/USART
3_NSS,
FT
_f
26
26 34 F2 34 F2 52 K10 74 26 26 34 52 K10 74 PB13 I/O
-
-
LPUART1_CTS,
TSC_G1_IO2,
UCPD1_FRSTX2,
SAI2_SCK_A,
TIM15_CH1N,
EVENTOUT
Table 21. STM32L552xx pin definitions (continued)
Pin Number
STM32L552xxxxP
STM32L552xxxxQ
STM32L552xx
Additional
functions
Alternate functions
TIM1_CH2N,
LPTIM3_ETR,
TIM8_CH2N,
I2C2_SDA,
SPI2_MISO,
FT
_fd
27
27 35 G1 35 G1 53 K11 75 27 27 35 53 K11 75 PB14 I/O
-
DFSDM1_DATIN2,
USART3_RTS/USART
3_DE, TSC_G1_IO3,
SAI2_MCLK_A,
TIM15_CH1,
UCPD1_DB2
EVENTOUT
RTC_REFIN,
TIM1_CH3N,
TIM8_CH3N,
SPI2_MOSI,
DFSDM1_CKIN2,
SAI2_SD_A,
TIM15_CH2,
EVENTOUT
FT
_c
28
28 36 F1 36 F1 54 K12 76 28 28 36 54 K12 76 PB15 I/O
-
UCPD1_CC2
USART3_TX,
FMC_D13, EVENTOUT
-
-
-
-
-
-
-
-
-
-
-
-
55 L12 77
56 J10 78
-
-
-
-
-
-
55 L12 77
56 J10 78
PD8
PD9
I/O FT
I/O FT
-
-
-
-
USART3_RX,
FMC_D14,
SAI2_MCLK_A,
EVENTOUT
Table 21. STM32L552xx pin definitions (continued)
Pin Number
STM32L552xxxxP
STM32L552xxxxQ
STM32L552xx
Additional
functions
Alternate functions
USART3_CK,
TSC_G6_IO1,
FMC_D15,
SAI2_SCK_A,
EVENTOUT
M1
2
M1
2
-
-
-
-
-
-
-
-
-
-
-
-
57
79
-
-
-
-
-
-
57
79 PD10 I/O FT
-
-
-
-
I2C4_SMBA,
USART3_CTS/USART
3_NSS, TSC_G6_IO2,
FMC_A16,
58 J11 80
58 J11 80 PD11 I/O FT
SAI2_SD_A,
LPTIM2_ETR,
EVENTOUT
TIM4_CH1, I2C4_SCL,
USART3_RTS/USART
3_DE, TSC_G6_IO3,
FMC_A17, SAI2_FS_A,
LPTIM2_IN1,
FT
-
-
-
-
-
-
59 J12 81
-
-
-
59 J12 81 PD12 I/O
_f
-
-
EVENTOUT
TIM4_CH2, I2C4_SDA,
TSC_G6_IO4,
FMC_A18,
FT
-
-
-
-
-
-
-
-
-
-
-
-
60 H11 82
-
-
-
-
-
-
60 H11 82 PD13 I/O
_f
-
-
-
-
LPTIM2_OUT,
EVENTOUT
-
-
83
-
-
83
VSS
S
-
-
Table 21. STM32L552xx pin definitions (continued)
Pin Number
STM32L552xxxxP
STM32L552xxxxQ
STM32L552xx
Additional
functions
Alternate functions
-
-
-
-
-
-
-
-
-
-
-
-
-
-
84
-
-
-
-
-
-
-
-
84
VDD
S
-
-
-
-
-
-
TIM4_CH3, FMC_D0,
EVENTOUT
61 H10 85
62 H12 86
61 H10 85 PD14 I/O FT
62 H12 86 PD15 I/O FT
FT
TIM4_CH4, FMC_D1,
EVENTOUT
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
SPI1_SCK, FMC_A12,
SAI2_SCK_B,
-
-
-
G10 87
G11 88
G9 89
-
-
-
G10 87
G11 88
G9 89
PG2 I/O
PG3 I/O
PG4 I/O
_s
EVENTOUT
SPI1_MISO,FMC_A13,
SAI2_FS_B,
FT
_s
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
EVENTOUT
SPI1_MOSI,FMC_A14,
SAI2_MCLK_B,
EVENTOUT
FT
_s
SPI1_NSS,
LPUART1_CTS,
FMC_A15,
SAI2_SD_B,
EVENTOUT
FT
_s
-
-
-
-
-
-
-
G12 90
-
-
-
-
G12 90
PG5 I/O
-
-
Table 21. STM32L552xx pin definitions (continued)
Pin Number
STM32L552xxxxP
STM32L552xxxxQ
STM32L552xx
Additional
functions
Alternate functions
OCTOSPI1_DQS,
I2C3_SMBA,
FT
_s
LPUART1_RTS/LPUA
RT1_DE,
-
-
-
-
-
-
-
F9 91
-
-
-
-
F9 91
PG6 I/O
-
-
UCPD1_FRSTX1,
EVENTOUT
SAI1_CK1, I2C3_SCL,
DFSDM1_CKOUT,
LPUART1_TX,
UCPD1_FRSTX2,
FMC_INT,
FT
_fs
-
-
-
-
-
-
-
-
-
-
-
-
-
-
F10 92
F12 93
-
-
-
-
-
-
-
-
F10 92
F12 93
PG7 I/O
-
-
-
-
SAI1_MCLK_A,
EVENTOUT
I2C3_SDA,
LPUART1_RX,
EVENTOUT
FT
_fs
PG8 I/O
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
94
95
-
-
-
-
-
-
-
-
-
-
94
95
VSS
S
S
-
-
-
-
-
-
-
-
VDDIO
2
Table 21. STM32L552xx pin definitions (continued)
Pin Number
STM32L552xxxxP
STM32L552xxxxQ
STM32L552xx
Additional
functions
Alternate functions
TIM3_CH1, TIM8_CH1,
DFSDM1_CKIN3,
SDMMC1_D0DIR,
TSC_G4_IO1,
-
-
37 E1 37 E1 63 F11 96
-
-
37 63 F11 96
PC6
I/O FT
-
-
SDMMC1_D6,
SAI2_MCLK_A,
EVENTOUT
TIM3_CH2, TIM8_CH2,
DFSDM1_DATIN3,
SDMMC1_D123DIR,
TSC_G4_IO2,
-
-
-
-
38 E2 38 E2 64 E10 97
-
-
-
-
38 64 E10 97
PC7
PC8
I/O FT
-
-
-
-
SDMMC1_D7,
SAI2_MCLK_B,
EVENTOUT
TIM3_CH3, TIM8_CH3,
TSC_G4_IO3,
39 F3 39 F3 65 E12 98
39 65 E12 98
I/O FT
SDMMC1_D0,
EVENTOUT
Table 21. STM32L552xx pin definitions (continued)
Pin Number
STM32L552xxxxP
STM32L552xxxxQ
STM32L552xx
Additional
functions
Alternate functions
TRACED0,
TIM8_BKIN2,
TIM3_CH4, TIM8_CH4,
TSC_G4_IO4,
USB_NOE,
FT
_f
-
-
40 G3 40 G3 66 E11 99
-
-
40 66 E11 99
PC9
I/O
-
-
SDMMC1_D1,
SAI2_EXTCLK,
EVENTOUT
MCO, TIM1_CH1,
SAI1_CK2,
FT
_f
USART1_CK,
SAI1_SCK_A,
LPTIM2_OUT,
EVENTOUT
29
30
31
29 41 F4 41 F4 67 D12 100 29 29 41 67 D12 100 PA8
I/O
I/O
-
-
-
-
-
-
TIM1_CH2, SPI2_SCK,
USART1_TX,
FT
_fu
30 42 D1 42 D1 68 D10 101 30 30 42 68 D10 101 PA9
SAI1_FS_A,
TIM15_BKIN,
EVENTOUT
TIM1_CH3, SAI1_D1,
USART1_RX,
CRS_SYNC,
FT
_fu
31 43 E3 43 E3 69 D11 102 31 31 43 69 D11 102 PA10 I/O
SAI1_SD_A,
TIM17_BKIN,
EVENTOUT
Table 21. STM32L552xx pin definitions (continued)
Pin Number
STM32L552xxxxP
STM32L552xxxxQ
STM32L552xx
Additional
functions
Alternate functions
TIM1_CH4,
TIM1_BKIN2,
FT
_u
SPI1_MISO,
32
32 44 C1 44 C1 70 C12 103 32 32 44 70 C12 103 PA11 I/O
-
-
USART1_CTS/USART
1_NSS, FDCAN1_RX,
USB_DM, EVENTOUT
TIM1_ETR,
SPI1_MOSI,
FT
_u
33
34
33 45 C2 45 C2 71 B12 104 33 33 45 71 B12 104 PA12 I/O
-
USART1_RTS/USART
1_DE, FDCAN1_TX,
USB_DP, EVENTOUT
-
-
PA13
JTMS/SWDIO,
IR_OUT, USB_NOE,
SAI1_SD_B,
(JTMS/
SWDI
O)
(3)
34 46 D2 46 D2 72 C10 105 34 34 46 72 C10 105
I/O FT
EVENTOUT
-
-
-
-
47
-
47
-
-
-
-
-
-
-
-
47
-
-
-
VSS
S
S
-
-
-
-
-
-
-
-
VDDU
SB
48 B1 48 B1 73 A12 106
48 73 A12 106
35
36
35
36
-
-
B5
A9
-
-
B5 74 H4 107 35 35
A9 75 D9 108 36 36
-
-
74 H4 107 VSS
75 D9 108 VDD
S
S
-
-
-
-
-
-
-
-
Table 21. STM32L552xx pin definitions (continued)
Pin Number
STM32L552xxxxP
STM32L552xxxxQ
STM32L552xx
Additional
functions
Alternate functions
JTCK/SWCLK,
LPTIM1_OUT,
I2C1_SMBA,
I2C4_SMBA,
SAI1_FS_B,
EVENTOUT
PA14
(JTCK/
SWCL
K)
(3)
37
38
37 49 D3 49 D3 76 C11 109 37 37 49 76 C11 109
I/O FT
-
JTDI, TIM2_CH1,
TIM2_ETR,
USART2_RX,
SPI1_NSS, SPI3_NSS,
USART3_RTS/USART
3_DE,
PA15
(JTDI)
FT
I/O
(3)
38 50 E4 50 E4 77 A11 110 38 38 50 77 A11 110
UCPD1_CC1
_c
UART4_RTS/UART4_
DE, SAI2_FS_B,
EVENTOUT
TRACED1,
LPTIM3_ETR,
SPI3_SCK,
USART3_TX,
UART4_TX,
TSC_G3_IO2,
SDMMC1_D2,
SAI2_SCK_B,
EVENTOUT
-
-
51 A2 51 A2 78 B11 111
-
-
51 78 B11 111 PC10 I/O FT
-
-
Table 21. STM32L552xx pin definitions (continued)
Pin Number
STM32L552xxxxP
STM32L552xxxxQ
STM32L552xx
Additional
functions
Alternate functions
LPTIM3_IN1,
OCTOSPI1_NCS,
SPI3_MISO,
USART3_RX,
UART4_RX,
-
-
52 C3 52 C3 79 A10 112
-
-
52 79 A10 112 PC11 I/O FT
-
-
TSC_G3_IO3,
UCPD1_FRSTX2,
SDMMC1_D3,
SAI2_MCLK_B,
EVENTOUT
TRACED3,
SPI3_MOSI,
USART3_CK,
UART5_TX,
TSC_G3_IO4,
SDMMC1_CK,
SAI2_SD_B,
EVENTOUT
-
-
53 B3 53 B3 80 B10 113
-
-
53 80 B10 113 PC12 I/O FT
-
-
SPI2_NSS,
FDCAN1_RX,
FMC_D2, EVENTOUT
-
-
-
-
-
-
-
-
-
-
-
-
81 C9 114
82 B9 115
-
-
-
-
-
-
81 C9 114 PD0
82 B9 115 PD1
I/O FT
I/O FT
-
-
-
-
SPI2_SCK,
FDCAN1_TX,
FMC_D3, EVENTOUT
Table 21. STM32L552xx pin definitions (continued)
Pin Number
STM32L552xxxxP
STM32L552xxxxQ
STM32L552xx
Additional
functions
Alternate functions
TRACED2, TIM3_ETR,
USART3_RTS/USART
3_DE, UART5_RX,
TSC_SYNC,
-
-
-
-
-
-
A3 54 A3 83 A9 116
-
-
-
-
54 83 A9 116 PD2
I/O FT
-
-
-
-
SDMMC1_CMD,
EVENTOUT
SPI2_SCK,
SPI2_MISO,
DFSDM1_DATIN0,
USART2_CTS/USART
2_NSS, FMC_CLK,
EVENTOUT
-
-
-
84 C8 117
-
84 C8 117 PD3
I/O FT
SPI2_MOSI,
DFSDM1_CKIN0,
USART2_RTS/USART
2_DE, OCTOSPI1_IO4,
FMC_NOE,
-
-
-
-
-
-
-
-
-
-
-
-
85 B8 118
-
-
-
-
-
-
85 B8 118 PD4
I/O FT
-
-
-
-
EVENTOUT
USART2_TX,
OCTOSPI1_IO5,
FMC_NWE,
86 A8 119
86 A8 119 PD5
I/O FT
EVENTOUT
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
120
121
-
-
-
-
-
-
-
-
-
-
120 VSS
121 VDD
S
S
-
-
-
-
-
-
-
-
Table 21. STM32L552xx pin definitions (continued)
Pin Number
STM32L552xxxxP
STM32L552xxxxQ
STM32L552xx
Additional
functions
Alternate functions
SAI1_D1, SPI3_MOSI,
DFSDM1_DATIN1,
USART2_RX,
-
-
-
-
-
-
87 A7 122
-
-
-
87 A7 122 PD6
I/O FT
-
OCTOSPI1_IO6,
FMC_NWAIT,
-
SAI1_SD_A,
EVENTOUT
DFSDM1_CKIN1,
USART2_CK,
-
-
-
-
-
-
-
-
-
-
88 D7 123
-
-
-
-
-
-
88 D7 123 PD7
I/O FT
-
-
OCTOSPI1_IO7,
FMC_NCE/FMC_NE1,
EVENTOUT
-
-
SPI3_SCK,
USART1_TX,
FMC_NCE/FMC_NE2,
SAI2_SCK_A,
FT
_s
D4
D4
-
-
B7 124
-
-
B7 124 PG9 I/O
TIM15_CH1N,
EVENTOUT
LPTIM1_IN1,
SPI3_MISO,
USART1_RX,
FMC_NE3,
SAI2_FS_A,
TIM15_CH1,
EVENTOUT
FT
_s
-
-
-
C4
-
C4
C7 125
-
-
-
C7 125 PG10 I/O
-
-
Table 21. STM32L552xx pin definitions (continued)
Pin Number
STM32L552xxxxP
STM32L552xxxxQ
STM32L552xx
Additional
functions
Alternate functions
LPTIM1_IN2,
OCTOSPI1_IO5,
SPI3_MOSI,
FT
_s
USART1_CTS/USART
1_NSS,
-
-
-
E5
-
E5
-
-
-
-
-
-
-
M11 126 PG11 I/O
-
-
SAI2_MCLK_A,
TIM15_CH2,
EVENTOUT
LPTIM1_ETR,
SPI3_NSS,
FT
_s
USART1_RTS/USART
1_DE, FMC_NE4,
SAI2_SD_A,
-
-
-
-
-
-
B4
A4
-
-
B4
A4
-
-
A6 126
-
-
-
-
-
-
-
-
A6 127 PG12 I/O
-
-
-
-
EVENTOUT
I2C1_SDA,
USART1_CK,
FMC_A24, EVENTOUT
M1
FT
_fs
-
-
127
128
128 PG13 I/O
0
FT
_fs
I2C1_SCL, FMC_A25,
EVENTOUT
-
-
-
-
-
-
-
-
-
D5
B8
A5
-
-
-
D5
B8
A5
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
M9 129 PG14 I/O
-
-
-
-
-
-
H9 129
D8 130
H9 130 VSS
S
S
-
-
-
-
VDDIO
D8 131
2
Table 21. STM32L552xx pin definitions (continued)
Pin Number
STM32L552xxxxP
STM32L552xxxxQ
STM32L552xx
Additional
functions
Alternate functions
LPTIM1_OUT,
I2C1_SMBA,
EVENTOUT
FT
_s
-
-
-
C5
-
C5
-
-
131
-
-
-
-
B4 132 PG15 I/O
-
-
-
JTDO/TRACESWO,
TIM2_CH2, SPI1_SCK,
SPI3_SCK,
USART1_RTS/USART
1_DE, CRS_SYNC,
SAI1_SCK_B,
PB3
(JTDO/
FT
_a
39
39 54 E6 55 E6 89 C6 132 39 39 55 89 C6 133 TRAC I/O
COMP2_INM
ESWO
)
EVENTOUT
NJTRST, TIM3_CH1,
I2C3_SDA,
SPI1_MISO,
SPI3_MISO,
PB4
USART1_CTS/USART
1_NSS,
UART5_RTS/UART5_
DE, TSC_G2_IO1,
SAI1_MCLK_B,
TIM17_BKIN,
FT
_fa
(3)
40
40 55 B6 56 B6 90 B6 133 40 40 56 90 B6 134 (NJTR I/O
ST)
COMP2_INP
EVENTOUT
Table 21. STM32L552xx pin definitions (continued)
Pin Number
STM32L552xxxxP
STM32L552xxxxQ
STM32L552xx
Additional
functions
Alternate functions
LPTIM1_IN1,
TIM3_CH2,
OCTOSPI1_NCLK,
I2C1_SMBA,
SPI1_MOSI,
SPI3_MOSI,
FT
_d
41
41 56 A6 57 A6 91 D6 134 41 41 57 91 D6 135 PB5
I/O
-
USART1_CK,
UART5_CTS/UART5_
NSS, TSC_G2_IO2,
COMP2_OUT,
SAI1_SD_B,
UCPD1_DB1
TIM16_BKIN,
EVENTOUT
LPTIM1_ETR,
TIM4_CH1,
TIM8_BKIN2,
I2C1_SCL, I2C4_SCL,
USART1_TX,
TSC_G2_IO3,
SAI1_FS_B,
FT
_fa
42
42 57 C6 58 C6 92 A5 135 42 42 58 92 A5 136 PB6
I/O
-
COMP2_INP
TIM16_CH1N,
EVENTOUT
Table 21. STM32L552xx pin definitions (continued)
Pin Number
STM32L552xxxxP
STM32L552xxxxQ
STM32L552xx
Additional
functions
Alternate functions
LPTIM1_IN2,
TIM4_CH2,
TIM8_BKIN,
I2C1_SDA, I2C4_SDA,
USART1_RX,
UART4_CTS,
TSC_G2_IO4,
FMC_NL,
FT
_fa
COMP2_INM,
PVD_IN
43
43 58 D6 59 D6 93 D5 136 43 43 59 93 D5 137 PB7
I/O
-
TIM17_CH1N,
EVENTOUT
PH3-
44
45
44 59 D7 60 D7 94 B5 137 44 44 60 94 B5 138 BOOT I/O FT
0
-
-
EVENTOUT
-
-
TIM4_CH3, SAI1_CK1,
I2C1_SCL,
DFSDM1_CKOUT,
SDMMC1_CKIN,
FDCAN1_RX,
FT
45 60 C7 61 C7 95 C5 138 45 45 61 95 C5 139 PB8
I/O
_f
SDMMC1_D4,
SAI1_MCLK_A,
TIM16_CH1,
EVENTOUT
Table 21. STM32L552xx pin definitions (continued)
Pin Number
STM32L552xxxxP
STM32L552xxxxQ
STM32L552xx
Additional
functions
Alternate functions
IR_OUT, TIM4_CH4,
SAI1_D2, I2C1_SDA,
SPI2_NSS,
SDMMC1_CDIR,
FDCAN1_TX,
SDMMC1_D5,
SAI1_FS_A,
TIM17_CH1,
EVENTOUT
FT
_f
-
-
61 A7
-
-
A7 96 A4 139 46 46 62 96 A4 140 PB9
I/O
-
-
TIM4_ETR,
FMC_NBL0,
TIM16_CH1,
EVENTOUT
-
-
-
-
-
-
-
-
-
97 C4 140
-
-
-
97 C4 141 PE0
I/O FT
I/O FT
-
-
-
-
FMC_NBL1,
TIM17_CH1,
EVENTOUT
-
-
-
-
-
-
A3 141
-
-
-
-
-
-
98 A3 142 PE1
VDD12
46
47
46 62 A8
-
-
-
-
-
S
S
-
-
-
-
-
-
-
-
_2
47 63 E8 62 E8 98 E4 142 47 47 63 99 E4 143 VSS
V15S
-
-
-
-
63 A8 99 B4 143
-
-
-
-
-
-
MPS_
2
S
S
-
-
-
-
-
-
-
-
48
48 64 F9 64 F9 100 J9 144 48 48 64 100 J9 144 VDD
1. PC13, PC14 and PC15 are supplied through the power switch. Since the switch only sinks a limited amount of current (3 mA), the use of GPIOs PC13 to PC15 in output
mode is limited:
- The speed should not exceed 2 MHz with a maximum load of 30 pF
- These GPIOs must not be used as current sources (for example to drive a LED).
2. After a Backup domain power-up, PC13, PC14 and PC15 operate as GPIOs. Their function then depends on the content of the RTC registers which are not reset by the
system reset. For details on how to manage these GPIOs, refer to the Backup domain and RTC register descriptions in the RM0438 reference manual.
3. After reset, these pins are configured as JTAG/SW debug alternate functions, and the internal pull-up on PA15, PA13, PB4 pins and the internal pull-down on PA14 pin are
activated.
(1)
Table 22. Alternate function AF0 to AF7
AF0
AF1
AF2
AF3
AF4
AF5
AF6
AF7
SPI2/SAI1/I2C4/
USART2/TIM1/8/
OCTOSPI1
SPI1/2/3/I2C4/
DFSDM1/
OCTOSPI1
Port
TIM1/2/5/8/L
PTIM1
TIM1/2/3/4/5/
LPTIM3
SPI3/I2C3/DFS
DM1/COMP1/
SYS_AF
I2C1/2/3/4
USART1/2/3
USART2_CTS_
NSS
PA0
-
-
TIM2_CH1
TIM2_CH2
TIM5_CH1
TIM5_CH2
TIM8_ETR
-
-
-
-
-
USART2_RTS_
DE
PA1
I2C1_SMBA
SPI1_SCK
PA2
PA3
PA4
PA5
-
-
-
-
TIM2_CH3
TIM2_CH4
-
TIM5_CH3
TIM5_CH4
-
-
-
-
-
-
-
-
USART2_TX
USART2_RX
USART2_CK
-
SAI1_CK1
-
-
OCTOSPI1_NCS
TIM8_CH1N
SPI1_NSS
SPI1_SCK
SPI3_NSS
-
TIM2_CH1
TIM2_ETR
USART3_CTS_
NSS
PA6
-
TIM1_BKIN
TIM3_CH1
TIM8_BKIN
-
SPI1_MISO
-
PA7
PA8
-
TIM1_CH1N
TIM1_CH1
TIM1_CH2
TIM1_CH3
TIM3_CH2
TIM8_CH1N
SAI1_CK2
SPI2_SCK
SAI1_D1
I2C3_SCL
SPI1_MOSI
-
-
-
-
-
Port
A
MCO
-
-
-
-
-
-
-
-
-
USART1_CK
USART1_TX
USART1_RX
PA9
-
-
PA10
USART1_CTS_
NSS
PA11
PA12
-
-
TIM1_CH4
TIM1_BKIN2
-
-
-
-
-
SPI1_MISO
SPI1_MOSI
-
-
USART1_RTS_
DE
TIM1_ETR
IR_OUT
PA13 JTMS/SWDIO
-
-
-
-
-
-
-
-
-
-
PA14 JTCK/SWCLK LPTIM1_OUT
PA15 JTDI TIM2_CH1
I2C1_SMBA
I2C4_SMBA
USART3_RTS_
DE
TIM2_ETR
USART2_RX
-
SPI1_NSS
SPI3_NSS
(1)
Table 22. Alternate function AF0 to AF7 (continued)
AF0
AF1
AF2
AF3
AF4
AF5
AF6
AF7
SPI2/SAI1/I2C4/
USART2/TIM1/8/
OCTOSPI1
SPI1/2/3/I2C4/
DFSDM1/
OCTOSPI1
Port
TIM1/2/5/8/L
PTIM1
TIM1/2/3/4/5/
LPTIM3
SPI3/I2C3/DFS
DM1/COMP1/
SYS_AF
I2C1/2/3/4
USART1/2/3
PB0
-
-
TIM1_CH2N
TIM1_CH3N
TIM3_CH3
TIM3_CH4
TIM8_CH2N
TIM8_CH3N
-
-
SPI1_NSS
-
-
USART3_CK
DFSDM1_DATI USART3_RTS_
PB1
PB2
PB3
PB4
N0
DE
DFSDM1_CKI
N0
-
LPTIM1_OUT
-
-
-
-
I2C3_SMBA
-
-
-
JTDO/TRACE
SWO
USART1_RTS_
DE
TIM2_CH2
-
-
SPI1_SCK
SPI1_MISO
SPI3_SCK
USART1_CTS_
NSS
NJTRST
TIM3_CH1
I2C3_SDA
SPI3_MISO
PB5
PB6
PB7
-
-
-
LPTIM1_IN1
LPTIM1_ETR
LPTIM1_IN2
TIM3_CH2
TIM4_CH1
TIM4_CH2
OCTOSPI1_NCLK
TIM8_BKIN2
I2C1_SMBA
I2C1_SCL
I2C1_SDA
SPI1_MOSI
I2C4_SCL
I2C4_SDA
SPI3_MOSI
USART1_CK
USART1_TX
USART1_RX
-
-
TIM8_BKIN
Port
B
DFSDM1_CKOU
T
PB8
-
-
TIM4_CH3
SAI1_CK1
I2C1_SCL
-
-
PB9
PB10
PB11
-
-
-
IR_OUT
TIM2_CH3
TIM2_CH4
TIM4_CH4
SAI1_D2
I2C4_SCL
I2C4_SDA
I2C1_SDA
I2C2_SCL
I2C2_SDA
SPI2_NSS
SPI2_SCK
-
-
-
-
-
LPTIM3_OUT
-
USART3_TX
USART3_RX
DFSDM1_DATI
N1
PB12
PB13
PB14
-
-
-
TIM1_BKIN
TIM1_CH1N
TIM1_CH2N
-
TIM1_BKIN
-
I2C2_SMBA
I2C2_SCL
I2C2_SDA
-
SPI2_NSS
SPI2_SCK
SPI2_MISO
SPI2_MOSI
USART3_CK
DFSDM1_CKI USART3_CTS_
N1 NSS
LPTIM3_IN1
LPTIM3_ETR
-
DFSDM1_DATI USART3_RTS_
TIM8_CH2N
TIM8_CH3N
N2
DE
DFSDM1_CKI
N2
PB15 RTC_REFIN TIM1_CH3N
-
(1)
Table 22. Alternate function AF0 to AF7 (continued)
AF0
AF1
AF2
AF3
AF4
AF5
AF6
AF7
SPI2/SAI1/I2C4/
USART2/TIM1/8/
OCTOSPI1
SPI1/2/3/I2C4/
DFSDM1/
OCTOSPI1
Port
TIM1/2/5/8/L
PTIM1
TIM1/2/3/4/5/
LPTIM3
SPI3/I2C3/DFS
DM1/COMP1/
SYS_AF
I2C1/2/3/4
USART1/2/3
PC0
-
LPTIM1_IN1
LPTIM1_OUT
-
-
OCTOSPI1_IO7
SPI2_MOSI
I2C3_SCL
I2C3_SDA
-
-
-
-
-
-
PC1
PC2
TRACED0
DFSDM1_CKO
UT
-
LPTIM1_IN2
-
-
-
SPI2_MISO
-
PC3
PC4
PC5
-
-
-
LPTIM1_ETR LPTIM3_OUT
SAI1_D1
-
-
-
-
SPI2_MOSI
-
-
-
-
-
-
-
-
-
-
USART3_TX
USART3_RX
SAI1_D3
DFSDM1_CKI
N3
PC6
PC7
-
-
-
-
TIM3_CH1
TIM3_CH2
TIM8_CH1
TIM8_CH2
-
-
-
-
-
-
Port
C
DFSDM1_DATI
N3
PC8
PC9
-
-
TIM3_CH3
TIM8_CH3
-
-
-
-
-
-
-
-
-
-
-
TRACED0
TIM8_BKIN2
TIM3_CH4
TIM8_CH4
-
-
-
PC10
PC11
PC12
PC13
PC14
PC15
TRACED1
-
-
-
-
-
-
LPTIM3_ETR
-
-
-
-
-
-
-
SPI3_SCK
USART3_TX
-
LPTIM3_IN1
OCTOSPI1_NCS
SPI3_MISO
USART3_RX
TRACED3
-
-
-
-
-
-
-
-
SPI3_MOSI
USART3_CK
-
-
-
-
-
-
-
-
-
(1)
Table 22. Alternate function AF0 to AF7 (continued)
AF0
AF1
AF2
AF3
AF4
AF5
AF6
AF7
SPI2/SAI1/I2C4/
USART2/TIM1/8/
OCTOSPI1
SPI1/2/3/I2C4/
DFSDM1/
OCTOSPI1
Port
TIM1/2/5/8/L
PTIM1
TIM1/2/3/4/5/
LPTIM3
SPI3/I2C3/DFS
DM1/COMP1/
SYS_AF
I2C1/2/3/4
USART1/2/3
PD0
-
-
-
-
-
-
-
-
-
-
SPI2_NSS
SPI2_SCK
-
-
-
-
PD1
PD2
USART3_RTS_
DE
TRACED2
-
-
-
TIM3_ETR
-
-
-
-
-
-
DFSDM1_DATI USART2_CTS_
N0 NSS
PD3
SPI2_SCK
SPI2_MISO
DFSDM1_CKI USART2_RTS_
PD4
PD5
PD6
-
-
-
-
-
-
-
-
-
-
-
-
-
SPI2_MOSI
-
N0
DE
-
-
USART2_TX
DFSDM1_DATI
N1
SAI1_D1
SPI3_MOSI
USART2_RX
USART2_CK
Port
D
DFSDM1_CKI
N1
PD7
-
-
-
-
-
-
PD8
PD9
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
USART3_TX
USART3_RX
USART3_CK
PD10
USART3_CTS_
NSS
PD11
PD12
-
-
-
-
-
-
-
I2C4_SMBA
I2C4_SCL
-
-
-
-
USART3_RTS_
DE
TIM4_CH1
PD13
PD14
PD15
-
-
-
-
-
-
TIM4_CH2
TIM4_CH3
TIM4_CH4
-
-
-
I2C4_SDA
-
-
-
-
-
-
-
-
-
-
-
(1)
Table 22. Alternate function AF0 to AF7 (continued)
AF0
AF1
AF2
AF3
AF4
AF5
AF6
AF7
SPI2/SAI1/I2C4/
USART2/TIM1/8/
OCTOSPI1
SPI1/2/3/I2C4/
DFSDM1/
OCTOSPI1
Port
TIM1/2/5/8/L
PTIM1
TIM1/2/3/4/5/
LPTIM3
SPI3/I2C3/DFS
DM1/COMP1/
SYS_AF
I2C1/2/3/4
USART1/2/3
PE0
-
-
-
-
-
TIM4_ETR
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
PE1
PE2
PE3
-
TRACECK
TRACED0
TIM3_ETR
TIM3_CH1
SAI1_CK1
OCTOSPI1_DQS
DFSDM1_DATI
N3
PE4
TRACED1
-
TIM3_CH2
SAI1_D2
-
-
-
DFSDM1_CKI
N3
PE5
PE6
PE7
TRACED2
TRACED3
-
-
TIM3_CH3
TIM3_CH4
-
SAI1_CK2
SAI1_D1
-
-
-
-
-
-
-
-
-
-
-
-
DFSDM1_DATI
N2
TIM1_ETR
Port
E
DFSDM1_CKI
N2
PE8
PE9
-
-
TIM1_CH1N
TIM1_CH1
-
-
-
-
-
-
-
-
-
-
DFSDM1_CKO
UT
PE10
PE11
PE12
PE13
PE14
PE15
-
-
-
-
-
-
TIM1_CH2N
TIM1_CH2
TIM1_CH3N
TIM1_CH3
TIM1_CH4
TIM1_BKIN
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
SPI1_NSS
SPI1_SCK
SPI1_MISO
SPI1_MOSI
-
-
TIM1_BKIN2
-
TIM1_BKIN2
TIM1_BKIN
(1)
Table 22. Alternate function AF0 to AF7 (continued)
AF0
AF1
AF2
AF3
AF4
AF5
AF6
AF7
SPI2/SAI1/I2C4/
USART2/TIM1/8/
OCTOSPI1
SPI1/2/3/I2C4/
DFSDM1/
OCTOSPI1
Port
TIM1/2/5/8/L
PTIM1
TIM1/2/3/4/5/
LPTIM3
SPI3/I2C3/DFS
DM1/COMP1/
SYS_AF
I2C1/2/3/4
USART1/2/3
PF0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
I2C2_SDA
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
PF1
PF2
PF3
PF4
PF5
PF6
PF7
PF8
PF9
-
-
I2C2_SCL
-
-
I2C2_SMBA
-
LPTIM3_IN1
LPTIM3_ETR
LPTIM3_OUT
TIM5_CH1
TIM5_CH2
TIM5_CH3
TIM5_CH4
-
-
-
-
-
-
-
-
-
TIM5_ETR
-
-
-
Port
F
DFSDM1_CKO
UT
PF10
-
-
-
OCTOSPI1_CLK
-
-
-
PF11
PF12
PF13
PF14
PF15
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
OCTOSPI1_NCLK
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
I2C4_SMBA
I2C4_SCL
I2C4_SDA
(1)
Table 22. Alternate function AF0 to AF7 (continued)
AF0
AF1
AF2
AF3
AF4
AF5
AF6
AF7
SPI2/SAI1/I2C4/
USART2/TIM1/8/
OCTOSPI1
SPI1/2/3/I2C4/
DFSDM1/
OCTOSPI1
Port
TIM1/2/5/8/L
PTIM1
TIM1/2/3/4/5/
LPTIM3
SPI3/I2C3/DFS
DM1/COMP1/
SYS_AF
I2C1/2/3/4
USART1/2/3
PG0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
PG1
PG2
PG3
PG4
PG5
PG6
-
-
-
-
-
SPI1_SCK
SPI1_MISO
SPI1_MOSI
SPI1_NSS
-
-
-
-
-
-
-
OCTOSPI1_DQS
I2C3_SMBA
DFSDM1_CKO
UT
PG7
-
-
-
SAI1_CK1
I2C3_SCL
-
-
PG8
PG9
-
-
-
-
-
-
-
-
I2C3_SDA
-
-
-
-
-
Port
G
SPI3_SCK
USART1_TX
PG1
0
-
-
-
-
-
-
LPTIM1_IN1
-
-
-
-
-
-
-
-
-
-
-
-
-
-
SPI3_MISO
USART1_RX
USART1_CTS_
NSS
PG11
LPTIM1_IN2
OCTOSPI1_IO5
-
SPI3_MOSI
PG1
2
USART1_RTS_
DE
LPTIM1_ETR
-
-
-
-
-
SPI3_NSS
PG1
3
-
I2C1_SDA
I2C1_SCL
I2C1_SMBA
-
-
-
USART1_CK
PG1
4
-
-
-
PG1
5
LPTIM1_OUT
(1)
Table 22. Alternate function AF0 to AF7 (continued)
AF0
AF1
AF2
AF3
AF4
AF5
AF6
AF7
SPI2/SAI1/I2C4/
USART2/TIM1/8/
OCTOSPI1
SPI1/2/3/I2C4/
DFSDM1/
OCTOSPI1
Port
TIM1/2/5/8/L
PTIM1
TIM1/2/3/4/5/
LPTIM3
SPI3/I2C3/DFS
DM1/COMP1/
SYS_AF
I2C1/2/3/4
USART1/2/3
Port PH0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
H
PH1
-
PH3
-
-
-
-
-
-
-
-
-
1. Refer to Table 23 for AF8 to AF15.
(1)
Table 23. Alternate function AF8 to AF15
AF8
AF9
AF10
AF11
AF12
AF13
AF14
AF15
Port
UART4/5/LPUA FDCAN1/
SDMMC1/COMP1
/2/TIM1/8/FMC
TIM2/8/15/16/17/
LPTIM2
USB/OCTOSPI1
UCPD1
SAI1/2/TIM8
EVENTOUT
RT1/SDMMC1
TSC
PA0
UART4_TX
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
SAI1_EXTCLK
TIM2_ETR
TIM15_CH1N
TIM15_CH1
TIM15_CH2
LPTIM2_OUT
LPTIM2_ETR
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
PA1
PA2
PA3
PA4
PA5
UART4_RX
OCTOSPI1_DQS
-
LPUART1_TX
OCTOSPI1_NCS UCPD1_FRSTX1
SAI2_EXTCLK
SAI1_MCLK_A
SAI1_FS_B
-
LPUART1_RX
OCTOSPI1_CLK
-
-
-
-
-
-
-
LPUART1_CTS
_NSS
PA6
-
OCTOSPI1_IO3
-
TIM1_BKIN
TIM8_BKIN
TIM16_CH1
EVENTOUT
PA7
PA8
-
-
-
-
-
-
-
-
OCTOSPI1_IO2
-
-
-
-
-
-
-
-
-
TIM17_CH1
LPTIM2_OUT
TIM15_BKIN
TIM17_BKIN
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
Port
A
-
SAI1_SCK_A
SAI1_FS_A
SAI1_SD_A
PA9
-
PA10
CRS_SYNC
FDCAN1_
RX
PA11
PA12
-
-
USB_DM
USB_DP
-
-
TIM1_BKIN2
-
-
-
-
-
EVENTOUT
EVENTOUT
FDCAN1_
TX
PA13
PA14
-
-
-
-
USB_NOE
-
-
-
-
-
SAI1_SD_B
SAI1_FS_B
-
-
EVENTOUT
EVENTOUT
UART4_RTS_D
E
PA15
-
-
-
-
SAI2_FS_B
-
EVENTOUT
(1)
Table 23. Alternate function AF8 to AF15 (continued)
AF8
AF9
AF10
AF11
AF12
AF13
AF14
AF15
Port
UART4/5/LPUA FDCAN1/
SDMMC1/COMP1
/2/TIM1/8/FMC
TIM2/8/15/16/17/
LPTIM2
USB/OCTOSPI1
UCPD1
SAI1/2/TIM8
EVENTOUT
RT1/SDMMC1
TSC
PB0
-
-
OCTOSPI1_IO1
OCTOSPI1_IO0
-
-
COMP1_OUT
-
SAI1_EXTCLK
-
-
EVENTOUT
EVENTOUT
LPUART1_RTS_
DE
PB1
-
LPTIM2_IN1
PB2
PB3
-
-
-
-
OCTOSPI1_DQS UCPD1_FRSTX1
-
-
-
-
-
EVENTOUT
EVENTOUT
CRS_SYNC
-
-
-
SAI1_SCK_B
UART5_RTS_D TSC_G2_
IO1
PB4
PB5
PB6
PB7
-
SAI1_MCLK_B
SAI1_SD_B
SAI1_FS_B
TIM8_BKIN
TIM17_BKIN
TIM16_BKIN
TIM16_CH1N
TIM17_CH1N
TIM16_CH1
TIM17_CH1
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
E
UART5_CTS_N TSC_G2_
-
-
-
-
-
-
-
-
-
-
COMP2_OUT
TIM8_BKIN2
FMC_NL
SS
IO2
TSC_G2_
IO3
-
UART4_CTS_N TSC_G2_
SS
IO4
Port
B
FDCAN1_
RX
PB8 SDMMC1_CKIN
PB9 SDMMC1_CDIR
SDMMC1_D4
SDMMC1_D5
SAI1_MCLK_A
SAI1_FS_A
FDCAN1_
TX
TSC_SY
NC
PB10
PB11
PB12
LPUART1_RX
LPUART1_TX
OCTOSPI1_CLK
OCTOSPI1_NCS
OCTOSPI1_NCLK
-
-
-
COMP1_OUT
SAI1_SCK_A
-
EVENTOUT
EVENTOUT
EVENTOUT
-
COMP2_OUT
-
-
-
LPUART1_RTS_ TSC_G1_
DE IO1
SAI2_FS_A
TIM15_BKIN
LPUART1_CTS TSC_G1_
PB13
-
UCPD1_FRSTX2
-
SAI2_SCK_A
TIM15_CH1N
EVENTOUT
_NSS
IO2
TSC_G1_
IO3
PB14
PB15
-
-
-
-
-
-
-
-
SAI2_MCLK_A
SAI2_SD_A
TIM15_CH1
TIM15_CH2
EVENTOUT
EVENTOUT
-
(1)
Table 23. Alternate function AF8 to AF15 (continued)
AF8
AF9
AF10
AF11
AF12
AF13
AF14
AF15
Port
UART4/5/LPUA FDCAN1/
SDMMC1/COMP1
/2/TIM1/8/FMC
TIM2/8/15/16/17/
LPTIM2
USB/OCTOSPI1
UCPD1
SAI1/2/TIM8
EVENTOUT
RT1/SDMMC1
TSC
PC0
LPUART1_RX
LPUART1_TX
-
-
-
-
-
SDMMC1_D5
-
SAI2_FS_A
SAI1_SD_A
LPTIM2_IN1
-
EVENTOUT
EVENTOUT
PC1
PC2
OCTOSPI1_IO4
TSC_G3_
IO1
-
-
OCTOSPI1_IO5
OCTOSPI1_IO6
-
-
-
-
-
-
EVENTOUT
EVENTOUT
TSC_G1_
IO4
PC3
SAI1_SD_A
LPTIM2_ETR
PC4
PC5
-
-
-
-
OCTOSPI1_IO7
-
-
-
-
-
-
-
-
-
EVENTOUT
EVENTOUT
SDMMC1_D0DI TSC_G4_
IO1
PC6
PC7
-
-
SDMMC1_D6
SDMMC1_D7
SDMMC1_D0
SDMMC1_D1
SDMMC1_D2
SDMMC1_D3
SDMMC1_CK
SAI2_MCLK_A
SAI2_MCLK_B
-
-
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
R
SDMMC1_D123 TSC_G4_
-
-
-
DIR
IO2
Port
C
TSC_G4_
IO3
PC8
-
-
-
-
TSC_G4_
IO4
PC9
-
USB_NOE
-
SAI2_EXTCLK
SAI2_SCK_B
SAI2_MCLK_B
SAI2_SD_B
TIM8_BKIN2
TSC_G3_
IO2
PC10
PC11
PC12
UART4_TX
UART4_RX
UART5_TX
-
-
-
-
-
-
-
TSC_G3_
IO3
UCPD1_FRSTX2
-
TSC_G3_
IO4
PC13
PC14
PC15
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
EVENTOUT
EVENTOUT
EVENTOUT
(1)
Table 23. Alternate function AF8 to AF15 (continued)
AF8
AF9
AF10
AF11
AF12
AF13
AF14
AF15
Port
UART4/5/LPUA FDCAN1/
SDMMC1/COMP1
/2/TIM1/8/FMC
TIM2/8/15/16/17/
LPTIM2
USB/OCTOSPI1
UCPD1
SAI1/2/TIM8
EVENTOUT
RT1/SDMMC1
TSC
FDCAN1_
RX
PD0
-
-
-
-
-
-
-
FMC_D2
FMC_D3
-
-
-
-
-
-
EVENTOUT
EVENTOUT
EVENTOUT
FDCAN1_
TX
PD1
PD2
-
TSC_SY
NC
UART5_RX
SDMMC1_CMD
PD3
PD4
PD5
PD6
-
-
-
-
-
-
-
-
-
-
-
-
-
FMC_CLK
FMC_NOE
FMC_NWE
FMC_NWAIT
-
-
-
-
-
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
OCTOSPI1_IO4
OCTOSPI1_IO5
OCTOSPI1_IO6
-
-
SAI1_SD_A
FMC_NCE/FMC_
NE1
PD7
-
-
OCTOSPI1_IO7
-
-
-
EVENTOUT
Port
D
PD8
PD9
-
-
-
-
-
-
-
-
FMC_D13
FMC_D14
-
-
-
EVENTOUT
EVENTOUT
SAI2_MCLK_A
TSC_G6_
IO1
PD10
PD11
PD12
PD13
-
-
-
-
-
-
-
-
-
-
-
-
FMC_D15
FMC_A16
FMC_A17
FMC_A18
SAI2_SCK_A
SAI2_SD_A
SAI2_FS_A
-
-
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
TSC_G6_
IO2
LPTIM2_ETR
LPTIM2_IN1
LPTIM2_OUT
TSC_G6_
IO3
TSC_G6_
IO4
PD14
PD15
-
-
-
-
-
-
-
-
FMC_D0
FMC_D1
-
-
-
-
EVENTOUT
EVENTOUT
(1)
Table 23. Alternate function AF8 to AF15 (continued)
AF8
AF9
AF10
AF11
AF12
AF13
AF14
AF15
Port
UART4/5/LPUA FDCAN1/
SDMMC1/COMP1
/2/TIM1/8/FMC
TIM2/8/15/16/17/
LPTIM2
USB/OCTOSPI1
UCPD1
SAI1/2/TIM8
EVENTOUT
RT1/SDMMC1
TSC
PE0
-
-
-
-
-
-
-
-
FMC_NBL0
FMC_NBL1
-
-
TIM16_CH1
TIM17_CH1
EVENTOUT
EVENTOUT
PE1
PE2
TSC_G7_
IO1
-
-
-
-
-
-
-
-
-
-
-
-
FMC_A23
FMC_A19
FMC_A20
FMC_A21
SAI1_MCLK_A
SAI1_SD_B
SAI1_FS_A
-
-
-
-
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
TSC_G7_
IO2
PE3
PE4
PE5
TSC_G7_
IO3
TSC_G7_
IO4
SAI1_SCK_A
PE6
PE7
PE8
PE9
-
-
-
-
-
-
-
-
-
-
-
-
-
FMC_A22
FMC_D4
FMC_D5
FMC_D6
SAI1_SD_A
SAI1_SD_B
SAI1_SCK_B
SAI1_FS_B
-
-
-
-
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
-
Port
E
-
OCTOSPI1_NCLK
TSC_G5_
IO1
PE10
PE11
PE12
PE13
-
-
-
-
OCTOSPI1_CLK
OCTOSPI1_NCS
OCTOSPI1_IO0
OCTOSPI1_IO1
-
-
-
-
FMC_D7
FMC_D8
FMC_D9
FMC_D10
SAI1_MCLK_B
-
-
-
-
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
TSC_G5_
IO2
-
-
-
TSC_G5_
IO3
TSC_G5_
IO4
PE14
PE15
-
-
-
-
OCTOSPI1_IO2
OCTOSPI1_IO3
-
-
FMC_D11
FMC_D12
-
-
-
-
EVENTOUT
EVENTOUT
(1)
Table 23. Alternate function AF8 to AF15 (continued)
AF8
AF9
AF10
AF11
AF12
AF13
AF14
AF15
Port
UART4/5/LPUA FDCAN1/
SDMMC1/COMP1
/2/TIM1/8/FMC
TIM2/8/15/16/17/
LPTIM2
USB/OCTOSPI1
UCPD1
SAI1/2/TIM8
EVENTOUT
RT1/SDMMC1
TSC
PF0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
FMC_A0
-
-
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
PF1
PF2
-
FMC_A1
-
-
-
FMC_A2
-
-
PF3
-
FMC_A3
-
-
PF4
-
FMC_A4
-
-
PF5
-
FMC_A5
-
-
PF6
OCTOSPI1_IO3
-
SAI1_SD_B
-
PF7
OCTOSPI1_IO2
-
SAI1_MCLK_B
-
Port
F
PF8
OCTOSPI1_IO0
-
SAI1_SCK_B
-
PF9
OCTOSPI1_IO1
-
SAI1_FS_B
TIM15_CH1
PF10
PF11
PF12
PF13
-
-
-
-
-
SAI1_D3
TIM15_CH2
-
-
-
-
-
-
-
FMC_A6
FMC_A7
TSC_G8_
IO1
PF14
PF15
-
-
-
-
-
-
FMC_A8
FMC_A9
-
-
-
-
EVENTOUT
EVENTOUT
TSC_G8_
IO2
(1)
Table 23. Alternate function AF8 to AF15 (continued)
AF8
AF9
AF10
AF11
AF12
AF13
AF14
AF15
Port
UART4/5/LPUA FDCAN1/
SDMMC1/COMP1
/2/TIM1/8/FMC
TIM2/8/15/16/17/
LPTIM2
USB/OCTOSPI1
UCPD1
SAI1/2/TIM8
EVENTOUT
RT1/SDMMC1
TSC
TSC_G8_
IO3
PG0
-
-
-
-
-
FMC_A10
FMC_A11
-
-
-
-
EVENTOUT
EVENTOUT
TSC_G8_
IO4
PG1
-
PG2
PG3
PG4
-
-
-
-
-
-
-
-
-
-
-
-
FMC_A12
FMC_A13
FMC_A14
SAI2_SCK_B
SAI2_FS_B
-
-
-
EVENTOUT
EVENTOUT
EVENTOUT
SAI2_MCLK_B
LPUART1_CTS
_NSS
PG5
PG6
-
-
-
-
-
FMC_A15
-
SAI2_SD_B
-
-
-
EVENTOUT
EVENTOUT
LPUART1_RTS_
DE
UCPD1_FRSTX1
Port
G
PG7
PG8
LPUART1_TX
LPUART1_RX
-
-
-
-
UCPD1_FRSTX2
-
FMC_INT
-
SAI1_MCLK_A
-
-
-
EVENTOUT
EVENTOUT
FMC_NCE/FMC_
NE2
PG9
-
-
-
-
SAI2_SCK_A
TIM15_CH1N
EVENTOUT
PG10
PG11
PG12
PG13
PG14
PG15
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
FMC_NE3
-
SAI2_FS_A
TIM15_CH1
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
SAI2_MCLK_A
TIM15_CH2
FMC_NE4
FMC_A24
FMC_A25
-
SAI2_SD_A
-
-
-
-
-
-
-
(1)
Table 23. Alternate function AF8 to AF15 (continued)
AF8
AF9
AF10
AF11
AF12
AF13
AF14
AF15
Port
UART4/5/LPUA FDCAN1/
SDMMC1/COMP1
/2/TIM1/8/FMC
TIM2/8/15/16/17/
LPTIM2
USB/OCTOSPI1
UCPD1
SAI1/2/TIM8
EVENTOUT
RT1/SDMMC1
TSC
PH0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
EVENTOUT
EVENTOUT
EVENTOUT
Port
H
PH1
PH3
1. Refer to Table 22 for AF0 to AF7.
Electrical characteristics
STM32L552xx
5
Electrical characteristics
5.1
Parameter conditions
Unless otherwise specified, all voltages are referenced to V
.
SS
5.1.1
Minimum and maximum values
Unless otherwise specified, the minimum and maximum values are guaranteed in the worst
conditions of ambient temperature, supply voltage and frequencies by tests in production on
100% of the devices with an ambient temperature at T = 25 °C and T = T max (given by
A
A
A
the selected temperature range).
Data based on characterization results, design simulation and/or technology characteristics
are indicated in the table footnotes and are not tested in production. Based on
characterization, the minimum and maximum values refer to sample tests and represent the
mean value plus or minus three times the standard deviation (mean ±3σ).
5.1.2
5.1.3
Typical values
Unless otherwise specified, typical data are based on T = 25 °C, V = V = 3 V. They
DDA
are given only as design guidelines and are not tested.
A
DD
Typical ADC accuracy values are determined by characterization of a batch of samples from
a standard diffusion lot over the full temperature range, where 95% of the devices have an
error less than or equal to the value indicated (mean ±2σ).
Typical curves
Unless otherwise specified, all typical curves are given only as design guidelines and are
not tested.
5.1.4
5.1.5
Loading capacitor
The loading conditions used for pin parameter measurement are shown in Figure 25.
Pin input voltage
The input voltage measurement on a pin of the device is described in Figure 26.
Figure 25. Pin loading conditions
Figure 26. Pin input voltage
MCU pin
MCU pin
C = 50 pF
VIN
MS19210V1
MS19211V1
138/340
DS12737 Rev 6
STM32L552xx
Electrical characteristics
5.1.6
Power supply scheme
Figure 27. STM32L552xx and STM32L562xx power supply overview
VBAT
Backup circuitry
(LSE, RTC,
Backup registers)
1.55 – 3.6 V
Power switch
VDD
VCORE
n x VDD
Regulator
VDDIO1
OUT
Kernel logic
(CPU, Digital
& Memories)
IO
logic
n x 100 nF
+1 x 4.7 μF
GPIOs
IN
n x VSS
VDDIO2
m x VDDIO2
VDDIO2
OUT
m x100 nF
+4.7 μF
IO
logic
GPIOs
IN
m x VSS
VDDA
VDDA
VREF
ADCs/
DACs/
10 nF
VREF+
VREF-
OPAMPs/
COMPs/
VREFBUF
+1 μF
100 nF +1 μF
VSSA
MSv62917V1
DS12737 Rev 6
139/340
307
Electrical characteristics
STM32L552xx
Figure 28. STM32L552xxxP and STM32L562xxxP power supply overview
VBAT
Backup circuitry
(LSE, RTC,
Backup registers)
1.55 – 3.6 V
Power switch
2 x VDD12
1.05 – 1.32 V
VDD
VCORE
n x VDD
Regulator
VDDIO1
OUT
Kernel logic
(CPU, Digital
& Memories)
IO
logic
n x 100 nF
+1 x 4.7 μF
GPIOs
IN
n x VSS
VDDIO2
m x VDDIO2
VDDIO2
OUT
m x100 nF
+4.7 μF
IO
logic
GPIOs
IN
m x VSS
VDDA
VDDA
VREF
ADCs/
DACs/
10 nF
VREF+
VREF-
OPAMPs/
COMPs/
VREFBUF
+1 μF
100 nF +1 μF
VSSA
MSv62918V1
Note:
If the selected package has the external SMPS option but no external SMPS is used by the
application (the embedded LDO is used instead), the VDD12 pins are kept unconnected.
140/340
DS12737 Rev 6
STM32L552xx
Electrical characteristics
Figure 29. STM32L552xxxQ and STM32L562xxxQ power supply overview
VBAT
Backup circuitry
(LSE, RTC,
Backup registers)
1.55 – 3.6 V
VDD
Power switch
VDDSMPS
VLXSMPS
SMPS
2 x V15SMPS
VSSSMPS
VDD
VCORE
n x VDD
GPIOs
Regulator
VDDIO1
OUT
Kernel logic
(CPU, Digital
& Memories)
IO
logic
n x 100 nF
+1 x 4.7 μF
IN
n x VSS
VDDIO2
m x VDDIO2
VDDIO2
OUT
m x100 nF
+4.7 μF
IO
logic
GPIOs
IN
m x VSS
VDDA
VDDA
VREF
ADCs/
DACs/
10 nF
VREF+
VREF-
OPAMPs/
COMPs/
VREFBUF
+1 μF
100 nF +1 μF
VSSA
MSv62919V1
1. Refer to Figure 3 for SMPS step down converter power supply scheme.
Note:
If the selected package has the SMPS step down converter option but the application does
not ever use the SMPS, it is recommended to set the SMPS power supply pins as follows:
VDDSMPS and VLXSMPS connected to VSS
V15SMPSconnected to VDD.
Caution:
Each power supply pair (V /V , V
/V
etc.) must be decoupled with filtering ceramic
DD SS DDA SSA
capacitors as shown above. These capacitors must be placed as close as possible to, or
below, the appropriate pins on the underside of the PCB to ensure the good functionality of
the device.
DS12737 Rev 6
141/340
307
Electrical characteristics
STM32L552xx
5.1.7
Current consumption measurement
The I
parameters given in Table 33 to Table 96 represent the total MCU consumption
DD_ALL
including the current supplying V , V
, V
, V
, V
and V
if the
DD
DDIO2
DDA
DDUSB
BAT
DDSMPS
device embeds the SMPS.
Figure 30. Current consumption measurement
IDD_VBAT
VBAT
IDD
VDD
VDDA
VDDUSB
VDDSMPS
VDDIO2
MSv62920V1
5.2
Absolute maximum ratings
Stresses above the absolute maximum ratings listed in Table 24: Voltage characteristics,
Table 25: Current characteristics and Table 26: Thermal characteristics may cause
permanent damage to the device. These are stress ratings only and functional operation of
the device at these conditions is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability. Device mission profile (application conditions)
is compliant with JEDEC JESD47 qualification standard, extended mission profiles are
available on demand.
(1)
Table 24. Voltage characteristics
Symbol
Ratings
Min
Max
Unit
External main supply voltage (including VDD
,
VDDX - VSS
V
DDA, VDDIO2, VDDUSB, VBAT, VDDSMPS
,
-0.3
4.0
VREF+
)
-0.3
-0.3
Allranges
0/1/2
V
DD12 - VSS External SMPS supply voltage
1.4
V
min (VDD, VDDA
,
Input voltage on FT_xxx pins except FT_c
pins
VDDIO2, VDDUSB,
VSS-0.3
VDDSMPS
)
+ 4.0(3)(4)
(2)
VIN
Input voltage on FT_c pins
VSS-0.3
VSS-0.3
5.5
Input voltage on any other pins
4.0
142/340
DS12737 Rev 6
STM32L552xx
Electrical characteristics
(1)
Table 24. Voltage characteristics (continued)
Symbol
Ratings
Min
Max
Unit
VREF+ - VDDA Allowed voltage difference for VREF+ > VDDA
Variations between different VDDX power
-
0.4
V
|ꢀVDDx
|
-
-
50
50
pins of the same domain
mV
Variations between all the different ground
pins(5)
|VSSx-VSS
|
1. All main power (VDD, VDDA, VDDIO2, VDDUSB, VBAT) and ground (VSS, VSSA) pins must always be
connected to the external power supply, in the permitted range.
2. VIN maximum must always be respected. Refer to Table 25: Current characteristics for the maximum
allowed injected current values.
3. This formula has to be applied only on the power supplies related to the IO structure described in the pin
definition table.
4. To sustain a voltage higher than 4 V the internal pull-up/pull-down resistors must be disabled.
5. Include VREF- pin.
Table 25. Current characteristics
Symbol
Ratings
Max
Unit
∑IVDD
∑IVSS
Total current into sum of all VDD power lines (source)(1) (2)
Total current out of sum of all VSS ground lines (sink)(1) (2)
160
160
100
100
20
IVDD(PIN) Maximum current into each VDD power pin (source)(1)
IVSS(PIN)
Maximum current out of each VSS ground pin (sink)(1)
Output current sunk by any I/O and control pin except FT_f
Output current sunk by any FT_f pin
IIO(PIN)
20
mA
Output current sourced by any I/O and control pin
Total output current sunk by sum of all I/Os and control pins(3)
Total output current sourced by sum of all I/Os and control pins(3)
20
100
100
∑IIO(PIN)
Injected current on FT_xxx, TT_xx, RST and B pins, except PA4, PA5 -5/+0(5)
(4)
IINJ(PIN)
Injected current on PA4, PA5
-5/0
∑|IINJ(PIN)
|
Total injected current (sum of all I/Os and control pins)(6)
+/-25
1. All main power (VDD, VDDA, VDDIO2, VDDUSB, VBAT) and ground (VSS, VSSA) pins must always be
connected to the external power supplies, in the permitted range.
2. Valid also for VDD12 on SMPS package.
3. This current consumption must be correctly distributed over all I/Os and control pins. The total output
current must not be sunk/sourced between two consecutive power supply pins referring to high pin count
QFP packages.
4. Positive injection (when VIN > VDDIOx) is not possible on these I/Os and does not occur for input voltages
lower than the specified maximum value.
5. A negative injection is induced by VIN < VSS. IINJ(PIN) must never be exceeded. Refer also to Table 24:
Voltage characteristics for the minimum allowed input voltage values.
6. When several inputs are submitted to a current injection, the maximum ∑|IINJ(PIN)| is the absolute sum of
the negative injected currents (instantaneous values).
DS12737 Rev 6
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307
Electrical characteristics
Symbol
STM32L552xx
Unit
Table 26. Thermal characteristics
Ratings
Value
TSTG
TJ
Storage temperature range
Maximum junction temperature
-65 to +150
150
°C
°C
5.3
Operating conditions
5.3.1
General operating conditions
Table 27. General operating conditions
Symbol
Parameter
Conditions
Min
Max
Unit
Internal AHB clock
frequency
fHCLK
-
0
0
0
110
110
110
3.6
Internal APB1 clock
frequency
fPCLK1
fPCLK2
VDD
-
-
-
MHz
Internal APB2 clock
frequency
1.71
Standard operating voltage
V
V
(1)
Supply voltage for the
VDDSMPS internal SMPS step-down
converter
1.71
VDDSMPS = VDD
3.6
(1)
Up to 110 MHz
Up to 80 MHz
1.14
1.08
1.32
1.32
VDD12
Standard operating voltage
V
V
1.05
Up to 26 MHz
1.32
(2)
At least one I/O in
PG[15:2] used
1.08
3.6
3.6
PG[15:2] I/Os supply
voltage
VDDIO2
PG[15:2] not used
ADC or COMP used
DAC or OPAMP used
VREFBUF used
0
1.62
1.8
2.4
VDDA
Analog supply voltage
3.6
V
ADC, DAC, OPAMP,
COMP, VREFBUF not
used
0
144/340
DS12737 Rev 6
STM32L552xx
Electrical characteristics
Table 27. General operating conditions (continued)
Symbol
Parameter
Conditions
Min
Max
Unit
VBAT
Backup operating voltage
-
1.55
3.6
V
USB used
3.0
0
3.6
3.6
VDDUSB USB supply voltage
V
USB not used
TT_xx I/O
FT_c I/O
-0.3
-0.3
VDDIOx+0.3
5
MIN(MIN(VDD
,
VIN
I/O input voltage
V
VDDA, VDDIO2
,
All I/O except FT_c and
TT_xx
-0.3
VDDUSB
+3.6 V,
)
5.5 V)(3)(4)
LQFP48
See Section 6.8:
Thermal
characteristics for
UFQFPN48
LQFP64
application appropriate
thermal resistance and
package. Power
dissipation is then
calculated according
ambient temperature
(TA) and maximum
junction temperature
(TJ) and selected
WLCSP81
LQFP100
UFBGA132
Power dissipation at
PD
mW
TA = 85 °C for suffix 6(5)
LQFP144
thermal resistance.
LQFP48
See Section 6.8:
Thermal
characteristics for
application appropriate
thermal resistance and
package. Power
dissipation is then
calculated according
ambient temperature
(TA) and maximum
junction temperature
(TJ) and selected
thermal resistance.
UFQFPN48
LQFP64
WLCSP81
LQFP100
UFBGA132
Power dissipation at
PD
mW
TA = 125 °C for suffix 3(5)
LQFP144
DS12737 Rev 6
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307
Electrical characteristics
Symbol
STM32L552xx
Table 27. General operating conditions (continued)
Parameter
Conditions
Min
Max
Unit
Maximum power
dissipation
–40
–40
–40
85
Ambient temperature for
the suffix 6 version
Low-power dissipation(6)
105
125
TA
TJ
°C
Maximum power
dissipation
Ambient temperature for
the suffix 3 version
Low-power dissipation(6)
–40
–40
–40
130
105
130
Suffix 6 version
Junction temperature range
°C
Suffix 3 version
1. When RESET is released functionality is guaranteed down to VBOR0 Min.
2. For Flash erase and program operation, VDD12 min must be 1.08 V.
3. This formula has to be applied only on the power supplies related to the IO structure described by the pin
definition table. Maximum I/O input voltage is the smallest value between MIN(VDD, VDDA, VDDIO2
DDUSB)+3.6 V and 5.5V.
,
V
4. For operation with voltage higher than Min (VDD, VDDA, VDDIO2, VDDUSB) +0.3 V, the internal Pull-up and
Pull-Down resistors must be disabled.
5. If TA is lower, higher PD values are allowed as long as TJ does not exceed TJmax (see Section 7.7: Thermal
characteristics).
6. In low-power dissipation state, TA can be extended to this range as long as TJ does not exceed TJmax (see
Section 7.7: Thermal characteristics).
5.3.2
SMPS step-down converter
The device embeds an SMPS step down converter which requires the external components
shown in below figure.
Figure 31. External components for SMPS step down converter
VDD
VCORE
VDDSMPS
VLXSMPS
SMPS
Regulator
L = 4.7 μH typ
C = 4.7 μF typ
2 x V15SMPS
VSSSMPS
MSv62972V2
The following table summarizes the SMPS behavior depending on the main regulator range,
VDD and consumption.
146/340
DS12737 Rev 6
STM32L552xx
Electrical characteristics
Table 28. SMPS modes summary
SMPS mode
Ranges Max AHB clock VCORE
VDD ≤ 2.05 V
VDD > 2.05 V
HP mode
Automatic Bypass mode
V15SMPS = VDD
Range 0
Range 1
Range 2
110 MHz
80 MHz
26 MHz
1.28 V
1.2 V
1.0 V
Max current consumption = 120 mA
V15SMPS = 1.6 V
HP mode
Automatic Bypass mode
Max current consumption = 80 mA
V15SMPS = 1.5 V
V15SMPS = VDD
LP mode or HP mode
Software Bypass mode(1)
V15SMPS = VDD
Max current consumption = 30 mA
V15SMPS = 1.3 V
1. There is no automatic SMPS bypass in Range 2. The user application should use PVD0 to monitor VDD supply and request
the SMPS Bypass mode.
(1)
Table 29. SMPS characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VDDSMPS SMPS power supply
V15SMPS SMPS output voltage
1.71(2)
1.55
3.6
V
Range 0
Range 1
Range 2
1.6
1.5
1.3
1.65
1.55
1.35
1.45
V
1.25
Fast startup disabled
SMPSFSTEN = 0
-
-
600
120
-
-
SMPS output slew
SR
µs/V
rate
Fast startup enabled
SMPSFSTEN = 1
1. Guaranteed by design.
2. When VDDSMPS is less than 2.05V, the SMPS bypass mode is forced by hardware in Range 0 and
Range 1. In Range 2, there is no automatic switch into SMPS bypass mode. It should be requested by
software. Refer to Table 28: SMPS modes summary.
DS12737 Rev 6
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307
Electrical characteristics
STM32L552xx
5.3.3
Operating conditions at power-up / power-down
The parameters given in Table 30 are derived from tests performed under the ambient
temperature condition summarized in Table 27.
(1)
Table 30. Operating conditions at power-up / power-down
Symbol
Parameter
Conditions
Min
Max
Unit
VDD rise time rate
0
10
0
∞
∞
∞
∞
∞
∞
∞
∞
tVDD
-
VDD fall time rate
VDDA rise time rate
VDDA fall time rate
VDDUSB rise time rate
VDDUSB fall time rate
VDDIO2 rise time rate
tVDDA
tVDDUSB
tVDDIO2
-
-
-
10
0
µs/V
10
0
VDDIO2 fall time rate
10
1. At power-up, the VDD12 voltage should not be forced externally.
5.3.4
Embedded reset and power control block characteristics
The parameters given in Table 31 are derived from tests performed under the ambient
temperature conditions summarized in Table 27: General operating conditions.
Table 31. Embedded reset and power control block characteristics
Symbol
Parameter
Conditions(1)
Min
Typ
Max
Unit
Reset temporization after
BOR0 is detected
(2)
tRSTTEMPO
VDD rising
-
250
400
μs
Rising edge
Falling edge
Rising edge
Falling edge
Rising edge
Falling edge
Rising edge
Falling edge
Rising edge
Falling edge
Rising edge
Falling edge
Rising edge
Falling edge
1.62
1.6
1.66
1.64
2.1
1.7
(2)
VBOR0
Brown-out reset threshold 0
Brown-out reset threshold 1
Brown-out reset threshold 2
Brown-out reset threshold 3
Brown-out reset threshold 4
V
V
V
V
V
V
V
1.69
2.14
2.04
2.35
2.24
2.66
2.57
2.95
2.86
2.19
2.1
2.06
1.96
2.26
2.16
2.56
2.47
2.85
2.76
2.1
VBOR1
VBOR2
VBOR3
VBOR4
VPVD0
VPVD1
2
2.31
2.20
2.61
2.52
2.90
2.81
2.15
2.05
2.31
2.20
Programmable voltage
detector threshold 0
2
2.26
2.15
2.36
2.25
PVD threshold 1
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DS12737 Rev 6
STM32L552xx
Electrical characteristics
Table 31. Embedded reset and power control block characteristics (continued)
Symbol
Parameter
Conditions(1)
Min
Typ
Max
Unit
Rising edge
Falling edge
Rising edge
Falling edge
Rising edge
Falling edge
Rising edge
Falling edge
Rising edge
Falling edge
2.41
2.31
2.56
2.47
2.69
2.59
2.85
2.75
2.92
2.84
2.46
2.36
2.61
2.52
2.74
2.64
2.91
2.81
2.98
2.90
2.51
2.41
2.66
2.57
2.79
2.69
2.96
2.86
3.04
2.96
VPVD2
PVD threshold 2
V
VPVD3
VPVD4
VPVD5
VPVD6
PVD threshold 3
PVD threshold 4
PVD threshold 5
PVD threshold 6
V
V
V
V
Hysteresis in
continuous
mode
-
20
-
Vhyst_BORH0 Hysteresis voltage of BORH0
Hysteresis voltage of BORH
mV
Hysteresis in
other mode
-
-
-
30
100
1.1
-
-
Vhyst_BOR_PVD
-
-
mV
µA
(except BORH0) and PVD
IDD
BOR(3) (except BOR0) and
1.6
(BOR_PVD)(2) PVD consumption from VDD
Rising edge
Falling edge
Rising edge
Falling edge
-
1.61
1.6
1.78
1.77
-
1.65
1.64
1.82
1.81
10
1.69
1.68
1.86
1.85
-
VDDA peripheral voltage
monitoring
VPVM3
V
V
VDDA peripheral voltage
monitoring
VPVM4
Vhyst_PVM3
Vhyst_PVM4
IDD
PVM3 hysteresis
PVM4 hysteresis
mV
mV
-
-
10
-
PVM1 and PVM2
consumption from VDD
(PVM1/PVM2)
-
-
-
-
0.2
2
-
-
µA
µA
(2)
IDD
PVM3 and PVM4
consumption from VDD
(PVM3/PVM4)
(2)
1. Continuous mode means Run/Sleep modes, or temperature sensor enable in Low-power run/Low-power
sleep modes.
2. Guaranteed by design.
3. BOR0 is enabled in all modes (except shutdown) and its consumption is therefore included in the supply
current characteristics tables.
DS12737 Rev 6
149/340
307
Electrical characteristics
STM32L552xx
5.3.5
Embedded voltage reference
The parameters given in Table 32 are derived from tests performed under the ambient
temperature and supply voltage conditions summarized in Table 27: General operating
conditions.
Table 32. Embedded internal voltage reference
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Internal reference
voltage
VREFINT
–40 °C < TA < +130 °C 1.182 1.212 1.232
V
ADC sampling time
when reading the
internal reference
voltage
(1)
tS_vrefint
-
-
-
4(2)
-
8
-
µs
µs
Start time of reference
voltage buffer when
ADC is enable
tstart_vrefint
-
-
-
12(2)
20(2)
7.5(2)
VREFINT buffer
consumption from VDD
DD(VREFINTBUF) when converted by
12.5
µA
mV
I
ADC
Internal reference
voltage spread over
∆VREFINT
VDD = 3 V
5
the temperature range
Average temperature
coefficient
TCoeff
ACoeff
–40°C < TA < +130°C
1000 hours, T = 25°C
3.0 V < VDD < 3.6 V
-
-
-
30
50(2) ppm/°C
Long term stability
300 1000(2)
ppm
Average voltage
coefficient
VDDCoeff
250 1200(2) ppm/V
VREFINT_DIV1
VREFINT_DIV2
VREFINT_DIV3
1/4 reference voltage
1/2 reference voltage
3/4 reference voltage
24
49
74
25
50
75
26
51
76
%
VREFINT
-
1. The shortest sampling time can be determined in the application by multiple iterations.
2. Guaranteed by design.
150/340
DS12737 Rev 6
STM32L552xx
Electrical characteristics
Figure 32. V
versus temperature
REFINT
V
1.235
1.23
1.225
1.22
1.215
1.21
1.205
1.2
1.195
1.19
1.185
°C
-40
-20
0
20
Mean
40
60
80
100
120
Min
Max
MSv40169V2
DS12737 Rev 6
151/340
307
Electrical characteristics
STM32L552xx
5.3.6
Supply current characteristics
The current consumption is a function of several parameters and factors such as the
operating voltage, ambient temperature, I/O pin loading, device software configuration,
operating frequencies, I/O pin switching rate, program location in memory and executed
binary code
The current consumption is measured as described in Section 5.1.7: Current consumption
measurement.
Typical and maximum current consumption
The MCU is placed under the following conditions:
•
•
•
All I/O pins are in analog input mode
All peripherals are disabled except when explicitly mentioned
The Flash memory access time is adjusted with the minimum wait states number,
depending on the f
frequency (refer to the table “Number of wait states according
HCLK
to CPU clock (HCLK) frequency” available in the RM0438 reference manual).
•
•
When the peripherals are enabled f = f
PCLK
HCLK
The voltage scaling range is adjusted to f
frequency as follows:
HCLK
–
–
–
Voltage Range 0 for 80 MHz < f
Voltage Range 1 for 26 MHz < f
<= 110 MHz
<= 80 MHz
HCLK
HCLK
Voltage Range 2 for f
<= 26 MHz
HCLK
The parameters given in Table 33 to Table 81 are derived from tests performed under
ambient temperature and supply voltage conditions summarized in Table 27: General
operating conditions.
152/340
DS12737 Rev 6
Table 33. Current consumption in Run and Low-power run modes, code with data processing
running from Flash in single Bank, ICACHE ON in 2-way
Conditions
TYP
MAX
Symbol
Parameter
Unit
Voltage
scaling
105°
C
-
fHCLK
25°C
55°C 85°C
125°C 25°C 55°C 85°C 105°C 125°C
26 MHz
16 MHz
8 MHz
4 MHz
2 MHz
1 MHz
3.20
2.05
3.54
2.38
1.45
0.99
4.47 5.80 8.10
3.31 4.62 6.92
2.38 3.68 5.97
1.91 3.22 5.50
4.38 6.84 12.12 18.82 29.63
3.24 5.69 10.95 17.63 28.39
2.33 4.77 10.02 16.68 27.42
1.14
Range 2
0.675
1.87 4.30
1.64 4.07
1.59 4.01
1.43 3.85
9.55
9.31
9.26
9.09
16.20 26.92
15.96 26.68
15.90 26.62
15.73 26.56
0.441 0.758 1.67 2.97 5.25
0.326 0.639 1.54 2.86 5.14
fHCLK = fHSE
up to 48 MHz
included,
100 KHz 0.223 0.533 1.45 2.74 5.03
Supply
current in
Run mode
IDD
bypass mode
PLL ON above
48 MHz all
peripherals
disabled
Range 0 110 MHz
80 MHz
16.7
11.4
10.3
9.20
6.97
4.73
3.62
2.51
424
17.3
11.9
10.8
9.68
7.44
5.18
4.06
2.93
779
18.7 20.5 23.7 19.07 21.53 31.38 41.23 56.59 mA
13.2 14.8 17.7 13.33 16.89 24.17 33.07 46.91
12.0 13.7 16.6 12.22 15.76 23.03 31.92 45.75
10.9 12.6 15.4 11.10 14.64 21.89 30.78 44.60
(Run)
72 MHz
64 MHz
Range 1 48 MHz
32 MHz
8.64 10.3 13.1
6.36 7.97 10.8
8.85 12.38 19.62 28.48 42.29
6.61 10.12 17.32 26.15 39.93
5.49 8.99 16.17 24.99 38.82
4.37 7.85 15.02 23.83 37.64
24 MHz
5.22 6.82
4.08 5.67
9.6
8.4
16 MHz
2 MHz
1816 3274 5719 2026 5001 12861 20164 31407
1686 3124 5588 1905 4941 11969 18559 31355
1594 3047 5499 1832 4762 11881 18519 31266
1559 3012 5469 1799 4573 11877 18469 31247
Supply
current in
Low-power
run mode
1 MHz
296
648
IDD
fHCLK = fMSI
all peripherals disabled
µA
(LPRun)
400 KHz
100 KHz
192
561
163
528
Table 34. Current consumption in Run and Low-power run modes, code with data processing
running from Flash in single Bank, ICACHE ON in 1-way
Conditions
TYP
MAX
Parame
ter
Voltag
e
Symbol
Unit
-
fHCLK
25°C
55°C
85°C 105°C 125°C 25°C
55°C
85°C
105°C
125°C
scaling
26 MHz
16 MHz
8 MHz
3.10
2.00
1.11
0.65
0.43
0.32
0.22
3.44
2.32
1.42
0.98
0.74
0.62
0.52
4.37
3.23
2.33
1.87
1.65
1.53
1.43
5.69
4.55
3.64
3.19
2.97
2.85
2.75
8.01
6.86
5.93
5.48
5.24
5.10
5.01
4.28
3.18
2.30
1.86
1.64
1.58
1.43
6.74
5.63
4.73
4.29
4.06
4.01
3.85
12.02
10.89
9.99
9.53
9.31
9.25
9.09
18.70
17.55
16.64
16.18
15.95
15.89
15.73
29.46
28.30
27.37
26.89
26.66
26.61
26.44
Range
2
4 MHz
2 MHz
fHCLK =
fHSE up to
48 MHz
1 MHz
100 KHz
Supply included,
current bypass
in Run mode PLL
mode ON above
48 MHz all
IDD
Range
0
110 MHz 16.1
16.7
18.2
20.0
23.2
18.54
22.63
30.86
40.70
56.07
mA
(Run)
80 MHz
72 MHz
64 MHz
48 MHz
32 MHz
24 MHz
16 MHz
2 MHz
11.0
10.0
8.90
6.75
4.59
3.51
2.43
416
11.5
10.5
9.38
7.21
5.03
3.94
2.85
770
12.8
11.7
10.6
8.41
6.22
5.10
3.99
1781
1659
1583
14.5
13.4
12.3
10.0
7.82
6.72
5.59
17.3
16.2
15.1
12.8
10.6
9.5
12.97
11.89
10.81
8.63
6.46
5.38
4.3
16.53
15.44
14.35
12.16
9.97
23.82
22.72
21.62
19.41
17.18
16.07
15.0
32.71
31.60
30.48
28.26
26.00
24.88
23.7
46.57
45.46
44.30
42.09
39.87
38.73
37.6
peripherals
disabled
Range
1
8.88
8.4
7.8
Supply
current
in Low-
power
run
3249 5708
3127 5575
3043 5502
2014
1899
1827
4968
4930
4765
12892
11960
11905
19856
18568
18328
31311
31264
31256
fHCLK = fMSI
all peripherals
disabled
1 MHz
291
633
IDD
µA
400 KHz
194
557
(LPRun)
100 KHz
147
519
1542
3020 5462
1795
4584
11898
18312
31238
mode
Table 35. Current consumption in Run and Low-power run modes, code with data processing
running from Flash in single Bank, ICACHE disabled
Conditions
TYP
MAX
Parame
ter
Symbol
Unit
Voltage
scaling
-
fHCLK
25°C
55°C
85°C 105°C 125°C
25°C
55°C
85°C
105°C
125°C
26 MHz
16 MHz
8 MHz
4.08
2.65
1.43
0.82
0.51
0.36
4.43
2.98
1.76
1.14
0.82
0.68
0.53
19.4
14.6
13.3
12.30
9.37
6.58
5.11
3.70
866
5.36
3.91
2.67
2.05
1.75
1.59
1.45
20.9
15.9
14.5
13.5
10.63
7.80
6.29
4.86
1890
1715
1603
6.72
5.22
3.99
3.36
3.05
2.89
2.76
22.8
17.6
16.2
15.2
12.3
9.44
7.92
6.47
3353
3168
3062
9.02
7.55
6.26
5.65
5.31
5.16
5.00
25.9
20.5
19.1
18.1
15.1
12.2
10.7
9.2
5.38
3.93
7.84
6.38
13.14
11.67
10.38
9.73
19.81
18.32
17.02
16.36
16.04
15.96
15.73
42.05
35.88
34.50
33.60
30.62
27.78
26.20
24.74
20681
18581
18580
30.60
29.09
27.77
27.11
26.78
26.70
26.47
57.42
49.75
48.37
47.45
44.47
41.68
40.09
38.61
31502
31161
31131
2.67
5.11
fHCLK =
fHSE up
to
48 MHz
included,
Range 2 4 MHz
2 MHz
2.04
4.48
1.73
4.16
9.41
1 MHz
1.65
4.08
9.33
100 KHz 0.22
1.43
3.86
9.11
Supply bypass
current mode
in Run PLL ON
IDD
Range 0 110 MHz 18.8
19.97
16.16
14.80
13.90
10.97
8.22
24.02
19.71
18.34
17.45
14.51
11.74
10.20
8.77
32.25
27.01
25.64
24.74
21.78
18.98
17.42
15.97
12721
12001
11924
mA
(Run)
mode
above
48 MHz
all
peripher
als
80 MHz
72 MHz
14.1
12.8
64 MHz 11.79
Range 1 48 MHz
8.87
6.12
4.66
3.26
511
disabled
32 MHz
24 MHz
16 MHz
2 MHz
6.70
5.28
Supply
current
in Low-
power
run
5834
5642
5505
2122
1949
1852
5256
5022
4828
fHCLK = fMSI
all peripherals
disabled
1 MHz
344
203
692
IDD
µA
(LPRun)
400 KHz
591
100 KHz
159
531
1553
3018
5468
1802
4590
11905
18301
30947
mode
Table 36. Current consumption in Run mode, code with data processing
running from Flash in single bank, ICACHE ON in 2-way and power
supplied by internal SMPS step down converter
Conditions
TYP
MAX
85°C
Symbol Parameter
Unit
Voltage
scaling
-
fHCLK
25°C
55°C
85°C
105°C 125°C
25°C
55°C
105°C 125°C
26 MHz
16 MHz
8 MHz
4 MHz
2 MHz
1 MHz
1.87
1.23
0.72
0.46
0.33
0.27
1.95
1.33
0.83
0.58
0.46
0.39
0.34
2.41
1.78
1.28
1.03
0.91
0.84
0.78
3.09
2.45
1.95
1.69
1.55
1.49
1.44
5.03
4.33
3.79
3.52
3.38
3.311
3.25
1.92
1.31
0.81
0.56
0.44
0.41
0.32
2.72
2.09
1.59
1.33
1.21
1.17
1.08
4.63
3.99
3.47
3.22
3.09
3.05
2.96
7.11
6.46
5.93
5.67
5.54
5.51
5.42
11.08
10.42
9.88
9.62
9.48
9.45
9.35
fHCLK =
fHSE up to
48 MHz
included,
bypass
mode PLL
ON above
48 MHz all
peripherals
disabled
Range 2
SMPS
LP
mode
Supply
IDD
current in
(Run)
Run mode
100 KHz 0.21
Range 0
SMPS
HP
110 MHz 11.21
11.76
12.72
13.98
17.58
11.49
13.03
16.3
20.32
26.73 mA
mode
80 MHz
72 MHz
64 MHz
48 MHz
32 MHz
24 MHz
16 MHz
7.00
6.34
5.68
4.36
3.03
2.36
1.69
7.28
6.61
5.94
4.61
3.25
2.57
1.90
8.37
7.57
6.73
5.28
3.91
3.21
2.53
9.41
8.67
7.96
6.49
4.86
4.13
3.43
11.92
11.20
10.44
8.97
7.52
6.87
6.19
4.82
3.43
2.73
2.03
8.94
8.25
7.55
6.15
4.73
4.01
3.3
11.84
11.19
10.53
9.18
7.7
15.22
14.55
13.92
12.6
20.62
19.93
19.26
17.89
16.52
15.82
15.14
fHCLK =
fHSE up to
48MHz
included,
bypass
mode PLL
ON above
48 MHz all
peripherals
disabled
Range 1
Supply
IDD
SMPS
HP
mode
current in
(Run)
Run mode
7.48
11.29
10.63
9.95
6.73
6.98
6.24
5.97
Table 37. Current consumption in Run mode, code with data processing
running from Flash in single bank, ICACHE ON in 1-way and power
supplied by internal SMPS step down converter
Conditions
TYP
MAX
Symbol
Parameter
Unit
Voltage
scaling
-
fHCLK
25°C 55°C 85°C 105°C 125°C 25°C 55°C 85°C 105°C 125°C
26 MHz 1.82
16 MHz 1.20
1.90
1.30
0.82
0.58
0.45
0.39
0.33
2.36
1.75
1.27
1.02
0.90
0.84
0.78
3.03
2.41
1.93
1.68
1.55
1.49
1.43
4.96
4.31
3.75
3.51
3.37
3.30
3.24
1.88
1.28
0.8
2.67
2.06
1.57
1.32
1.2
4.58
3.96
3.46
3.21
3.08
3.05
2.96
7.06 11.03
6.43 10.39
fHCLK = fHSE up
to 48MHz
8 MHz
4 MHz
2 MHz
1 MHz
0.70
0.45
0.33
0.26
5.92
5.67
5.54
5.51
5.42
9.87
9.61
9.48
9.45
9.35
Range 2
0.56
0.44
0.4
SMPS
LP mode
included,
IDD
Supply current in
Run mode
bypass mode
PLL ON above
48 MHz all
peripherals
disabled
(Run)
1.17
1.08
100 KHz 0.21
0.32
Range 0
110 MHz 10.80 11.38 12.35 13.61 17.20 11.18 12.71 15.98 19.99 26.39 mA
SMPS
HP mode
80 MHz 6.79
72 MHz 6.15
64 MHz 5.51
48 MHz 4.23
32 MHz 2.94
24 MHz 2.29
16 MHz 1.65
7.06 8.152 9.17 11.65 7.32
8.74 11.64 15.01 20.4
8.06 11.01 14.37 19.73
7.38 10.36 13.75 19.09
fHCLK = fHSE up
to 48 MHz
6.42
5.77
4.48
3.17
2.51
1.85
7.38
6.62
5.15
3.82
3.15
2.49
8.46 10.92 6.68
7.77 10.22 6.02
6.34 8.814 4.69
4.76 7.341 3.34
included,
Range 1
IDD
Supply current in
Run mode
bypass mode
PLL ON above
48 MHz all
peripherals
disabled
6.02
4.64
3.95
3.25
9.05 12.48 17.76
7.62 11.21 16.43
6.91 10.56 15.76
SMPS
HP mode
(Run)
4.06
3.39
6.62
5.89
2.66
1.99
6.2
9.91 15.09
Table 38. Current consumption in Run mode, code with data processing
running from Flash in single bank, ICACHE disabled and power
supplied by internal SMPS step down converter
Conditions
TYP
MAX
Symbol
Parameter
Unit
Voltage
scaling
-
fHCLK
25°C 55°C 85°C 105°C 125°C 25°C 55°C 85°C 105°C 125°C
26 MHz 2.38
16 MHz 1.57
2.44
1.66
0.99
0.67
0.50
0.41
0.34
2.91
2.11
1.45
1.11
0.94
0.86
0.78
3.60
2.79
2.11
1.77
1.60
1.52
1.43
5.55
4.68
3.97
3.59
3.42
3.33
3.24
2.43
1.64
0.98
0.65
0.48
0.44
0.32
3.23
2.43
1.76
1.41
1.24
1.2
5.15
4.34
3.65
3.3
7.63 11.61
6.8 10.77
6.11 10.06
8 MHz
4 MHz
2 MHz
1 MHz
0.89
0.54
0.37
0.29
Range 2
5.76
5.59
5.54
5.42
9.7
SMPS
LP mode
3.13
3.09
2.97
9.52
9.48
9.36
fHCLK = fHSE up
to 48 MHz
100 KHz 0.21
1.08
included,
Range 0
IDD
Supply current in
Run mode
bypass mode
PLL ON above
48 MHz all
peripherals
disabled
110 MHz 12.87 13.29 14.25 15.62 18.91 13.02 14.59 17.89 21.92 28.32 mA
SMPS
HP mode
(Run)
80 MHz 8.69
72 MHz 7.88
64 MHz 7.28
48 MHz 5.56
32 MHz 3.87
24 MHz 2.99
16 MHz 2.15
9.01 10.21 11.24 13.82 9.35 10.76 13.6 17.02 22.47
8.23
7.56
5.81
4.11
3.21
2.36
9.30 10.34 12.83 8.53
9.98 12.77 16.15 21.57
9.27 12.16 15.54 20.94
7.44 10.46 13.82 19.16
8.67
6.66
4.79
3.87
3.00
9.70 12.17 7.86
Range 1
7.79 10.30
6.1
SMPS
HP mode
5.87
4.84
3.92
8.40
7.41
6.45
4.33
3.41
2.52
5.65
4.7
8.63 12.16 17.41
7.67 11.28 16.5
6.73 10.42 15.62
3.79
Table 39. Current consumption in Run and Low-power run modes, code with data processing
running from Flash in dual bank, ICACHE ON in 2-way
Conditions
TYP
MAX
Symbol Parameter
Unit
Voltage
scaling
-
fHCLK
25°C
55°C
85°C 105°C 125°C 25°C
55°C
85°C
105°C
125°C
26 MHz
16 MHz
8 MHz
3.19
2.05
1.13
0.67
0.43
0.32
3.53
2.38
1.45
0.99
0.75
0.63
0.53
4.57
3.41
2.47
1.98
1.76
1.63
1.53
6.08
4.90
3.95
3.48
3.24
3.13
3.00
8.87
7.67
6.71
6.22
5.97
5.85
5.75
4.38
3.24
2.33
1.87
1.64
1.59
1.43
6.84
5.69
4.77
4.30
4.07
4.02
3.85
12.13
10.96
10.03
9.56
18.79
17.60
16.64
16.16
15.92
15.86
15.70
41.18
33.02
31.87
30.72
28.43
26.10
24.94
23.77
20319
18764
18426
18139
29.69
28.45
27.47
26.97
26.73
26.66
26.48
56.65
46.97
45.80
44.63
42.33
39.96
38.85
37.67
31556
31438
31274
30765
Range 2 4 MHz
2 MHz
9.32
fHCLK =
fHSE up to
48MHz
included,
bypass
mode PLL
ON above
48 MHz all
peripherals
disabled
1 MHz
9.26
100 KHz 0.22
9.10
Supply
IDD
current in
Range 0 110 MHz 16.66 17.28 18.84 20.97 24.75 19.07 23.15
80 MHz 11.39 11.91 13.30 15.22 18.68 13.33 16.88
72 MHz 10.28 10.79 12.16 14.08 17.52 12.22 15.76
31.38
24.17
23.03
21.89
19.62
17.32
16.17
15.02
12805
11887
11810
11807
mA
(Run)
Run mode
64 MHz
Range 1 48 MHz
32 MHz
9.18
6.95
4.72
3.61
2.50
9.68
7.43
5.17
4.05
2.92
11.02 12.93 16.35 11.10 14.64
8.76
6.48
5.35
4.20
10.63 14.02
8.85
6.61
5.49
4.37
2025
1907
1835
1797
12.38
10.12
8.98
8.33
7.20
6.04
3558
3435
3359
3306
11.68
10.50
9.33
24 MHz
16 MHz
7.85
2 MHz 402.64 785.95 1919
1 MHz 274.43 651.32 1775
400 KHz 184.36 568.08 1697
100 KHz 164.07 526.82 1660
6501
6367
6278
6238
4984
4958
4759
4578
Supply
fHCLK = fMSI
all peripherals disabled
IDD
current in
µA
(LPRun) Low-power
run mode
Table 40. Current consumption in Run and Low-power run modes, code with data processing
running from Flash in dual bank, ICACHE ON in 1-way
Conditions
TYP
MAX
Symbol Parameter
Unit
Voltage
scaling
-
fHCLK
25°C 55°C
85°C
105°C 125°C
25°C
55°C
85°C
105°C
125°C
26 MHz 3.10
16 MHz 1.99
3.44
2.32
1.42
0.97
0.76
0.63
0.53
4.45
3.33
2.43
1.96
1.75
1.63
1.52
5.99
4.84
8.76
7.60
4.28
3.18
2.30
1.86
1.64
1.58
1.43
18.54
12.97
11.89
10.81
8.63
6.46
5.38
4.30
6.74
5.63
12.01
10.88
9.97
18.65
17.51
16.59
16.13
15.90
15.85
15.69
40.64
32.65
31.54
30.43
28.20
25.95
24.82
23.69
29.47
28.31
27.37
26.90
26.67
26.61
26.45
56.06
46.57
45.44
44.31
42.08
39.86
38.72
37.57
8 MHz
1.10
0.65
0.43
0.31
3.93
6.67
4.73
Range 2 4 MHz
2 MHz
3.47
6.19
4.29
9.52
mA
3.24
5.97
4.06
9.29
fHCLK =
fHSE up to
48MHz
1 MHz
3.14
5.84
4.01
9.24
100 KHz 0.21
3.01
5.75
3.85
9.08
included,
bypass
mode PLL
ON above
48 MHz all
peripherals
disabled
Supply
IDD
current in
Range 0 110 MHz 16.14 16.75 18.31
80 MHz 11.03 11.54 12.91
20.43
14.83
13.73
12.62
10.41
8.19
24.12
18.22
17.10
16.00
13.77
11.47
10.36
9.21
22.62
16.52
15.44
14.35
12.16
9.97
30.83
23.79
22.69
21.59
19.38
17.16
16.04
14.93
(Run)
Run mode
72 MHz 9.96 10.46 11.81
64 MHz 8.89
Range 1 48 MHz 6.74
32 MHz 4.58
9.39
7.21
5.04
3.94
2.85
10.72
8.52
6.31
5.22
4.10
mA
24 MHz 3.50
7.07
8.87
16 MHz 2.42
5.93
7.78
395.2 772.8
2 MHz
1 MHz
1907
1775
1698
1666
3571
3418
3343
3299
6492
6339
6271
6245
2013
1907
1823
1799
4976
4922
4765
4595
12833
11903
11840
11826
20077
18462
18375
18345
31507
31382
31356
30923
8
3
289.9 641.7
Supply
current in
8
3
IDD
fHCLK = fMSI
all peripherals disabled
µA
Low-power
(LPRun)
186.6 557.5
400 KHz
100 KHz
run mode
8
3
165.5 523.3
4
3
Table 41. Current consumption in Run and Low-power run modes, code with data processing
running from Flash in dual bank, ICACHE disabled
Conditions
TYP
MAX
Symbol
Parameter
Unit
Voltage
scaling
-
fHCLK
25°C 55°C
85°C 105°C 125°C 25°C
55°C
85°C
105°C 125°C
26 MHz
16 MHz
8 MHz
4.17
2.73
1.47
4.52
3.07
1.80
5.55
4.09
2.81
2.16
1.84
1.68
1.53
7.10
5.63
4.32
3.66
3.33
3.18
3.03
9.86
8.40
7.05
6.39
6.05
5.89
5.74
5.38
3.93
2.67
2.04
1.73
1.65
1.43
7.84
6.38
13.11
11.64
10.35
9.70
19.77
18.28
16.98
16.33
16.00
15.92
15.70
42.00
35.83
34.46
33.55
30.58
27.74
26.16
24.70
30.58
29.07
27.75
27.08
26.76
26.67
26.44
57.39
49.73
48.34
47.42
44.45
41.65
40.06
38.58
5.11
Range 2 4 MHz
2 MHz
0.84 1.166
4.47
0.52
0.36
0.84
0.68
0.53
4.16
9.38
fHCLK =
fHSE up to
48MHz
1 MHz
4.08
9.30
100 KHz 0.22
3.86
9.08
included,
bypass
mode PLL
ON above
48 MHz all
peripherals
disabled
Supply
current in Run
mode
IDD
Range 0 110 MHz 17.20 17.81 19.35 21.47 25.17 19.96
80 MHz 13.93 14.47 15.86 17.80 21.23 16.17
72 MHz 12.60 13.12 14.51 16.45 19.86 14.80
64 MHz 11.82 12.34 13.73 15.65 19.05 13.90
24.02
19.70
18.34
17.45
14.51
11.74
10.20
8.77
32.20
26.96
25.59
24.69
21.73
18.93
17.37
15.92
mA
(Run)
Range 1 48 MHz 8.922 9.42
10.78 12.69 16.08 10.97
32 MHz
24 MHz
16 MHz
6.24
4.75
3.38
6.72
5.21
3.83
8.03
6.50
5.09
9.92
8.35
6.93
13.28
11.67
10.22
8.22
6.70
5.28
483.6 889.5
2 MHz
1 MHz
2022
1836
1722
1666
3671
3468
3355
3315
6622
6424
6314
6247
2109
1954
1849
1809
5283
5032
4802
4600
12566 20777 31527
11918 18517 31263
11889 18449 31148
11847 18240 30791
4
6
332.2 705.1
Supply
current in
(LPRun) Low-power
run mode
4
9
fHCLK = fMSI
all peripherals disabled
IDD
µA
206.5 588.2
400 KHz
100 KHz
9
5
156.4 527.8
1
0
Table 42. Current consumption in Run mode, code with data processing
running from Flash in dual bank, ICACHE ON in 2-way and power
supplied by internal SMPS step down converter
Conditions
TYP
MAX
Symbol
Parameter
Unit
Voltage
scaling
-
fHCLK
25°C 55°C 85°C 105°C 125°C 25°C 55°C 85°C 105°C 125°C
26 MHz 1.85
16 MHz 1.21
1.94
1.33
0.83
0.58
0.46
0.39
0.33
2.41
1.79
1.29
1.03
0.90
0.84
0.79
3.14
2.48
1.98
1.77
1.60
1.54
1.51
4.40
3.76
3.25
3.00
2.88
2.79
2.74
1.93
1.31
0.81
0.56
0.44
0.41
0.32
2.73
2.09
1.59
1.33
1.21
1.17
1.08
4.65
3.99
3.47
3.22
3.09
3.05
2.96
7.13 11.13
6.46 10.43
8 MHz
4 MHz
2 MHz
1 MHz
0.70
0.45
0.32
0.26
5.94
5.68
5.54
5.51
5.42
9.89
9.62
9.49
9.46
9.36
Range 2
SMPS
LP mode
fHCLK = fHSE up
to 48 MHz
100 KHz 0.20
Range 0
included,
IDD
Supply current in
Run mode
bypass mode
PLL ON above
48 MHz all
peripherals
disabled
SMPS
HP
mode
110 MHz 11.05 11.73 12.72 14.01 16.84 11.49 13.03 16.31 20.32 26.75 mA
(Run)
80 MHz 6.96
72 MHz 6.30
64 MHz 5.65
48 MHz 4.33
32 MHz 3.00
24 MHz 2.33
16 MHz 1.67
7.27
6.61
5.94
4.60
3.25
2.57
1.89
8.38
7.62
6.80
5.29
3.92
3.22
2.53
9.46 11.35 7.53
8.69 10.58 6.87
8.94 11.84 15.22 20.64
8.26 11.2 14.56 19.94
7.55 10.53 13.92 19.27
Range 1
8.00
6.51
4.92
4.15
3.47
9.88
8.40
6.92
6.15
5.33
6.19
4.83
3.43
2.73
2.03
SMPS
HP
mode
6.15
4.73
4.01
3.3
9.18
7.7
12.6
17.9
11.29 16.53
6.98 10.63 15.83
6.24 9.95 15.15
Table 43. Current consumption in Run mode, code with data processing
running from Flash in dual bank, ICACHE ON in 1-way and power
supplied by internal SMPS step down converter
Conditions
TYP
MAX
Symbol
Parameter
Unit
Voltage
scaling
-
fHCLK
25°C 55°C 85°C 105°C 125°C 25°C 55°C 85°C 105°C 125°C
26 MHz 1.80
16 MHz 1.18
1.89
1.30
0.82
0.58
0.46
0.39
0.33
2.37
1.76
1.27
1.02
0.90
0.84
0.78
3.07
2.46
1.98
1.72
1.59
1.53
1.48
4.35
3.72
3.23
2.98
2.86
2.79
2.73
1.88
1.28
0.8
2.67
2.06
1.57
1.32
1.2
4.58
3.96
3.46
3.21
3.08
3.05
2.96
7.06 11.04
6.43 10.39
8 MHz
4 MHz
2 MHz
1 MHz
0.69
0.44
0.32
0.26
5.92
5.67
5.54
5.51
5.42
9.87
9.61
9.48
9.45
9.36
Range 2
0.56
0.44
0.4
SMPS
LP mode
1.17
1.08
fHCLK = fHSE up
to 48 MHz
100 KHz 0.20
0.32
included,
Range 0
IDD
Supply current
in Run mode
bypass mode
PLL ON above
48 MHz all
peripherals
disabled
110 MHz 10.51 11.37 12.33 13.63 16.26 11.18 12.72 15.98
20
26.4 mA
SMPS
HP mode
(Run)
80 MHz 6.75
72 MHz 6.12
64 MHz 5.48
48 MHz 4.20
32 MHz 2.92
24 MHz 2.27
16 MHz 1.63
7.06
6.41
5.77
4.48
3.16
2.51
1.85
8.15
7.39
6.65
5.15
3.82
3.15
2.49
9.21 11.07 7.33
8.50 10.37 6.68
8.74 11.64 15.01 20.41
8.06 11.01 14.37 19.75
7.38 10.37 13.75 19.1
7.82
6.38
4.79
4.12
3.44
9.68
8.25
6.81
6.06
5.26
6.02
4.69
3.34
2.66
1.99
Range 1
6.02
4.64
3.95
3.25
9.06 12.48 17.77
7.62 11.21 16.44
6.91 10.56 15.76
SMPS
HP mode
6.2
9.91
15.1
Table 44. Current consumption in Run mode, code with data processing
running from Flash in dual bank, ICACHE disabled and power
supplied by internal SMPS step down converter
Conditions
TYP
MAX
Symbol
Parameter
Unit
Voltage
scaling
-
fHCLK
25°C 55°C 85°C 105°C 125°C 25°C 55°C 85°C 105°C 125°C
26 MHz 2.40
16 MHz 1.61
2.49
1.71
1.02
0.67
0.51
2.97
2.17
1.47
1.12
0.95
0.87
0.79
3.67
2.87
2.18
1.82
1.64
1.55
1.48
4.94
4.16
3.44
3.07
2.89
2.81
2.74
2.47
1.68
1
3.28
2.48
1.78
1.43
1.25
1.21
1.08
5.2
7.68 11.67
6.86 10.83
6.14 10.09
4.39
3.67
3.31
3.14
3.09
2.97
Range 2
8 MHz
4 MHz
2 MHz
0.90
0.55
0.37
SMPS
LP
mode
0.66
0.49
0.44
0.32
5.77
5.59
5.55
5.42
9.72
9.54
9.49
9.36
1 MHz 0.286 0.42
100 KHz 0.20 0.34
fHCLK = fHSE up
to 48 MHz
Range 0
included,
IDD
Supply current in bypass mode
SMPS
HP
mode
110 MHz 11.59 12.15 13.24 14.24 16.59 11.99 13.58 16.92 20.93 27.3 mA
Run mode
PLL ON above
48 MHz all
peripherals
disabled
(Run)
80 MHz 8.53
72 MHz 7.74
64 MHz 7.26
48 MHz 5.54
32 MHz 3.92
24 MHz 3.03
16 MHz 2.20
8.95 10.06 11.12 13.07 9.31
10.7 13.49 16.89 22.35
9.9 12.69 16.07 21.5
9.38 12.21 15.58 21
7.51 10.51 13.86 19.2
8.07
7.57
5.82
4.18
3.27
2.43
9.20 10.26 12.17 8.47
Range 1
8.71
6.66
4.85
3.92
3.07
9.75 11.64 7.95
SMPS
HP
mode
7.87
5.98
4.91
4.03
9.74
7.91
6.93
5.95
6.15
4.42
3.48
2.59
5.74
4.78
3.87
8.74 12.24 17.5
7.75 11.33 16.55
6.81 10.49 15.69
Table 45. Current consumption in Run and Low-power run modes,
code with data processing running from SRAM1
Conditions
TYP
MAX
Symbol Parameter
Unit
Voltage
scaling
-
fHCLK
25°C
55°C
85°C
105°C 125°C 25°C 55°C
85°C 105°C 125°C
26 MHz
16 MHz
8 MHz
3.25
2.08
1.15
0.68
0.44
0.32
0.22
3.59
2.41
1.47
1.00
0.76
0.64
0.53
17.57
12.13
10.99
9.85
7.56
5.27
4.11
4.62
3.43
2.47
1.99
1.75
1.64
1.52
19.10
13.48
12.33
11.18
8.87
6.55
5.37
4.22
1911
6.12
4.93
8.92
7.69
6.73
6.23
5.97
5.86
5.76
4.44
3.27
2.35
1.88
1.65
1.59
1.42
6.89
5.72
4.78
4.31
4.07
4.01
3.84
12.15
10.96
10.01
9.53
18.80
17.61
16.64
16.16
15.92
15.86
15.68
41.44
33.21
32.04
30.87
28.54
26.18
24.99
23.81
29.60
28.38
27.40
26.91
26.67
26.61
26.43
3.97
Range 2 4 MHz
2 MHz
3.51
3.25
9.30
fHCLK = fHSE
up to 48MHz
included,
1 MHz
3.14
9.24
100 KHz
3.03
9.06
Supply
IDD
bypass
current in
(Run)
mode PLL Range 0 110 MHz 16.99
21.22
15.38
14.22
13.07
10.74
8.40
24.94 19.40 23.45 31.63
18.76 13.57 17.11 24.35
17.62 12.42 15.96 23.19
16.43 11.28 14.81 22.04
56.82 mA
47.09
Run mode ON above 48
80 MHz 11.63
72 MHz 10.50
MHz all
peripherals
disabled
45.92
64 MHz
9.37
7.10
44.74
Range 1 48 MHz
14.10
11.70
10.54
9.34
8.99
6.70
5.55
4.41
2010
1896
1818
1423
12.51 19.71
10.20 17.38
42.40
32 MHz 4.826
40.08
24 MHz
16 MHz
3.68
2.54
7.23
9.05
7.89
16.21
15.04
38.88
2.97
6.05
37.68
2 MHz 385.23 772.80
3545
3405
3337
3286
6506
6382
6298
6267
4724 12895 21185 30901
4686 12648 20905 30715
4633 10788 18052 30448
Supply
fHCLK = fMSI
all peripherals disabled
FLASH in power-down
1 MHz 271.61 633.31 1776
400 KHz 198.95 554.43 1694
100 KHz 142.82 517.78 1638
IDD
current in
Low-power
run mode
µA
(LPRun)
3848
9073
15687 26433
Table 46. Current consumption in Run mode, code with data processing running
from SRAM1 and power supplied by internal SMPS step down converter
Conditions
TYP
MAX
Symbol
Parameter
Unit
Voltage
scaling
-
fHCLK
25°C 55°C 85°C 105°C 125°C 25°C 55°C 85°C 105°C 125°C
26 MHz 1.88
16 MHz 1.24
1.99
1.35
0.85
0.59
0.46
0.40
0.34
2.46
1.81
1.29
1.04
0.91
0.84
0.78
3.15
2.51
1.99
1.73
1.60
1.53
1.48
4.42
3.76
3.24
2.97
2.85
2.77
2.71
1.96
1.33
0.82
0.57
0.44
0.41
0.32
2.76
2.11
1.6
4.67
4.01
3.48
3.22
3.09
3.06
2.96
7.14 11.12
6.48 10.44
8 MHz
4 MHz
2 MHz
1 MHz
0.72
0.46
0.32
0.26
5.94
5.68
5.54
5.51
5.41
9.89
9.62
9.48
9.45
9.34
Range 2
1.34
1.21
1.18
1.08
SMPS
LP mode
fHCLK = fHSE up
to 48 MHz
100 KHz 0.20
included,
Range 0
IDD
Supply current bypass mode
in Run mode PLL ON above
48 MHz all
110 MHz 11.28 12.01 12.99 14.29 17.00 12.06 14.37 19.01 24.79 33.4 mA
SMPS
HP mode
(Run)
peripherals
disabled
80 MHz 7.10
72 MHz 6.44
64 MHz 5.76
48 MHz 4.42
32 MHz 3.06
24 MHz 2.38
16 MHz 1.70
7.42
6.74
6.05
4.69
3.31
2.61
1.92
8.55
7.80
6.89
5.37
3.96
3.26
2.55
9.55 11.47 8.33 10.16 13.97 18.72 26.04
8.84 10.70 7.52
9.42 13.31 18.02 25.3
8.74 12.64 17.33 24.58
7.29 11.35 15.96 23.16
8.10
6.60
4.93
4.20
3.51
9.95
8.46
6.93
6.16
5.32
6.8
Range 1
5.34
3.86
3.15
2.45
SMPS
HP mode
5.79
5.05
4.31
9.98 14.58 21.7
9.26 13.88 20.98
8.52 13.19 20.25
Table 47. Current consumption in Run and Low-power run modes, code with data processing
running from SRAM2
Conditions
TYP
MAX
Symbol
Parameter
Unit
Voltage
scaling
-
fHCLK
25°C
55°C
85°C 105°C 125°C 25°C
55°C
85°C 105°C 125°C
26 MHz
16 MHz
8 MHz
3.20
2.05
1.13
0.67
0.43
0.32
3.53
2.38
1.45
0.99
0.76
0.63
0.53
4.55
3.40
2.46
1.99
1.75
1.63
1.53
6.08
4.90
3.97
3.47
3.24
3.13
3.01
8.86
7.67
6.71
6.21
5.97
5.86
5.74
4.33
3.19
2.28
1.82
1.59
1.53
1.37
6.79
5.63
4.71
4.25
4.01
3.96
3.79
12.05
18.6
29.56
10.88 17.41 28.32
9.94
9.47
9.24
9.18
9
16.46 27.34
15.98 26.84
15.74 26.59
15.68 26.52
Range 2 4 MHz
2 MHz
fHCLK =
fHSE up to
48 MHz
included,
bypass
1 MHz
100 KHz 0.22
15.5
26.33
IDD
Supply current
Range 0 110 MHz 16.71 17.32 18.86 20.97 24.66 19.04 23.09 31.27 40.87 56.41 mA
80 MHz 11.43 11.94 13.30 15.21 18.64 13.29 16.83 24.07 32.71 46.77
in Run mode mode PLL
ON above
(Run)
48 MHz all
peripherals
72 MHz 10.32 10.82 12.16 14.07 17.48 12.17 15.71 22.94 31.55
45.6
disabled
64 MHz 9.219
9.70
7.44
5.19
4.06
2.93
11.03 12.94 16.31 11.05 14.58 21.79 30.39 44.44
Range 1 48 MHz
6.98
8.77
6.48
5.33
4.19
10.63 13.98
8.79
6.54
5.42
4.29
1946
1829
1757
1373
12.31
10.04
8.9
19.5
17.2
28.16 42.12
25.84 39.83
32 MHz 4.746
8.33
7.17
6.02
3546
3445
3339
3299
11.65
10.49
9.29
24 MHz
16 MHz
3.62
2.50
16.05 24.67 38.64
14.9 23.51 37.45
7.76
2 MHz 386.41 774.71 1901
1 MHz 276.23 635.13 1767
400 KHz 196.75 552.97 1679
100 KHz 146.57 513.87 1644
6475
6360
6278
6249
2886
2796
2749
2313
7270 11761 20360
6688 12192 20188
6961 11520 19976
5697 10033 17534
fHCLK = fMSI
in Low-power all peripherals disabled
Supply current
IDD(LPRu
n)
µA
run mode
FLASH in power-down
Table 48. Current consumption in Run mode, code with data processing
running from SRAM2 and power supplied by internal SMPS step down converter
Conditions
TYP
MAX
Symbol
Parameter
Unit
Voltage
scaling
-
fHCLK
25°C 55°C 85°C 105°C 125°C 25°C 55°C 85°C 105°C 125°C
26 MHz 1.86
16 MHz 1.22
1.96
1.33
0.83
2.43
1.79
1.28
1.03
0.90
0.84
0.78
3.12
2.50
1.99
1.74
1.60
1.54
1.49
4.43
3.75
3.24
2.99
2.86
2.79
2.73
2.22
1.61
1.11
0.86
0.74
0.71
0.62
3.49
2.87
2.37
2.12
1.99
1.96
1.87
6.48 10.14 15.89
5.83
5.32
5.07
4.94
4.9
9.48 15.21
8.95 14.64
8.69 14.36
8.56 14.22
8.52 14.18
8.43 14.07
8 MHz
0.71
Range 2
4 MHz 0.456 0.58
SMPS LP
mode
2 MHz
1 MHz
0.32
0.26
0.46
0.40
0.34
fHCLK = fHSE up
to 48 MHz
100 KHz 0.20
4.81
included,
Range 0
IDD
Supply current bypass mode
in Run mode PLL ON above
48 MHz all
110 MHz 11.04 11.78 12.75 14.05 16.87 12.16 14.52 19.77 25.94 35.47 mA
SMPS HP
mode
(Run)
peripherals
disabled
80 MHz 7.00
72 MHz 6.34
64 MHz 5.68
48 MHz 4.35
32 MHz 3.02
24 MHz 2.35
16 MHz 1.68
7.29
6.62
5.95
4.61
3.26
2.58
1.90
8.40
7.64
6.82
5.30
3.91
3.22
2.53
9.44 11.33 8.23 10.44 14.63 19.73 27.8
8.72 10.59 7.49
9.79 13.98 19.05 27.08
8.97 13.41 18.39 26.39
7.53 12.27 17.03 24.99
6.11 10.94 15.72 23.52
8.00
6.51
4.89
4.18
3.49
9.86
8.38
6.89
6.11
5.31
6.8
Range 1
5.39
3.98
3.28
2.58
SMPS HP
mode
5.4
10.17 15.11 22.8
9.42 14.54 22.09
4.68
Table 49. Typical current consumption in Run and Low-power run modes,
with different codes running from Flash, ICACHE ON (2-way)
TYP
TYP
TYP
TYP
Single
Bank
Mode
Dual
Bank
Mode
Single
Bank
Mode
Dual
Bank
Mode
Conditions
Symbol
Parameter
Unit
Unit
-
Voltage scaling
Code
25°C
25°C
25°C
25°C
Reduced code
Coremark
Dhrystone2.1
Fibonacci
3.20
3.43
3.66
3.06
2.77
11.4
12.2
13.1
10.8
9.9
3.19
3.43
3.64
3.05
2.77
11.4
12.2
13.0
10.8
9.9
123
132
141
118
106
143
153
163
135
123
152
163
174
143
131
212
224
239
214
175
123
132
140
117
106
142
153
163
135
123
152
163
173
143
131
201
207
216
192
185
Range2
fHCLK=26MHz
mA
µA/MHz
While
Reduced code
Coremark
Dhrystone2.1
Fibonacci
fHCLK=fHSE up to
48 MHZincluded,
bypass mode
PLL ON above
48 MHz all
Supply current in
Run mode
Range 1
fHCLK=80 MHz
IDD (Run)
mA
mA
µA
µA/MHz
µA/MHz
µA/MHz
peripherals
disabled
While
Reduced code
Coremark
Dhrystone2.1
Fibonacci
16.7
18.0
19.1
15.8
14.5
424
16.7
18.0
19.0
15.8
14.5
403
Range 0
fHCLK= 110 MHz
While
Reduced code
Coremark
Dhrystone2.1
Fibonacci
447
415
IDD
Supply current in fHCLK = fMSI = 2 MHz all peripherals
Low-power run disabled
477
432
(LPRun)
427
383
While
350
369
Table 50. Typical current consumption in Run mode with SMPS,
with different codes running from Flash, ICACHE ON (2-way)
TYP
TYP
TYP
TYP
Single
Bank
Mode
Dual
Bank
Mode
Single
Bank
Mode
Dual
Bank
Mode
Conditions
Unit
-
Unit
-
Symbol
Parameter
-
Voltage scaling
Code
25°C
25°C
25°C
25°C
Reduced
code
1.88
1.85
72
71
Coremark
Dhrystone2.1
Fibonacci
While
2.00
2.13
1.79
1.65
1.98
2.09
1.77
1.64
77
82
69
64
76
81
68
63
Range2, SMPS
LP
fHCLK=26 MHz
mA
mA
mA
µA/MHz
µA/MHz
µA/MHz
Reduced
code
7.0
7.0
88
87
fHCLK=fHSE up to
48 MHZ included,
bypass mode PLL ON
above 48 MHz all
Coremark
Dhrystone2.1
Fibonacci
While
7.5
8.0
6.7
6.1
7.5
7.9
6.6
6.1
94
100
83
93
99
83
76
Range 1, SMPS
HP
fHCLK=80 MHz
IDD
(Run)
Supply current in
Run mode
peripherals disabled
77
Reduced
code
11.2
11.1
102
101
Range 0, SMPS
HP
Coremark
Dhrystone2.1
Fibonacci
While
12.2
13.0
10.6
9.3
12.1
12.9
10.6
9.3
111
118
97
110
117
96
fHCLK= 110 MHz
85
84
Table 51. Typical current consumption in Run and Low-power run modes,
with different codes running from Flash, ICACHE ON (1-way)
TYP
TYP
TYP
TYP
Dual
Single
Bank
Mode
Dual
Bank
Mode
Conditions
Single Bank
Mode
Bank
Mode
Symbol
Parameter
Unit
Unit
-
Voltage scaling
Code
25°C
25°C
25°C
25°C
Reduced code
Coremark
Dhrystone2.1
Fibonacci
3.10
3.26
3.48
2.95
2.73
11.0
11.6
12.4
10.4
9.7
3.10
3.26
3.47
2.95
2.72
11.0
11.6
12.4
10.4
9.7
119
125
134
114
105
138
145
155
130
121
147
154
165
138
129
208
213
226
196
178
119
125
133
113
105
138
145
155
130
121
147
154
164
138
129
198
194
203
188
186
Range2
fHCLK=26 MHz
mA
µA/MHz
While
Reduced code
Coremark
Dhrystone2.1
Fibonacci
fHCLK=fHSE up to
48 MHZ included,
bypass mode PLL
IDD
(Run)
Supply current in
Run mode
Range 1
mA
mA
µA
µA/MHz
µA/MHz
µA/MHz
ON above 48 MHz fHCLK=80 MHz
all peripherals
disabled
While
Reduced code
Coremark
Dhrystone2.1
Fibonacci
16.1
17.0
18.2
15.2
14.2
416
16.1
17.0
18.1
15.2
14.2
395
Range 0
fHCLK= 110
MHz
While
Reduced code
Coremark
Dhrystone2.1
Fibonacci
425
389
IDD
Supply current in
Low-power run
fHCLK = fMSI = 2 MHz all peripherals
disabled
451
405
(LPRu
n)
392
375
While
355
372
Table 52. Typical current consumption in Run mode with SMPS,
with different codes running from Flash, ICACHE ON (1-way)
TYP
TYP
TYP
TYP
Single
Bank
Mode
Dual
Bank
Mode
Single
Bank
Mode
Dual
Bank
Mode
Conditions
Symbol
Parameter
Unit
Unit
Voltage
scaling
-
Code
25°C
25°C
25°C
25°C
Reduced code
Coremark
Dhrystone2.1
Fibonacci
1.82
1.91
2.03
1.74
1.63
6.8
1.80
1.89
2.00
1.72
1.61
6.8
70
73
78
67
63
85
89
95
80
75
98
105
112
91
83
69
73
77
66
62
84
88
94
80
75
96
104
111
91
83
Range2,
SMPS LP
fHCLK=26
MHz
mA
mA
mA
µA/MHz
µA/MHz
µA/MHz
While
Reduced code
Coremark
Dhrystone2.1
Fibonacci
fHCLK=fHSE up to
48 MHZ included,
bypass mode PLL ON
above 48 MHz all
7.1
7.1
Range 1,
SMPS HP
fHCLK=80
MHz
IDD
(Run)
Supply current in Run
mode
7.6
7.6
6.4
6.4
peripherals disabled
While
6.0
6.0
Reduced code
Coremark
Dhrystone2.1
Fibonacci
10.8
11.5
12.4
10.0
9.2
10.5
11.4
12.2
10.0
9.1
Range 0,
SMPS HP
fHCLK=
110 MHz
While
Table 53. Typical current consumption in Run and Low-power run modes,
with different codes running from Flash, ICACHE disabled
TYP
TYP
TYP
TYP
Single
Bank
Mode
Dual
Bank
Mode
Single
Bank
Mode
Dual
Bank
Mode
Conditions
Symbol
Parameter
Unit
Unit
-
Voltage scaling
Code
25°C
25°C
25°C
25°C
Reduced code
Coremark
Dhrystone2.1
Fibonacci
4.08
4.42
4.56
3.62
3.04
14.1
13.6
12.5
12.1
10.9
18.8
17.5
17.7
16.6
15.9
511
4.17
4.22
4.41
3.55
3.14
13.9
12.2
12.5
11.3
11.3
17.2
15.2
15.5
15.1
16.5
484
157
170
175
139
117
176
171
156
151
136
171
159
161
151
145
255
289
299
235
208
160
162
170
137
121
174
152
156
142
141
156
138
141
138
150
242
275
275
231
199
Range2
fHCLK=26 MHz
mA
µA/MHz
While
Reduced code
Coremark
Dhrystone2.1
Fibonacci
fHCLK=fHSE up to
48 MHZ included,
bypass mode PLL ON
above 48 MHz all
IDD
(Run)
Supply current in
Run mode
Range 1 fHCLK=80
MHz
mA
mA
µA
µA/MHz
µA/MHz
µA/MHz
peripherals disabled
While
Reduced code
Coremark
Dhrystone2.1
Fibonacci
Range 0
fHCLK= 110 MHz
While
Reduced code
Coremark
Dhrystone2.1
Fibonacci
577
550
IDD(LPR Supply current in
un) Low-power run
fHCLK = fMSI = 2MHz all peripherals
disabled
599
551
470
462
While
416
398
Table 54. Typical current consumption in Run mode with internal SMPS,
with different codes running from Flash, ICACHE disabled
TYP
TYP
TYP
Single Dual
Bank Bank
Mode Mode
TYP
Single
Bank
Mode Mode
Dual
Bank
Conditions
Symbol
Parameter
Unit
Unit
-
Voltage scaling
Code
25°C
25°C
25°C
25°C
Reduced code
Coremark
Dhrystone2.1
Fibonacci
2.38
2.59
2.67
2.13
1.80
8.7
2.41
2.44
2.55
2.07
1.86
8.5
92
100
103
82
93
94
Range2, SMPS
LP
fHCLK=26 MHz
mA
98
µA/MHz
79
While
69
72
Reduced code
Coremark
Dhrystone2.1
Fibonacci
109
106
107
93
107
93
fHCLK=fHSE up to 48
8.4
7.5
MHZ included, bypass Range 1, SMPS
IDD
(Run)
Supply current in Run
mode
mode PLL ON above
48 MHz all peripherals
disabled
HP fHCLK=80
8.6
7.7
mA
mA
96
µA/MHz
µA/MHz
MHz
7.5
7.0
87
While
6.8
7.0
84
87
Reduced code
Coremark
Dhrystone2.1
Fibonacci
12.9
11.9
12.0
11.3
10.7
11.6
10.1
10.4
10.1
11.1
117
109
109
102
97
105
92
Range 0, SMPS
HP
94
fHCLK= 110 MHz
92
While
101
Table 55. Typical current consumption in Run and Low-power run modes,
with different codes running from SRAM1
Conditions
Voltage scaling
TYP
TYP
Symbol
Parameter
Unit
Unit
-
Code
25°C
25°C
Reduced code
Coremark
Dhrystone2.1
Fibonacci
3.26
3.41
3.35
3.50
3.82
11.6
12.22
11.9
12.5
13.93
17.0
17.88
17.4
18.3
20.4
385
125
131
129
134
147
145
153
149
157
174
154
163
159
166
186
193
211
192
204
221
Range2
fHCLK=26MHz
mA
µA/MHz
While
Reduced code
Coremark
Dhrystone2.1
Fibonacci
fHCLK=fHSE up to 48 MHZ
Supply current in
Run mode
included, bypass mode PLL Range 1 fHCLK=80
IDD (Run)
mA
mA
µA
µA/MHz
µA/MHz
µA/MHz
ON above 48 MHz all
peripherals disabled
MHz
While
Reduced code
Coremark
Dhrystone2.1
Fibonacci
Range 0
fHCLK= 110 MHz
While
Reduced code
Coremark
Dhrystone2.1
Fibonacci
421
Supply current in
Low-power run
IDD(LPRun)
fHCLK = fMSI = 2MHz all peripherals disabled
384
409
While
442
Table 56. Typical current consumption in Run mode with internal SMPS,
with different codes running from SRAM1
Conditions
Voltage scaling
TYP
TYP
Symbol
Parameter
Unit
Unit
-
Code
25°C
25°C
Reduced code
Coremark
Dhrystone2.1
Fibonacci
1.89
1.9
73
73
Range2, LP
fHCLK=26MHz
1.94
2.01
2.22
7.1
mA
75
µA/MHz
77
While
85
Reduced code
Coremark
Dhrystone2.1
Fibonacci
89
7.25
7.3
91
fHCLK=fHSE up to 48 MHZ
Supply current in Run included, bypass mode PLL
Range 1, HP
fHCLK=80 MHz
IDD (Run)
mA
mA
91
µA/MHz
µA/MHz
mode
ON above 48 MHz all
peripherals disabled
7.6
95
While
8.51
11.3
11.32
11.7
12.3
13.9
106
103
103
107
112
126
Reduced code
Coremark
Dhrystone2.1
Fibonacci
Range 0, HP
fHCLK= 110 MHz
While
Table 57. Typical current consumption in Run and Low-power run modes,
with different codes running from SRAM2
Conditions
TYP
TYP
Symbol
Parameter
Unit
Unit
-
Voltage scaling
Code
25°C
25°C
Reduced code
Coremark
Dhrystone2.1
Fibonacci
3.20
3.33
3.20
3.34
3.66
11.4
11.92
11.4
12.0
13.24
16.7
17.44
16.6
17.5
19.5
386
123
128
123
129
141
143
149
142
149
165
152
159
151
159
177
193
207
187
196
218
Range2
fHCLK=26MHz
mA
µA/MHz
While
Reduced code
Coremark
Dhrystone2.1
Fibonacci
fHCLK=fHSE up to 48 MHZ
Supply current in Run included, bypass mode PLL
Range 1
fHCLK=80 MHz
IDD (Run)
mA
mA
µA
µA/MHz
µA/MHz
µA/MHz
mode
ON above 48 MHz all
peripherals disabled
While
Reduced code
Coremark
Dhrystone2.1
Fibonacci
Range 0
fHCLK= 110 MHz
While
Reduced code
Coremark
Dhrystone2.1
Fibonacci
414
IDD
Supply current in Low-
power run
fHCLK = fMSI = 2MHz all peripherals disabled
373
(LPRun)
393
While
436
Table 58. Typical current consumption in Run mode with internal SMPS,
with different codes running from SRAM2
Conditions
TYP
TYP
Symbol
Parameter
Unit
Unit
-
Voltage scaling
Code
25°C
25°C
Reduced code
Coremark
Dhrystone2.1
Fibonacci
1.90
2.08
1.90
1.98
2.14
7.0
73
80
Range2, LP
fHCLK=26MHz
mA
73
µA/MHz
76
While
82
Reduced code
Coremark
Dhrystone2.1
Fibonacci
88
7.0
88
fHCLK=fHSE up to 48 MHZ
included, bypass mode
PLL ON above 48 MHz all
peripherals disabled
Supply current in Run
mode
Range 1,HP
fHCLK=80 MHz
IDD (Run)
7.0
mA
mA
87
µA/MHz
µA/MHz
7.3
92
While
8.05
11.0
11.1
11.2
11.8
13.1
101
100
101
102
108
119
Reduced code
Coremark
Dhrystone2.1
Fibonacci
Range 0, HP
fHCLK= 110 MHz
While
Table 59. Current consumption in Sleep and Low-power sleep mode, Flash ON
Conditions
TYP
MAX
85°C
Symbol
Parameter
Unit
Voltage
scaling
-
fHCLK
25°C
55°C
85°C 105°C 125°C 25°C 55°C
105°C 125°C
26 MHz
16 MHz
8 MHz
1.04
0.72
0.46
0.33
0.27
0.24
1.37
1.04
0.79
0.65
0.58
0.55
0.52
5.23
3.74
3.44
3.14
2.53
1.91
1.60
1.29
2.36
2.04
1.78
1.65
1.58
1.55
1.52
6.62
5.01
4.71
4.41
3.79
3.17
2.84
2.53
3.88
3.55
3.29
3.14
3.07
3.03
3.01
8.65
6.88
6.56
6.26
5.62
4.98
4.67
4.34
3383
3343
3313
3308
6.62
6.30
6.01
5.85
5.78
5.73
5.72
12.21
10.19
9.86
9.56
8.92
8.27
7.93
7.60
6283
6248
6222
6219
2.25
1.93
1.67
1.54
1.48
1.46
1.42
4.69
4.36
4.10
3.97
3.90
3.88
3.84
9.93
9.60
9.33
9.19
9.12
9.11
9.06
16.57
16.23
15.95
15.80
15.73
15.72
15.67
28.98
24.74
24.42
24.10
23.45
22.78
22.44
22.10
27.36
27.00
26.70
26.55
26.48
26.46
26.41
44.29
38.70
38.36
38.03
37.38
36.67
36.32
35.96
Range 2 4 MHz
2 MHz
fHCLK = fHSE
up to 48MHz
included,
bypassmode
PLL ON
above 48
MHz all
peripherals
disabled
1 MHz
100 KHz 0.211
Supply
current in
Sleep mode
IDD
Range 0 110 MHz 4.73
7.00 11.02 19.15
mA
(Sleep)
80 MHz
72 MHz
3.31
3.01
2.71
2.10
1.49
1.18
0.88
5.20
4.90
4.60
3.98
3.37
3.06
2.75
8.71
8.40
8.10
7.47
6.84
6.52
6.21
15.92
15.61
15.29
14.66
14.00
13.68
13.35
64 MHz
Range 1 48 MHz
32 MHz
24 MHz
16 MHz
2 MHz 205.22 584.41 1712
1 MHz 192.80 547.20 1678
400 KHz 143.73 520.85 1655
100 KHz 137.82 519.15 1650
1843 4745 12643 19003 31504
1815 4665 12037 18615 31391
1793 4567 11872 18346 30902
1786 4554 11814 18206 30849
Supply
fHCLK = fMSI
all peripherals disabled
IDD(LPSl
eep)
current in
Low-power
sleep mode
µA
Table 60. Current consumption in Low-power sleep mode, Flash in power-down
Conditions
TYP
MAX
Symbol
Parameter
Unit
Voltage
scaling
-
fHCLK
25°C
55°C
85°C
105°C 125°C
25°C
55°C
85°C
105°C
125°C
2 MHz
1 MHz
197.64 567.40
165.99 540.66
1699
1672
1640
1629
3374
3313
3312
3288
6136
6109
6084
6062
1839
1805
1785
1423
4641
4599
4578
3848
12810
12189
10816
9087
20855
20334
17908
15694
31559
31071
30945
26452
Supply
current in
Low-power
sleep
fHCLK = fMSI
all peripherals
disabled
IDD
µA
(LPSleep)
400 KHz 145.78 510.80
100 KHz 143.34 506.41
mode
Table 61. Current consumption in Sleep mode,
Flash ON and power supplied by internal SMPS step down converter
Conditions
TYP
MAX
Symbol Parameter
Unit
Voltage
scaling
-
fHCLK
25°C
55°C
85°C 105°C 125°C 25°C
55°C
85°C 105°C 125°C
26 MHz 0.69
16 MHz 0.50
0.82
0.64
0.48
0.40
0.37
0.35
0.33
1.27
1.09
0.93
0.85
0.82
0.79
0.78
1.99
1.80
1.65
1.55
1.52
1.50
1.48
3.22
3.05
2.88
2.81
2.77
2.73
2.73
0.8
1.57
1.39
1.23
1.16
1.12
1.11
1.08
3.47
3.27
3.11
3.03
2.99
2.98
2.95
5.93
5.73
5.57
5.48
5.44
5.43
5.4
9.88
9.67
9.5
0.62
0.47
0.39
0.35
0.34
0.32
8 MHz
4 MHz
2 MHz
1 MHz
0.35
0.27
0.23
0.21
Range 2
9.42
9.37
9.36
9.33
SMPS LP
mode
fHCLK = fHSE up
to 48MHz
100 KHz 0.20
included,
Range 0
Supply
IDD
bypass mode
PLL ON above
48 MHz all
peripherals
disabled
current in
110 MHz 3.22
3.49
4.24
5.40
7.70
3.81
5.39
9.01
12.92 19.03 mA
SMPS HP
mode
(Sleep)
Sleep mode
80 MHz 2.22
72 MHz 2.04
64 MHz 1.85
48 MHz 1.48
32 MHz 1.10
24 MHz 0.91
16 MHz 0.72
2.44
2.26
2.07
1.70
1.32
1.12
0.93
3.09
2.90
2.71
2.34
1.94
1.74
1.55
4.06
3.89
3.70
3.31
2.91
2.71
2.52
5.98
5.78
5.53
5.11
4.62
4.40
4.18
2.6
3.9
3.7
6.89
6.68
6.48
6.07
5.64
5.42
5.2
10.56 15.77
10.37 15.58
10.19 15.38
2.41
2.22
1.83
1.44
1.24
1.04
3.51
3.1
Range 1
9.81
9.39
9.18
8.97
15
SMPS HP
mode
2.69
2.48
2.28
14.58
14.38
14.17
Table 62. Current consumption in Run mode, code with data processing running from Flash
in single bank, ICACHE ON in 2-way and power supplied by external SMPS
Conditions(1)
TYP
Symbol
Parameter
Unit
-
VDD12
fHCLK
25°C
55°C
85°C
105°C
125°C
VDD12=1.2V 110 MHz
80 MHz
6.69
4.1
6.93
4.77
4.33
3.88
2.98
2.08
1.91
1.29
0.76
0.49
0.36
0.29
0.23
7.5
8.23
5.94
5.49
5.04
4.12
3.2
9.5
5.28
4.83
4.38
3.47
2.55
2.31
1.69
1.15
0.88
0.75
0.69
0.63
7.1
72 MHz
3.7
6.65
6.18
5.27
4.32
3.89
3.26
2.7
64 MHz
3.31
2.51
1.7
48 MHz
32 MHz
fHCLK = fHSE up to 48 MHz
Supply current in Run included, bypass mode PLL ON
IDD(Run)
26 KHz
VDD12=1.1V
1.76
1.14
0.62
0.35
0.22
0.16
0.1
2.9
mA
mode
above 48 MHz all peripherals
disabled
16 MHz
2.25
1.72
1.45
1.32
1.25
1.19
8 MHz
4 MHz
2 MHz
1 MHz
100 KHz
2.44
2.29
2.23
2.16
1. All values are obtained by calculation based on measurements done with internal voltage regulator and using following parameters: SMPS input = 3.3 V, SMPS efficiency
= 85%.
Table 63. Current consumption in Run mode, code with data processing running from Flash
in single bank, ICACHE ON in 1-way and power supplied by external SMPS
Conditions(1)
TYP
Symbol
Parameter
Unit
-
VDD12
fHCLK
25°C
55°C
85°C 105°C 125°C
VDD12=1.2V 110 MHz 6.47
6.71
4.15
3.76
3.37
2.59
1.81
7.28
4.6
8.03
5.2
9.28
6.23
5.82
5.43
4.62
3.81
80 MHz
72 MHz
64 MHz
48 MHz
32 MHz
3.97
3.58
3.2
4.21
3.82
3.02
2.24
4.81
4.41
3.61
2.81
2.43
1.65
fHCLK = fHSE up to 48 MHz
included, bypass mode PLL ON
above 48 MHz all peripherals
disabled
Supply current in Run
mode
IDD(Run)
26 KHz 1.337 1.484 1.885 2.455 3.455
16 MHz 0.863 1.001 1.393 1.963 2.959
mA
VDD12=1.1V
8 MHz
4 MHz
2 MHz
1 MHz
0.479 0.613 1.005
1.57
2.558
0.285 0.423 0.807 1.376 2.364
0.185 0.324 0.712 1.281
0.138 0.272 0.66 1.229
2.26
2.2
100 KHz 0.095 0.229 0.617 1.186 2.161
1. All values are obtained by calculation based on measurements done with internal voltage regulator and using following parameters: SMPS input = 3.3 V, SMPS efficiency
= 85%.
Table 64. Current consumption in Run mode, code with data processing running from Flash
in single bank, ICACHE disabled and power supplied by external SMPS
Conditions(1)
TYP
Symbol
Parameter
Unit
-
VDD12
fHCLK
25°C
55°C
85°C 105°C 125°C
VDD12=1.2V 110 MHz 7.55
7.8
5.26
4.77
4.42
3.37
2.37
1.911
8.37
5.72
5.22
4.87
3.82
2.8
9.13
6.34
5.83
5.48
4.42
3.39
10.39
7.36
6.87
6.5
80 MHz
72 MHz
64 MHz
48 MHz
32 MHz
26 KHz
5.07
4.58
4.24
3.19
2.2
5.43
4.4
fHCLK = fHSE up to 48 MHz
included, bypass mode PLL ON
above 48 MHz all peripherals
disabled
Supply current in Run
mode
IDD(Run)
1.76
2.312 2.899
3.891
3.257
2.7
mA
VDD12=1.1V
16 MHz 1.143
1.285 1.687 2.252
0.759 1.152 1.721
0.492 0.884 1.449
0.358 0.755 1.316
0.293 0.686 1.247
0.233 0.625 1.191
8 MHz
4 MHz
2 MHz
1 MHz
0.617
0.354
0.22
2.437
2.291
2.226
2.157
0.155
100 KHz 0.099
1. All values are obtained by calculation based on measurements done with internal voltage regulator and using following parameters: SMPS input = 3.3 V, SMPS efficiency
= 85%.
Table 65. Current consumption in Run mode, code with data processing running from Flash
in dual bank, ICACHE on in 2-way and power supplied by external SMPS
Conditions(1)
TYP
Symbol
Parameter
Unit
-
VDD12
fHCLK
25°C
55°C
85°C 105°C 125°C
VDD12=1.2V 110 MHz 6.69
6.93
4.28
3.88
3.48
2.67
1.86
7.56
4.78
4.37
3.97
3.15
2.33
8.41
5.47
5.06
4.65
3.82
2.99
9.93
6.72
6.3
80 MHz
72 MHz
64 MHz
48 MHz
32 MHz
4.09
3.7
3.3
2.5
1.7
5.88
5.04
4.2
fHCLK = fHSE up to 48 MHz
included, bypass mode PLL ON
above 48 MHz all peripherals
disabled
Supply current in Run
mode
IDD(Run)
26 KHz 1.147 1.269 1.643 2.189 3.189
16 MHz 0.737 0.856 1.226 1.765 2.761
mA
VDD12=1.1V
8 MHz
4 MHz
2 MHz
1 MHz
0.406 0.521 0.888 1.424 2.412
0.241 0.356 0.715 1.255
0.158 0.273 0.633 1.168
2.24
2.15
0.115
0.23
0.586 1.129 2.103
100 KHz 0.079 0.191 0.554 1.078 2.067
1. All values are obtained by calculation based on measurements done with internal voltage regulator and using following parameters: SMPS input = 3.3 V, SMPS efficiency
= 85%.
Table 66. Current consumption in Run mode, code with data processing running from Flash
in dual bank, ICACHE on in 1-way and power supplied by external SMPS
Conditions(1)
TYP
Symbol
Parameter
Unit
-
VDD12
fHCLK
25°C
55°C
85°C 105°C 125°C
VDD12=1.2V 110 MHz 6.47
6.72
4.15
3.76
3.38
2.59
1.81
7.34
4.64
4.25
3.86
3.06
2.27
8.02
5.33
4.94
4.54
3.74
2.95
9.68
6.55
6.15
5.75
4.95
4.13
80 MHz
72 MHz
64 MHz
48 MHz
32 MHz
3.97
3.58
3.2
2.42
1.65
fHCLK = fHSE up to 48 MHz
included, bypass mode PLL ON
above 48 MHz all peripherals
disabled
Supply current in Run
mode
IDD(Run)
26 KHz 1.114 1.237 1.603 2.157 3.153
16 MHz 0.719 0.834 1.201 1.74 2.732
mA
VDD12=1.1V
8 MHz
4 MHz
2 MHz
1 MHz
0.399 0.514 0.877 1.416 2.401
0.237 0.352 0.708 1.251 2.229
0.155 0.273 0.629 1.165
0.115 0.23 0.586 1.129 2.103
0.55 1.086 2.067
2.15
100 KHz 0.079 0.194
1. All values are obtained by calculation based on measurements done with internal voltage regulator and using following parameters: SMPS input = 3.3 V, SMPS efficiency
= 85%.
Table 67. Current consumption in Run mode, code with data processing running from Flash
in dual bank, ICACHE disabled and power supplied by external SMPS
Conditions(1)
TYP
Symbol
Parameter
Unit
-
VDD12
fHCLK
25°C
55°C
85°C 105°C 125°C
VDD12=1.2V 110 MHz
80 MHz
6.9
7.15
5.21
4.72
4.44
3.39
2.42
7.76
5.7
8.61
6.4
10.1
7.63
7.14
6.85
5.78
4.77
5.01
4.53
4.25
3.21
2.25
72 MHz
5.22
4.94
3.88
2.89
5.91
5.63
4.57
3.57
64 MHz
48 MHz
32 MHz
fHCLK = fHSE up to 48 MHz
included, bypass mode PLL ON
above 48 MHz all peripherals
disabled
Supply current in Run
mode
IDD(Run)
26 KHz 1.499 1.625 1.999 2.552 3.544
16 MHz 0.985 1.107 1.474 2.024 3.02
1.557 2.538
mA
VDD12=1.1V
8 MHz
4 MHz
2 MHz
1 MHz
0.532 0.647
1.01
0.302 0.421 0.776 1.316 2.301
0.187 0.302 0.665 1.197 2.178
0.133 0.248 0.604 1.147 2.117
100 KHz 0.079 0.194 0.554 1.089 2.063
1. All values are obtained by calculation based on measurements done with internal voltage regulator and using following parameters: SMPS input = 3.3 V, SMPS efficiency
= 85%.
Table 68. Current consumption in Run mode, code with data processing running from SRAM1,
and power supplied by external SMPS
Conditions(1)
TYP
Symbol
Parameter
Unit
-
VDD12
fHCLK
25°C
55°C
85°C 105°C 125°C
VDD12=1.2V 110 MHz 6.81
7.05
4.36
3.95
3.54
2.72
1.89
7.66
4.85
4.43
4.02
3.19
2.35
8.51
5.53
5.12
4.7
10
80 MHz
72 MHz
64 MHz
48 MHz
32 MHz
4.18
3.78
3.37
2.55
1.74
6.75
6.34
5.91
5.07
4.21
3.21
3.86
3.02
fHCLK = fHSE up to 48 MHz
included, bypass mode PLL ON
above 48 MHz all peripherals
disabled
Supply current in Run
mode
IDD(Run)
26 KHz 1.172 1.294 1.661 2.204
16 MHz 0.751 0.87
mA
VDD12=1.1V
1.233 1.776 2.764
8 MHz
4 MHz
2 MHz
1 MHz
0.413 0.532 0.892 1.427 2.419
0.244 0.359 0.719 1.262 2.243
0.158 0.273 0.633 1.168
0.119 0.23 0.593 1.129
0.55
2.15
2.11
100 KHz 0.079 0.194
1.093 2.071
1. All values are obtained by calculation based on measurements done with internal voltage regulator and using following parameters: SMPS input = 3.3 V, SMPS efficiency
= 85%.
Table 69. Current consumption in Run mode, code with data processing running from SRAM2,
and power supplied by external SMPS
Conditions(1)
TYP
Symbol
Parameter
Unit
-
VDD12
fHCLK
25°C
55°C
85°C 105°C 125°C
VDD12=1.2V 110 MHz
80 MHz
6.7
6.95
4.29
3.89
3.49
2.68
1.87
7.56
4.78
4.37
3.97
3.16
2.33
8.41
5.47
5.06
4.65
3.82
3
9.89
6.7
4.11
3.71
3.31
2.51
1.71
1.15
72 MHz
6.28
5.87
5.03
4.19
3.185
2.757
2.412
2.236
2.15
2.11
64 MHz
48 MHz
32 MHz
fHCLK = fHSE up to 48 MHz
included, bypass mode PLL ON
above 48 MHz all peripherals
disabled
Supply current in Run
mode
IDD(Run)
26 KHz
1.273 1.639 2.186
0.856 1.222 1.761
0.525 0.888 1.427
0.356 0.715 1.251
0.273 0.629 1.168
mA
VDD12=1.1V
16 MHz 0.741
8 MHz
4 MHz
2 MHz
1 MHz
0.41
0.241
0.158
0.115
0.23
0.59
0.55
1.129
1.086
100 KHz 0.079
0.194
2.067
1. All values are obtained by calculation based on measurements done with internal voltage regulator and using following parameters: SMPS input = 3.3 V, SMPS efficiency
= 85%.
Table 70. Current consumption in Sleep mode, Flash ON and power supplied by external SMPS
Conditions(1)
TYP
Symbol
Parameter
Unit
-
VDD12
fHCLK
25°C
55°C
85°C 105°C 125°C
VDD12=1.20V 110 MHz 1.90
2.10
1.35
1.24
1.13
0.91
0.69
2.66
1.80
1.70
1.59
1.36
1.14
3.47
2.47
2.36
2.25
2.02
1.79
4.90
3.67
3.54
3.44
3.21
2.97
80 MHz
72 MHz
64 MHz
48 MHz
32 MHz
1.19
1.08
0.98
0.76
0.54
fHCLK = fHSE up to 48 MHz
included, bypass mode PLL ON
above 48 MHz all peripherals
disabled
Supply current in
Sleep mode
IDD(Sleep)
26 MHz 0.453 0.591 1.022 1.678 2.860
16 MHz 0.315 0.453 0.880 1.531 2.718
mA
VDD12=1.10V
8 MHZ
4 MHz
2MHz
1 MHz
0.203 0.341 0.768 1.424 2.593
0.147 0.285 0.712 1.355 2.528
0.116
0.255 0.682 1.329 2.498
0.104 0.242 0.669 1.307 2.476
100 Khz 0.091 0.229 0.656 1.298 2.472
1. All values are obtained by calculation based on measurements done with internal voltage regulator and using following parameters: SMPS input = 3.3 V, SMPS efficiency
= 85%.
Table 71. Current consumption in Run mode, code with data processing running from Flash,
ICACHE on (2-way) and power supplied by external SMPS
TYP
single
bank
TYP
single
bank
TYP
single
bank
TYP
single
bank
Conditions(1)
VDD12
Symbol Parameter
Unit
Unit
mode
mode
mode
mode
-
fHCLK
code
25°C
25°C
25°C
25°C
Reduced code
Coremark
1.2
1.29
1.37
1.15
1.04
1.45
1.56
1.66
1.39
1.26
4.1
1.2
46.15
49.62
52.69
44.23
40
46.15
49.62
52.69
43.85
40
1.29
1.37
1.14
1.04
1.45
1.56
1.65
1.38
1.26
4.09
4.4
VDD12=1.00V fHCLK=26MHz Dhrystone2.1
mA
µA/MHz
Fibonacci
While(1)
Reduced code
55.77
60
55.77
60
Coremark
fHCLK=26MHz Dhrystone2.1
Fibonacci
mA
mA
mA
63.85
53.46
48.46
51.25
55
63.46
53.08
48.46
51.13
55
µA/MHz
µA/MHz
µA/MHz
fHCLK = fHSE up to
48MHz included, bypass
mode PLL ON above 48
MHz all peripherals
disabled
While(1)
Supply
current in
Run mode
IDD(Run)
VDD12=1.10V
Reduced code
Coremark
4.4
fHCLK=80MHz Dhrystone2.1
4.7
4.68
3.88
3.55
6.69
7.2
58.75
48.5
58.5
Fibonacci
3.88
3.55
6.69
7.2
48.5
While(1)
44.38
60.82
65.45
69.64
57.45
52.73
44.38
60.82
65.45
69.27
57.45
52.73
Reduced code
Coremark
VDD12=1.20V fHCLK=110MHz Dhrystone2.1
7.66
6.32
5.8
7.62
6.32
5.8
Fibonacci
While(1)
1. All values are obtained by calculation based on measurements done with internal voltage regulator and using following parameters: SMPS input = 3.3 V, SMPS efficiency =
85%.
Table 72. Current consumption in Run mode, code with data processing running from Flash,
ICACHE on (1-way) and power supplied by external SMPS
TYP
Single
Bank
mode
TYP
Single
Bank
mode
TYP
Single
Bank
mode
TYP
Single
Bank
mode
Conditions(1)
VDD12
Symbol Parameter
Unit
mA
mA
mA
mA
Unit
-
fHCLK
code
25°C
25°C
25°C
25°C
Reduced code
Coremark
1.16
1.22
1.31
1.11
1.02
1.41
1.48
1.58
1.34
1.24
3.97
4.16
4.47
3.73
3.49
6.47
6.81
7.28
6.09
5.71
1.16
1.22
1.3
44.62
46.92
50.38
42.69
39.23
54.23
56.92
60.77
51.54
47.69
49.63
52
44.62
46.92
50
VDD12=1.00V fHCLK=26MHz Dhrystone2.1
µA/MHz
µA/MHz
µA/MHz
µA/MHz
Fibonacci
While(1)
1.11
1.02
1.41
1.48
1.58
1.34
1.24
3.97
4.16
4.45
3.73
3.49
6.47
6.81
7.25
6.09
5.7
42.69
39.23
54.23
56.92
60.77
51.54
47.69
49.63
52
Reduced code
Coremark
fHCLK=26MHz Dhrystone2.1
Fibonacci
fHCLK = fHSE up to
48MHz included, bypass
mode PLL ON above 48
MHz all peripherals
disabled
While(1)
Supply
IDD(Run)
current in
VDD12=1.10V
Reduced code
Run mode
Coremark
fHCLK=80MHz Dhrystone2.1
55.88
46.63
43.63
58.82
61.91
66.18
55.36
51.91
55.63
46.63
43.63
58.82
61.91
65.91
55.36
51.82
Fibonacci
While(1)
Reduced code
Coremark
VDD12=1.20V fHCLK=110MHz Dhrystone2.1
Fibonacci
While(1)
1. All values are obtained by calculation based on measurements done with internal voltage regulator and using following parameters: SMPS input = 3.3 V, SMPS efficiency =
85%.
Table 73. Current consumption in Run mode, code with data processing running from Flash,
ICACHE disabled and power supplied by external SMPS
TYP
Single
Bank
mode
TYP
Single
Bank
mode
TYP
Single
Bank
mode
TYP
Single
Bank
mode
Conditions(1)
VDD12
Symbol Parameter
Unit
mA
mA
mA
mA
Unit
-
fHCLK
code
25°C
25°C
25°C
25°C
Reduced code
Coremark
1.53
1.66
1.71
1.36
1.14
1.85
2.01
2.07
1.64
1.38
5.07
4.91
4.49
4.34
3.9
1.56
1.58
1.65
1.33
1.18
1.89
1.92
2
58.85
63.85
65.77
52.31
43.85
71.15
77.31
79.62
63.08
53.08
63.38
61.38
56.13
54.25
48.75
68.64
63.91
64.36
60.36
58.09
60
60.77
63.46
51.15
45.38
72.69
73.85
76.92
61.92
55
VDD12=1.00V fHCLK=26MHz Dhrystone2.1
µA/MHz
µA/MHz
µA/MHz
µA/MHz
Fibonacci
While(1)
Reduced code
Coremark
fHCLK=26MHz Dhrystone2.1
Fibonacci
1.61
1.43
5.01
4.37
4.49
4.07
4.04
6.9
fHCLK = fHSE up to
48MHz included, bypass
mode PLL ON above 48
MHz all peripherals
disabled
While(1)
Supply
IDD(Run)
current in
VDD12=1.10V
Reduced code
62.63
54.63
56.13
50.88
50.5
Run mode
Coremark
fHCLK=80MHz Dhrystone2.1
Fibonacci
While(1)
Reduced code
7.55
7.03
7.08
6.64
6.39
62.73
55.36
56.36
55.18
60.27
Coremark
6.09
6.2
VDD12=1.20V fHCLK=110MHz Dhrystone2.1
Fibonacci
While(1)
6.07
6.63
1. All values are obtained by calculation based on measurements done with internal voltage regulator and using following parameters: SMPS input = 3.3 V, SMPS efficiency =
85%.
Table 74. Current consumption in Run mode, code with data processing running from SRAM1,
and power supplied by external SMPS
Conditions(1)
TYP
TYP
Symbol
Parameter
Unit
Unit
-
VDD12
fHCLK
code
25°C
25°C
Reduced code
Coremark
1.22
0.57
1.26
1.31
1.43
1.48
0.69
1.52
1.59
1.73
4.18
1.84
4.29
4.5
46.92
21.92
48.46
50.38
55
VDD12=1.00V fHCLK=26MHz
Dhrystone2.1
Fibonacci
mA
µA/MHz
While(1)
Reduced code
Coremark
56.92
26.54
58.46
61.15
66.54
52.25
23
fHCLK=26MHz
Dhrystone2.1
Fibonacci
mA
mA
mA
µA/MHz
µA/MHz
µA/MHz
While(1)
fHCLK = fHSE up to 48MHz included,
IDD(Run) Supply current in Run mode bypass mode PLL ON above 48 MHz VDD12=1.10V
all peripherals disabled
Reduced code
Coremark
fHCLK=80MHz
Dhrystone2.1
Fibonacci
53.63
56.25
62.63
61.91
27
While(1)
5.01
6.81
2.97
7
Reduced code
Coremark
VDD12=1.20V fHCLK=110MHz Dhrystone2.1
63.64
66.73
74.45
Fibonacci
While(1)
7.34
8.19
1. All values are obtained by calculation based on measurements done with internal voltage regulator and using following parameters: SMPS input = 3.3 V, SMPS efficiency =
85%.
Table 75. Current consumption in Run mode, code with data processing running from SRAM2,
and power supplied by external SMPS
Conditions (1)
TYP
TYP
Symbol
Parameter
Unit
Unit
-
VDD12
fHCLK
code
25°C
25°C
Reduced
code
1.20
46.15
Coremark
Dhrystone2.1
Fibonacci
0.57
1.20
1.25
1.37
21.92
46.15
48.08
52.69
VDD12=1.00V fHCLK=26MHz
mA
µA/MHz
While(1)
Reduced
code
1.45
55.77
Coremark
Dhrystone2.1
Fibonacci
0.69
1.45
1.52
1.66
26.54
55.77
58.46
63.85
fHCLK=26MHz
mA
mA
mA
µA/MHz
µA/MHz
µA/MHz
While(1)
fHCLK = fHSE up to 48MHz included,
IDD(Run) Supply current in Run mode bypass mode PLL ON above 48 MHz all VDD12=1.10V
peripherals disabled
Reduced
code
4.11
51.38
Coremark
Dhrystone2.1
Fibonacci
1.84
4.09
4.30
4.76
23.00
51.13
53.75
59.50
fHCLK=80MHz
While(1)
Reduced
code
6.70
60.91
Coremark
Dhrystone2.1
Fibonacci
2.97
6.67
7.01
7.80
27.00
60.64
63.73
70.91
VDD12=1.20V fHCLK=110MHz
While(1)
1. All values are obtained by calculation based on measurements done with internal voltage regulator and using following parameters: SMPS input = 3.3 V, SMPS efficiency =
85%.
Table 76. Current consumption in Stop 2 mode
TYP
Conditions
-
MAX
Symbol
Parameter
Unit
VDD
25°C
55°C
85°C 105°C 125°C 25°C
55°C
85°C 105°C 125°C
1.8 V
2.4 V
3 V
3.07
3.09
3.13
3.2
16.61 68.35 158.43 332.53 19.03 67.19 202.18 407.53 797.08
16.86 69.13 160.32 335.88 19.08 67.43 201.94 409.7 802.29
Supply current
in Stop 2 mode,
IDD
-
(Stop 2)
17.24
17.42 71.15 164.99 349.3 19.39 68.67 205.04 415.22 816.69
17.32 68.52 159.57 333.56 19.7 67.81 202.19 408.09 797.2
69.5 161.75 341.1 19.18 67.79 203.72 412.34 812.99
RTC disabled
3.6 V
1.8 V
2.4 V
3 V
3.66
3.88
4.2
17.74 69.73 160.86 338.16 20.07 68.34 202.52 410.27 802.48
17.94 70.57 163.39 342.82 20.37 68.62 205.35 413.58 813.45
18.71 72.31 166.43 348.19 20.79 69.72 205.83 416.46 818.3
RTC clocked by LSI
3.6 V
1.8 V
2.4 V
3 V
4.42
3.5
17.14 69.36 159.76 332.52
17.68 70.03 161.58 336.53
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
RTC clocked by LSI
with LPCAL = 1,
ULPEN = 1
3.62
3.82
4.06
3.44
3.58
3.79
4.59
3.18
3.27
3.41
4.16
µA
18.2
18.8
71
163.7 343.17
IDD
Supply current
in Stop 2 mode,
RTC enabled
3.6 V
1.8 V
2.4 V
3 V
72.72 168.58 351.22
(Stop 2
with RTC)
17.15 68.39 159.57 333.37
17.35 69.8 161.86 336.47
RTC clocked by LSE
bypassed at 32768 Hz
with LPCAL = 0,
17.77 70.33 163.41 342.2
18.34 72.03 166.18 350.97
ULPEN = 0
3.6 V
1.8 V
2.4 V
3 V
16.98
69.4 160.31 335.07
RTC clocked by LSE
bypassed at 32768 Hz
with LPCAL = 1,
17.29 69.65 161.79 339.1
17.91 71.21 163.77 343.27
ULPEN = 1
3.6 V
18.5
72.62 167.08 350.59
Table 76. Current consumption in Stop 2 mode (continued)
Conditions
TYP
MAX
Symbol
Parameter
Unit
-
VDD
25°C
55°C
85°C 105°C 125°C 25°C
55°C
85°C 105°C 125°C
1.8 V
2.4 V
3 V
3.48
3.58
3.71
3.91
3.16
3.21
3.27
3.42
16.53
66.1
151.2 295.85
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
RTC clocked by LSE
quartz in low drive
mode
16.86 66.79 153.07 299.45
17.18 67.57 155.09 302.75
17.74 68.97 158.26 309.93
16.68 66.32 151.87 296.04
16.99 66.91 153.42 299.34
17.39 68.27 155.45 304.73
17.93 69.41 158.77 310.4
IDD
Supply current
in Stop 2 mode,
RTC enabled
(continued)
3.6 V
1.8 V
2.4 V
3 V
(Stop 2
with RTC)
(continued)
µA
RTC clocked by LSE
quartz in low drive
mode with LPCAL = 1,
ULPEN = 1
3.6 V
Wakeup clock is
MSI = 48 MHz,
voltage Range 1
3 V
3 V
3 V
1.96
1.09
1.72
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
IDD
Supply current
during wakeup
from Stop 2
mode
Wakeup clock is
MSI = 4 MHz, voltage
Range 2
(wakeup
from
Stop 2)
mA
Wakeup clock is
HSI = 16 MHz,
voltage Range 1
Table 77. Current consumption in Stop 1 mode
TYP
Conditions
-
MAX
85°C
Symbol Parameter
Unit
VDD
25°C
55°C
85°C
105°C 125°C
25°C
55°C
105°C
125°C
Supply
current in
Stop 1
mode,
1.8 V
2.4 V
3 V
91.47
91.94
92.51
372.36
375.16
375.46
1243
1251
1249
2527
2531
2549
4611
4652
4675
1196
1199
1204
3403
3418
3427
8100
8133
8174
13853
13906
13988
22830
22920
23189
IDD
-
(Stop 1)
RTC
3.6 V
93.26
380.59
1270
2567
4721
1215
3433
8158
14083
23335
disabled
1.8 V
2.4 V
3 V
92.46
92.48
93.34
93.38
92.35
92.31
93.59
93.19
373.25
372.19
374.54
378.64
371.81
374.21
375.92
377.07
1248
1250
1253
1267
1248
1245
1256
1262
1214
1224
1228
1239
2518
2528
2541
2559
2518
2521
2534
2551
2442
2447
2466
2480
4617
4643
4683
4712
4605
4640
4673
4713
-
1196
3405
8103
13874
22793
1201
3433
8135
13924
22927
RTC clocked
by LSI
1206
3424
8185
13994
23140
3.6 V
1.8 V
2.4 V
3 V
1213
3434
8176
14091
23336
µA
Supply
current in
Stop 1
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
RTC clocked
by LSE
bypassed at
32768 Hz
IDD
(Stop 1
with RTC)
mode,
RTC
3.6 V
enabled
1.8 V 100.67 381.08
2.4 V 101.20 380.64
RTC clocked
by LSE quartz
in low drive
mode
-
3 V
102.04 378.49
-
3.6 V 103.34 387.73
-
Table 77. Current consumption in Stop 1 mode (continued)
TYP
Conditions
-
MAX
85°C
Symbol Parameter
Unit
VDD
25°C
55°C
85°C
105°C 125°C
25°C
55°C
105°C
125°C
Wakeup clock
is MSI = 48
MHz, voltage
Range 1
3 V
2.02
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Supply
current
during
wakeup
from Stop
1 mode
IDD
Wakeup clock
is MSI = 4
MHz, voltage
Range 2
(wakeup
from Stop
1)
3 V
3 V
0.58
1.27
-
-
-
-
-
-
-
-
-
-
-
-
mA
Wakeup clock
is HSI = 16
MHz, voltage
Range 1
Table 78. Current consumption in Stop 0 mode
TYP
Conditions
MAX
Symbol Parameter
Unit
-
VDD
25°C
55°C
85°C
105°C
125°C
25°C
55°C
85°C
105°C
125°C
Supply
current in
Stop 0
mode,
-
-
-
1.8 V
2.4 V
3 V
192.69
194.69
196.09
494.92
495.31
495.47
1425
1430
1431
2797
2804
2812
5106
5108
5124
1395
1396
1397
3797
3798
3799
8974
8953
8996
15426
15440
15465
25827
25851
25967
IDD
µA
(Stop 0)
RTC
disabled
-
3.6 V
197.54
497.36
1434
2814
5155
1399
3802
8967
15488
26025
Table 79. Current consumption in Standby mode
Conditions
TYP
MAX
85°C
Symbol
Parameter
Unit
-
VDD
25°C
55°C
85°C 105°C 125°C
25°C
55°C
105°C
125°C
1.8 V
2.4 V
3 V
108
119
134
183
347
405
483
596
382
2374
2795
3215
7132 19259
8332 22151
9665 26746
237
361
411
558
572
708
609
999
2269
2497
2716
3214
2578
2832
2913
3466
6948
7770
8919
9577
7079
7868
8597
10069
12467
14021
15987
17816
12599
14061
16110
18212
31340
40505
45394
50551
31388
39741
44085
48579
No
476
independent
watchdog
591
Supply current in
Standby mode
(backup registers
retained),
3.6 V
1.8 V
2.4 V
3 V
827
4232 12128 31763
IDD
(Standby)
nA
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
RTC disabled
With
independent
watchdog
3.6 V
Table 79. Current consumption in Standby mode (continued)
Conditions
TYP
MAX
85°C
Symbol
Parameter
Unit
-
VDD
25°C
55°C
85°C 105°C 125°C
25°C
55°C
105°C
125°C
1.8 V
2.4 V
3 V
717
887
971
1266
1584
2059
779
2924
3589
7693 19714
9054 22856
930
2760
7456
12882
31665
RTC clocked
by LSI, no
independent
watchdog
1224
3096
8393
14557
40166
1113
1394
457
4206 10666 27521
5515 13394 32693
1303
3509
9212
16779
44936
3.6 V
1828
3889
10504
18898
48363
RTC clocked 1.8 V
3075
4082
8179 20106
9786 23298
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
by LSI, no
independent
watchdog
with
2.4 V
582
1080
1425
3 V
740
5195 11380 28044
LPCAL = 1,
ULPEN = 1
3.6 V
955
1905
6884 14210 33407
-
-
-
-
-
1.8 V
2.4 V
3 V
766
948
-
-
-
-
-
-
-
-
-
-
847
2549
7430
12888
31689
Supply current in
Standby mode
RTC clocked
by LSI, with
independent
watchdog
IDD
-
-
1267
3171
8250
14679
40296
(backup registers
retained),
nA
(Standby
with RTC)
1196
1492
435
-
-
1561
3610
9492
16773
44760
RTC enabled
3.6 V
1.8 V
2.4 V
3 V
-
711
954
1247
1686
-
-
1896
4136
10423
19143
48559
2650
3254
7592 19645
8972 22787
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
RTC clocked
by LSE
bypassed at
32768 Hz
569
768
3963 10303 27154
5174 13141 32293
3.6 V
1024
166
RTC clocked 1.8 V
-
-
-
-
-
-
-
-
-
by LSE
bypassed at
32768 Hz
with
2.4 V
236
-
3 V
356
-
LPCAL = 1,
ULPEN = 1
3.6 V
575
-
-
-
-
-
-
-
-
-
Table 79. Current consumption in Standby mode (continued)
Conditions
TYP
MAX
85°C
Symbol
Parameter
Unit
-
VDD
25°C
55°C
85°C 105°C 125°C
25°C
55°C
105°C
125°C
1.8 V
2.4 V
3 V
491
574
696
870
222
250
297
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
RTC clocked
by LSE
quartz in low
drive mode
Supply current in
Standby mode
IDD
3.6 V
(backup registers
retained),
(Standby
with RTC)
(continued)
RTC clocked 1.8 V
by LSE
quartz in low
drive mode
with
2.4 V
RTC enabled
(continued)
3 V
LPCAL = 1,
ULPEN = 1
3.6 V
403
-
-
-
-
-
-
-
-
-
nA
1.8 V
2.4 V
3 V
668
704
739
840
164
201
231
3089 13834 34240 75362
3193 14412 35468 78515
3283 14722 36843 82664
3571 15867 38708 88150
1834
1859
1907
1973
518
8192
8376
8514
8919
2685
2758
3243
28470
28905
29857
30509
8359
36317 135595
36890 140894
37533 144576
38460 149487
Supply current to
be added in
Standby mode
when Full SRAM2
(64KB) is retained
IDD
-
-
(SRAM2)
3.6 V
1.8 V
2.4 V
3 V
Supply current to
be added in
Standby mode
when partial
658
764
871
3378
9485 23856
8164
8842
9601
39054
47739
51857
3853 10707 26844
4319 12043 31160
585
9134
IDD
(SRAM)
606
9975
SRAM2 (4 KB) is
retained
3.6 V
326
1128
5250 14470 36553
723
3570
10872
10707
55419
Supply current
during wakeup
from Standby
mode
IDD (wakeup
from
Standby)
Wakeup
clock is
MSI = 4 MHz
3 V
1.11
-
-
-
-
-
-
-
-
-
mA
Table 80. Current consumption in Shutdown mode
TYP
Conditions
MAX
85°C
Symbol
Parameter
Unit
-
VDD
25°C
55°C
85°C
105°C 125°C
25°C
55°C
105°C
125°C
Supply
current in
Shutdown
mode
1.8 V
2.4 V
3 V
17.0
18.0
44.0
198
269
361
1533
1803
2314
5195
6166
7212
15336
17522
21381
99
590
679
800
3169
3610
4108
9252
10477
11860
26038
29468
32843
115
141
IDD
-
(backup
(Shutdown)
registers
retained)
RTC disabled
3.6 V 127.0
587
3159
9534
26115
196
990
4877
13734
37480
RTC clocked 1.8 V
307
485
689
525
746
1905
2363
2905
5592
6676
7919
15801
18041
22214
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
by LSE
bypassed at
2.4 V
32768 Hz
with
LPCAL = 0
3 V
1015
3.6 V
974
1435
4082
10392 26856
-
-
-
-
-
RTC clocked 1.8 V
116
221
339
325
491
656
1711
2100
2636
5423
6395
7450
15551
17909
21753
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
by LSE
bypassed at
nA
2.4 V
Supply
current in
Shutdown
mode
32768 Hz
with
LPCAL = 1
3 V
IDD
3.6 V
535
996
3645
9998
26420
-
-
-
-
-
(Shutdown
with RTC)
(backup
RTC clocked 1.8 V
405
486
604
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
registers
retained)
RTC enabled
by LSE
quartz in low
2.4 V
drive mode
with
LPCAL = 0
3 V
3.6 V
768
-
-
-
-
-
-
-
-
-
RTC clocked 1.8 V
207
232
272
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
by LSE
quartz in low
2.4 V
drive mode
with
LPCAL = 1
3 V
3.6 V
345
-
-
-
-
-
-
-
-
-
Table 80. Current consumption in Shutdown mode (continued)
Conditions
TYP
MAX
85°C
Symbol
Parameter
Unit
-
VDD
25°C
55°C
85°C
105°C 125°C
25°C
55°C
105°C
125°C
Supply
IDD
currentduring Wakeupclock
(wakeup
from
Shutdown)
wakeup from
Shutdown
mode
is
3 V
0.53
-
-
-
-
-
-
-
-
-
mA
MSI = 4 MHz
Table 81. Current consumption in VBAT mode
TYP
Conditions
-
MAX
Symbol Parameter
Unit
VBAT 25°C 55°C 85°C 105°C 125°C 25°C 55°C 85°C 105°C 125°C
1.8 V
2.4 V
3 V
3.4
3.9
45
55
73
136
369
528
727
996
381
406
441
518
-
307
358
447
786
654
843
1119
1680
692
738
841
1163
-
966
1097
1350
2303
1303
1595
2045
3247
1369
1499
1761
2707
-
2699
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
2995
RTC disabled
5.9
3699
3.6 V
1.8 V
2.4 V
3 V
13.4
330
446
632
867
130
183
288
392
387
461
568
700
187
202
229
275
6528
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
RTC enabled and
clocked by LSE
bypassed at
32768 Hz with
LPCAL = 0
3.6 V
1.8 V
2.4 V
3 V
RTC enabled and
clocked by LSE
bypassed at
32768 Hz with
LPCAL=1
Backup
IDD
(VBAT)
domain
supply
current
nA
3.6 V
1.8 V
2.4 V
3 V
RTC enabled and
clocked by LSE
quartz with
-
-
-
-
-
-
LPCAL = 0
3.6 V
1.8 V
2.4 V
3 V
-
-
-
-
-
-
RTC enabled and
clocked by LSE
quartz with
-
-
-
-
-
-
LPCAL = 1
3.6 V
-
-
-
Electrical characteristics
STM32L552xx
I/O system current consumption
The current consumption of the I/O system has two components: static and dynamic.
I/O static current consumption
All the I/Os used as inputs with pull-up generate current consumption when the pin is
externally held low. The value of this current consumption can be simply computed by using
the pull-up/pull-down resistors values given in Table 102: I/O static characteristics.
For the output pins, any external pull-down or external load must also be considered to
estimate the current consumption.
Additional I/O current consumption is due to I/Os configured as inputs if an intermediate
voltage level is externally applied. This current consumption is caused by the input Schmitt
trigger circuits used to discriminate the input value. Unless this specific configuration is
required by the application, this supply current consumption can be avoided by configuring
these I/Os in analog mode. This is notably the case of ADC input pins which should be
configured as analog inputs.
Caution:
Any floating input pin can also settle to an intermediate voltage level or switch inadvertently,
as a result of external electromagnetic noise. To avoid current consumption related to
floating pins, they must either be configured in analog mode, or forced internally to a definite
digital value. This can be done either by using pull-up/down resistors or by configuring the
pins in output mode.
I/O dynamic current consumption
In addition to the internal peripheral current consumption measured previously (see ), the
I/Os used by an application also contribute to the current consumption. When an I/O pin
switches, it uses the current from the I/O supply voltage to supply the I/O pin circuitry and to
charge/discharge the capacitive load (internal or external) connected to the pin:
ISW = VDDIOx × fSW × C
where
I
is the current sunk by a switching I/O to charge/discharge the capacitive load
SW
V
is the I/O supply voltage
DDIOx
f
is the I/O switching frequency
SW
C is the total capacitance seen by the I/O pin: C = C + C
+ C
S
INT
EXT
C is the PCB board capacitance including the pad pin.
S
The test pin is configured in push-pull output mode and is toggled by software at a fixed
frequency.
206/340
DS12737 Rev 6
STM32L552xx
Electrical characteristics
On-chip peripheral current consumption
The current consumption of the on-chip peripherals is given in Table 82. The MCU is placed
under the following conditions:
•
•
All I/O pins are in Analog mode
The given value is calculated by measuring the difference of the current consumptions:
–
–
when the peripheral is clocked on
when the peripheral is clocked off
•
•
Ambient operating temperature and supply voltage conditions summarized in Table 24:
Voltage characteristics
The power consumption of the digital part of the on-chip peripherals is given in
Table 82. The power consumption of the analog part of the peripherals (where
applicable) is indicated in each related section of the datasheet.
Table 82. Peripheral current consumption
Low-power
Peripheral
Range 0
Range 1
Range 2
run and
sleep
Unit
Bus matrix
5.85
3.67
3.71
7.11
5.32
2.03
1.05
1.77
0.38
0.38
0.40
0.25
0.31
0.30
0.19
0.21
0.32
0.29
3.32
5.92
0.15
5.47
3.38
3.43
6.64
4.95
1.90
0.99
1.67
0.36
0.38
0.41
0.23
0.27
0.26
0.17
0.18
0.26
0.27
3.08
5.49
0.14
4.09
2.54
2.56
4.96
3.69
1.43
0.76
1.24
0.27
0.27
0.30
0.17
0.21
0.21
0.16
0.14
0.22
0.21
2.34
4.16
0.08
5.36
3.16
3.20
6.16
4.59
1.75
0.95
1.49
0.35
1.00
0.32
0.22
0.37
0.26
0.21
0.19
0.31
0.25
2.90
5.11
0.14
DMA1
DMA2
DMAMUX1
FLASH
SRAM1
CRC
TSC
GTZC
ICACHE
GPIOA
AHB
µA/MHz
GPIOB
GPIOC
GPIOD
GPIOE
GPIOF
GPIOG
GPIOH
SRAM2
ADC AHB clock domain
ADC independent clock domain
DS12737 Rev 6
207/340
307
Electrical characteristics
STM32L552xx
Table 82. Peripheral current consumption (continued)
Low-power
Peripheral
Range 0
Range 1
Range 2
run and
sleep
Unit
HASH
3.91
2.44
4.55
20.52
4.92
11.17
10.77
0.12
47.58
0.41
6.65
5.46
5.38
6.92
1.12
1.24
3.50
0.58
2.52
2.39
3.40
6.41
2.96
6.96
2.81
5.59
2.75
3.64
2.27
6.12
19.07
6.63
10.39
10.00
0.11
47.47
0.43
6.19
5.08
5.02
6.47
1.04
1.16
3.32
0.52
2.34
2.22
3.14
5.99
2.73
6.49
2.60
5.26
2.58
2.74
NA
3.44
NA
RNG AHB clock domain
RNG independent clock domain
SDMMC1 AHB clock domain
SDMMC1 independent clock domain
FMC
µA/MHz
NA
NA
NA
NA
NA
NA
AHB
7.82
7.61
0.04
55.06
0.36
4.67
3.82
3.78
4.86
0.79
0.86
2.50
0.40
1.78
1.69
2.39
4.50
2.12
4.86
1.99
3.95
1.99
9.90
9.57
1.00
350.76
0.61
5.81
4.75
4.73
6.08
0.98
0.98
3.08
0.48
2.25
2.16
3.03
5.53
2.57
6.09
2.48
4.85
2.45
(Cont)
µA/MHz
OSPI1 AHB clock domain
OPSPI1 independent clock domain
ALL AHB peripherals
AHB to APB1 bridge
TIM2
TIM3
TIM4
TIM5
TIM6
TIM7
RTCAPB
WWDG
APB1
µA/MHz
SPI2
SPI3
USART2 APB clock domain
USART2 independent clock domain
USART3 APB clock domain
USART3 independent clock domain
UART4 APB clock domain
UART4 independent clock domain
UART5 APB clock domain
208/340
DS12737 Rev 6
STM32L552xx
Electrical characteristics
Table 82. Peripheral current consumption (continued)
Low-power
run and
sleep
Peripheral
Range 0
Range 1
Range 2
Unit
UART5 independent clock domain
I2C1 APB clock domain
I2C1 independent clock domain
I2C2 APB clock domain
I2C2 independent clock domain
I2C3 APB clock domain
I2C3 independent clock domain
CRS
5.59
1.42
3.47
1.32
3.33
1.14
2.75
0.35
1.54
2.89
0.34
1.10
3.37
1.66
3.43
1.40
3.31
1.36
3.80
1.02
3.16
7.99
0.16
3.51
4.53
2.67
6.64
0.75
9.40
2.69
8.94
3.16
5.19
1.34
3.22
1.24
3.11
1.05
2.58
0.30
1.44
2.69
0.36
1.01
3.18
1.54
3.24
1.28
3.11
1.26
3.58
0.93
2.98
7.41
0.22
3.25
6.08
2.46
6.16
0.71
8.74
2.51
8.34
2.92
3.90
1.00
2.46
0.93
2.37
0.81
1.97
0.22
1.03
2.03
0.23
0.78
2.39
1.19
2.44
0.97
2.34
0.96
2.66
0.74
2.21
5.56
3.20
NA
4.79
1.22
3.12
1.10
3.06
0.90
2.61
0.50
1.22
2.43
1.00
0.87
3.07
1.61
2.99
1.24
2.90
1.15
3.35
0.94
2.80
6.70
4.05
NA
PWR
DAC1
OPAMP
LPTIM1 APB clock domain
LPTIM1 independent clock domain
LPUART1 APB clock domain
LPUART1 independent clock domain
I2C4 APB clock domain
I2C4 independent clock domain
LPTIM2 APB clock domain
LPTIM2 independent clock domain
LPTIM3 APB clock domain
LPTIM3 independent clock domain
FDCAN APB clock domain
FDCAN independent clock domain
USBFS APB clock domain
USBFS independent clock domain
UCPD1
APB1
(Cont)
µA/MHz
NA
NA
1.84
4.68
0.54
6.57
1.90
6.29
2.23
NA(1)
8.43
0.67
8.33
2.43
8.06
3.09
AHB to APB2 bridge
SYSCFG
TIM1
APB2
µA/MHz
SPI1
TIM8
USART1 APB clock domain
DS12737 Rev 6
209/340
307
Electrical characteristics
STM32L552xx
Table 82. Peripheral current consumption (continued)
Low-power
Peripheral
Range 0
Range 1
Range 2
run and
sleep
Unit
USART1 independent clock domain
7.01
4.93
3.27
3.76
3.04
2.20
3.32
2.14
8.18
275.73
6.54
4.60
3.05
3.49
2.84
2.92
3.07
2.94
7.61
256.25
4.91
3.45
2.29
2.62
2.12
2.85
2.30
3
6.01
4.45
2.83
3.40
0.50
2.5
TIM15
TIM16
TIM17
APB2
(Cont)
SAI1 APB clock domain
SAI1 independent clock domain
SAI2 APB clock domain
SAI2 independent clock domain
DFSDM1
µA/MHz
2.99
3
5.73
188.42
7.42
233
ALL
-
1. The UCPD1 is always clocked by the HSI16.
210/340
DS12737 Rev 6
STM32L552xx
Electrical characteristics
5.3.7
Wakeup time from low-power modes and voltage scaling
transition times
The wakeup times given in Table 83 are the latency between the event and the execution of
the first user instruction.
The device goes in low-power mode after the WFE (wait for event) instruction.
(1)
Table 83. Low-power mode wakeup timings
-
Parameter
Conditions
Typ
Max
Unit
Wakeup time
from Sleep
mode to Run
mode
-
14
17
Number of
CPU cycles
Wakeup time
from Low-
power sleep
mode to Low-
power
Sleep
Sleep Power Down
(SLEEP_PD=1
14
17
in FLASH_ACR) and with clock
MSI = 2 MHz
run mode
MSI48
Range 1
5.83
5.23
18.48
17.56
23.36
1.79
2.79
2.43
2.80
9.66
9.74
9.22
21.84
20.98
25.48
5.58
6.68
5.69
6.18
11.04
81.2
17.8
6.26
5.46
HSI16
Flash
MSI24
18.96
17.94
24.59
2.16
Range 2
Range 1
Range 2
Range 1
Range 2
Range 1
Range 2
HSI16
MSI4
Stop 0
MSI48
HSI16
MSI24
HSI16
MSI4
3.01
SRAM1
2.82
3.03
10.88
10.22
9.67
MSI48
HSI16
MSI24
HSI16
MSI4
µs
Flash
22.63
21.81
26.34
5.95
MSI48
HSI16
MSI24
HSI16
MSI4
Stop 1
7.06
SRAM1
6.24
6.88
11.99
82.5
Flash
Low Power
Run (LPR=1)
MSI2
SRAM1
19
DS12737 Rev 6
211/340
307
Electrical characteristics
STM32L552xx
Unit
(1)
Table 83. Low-power mode wakeup timings (continued)
-
Parameter
Conditions
Typ
Max
MSI48
11.20
10.35
23.76
22.24
27.81
6.19
11.64
10.77
24.15
22.62
28.46
6.61
Range 1
Range 2
Range 1
Range 2
Range 2
HSI16
MSI24
HSI16
MSI4
Flash
Stop 2
MSI48
HSI16
MSI24
HSI16
MSI4
7.33
7.75
SRAM1
Flash
6.31
6.64
µs
6.89
7.22
11.69
52.5
12.36
55.73
55.78
55.74
55.73
292.42
MSI8
MSI4
52.58
52.5
Standby
MSI8
Flash with
SRAM2
Range 2
Range 2
MSI4
52.60
276.48
Shutdown
Flash
MSI4
1. Guaranteed by characterization results.
(1)
Table 84. Regulator modes transition times
Symbol
Parameter
Conditions
Typ Max Unit
Wakeup time from Low- power run
mode to Run mode(2)
tWULPRUN
Code run with MSI 2 MHz
Code run with MSI 24 MHz
5
7
μs
Regulator transition time from
Range 2 to Range 1 or
Range 1 to Range 2(3)
tVOST
20
40
1. Guaranteed by characterization results.
2. Time until REGLPF flag is cleared in PWR_SR2.
3. Time until VOSF flag is cleared in PWR_SR2.
(1)
Table 85. Wakeup time using USART/LPUART
Parameter Conditions
Symbol
Typ Max Unit
Wakeup time needed to calculate Stop mode 0
the maximum USART/LPUART
baudrate allowing to wakeup up
-
1.7
tWUUSART
μs
from stop mode when
USART/LPUART clock source is
HSI
tWULPUART
Stop mode 1/2
-
8.5
1. Guaranteed by design.
212/340
DS12737 Rev 6
STM32L552xx
Electrical characteristics
5.3.8
External clock source characteristics
High-speed external user clock generated from an external source
In bypass mode the HSE oscillator is switched off and the input pin is a standard GPIO.
The external clock signal has to respect the I/O characteristics in Section 5.3.15. However,
the recommended clock input waveform is shown in Figure 33: High-speed external clock
source AC timing diagram.
(1)
Table 86. High-speed external user clock characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Voltage scaling
Range 0 and 1
-
8
48
User external clock
source frequency
fHSE_ext
MHz
Voltage scaling
Range 2
-
8
-
26
OSC_IN input pin high
level voltage
VHSEH
VHSEL
-
-
0.7 VDDIOx
VDDIOx
V
OSC_IN input pin low
level voltage
VSS
7
-
0.3 VDDIOx
Voltage scaling
Range 0 and 1
-
-
-
tw(HSEH)
tw(HSEL)
OSC_IN high or low time
ns
Voltage scaling
Range 2
18
-
1. Guaranteed by design.
Figure 33. High-speed external clock source AC timing diagram
t
w(HSEH)
V
HSEH
90%
10%
V
HSEL
t
t
t
t
r(HSE)
f(HSE)
w(HSEL)
T
HSE
MS19214V2
DS12737 Rev 6
213/340
307
Electrical characteristics
STM32L552xx
Low-speed external user clock generated from an external source
In bypass mode the LSE oscillator is switched off and the input pin is a standard GPIO.
The external clock signal has to respect the I/O characteristics in Section 5.3.15. However,
the recommended clock input waveform is shown in Figure 34.
(1)
Table 87. Low-speed external user clock characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
User external clock source
frequency
fLSE_ext
-
-
32.768
1000
kHz
OSC32_IN input pin high
level voltage
VLSEH
VLSEL
tw(LSEH)
-
-
-
0.7 VDDIOx
VSS
-
-
-
VDDIOx
0.3 VDDIOx
-
V
OSC32_IN input pin low level
voltage
OSC32_IN high or low time
250
ns
tw(LSEL)
1. Guaranteed by design.
Figure 34. Low-speed external clock source AC timing diagram
t
w(LSEH)
V
LSEH
90%
10%
V
LSEL
t
t
t
r(LSE)
f(LSE)
t
w(LSEL)
T
LSE
MS19215V2
214/340
DS12737 Rev 6
STM32L552xx
Electrical characteristics
High-speed external clock generated from a crystal/ceramic resonator
The high-speed external (HSE) clock can be supplied with a 4 to 48 MHz crystal/ceramic
resonator oscillator. All the information given in this paragraph are based on design
simulation results obtained with typical external components specified in Table 88. In the
application, the resonator and the load capacitors have to be placed as close as possible to
the oscillator pins in order to minimize output distortion and startup stabilization time. Refer
to the crystal resonator manufacturer for more details on the resonator characteristics
(frequency, package, accuracy).
(1)
Table 88. HSE oscillator characteristics
Symbol
fOSC_IN Oscillator frequency
RF Feedback resistor
Parameter
Conditions(2)
Min
Typ
Max
Unit
-
4
-
8
200
-
48
-
MHz
-
kΩ
During startup(3)
-
5.5
VDD = 3 V,
Rm = 30 Ω,
CL = 10 pF@8 MHz
-
-
-
-
-
0.44
0.45
0.68
0.94
1.77
-
-
-
-
-
VDD = 3 V,
Rm = 45 Ω,
CL = 10 pF@8 MHz
VDD = 3 V,
IDD(HSE) HSE current consumption
mA
Rm = 30 Ω,
CL = 5 pF@48 MHz
VDD = 3 V,
Rm = 30 Ω,
CL = 10 pF@48 MHz
VDD = 3 V,
Rm = 30 Ω,
CL = 20 pF@48 MHz
Maximum critical crystal
transconductance
Gm
Startup
-
-
-
1.5
-
mA/V
ms
(4)
tSU(HSE)
Startup time
VDD is stabilized
2
1. Guaranteed by design.
2. Resonator characteristics given by the crystal/ceramic resonator manufacturer.
3. This consumption level occurs during the first 2/3 of the tSU(HSE) startup time
4. tSU(HSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 8 MHz
oscillation is reached. This value is measured for a standard crystal resonator and it can vary significantly
with the crystal manufacturer
For C and C , it is recommended to use high-quality external ceramic capacitors in the
L1
L2
5 pF to 20 pF range (typ.), designed for high-frequency applications, and selected to match
the requirements of the crystal or resonator (see Figure 35). C and C are usually the
L1
L2
same size. The crystal manufacturer typically specifies a load capacitance which is the
series combination of C and C . PCB and MCU pin capacitance must be included (10 pF
L1
L2
can be used as a rough estimate of the combined pin and board capacitance) when sizing
and C .
C
L1
L2
DS12737 Rev 6
215/340
307
Electrical characteristics
STM32L552xx
Note:
For information on selecting the crystal, refer to the application note AN2867 “Oscillator
design guide for ST microcontrollers” available from the ST website www.st.com.
Figure 35. Typical application with an 8 MHz crystal
Resonator with integrated
capacitors
CL1
OSC_IN
fHSE
Bias
controlled
gain
8 MHz
resonator
RF
(1)
OSC_OUT
REXT
CL2
MS19876V1
1. REXT value depends on the crystal characteristics.
Low-speed external clock generated from a crystal resonator
The low-speed external (LSE) clock can be supplied with a 32.768 kHz crystal resonator
oscillator. All the information given in this paragraph are based on design simulation results
obtained with typical external components specified in Table 89. In the application, the
resonator and the load capacitors have to be placed as close as possible to the oscillator
pins in order to minimize output distortion and startup stabilization time. Refer to the crystal
resonator manufacturer for more details on the resonator characteristics (frequency,
package, accuracy).
216/340
DS12737 Rev 6
STM32L552xx
Electrical characteristics
(1)
Table 89. LSE oscillator characteristics (fLSE = 32.768 kHz)
Symbol
Parameter
Conditions(2)
Min
Typ
Max Unit
LSEDRV[1:0] = 00
Low drive capability
-
250
-
LSEDRV[1:0] = 01
Medium low drive capability
-
-
-
-
-
-
315
-
IDD(LSE) LSE current consumption
nA
LSEDRV[1:0] = 10
Medium high drive capability
500
-
LSEDRV[1:0] = 11
High drive capability
630
-
LSEDRV[1:0] = 00
Low drive capability
-
-
-
0.5
LSEDRV[1:0] = 01
Medium low drive capability
0.75
µA/V
1.7
Maximum critical crystal
gm
Gmcritmax
LSEDRV[1:0] = 10
Medium high drive capability
LSEDRV[1:0] = 11
High drive capability
-
-
-
2.7
(3)
tSU(LSE)
Startup time
VDD is stabilized
2
-
s
1. Guaranteed by design.
2. Refer to the note and caution paragraphs below the table, and to the application note AN2867 “Oscillator
design guide for ST microcontrollers”.
3. tSU(LSE) is the startup time measured from the moment it is enabled (by software) to a stabilized
32.768 kHz oscillation is reached. This value is measured for a standard crystal and it can vary significantly
with the crystal manufacturer
Note:
For information on selecting the crystal, refer to the application note AN2867 “Oscillator
design guide for ST microcontrollers” available from the ST website www.st.com.
Figure 36. Typical application with a 32.768 kHz crystal
Resonator with integrated
capacitors
CL1
OSC32_IN
fLSE
Drive
32.768 kHz
resonator
programmable
amplifier
OSC32_OUT
CL2
MS30253V2
Note:
An external resistor is not required between OSC32_IN and OSC32_OUT and it is forbidden
to add one.
DS12737 Rev 6
217/340
307
Electrical characteristics
STM32L552xx
5.3.9
Internal clock source characteristics
The parameters given in Table 90 are derived from tests performed under ambient
temperature and supply voltage conditions summarized in Table 27: General operating
conditions. The provided curves are characterization results, not tested in production.
High-speed internal (HSI16) RC oscillator
(1)
Table 90. HSI16 oscillator characteristics
Symbol
Parameter
Conditions
Min
Typ
Max Unit
fHSI16
HSI16 Frequency
VDD=3.0 V, TA=30 °C
15.88
-
16.08 MHz
Trimming code is not a
multiple of 64
0.2
-4
0.3
-6
0.4
%
TRIM
HSI16 user trimming step
Trimming code is a
multiple of 64
-8
DuCy(HSI16)(2) Duty Cycle
-
45
-1
-2
-
-
-
55
1
%
%
TA= 0 to 85 °C
TA= -40 to 125 °C
HSI16 oscillator frequency
drift over temperature
∆Temp(HSI16)
1.5
%
%
HSI16 oscillator frequency
drift over VDD
∆VDD(HSI16)
VDD=1.62 V to 3.6 V
-0.1
-
0.05
1.2
5
HSI16 oscillator start-up
time
tsu(HSI16)(2)
tstab(HSI16)(2)
IDD(HSI16)(2)
-
-
-
-
-
-
0.8
3
μs
μs
μA
HSI16 oscillator
stabilization time
HSI16 oscillator power
consumption
155
190
1. Guaranteed by characterization results.
2. Guaranteed by design.
218/340
DS12737 Rev 6
STM32L552xx
Electrical characteristics
Figure 37. HSI16 frequency versus temperature
MHz
16.4
+2 %
+1.5 %
+1 %
16.3
16.2
16.1
16
15.9
15.8
15.7
15.6
-1 %
-1.5 %
-2 %
-40
-20
0
20
40
60
80
100
120 °C
Mean
min
max
MSv39299V2
DS12737 Rev 6
219/340
307
Electrical characteristics
STM32L552xx
Multi-speed internal (MSI) RC oscillator
Table 91. MSI oscillator characteristics(1)
Conditions
Symbol
Parameter
Min
Typ
Max Unit
Range 0
Range 1
Range 2
Range 3
Range 4
Range 5
Range 6
Range 7
Range 8
Range 9
Range 10
Range 11
Range 0
Range 1
Range 2
Range 3
Range 4
Range 5
Range 6
Range 7
Range 8
Range 9
Range 10
Range 11
TA= -0 to 85 °C
98.7
100
200
101.3
197.4
202.6
kHz
405.2
394.8
400
7896
800
810.4
1.013
2.026
4.052
0.987
1
1.974
2
MSI mode
3.948
4
7.896
8
8.104
MHz
16.21
15.79
16
23.69
24
24.31
32.42
48.62
-
31.58
32
MSI frequency
after factory
calibration, done
at VDD=3 V and
TA=30 °C
47.38
48
fMSI
-
98.304
196.608
393.216
786.432
1.016
1.999
3.998
7.995
15.991
23.986
32.014
48.005
-
-
-
kHz
-
-
-
-
-
-
-
-
PLL mode
XTAL=
32.768 kHz
-
-
-
-
MHz
-
-
-
-
-
-
-
-
MSI oscillator
frequency drift
over
-3.5
3
∆
TEMP(MSI)(2)
MSI mode
%
6
TA= -40 to 125 °C
-8
-
temperature
220/340
DS12737 Rev 6
STM32L552xx
Symbol
Electrical characteristics
Table 91. MSI oscillator characteristics(1) (continued)
Parameter
Conditions
Min
Typ
Max Unit
V
DD=1.62 V
-1.2
-
to 3.6 V
Range 0 to 3
0.5
VDD=2.4 V
to 3.6 V
-0.5
-2.5
-0.8
-5
-
-
-
-
MSI oscillator
frequency drift
VDD=1.62 V
to 3.6 V
∆
VDD(MSI)(2) over VDD
MSI mode Range 4 to 7
0.7
1
%
VDD=2.4 V
(reference is
3 V)
to 3.6 V
VDD=1.62 V
to 3.6 V
Range 8 to 11
VDD=2.4 V
to 3.6 V
-1.6
-
-
Frequency
variation in
sampling
mode(3)
TA= -40 to 85 °C
1
2
4
∆FSAMPLING
MSI mode
%
(MSI)(2)(4)
TA= -40 to 125 °C
-
-
2
RMS cycle-to-
cycle jitter
CC jitter(MSI)(4)
PLL mode Range 11
-
60
-
ps
ps
P jitter(MSI)(4) RMS Period jitter PLL mode Range 11
-
-
-
-
-
-
-
-
-
-
-
-
-
-
50
10
5
-
20
10
8
Range 0
Range 1
Range 2
4
MSI oscillator
start-up time
t
SU(MSI)(4)
us
Range 3
3
7
Range 4 to 7
Range 8 to 11
3
6
2.5
6
10 % of final
frequency
-
-
-
-
-
-
0.25
0.5
-
0.5
MSI oscillator
stabilization time Range 11
PLL mode 5 % of final
tSTAB(MSI)(4)
1.25 ms
2.5
frequency
1 % of final
frequency
DS12737 Rev 6
221/340
307
Electrical characteristics
STM32L552xx
Max Unit
Table 91. MSI oscillator characteristics(1) (continued)
Symbol
Parameter
Conditions
Min
Typ
Range 0
Range 1
Range 2
Range 3
Range 4
Range 5
Range 6
Range 7
Range 8
Range 9
Range 10
Range 11
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0.6
0.8
1.2
1.9
4.7
6.5
11
1
1.2
1.7
2.5
6
MSI oscillator
power
consumption
9
MSI and
PLL mode
IDD(MSI)(4)
µA
15
18.5
62
25
80
85
110
130
190
110
155
1. Guaranteed by characterization results.
2. This is a deviation for an individual part once the initial frequency has been measured.
3. Sampling mode means Low-power run/Low-power sleep modes with Temperature sensor disable.
4. Guaranteed by design.
Figure 38. Typical current consumption versus MSI frequency
222/340
DS12737 Rev 6
STM32L552xx
Electrical characteristics
High-speed internal 48 MHz (HSI48) RC oscillator
(1)
Table 92. HSI48 oscillator characteristics
Symbol
Parameter
Conditions
Min
Typ
Max Unit
fHSI48
TRIM
HSI48 Frequency
VDD=3.0V, TA=30°C
-
-
-
48
-
MHz
%
HSI48 user trimming step
0.11(2) 0.18(2)
USER TRIM HSI48 user trimming
COVERAGE coverage
±32 steps
-
±3(3)
45(2)
-
±3.5(3)
-
%
%
DuCy(HSI48) Duty Cycle
-
-
55(2)
±3(3)
VDD = 3.0 V to 3.6 V,
Accuracy of the HSI48
ACCHSI48_REL oscillator over temperature
(factory calibrated)
TA = –15 to 85 °C
%
VDD = 1.65 V to 3.6 V,
TA = –40 to 125 °C
-
-
±4.5(3)
VDD = 3 V to 3.6 V
-
-
0.025(3) 0.05(3)
HSI48 oscillator frequency
DVDD(HSI48)
%
0.05(3)
0.1(3)
drift with VDD
VDD = 1.65 V to 3.6 V
HSI48 oscillator start-up
tsu(HSI48)
time
-
-
-
-
2.5(2)
6(2)
μs
HSI48 oscillator power
IDD(HSI48)
340(2)
380(2) μA
consumption
Next transition jitter
NT jitter
PT jitter
Accumulated jitter on 28
-
-
-
-
+/-0.15(2)
-
-
ns
ns
cycles(4)
Paired transition jitter
Accumulated jitter on 56
cycles(4)
+/-0.25(2)
1. VDD = 3 V, TA = –40 to 125°C unless otherwise specified.
2. Guaranteed by design.
3. Guaranteed by characterization results.
4. Jitter measurement are performed without clock source activated in parallel.
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Electrical characteristics
STM32L552xx
Figure 39. HSI48 frequency versus temperature
%
6
4
2
0
-2
-4
-6
-50
-30
-10
10
30
50
70
90
110
130
°C
Avg
min
max
MSv40989V1
Low-speed internal (LSI) RC oscillator
(1)
Table 93. LSI oscillator characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
V
DD = 3.0 V,
31.04
-
32.96
34
TA = 30 °C
fLSI
LSI Frequency
kHz
VDD = 1.62 to 3.6 V,
TA = -40 to 125 °C
29.5
-
LSI oscillator start-up
time
tSU(LSI)(2)
tSTAB(LSI)(2)
IDD(LSI)(2)
-
-
-
-
80
130
180
180
μs
μs
nA
LSI oscillator stabilization
time
5% of final frequency
-
125
110
LSI oscillator power
consumption
1. Guaranteed by characterization results.
2. Guaranteed by design.
224/340
DS12737 Rev 6
STM32L552xx
Electrical characteristics
5.3.10
PLL characteristics
The parameters given in Table 94 are derived from tests performed under temperature and
V
supply voltage conditions summarized in Table 27: General operating conditions.
DD
(1)
Table 94. PLL, PLLSAI1, PLLSAI2 characteristics
Symbol
fPLL_IN
Parameter
Conditions
Min
Typ Max Unit
PLL input clock(2)
-
-
2.66
45
-
16
55
MHz
%
PLL input clock duty cycle
-
Voltage scaling Range 1 2.0645
-
80
fPLL_P_OUT PLL multiplier output clock P Voltage scaling Range 0 2.0645
Voltage scaling Range 2 2.0645
-
110
26
-
Voltage scaling Range 1
fPLL_Q_OUT PLL multiplier output clock Q Voltage scaling Range 0
Voltage scaling Range 2
8
8
8
8
8
8
64
64
-
-
-
80
110
26
-
MHz
Voltage scaling Range 1
-
80
fPLL_R_OUT PLL multiplier output clock R Voltage scaling Range 0
Voltage scaling Range 2
-
110
26
-
Voltage scaling Range 1
fVCO_OUT PLL VCO output
-
344
128
40
Voltage scaling Range 2
-
tLOCK
Jitter
PLL lock time
-
15
40
30
150
200
300
520
μs
RMS cycle-to-cycle jitter
RMS period jitter
-
-
System clock 80 MHz
±ps
-
-
VCO freq = 64 MHz
VCO freq = 96 MHz
VCO freq = 192 MHz
VCO freq = 344 MHz
-
200
260
380
650
-
PLL power consumption on
VDD
IDD(PLL)
μA
(1)
-
-
1. Guaranteed by design.
2. Take care of using the appropriate division factor M to obtain the specified PLL input clock values. The M
factor is shared between the 3 PLLs.
DS12737 Rev 6
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Electrical characteristics
STM32L552xx
5.3.11
Flash memory characteristics
(1)
Table 95. Flash memory characteristics
Symbol
Parameter
Conditions
Typ
Max Unit
tprog
64-bit programming time
-
81.69
2.61
NA
83.35
2.67
NA
µs
Normal programming
Fast programming
Normal programming
Fast programming
One row (64 double
word) programming time
tprog_row
20.91
NA
21.34
NA
One page (4 Kbytes)
programming time
ms
tprog_page
tERASE
tprog_bank
tME
Page (4 Kbytes) erase
time
-
22.02
24.47
Normal programming
Fast programming
2.68
NA
2.73
NA
One bank (1 Mbyte)
programming time
s
Mass erase time
(one or two banks)
-
22.13
24.59 ms
NA
Write mode
Erase mode
Write mode
Erase mode
3.1
3.1
NA
NA
Average consumption
from VDD
NA
mA
NA
IDD
Maximum current (peak)
NA
1. Guaranteed by design.
Table 96. Flash memory endurance and data retention
Symbol
Parameter
Endurance
Conditions
Min(1)
Unit
NEND
TA = –40 to +105 °C
10
30
15
7
kcycles
1 kcycle(2) at TA = 85 °C
1 kcycle(2) at TA = 105 °C
1 kcycle(2) at TA = 125 °C
10 kcycles(2) at TA = 55 °C
10 kcycles(2) at TA = 85 °C
10 kcycles(2) at TA = 105 °C
tRET
Data retention
Years
30
15
10
1. Guaranteed by characterization results.
2. Cycling performed over the whole temperature range.
226/340
DS12737 Rev 6
STM32L552xx
Electrical characteristics
5.3.12
EMC characteristics
Susceptibility tests are performed on a sample basis during device characterization.
Functional EMS (electromagnetic susceptibility)
While a simple application is executed on the device (toggling 2 LEDs through I/O ports).
the device is stressed by two electromagnetic events until a failure occurs. The failure is
indicated by the LEDs:
•
Electrostatic discharge (ESD) (positive and negative) is applied to all device pins until
a functional disturbance occurs. This test is compliant with the IEC 61000-4-2 standard.
•
FTB: A Burst of Fast Transient voltage (positive and negative) is applied to V and
DD
V
through a 100 pF capacitor, until a functional disturbance occurs. This test is
SS
compliant with the IEC 61000-4-4 standard.
A device reset allows normal operations to be resumed.
The test results are given in Table 97. They are based on the EMS levels and classes
defined in application note AN1709.
Table 97. EMS characteristics
Level/
Class
Symbol
Parameter
Conditions
VDD = 3.3 V, TA = +25 °C,
fHCLK = 110 MHz,
conforming to IEC 61000-4-2
Voltage limits to be applied on any I/O pin
to induce a functional disturbance
VFESD
3B
5A
Fast transient voltage burst limits to be
VEFTB applied through 100 pF on VDD and VSS
pins to induce a functional disturbance
VDD = 3.3 V, TA = +25 °C,
fHCLK = 110 MHz,
conforming to IEC 61000-4-4
Designing hardened software to avoid noise problems
EMC characterization and optimization are performed at component level with a typical
application environment and simplified MCU software. It should be noted that good EMC
performance is highly dependent on the user application and the software in particular.
Therefore it is recommended that the user applies EMC software optimization and
prequalification tests in relation with the EMC level requested for his application.
Software recommendations
The software flowchart must include the management of runaway conditions such as:
•
•
•
Corrupted program counter
Unexpected reset
Critical Data corruption (control registers...)
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Electrical characteristics
STM32L552xx
Prequalification trials
Most of the common failures (unexpected reset and program counter corruption) can be
reproduced by manually forcing a low state on the NRST pin or the Oscillator pins for 1
second.
To complete these trials, ESD stress can be applied directly on the device, over the range of
specification values. When unexpected behavior is detected, the software can be hardened
to prevent unrecoverable errors occurring (see application note AN1015).
Electromagnetic Interference (EMI)
The electromagnetic field emitted by the device are monitored while a simple application is
executed (toggling 2 LEDs through the I/O ports). This emission test is compliant with
IEC 61967-2 standard which specifies the test board and the pin loading.
Table 98. EMI characteristics
Max vs
Monitored frequency
[fHSE/fHCLK
]
Symbol Parameter
Conditions
Unit
band
8 MHz / 110 MHz
0.1 MHz to 30 MHz
30 MHz to 130 MHz
130 MHz to 1 GHz
1 GHz to 2 GHz
EMI Level
4
0
V
DD = 3.6 V,
TA = 25°C,
LQFP144 package
compliant with IEC
61967-2
dBμV
SEMI
Peak level
16
11
3.5
-
5.3.13
Electrical sensitivity characteristics
Based on three different tests (ESD, LU) using specific measurement methods, the device is
stressed in order to determine its performance in terms of electrical sensitivity.
Electrostatic discharge (ESD)
Electrostatic discharges (a positive then a negative pulse separated by 1 second) are
applied to the pins of each sample according to each pin combination. The sample size
depends on the number of supply pins in the device (3 parts × (n+1) supply pins). This test
conforms to the ANSI/JEDEC standard.
Table 99. ESD absolute maximum ratings
Maximum
Symbol
Ratings
Conditions
Class
Unit
value(1)
Electrostatic discharge
voltage (human body model) ANSI/ESDA/JEDEC JS-001
TA = +25 °C, conforming to
VESD(HBM)
2
2000
TA = +25 °C,
conforming to
ANSI/ESDA/JEDEC
JS-002
LQFP144, LQFP100,
WLCSP81
V
Electrostatic discharge
VESD(CDM) voltage (charge device
model)
C1
250
500
Other packages
C2a
1. Guaranteed by characterization results.
228/340
DS12737 Rev 6
STM32L552xx
Electrical characteristics
Static latch-up
Two complementary static tests are required on three parts to assess the latch-up
performance:
•
•
A supply overvoltage is applied to each power supply pin.
A current injection is applied to each input, output and configurable I/O pin.
These tests are compliant with EIA/JESD 78E IC latch-up standard.
Table 100. Electrical sensitivities
Symbol
Parameter
Conditions
Class
LU
Static latch-up class
TA = +105 °C conforming to JESD78E
Class II level A
5.3.14
I/O current injection characteristics
As a general rule, current injection to the I/O pins, due to external voltage below V or
SS
above V
(for standard, 3.3 V-capable I/O pins) should be avoided during normal
DDIOx
product operation. However, in order to give an indication of the robustness of the
microcontroller in cases when abnormal injection accidentally happens, susceptibility tests
are performed on a sample basis during device characterization.
Functional susceptibility to I/O current injection
While a simple application is executed on the device, the device is stressed by injecting
current into the I/O pins programmed in floating input mode. While current is injected into
the I/O pin, one at a time, the device is checked for functional failures.
The failure is indicated by an out of range parameter: ADC error above a certain limit (higher
than 5 LSB TUE), out of conventional limits of induced leakage current on adjacent pins (out
of the -5 µA/+0 µA range) or other functional failure (for example reset occurrence or
oscillator frequency deviation).
The characterization results are given in Table 101.
Negative induced leakage current is caused by negative injection and positive induced
leakage current is caused by positive injection.
Table 101. I/O current injection susceptibility
Functional
susceptibility
Symbol
Description
Unit
Negative Positive
injection injection
Injected current on all pins except TT_a, PB0, PB15,
PE9, PG0
-5
NA
(1)
IINJ
mA
Injected current on pins PB0, PB15, PE9, PG0
Injected current on TT_a pins
0
NA
0
-5
1. Guaranteed by characterization.
DS12737 Rev 6
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307
5.3.15
I/O port characteristics
General input/output characteristics
Unless otherwise specified, the parameters given in Table 102 are derived from tests performed under the conditions summarized
in Table 27: General operating conditions. All I/Os are designed as CMOS- and TTL-compliant.
Table 102. I/O static characteristics
Sym
bol
Parameter
Conditions
Min
Typ
Max
Unit
(2)
1.62 V < VDDIOx < 3.6 V
1.62 V < VDDIOx < 3.6 V
1.08 V < VDDIOx < 1.62 V
1.62 V < VDDIOx < 3.6 V
1.62 V < VDDIOx < 3.6 V
1.08 V < VDDIOx < 1.62 V
1.62 V < VDDIOx < 3.6 V
1.62 V < VDDIOx < 3.6 V
1.08 V < VDDIOx < 1.62 V
1.62 V < VDDIOx < 3.6 V
1.08 V < VDDIOx < 1.62 V
-
-
-
-
-
-
-
-
-
-
-
-
0.3×VDDIOx
All IOs except FT_c
-
0.39×VDDIOx-0.06(2)
0.43×VDDIOx-0.1(2)
-
I/O input low level
voltage
(1)
VIL
V
(2)
-
0.3×VDDIOX
(2)
FT_c
-
0.25×VDDIOX
(2)
-
0.2×VDDIOX
(2)
0.7×VDDIOx
-
-
All IOs except FT_c
FT_c
0.49×VDDIOX+0.26(2)
0.61×VDDIOX+0.05(2)
I/O input high level
voltage
(1)
VIH
-
V
(2)
0.7×VDDIOX
5
5
(2)
0.7×VDDIOX
TT_xx, FT_xx and
NRST
1.62 V < VDDIOx < 3.6 V
1.08 V < VDDIOx < 1.62 V
-
-
200
150
-
-
(2)
Vhys
Input hysteresis
mV
FT_sx
Table 102. I/O static characteristics (continued)
Sym
bol
Parameter
Conditions
Min
Typ
Max
Unit
(4)(5)
0 < VIN ≤ Max(VDDXXX
)
-
-
-
-
±100
650
FT_xx(3)
FT_u
Max(VDDXXX) ≤ VIN ≤ Max(VDDXXX) + 1 V(4)(5)
Max(VDDXXX) + 1 V < VIN ≤ 5.5 V(4)(5)
-
-
200
(4)(5)
0 <VIN ≤ Max(VDDXXX
)
-
-
±150
2500(6)
250(6)
±150
Max(VDDXXX) ≤ VIN ≤ Max(VDDXXX) +1 V(4)(5)
-
-
Max(VDDXXX) +1 V < VIN ≤ 5.5 V(4)(5)(7)
-
-
Input leakage
current
(5)
Ilkg
V
IN ≤ Max(VDDXXX
)
-
-
nA
TT_xx
Max(VDDXXX) ≤ VIN < 3.6 V(5)
-
-
2000(2)
(8)
OPAMPx_VINM(x=1,2)
FT_c
-
-
-
(3)
0 <VIN ≤ Max(VDDXXX
)
-
-
2000
3000
4500
9000
55
Max(VDDXXX) < VIN ≤ 5 V(3)(5)(6)
-
-
(5)
0 <VIN ≤ Max(VDDXXX
)
-
-
FT_d
Max(VDDXXX) < VIN ≤ 5.5 V(3)(4)(5)
-
-
RPU Weak pull-up equivalent resistor
RPD Weak pull-down equivalent resistor
CIO I/O pin capacitance
VIN = VSS
25
25
-
40
40
5
kΩ
kΩ
pF
VIN = VDDIOx
55
-
-
1. Refer to Figure 40: I/O input characteristics.
2. Guaranteed by design.
3. All FT_xx IO except FT_u and FT_c.
4. This value represents the pad leakage of the IO itself. The total product pad leakage is provided by this formula: ITotal_Ileak_max = 10 μA + [number of IOs where VIN is
applied on the pad] × Ilkg(Max).
5. Max(VDDXXX) is the maximum value of all the I/O supplies. Refer to Table: Legend/Abbreviations used in the pinout table.
6. To sustain a voltage higher than MIN(VDD, VDDA, VDDIO2 and VDDUSB) +0.3 V, the internal Pull-up and Pull-Down resistors must be disabled.
7. Pull-up and pull-down resistors are designed with a true resistance in series with a switchable PMOS/NMOS. This PMOS/NMOS contribution to the series resistance is
minimal (~10% order).
8. Refer to Ibias in Table 119: OPAMP characteristics for the values of the OPAMP dedicated input leakage current.
Electrical characteristics
STM32L552xx
All I/Os are CMOS- and TTL-compliant (no software configuration required). Their
characteristics cover more than the strict CMOS-technology or TTL parameters. The
coverage of these requirements is shown in Figure 40 for standard I/Os, and in Figure 40 for
5 V tolerant I/Os.
Figure 40. I/O input characteristics
Vil – Vih all IO
TTL requirement Vih min = 2V
TTL requirement Vil max = 0.8V
MSv62973V1
Output driving current
The GPIOs (general purpose input/outputs) can sink or source up to ±8 mA, and sink or
source up to ± 20 mA (with a relaxed V /V ).
OL OH
In the user application, the number of I/O pins which can drive current must be limited to
respect the absolute maximum rating specified in Section 5.2:
•
The sum of the currents sourced by all the I/Os on V
plus the maximum
DDIOx,
consumption of the MCU sourced on V
cannot exceed the absolute maximum rating
DD,
ΣI
(see Table 24: Voltage characteristics).
VDD
•
The sum of the currents sunk by all the I/Os on V , plus the maximum consumption of
SS
the MCU sunk on V , cannot exceed the absolute maximum rating ΣI
(see
SS
VSS
Table 24: Voltage characteristics).
Output voltage levels
Unless otherwise specified, the parameters given in the table below are derived from tests
performed under the ambient temperature and supply voltage conditions summarized in
Table 27: General operating conditions. All I/Os are CMOS- and TTL-compliant (FT OR TT
unless otherwise specified).
232/340
DS12737 Rev 6
STM32L552xx
Symbol
Electrical characteristics
(1)
Table 103. Output voltage characteristics
Parameter Conditions
Output low level voltage for
Min
Max
Unit
CMOS port(2)
VOL
VOH
-
0.4
an I/O pin
|IIO| = 2 mA for FT_c
|IIO| = 8 mA for other I/Os
VDDIOx ≥ 2.7 V
Output high level voltage for
an I/O pin
VDDIOx-0.4
-
0.4
-
TTL port(2)
|IIO| = 2 mA for FT_c
|IIO|= 8 mA for other I/Os
VDDIOx ≥ 2.7 V
Output low level voltage for
an I/O pin
(3)
VOL
-
2.4
-
Output high level voltage for
an I/O pin
(3)
VOH
Output low level voltage for
an I/O pin
(3)
(3)
VOL
1.3
-
All I/Os except FT_c
|IIO| = 20 mA
VDDIOx ≥ 2.7 V
Output high level voltage for
an I/O pin
VOH
V
DDIOx-1.3
Output low level voltage for
an I/O pin
(3)
VOL
-
0.4
-
V
|IIO| = 1 mA for FT_c
|IIO| = 4 mA for other I/Os
1.62 V ≤ VDDIOx ≤ 3.6 V
Output high level voltage for
an I/O pin
(3)
VOH
VDDIOx-0.45
Output low level voltage for
an I/O pin
0.35 ₓ
VDDIOx
(3)
VOL
-
|IIO| = 1 mA for FT_c
|IIO| = 2 mA for other I/Os
1.08 V ≤ VDDIOx < 1.62 V
Output high level voltage for
an I/O pin
(3)
VOH
0.65ₓVDDIOx
-
|IIO| = 20 mA
VDDIOx ≥ 2.7 V
-
-
-
0.4
0.4
0.4
Output low level voltage for
an FT I/O pin in FM+ mode
(FT I/O with "f" option)
VOLFM+
|IIO| = 10 mA
1.62 V ≤ VDDIOx ≤ 3.6 V
(3)
|IIO| = 2 mA
1.08 V ≤ VDDIOx < 1.62 V
1. The IIO current sourced or sunk by the device must always respect the absolute maximum rating specified in Table 24:
Voltage characteristics, and the sum of the currents sourced or sunk by all the I/Os (I/O ports and control pins) must always
respect the absolute maximum ratings ΣIIO
.
2. TTL and CMOS outputs are compatible with JEDEC standards JESD36 and JESD52.
3. Guaranteed by design.
Input/output AC characteristics
The definition and values of input/output AC characteristics are given in Figure 41 and
Table 104, respectively.
Unless otherwise specified, the parameters given are derived from tests performed under
the ambient temperature and supply voltage conditions summarized in Table 27: General
operating conditions.
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307
Electrical characteristics
STM32L552xx
(1)(2)
Table 104. I/O AC characteristics (All I/Os except FT_c)
Speed Symbol
Parameter
Conditions
Min
Max
Unit
C=50 pF, 2.7 V≤VDDIOx≤3.6 V
C=50 pF, 1.62 V≤VDDIOx≤2.7 V
C=50 pF, 1.08 V≤VDDIOx≤1.62 V
C=10 pF, 2.7 V≤VDDIOx≤3.6 V
C=10 pF, 1.62 V≤VDDIOx≤2.7 V
C=10 pF, 1.08 V≤VDDIOx≤1.62 V
C=50 pF, 2.7 V≤VDDIOx≤3.6 V
C=50 pF, 1.62 V≤VDDIOx≤2.7 V
C=50 pF, 1.08 V≤VDDIOx≤1.62 V
C=10 pF, 2.7 V≤VDDIOx≤3.6 V
C=10 pF, 1.62 V≤VDDIOx≤2.7 V
C=10 pF, 1.08 V≤VDDIOx≤1.62 V
C=50 pF, 2.7 V≤VDDIOx≤3.6 V
C=50 pF, 1.62 V≤VDDIOx≤2.7 V
C=50 pF, 1.08 V≤VDDIOx≤1.62 V
C=10 pF, 2.7 V≤VDDIOx≤3.6 V
C=10 pF, 1.62 V≤VDDIOx≤2.7 V
C=10 pF, 1.08 V≤VDDIOx≤1.62 V
C=50 pF, 2.7 V≤VDDIOx≤3.6 V
C=50 pF, 1.62 V≤VDDIOx≤2.7 V
C=50 pF, 1.08 V≤VDDIOx≤1.62 V
C=10 pF, 2.7 V≤VDDIOx≤3.6 V
C=10 pF, 1.62 V≤VDDIOx≤2.7 V
C=10 pF, 1.08 V≤VDDIOx≤1.62 V
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
5
1
0.1
10
1.5
0.1
25
52
140
17
37
110
25
10
1
Maximum
frequency
Fmax
MHz
00
Output rise and
fall time
Tr/Tf
ns
MHz
ns
Maximum
frequency
Fmax
50
15
1
01
9
16
40
4.5
9
Output rise and
fall time
Tr/Tf
21
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DS12737 Rev 6
STM32L552xx
Electrical characteristics
(1)(2)
Table 104. I/O AC characteristics (All I/Os except FT_c)
(continued)
Speed Symbol
Parameter
Conditions
Min
Max
Unit
C=50 pF, 2.7 V≤VDDIOx≤3.6 V
C=50 pF, 1.62 V≤VDDIOx≤2.7 V
C=50 pF, 1.08 V≤VDDIOx≤1.62 V
C=10 pF, 2.7 V≤VDDIOx≤3.6 V
C=10 pF, 1.62 V≤VDDIOx≤2.7 V
C=10 pF, 1.08 V≤VDDIOx≤1.62 V
C=50 pF, 2.7 V≤VDDIOx≤3.6 V
C=50 pF, 1.62 V≤VDDIOx≤2.7 V
C=50 pF, 1.08 V≤VDDIOx≤1.62 V
C=10 pF, 2.7 V≤VDDIOx≤3.6 V
C=10 pF, 1.62 V≤VDDIOx≤2.7 V
C=10 pF, 1.08 V≤VDDIOx≤1.62 V
C=30 pF, 2.7 V≤VDDIOx≤3.6 V
C=30 pF, 1.62 V≤VDDIOx≤2.7 V
C=30 pF, 1.08 V≤VDDIOx≤1.62 V
C=10 pF, 2.7 V≤VDDIOx≤3.6 V
C=10 pF, 1.62 V≤VDDIOx≤2.7 V
C=10 pF, 1.08 V≤VDDIOx≤1.62 V
C=30 pF, 2.7 V≤VDDIOx≤3.6 V
C=30 pF, 1.62 V≤VDDIOx≤2.7 V
C=30 pF, 1.08 V≤VDDIOx≤1.62 V
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
50
25
5
Maximum
frequency
Fmax
MHz
100
37.5
5
10
5.8
11
28
Output rise and
fall time
Tr/Tf
ns
2.5
5
12
110
50
10
Maximum
frequency
Fmax
Tr/Tf
MHz
180(3)
11
75
10
3.3
6
Output rise and
fall time
ns
16
Maximum
frequency
Fmax
Tf
-
-
1
5
MHz
ns
Fm+
C=50 pF, 1.6 V≤VDDIOx≤3.6 V
Output fall
time(4)
1. The I/O speed is configured using the OSPEEDRy[1:0] bits. The Fm+ mode is configured in the
SYSCFG_CFGR1 register. Refer to the RM0438 reference manual for a description of GPIO Port
configuration register.
2. Guaranteed by design.
3. This value represents the I/O capability but the maximum system frequency is limited to 110 MHz.
4. The fall time is defined between 70% and 30% of the output waveform accordingly to I2C specification.
DS12737 Rev 6
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307
Electrical characteristics
Speed Symbol
STM32L552xx
(1)(2)
Table 105. FT_c I/O AC characteristics
Parameter
Conditions
Min
Max
Unit
C=50 pF, 2.7 V≤VDDIOx≤3.6 V
C=50 pF, 1.6 V≤VDDIOx≤2.7 V
C=50 pF, 1.08 V≤VDDIOx≤3.6 V
C=50 pF, 2.7 V≤VDDIOx≤3.6 V
C=50 pF, 1.6 V≤VDDIOx≤2.7 V
C=50 pF, 1.08 V≤VDDIOx≤3.6 V
C=50 pF, 2.7 V≤VDDIOx≤3.6 V
C=50 pF, 1.6 V≤VDDIOx≤2.7 V
C=50 pF, 1.08 V≤VDDIOx≤3.6 V
C=50 pF, 2.7 V≤VDDIOx≤3.6 V
C=50 pF, 1.6 V≤VDDIOx≤2.7 V
C=50 pF, 1.08 V≤VDDIOx≤3.6 V
-
-
-
-
-
-
-
-
-
-
-
-
2
1
Maximum
frequency
Fmax
MHz
0.1
170
330
3300
10
0
Output rise and
fall time
Tr/Tf
ns
MHz
ns
Maximum
frequency
Fmax
5
0.7
35
1
Output rise and
fall time
Tr/Tf
65
400
1. The I/O speed is configured using the OSPEEDRy[0] bit. Refer to the RM0438 reference manual for a
description of GPIO Port configuration register.
2. Guaranteed by design.
(1)
Figure 41. I/O AC characteristics definition
10%
90%
50%
50%
10%
90%
t
t
r(IO)out
f(IO)out
T
Maximum frequency is achieved if (t + t (≤ 2/3)T and if the duty cycle is (45-55%)
r
f
when loaded by the specified capacitance.
MS32132V2
1. Refer to Table 104: I/O AC characteristics (All I/Os except FT_c).
5.3.16
NRST pin characteristics
The NRST pin input driver uses the CMOS technology. It is connected to a permanent pull-
up resistor, R
.
PU
Unless otherwise specified, the parameters given in the table below are derived from tests
performed under the ambient temperature and supply voltage conditions summarized in
Table 27: General operating conditions.
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STM32L552xx
Electrical characteristics
(1)
Table 106. NRST pin characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
NRST input low level
voltage
VIL(NRST)
-
-
-
-
0.3ₓVDDIOx
V
NRST input high level
voltage
VIH(NRST)
-
0.7ₓVDDIOx
-
-
NRST Schmitt trigger
voltage hysteresis
Vhys(NRST)
RPU
VF(NRST)
VNF(NRST)
-
-
25
-
200
40
-
mV
kΩ
ns
Weak pull-up equivalent
resistor(2)
VIN = VSS
-
55
70
-
NRST input filtered
pulse
NRST input not filtered
pulse
1.71 V ≤ VDD
≤ 3.6 V
350
-
ns
1. Guaranteed by design.
2. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution to
the series resistance is minimal (~10% order).
Figure 42. Recommended NRST pin protection
External
reset circuit(1)
VDD
RPU
NRST(2)
Internal reset
Filter
0.1 μF
MS19878V3
1. The reset network protects the device against parasitic resets.
2. The user must ensure that the level on the NRST pin can go below the VIL(NRST) max level specified in
Table 106: NRST pin characteristics. Otherwise the reset is not taken into account by the device.
3. The external capacitor on NRST must be placed as close as possible to the device.
5.3.17
Extended interrupt and event controller input (EXTI) characteristics
The pulse on the interrupt input must have a minimal length in order to guarantee that it is
detected by the event controller.
(1)
Table 107. EXTI input characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Pulse length to event
controller
PLEC
-
20
-
-
ns
1. Guaranteed by design.
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Electrical characteristics
STM32L552xx
5.3.18
Analog switches booster
(1)
Table 108. Analog switches booster characteristics
Symbol
Parameter
Supply voltage
Min
Typ
Max
Unit
VDD
1.62
-
-
-
3.6
V
tSU(BOOST)
Booster startup time
240
µs
Booster consumption for
-
-
-
-
-
-
250
500
900
1.62 V ≤ VDD ≤ 2.0 V
Booster consumption for
IDD(BOOST)
µA
2.0 V ≤ VDD ≤ 2.7 V
Booster consumption for
2.7 V ≤ VDD ≤ 3.6 V
1. Guaranteed by design.
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DS12737 Rev 6
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Electrical characteristics
5.3.19
Analog-to-digital converter characteristics
Unless otherwise specified, the parameters given in Table 109 are preliminary values
derived from tests performed under ambient temperature, f
frequency and V
supply
PCLK
DDA
voltage conditions summarized in Table 27: General operating conditions.
Note:
It is recommended to perform a calibration after each power-up.
(1) (2)
Table 109. ADC characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Analog supply
voltage
VDDA
-
1.62
2
-
3.6
V
Positive
reference
voltage
V
DDA ≥ 2 V
-
VDDA
V
V
VREF+
VDDA < 2 V
VDDA
Negative
reference
voltage
VREF-
-
VSSA
V
Range 0 and 1
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
80
ADC clock
frequency
fADC
MHz
Range 2
26
Resolution = 12 bits
Resolution = 10 bits
Resolution = 8 bits
Resolution = 6 bits
Resolution = 12 bits
Resolution = 10 bits
Resolution = 8 bits
Resolution = 6 bits
5.33
6.15
7.27
8.88
4.21
4.71
5.33
6.15
Sampling rate
for FAST
channels
fs
Msps
Sampling rate
for SLOW
channels
fADC = 80 MHz
Resolution = 12 bits
-
-
-
-
-
5.33
15
MHz
1/fADC
V
External trigger
frequency
fTRIG
Resolution = 12 bits
-
Conversion
voltage range(2)
(3)
VAIN
0
VREF+
External input
impedance
RAIN
-
-
-
-
-
-
5
1
50
-
kΩ
Internal sample
and hold
capacitor
CADC
pF
conversi
on cycle
tSTAB
Power-up time
Calibration time
f
ADC = 80 MHz
1.45
116
µs
tCAL
-
1/fADC
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307
Electrical characteristics
Symbol
STM32L552xx
(1) (2)
Table 109. ADC characteristics
(continued)
Parameter
Conditions
Min
1.5
Typ
Max
Unit
Trigger
CKMODE = 00
CKMODE = 01
CKMODE = 10
2
-
2.5
2.0
conversion
latency Regular
and injected
channels
-
-
-
2.25
tLATR
1/fADC
without
conversion
abort
CKMODE = 11
-
-
2.125
Trigger
CKMODE = 00
CKMODE = 01
CKMODE = 10
2.5
3
-
3.5
3.0
conversion
latency Injected
channels
-
-
tLATRINJ
1/fADC
-
3.25
aborting a
regular
conversion
CKMODE = 11
-
-
3.125
fADC = 80 MHz
-
0.03125
2.5
-
-
8.00625
640.5
µs
ts
Sampling time
1/fADC
ADC voltage
regulator start-
up time
tADCVREG_STU
-
-
-
-
20
µs
P
fADC = 80 MHz
Resolution = 12 bits
0.1875
8.1625
µs
Total conversion
time
(including
tCONV
ts + 12.5 cycles for
successive approximation
= 15 to 653
Resolution = 12 bits
1/fADC
sampling time)
fs = 5 Msps
fs = 1 Msps
fs = 10 ksps
fs = 5 Msps
fs = 1 Msps
-
-
-
-
-
730
160
16
830
220
50
ADC
consumption
from the VDDA
supply
IDDA(ADC)
µA
ADC
consumption
DDV_S(ADC) from the VREF+
single ended
130
30
160
40
I
µA
µA
fs = 10 ksps
-
0.6
2
mode
fs = 5 Msps
fs = 1 Msps
fs = 10 ksps
-
-
-
260
60
310
70
3
ADC
consumption
from the VREF+
differential mode
I
DDV_D(ADC)
1.3
1. Guaranteed by design
2. The I/O analog switch voltage booster is enable when VDDA < 2.4 V (BOOSTEN = 1 in the
SYSCFG_CFGR1 when VDDA < 2.4V). It is disable when VDDA ≥ 2.4 V.
3. VREF+ can be internally connected to VDDA and VREF- can be internally connected to VSSA, depending on
the package.
Refer to Section 4: Pinouts and pin description for further details.
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Electrical characteristics
The maximum value of R
can be found in Table 110: Maximum ADC RAIN.
AIN
(1)(2)
AIN
Table 110. Maximum ADC R
RAIN max (Ω)
Fast channels(3) Slow channels(4)
Sampling cycle
@80 MHz
Sampling time
[ns] @80 MHz
Resolution
2.5
6.5
31.25
81.25
100
330
N/A
100
12.5
24.5
47.5
92.5
247.5
640.5
2.5
156.25
306.25
593.75
1156.25
3093.75
8006.75
31.25
680
470
1500
2200
4700
12000
39000
120
1200
1800
3900
10000
33000
N/A
12 bits
6.5
81.25
390
180
12.5
24.5
47.5
92.5
247.5
640.5
2.5
156.25
306.25
593.75
1156.25
3093.75
8006.75
31.25
820
560
1500
2200
5600
12000
47000
180
1200
1800
4700
10000
39000
N/A
10 bits
8 bits
6 bits
6.5
81.25
470
270
12.5
24.5
47.5
92.5
247.5
640.5
2.5
156.25
306.25
593.75
1156.25
3093.75
8006.75
31.25
1000
1800
2700
6800
15000
50000
220
680
1500
2200
5600
12000
50000
N/A
6.5
81.25
560
330
12.5
24.5
47.5
92.5
247.5
640.5
156.25
306.25
593.75
1156.25
3093.75
8006.75
1200
2700
3900
8200
18000
50000
1000
2200
3300
6800
15000
50000
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Electrical characteristics
STM32L552xx
1. Guaranteed by design.
2. The I/O analog switch voltage booster is enable when VDDA < 2.4 V (BOOSTEN = 1 in the
SYSCFG_CFGR1 when VDDA < 2.4V). It is disable when VDDA ≥ 2.4 V.
3. Fast channels are: PC0, PC1, PC2, PC3, PA0.
4. Slow channels are: all ADC inputs except the fast channels.
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STM32L552xx
Sym-
Electrical characteristics
(1)(2)(3)
Table 111. ADC accuracy - limited test conditions 1
Conditions(4)
Parameter
Min Typ Max Unit
bol
Fast channel (max speed)
Single
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
4
4
5
5
ended
Total
Slow channel (max speed)
ET
unadjusted
error
Fast channel (max speed)
Differential
3.5 4.5
3.5 4.5
Slow channel (max speed)
Fast channel (max speed)
Single
1
1
2.5
2.5
ended
Slow channel (max speed)
Offset
error
EO
EG
ED
EL
Fast channel (max speed)
Differential
1.5 2.5
1.5 2.5
2.5 4.5
2.5 4.5
2.5 3.5
2.5 3.5
Slow channel (max speed)
Fast channel (max speed)
Single
ended
Slow channel (max speed)
Gain error
LSB
Fast channel (max speed)
Differential
Slow channel (max speed)
1
1
1
1
3.5
3.5
2
Fast channel (max speed)
Single
ended
Differential
linearity
error
Slow channel (max speed)
ADC clock frequency ≤
80 MHz,
Fast channel (max speed)
Slow channel (max speed)
Fast channel (max speed)
Slow channel (max speed)
Fast channel (max speed)
Slow channel (max speed)
Differential
Sampling rate ≤ 5.33 Msps,
VDDA = VREF+ = 3 V,
2
1.5 2.5
1.5 2.5
Single
ended
TA = 25 °C
(ADC clock frequency ≤
58 MHz for LQFP144)
Integral
linearity
error
1
1
2
2
-
-
-
-
-
-
-
-
-
-
-
-
Differential
Fast channel (max speed) 10.4 10.5
Slow channel (max speed) 10.4 10.5
Fast channel (max speed) 10.8 10.9
Slow channel (max speed) 10.8 10.9
Fast channel (max speed) 64.4 65
Slow channel (max speed) 64.4 65
Fast channel (max speed) 66.8 67.4
Slow channel (max speed) 66.8 67.4
Single
ended
Effective
ENOB number of
bits
bits
Differential
Single
ended
Signal-to-
noise and
distortion
SINAD
ratio
Differential
dB
Fast channel (max speed) 65
Slow channel (max speed) 65
Fast channel (max speed) 67
Slow channel (max speed) 67
66
66
68
68
Single
ended
Signal-to-
SNR
noise ratio
Differential
DS12737 Rev 6
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307
Electrical characteristics
STM32L552xx
(1)(2)(3)
Table 111. ADC accuracy - limited test conditions 1
(continued)
Min Typ Max Unit
Sym-
bol
Parameter
Conditions(4)
ADC clock frequency ≤
80 MHz,
Fast channel (max speed)
Slow channel (max speed)
Fast channel (max speed)
-
-
-
-74 -73
-74 -73
-79 -76
Single
ended
Sampling rate ≤ 5.33 Msps,
Total
THD harmonic
distortion
dB
VDDA = VREF+ = 3 V,
TA = 25 °C
(ADC clock frequency ≤
58 MHz for LQFP144)
Differential
Slow channel (max speed)
-
-79 -76
1. Guaranteed by design.
2. ADC DC accuracy values are measured after internal calibration.
3. ADC accuracy vs. negative Injection Current: Injecting negative current on any analog input pins should be avoided as this
significantly reduces the accuracy of the conversion being performed on another analog input. It is recommended to add a
Schottky diode (pin to ground) to analog pins which may potentially inject negative current.
4. The I/O analog switch voltage booster is enable when VDDA < 2.4 V (BOOSTEN = 1 in the SYSCFG_CFGR1 when
V
DDA < 2.4 V). It is disable when VDDA ≥ 2.4 V. No oversampling.
244/340
DS12737 Rev 6
STM32L552xx
Sym-
Electrical characteristics
(1)(2)(3)
Table 112. ADC accuracy - limited test conditions 2
Conditions(4)
Parameter
Min Typ Max Unit
bol
Fast channel (max speed)
Single
-
-
-
-
-
-
-
-
-
-
-
-
-
4
4
6.5
6.5
ended
Total
Slow channel (max speed)
ET
unadjusted
error
Fast channel (max speed)
Differential
3.5 5.5
3.5 5.5
Slow channel (max speed)
Fast channel (max speed)
Single
1
4.5
5
ended
Slow channel (max speed)
1
Offset
error
EO
EG
ED
EL
Fast channel (max speed)
Differential
1.5
1.5
2.5
2.5
3
Slow channel (max speed)
3
Fast channel (max speed)
Single
6
ended
Slow channel (max speed)
6
Gain error
LSB
Fast channel (max speed)
Differential
2.5 3.5
2.5 3.5
Slow channel (max speed)
1
1
1
1
3.5
3.5
2
Fast channel (max speed)
Single
ended
Differential
linearity
error
-
Slow channel (max speed)
ADC clock frequency ≤
80 MHz,
-
Fast channel (max speed)
Differential
-
2
Slow channel (max speed)
Fast channel (max speed)
Slow channel (max speed)
Fast channel (max speed)
Slow channel (max speed)
Sampling rate ≤ 5.33 Msps,
2 V ≤ VDDA
(ADC clock frequency ≤
58 MHz for LQFP144)
-
-
-
-
2.5 4.5
2.5 4.5
Single
ended
Integral
linearity
error
1
1
3
Differential
2.5
Fast channel (max speed) 10 10.5
Slow channel (max speed) 10 10.5
Fast channel (max speed) 10.7 10.9
Slow channel (max speed) 10.7 10.9
-
-
-
-
-
-
-
-
-
-
-
-
Single
ended
Effective
ENOB number of
bits
bits
Differential
Fast channel (max speed) 62
Slow channel (max speed) 62
65
65
Single
ended
Signal-to-
noise and
distortion
ratio
SINAD
Fast channel (max speed) 66 67.4
Slow channel (max speed) 66 67.4
Differential
dB
Fast channel (max speed) 64
Slow channel (max speed) 64
66
66
Single
ended
Signal-to-
SNR
noise ratio
Fast channel (max speed) 66.5 68
Slow channel (max speed) 66.5 68
Differential
DS12737 Rev 6
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307
Electrical characteristics
STM32L552xx
(1)(2)(3)
Table 112. ADC accuracy - limited test conditions 2
(continued)
Min Typ Max Unit
Sym-
bol
Parameter
Conditions(4)
ADC clock frequency ≤
80 MHz,
Fast channel (max speed)
Slow channel (max speed)
Fast channel (max speed)
-
-
-
-74 -65
-74 -67
-79 -70
Single
ended
Total
Sampling rate ≤ 5.33 Msps,
THD harmonic
distortion
dB
2 V ≤ VDDA
(ADC clock frequency ≤
58 MHz for LQFP144)
Differential
Slow channel (max speed)
-
-79 -71
1. Guaranteed by design.
2. ADC DC accuracy values are measured after internal calibration.
3. ADC accuracy vs. negative Injection Current: Injecting negative current on any analog input pins should be avoided as this
significantly reduces the accuracy of the conversion being performed on another analog input. It is recommended to add a
Schottky diode (pin to ground) to analog pins which may potentially inject negative current.
4. The I/O analog switch voltage booster is enable when VDDA < 2.4 V (BOOSTEN = 1 in the SYSCFG_CFGR1 when
V
DDA < 2.4 V). It is disable when VDDA ≥ 2.4 V. No oversampling.
246/340
DS12737 Rev 6
STM32L552xx
Sym-
Electrical characteristics
(1)(2)(3)
Table 113. ADC accuracy - limited test conditions 3
Conditions(4)
Parameter
Min Typ Max Unit
bol
Fast channel (max speed)
Single
-
-
-
-
-
-
-
-
-
-
-
-
-
5.5 7.5
4.5 6.5
4.5 7.5
4.5 5.5
ended
Total
Slow channel (max speed)
ET
unadjusted
error
Fast channel (max speed)
Differential
Slow channel (max speed)
Fast channel (max speed)
Single
2
2.5
2
5
5
ended
Slow channel (max speed)
Offset
error
EO
EG
ED
EL
Fast channel (max speed)
Differential
3.5
3
Slow channel (max speed)
2.5
4.5
3.5
3.5
3.5
1
Fast channel (max speed)
Single
7
ended
Slow channel (max speed)
6
Gain error
LSB
Fast channel (max speed)
Differential
4
Slow channel (max speed)
5
3.5
3.5
2
Fast channel (max speed)
Single
ended
Differential
linearity
error
-
1
Slow channel (max speed)
Fast channel (max speed)
Slow channel (max speed)
Fast channel (max speed)
Slow channel (max speed)
Fast channel (max speed)
Slow channel (max speed)
ADC clock frequency ≤
80 MHz,
-
1
Sampling rate ≤ 5.33 Msps,
Differential
-
1
2
1.65 V ≤ VDDA = VREF+
≤
3.6 V,
-
-
-
-
2.5 4.5
2.5 4.5
Single
ended
Voltage scaling Range 1
(ADC clock frequency ≤
58 MHz for LQFP144)
Integral
linearity
error
2
2
2.5
Differential
2.5
Fast channel (max speed) 10 10.4
Slow channel (max speed) 10 10.4
Fast channel (max speed) 10.6 10.7
Slow channel (max speed) 10.6 10.7
-
-
-
-
-
-
-
-
-
-
-
-
Single
ended
Effective
ENOB number of
bits
bits
Differential
Fast channel (max speed) 62
Slow channel (max speed) 62
Fast channel (max speed) 65
Slow channel (max speed) 65
Fast channel (max speed) 63
Slow channel (max speed) 63
Fast channel (max speed) 66
Slow channel (max speed) 66
64
64
66
66
65
65
67
67
Single
ended
Signal-to-
noise and
distortion
ratio
SINAD
Differential
dB
Single
ended
Signal-to-
SNR
noise ratio
Differential
DS12737 Rev 6
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307
Electrical characteristics
STM32L552xx
(1)(2)(3)
Table 113. ADC accuracy - limited test conditions 3
(continued)
Min Typ Max Unit
Sym-
bol
Parameter
Conditions(4)
ADC clock frequency ≤
80 MHz,
Fast channel (max speed)
Slow channel (max speed)
Fast channel (max speed)
-
-
-
-69 -67
-71 -67
-72 -71
Single
ended
Sampling rate ≤ 5.33 Msps,
Total
1.65 V ≤ VDDA = VREF+
≤
THD harmonic
distortion
dB
3.6 V,
Differential
Voltage scaling Range 1
(ADC clock frequency ≤
58 MHz for LQFP144)
Slow channel (max speed)
-
-72 -71
1. Guaranteed by design.
2. ADC DC accuracy values are measured after internal calibration.
3. ADC accuracy vs. negative Injection Current: Injecting negative current on any analog input pins should be avoided as this
significantly reduces the accuracy of the conversion being performed on another analog input. It is recommended to add a
Schottky diode (pin to ground) to analog pins which may potentially inject negative current.
4. The I/O analog switch voltage booster is enable when VDDA < 2.4 V (BOOSTEN = 1 in the SYSCFG_CFGR1 when
V
DDA < 2.4 V). It is disable when VDDA ≥ 2.4 V. No oversampling.
248/340
DS12737 Rev 6
STM32L552xx
Sym-
Electrical characteristics
(1)(2)(3)
Table 114. ADC accuracy - limited test conditions 4
Conditions(4)
Parameter
Min Typ Max Unit
bol
Fast channel (max speed)
Single
-
-
-
-
-
-
-
-
-
-
-
-
-
5
4
4
5.4
5
ended
Total
Slow channel (max speed)
ET
unadjusted
error
Fast channel (max speed)
Differential
5
Slow channel (max speed)
3.5 4.5
Fast channel (max speed)
Single
2
2
4
4
ended
Slow channel (max speed)
Offset
error
EO
EG
ED
EL
Fast channel (max speed)
Differential
2
3.5
3.5
4.5
4.5
4
Slow channel (max speed)
2
Fast channel (max speed)
Single
4
ended
Slow channel (max speed)
4
Gain error
LSB
Fast channel (max speed)
Differential
3
Slow channel (max speed)
3
4
1
1.5
1.5
1.2
1.2
3
Fast channel (max speed)
Single
ended
Differential
linearity
error
-
1
Slow channel (max speed)
-
1
Fast channel (max speed)
Slow channel (max speed)
Fast channel (max speed)
Slow channel (max speed)
Fast channel (max speed)
Slow channel (max speed)
ADC clock frequency ≤
26 MHz,
Differential
-
1
1.65 V ≤ VDDA = VREF+ ≤
3.6 V,
-
-
-
-
2.5
2.5
2
Single
ended
Integral
linearity
error
Voltage scaling Range 2
3
2.5
2.5
-
Differential
2
Fast channel (max speed) 10.2 10.5
Slow channel (max speed) 10.2 10.5
Fast channel (max speed) 10.6 10.7
Slow channel (max speed) 10.6 10.7
Single
ended
Effective
-
ENOB number of
bits
bits
-
Differential
-
Fast channel (max speed) 63
Slow channel (max speed) 63
Fast channel (max speed) 65
Slow channel (max speed) 65
Fast channel (max speed) 64
Slow channel (max speed) 64
Fast channel (max speed) 66
Slow channel (max speed) 66
65
65
66
66
65
65
67
67
-
Single
ended
Signal-to-
noise and
distortion
ratio
-
SINAD
-
Differential
-
dB
-
Single
ended
-
Signal-to-
SNR
noise ratio
-
Differential
-
DS12737 Rev 6
249/340
307
Electrical characteristics
STM32L552xx
(1)(2)(3)
Table 114. ADC accuracy - limited test conditions 4
(continued)
Min Typ Max Unit
Sym-
bol
Parameter
Conditions(4)
Fast channel (max speed)
Slow channel (max speed)
Fast channel (max speed)
Slow channel (max speed)
-
-
-
-
-71 -69
-71 -69
-73 -72
-73 -72
ADC clock frequency ≤
26 MHz,
Single
ended
Total
THD harmonic 1.65 V ≤ VDDA = VREF+ ≤
dB
distortion
3.6 V,
Differential
Voltage scaling Range 2
1. Guaranteed by design.
2. ADC DC accuracy values are measured after internal calibration.
3. ADC accuracy vs. negative Injection Current: Injecting negative current on any analog input pins should be avoided as this
significantly reduces the accuracy of the conversion being performed on another analog input. It is recommended to add a
Schottky diode (pin to ground) to analog pins which may potentially inject negative current.
4. The I/O analog switch voltage booster is enable when VDDA < 2.4 V (BOOSTEN = 1 in the SYSCFG_CFGR1 when
V
DDA < 2.4 V). It is disable when VDDA ≥ 2.4 V. No oversampling.
250/340
DS12737 Rev 6
STM32L552xx
Electrical characteristics
Figure 43. ADC accuracy characteristics
VSSA
4095
EG
(1) Example of an actual transfer curve
(2) The ideal transfer curve
(3) End point correlation line
4094
4093
ET = total unajusted error: maximum deviation
between the actual and ideal transfer curves.
EO = offset error: maximum deviation
between the first actual transition and
the first ideal one.
(2)
ET
(3)
7
6
(1)
EG = gain error: deviation between the last
ideal transition and the last actual one.
ED = differential linearity error: maximum
deviation between actual steps and the ideal ones.
EL = integral linearity error: maximum deviation
between any actual transition and the end point
correlation line.
5
EO
EL
4
3
2
1
ED
1 LSB IDEAL
0
4096
VDDA
4094 4095
7
4093
2
3
4
5
6
1
MS19880V2
Figure 44. Typical connection diagram using the ADC
VDDA
VT
Sample and hold ADC converter
(1)
RAIN
RADC
AINx
12-bit
converter
(2)
(3)
Cparasitic
CADC
VT
Ilkg
VAIN
MS33900V5
1. Refer to Table 109: ADC characteristics for the values of RAIN and CADC
.
2. Cparasitic represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the
pad capacitance (refer to Table 102: I/O static characteristics for the value of the pad capacitance). A high
C
parasitic value downgrades the conversion accuracy. To remedy this, fADC should be reduced.
3. Refer to Table 102: I/O static characteristics for the values of Ilkg
.
General PCB design guidelines
Power supply decoupling should be performed as shown in the corresponding power supply
scheme. The 10 nF capacitor should be ceramic (good quality) and it should be placed as
close as possible to the chip.
DS12737 Rev 6
251/340
307
Electrical characteristics
STM32L552xx
5.3.20
Digital-to-Analog converter characteristics
(1)
Table 115. DAC characteristics
Conditions
Symbol
Parameter
Min
1.71
1.80
1.71
1.80
Typ
Max
Unit
DAC output buffer OFF, DAC_OUT
pin not connected (internal
connection only)
-
-
-
-
Analog supply voltage for
DAC ON
VDDA
3.6
Other modes
DAC output buffer OFF, DAC_OUT
pin not connected (internal
connection only)
V
VREF+
Positive reference voltage
Negative reference voltage
VDDA
Other modes
-
VREF-
VSSA
connected to VSSA
DAC output
5
25
9.6
-
-
-
-
RL
Resistive load
kΩ
kΩ
buffer ON
connected to VDDA
-
11.7
-
RO
Output Impedance
DAC output buffer OFF
13.8
2
Output impedance sample VDD = 2.7 V
and hold mode, output
RBON
kΩ
kΩ
VDD = 2.0 V
-
-
-
-
-
-
3.5
buffer ON
Output impedance sample VDD = 2.7 V
and hold mode, output
16.5
18.0
RBOFF
VDD = 2.0 V
buffer OFF
CL
DAC output buffer ON
Sample and hold mode
-
-
-
50
1
pF
µF
Capacitive load
CSH
0.1
VREF+
– 0.2
DAC output buffer ON
0.2
-
Voltage on DAC_OUT
output
VDAC_OUT
V
DAC output buffer OFF
±0.5 LSB
0
-
-
VREF+
3
1.7
Normal mode
DAC output
buffer ON
CL ≤ 50 pF,
RL ≥ 5 kΩ
Settling time (full scale: for
a 12-bit code transition
between the lowest and the
±1 LSB
-
1.6
2.9
±2 LSB
±4 LSB
±8 LSB
-
1.55
1.48
1.4
2.85
2.8
tSETTLING highest input codes when
DAC_OUT reaches final
µs
-
-
2.75
value ±0.5LSB, ±1 LSB,
±2 LSB, ±4 LSB, ±8 LSB)
Normal mode DAC output buffer
OFF, ±1LSB, CL = 10 pF
-
-
-
-
2
2.5
7.5
5
Normal mode DAC output buffer ON
CL ≤ 50 pF, RL ≥ 5 kΩ
Wakeup time from off state
4.2
2
(setting the ENx bit in the
DAC Control register) until
final value ±1 LSB
(2)
tWAKEUP
µs
Normal mode DAC output buffer
OFF, CL ≤ 10 pF
Normal mode DAC output buffer ON
CL ≤ 50 pF, RL = 5 kΩ, DC
PSRR
VDDA supply rejection ratio
-80
-28
dB
252/340
DS12737 Rev 6
STM32L552xx
Symbol
Electrical characteristics
(1)
Table 115. DAC characteristics (continued)
Parameter
Conditions
Min
Typ
Max
Unit
Minimal time between two
consecutive writes into the
DAC_DORx register to
guarantee a correct
DAC_OUT for a small
variation of the input code
(1 LSB)
TW_to_W
-
-
µs
DAC_MCR:MODEx[2:0] =
000 or 001
DAC_MCR:MODEx[2:0] =
010 or 011
CL ≤ 50 pF, RL ≥ 5 kΩ
CL ≤ 10 pF
1
1.4
-
DAC output buffer
0.7
3.5
18
ON, CSH = 100 nF
DAC_OUT
ms
Sampling time in sample
and hold mode (code
transition between the
lowest input code and the
highest input code when
DACOUT reaches final
value ±1LSB)
pin connected
DAC output buffer
OFF, CSH = 100 nF
-
10.5
tSAMP
DAC_OUT
pin not
connected
(internal
connection
only)
DAC output buffer
OFF
-
2
3.5
µs
Sample and hold mode,
DAC_OUT pin connected
(3)
Ileak
Output leakage current
-
-
-
nA
Internal sample and hold
capacitor
CIint
-
5.2
7
8.8
pF
µs
tTRIM
Middle code offset trim time DAC output buffer ON
50
-
-
-
-
-
VREF+ = 3.6 V
1500
750
Middle code offset for 1 trim
code step
Voffset
µV
µA
VREF+ = 1.8 V
-
No load, middle
code (0x800)
-
-
-
315
450
500
670
DAC output
buffer ON
No load, worst code
(0xF1C)
DAC consumption from
VDDA
DAC output
buffer OFF
No load, middle
code (0x800)
I
DDA(DAC)
-
0.2
315 ₓ
670 ₓ
Sample and hold mode, CSH
100 nF
=
Ton/(Ton Ton/(Ton
+Toff) +Toff)
-
(4)
(4)
DS12737 Rev 6
253/340
307
Electrical characteristics
STM32L552xx
(1)
Table 115. DAC characteristics (continued)
Parameter Conditions Min
No load, middle
Symbol
Typ
Max
Unit
-
-
-
185
240
code (0x800)
DAC output
buffer ON
No load, worst code
(0xF1C)
340
400
DAC output
buffer OFF
No load, middle
code (0x800)
155
205
DAC consumption from
VREF+
IDDV(DAC)
µA
185 ₓ
Ton/(Ton Ton/(Ton
400 ₓ
Sample and hold mode, buffer ON,
CSH = 100 nF, worst case
-
-
+Toff)
+Toff)
(4)
(4)
155 ₓ
205 ₓ
Sample and hold mode, buffer OFF,
CSH = 100 nF, worst case
Ton/(Ton Ton/(Ton
+Toff) +Toff)
(4)
(4)
1. Guaranteed by design.
2. In buffered mode, the output can overshoot above the final value for low input code (starting from min value).
3. Refer to Table 102: I/O static characteristics.
4. Ton is the Refresh phase duration. Toff is the Hold phase duration. Refer to RM0351 reference manual for more details.
Figure 45. 12-bit buffered / non-buffered DAC
Buffered/non-buffered DAC
Buffer(1)
RLOAD
12-bit
DACx_OUT
digital to
analog
converter
CLOAD
ai17157d
1. The DAC integrates an output buffer that can be used to reduce the output impedance and to drive external
loads directly without the use of an external operational amplifier. The buffer can be bypassed by
configuring the BOFFx bit in the DAC_CR register.
254/340
DS12737 Rev 6
STM32L552xx
Electrical characteristics
.
(1)
Table 116. DAC accuracy ranges 0/1
Conditions
Symbol
Parameter
Min
Typ
Max
Unit
DAC output buffer ON
DAC output buffer OFF
10 bits
-
-
-
±2
±2
Differential non
linearity (2)
DNL
-
-
monotonicity
guaranteed
DAC output buffer ON
CL ≤ 50 pF, RL ≥ 5 kΩ
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
±4
±4
Integral non
linearity(3)
INL
DAC output buffer OFF
CL ≤ 50 pF, no RL
VREF+ = 3.6 V
±12
±25
±8
DAC output buffer ON
CL ≤ 50 pF, RL ≥ 5 kΩ
LSB
Offset error at
code 0x800(3)
Offset
VREF+ = 1.8 V
DAC output buffer OFF
CL ≤ 50 pF, no RL
Offset error at
code 0x001(4)
DAC output buffer OFF
CL ≤ 50 pF, no RL
Offset1
±5
VREF+ = 3.6 V
±5
Offset Error at
OffsetCal code 0x800
after calibration
DAC output buffer ON
CL ≤ 50 pF, RL ≥ 5 kΩ
VREF+ = 1.8 V
±7
DAC output buffer ON
CL ≤ 50 pF, RL ≥ 5 kΩ
±0.5
±0.5
±30
±12
Gain
Gain error(5)
%
DAC output buffer OFF
CL ≤ 50 pF, no RL
DAC output buffer ON
CL ≤ 50 pF, RL ≥ 5 kΩ
Total
TUE
unadjusted
error
LSB
LSB
DAC output buffer OFF
CL ≤ 50 pF, no RL
Total
unadjusted
error after
calibration
DAC output buffer ON
CL ≤ 50 pF, RL ≥ 5 kΩ
TUECal
-
-
±23
DAC output buffer ON
CL ≤ 50 pF, RL ≥ 5 kΩ
1 kHz, BW 500 kHz
-
-
71.2
71.6
-
-
Signal-to-noise
ratio
SNR
THD
dB
dB
DAC output buffer OFF
CL ≤ 50 pF, no RL, 1 kHz
BW 500 kHz
DAC output buffer ON
CL ≤ 50 pF, RL ≥ 5 kΩ, 1 kHz
-
-
-78
-79
-
-
Total harmonic
distortion
DAC output buffer OFF
CL ≤ 50 pF, no RL, 1 kHz
DS12737 Rev 6
255/340
307
Electrical characteristics
STM32L552xx
(1)
Table 116. DAC accuracy ranges 0/1 (continued)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
DAC output buffer ON
CL ≤ 50 pF, RL ≥ 5 kΩ, 1 kHz
-
70.4
-
Signal-to-noise
and distortion
ratio
SINAD
dB
DAC output buffer OFF
CL ≤ 50 pF, no RL, 1 kHz
-
-
-
71
-
-
-
DAC output buffer ON
CL ≤ 50 pF, RL ≥ 5 kΩ, 1 kHz
11.4
11.5
Effective
number of bits
ENOB
bits
DAC output buffer OFF
CL ≤ 50 pF, no RL, 1 kHz
1. Guaranteed by design.
2. Difference between two consecutive codes - 1 LSB.
3. Difference between measured value at Code i and the value at Code i on a line drawn between Code 0 and last Code 4095.
4. Difference between the value measured at Code (0x001) and the ideal value.
5. Difference between ideal slope of the transfer function and measured slope computed from code 0x000 and 0xFFF when
buffer is OFF, and from code giving 0.2 V and (VREF+ – 0.2) V when buffer is ON.
256/340
DS12737 Rev 6
STM32L552xx
Electrical characteristics
5.3.21
Voltage reference buffer characteristics
(1)
Table 117. VREFBUF characteristics
Conditions Min
2.4
Symbol
Parameter
Typ
Max
Unit
VRS = 0
-
3.6
3.6
Normal mode
VRS = 1
VRS = 0
2.8
1.65
-
Analog supply
voltage
VDDA
-
2.4
Degraded mode(2)
VRS = 1
1.65
-
2.8
V
VRS = 0
VRS = 1
VRS = 0
VRS = 1
2.044
2.048
2.052
2.504
VDDA
VDDA
Normal mode
Iload=100 µA/T=30°C
Voltage
reference
output
2.496
2.5
VREFBUF_
OUT
VDDA-250 mV
VDDA-250 mV
-
-
Degraded mode(2)
Normal mode
Voltage
reference
output spread
over the main
supply range
VRS=0
VRS=1
-
-
-
-
5
4
mV
mV
ꢀVREFOUT_
VD D
Trim step
resolution
TRIM
CL
-
-
-
-
±0.05
1
±0.1
1.5
%
Load capacitor
-
-
0.5
µF
Equivalent
Serial Resistor
of Cload
esr
-
-
-
-
-
-
2
4
Ω
Static load
current
Iload
-
mA
I
load = 500 µA
-
-
-
2000
500
Iline_reg
Line regulation 2.8 V ≤ VDDA ≤ 3.6 V
ppm/V
ppm/mA
Iload = 4 mA
100
Load
regulation
Iload_reg
500 μA ≤ Iload ≤4 mA Normal mode
-
-
50
-
500
Tcoeff_
-40 °C < TJ < +125 °C
vrefint +
50
Temperature
coefficient
TCoeff
ppm/ °C
Tcoeff_
0 °C < TJ < +50 °C
-
-
+
vrefint
50
DC
40
25
-
55
40
-
Power supply
rejection
PSRR
tSTART
dB
µs
100 kHz
-
CL = 0.5 µF(3)
CL = 1.1 µF(3)
CL = 1.5 µF(3)
300
500
650
350
650
800
Start-up time
-
-
DS12737 Rev 6
257/340
307
Electrical characteristics
STM32L552xx
(1)
Table 117. VREFBUF characteristics (continued)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Control of
maximum DC
current drive
on VREFBUF_
OUT during
IINRUSH
-
-
-
8
-
mA
start-up phase
(4)
I
load = 0 µA
-
-
-
16
18
35
25
30
50
VREFBUF
consumption
from VDDA
I
DDA(VREF
BUF)
Iload = 500 µA
Iload = 4 mA
µA
1. Guaranteed by design and characterization result, unless otherwise specified.
2. In degraded mode, the voltage reference buffer can not maintain accurately the output voltage which follows (VDDA - drop
voltage).
3. The capacitive load must include a 100 nF capacitor in order to cut-off the high frequency noise.
4. To correctly control the VREFBUF inrush current during start-up phase and scaling change, the VDDA voltage should be in
the range [2.4 V to 3.6 V] and [2.8 V to 3.6 V] respectively for VRS = 0 and VRS = 1.
Figure 46. VREFBUF in case VRS = 0
V
2.06
2.055
2.05
2.045
2.04
2.035
2.03
2.025
-40
-20
0
20
40
60
80
100
120 °C
Mean
Min
Max
MSv62522V1
258/340
DS12737 Rev 6
STM32L552xx
Electrical characteristics
Figure 47. VREFBUF in case VRS = 1
V
2.51
2.505
2.5
2.495
2.49
2.485
2.48
2.475
-40
-20
0
20
40
60
80
100
120 °C
Mean
Min
Max
MSv62523V1
DS12737 Rev 6
259/340
307
Electrical characteristics
STM32L552xx
5.3.22
Comparator characteristics
(1)
Table 118. COMP characteristics
Conditions
Symbol
VDDA
Parameter
Min
Typ
Max
Unit
Analog supply voltage
-
-
1.62
-
3.6
Comparator input voltage
range
VIN
0
-
VDDA
V
(2)
VBG
Scaler input voltage
Scaler offset voltage
-
VREFINT
VSC
-
BRG_EN=0 (bridge disable)
BRG_EN=1 (bridge enable)
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
±5
200
0.8
100
-
±10
300
1
mV
nA
µA
µs
Scaler static consumption
from VDDA
I
DDA(SCALER)
tSTART_SCALER Scaler startup time
200
5
VDDA ≥ 2.7 V
High-speed
mode
V
V
V
DDA < 2.7 V
DDA ≥ 2.7 V
DDA < 2.7 V
-
7
Comparator startup time to
reach propagation delay
specification
tSTART
-
15
25
80
80
100
0.9
1
µs
ns
Medium mode
-
Ultra-low-power mode
-
VDDA ≥ 2.7 V
VDDA < 2.7 V
DDA ≥ 2.7 V
VDDA < 2.7 V
55
65
0.55
0.65
5
High-speed
mode
Propagation delay for
200 mV step
with 100 mV overdrive
(3)
tD
V
Medium mode
µs
Ultra-low-power mode
12
Full common
mode range
Voffset
Comparator offset error
Comparator hysteresis
-
-
±5
±20
mV
No hysteresis
-
-
-
-
0
8
-
-
-
-
Low hysteresis
Medium hysteresis
High hysteresis
Vhys
mV
15
27
260/340
DS12737 Rev 6
STM32L552xx
Symbol
Electrical characteristics
(1)
Table 118. COMP characteristics (continued)
Parameter
Conditions
Min
Typ
Max
Unit
Static
-
400
600
Ultra-low-
power mode
With 50 kHz
±100 mV overdrive
square signal
nA
-
-
-
-
-
1200
5
-
Static
7
Comparator consumption
from VDDA
With 50 kHz
±100 mV overdrive
square signal
IDDA(COMP)
Medium mode
6
-
100
-
µA
nA
Static
70
75
High-speed
mode
With 50 kHz
±100 mV overdrive
square signal
Comparator input bias
current
(4)
-
-
-
-
I
bias
1. Guaranteed by design, unless otherwise specified.
2. Refer to Table 32: Embedded internal voltage reference.
3. Guaranteed by characterization results.
4. Mostly I/O leakage when used in analog mode. Refer to Ilkg parameter in Table 102: I/O static characteristics.
5.3.23
Operational amplifiers characteristics
(1)
Table 119. OPAMP characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Analog supply
voltage
VDDA
CMIR
-
1.8
-
3.6
V
Common mode
input range
-
0
-
VDDA
V
25 °C, No Load on output.
All voltage/Temp.
Normal mode
-
-
-
-
-
-
±1.5
Input offset
voltage
VIOFFSET
mV
±3
-
±5
±10
Input offset
voltage drift
∆VIOFFSET
μV/°C
Low-power mode
-
Offset trim step
TRIMOFFSETP at low common
TRIMLPOFFSETP input voltage
-
-
-
-
0.8
1
1.1
(0.1 ₓ VDDA
)
mV
Offset trim step
TRIMOFFSETN at high common
TRIMLPOFFSETN input voltage
1.35
(0.9 ₓ VDDA
)
DS12737 Rev 6
261/340
307
Electrical characteristics
STM32L552xx
(1)
Table 119. OPAMP characteristics (continued)
Parameter Conditions Min
Symbol
Typ
Max
Unit
Normal mode
-
-
-
-
-
-
-
-
500
100
450
50
ILOAD
Drive current
VDDA ≥ 2 V
VDDA ≥ 2 V
Low-power mode
Normal mode
µA
Drive current in
PGA mode
ILOAD_PGA
Low-power mode
Resistive load
(connected to
VSSA or to
VDDA)
Normal mode
4
-
-
-
-
-
-
-
-
RLOAD
V
DDA < 2 V
Low-power mode
Normal mode
20
4.5
40
kΩ
Resistive load
in PGA mode
(connected to
VSSA or to
RLOAD_PGA
VDDA < 2 V
Low-power mode
V
)
DDA
CLOAD
CMRR
Capacitive load
-
-
-
-
-
50
-
pF
dB
Normal mode
-85
-90
Common mode
rejection ratio
Low-power mode
-
CLOAD ≤ 50 pf,
RLOAD ≥ 4 kΩ DC
Normal mode
70
72
85
90
-
-
Power supply
rejection ratio
PSRR
GBW
dB
CLOAD ≤ 50 pf,
RLOAD ≥ 20 kΩ DC
Low-power mode
Normal mode
550
100
250
40
-
1600 2200
VDDA ≥ 2.4 V
(OPA_RANGE = 1)
Low-power mode
Normal mode
420
700
180
700
180
300
80
600
Gain Bandwidth
Product
kHz
950
VDDA < 2.4 V
(OPA_RANGE = 0)
Low-power mode
Normal mode
280
-
-
-
-
-
-
VDDA ≥ 2.4 V
Slew rate
Low-power mode
Normal mode
-
(from 10 and
90% of output
voltage)
SR(2)
V/ms
dB
-
VDDA < 2.4 V
Low-power mode
Normal mode
-
55
45
110
110
AO
Open loop gain
Low-power mode
VDDA
100
-
-
Normal mode
-
-
-
-
High saturation
voltage
Iload = max or Rload
=
=
(2)
VOHSAT
min Input at VDDA
.
VDDA
50
Low-power mode
mV
Normal mode
-
-
-
-
-
100
Low saturation
voltage
Iload = max or Rload
min Input at 0.
(2)
VOLSAT
Low-power mode
Normal mode
-
50
-
74
66
φm
Phase margin
°
Low-power mode
-
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DS12737 Rev 6
STM32L552xx
Electrical characteristics
(1)
Table 119. OPAMP characteristics (continued)
Parameter Conditions Min
Symbol
Typ
Max
Unit
Normal mode
-
-
13
20
-
-
GM
Gain margin
dB
Low-power mode
CLOAD ≤ 50 pf,
RLOAD ≥ 4 kΩ
follower
Normal mode
-
5
10
configuration
Wake up time
from OFF state.
tWAKEUP
µs
CLOAD ≤ 50 pf,
RLOAD ≥ 20 kΩ
follower
Low-power mode
-
-
10
-
30
configuration
General purpose input (all packages
except UFBGA132)
(3)
TJ ≤ 75 °C
-
-
-
-
-
-
-
-
-
-
1
3
8
15
-
OPAMP input
bias current
Ibias
nA
TJ ≤ 85 °C
-
Dedicated input
(UFBGA132)
TJ ≤ 105 °C
-
TJ ≤ 125 °C
-
2
4
-
Non inverting
gain value
PGA gain(2)
-
-
8
-
16
80/80
-
PGA Gain = 2
PGA Gain = 4
-
120/
40
-
-
-
-
-
-
R2/R1 internal
resistance
Rnetwork
kΩ/kΩ
140/
20
values in PGA
PGA Gain = 8
PGA Gain = 16
mode(4)
150/
10
Resistance
variation (R1 or
R2)
Delta R
-
-
-15
-
15
%
%
PGA gain error
PGA gain error
-1
-
-
1
-
GBW/
2
Gain = 2
Gain = 4
Gain = 8
Gain = 16
-
-
-
-
GBW/
4
-
-
-
-
-
-
PGA bandwidth
for different non
inverting gain
PGA BW
MHz
GBW/
8
GBW/
16
DS12737 Rev 6
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307
Electrical characteristics
STM32L552xx
(1)
Table 119. OPAMP characteristics (continued)
Parameter Conditions Min
at 1 kHz, Output
Symbol
Typ
Max
Unit
Normal mode
-
-
-
-
500
-
loaded with 4 kΩ
at 1 kHz, Output
loaded with 20 kΩ
Low-power mode
Normal mode
600
180
290
-
-
-
Voltage noise
density
en
nV/√Hz
at 10 kHz, Output
loaded with 4 kΩ
at 10 kHz, Output
loaded with 20 kΩ
Low-power mode
OPAMP
Normal mode
-
-
120
45
260
100
no Load, quiescent
mode
IDDA(OPAMP)(2) consumption
from VDDA
µA
Low-power mode
1. Guaranteed by design, unless otherwise specified.
2. Guaranteed by characterization results.
3. Mostly I/O leakage, when used in analog mode. Refer to Ilkg parameter in Table 102: I/O static characteristics.
4. R2 is the internal resistance between OPAMP output and OPAMP inverting input. R1 is the internal resistance between
OPAMP inverting input and ground. The PGA gain =1+R2/R1
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DS12737 Rev 6
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Electrical characteristics
5.3.24
Temperature sensor characteristics
Table 120. TS characteristics
Symbol
Parameter
Min
Typ
Max
Unit
(1)
TL
VTS linearity with temperature
-
±1
2.5
±2
2.7
°C
mV/°C
V
Avg_Slope(2) Average slope
2.3
V30
Voltage at 30°C (±5 °C)(3)
0.742
0.76
0.785
tSTART
Sensor Buffer Start-up time in continuous
-
-
8
70
-
15
120
-
µs
µs
µs
µA
(TS_BUF)(1) mode(4)
Start-up time when entering in continuous
(1)
tSTART
mode(4)
ADC sampling time when reading the
temperature
(1)
tS_temp
5
-
Temperature sensor consumption from VDD
when selected by ADC
,
IDD(TS)(1)
4.7
7
1. Guaranteed by design.
2. Guaranteed by characterization results.
3. Measured at VDDA = 3.0 V ±10 mV. The V30 ADC conversion result is stored in the TS_CAL1 byte. Refer to
Table 14: Temperature sensor calibration values.
4. Continuous mode means Run/Sleep modes, or temperature sensor enable in Low-power run/Low-power
sleep modes.
5.3.25
V
monitoring characteristics
BAT
(1)
Table 121. V
monitoring characteristics
BAT
Symbol
Parameter
Resistor bridge for VBAT
Min
Typ
Max
Unit
R
Q
-
-
39
3
-
-
-
kΩ
-
Ratio on VBAT measurement
Error on Q
Er(2)
-10
12
10
-
%
µs
(2)
tS_vbat
ADC sampling time when reading the VBAT
-
1. 1.55 V < VBAT < 3.6 V
2. Guaranteed by design.
Table 122. V
charging characteristics
BAT
Symbol
Parameter Conditions
Min
Typ
5
Max
Unit
Battery
charging
resistor
VBRS = 0
VBRS = 1
-
-
-
-
RBC
kΩ
1.5
DS12737 Rev 6
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307
Electrical characteristics
STM32L552xx
5.3.26
Temperature and V thresholds monitoring
DD
Temperature and upper V voltage monitoring characteristics for tamper detection are
DD
detailed in the table below:
Table 123. Temp and V monitoring characteristics
DD
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
High temperature
threshold monitoring
TEMPhigh
-
115
123(1)
130
°C
Low temperature
threshold monitoring
TEMPlow
VDDhigh
-
-
-45
3.6
-36(1)
-30
3.7
High VDD supply
monitoring
3.65(1)
V
Minimum PWM ON
time in case of
TPWMon
-
-
400(2)
-
μs
periodic monitoring
1. Guaranteed by characterization results.
2. Guaranteed by design.
5.3.27
DFSDM characteristics
Unless otherwise specified, the parameters given in Table 124 for DFSDM are derived from
tests performed under the ambient temperature, f frequency and V supply voltage
APB2
DD
conditions summarized in Table 27: General operating conditions.
•
•
•
Output speed is set to OSPEEDRy[1:0] = 10
Capacitive load C = 30 pF
Measurement points are done at CMOS levels: 0.5 x V
DD
Refer to Section 5.3.15: I/O port characteristics for more details on the input/output alternate
function characteristics (DFSDM1_CKINy, DFSDM1_DATINy, DFSDM1_CKOUT for
DFSDM).
266/340
DS12737 Rev 6
STM32L552xx
Electrical characteristics
(1)
Table 124. DFSDM measured timing 1.71 to 3.6 V
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
DFSDM
clock
fDFSDMCLK
1.71 < VDD < 3.6 V
-
-
fSYSCLK
SPI mode (SITP[1:0]=0,1),
External clock mode
(SPICKSEL[1:0]=0),
1.71 < VDD < 3.6 V
-
-
-
-
-
-
20
20
20
SPI mode (SITP[1:0]=0,1),
External clock mode
(SPICKSEL[1:0]=0),
2.7 < VDD < 3.6 V
fCKIN
(1/TCKIN
Input clock
frequency
)
MHz
SPI mode (SITP[1:0]=0,1),
Internal clock mode
(SPICKSEL[1:0]≠0),
1.71 < VDD < 3.6 V
SPI mode (SITP[1:0]=0,1),
Internal clock mode
(SPICKSEL[1:0]≠0),
2.7 < VDD < 3.6 V
-
-
-
-
20
20
55
Output
clock
fCKOUT
1.71 < VDD < 3.6 V
1.71 < VDD < 3.6 V
frequency
Output
clock
frequency
duty cycle
DuCyCKOUT
45
50
%
SPI mode (SITP[1:0]=0,1),
External clock mode
(SPICKSEL[1:0]=0),
1.71 < VDD < 3.6 V
Input clock
high and
low time
twh(CKIN)
twl(CKIN)
TCKIN/2-0.5
TCKIN/2
-
-
-
SPI mode (SITP[1:0]=0,1),
Data input External clock mode
setup time (SPICKSEL[1:0]=0),
1.71 < VDD < 3.6 V
tsu
3
-
-
ns
SPI mode (SITP[1:0]=0,1),
Data input External clock mode
hold time (SPICKSEL[1:0]=0),
1.71 < VDD < 3.6 V
th
2.5
Manchester Manchester mode
data period (SITP[1:0]=2,3),
(recovered Internal clock mode
(CKOUTDIV
+1) *
(2*CKOUTDI
V) *
TManchester
-
clock
period)
(SPICKSEL[1:0]≠0),
1.71 < VDD < 3.6 V
TDFSDMCLK
TDFSDMCLK
1. Data based on characterization results, not tested in production.
DS12737 Rev 6
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307
Electrical characteristics
STM32L552xx
Figure 16: DFSDM timing diagram
WZO
WZK
WU
WI
63,&.6(/ꢅ ꢅꢆ
6,73ꢅ ꢅꢆꢆ
WVX WK
WVX WK
6,73ꢅ ꢅꢆꢄ
63,&.6(/ꢅ ꢅꢀ
63,&.6(/ꢅ ꢅꢂ
63,&.6(/ꢅ ꢅꢄ
6,73ꢅ ꢅꢆꢆ
WU
WI
WZO
WZK
WVX WK
WVX WK
6,73ꢅ ꢅꢆꢄ
6,73ꢅ ꢅꢂ
6,73ꢅ ꢅꢀ
5HFRYHUHGꢅFORFN
5HFRYHUHGꢅGDWD
ꢆ
ꢆ
ꢄ
ꢄ
ꢆ
06Yꢀꢁꢂꢁꢃ9ꢄ
5.3.28
Timer characteristics
The parameters given in the following tables are guaranteed by design.
Refer to Section 5.3.15: I/O port characteristics for details on the input/output alternate
function characteristics (output compare, input capture, external clock, PWM output).
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DS12737 Rev 6
STM32L552xx
Electrical characteristics
(1)
Table 125. TIMx characteristics
Symbol
Parameter
Conditions
Min
Max
Unit
-
1
8.33
0
-
tTIMxCLK
ns
tres(TIM)
Timer resolution time
fTIMxCLK = 110 MHz
-
-
Timer external clock
frequency on CH1 to
CH4
f
TIMxCLK/2
MHz
fEXT
fTIMxCLK = 110 MHz
0
-
55
16
MHz
TIMx (except TIM2
and TIM5)
ResTIM
Timer resolution
bit
TIM2 and TIM5
-
32
-
1
0.009
-
65536
595.78
tTIMxCLK
µs
16-bit counter clock
period
tCOUNTER
fTIMxCLK = 110 MHz
-
Maximum possible
tMAX_COUNT count with 32-bit
counter
65536 × 65536
39.045
tTIMxCLK
fTIMxCLK = 110 MHz
-
s
1. TIMx, is used as a general term in which x stands for 1,2,3,4,5,6,7,8,15,16 or 17.
(1)
Table 126. IWDG min/max timeout period at 32 kHz (LSI)
Min timeout RL[11:0]=
0x000
Max timeout RL[11:0]=
0xFFF
Prescaler divider PR[2:0] bits
Unit
/4
/8
0
0.125
0.250
0.500
1.0
512
1024
2048
4096
8192
16384
32768
1
/16
/32
/64
/128
/256
2
3
4
ms
2.0
5
4.0
6 or 7
8.0
1. The exact timings still depend on the phasing of the APB interface clock versus the LSI clock so that there
is always a full RC period of uncertainty.
Table 127. WWDG min/max timeout value at 110 MHz (PCLK)
Prescaler
WDGTB
Min timeout value
Max timeout value
Unit
1
2
4
8
0
1
2
3
0.037
0.074
0.149
0.298
2.368
4.736
9.536
19.072
ms
DS12737 Rev 6
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307
Electrical characteristics
STM32L552xx
5.3.29
Communication interfaces characteristics
I2C interface characteristics
2
The I2C interface meets the timings requirements of the I C-bus specification and user
manual rev. 03 for:
•
•
•
Standard-mode (Sm): with a bit rate up to 100 kbit/s
Fast-mode (Fm): with a bit rate up to 400 kbit/s
Fast-mode Plus (Fm+): with a bit rate up to 1 Mbit/s.
The I2C timings requirements are guaranteed by design when the I2C peripheral is properly
configured (refer to RM0351 reference manual).
The SDA and SCL I/O requirements are met with the following restrictions: the SDA and
SCL I/O pins are not “true” open-drain. When configured as open-drain, the PMOS
connected between the I/O pin and V
is disabled, but is still present. Only FT_f I/O pins
DDIOx
support Fm+ low level output current maximum requirement. Refer to Section 5.3.15: I/O
port characteristics for the I2C I/Os characteristics.
All I2C SDA and SCL I/Os embed an analog filter. Refer to Table 128 below for the analog
filter characteristics:
(1)
Table 128. I2C analog filter characteristics
Symbol
Parameter
Min
Max
Unit
Maximum pulse width of spikes that
are suppressed by the analog filter
tAF
50(2)
260(3)
ns
1. Guaranteed by design.
2. Spikes with widths below tAF(min) are filtered.
3. Spikes with widths above tAF(max) are not filtered
270/340
DS12737 Rev 6
STM32L552xx
Electrical characteristics
SPI characteristics
Unless otherwise specified, the parameters given in Table 129 for SPI are derived from tests
performed under the ambient temperature, f frequency and supply voltage conditions
PCLKx
summarized in Table 27: General operating conditions.
•
•
•
Output speed is set to OSPEEDRy[1:0] = 11
Capacitive load C = 30 pF
Measurement points are done at CMOS levels: 0.5V
DD
Refer to Section 5.3.15: I/O port characteristics for more details on the input/output alternate
function characteristics (NSS, SCK, MOSI, MISO for SPI).
(1)
Table 129. SPI characteristics
Symbol
Parameter
Conditions
Min
Typ
Max(2)
Unit
Master mode
2.7<VDD<3.6
55
Voltage ranges 0/1
Master mode
1.71<VDD<3.6
Voltage ranges 0/1
44
Master transmitter mode
1.71<VDD<3.6
55
55
36
Voltage ranges 0/1
Slave receiver mode 1.71<VDD<3.6
Voltage ranges 0/1
fSCK
SPI clock frequency
-
-
MHz
1/tc(SCK)
Slave mode transmitter/full duplex
2.7<VDD<3.6
Voltage ranges 0/1
Slave mode transmitter/full duplex
1.71<VDD<3.6
23
Voltage ranges 0/1
Slave mode transmitter/full duplex
1.71<VDD<3.6
20
12
Voltage range 2
Slave mode transmitter/full duplex
1.08<VDD<1.32(3)
tsu(NSS)
th(NSS)
NSS setup time
NSS hold time
Slave mode, SPI presc = 2
Slave mode, SPI presc = 2
4×Tpclk
2TTpclk
-
-
-
-
-
tw(SCKH)
tw(SCKL)
SCK high and low
time
Master mode
Tpclk-1 Tpclk Tpclk+1
DS12737 Rev 6
271/340
307
Electrical characteristics
STM32L552xx
(1)
Table 129. SPI characteristics (continued)
Symbol
Parameter
Conditions
Min
Typ
Max(2)
Unit
tsu(MI)
tsu(SI)
th(MI)
th(SI)
Master mode
Slave mode
Master mode
Slave mode
2
-
-
-
-
-
-
-
-
Data input setup
time
1.5
7.5
3
Data input hold time
Data output access
time
ta(SO)
Slave mode
Slave mode
9
9
-
-
-
34
16
Data output disable
time
tdis(SO)
Slave mode 2.7<VDD<3.6V
Voltage ranges 0/1
9
13.75
Slave mode 1.71<VDD<3.6V
Voltage ranges 0/1
-
-
9
21.5
24.5
ns
tv(SO)
Data output valid
time
Slave mode 1.71<VDD<3.6V
Voltage range 2
11.5
Slave mode(3)
-
-
28.5
40.5
1.08<VDD<1.32V
tv(MO)
th(SO)
th(MO)
Master mode
0
-
1
-
Slave mode
7.5
1.71<VDD<3.6V
Data output hold
time
Slave mode(3)
21
0
-
-
-
-
1.08<VDD<1.32V
Master mode
1. Guaranteed by characterization results.
2. Maximum frequency in Slave transmitter mode is determined by the sum of tv(SO) and tsu(MI) which has to fit into SCK low
or high phase preceding the SCK sampling edge. This value can be achieved when the SPI communicates with a master
having tsu(MI) = 0 while Duty(SCK) = 50%.
3. SPI mapped on GPIOG port which is supplied by VDDIO2 specified down to 1.08 V. SPI is tested in this voltage.
272/340
DS12737 Rev 6
STM32L552xx
Electrical characteristics
Figure 48. SPI timing diagram - slave mode and CPHA = 0
NSS input
tc(SCK)
th(NSS)
tsu(NSS)
tw(SCKH)
tr(SCK)
CPHA=0
CPOL=0
CPHA=0
CPOL=1
ta(SO)
tw(SCKL)
tv(SO)
th(SO)
tf(SCK)
Last bit OUT
tdis(SO)
MISO output
MOSI input
First bit OUT
th(SI)
Next bits OUT
tsu(SI)
First bit IN
Next bits IN
Last bit IN
MSv41658V1
Figure 49. SPI timing diagram - slave mode and CPHA = 1
NSS input
tc(SCK)
tsu(NSS)
tw(SCKH)
tf(SCK)
th(NSS)
CPHA=1
CPOL=0
CPHA=1
CPOL=1
ta(SO)
tw(SCKL)
tv(SO)
First bit OUT
tsu(SI) th(SI)
First bit IN
th(SO)
Next bits OUT
tr(SCK)
tdis(SO)
MISO output
MOSI input
Last bit OUT
Next bits IN
Last bit IN
MSv41659V1
1. Measurement points are done at CMOS levels: 0.3 VDD and 0.7 VDD
.
DS12737 Rev 6
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307
Electrical characteristics
STM32L552xx
Figure 50. SPI timing diagram - master mode
High
NSS input
t
c(SCK)
CPHA=0
CPOL=0
CPHA=0
CPOL=1
CPHA=1
CPOL=0
CPHA=1
CPOL=1
t
t
t
t
w(SCKH)
w(SCKL)
r(SCK)
f(SCK)
t
su(MI)
MISO
INPUT
BIT6 IN
LSB IN
MSB IN
t
h(MI)
MOSI
OUTPUT
BIT1 OUT
LSB OUT
MSB OUT
t
t
h(MO)
v(MO)
ai14136c
1. Measurement points are done at CMOS levels: 0.3 VDD and 0.7 VDD
.
SAI characteristics
Unless otherwise specified, the parameters given in Table 130 for SAI are derived from
tests performed under the ambient temperature, f frequency and V supply voltage
PCLKx
DD
conditions summarized inTable 27: General operating conditions, with the following configu-
ration:
•
•
•
Output speed is set to OSPEEDRy[1:0] = 10
Capacitive load C = 30 pF
Measurement points are done at CMOS levels: 0.5V
DD
Refer to Section 5.3.15: I/O port characteristics for more details on the input/output alternate
function characteristics (CK,SD,FS).
274/340
DS12737 Rev 6
STM32L552xx
Electrical characteristics
(1)
Table 130. SAI characteristics
Conditions
Symbol
Parameter
Min
Max
Unit
fMCK
SAI Main clock output
-
-
50
Master Transmitter
2.7<=VDD<=3.6
-
23.5
Voltage ranges 0/1
Master Transmitter
1.71<=VDD<=3.6
Voltage ranges 0/1
-
-
-
16
16
26
Master Receiver
Voltage ranges 0/1
MHz
fCK
SAI clock frequency(2)
Slave Transmitter
2.7<=VDD<=3.6
Voltage ranges 0/1
Slave Transmitter
1.71<=VDD<=3.6
Voltage ranges 0/1
-
20
Slave Receiver
-
-
50
13
Voltage ranges 0/1
Voltage range 2
DS12737 Rev 6
275/340
307
Electrical characteristics
STM32L552xx
(1)
Table 130. SAI characteristics (continued)
Symbol
Parameter
Conditions
Min
Max
Unit
Master mode
-
21
25
2.7<=VDD<=3.6
tv(FS)
FS valid time
Master mode
-
1.71<=VDD<=3.6
th(FS)
tsu(FS)
FS hold time
FS setup time
FS hold time
Master mode
Slave mode
10
1.5
2.5
1
-
-
-
-
-
-
-
th(FS)
Slave mode
tsu(SD_A_MR)
tsu(SD_B_SR)
th(SD_A_MR)
th(SD_B_SR)
Master receiver
Slave receiver
Master receiver
Slave receiver
Data input setup time
Data input hold time
1.5
5
ns
0
Slave transmitter (after enable edge)
2.7<=VDD<=3.6
-
19
tv(SD_B_ST)
th(SD_B_ST)
tv(SD_A_MT)
th(SD_A_MT)
Data output valid time
Data output hold time
Data output valid time
Data output hold time
Slave transmitter (after enable edge)
1.71<=VDD<=3.6
-
10
-
25
-
Slave transmitter (after enable edge)
Master transmitter (after enable edge)
2.7<=VDD<=3.6
17
Master transmitter (after enable edge)
1.71<=VDD<=3.6
-
25
-
Master transmitter (after enable edge)
9
1. Guaranteed by characterization results.
2. 2.APB clock frequency must be at least twice SAI clock frequency.
Figure 51. SAI master timing waveforms
1/f
SCK
SAI_SCK_X
t
h(FS)
SAI_FS_X
(output)
t
t
t
h(SD_MT)
v(FS)
v(SD_MT)
SAI_SD_X
(transmit)
Slot n
Slot n+2
t
t
h(SD_MR)
su(SD_MR)
SAI_SD_X
(receive)
Slot n
MS32771V1
276/340
DS12737 Rev 6
STM32L552xx
Electrical characteristics
Figure 52. SAI slave timing waveforms
1/f
SCK
SAI_SCK_X
t
t
t
h(FS)
w(CKH_X)
w(CKL_X)
SAI_FS_X
(input)
t
t
t
h(SD_ST)
su(FS)
v(SD_ST)
SAI_SD_X
(transmit)
Slot n
Slot n+2
t
t
h(SD_SR)
su(SD_SR)
SAI_SD_X
(receive)
Slot n
MS32772V1
CAN (controller area network) interface
Refer to Section 5.3.15: I/O port characteristics for more details on the input/output alternate
function characteristics (FDCAN_TX and FDCAN_RX).
USART characteristics
Unless otherwise specified, the parameters given in Table 131 for USART are derived from
tests performed under the ambient temperature, fPCLKx frequency and VDD supply voltage
conditions summarized in Table 27: General operating conditions, with the following
configuration:
•
•
•
Output speed is set to OSPEEDRy[1:0] = 11
Capacitive load C=30pF
Measurement points are done at CMOS levels: 0.5VDD
Refer to Section 5.3.15: I/O port characteristics for more details on the input/output alternate
function characteristics (NSS, CK, TX, RX for USART).
(1)
Table 131. USART characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Master mode
-
-
13
1.71<VDD<3.6
Slave receiver mode
1.71<VDD<3.6
-
-
-
-
-
-
36
19
26
fSCK
SPI clock frequency
MHz
Slave mode transmitter
2.7<VDD<3.6
Slave mode transmitter
1.71<VDD<3.6
DS12737 Rev 6
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307
Electrical characteristics
STM32L552xx
(1)
Table 131. USART characteristics (continued)
Symbol
Parameter
Conditions
Slave mode
Slave mode
Min
Typ
Max
Unit
tsu(NSS)
th(NSS)
NSS setup time
NSS hold time
Tker +4
1
-
-
-
-
-
tw(SCKH)
tw(SCKL)
SCK high and low time Master mode
1/fsck/2-1
1/fsck/2
1/fsck/2+1
tsu(MI)
tsu(SI)
th(MI)
th(SI)
Master mode
Data input setup time
22.5
-
-
-
-
-
-
-
-
Slave mode
1
0
3
Master mode
Data input hold time
Slave mode
Slave mode
-
14.5
19
2.7<VDD<3.6V
ns
tv(SO)
Data output valid time
Data output hold time
Slave mode
-
-
14.5
26
3
-
1.71<VDD<3.6V
tv(MO)
th(SO)
th(MO)
Master mode
1.5
Slave mode
12
1
-
-
1.71<VDD<3.6V
Master mode
-
1. Guaranteed by characterization results, not tested in production.
Figure 53. USART master mode timing diagram
tc(SCK)
CPHA=0
CPOL=0
CPHA=0
CPOL=1
CPHA=1
CPOL=0
CPHA=1
CPOL=1
tw(SCKH)
tw(SCKL)
tr(SCK)
tf(SCK)
tsu(RX)
MSB
RX
TX
LSB
th(RX)
MSB
LSB
tv(TX)
th(TX)
MSv64015V1
278/340
DS12737 Rev 6
STM32L552xx
Electrical characteristics
Figure 54. USART slave mode timing diagram
NSS input
MISO
MSB OUT
BIT6 OUT
BIT1 IN
LSB OUT
OUTPUT
(SI)
MOSI
INPUT
LSB IN
MSB IN
(SI)
5.3.30
FSMC characteristics
Unless otherwise specified, the parameters given in Table 132 to Table 145 for the FMC
interface are derived from tests performed under the ambient temperature, f frequency
HCLK
and V supply voltage conditions summarized in Table 27: General operating conditions,
DD
with the following configuration:
•
•
•
Output speed is set to OSPEEDRy[1:0] = 11
Capacitive load C = 30 pF
Measurement points are done at CMOS levels: 0.5 x V
DD
Refer to Section 5.3.15: I/O port characteristics for more details on the input/output
characteristics.
Asynchronous waveforms and timings
Figure 55 through Figure 58 represent asynchronous waveforms and Table 132 through
Table 139 provide the corresponding timings. The results shown in these tables are
obtained with the following FMC configuration:
•
•
•
•
•
AddressSetupTime (ADDSET) = 0x1
AddressHoldTime (ADDHLD) = 0x1
DataHoldTime = 0x1
ByteLaneSetup (NBLSET) = 0x1
DataSetupTime (DATAST) = 0x1 (except for asynchronous NWAIT mode,
DataSetupTime = 0x5)
•
DataHoldTime (DATAHLD) = 0x1 (1THCLK for read operations and 2THCLK for write
operations)
•
•
BusTurnAroundDuration = 0x0
Capacitive load CL = 30 pF
In all timing tables, the THCLK is the HCLK clock period.
DS12737 Rev 6
279/340
307
Electrical characteristics
STM32L552xx
Figure 55. Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms
t
w(NE)
FMC_NE
t
t
t
h(NE_NOE)
w(NOE)
v(NOE_NE)
FMC_NOE
FMC_NWE
tv(A_NE)
t
h(A_NOE)
FMC_A[25:0]
Address
tv(BL_NE)
t
h(BL_NOE)
FMC_NBL[1:0]
t
h(Data_NE)
t
t
su(Data_NOE)
h(Data_NOE)
t
su(Data_NE)
Data
FMC_D[15:0]
t
v(NADV_NE)
t
w(NADV)
(1)
FMC_NADV
FMC_NWAIT
th(NE_NWAIT)
tsu(NWAIT_NE)
MS32753V1
280/340
DS12737 Rev 6
STM32L552xx
Electrical characteristics
(1)
Table 132. Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings
Symbol
Parameter
Min
Max
Unit
tw(NE)
FMC_NE low time
3THCLK– 0.5
3 THCLK+1
FMC_NEx low to
FMC_NOE low
tv(NOE_NE)
tw(NOE)
0
1
FMC_NOE low time
2THCLK -0.5
2THCLK + 1
FMC_NOE high to
FMC_NE high hold
time
th(NE_NOE)
THCLK
-
FMC_NEx low to
FMC_A valid
tv(A_NE)
th(A_NOE)
-
1
-
Address hold time after
FMC_NOE high
2THCLK-1
ns
Data to FMC_NEx high
setup time
tsu(Data_NE)
tsu(Data_NOE)
th(Data_NOE)
th(Data_NE)
THCLK +14
-
Data to FMC_NOEx
high setup time
14
0
-
Data hold time after
FMC_NOE high
-
Data hold time after
FMC_NEx high
0
-
FMC_NEx low to
FMC_NADV low
tv(NADV_NE)
tw(NADV)
-
-
0
FMC_NADV low time
THCLK+1.5
1. Guaranteed by characterization results, not tested in production.
Table 133. Asynchronous non-multiplexed SRAM/PSRAM/NOR read-NWAIT
(1)
timings
Symbol
Parameter
Min
Max
Unit
tw(NE)
tw(NOE)
tw(NWAIT)
FMC_NE low time
FMC_NWE low time
FMC_NWAIT low time
8THCLK-0.5
8THCLK+1
7THCLK -0.5 7THCLK +0.5
THCLK
-
ns
5THCLK
+12.5
tsu(NWAIT_NE) FMC_NWAIT valid before FMC_NEx high
-
FMC_NEx hold time after FMC_NWAIT
th(NE_NWAIT)
invalid
4THCLK+12
-
1. Guaranteed by characterization results, not tested in production.
DS12737 Rev 6
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307
Electrical characteristics
STM32L552xx
Figure 56. Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms
t
w(NE)
FMC_NEx
FMC_NOE
FMC_NWE
t
t
w(NWE)
t
h(NE_NWE)
v(NWE_NE)
t
th(A_NWE)
v(A_NE)
FMC_A[25:0]
Address
t
t
v(BL_NE)
h(BL_NWE)
FMC_NBL[1:0]
NBL
t
t
v(Data_NE)
h(Data_NWE)
Data
FMC_D[15:0]
t
v(NADV_NE)
t
w(NADV)
(1)
FMC_NADV
FMC_NWAIT
th(NE_NWAIT)
tsu(NWAIT_NE)
MS32754V1
(1)
Table 134. Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings
Symbol
Parameter
Min
Max
Unit
tw(NE)
tv(NWE_NE)
tw(NWE)
FMC_NE low time
FMC_NEx low to FMC_NWE low
FMC_NWE low time
4THCLK-0.5 4THCLK+1
Ns
THCLK-0.5
THCLK-0.5
THCLK +1
THCLK+1
FMC_NWE high to FMC_NE high hold
time
th(NE_NWE)
2THCLK-0.5
-
tv(A_NE)
th(A_NWE)
tv(BL_NE)
FMC_NEx low to FMC_A valid
Address hold time after FMC_NWE high
FMC_NEx low to FMC_BL valid
-
0
2THCLK-1
-
-
-
THCLK
th(BL_NWE)
tv(Data_NE)
th(Data_NWE)
tv(NADV_NE)
tw(NADV)
FMC_BL hold time after FMC_NWE high 2THCLK-0.5
-
FMC_NEx low to Data valid
Data hold time after FMC_NWE high
FMC_NEx low to FMC_NADV low
FMC_NADV low time
-
THCLK+3
2THCLK+1
-
-
-
1
THCLK+ 1.5
1. Guaranteed by characterization results, not tested in production.
282/340
DS12737 Rev 6
STM32L552xx
Electrical characteristics
Table 135. Asynchronous non-multiplexed SRAM/PSRAM/NOR write-NWAIT
(1)
timings
Symbol
Parameter
Min
Max
Unit
tw(NE)
FMC_NE low time
9THCLK-0.5
6THCLK-0.5
9THCLK+1.5
6THCLK+1
tw(NWE)
FMC_NWE low time
tsu(NWAIT_
NE)
ns
FMC_NWAIT valid before FMC_NEx high
7THCLK+13
-
-
th(NE_NWA
IT)
FMC_NEx hold time after FMC_NWAIT invalid 5THCLK+13
1. Guaranteed by characterization results, not tested in production.
Figure 57. Asynchronous multiplexed PSRAM/NOR read waveforms
t
w(NE)
FMC_ NE
FMC_NOE
t
t
h(NE_NOE)
v(NOE_NE)
t
w(NOE)
t
FMC_NWE
t
h(A_NOE)
v(A_NE)
FMC_ A[25:16]
Address
NBL
t
t
v(BL_NE)
h(BL_NOE)
FMC_ NBL[1:0]
t
h(Data_NE)
t
su(Data_NE)
t
t
t
h(Data_NOE)
v(A_NE)
Address
su(Data_NOE)
Data
FMC_ AD[15:0]
t
t
h(AD_NADV)
v(NADV_NE)
t
w(NADV)
FMC_NADV
FMC_NWAIT
th(NE_NWAIT)
tsu(NWAIT_NE)
MS32755V1
DS12737 Rev 6
283/340
307
Electrical characteristics
STM32L552xx
(1)
Table 136. Asynchronous multiplexed PSRAM/NOR read timings
Symbol
Parameter
Min
Max
Unit
4THCLK
+1
tw(NE)
FMC_NE low time
4THCLK-0.5
2THCLK
+1
tv(NOE_NE)
tw(NOE)
FMC_NEx low to FMC_NOE low
FMC_NOE low time
2THCLK -0.5
THCLK-0.5
THCLK-1
THCLK+
0.5
FMC_NOE high to FMC_NE high
hold time
th(NE_NOE)
tv(A_NE)
-
FMC_NEx low to FMC_A valid
-
3
tv(NADV_NE) FMC_NEx low to FMC_NADV low
0.5
1.5
THCLK+
1.5
tw(NADV)
th(AD_NADV)
th(A_NOE)
FMC_NADV low time
THCLK
Ns
FMC_AD(address) valid hold time
after FMC_NADV high)
THCLK-3
-
Address hold time after
FMC_NOE high
Address holded until next
read operation
-
-
-
tsu(Data_NE) Data to FMC_NEx high setup time
THCLK+14
14
Data to FMC_NOE high setup
tsu(Data_NOE)
time
Data hold time after FMC_NEx
th(Data_NE)
high
0
0
-
-
Data hold time after FMC_NOE
th(Data_NOE)
high
1. Guaranteed by characterization results, not tested in production.
(1)
Table 137. Asynchronous multiplexed PSRAM/NOR read-NWAIT timings
Symbol
Parameter
Min
Max
Unit
tw(NE)
FMC_NE low time
FMC_NOE low time
8THCLK-0.5 9THCLK+1
5THCLK -0.5 6THCLK +1
tw(NOE)
Ns
tsu(NWAIT_NE) FMC_NWAIT valid before FMC_NEx high
5THCLK+12
4THCLK+11
-
-
FMC_NEx hold time after FMC_NWAIT
th(NE_NWAIT)
invalid
1. Guaranteed by characterization results, not tested in production.
284/340
DS12737 Rev 6
STM32L552xx
Electrical characteristics
Figure 58. Asynchronous multiplexed PSRAM/NOR write waveforms
t
w(NE)
FMC_ NEx
FMC_NOE
t
t
w(NWE)
t
h(NE_NWE)
v(NWE_NE)
FMC_NWE
t
t
h(A_NWE)
v(A_NE)
FMC_ A[25:16]
Address
t
t
v(BL_NE)
h(BL_NWE)
FMC_ NBL[1:0]
NBL
v(Data_NADV)
Data
t
t
h(Data_NWE)
t
v(A_NE)
Address
FMC_ AD[15:0]
t
t
h(AD_NADV)
v(NADV_NE)
t
w(NADV)
FMC_NADV
FMC_NWAIT
th(NE_NWAIT)
tsu(NWAIT_NE)
MS32756V1
DS12737 Rev 6
285/340
307
Electrical characteristics
STM32L552xx
(1)
Table 138. Asynchronous multiplexed PSRAM/NOR write timings
Symbol
Parameter
Min
Max
Unit
tw(NE)
FMC_NE low time
5THCLK-0.5 5THCLK+1
THCLK– 0.5 THCLK+ 1
tv(NWE_NE)
FMC_NEx low to FMC_NWE low
2THCLK+0.
tw(NWE)
FMC_NWE low time
2THCLK-0.5
5
th(NE_NWE)
tv(A_NE)
FMC_NWE high to FMC_NE high hold time
FMC_NEx low to FMC_A valid
FMC_NEx low to FMC_NADV low
FMC_NADV low time
2THCLK-0.5
-
-
3
1
tv(NADV_NE)
tw(NADV)
0
THCLK+0.5 THCLK+1.5
ns
FMC_AD(adress) valid hold time after
FMC_NADV high)
th(AD_NADV)
THCLK-3
-
Address
holded until
next write
operation
th(A_NWE)
Address hold time after FMC_NWE high
-
th(BL_NWE)
tv(BL_NE)
FMC_BL hold time after FMC_NWE high
FMC_NEx low to FMC_BL valid
2THCLK-0.5
-
THCLK
THCLK+2
-
-
tv(Data_NADV)
th(Data_NWE)
FMC_NADV high to Data valid
-
Data hold time after FMC_NWE high
2THCLK+0.5
1. Guaranteed by characterization results, not tested in production.
(1)
Table 139. Asynchronous multiplexed PSRAM/NOR write-NWAIT timings
Symbol
Parameter
Min
Max
Unit
tw(NE)
FMC_NE low time
10THCLK-0.5 10THCLK+1
7THCLK-0.5 7THCLK+0.5
tw(NWE)
FMC_NWE low time
ns
tsu(NWAIT_NE) FMC_NWAIT valid before FMC_NEx high 7THCLK+11.5
FMC_NEx hold time after FMC_NWAIT
-
-
th(NE_NWAIT)
5THCLK+12.5
invalid
1. Guaranteed by characterization results, not tested in production.
Synchronous waveforms and timings
Figure 59 through Figure 62 represent synchronous waveforms and Table 140
through Table 143 provide the corresponding timings. The results shown in these
tables are obtained with the following FMC configuration:
•
•
•
•
•
BurstAccessMode = FMC_BurstAccessMode_Enable
MemoryType = FMC_MemoryType_CRAM
WriteBurst = FMC_WriteBurst_Enable
CLKDivision = 1
DataLatency = 1 for NOR Flash; DataLatency = 0 for PSRAM
286/340
DS12737 Rev 6
STM32L552xx
Electrical characteristics
In all timing tables, the THCLK is the HCLK clock period.
•
Maximum FMC_CLK =55MHz for CLKDIV=0x1 and 42MHz CLKDIV=0x0 for
2.7V<VDD<3.6V
•
Maximum FMC_CLK =55MHz for CLKDIV=0x1 and 26MHz CLKDIV=0x0 for
1.71V<VDD<1.9V with CL=20pF
Figure 59. Synchronous multiplexed NOR/PSRAM read timings
BUSTURN = 0
t
t
w(CLK)
w(CLK)
FMC_CLK
Data latency = 0
d(CLKL-NExL)
t
td(CLKH-NExH)
FMC_NEx
t
t
d(CLKL-NADVL)
d(CLKL-NADVH)
FMC_NADV
t
td(CLKH-AIV)
d(CLKL-AV)
FMC_A[25:16]
t
td(CLKH-NOEH)
d(CLKL-NOEL)
FMC_NOE
t
t
t
h(CLKH-ADV)
d(CLKL-ADIV)
t
t
t
su(ADV-CLKH)
su(ADV-CLKH)
d(CLKL-ADV)
h(CLKH-ADV)
FMC_AD[15:0]
AD[15:0]
t
D1
D2
t
su(NWAITV-CLKH)
h(CLKH-NWAITV)
FMC_NWAIT
(WAITCFG = 1b,
WAITPOL + 0b)
t
t
su(NWAITV-CLKH)
h(CLKH-NWAITV)
FMC_NWAIT
(WAITCFG = 0b,
WAITPOL + 0b)
t
t
h(CLKH-NWAITV)
su(NWAITV-CLKH)
MS32757V1
DS12737 Rev 6
287/340
307
Electrical characteristics
STM32L552xx
(1)(2)
Table 140. Synchronous multiplexed NOR/PSRAM read timings
Symbol
Parameter
Min
Max
Unit
)
tw(CLK)
FMC_CLK period
R*THCLK-0.5(2)
-
2.5
-
td(CLKL-NExL)
FMC_CLK low to FMC_NEx low (x=0..2)
-
td(CLKH_NExH) FMC_CLK high to FMC_NEx high (x= 0…2)
R*THCLK/2+1(2)
td(CLKL-NADVL)
td(CLKL-NADVH)
td(CLKL-AV)
FMC_CLK low to FMC_NADV low
FMC_CLK low to FMC_NADV high
-
2
-
2.5
-
FMC_CLK low to FMC_Ax valid (x=16…25)
5.5
FMC_CLK high to FMC_Ax invalid
(x=16…25)
td(CLKH-AIV)
R*THCLK/2 + 1(2)
-
td(CLKL-NOEL)
td(CLKH-NOEH)
td(CLKL-ADV)
td(CLKL-ADIV)
FMC_CLK low to FMC_NOE low
FMC_CLK high to FMC_NOE high
FMC_CLK low to FMC_AD[15:0] valid
FMC_CLK low to FMC_AD[15:0] invalid
-
2
-
ns
R*THCLK/2+1(2)
-
3
-
0
FMC_A/D[15:0] valid data before FMC_CLK
high
tsu(ADV-CLKH)
th(CLKH-ADV)
2
4
-
-
FMC_A/D[15:0] valid data after FMC_CLK
high
tsu(NWAIT-
CLKH)
FMC_NWAIT valid before FMC_CLK high
FMC_NWAIT valid after FMC_CLK high
1.5
4
-
-
th(CLKH-NWAIT)
1. Guaranteed by characterization results, not tested in production.
2. Clock ratio R = (HCLK period /FMC_CLK period).
288/340
DS12737 Rev 6
STM32L552xx
Electrical characteristics
Figure 60. Synchronous multiplexed PSRAM write timings
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DS12737 Rev 6
289/340
307
Electrical characteristics
STM32L552xx
(1)(2)
Table 141. Synchronous multiplexed PSRAM write timings
Symbol
Parameter
Min
Max
Unit
R*THCLK-0.5(2)
tw(CLK)
FMC_CLK period, VDD range= 2.7 to 3.6 V
FMC_CLK low to FMC_NEx low (x=0..2)
-
2.5
-
td(CLKL-NExL)
-
td(CLKH-NExH) FMC_CLK high to FMC_NEx high (x= 0…2) R*THCLK/2+1(2)
td(CLKL-NADVL)
td(CLKL-NADVH)
td(CLKL-AV)
FMC_CLK low to FMC_NADV low
FMC_CLK low to FMC_NADV high
-
2
-
2.5
-
FMC_CLK low to FMC_Ax valid (x=16…25)
5.75
FMC_CLK high to FMC_Ax invalid
(x=16…25)
td(CLKH-AIV)
R*THCLK/2+1(2)
-
td(CLKL-NWEL)
td(CLKH-NWEH)
td(CLKL-ADV)
td(CLKL-ADIV)
FMC_CLK low to FMC_NWE low
FMC_CLK high to FMC_NWE high
FMC_CLK low to to FMC_AD[15:0] valid
FMC_CLK low to FMC_AD[15:0] invalid
-
2
-
ns
R*THCLK/2+1(2)
-
3
-
0
FMC_A/D[15:0] valid data after FMC_CLK
low
td(CLKL-DATA)
-
3.5
td(CLKL-NBLL)
td(CLKH-NBLH)
FMC_CLK low to FMC_NBL low
FMC_CLK high to FMC_NBL high
1
-
-
R*THCLK/2+1.5(2)
tsu(NWAIT-CLKH) FMC_NWAIT valid before FMC_CLK high
th(CLKH-NWAIT) FMC_NWAIT valid after FMC_CLK high
1.5
4
-
-
1. Guaranteed by characterization results, not tested in production.
2. Clock ratio R = (HCLK period /FMC_CLK period).
290/340
DS12737 Rev 6
STM32L552xx
Electrical characteristics
Figure 61. Synchronous non-multiplexed NOR/PSRAM read timings
t
t
w(CLK)
w(CLK)
FMC_CLK
t
t
d(CLKH-NExH)
d(CLKL-NExL)
Data latency = 0
d(CLKL-NADVH)
FMC_NEx
t
t
d(CLKL-NADVL)
FMC_NADV
FMC_A[25:0]
t
t
d(CLKH-AIV)
d(CLKL-AV)
t
t
d(CLKL-NOEL)
d(CLKH-NOEH)
FMC_NOE
t
t
su(DV-CLKH)
h(CLKH-DV)
su(DV-CLKH)
t
t
h(CLKH-DV)
FMC_D[15:0]
FMC_NWAIT
D1
D2
t
t
su(NWAITV-CLKH)
h(CLKH-NWAITV)
(WAITCFG = 1b,
WAITPOL + 0b)
t
t
h(CLKH-NWAITV)
su(NWAITV-CLKH)
FMC_NWAIT
(WAITCFG = 0b,
WAITPOL + 0b)
t
t
su(NWAITV-CLKH)
h(CLKH-NWAITV)
MS32759V1
DS12737 Rev 6
291/340
307
Electrical characteristics
STM32L552xx
(1)(2)
Table 142. Synchronous non-multiplexed NOR/PSRAM read timings
Symbol
Parameter
Min
Max
Unit
R*THCLK-0.5(2)
tw(CLK)
FMC_CLK period
-
td(CLKL-NExL)
FMC_CLK low to FMC_NEx low (x=0..2)
-
2.5
-
td(CLKH-NExH) FMC_CLK high to FMC_NEx high (x= 0…2)
R*THCLK/2+1(2)
td(CLKL-NADVL)
td(CLKL-NADVH)
td(CLKL-AV)
FMC_CLK low to FMC_NADV low
FMC_CLK low to FMC_NADV high
-
2
-
2.5
-
FMC_CLK low to FMC_Ax valid (x=0…25)
5.5
FMC_CLK high to FMC_Ax invalid
(x=0…25)
td(CLKH-AIV)
R*THCLK/2+0.5(2)
-
ns
td(CLKL-NOEL)
td(CLKH-NOEH)
FMC_CLK low to FMC_NOE low
FMC_CLK high to FMC_NOE high
-
2
-
R*THCLK/2+1(2)
FMC_D[15:0] valid data before FMC_CLK
high
tsu(DV-CLKH)
th(CLKH-DV)
2
4
-
-
FMC_D[15:0] valid data after FMC_CLK
high
tsu(NWAIT-
CLKH)
FMC_NWAIT valid before FMC_CLK high
FMC_NWAIT valid after FMC_CLK high
1.5
4
-
-
th(CLKH-NWAIT)
1. Guaranteed by characterization results, not tested in production.
2. Clock ratio R = (HCLK period /FMC_CLK period).
292/340
DS12737 Rev 6
STM32L552xx
Electrical characteristics
Figure 62. Synchronous non-multiplexed PSRAM write timings
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DS12737 Rev 6
293/340
307
Electrical characteristics
STM32L552xx
(1)(2)
Table 143. Synchronous non-multiplexed PSRAM write timings
Symbol
Parameter
Min
Max
Unit
R*THCLK-0.5(2)
-
tw(CLK)
FMC_CLK period
-
td(CLKL-NExL)
FMC_CLK low to FMC_NEx low (x=0..2)
2.5
FMC_CLK high to FMC_NEx high (x=
0…2)
R*THCLK/2 +1(2)
td(CLKH-NExH)
-
td(CLKL-NADVL)
td(CLKL-NADVH)
td(CLKL-AV)
FMC_CLK low to FMC_NADV low
FMC_CLK low to FMC_NADV high
-
2
-
2.5
-
FMC_CLK low to FMC_Ax valid (x=0…25)
5.5
FMC_CLK high to FMC_Ax invalid
(x=0…25)
R*THCLK/2+0.5(2)
td(CLKH-AIV)
-
ns
td(CLKL-NWEL)
td(CLKH-NWEH)
FMC_CLK low to FMC_NWE low
FMC_CLK high to FMC_NWE high
-
2
-
R*THCLK/2+1(2)
FMC_D[15:0] valid data after FMC_CLK
low
td(CLKL-Data)
-
3.5
td(CLKL-NBLL)
td(CLKH-NBLH)
FMC_CLK low to FMC_NBL low
FMC_CLK high to FMC_NBL high
1
-
-
-
-
R*THCLK/2+1.5(2)
tsu(NWAIT-CLKH) FMC_NWAIT valid before FMC_CLK high
th(CLKH-NWAIT) FMC_NWAIT valid after FMC_CLK high
1.5
4
1. Guaranteed by characterization results, not tested in production.
2. Clock ratio R = (HCLK period /FMC_CLK period).
NAND controller waveforms and timings
Figure 63 through Figure 66 represent synchronous waveforms, and Table 144 and
Table 145 provide the corresponding timings. The results shown in these tables are
obtained with the following FMC configuration:
•
•
•
•
•
•
•
•
•
•
•
•
•
•
COM.FMC_SetupTime = 0x01
COM.FMC_WaitSetupTime = 0x03
COM.FMC_HoldSetupTime = 0x02
COM.FMC_HiZSetupTime = 0x01
ATT.FMC_SetupTime = 0x01
ATT.FMC_WaitSetupTime = 0x03
ATT.FMC_HoldSetupTime = 0x02
ATT.FMC_HiZSetupTime = 0x01
Bank = FMC_Bank_NAND
MemoryDataWidth = FMC_MemoryDataWidth_16b
ECC = FMC_ECC_Enable
ECCPageSize = FMC_ECCPageSize_512Bytes
TCLRSetupTime = 0
TARSetupTime = 0
294/340
DS12737 Rev 6
STM32L552xx
Electrical characteristics
In all timing tables, the THCLK is the HCLK clock period.
Figure 63. NAND controller waveforms for read access
FMC_NCEx
ALE (FMC_A17)
CLE (FMC_A16)
FMC_NWE
th(NOE-ALE)
td(NCE-NOE)
FMC_NOE (NRE)
FMC_D[15:0]
tsu(D-NOE)
th(NOE-D)
MSv38003V1
Figure 64. NAND controller waveforms for write access
FMC_NCEx
ALE (FMC_A17)
CLE (FMC_A16)
th(NWE-ALE)
td(NCE-NWE)
FMC_NWE
FMC_NOE (NRE)
FMC_D[15:0]
th(NWE-D)
tv(NWE-D)
MSv38004V1
DS12737 Rev 6
295/340
307
Electrical characteristics
STM32L552xx
Figure 65. NAND controller waveforms for common memory read access
FMC_NCEx
ALE (FMC_A17)
CLE (FMC_A16)
th(NOE-ALE)
td(NCE-NOE)
FMC_NWE
FMC_NOE
tw(NOE)
tsu(D-NOE)
th(NOE-D)
FMC_D[15:0]
MSv38005V1
Figure 66. NAND controller waveforms for common memory write access
FMC_NCEx
ALE (FMC_A17)
CLE (FMC_A16)
td(NCE-NWE)
tw(NWE)
th(NOE-ALE)
FMC_NWE
FMC_NOE
td(D-NWE)
tv(NWE-D)
th(NWE-D)
FMC_D[15:0]
MSv38006V1
(1)
Table 144. Switching characteristics for NAND Flash read cycles
Symbol
Parameter
Min
Max
Unit
Tw(N0E)
FMC_NOE low width
4THCLK - 0.5 4THCLK+0.5
FMC_D[15-0] valid data before FMC_NOE
high
Tsu(D-NOE)
14
-
ns
Th(NOE-D) FMC_D[15-0] valid data after FMC_NOE high
0
-
Td(ALE-NOE)
Th(NOE-ALE)
FMC_ALE valid before FMC_NOE low
FMC_NWE high to FMC_ALE invalid
-
3THCLK-1
-
3THCLK-0.5
1. Guaranteed by characterization results, not tested in production.
296/340
DS12737 Rev 6
STM32L552xx
Electrical characteristics
(1)
Table 145. Switching characteristics for NAND Flash write cycles
Symbol
Parameter
Min
Max
Unit
Tw(NWE)
Tv(NWE-D)
Th(NWE-D)
FMC_NWE low width
4THCLK - 0.5 4THCLK+0.5
FMC_NWE low to FMC_D[15-0] valid
FMC_NWE high to FMC_D[15-0] invalid
0
-
-
2THCLK
ns
FMC_D[15-0] valid before FMC_NWE
high
Td(D-NWE)
5THCLK - 1
-
Td(ALE_NWE)
Th(NWE-ALE)
FMC_ALE valid before FMC_NWE low
FMC_NWE high to FMC_ALE invalid
-
3THCLK-1
-
3THCLK-0.5
1. Guaranteed by characterization results, not tested in production.
DS12737 Rev 6
297/340
307
Electrical characteristics
STM32L552xx
5.3.31
OCTOSPI characteristics
Unless otherwise specified, the parameters given in Table 146, Table 147 and Table 148 for
OCTOSPI are derived from tests performed under the ambient temperature, f
frequency
AHB
and V supply voltage conditions summarized in Table 27: General operating conditions,
DD
with the following configuration:
•
•
Output speed is set to OSPEEDRy[1:0] = 11
For DTR(with DQS)/HyperBus the delay resister is set to DLYCFGR[3:0]=4
Refer to Section 5.3.15: I/O port characteristics for more details on the input/output alternate
function characteristics.
The following table summarizes the parameters measured in SDR mode.
(1)
(2)
Table 146. OCTOSPI characteristics in SDR mode
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
1.71<VDD<3.6
Voltage ranges 0/1
20 pF
-
-
54
2.7<VDD<3.6
Voltage ranges 0/1
20pF
-
-
-
-
-
-
90
56
26
OCTOSPI clock
frequency
F(CLK)
MHz
1.71<VDD<3.6
Voltage ranges 0/1
15pF
1.71<VDD<3.6
Voltage range 2
CL=20pF
tw(CKH)
tw(CKL)
t(CK)/2 - 0.5
t(CK)/2 -0.5
-
-
t(CK)/2
t(CK)/2
PRESCALER[7:0] =
n = 0,1,3,5
OCTOSPI clock high
and low time
(n/2)×t(CK)/
(n+1)- 0.5
(n/2)×t(CK)
/(n+1)
tw(CKH)
tw(CKL)
-
-
OCTOSPI clock high
and low time
PRESCALER[7:0] =
n = 2,4,6,8
(n/2+1)×t(CK)/
(n+1) -0.5
(n/2+1)×
t(CK)/(n+1)
Odd division
Voltage ranges 0/1
Voltage range 2
Voltage ranges 0/1
Voltage range 2
Voltage ranges 0/1
Voltage range 2
Voltage ranges 0/1
Voltage range 2
1.5
2
-
-
-
ts(IN)
th(IN)
Data input setup time
Data input hold time
ns
-
4
-
-
-
5.25
-
-
0.5
0.5
-
2
1.5
-
tv(OUT) Data output valid time
th(OUT) Data output hold time
-
-0.5
-0.75
-
-
1. Values in the table applies to octal and quad SPI mode.
2. Guaranteed by characterization results.
298/340
DS12737 Rev 6
STM32L552xx
Electrical characteristics
The following table summarizes the parameters measured in DTR mode (no DQS).
(1)
(2)
Table 147. OCTOSPI characteristics in DTR mode (no DQS)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
1.71<VDD<3.6
Voltage ranges 0/1
20 pF
-
-
56
2.7<VDD<3.6
Voltage ranges 0/1
20 pF
-
-
-
60
OCTOSPI clock
frequency
F(CLK)
MHz
1.71<VDD<3.6
Voltage ranges 0/1
15 pF
-
-
60
26
1.71<VDD<3.6
-
-
Voltage range 2
t(CK)/2
-0.5
tw(CKH)
t(CK)/2+0.5
t(CK)/2+0.5
PRESCALER[7:0] =
n = 0,1,3,5
OCTOSPI clock
high and low time
t(CK)/2
-0.5
tw(CKL)
tw(CKH)
tw(CKL)
-
-
-
(n/2)×t(CK)/(n+1)-
0.5
(n/2)×t(CK)/(n+1)+
0.5
OCTOSPI clock
high and low time
PRESCALER[7:0] =
n = 2,4,6,8
(n/2+1)×t(CK)/
(n+1) -0.5
(n/2+1)×t(CK)/
(n+1)+0.5
Odd division
Voltage ranges 0/1
Voltage range 2
Voltage ranges 0/1
Voltage range 2
2.5
1.5
3
-
-
Data input setup
time
tsr(IN), tsf(IN)
thr(IN),thf(IN)
-
-
-
-
-
Data input hold
time
4
-
ns
DHQC=0
Voltage
-
5.5
7.25
Tpclk
/4
DHQC=1
ranges
Tpclk/4
+2
Pres=1,2
0/1
-
tvr(OUT),
tvf(OUT)
Data output valid
time
…
+0.5
Voltage range 2
DHQC=0
-
8
-
10
-
DHQC=0
Voltage
5
DHQC=1
ranges
Tpclk/4
-0.25
Pres=1,2
0/1
-
-
-
-
thr(OUT),
thf(OUT)
Data output hold
time
…
Voltage range 2
DHQC=0
8
1. Values in the table applies to octal and quad SPI mode.
2. Guaranteed by characterization results.
DS12737 Rev 6
299/340
307
Electrical characteristics
STM32L552xx
The following table summarizes the parameters measured in DTR mode (with DQS) /
HyperBus.
(1)
Table 148. OCTOSPI characteristics in DTR mode (with DQS) /Octal and HyperBus
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
1.71<VDD<3.6
Voltage ranges 0/1
20 pF
-
-
58(2)
2.7<VDD<3.6
Voltage ranges 0/1
20 pF
OCTOSPI
clock
frequency
F(CLK)
-
-
-
76(2)
MHz
1.71<VDD<3.6
Voltage range 2
20 pF
-
-
26(2)
t(CK)/2
-1
t(CK)/2
+0.5
OCTOSPI
clock high and
low time
tw(CKH)
-
-
t(CK)/2
-0.5
tw(CKL)
tw(CKH)
tw(CKL)
tv(CK)
-
-
-
-
-
t(CK)/2+0.5
Even division
(n/2)×t(CK)/(n+1)
-0.5
(n/2)×t(CK)/(n+1)
+0.5
OCTOSPI
clock high and
low time
ns
(n/2+1)×t(CK)/
(n+1) - 0.5
(n/2+1)*×(CK)/
(n+1)+0.5
Odd division
Clock valid
time
-
-
-
t(CK) + 2
-
t(CK)/2
-0.5
Clock hold
time
th(CK)
CK,CK#
crossing level
on CK rising
edge
VODr(CK)(3)
VODf(CK)(3)
VDD=1v8
VDD=1v8
832
840
-
-
1050
1071
mV
CK,CK#
crossing level
on CK falling
edge
300/340
DS12737 Rev 6
STM32L552xx
Electrical characteristics
(1)
Table 148. OCTOSPI characteristics in DTR mode (with DQS) /Octal and HyperBus (continued)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Chip select
high time
tw(CS)
-
3×t(CK)
-
-
Data input
valid time
tv(DQ)
tv(DS)
th(DS)
0
-
-
-
Data strobe
input valid time
Data strobe
input hold time
-
-
0
-
-
-
-
Data strobe
output valid
time
tv(RWDS)
3×t(CK)
t(CK)/2
-5.75(4)
Voltage ranges 0/1
Voltage range 2
-0.75
-2.25
-
-
Data input
setup time
tsr(DQ),tsf(DQ)
thr(DQ),thf(DQ)
t(CK)/2
-8(4)
Voltage ranges 0/1
Voltage range 2
3.75
4.75
-
-
-
-
Data input hold
time
ns
DHQC=
0
-
5.75
7.75
Voltage
DHQC=
ranges 0/1
Tpclk/4
+0.75
Tpclk/4
+2.5
1
tvr(OUT),
tvf(OUT)
Data output
valid time
-
Pres=1,
2…
Voltage range 2
DHQC=0
-
8
-
11
-
DHQC=
0
3.25
Voltage
DHQC=
ranges 0/1
Tpclk/4
-0.25
1
thr(OUT),
thf(OUT)
Data output
hold time
-
-
-
-
Pres=1,
2…
Voltage range 2
DHQC=0
6.5
1. Guaranteed by characterization results.
2. Maximum frequency values are given for a RWDS to DQ skew of maximum +/-1.0 ns.
3. (PA3/PF11), (PF10/PB12), (PF10/PB5), (PE10/PF11), (PA3/PE9) and (PE10/PB5) clk/clk# pair usage is recommended in
order to respect HyperMemory AC differential crossing voltage margins.
4. Data input setup time maximum does not take into account the data level switching duration.
DS12737 Rev 6
301/340
307
Electrical characteristics
STM32L552xx
Figure 67. OCTOSPI timing diagram - SDR mode
tr(CK)
t(CK)
tw(CKH)
tw(CKL)
tf(CK)
Clock
tv(OUT)
th(OUT)
Data output
D0
D1
D2
ts(IN)
th(IN)
Data input
D0
D1
D2
MSv36878V1
Figure 68. OCTOSPI timing diagram - DDR mode
tr(CLK)
t(CLK)
tw(CLKH)
tw(CLKL)
tf(CLK)
Clock
tvf(OUT) thr(OUT)
IO0
tvr(OUT)
thf(OUT)
IO3
Data output
IO1
IO2
IO4
tsr(IN)thr(IN)
IO5
tsf(IN) thf(IN)
Data input
IO0
IO1
IO2
IO3
IO4
IO5
MSv36879V3
Figure 69. OCTOSPI HyperBus clock
tr(CK)
tf(CK#)
tw(CKH)
tw(CK#L)
tw(CKL)
tw(CK#H)
t(CK)
t(CK#)
tf(CK)
tr(CK#)
CK#
CK
VOD(CK)
MSv47732V1
302/340
DS12737 Rev 6
STM32L552xx
Electrical characteristics
Figure 70. OCTOSPI HyperBus read
tw(CS)
CS#
th(CK)
tv(CK)
tACC = Initial Access
CK, CK#
tv(RWDS)
tv(DS)
th(DS)
RWDS
tv(OUT)
th(OUT)
tv(DQ)
ts(DQ)
th(DQ)
Latency Count
Dn
Dn
B
Dn+1
A
Dn+1
47:40 39:32 31:24 23:16
15:8
7:0
DQ[7:0]
A
B
Command-Address
Host drives DQ[7:0] and Memory drives RWDS
Memory drives DQ[7:0] and RWDS
MSv47733V1
Figure 71. OCTOSPI HyperBus read with double latency
CS#
tRWR =Read Write Recovery
Additional Latency
tACC = Access
CK, CK#
RWDS
tCKDS
High = 2x Latency Count
Low = 1x Latency Count
RWDS and Data
are edge aligned
Dn
A
Dn Dn+1 Dn+1
47:40 39:32 31:24 23:16 15:8
7:0
DQ[7:0]
B
A
B
Command-Address
Memory drives DQ[7:0]
and RWDS
Host drives DQ[7:0] and Memory drives RWDS
MSv49351V1
Figure 72. OCTOSPI HyperBus write
tw(CS)
CS#
Read Write Recovery
tv(CK)
Access Latency
th(CK)
CK, CK#
RWDS
th(OUT)
tv(OUT)
tv(RWDS)
High = 2x Latency Count
Low = 1x Latency Count
Latency Count
th(OUT)
th(OUT)
tv(OUT)
tv(OUT)
Dn
A
Dn
B
Dn+1
A
Dn+1
B
47:40 39:32 31:24 23:16
15:8
7:0
DQ[7:0]
Command-Address
Host drives DQ[7:0] and RWDS
Host drives DQ[7:0] and Memory drives RWDS
MSv47734V1
DS12737 Rev 6
303/340
307
Electrical characteristics
Delay block
STM32L552xx
Unless otherwise specified, the parameters given in Table 149 for delay block are derived
from tests performed under the ambient temperature, fPCLKx frequency and VDD supply
voltage conditions summarized in Table 27: General operating conditions with the
configuration shown in the figure below.
Table 149. Dynamics characteristics: delay block characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
tinit
t∆
Initial delay
Unit delay
-
-
1175
250
1375
500
1450
750
ps
5.3.32
SD/SDIO/MMC card host interfaces (SDMMC)
Unless otherwise specified, the parameters given in Table 150 and Table 151 for SDIO are
derived from tests performed under the ambient temperature, fPCLKx frequency and VDD
supply voltage conditions summarized in Table 27: General operating conditions with the
following configuration:
•
•
•
Output speed is set to OSPEEDRy[1:0] = 11
Capacitive load C = 30 pF
Measurement points are done at CMOS levels: 0.5V
DD
Refer to Section 5.3.15: I/O port characteristics for more details on the input/output
characteristics.
Table 150. Dynamics characteristics: SD / eMMC characteristics,
(1)
VDD=2.7V to 3.6 V
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Clock frequency in data transfer
mode
fPP
-
0
-
70
MHz
-
-
SDIO_CK/fPCLK2 frequency ratio
Clock low time
-
-
-
8/3
tW(CKL)
tW(CKH)
fpp =52MHz
fpp =52MHz
8.5
8.5
9.5
9.5
-
-
ns
ns
ns
ns
Clock high time
CMD, D inputs (referenced to CK) in eMMC legacy/SDR/DDR and SD HS/SDR(2)/DDR(2) mode
tISU
tIHD
Input setup time HS
Input hold time HS
-
-
2.5
1
-
-
-
-
CMD, D outputs (referenced to CK) in eMMC legacy/SDR/DDR and SD HS/SDR(2)/DDR(2) mode
tOV
tOH
Output valid time HS
Output hold time HS
-
-
-
5
-
6
-
4.5
CMD, D inputs (referenced to CK) in SD default mode
tISUD
tIHD
Input setup time SD
Input hold time SD
-
-
2.5
1
-
-
-
-
304/340
DS12737 Rev 6
STM32L552xx
Electrical characteristics
Table 150. Dynamics characteristics: SD / eMMC characteristics,
(1)
VDD=2.7V to 3.6 V (continued)
Symbol
Parameter Conditions Min
Typ
Max
Unit
CMD, D outputs (referenced to CK) in SD default mode
tOVD
tOHD
Output valid default time SD
Output hold default time SD
-
-
-
1
-
2.5
-
ns
0.5
1. Guaranteed by characterization results.
2. For SD 1.8 V support, an external voltage converter is needed.
(1)(2)
Unit
Table 151. Dynamics characteristics: eMMC characteristics VDD=1.71 V to 1.9 V
Symbol
Parameter
Conditions
Min
Typ
Max
Clock frequency in data transfer
mode
fPP
-
0
-
52
MHz
-
-
SDIO_CK/fPCLK2 frequency ratio
Clock low time
-
-
-
8/3
tW(CKL)
tW(CKH)
fpp =52 MHz
fpp =52 MHz
8.5
8.5
9.5
9.5
-
-
ns
ns
ns
Clock high time
CMD, D inputs (referenced to CK) in eMMC mode
tISU
tIH
Input setup time HS
Input hold time HS
-
-
2.5
2
-
-
-
-
CMD, D outputs (referenced to CK) in eMMC mode
tOV
tOH
Output valid time HS
Output hold time HS
-
-
-
5.5
-
6.5
-
4
1. Guaranteed by characterization results.
2. Cload=20 pF.
DS12737 Rev 6
305/340
307
Electrical characteristics
STM32L552xx
See the different SDMMC diagrams in Figure 73, Figure 74 and Figure 75 below.
Figure 73. SDIO high-speed mode
Figure 74. SD default mode
CK
t
t
OVD
OHD
D, CMD
(output)
ai14888
Figure 75. DDR mode
tr(CLK)
t(CLK)
tw(CLKH)
tw(CLKL)
tf(CLK)
Clock
tvf(OUT) thr(OUT)
IO0
tvr(OUT)
thf(OUT)
IO3
Data output
IO1
IO2
IO4
tsr(IN)thr(IN)
IO5
tsf(IN) thf(IN)
Data input
IO0
IO1
IO2
IO3
IO4
IO5
MSv36879V3
306/340
DS12737 Rev 6
STM32L552xx
Electrical characteristics
5.3.33
UCPD characteristics
UCPD controller complies with USB Type-C Rev 1.2 and USB Power Delivery Rev 3.0
specifications.
Table 152. UCPD characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Sink mode only
3.0
3.3
3.3
3.6
UCPD operating
supply voltage
VDD
V
Sink and source mode
3.135
3.465
DS12737 Rev 6
307/340
307
Package information
STM32L552xx
6
Package information
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK packages, depending on their level of environmental compliance. ECOPACK
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK is an ST trademark.
6.1
LQFP48 package information
LQFP48 is a 48-pin, 7 x 7 mm, low-profile quad flat package.
Figure 76. LQFP48 outline
SEATING
PLANE
C
0.25 mm
GAUGE PLANE
ccc
C
D
L
D1
D3
L1
36
25
37
24
b
48
13
PIN 1
IDENTIFICATION
1
12
e
5B_ME_V2
1. Drawing is not to scale.
Table 153. LQFP48 mechanical data
millimeters
inches(1)
Typ
Symbol
Min
Typ
Max
Min
Max
A
-
-
-
1.600
0.150
1.450
-
-
-
0.0630
0.0059
0.0571
A1
A2
0.050
1.350
0.0020
0.0531
1.400
0.0551
308/340
DS12737 Rev 6
STM32L552xx
Package information
Table 153. LQFP48 mechanical data (continued)
millimeters
Typ
inches(1)
Symbol
Min
Max
Min
Typ
Max
b
c
0.170
0.220
-
0.270
0.200
9.200
7.200
-
0.0067
0.0087
-
0.0106
0.0079
0.3622
0.2835
-
0.090
0.0035
D
8.800
9.000
7.000
5.500
9.000
7.000
5.500
0.500
0.600
1.000
3.5°
0.3465
0.3543
0.2756
0.2165
0.3543
0.2756
0.2165
0.0197
0.0236
0.0394
3.5°
D1
D3
E
6.800
0.2677
-
-
8.800
9.200
7.200
-
0.3465
0.3622
0.2835
-
E1
E3
e
6.800
0.2677
-
-
-
-
-
-
L
0.450
0.750
-
0.0177
0.0295
-
L1
k
-
0°
-
-
0°
-
7°
7°
ccc
-
0.080
-
0.0031
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Figure 77. LQFP48 recommended footprint
0.50
1.20
0.30
36
25
37
24
0.20
7.30
9.70 5.80
7.30
48
13
12
1
1.20
5.80
9.70
ai14911d
1. Dimensions are expressed in millimeters.
DS12737 Rev 6
309/340
333
Package information
STM32L552xx
Device marking for LQFP48
The following figure gives an example of topside marking orientation versus pin 1 identifier
location.
The printed markings may differ depending on the supply chain.
Other optional marking or inset/upset marks, which also depend on supply chain operations,
are not indicated below.
Figure 78. Example of LQFP48 package marking (package top view)
STM32L552
Product identification(1)
CET6P
Date code
Y WW
Pin 1 identifier
Revision code
R
MSv60472V2
1. Parts marked as ES or E or accompanied by an Engineering Sample notification letter are not yet qualified
and therefore not approved for use in production. ST is not responsible for any consequences resulting
from such use. In no event will ST be liable for the customer using any of these engineering samples in
production. ST’s Quality department must be contacted prior to any decision to use these engineering
samples to run a qualification activity.
310/340
DS12737 Rev 6
STM32L552xx
Package information
6.2
UFQFPN48 package information
UFQFPN48 is a 48-lead, 7 x 7 mm, 0.5 mm pitch, ultra thin fine pitch quad flat package.
Figure 79. UFQFPN48 outline
Pin 1 identifier
laser marking area
D
A
E
Y
E
Seating
plane
T
ddd
A1
b
e
Detail Y
D
Exposed pad
area
D2
1
L
48
C 0.500x45°
pin1 corner
R 0.125 typ.
Detail Z
E2
1
48
Z
A0B9_ME_V3
1. Drawing is not to scale.
2. All leads/pads should also be soldered to the PCB to improve the lead/pad solder joint life.
3. There is an exposed die pad on the underside of the UFQFPN package. It is recommended to connect and
solder this back-side pad to PCB ground.
Table 154. UFQFPN48 mechanical data
millimeters
Typ
inches(1)
Typ
Symbol
Min
Max
Min
Max
A
A1
D
0.500
0.000
6.900
6.900
5.500
5.500
0.550
0.020
7.000
7.000
5.600
5.600
0.600
0.050
7.100
7.100
5.700
5.700
0.0197
0.0000
0.2717
0.2717
0.2165
0.2165
0.0217
0.0008
0.2756
0.2756
0.2205
0.2205
0.0236
0.0020
0.2795
0.2795
0.2244
0.2244
E
D2
E2
DS12737 Rev 6
311/340
333
Package information
STM32L552xx
Table 154. UFQFPN48 mechanical data (continued)
millimeters
Typ
inches(1)
Symbol
Min
Max
Min
Typ
Max
L
T
0.300
0.400
0.152
0.250
0.500
-
0.500
-
0.0118
0.0157
0.0060
0.0098
0.0197
-
0.0197
-
-
-
b
0.200
0.300
-
0.0079
0.0118
-
e
-
-
-
-
ddd
0.080
0.0031
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Figure 80. UFQFPN48 recommended footprint
7.30
6.20
48
37
1
36
5.60
0.20
7.30
5.80
6.20
5.60
0.30
12
25
13
24
0.75
0.50
0.55
5.80
A0B9_FP_V2
1. Dimensions are expressed in millimeters.
Device marking for UFQFPN48 (7 x 7)
The following figure gives an example of topside marking orientation versus pin 1 identifier
location.
The printed markings may differ depending on the supply chain.
Other optional marking or inset/upset marks, which also depend on supply chain operations,
are not indicated below.
312/340
DS12737 Rev 6
STM32L552xx
Package information
Figure 81. Example of UFQFPN48 package marking (package top view)
STM32L552
CEU6P
Product identification(1)
Date code
Y WW
Pin 1 identifier
Revision code
R
MSv60473V2
1. Parts marked as ES or E or accompanied by an Engineering Sample notification letter are not yet qualified
and therefore not approved for use in production. ST is not responsible for any consequences resulting
from such use. In no event will ST be liable for the customer using any of these engineering samples in
production. ST’s Quality department must be contacted prior to any decision to use these engineering
samples to run a qualification activity.
DS12737 Rev 6
313/340
333
Package information
STM32L552xx
6.3
LQFP64 package information
LQFP64 is a 64-pin, 10 x 10 mm, low-profile quad flat package.
Figure 82. LQFP64 outline
SEATING PLANE
C
0.25 mm
GAUGE PLANE
ccc
C
D
D1
D3
L
L1
33
48
32
49
64
b
17
16
1
PIN 1
IDENTIFICATION
e
5W_ME_V3
1. Drawing is not to scale.
Table 155. LQFP64 mechanical data
millimeters
inches(1)
Typ
Symbol
Min
Typ
Max
Min
Max
A
A1
A2
b
-
-
1.600
-
-
0.0630
0.050
-
0.150
0.0020
-
0.0059
1.350
1.400
0.220
-
1.450
0.0531
0.0551
0.0087
-
0.0571
0.170
0.270
0.0067
0.0106
c
0.090
0.200
0.0035
0.0079
D
-
-
-
-
-
12.000
10.000
7.500
12.000
10.000
-
-
-
-
-
-
-
-
-
-
0.4724
0.3937
0.2953
0.4724
0.3937
-
-
-
-
-
D1
D3
E
E1
314/340
DS12737 Rev 6
STM32L552xx
Package information
Table 155. LQFP64 mechanical data (continued)
millimeters
Typ
inches(1)
Symbol
Min
Max
Min
Typ
Max
E3
e
-
7.500
0.500
3.5°
-
-
0.2953
0.0197
3.5°
-
-
-
7°
-
-
7°
K
0°
0°
L
0.450
0.600
1.000
-
0.750
-
0.0177
0.0236
0.0394
-
0.0295
-
L1
ccc
-
-
-
-
0.080
0.0031
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Figure 83. LQFP64 recommended footprint
48
33
0.3
0.5
49
32
12.7
10.3
10.3
7.8
17
64
1.2
16
1
12.7
ai14909c
1. Dimensions are expressed in millimeters.
Device marking for LQFP64 (10 x 10)
The following figure gives an example of topside marking orientation versus pin 1 identifier
location.
The printed markings may differ depending on the supply chain.
Other optional marking or inset/upset marks, which also depend on supply chain operations,
are not indicated below.
DS12737 Rev 6
315/340
333
Package information
STM32L552xx
Figure 84. Example of LQFP64 package marking (package top view)
STM32L552
RET6P
Product identification(1)
Date code
Y WW
Pin 1 identifier
Revision code
R
MSv60474V2
1. Parts marked as ES or E or accompanied by an Engineering Sample notification letter are not yet qualified
and therefore not approved for use in production. ST is not responsible for any consequences resulting
from such use. In no event will ST be liable for the customer using any of these engineering samples in
production. ST’s Quality department must be contacted prior to any decision to use these engineering
samples to run a qualification activity.
316/340
DS12737 Rev 6
STM32L552xx
Package information
6.4
WLCSP81 package information
WLCSP81 is a 81-ball, 4.36 x 4.07 mm, 0.4 mm pitch, wafer level chip scale package.
Figure 85. WLCSP81 outline
bbb Z
A1
A1 BALL LOCATION
F
e1
aaa
(4x)
G
DETAIL A
E
e2
e
e
A
A2
D
BOTTOM VIEW
TOP VIEW
SIDE VIEW
A2
A3
BUMP
b
eee
Z
FRONT VIEW
Z
b(81x)
ccc Z XY
ddd
Z
SEATING PLANE
DETAIL A
ROTATED 90
B01H_WLCSP81_ME_V1
1. Drawing is not to scale.
2. Dimension is measured at the maximum bump diameter parallel to primary datum Z.
3. Primary datum Z and seating plane are defined by the spherical crowns of the bump.
4. Bump position designation per JESD 95-1, SPP-010.
Table 156. WLCSP81 mechanical data
millimeters
Typ
inches(1)
Symbol
Min
Max
Min
Typ
Max
A(2)
A1
A2
A3(3)
b
-
-
0.59
-
-
-
0.023
-
0.18
0.38
0.025
0.25
4.36
4.07
-
0.007
0.015
0.001
0.010
0.172
0.160
-
-
-
-
-
-
-
-
-
0.22
4.33
4.05
0.28
4.39
4.09
0.009
0.170
0.159
0.011
0.173
0.161
D
E
DS12737 Rev 6
317/340
333
Package information
STM32L552xx
Table 156. WLCSP81 mechanical data (continued)
millimeters
Typ
inches(1)
Symbol
Min
Max
Min
Typ
Max
e
-
-
-
-
-
-
-
-
-
-
0.40
3.20
3.20
0.580
0.435
0.10
0.10
0.10
0.05
0.05
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0.016
0.126
0.126
0.023
0.017
0.004
0.004
0.004
0.002
0.002
-
-
-
-
-
-
-
-
-
-
e1
e2
F(4)
G(4)
aaa
bbb
ccc
ddd
eee
1. Values in inches are converted from mm and rounded to 4 decimal digits.
2. The maximum total package height is calculated by the RSS method (Root Sum Square) using nominal
and tolerances values of A1 and A2.
3. Back side coating. Nominal dimension is rounded to the 3rd decimal place resulting from process
capability.
4. Calculated dimensions are rounded to the 3rd decimal place.
Figure 86. WLCSP 81 recommended footprint
Dpad
Dsm
BGA_WLCSP_FT_V1
1. Dimensions are expressed in millimeters.
318/340
DS12737 Rev 6
STM32L552xx
Package information
Table 157. WLCSP81 recommended PCB design rules
Dimension Recommended values
Pitch
0.4 mm
Dpad
Dsm
0,225 mm
0.290 mm typ. (depends on soldermask registration tolerance)
Stencil opening
Stencil thickness
0.250 mm
0.100 mm
Device marking for WLCSP81
The following figure gives an example of topside marking orientation versus ball A1 identifier
location.
The printed markings may differ depending on the supply chain.
Other optional marking or inset/upset marks, which also depend on supply chain operations,
are not indicated below.
Figure 87. Example of WLCSP81 package marking (package top view)
Product identification(1)
L552ME6P
Date code
Additional information
Y WW R
MSv60475V2
1. Parts marked as ES or E or accompanied by an Engineering Sample notification letter are not yet qualified
and therefore not approved for use in production. ST is not responsible for any consequences resulting
from such use. In no event will ST be liable for the customer using any of these engineering samples in
production. ST’s Quality department must be contacted prior to any decision to use these engineering
samples to run a qualification activity.
DS12737 Rev 6
319/340
333
Package information
STM32L552xx
6.5
LQFP100 package information
LQFP100 is a 100-pin, 14 x 14 mm low-profile quad flat package.
Figure 88. LQFP100 outline
SEATING PLANE
C
0.25 mm
GAUGE PLANE
ccc
75
C
D
D1
D3
L
L1
51
50
76
100
26
PIN 1
IDENTIFICATION
25
1
e
1L_ME_V5
1. Drawing is not to scale.
Table 158. LQPF100 mechanical data
millimeters
inches(1)
Typ
Symbol
Min
Typ
Max
Min
Max
A
A1
A2
b
-
-
1.600
0.150
1.450
0.270
0.200
16.200
14.200
-
-
-
0.0630
0.0059
0.0571
0.0106
0.0079
0.6378
0.5591
-
0.050
1.350
0.170
0.090
15.800
13.800
-
-
0.0020
0.0531
0.0067
0.0035
0.6220
0.5433
-
-
1.400
0.220
-
0.0551
0.0087
-
c
D
16.000
14.000
12.000
16.000
0.6299
0.5512
0.4724
0.6299
D1
D3
E
15.800
16.200
0.6220
0.6378
320/340
DS12737 Rev 6
STM32L552xx
Package information
Table 158. LQPF100 mechanical data (continued)
millimeters
Typ
inches(1)
Symbol
Min
Max
Min
Typ
Max
E1
E3
e
13.800
14.000
12.000
0.500
0.600
1.000
3.5°
14.200
0.5433
0.5512
0.4724
0.0197
0.0236
0.0394
3.5°
0.5591
-
-
-
-
-
-
-
-
L
0.450
0.750
-
0.0177
0.0295
-
L1
k
-
0.0°
-
-
0.0°
-
7.0°
0.080
7.0°
0.0031
ccc
-
-
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Figure 89. LQFP100 recommended footprint
75
51
76
50
0.5
0.3
16.7 14.3
100
26
1.2
1
25
12.3
16.7
ai14906c
1. Dimensions are expressed in millimeters.
Device marking for LQFP100
The following figure gives an example of topside marking orientation versus pin 1 identifier
location.
The printed markings may differ depending on the supply chain.
Other optional marking or inset/upset marks, which also depend on supply chain operations,
are not indicated below.
DS12737 Rev 6
321/340
333
Package information
STM32L552xx
Figure 90. Example of LQFP100 package marking (package top view)
STM32L552
VET6Q
Product identification(1)
R
Date code
YWW
Pin 1 identifier
MSv60476V2
1. Parts marked as ES or E or accompanied by an Engineering Sample notification letter are not yet qualified
and therefore not approved for use in production. ST is not responsible for any consequences resulting
from such use. In no event will ST be liable for the customer using any of these engineering samples in
production. ST’s Quality department must be contacted prior to any decision to use these engineering
samples to run a qualification activity.
322/340
DS12737 Rev 6
STM32L552xx
Package information
6.6
UFBGA132 package information
UFBGA132 is a 132-pin, 7 x 7 mm, ultra thin fine pitch ball grid array package.
Figure 91. UFBGA132 outline
A1 ball identifier
B
A
D
E1
E
e
Z
A
Z
e
D1
M
1
12
Øb (132 balls)
BOTTOM VIEW
TOP VIEW
M
Øeee C A B
Ø fff
M
C
A4
ddd C
A2
A3
A1
A
b
SEATING
PLANE
UFBGA132_A0G8_ME_V2
1. Drawing is not to scale.
Table 159. UFBGA132 mechanical data
millimeters
inches(1)
Typ
Symbol
Min
Typ
Max
Min
Max
A
A1
A2
A3
A4
b
-
-
0.600
-
-
0.0236
-
-
0.110
-
-
0.0043
-
0.450
0.130
0.320
0.290
7.000
5.500
7.000
5.500
0.500
-
-
0.0177
0.0051
0.0126
0.0114
0.2756
0.2165
0.2756
0.2165
0.0197
-
-
-
-
-
-
-
-
-
0.240
0.340
0.0094
0.0134
D
6.850
7.150
0.2697
0.2815
D1
E
-
-
-
-
6.850
7.150
0.2697
0.2815
E1
e
-
-
-
-
-
-
-
-
DS12737 Rev 6
323/340
333
Package information
Symbol
STM32L552xx
Table 159. UFBGA132 mechanical data (continued)
millimeters
Typ
inches(1)
Min
Max
Min
Typ
Max
Z
-
0.750
0.080
0.150
0.050
-
-
-
-
-
-
-
-
0.0295
0.0031
0.0059
0.0020
-
-
-
-
ddd
eee
fff
-
-
-
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Figure 92. UFBGA132 recommended footprint
Dpad
Dsm
UFBGA132_A0G8_FP_V1
Table 160. UFBGA132 recommended PCB design rules (0.5 mm pitch BGA)
Dimension Recommended values
Pitch
Dpad
0.5 mm
0.280 mm
0.370 mm typ. (depends on the soldermask reg-
istration tolerance)
Dsm
Stencil opening
Stencil thickness
Pad trace width
Ball diameter
0.280 mm
Between 0.100 mm and 0.125 mm
0.100 mm
0.280 mm
324/340
DS12737 Rev 6
STM32L552xx
Package information
Device marking for UFBGA132 (7 x 7)
The following figure gives an example of topside marking orientation versus ball A1 identifier
location.
The printed markings may differ depending on the supply chain.
Other optional marking or inset/upset marks, which also depend on supply chain operations,
are not indicated below.
Figure 93. Example of UFBGA132 package marking (package top view)
STM32L
Product identification(1)
552QEI6Q
Date code
Y WW
Additional
information
R
MSv60480V2
1. Parts marked as ES or E or accompanied by an Engineering Sample notification letter are not yet qualified
and therefore not approved for use in production. ST is not responsible for any consequences resulting
from such use. In no event will ST be liable for the customer using any of these engineering samples in
production. ST’s Quality department must be contacted prior to any decision to use these engineering
samples to run a qualification activity.
DS12737 Rev 6
325/340
333
Package information
STM32L552xx
6.7
LQFP144 package information
LQFP144 is a 144-pin, 20 x 20 mm low-profile quad flat package.
Figure 94. LQFP144 outline
SEATING
PLANE
C
0.25 mm
GAUGE PLANE
ccc
C
D
L
D1
D3
L1
108
73
109
72
37
144
1
36
PIN 1
IDENTIFICATION
e
1A_ME_V4
1. Drawing is not to scale.
326/340
DS12737 Rev 6
STM32L552xx
Symbol
Package information
Table 161. LQFP144 mechanical data
millimeters
inches(1)
Typ
Min
Typ
Max
Min
Max
A
A1
A2
b
-
0.050
1.350
0.170
0.090
21.800
19.800
-
-
1.600
0.150
1.450
0.270
0.200
22.200
20.200
-
-
-
0.0630
0.0059
0.0571
0.0106
0.0079
0.8740
0.7953
-
-
0.0020
0.0531
0.0067
0.0035
0.8583
0.7795
-
-
1.400
0.220
-
0.0551
0.0087
-
c
D
22.000
20.000
17.500
22.000
20.000
17.500
0.500
0.600
1.000
3.5°
0.8661
0.7874
0.6890
0.8661
0.7874
0.6890
0.0197
0.0236
0.0394
3.5°
D1
D3
E
21.800
19.800
-
22.200
20.200
-
0.8583
0.7795
-
0.8740
0.7953
-
E1
E3
e
-
-
-
-
L
0.450
-
0.750
-
0.0177
-
0.0295
-
L1
k
0°
7°
0°
7°
ccc
-
-
0.080
-
-
0.0031
1. Values in inches are converted from mm and rounded to 4 decimal digits.
DS12737 Rev 6
327/340
333
Package information
STM32L552xx
Figure 95. LQFP144 recommended footprint
1.35
108
73
109
72
0.35
0.5
19.9
17.85
22.6
144
37
1
36
19.9
22.6
ai14905e
1. Dimensions are expressed in millimeters.
Device marking for LQFP144
The following figure gives an example of topside marking orientation versus pin 1 identifier
location.
The printed markings may differ depending on the supply chain.
Other optional marking or inset/upset marks, which also depend on supply chain operations,
are not indicated below.
328/340
DS12737 Rev 6
STM32L552xx
Package information
Figure 96. Example of LQFP144 package marking (package top view)
Product identification(1)
STM32L552ZET6Q
Additional
information
R
Date code
Y WW
Pin 1 identifier
MSv60479V2
1. Parts marked as ES or E or accompanied by an Engineering Sample notification letter are not yet qualified
and therefore not approved for use in production. ST is not responsible for any consequences resulting
from such use. In no event will ST be liable for the customer using any of these engineering samples in
production. ST’s Quality department must be contacted prior to any decision to use these engineering
samples to run a qualification activity.
DS12737 Rev 6
329/340
333
Package information
STM32L552xx
6.8
Thermal characteristics
The maximum chip-junction temperature, T max, in degrees Celsius, may be calculated
J
using the following equation:
T max = T max + (P max x Θ )
J
A
D
JA
Where:
•
•
•
•
T max is the maximum ambient temperature in °C,
A
Θ
is the package junction-to-ambient thermal resistance, in °C/W,
JA
P max is the sum of P
max and P max (P max = P
max + P max),
INT I/O
D
INT
I/O
D
P
max is the product of I and V , expressed in Watts. This is the maximum chip
DD DD
INT
internal power.
P
max represents the maximum power dissipation on output pins where:
I/O
P
max = Σ (V × I ) + Σ ((V
– V ) × I ),
I/O
OL
OL
DDIOx OH OH
taking into account the actual V / I and V / I of the I/Os at low and high level in the
OL OL
OH OH
application.
Table 162. Package thermal characteristics
Symbol
Parameter
Value
Unit
Thermal resistance junction-ambient
LQFP144 20 x 20 mm
47.4
49.3
50.7
52.3
25.6
39.6
45
Thermal resistance junction-ambient
LQFP100 - 14 × 14 mm
Thermal resistance junction-ambient
LQFP64 10 x 10 mm
Thermal resistance junction-ambient
LQFP48 7 x 7 mm
ΘJA
°C/W
Thermal resistance junction-ambient
UFQFPN48 7 x 7 mm
Thermal resistance junction-ambient
UFBGA132 7 x 7 mm
Thermal resistance junction-ambient
WLCSP81 4.36 x 4.07 mm
330/340
DS12737 Rev 6
STM32L552xx
Package information
Table 162. Package thermal characteristics (continued)
Symbol
Parameter
Value
Unit
Thermal resistance junction-case
LQFP144 20 x 20 mm
13.5
Thermal resistance junction-case
LQFP100 - 14 × 14 mm
14
Thermal resistance junction-case
LQFP64 10 x 10 mm
14.2
14.4
1.5
Thermal resistance junction-case
LQFP48 7 x 7 mm
ΘJC
°C/W
Thermal resistance junction-case
UFQFPN48 7 x 7 mm
Thermal resistance junction-case
UFBGA132 7 x 7 mm
38.1
1.5
Thermal resistance junction-case
WLCSP81 4.36 x 4.07 mm
Thermal resistance junction-board
LQFP144 20 x 20 mm
43.3
41.5
39.5
37.4
13.5
13.2
27
Thermal resistance junction-board
LQFP100 - 14 × 14 mm
Thermal resistance junction-board
LQFP64 10 x 10 mm
Thermal resistance junction-board
LQFP48 7 x 7 mm
ΘJB
°C/W
Thermal resistance junction-board
UFQFPN48 7 x 7 mm
Thermal resistance junction-board
UFBGA132 7 x 7 mm
Thermal resistance junction-board
WLCSP81 4.36 x 4.07 mm
6.8.1
6.8.2
Reference document
JESD51-2 Integrated Circuits Thermal Test Method Environment Conditions - Natural
Convection (Still Air). Available from www.jedec.org
Selecting the product temperature range
When ordering the microcontroller, the temperature range is specified in the ordering
information scheme shown in Section 7: Ordering information.
Each temperature range suffix corresponds to a specific guaranteed ambient temperature at
maximum dissipation and, to a specific maximum junction temperature.
DS12737 Rev 6
331/340
333
Package information
STM32L552xx
As applications do not commonly use the STM32L552xx at maximum dissipation, it is useful
to calculate the exact power consumption and junction temperature to determine which
temperature range is best suited to the application.
The following examples show how to calculate the temperature range needed for a given
application.
Example 1: High-performance application
Assuming the following application conditions:
Maximum ambient temperature T
= 82 °C (measured according to JESD51-2),
Amax
I
= 50 mA, V = 3.5 V, maximum 20 I/Os used at the same time in output at low
DDmax
DD
level with I = 8 mA, V = 0.4 V and maximum 8 I/Os used at the same time in output
OL
OL
at low level with I = 20 mA, V = 1.3 V
OL
OL
P
P
50 mA × 3.5 V= 175 mW
INTmax =
20 × 8 mA × 0.4 V + 8 × 20 mA × 1.3 V = 272 mW
IOmax =
This gives: P
= 175 mW and P
= 272 mW:
IOmax
INTmax
P
175 272 = 447 mW
+
Dmax =
Using the values obtained in T
is calculated as follows:
Jmax
–
T
For LQFP100, 49.3°C/W
= 82 °C + (49.3°C/W × 447 mW) = 82 °C + 22.04 °C = 104.04 °C
Jmax
This is within the range of the suffix 6 version parts (–40 < T < 105 °C) see Section 7:
J
Ordering information.
In this case, parts must be ordered at least with the temperature range suffix 6 (see
Section 7: Ordering information).
Note:
With this given P
we can find the TAmax allowed for a given device temperature range
Dmax
(order code suffix 6 or 7).
Suffix 6: T
Suffix 3: T
= T
= T
- (49.3°C/W × 447 mW) = 105 - 22.03= 82.97 °C
- (49.3°C/W × 447 mW) = 130 - 22.03 = 107.97 °C
Amax
Amax
Jmax
Jmax
Example 2: High-temperature application
Using the same rules, it is possible to address applications that run at high ambient
temperatures with a low dissipation, as long as junction temperature T remains within the
J
specified range.
Assuming the following application conditions:
Maximum ambient temperature T
= 100 °C (measured according to JESD51-2),
Amax
I
= 20 mA, V = 3.5 V, maximum 20 I/Os used at the same time in output at low
DDmax
DD
level with I = 8 mA, V = 0.4 V
OL
OL
P
P
20 mA × 3.5 V= 70 mW
INTmax =
× 8 mA × 0.4 V = 64 mW
IOmax = 20
This gives: P
= 70 mW and P
= 64 mW:
IOmax
INTmax
P
70 64 = 134 mW
Dmax =
+
Thus: P
= 134 mW
Dmax
332/340
DS12737 Rev 6
STM32L552xx
Package information
Using the values obtained in T
is calculated as follows:
Jmax
–
T
For LQFP100, 49.3 °C/W
= 100 °C + (49.3 °C/W × 134 mW) = 100 °C + 6.6 °C = 106.6 °C
Jmax
This is above the range of the suffix 6 version parts (–40 < T < 105 °C).
J
In this case, parts must be ordered at least with the temperature range suffix 3 (see
Section 7: Ordering information) unless we reduce the power dissipation in order to be able
to use suffix 6 parts.
DS12737 Rev 6
333/340
333
Ordering information
STM32L552xx
7
Ordering information
Table 163. STM32L552xx ordering information scheme
STM32 552
Example:
L
V
E
T
6 Q TR
Device family
®
STM32 = Arm based 32-bit microcontroller
Product type
L = ultra-low-power
Device subfamily
552 = STM32L552xx
Pin count
C = 48 pins
R = 64 pins
M = 81 pins
V = 100 pins
Q = 132 balls
Z = 144 pins
Flash memory size
E = 512 Kbytes of Flash memory
C= 256 Kbytes of Flash memory
Package
T = LQFP
I = UFBGA
U = UFQFPN
Y = WLCSP
Temperature range
6 = Industrial temperature range, -40 to 85 °C (105 °C junction)
3 = Industrial temperature range, -40 to 125 °C (130°C junction)
Dedicated pinout
Q = Dedicated pinout supporting SMPS step down converter
P = Dedicated pinout supporting external SMPS
Packing
TR = tape and reel
xxx = programmed parts
1. All packages are ECOPACK2 (RoHS compliant and free of brominated, chlorinated and antimony-oxide
flame retardants).
2. For a list of available options (speed, package, etc.) or for further information on any aspect of this device,
please contact your nearest ST sales office.
334/340
DS12737 Rev 6
STM32L552xx
Revision history
8
Revision history
Table 164. Document revision history
Date
Revision
Changes
04-Oct-2019
1
Internal release
Updated Section : Features.
Updated Section 3.3: Memory protection unit.
Updated Section 3.4: Embedded Flash memory.
Updated Table 5: Boot space versus RDP protection.
Updated Section 3.9.4: SMPS step down converter.
Updated Table 11: Functionalities depending on the
working mode.
Updated Figure 7: STM32L552xx clock tree.
Updated Table 27: General operating conditions.
Updated Table 36: Current consumption in Run mode,
code with data processing running from Flash in single
bank, ICACHE ON in 2-way and power supplied by
internal SMPS step down converter.
Updated Table 37: Current consumption in Run mode,
code with data processing running from Flash in single
bank, ICACHE ON in 1-way and power supplied by
internal SMPS step down converter.
Updated Table 38: Current consumption in Run mode,
code with data processing running from Flash in single
bank, ICACHE disabled and power supplied by internal
SMPS step down converter.
18-Dec-2019
2
Updated Table 42: Current consumption in Run mode,
code with data processing running from Flash in dual
bank, ICACHE ON in 2-way and power supplied by
internal SMPS step down converter.
Updated Table 43: Current consumption in Run mode,
code with data processing running from Flash in dual
bank, ICACHE ON in 1-way and power supplied by
internal SMPS step down converter.
Updated Table 44: Current consumption in Run mode,
code with data processing running from Flash in dual
bank, ICACHE disabled and power supplied by internal
SMPS step down converter.
Updated Table 46: Current consumption in Run mode,
code with data processing running from SRAM1 and
power supplied by internal SMPS step down converter.
Updated Table 47: Current consumption in Run and
Low-power run modes, code with data processing
running from SRAM2.
DS12737 Rev 6
335/340
339
Revision history
STM32L552xx
Table 164. Document revision history
Date
Revision
Changes
Updated Table 48: Current consumption in Run mode,
code with data processing running from SRAM2 and
power supplied by internal SMPS step down converter.
Updated Table 61: Current consumption in Sleep mode,
Flash ON and power supplied by internal SMPS step
down converter.
Updated Table 76: Current consumption in Stop 2 mode.
Updated Table 77: Current consumption in Stop 1
mode..
Updated Table 79: Current consumption in Standby
mode.
Updated Table 80: Current consumption in Shutdown
mode.
2
18-Dec-2019
(continued)
Updated Table 81: Current consumption in VBAT mode.
Updated Table 83: Low-power mode wakeup timings.
Updated Table 102: I/O static characteristics.
Updated Table 103: Output voltage characteristics.
Updated Table 129: SPI characteristics.
Updated Table 130: SAI characteristics.
Updated Table 146: OCTOSPI characteristics in SDR
mode.
Updated Table 147: OCTOSPI characteristics in DTR
mode (no DQS).
Updated Table 148: OCTOSPI characteristics in DTR
mode (with DQS)/Octal and HyperBus.
Updated LQFP silhouette on cover page.
Updated Table 2: STM32L552xx features and peripheral
counts.
Updated Figure 1: STM32L552xx block diagram.
Updated Section 3.1: Arm® Cortex®-M33 core with
TrustZone® and FPU
Updated Section 3.2: Art Accelerator – instruction cache
(ICACHE)
Updated Section 3.6: Boot modes
Updated Table 5: Boot space versus RDP protection.
11-Feb-2020
3
Updated Table 6: Example of memory map security
attribution vs SAU configuration regions.
Updated Table 7: Securable peripherals by TZSC.
Updated Section 3.9.4: SMPS step down converter.
Updated Table 10: STM32L552xx modes overview.
Updated Table 11: Functionalities depending on the
working mode.
Updated Table 12: STM32L552xx peripherals
interconnect matrix.
Updated Section 3.17.1: Nested vectored interrupt
controller (NVIC).
336/340
DS12737 Rev 6
STM32L552xx
Revision history
Table 164. Document revision history
Date
Revision
Changes
Updated Section 3.21: Analog-to-digital converter
(ADC).
Removed information related to UFBGA132_ExtSMPS
in Section 4: Pinouts and pin description.
Updated Table 24: Voltage characteristics.
Updated Table 33: Current consumption in Run and
Low-power run modes, code with data processing
running from Flash in single Bank, ICACHE ON in 2-
way.
Updated Table 55: Typical current consumption in Run
and Low-power run modes, with different codes running
from SRAM1.
Updated Table 56: Typical current consumption in Run
mode with internal SMPS, with different codes running
from SRAM1.
3
11-Feb-2020
(continued)
Updated Table 57: Typical current consumption in Run
and Low-power run modes, with different codes running
from SRAM2.
Updated Table 58: Typical current consumption in Run
mode with internal SMPS, with different codes running
from SRAM2.
Updated Table 79: Current consumption in Standby
mode.
Updated Table 99: ESD absolute maximum ratings.
Updated Table 102: I/O static characteristics.
Updated Table 117: VREFBUF characteristics.
Updated Table 119: OPAMP characteristics.
Updated Table 123: Temp and VDD monitoring
characteristics.
Updated:
– Figure 1: STM32L552xx block diagram.
– Figure 2: STM32L552xx power supply overview.
– Figure 3: STM32L552xxxxP power supply overview.
– Figure 12: STM32L552xx UFQFPN48 pinout.
– Figure 13: STM32L552xxxxP UFQFPN48 external
SMPS pinout.
14-May-2020
4
– Section 5.3.2: SMPS step-down converter.
– Table 20: Legend/abbreviations used in the pinout
table.
Updated title of Table 36, Table 37, Table 38, Table 42,
Table 43, Table 44, Table 46, Table 48, Table 50,
Table 52, Table 54, Table 56, Table 58, Table 61.
DS12737 Rev 6
337/340
339
Revision history
STM32L552xx
Table 164. Document revision history
Date
Revision
Changes
Added:
– Table 28: SMPS modes summary
– Table 29: SMPS characteristics
– Table 62: Current consumption in Run mode, code
with data processing running from Flash in single
bank, ICACHE ON in 2-way and power supplied by
external SMPS.
– Table 63: Current consumption in Run mode, code
with data processing running from Flash in single
bank, ICACHE ON in 1-way and power supplied by
external SMPS.
– Table 64: Current consumption in Run mode, code
with data processing running from Flash in single
bank, ICACHE disabled and power supplied by
external SMPS.
– Table 65: Current consumption in Run mode, code
with data processing running from Flash in dual bank,
ICACHE on in 2-way and power supplied by external
SMPS.
– Table 66: Current consumption in Run mode, code
with data processing running from Flash in dual bank,
ICACHE on in 1-way and power supplied by external
SMPS.
– Table 67: Current consumption in Run mode, code
with data processing running from Flash in dual bank,
ICACHE disabled and power supplied by external
SMPS.
14-May-2020
4 (continued)
– Table 68: Current consumption in Run mode, code
with data processing running from SRAM1, and power
supplied by external SMPS.
– Table 69: Current consumption in Run mode, code
with data processing running from SRAM2, and power
supplied by external SMPS.
– Table 70: Current consumption in Sleep mode, Flash
ON and power supplied by external SMPS.
– Table 71: Current consumption in Run mode, code
with data processing running from Flash, ICACHE on
(2-way) and power supplied by external SMPS.
– Table 72: Current consumption in Run mode, code
with data processing running from Flash, ICACHE on
(1-way) and power supplied by external SMPS.
– Table 73: Current consumption in Run mode, code
with data processing running from Flash, ICACHE
disabled and power supplied by external SMPS.
– Table 74: Current consumption in Run mode, code
with data processing running from SRAM1, and power
supplied by external SMPS.
– Table 75: Current consumption in Run mode, code
with data processing running from SRAM2, and power
supplied by external SMPS.
338/340
DS12737 Rev 6
STM32L552xx
Revision history
Table 164. Document revision history
Date
Revision
Changes
Updated Table 102: I/O static characteristics.
Updated Table 146: OCTOSPI characteristics in SDR
mode.
Updated Table 147: OCTOSPI characteristics in DTR
mode (no DQS).
Updated Table 148: OCTOSPI characteristics in DTR
mode (with DQS)/Octal and HyperBus.
14-May-2020
4 (continued)
Updated Table 150: Dynamics characteristics: SD /
eMMC characteristics, VDD=2.7V to 3.6 V.
Updated Table 151: Dynamics characteristics: eMMC
characteristics VDD=1.71 V to 1.9 V.
Updated Section 6: Package information.
Updated Table 163: STM32L552xx ordering information
scheme.
Updated:
– Table 10: STM32L552xx modes overview.
– Section 3.28: True random number generator (RNG).
– Table 77: Current consumption in Stop 1 mode.
– Table 80: Current consumption in Shutdown mode.
– Table 82: Peripheral current consumption.
– Table 83: Low-power mode wakeup timings.
09-Sep-2020
5
Updated:
– Table 10: STM32L552xx modes overview.
– Table 14: Temperature sensor calibration values
– Table 21: STM32L552xx pin definitions
– Table 77: Current consumption in Stop 1 mode
– Table 80: Current consumption in Shutdown mode.
– Table 83: Low-power mode wakeup timings
– Table 117: VREFBUF characteristics
– Table 121: VBAT monitoring characteristics
– Section 3.28: True random number generator (RNG)
Added
21-Oct-2020
6
– Figure 46: VREFBUF in case VRS = 0
– Figure 47: VREFBUF in case VRS = 1
DS12737 Rev 6
339/340
339
STM32L552xx
IMPORTANT NOTICE – PLEASE READ CAREFULLY
STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and
improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on
ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order
acknowledgement.
Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or
the design of Purchasers’ products.
No license, express or implied, to any intellectual property right is granted by ST herein.
Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product.
ST and the ST logo are trademarks of ST. For additional information about ST trademarks, please refer to www.st.com/trademarks. All other
product or service names are the property of their respective owners.
Information in this document supersedes and replaces information previously supplied in any prior versions of this document.
© 2020 STMicroelectronics – All rights reserved
340/340
DS12737 Rev 6
相关型号：
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STMICROELECTR
STM32L562CET3QTR
Ultra-low-power Arm® Cortex®-M33 32-bit MCUTrustZone®FPU, 165DMIPS, up to 512KB Flash, 256KB SRAM, SMPS, AESPKAWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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STMICROELECTR
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