STM32MP157CAC1T [STMICROELECTRONICS]
Arm® dual Cortex®-A7 800 MHz Cortex®-M4 MPU, 3D GPU, TFT/DSI, 37 comm. interfaces, 29 timers, adv. analog, crypto;
| 型号： | STM32MP157CAC1T |
| 厂家： | 
ST |
| 描述： | Arm® dual Cortex®-A7 800 MHz Cortex®-M4 MPU, 3D GPU, TFT/DSI, 37 comm. interfaces, 29 timers, adv. analog, crypto |
| 文件： | 总260页 (文件大小：3560K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
STM32MP157C/F
Arm® dual Cortex®-A7 800 MHz + Cortex®-M4 MPU, 3D GPU,
TFT/DSI, 37 comm. interfaces, 29 timers, adv. analog, crypto
Datasheet - production data
Features
TFBGA
LFBGA
Core
LFBGA448 (18 × 18mm)
LFBGA354 (16 × 16mm)
Pitch 0.8mm
TFBGA361 (12 × 12 mm)
TFBGA257 (10 × 10 mm)
min Pitch 0.5mm
®
®
• 32-bit dual-core Arm Cortex -A7
– L1 32-Kbyte I / 32-Kbyte D for each core
– 256-Kbyte unified level 2 cache
• DDR memory retention in Standby mode
• Controls for PMIC companion chip
®
®
®
– Arm NEON™ and Arm TrustZone
®
®
• 32-bit Arm Cortex -M4 with FPU/MPU
®
Low-power consumption
– Up to 209 MHz (Up to 703 CoreMark )
• Total current consumption down to 2 µA
(Standby mode, no RTC, no LSE, no
BKPSRAM, no RETRAM)
Memories
• External DDR memory up to 1 Gbyte
– up to LPDDR2/LPDDR3-1066 16/32-bit
– up to DDR3/DDR3L-1066 16/32-bit
Clock management
• Internal oscillators: 64 MHz HSI oscillator,
• 708 Kbytes of internal SRAM: 256 Kbytes of
AXI SYSRAM + 384 Kbytes of AHB SRAM +
64 Kbytes of AHB SRAM in Backup domain
and 4 Kbytes of SRAM in Backup domain
4 MHz CSI oscillator, 32 kHz LSI oscillator
• External oscillators: 8-48 MHz HSE oscillator,
32.768 kHz LSE oscillator
• 6 × PLLs with fractional mode
• Dual mode Quad-SPI memory interface
• Flexible external memory controller with up to
16-bit data bus: parallel interface to connect
external ICs and SLC NAND memories with up
to 8-bit ECC
General-purpose input/outputs
• Up to 176 I/O ports with interrupt capability
– Up to 8 secure I/Os
– Up to 6 Wakeup, 3 tampers, 1 active
tamper
Security/safety
®
• Secure boot, TrustZone peripherals, active
Interconnect matrix
tamper
®
• 2 bus matrices
• Cortex -M4 resources isolation
®
®
– 64-bit Arm AMBA AXI interconnect, up to
266 MHz
Reset and power management
• 1.71 V to 3.6 V I/Os supply (5 V-tolerant I/Os)
• POR, PDR, PVD and BOR
®
®
– 32-bit Arm AMBA AHB interconnect, up
to 209 MHz
• On-chip LDOs (RETRAM, BKPSRAM, DSI
3 DMA controllers to unload the CPU
1.2 V, USB 1.8 V, 1.1 V)
• 48 physical channels in total
• Backup regulator (~0.9 V)
• 1 × high-speed general-purpose master direct
• Internal temperature sensors
memory access controller (MDMA)
• Low-power modes: Sleep, Stop and Standby
December 2020
DS12505 Rev 5
1/260
This is information on a product in full production.
www.st.com
STM32MP157C/F
• 2 × dual-port DMAs with FIFO and request
router capabilities for optimal peripheral
management
– Pixel clock up to 90 MHz
– Two layers with programmable colour LUT
®
• MIPI DSI 2 data lanes up to 1 GHz each
Up to 37 communication peripherals
Up to 29 timers and 3 watchdogs
2
• 6 × I C FM+ (1 Mbit/s, SMBus/PMBus)
• 2 × 32-bit timers with up to 4 IC/OC/PWM or
pulse counter and quadrature (incremental)
encoder input
• 4 × UART + 4 × USART (12.5 Mbit/s, ISO7816
interface, LIN, IrDA, SPI slave)
• 6 × SPI (50 Mbit/s, including 3 with full duplex
• 2 × 16-bit advanced motor control timers
2
I S audio class accuracy via internal audio PLL
• 10 × 16-bit general-purpose timers (including 2
or external clock)
basic timers without PWM)
2
• 4 × SAI (stereo audio: I S, PDM, SPDIF Tx)
• 5 × 16-bit low-power timers
• SPDIF Rx with 4 inputs
• HDMI-CEC interface
• MDIO Slave interface
• RTC with sub-second accuracy and hardware
calendar
®
• 2 × 4 Cortex -A7 system timers (secure, non-
™
secure, virtual, hypervisor)
• 3 × SDMMC up to 8-bit (SD / e•MMC / SDIO)
• 1 × SysTick M4 timer
• 2 × CAN controllers supporting CAN FD
protocol, out of which one supports time-
triggered CAN (TTCAN)
• 3 × watchdogs (2 × independent and window)
Hardware acceleration
• 2 × USB 2.0 high-speed Host
+ 1 × USB 2.0 full-speed OTG simultaneously
• AES 128, 192, 256, TDES
– or 1 × USB 2.0 high-speed Host
+ 1 × USB 2.0 high-speed OTG
simultaneously
• HASH (MD5, SHA-1, SHA224, SHA256),
HMAC
• 2 × true random number generator
• 10/100M or Gigabit Ethernet GMAC
(3 oscillators each)
– IEEE 1588v2 hardware,
MII/RMII/GMII/RGMII
• 2 × CRC calculation unit
• 8- to 14-bit camera interface up to 140 Mbyte/s
Debug mode
®
• Arm CoreSight™ trace and debug: SWD and
6 analog peripherals
JTAG interfaces
• 2 × ADCs with 16-bit max. resolution (12 bits
up to 4.5 Msps, 14 bits up to 4 Msps, 16 bits up
to 3.6 Msps)
• 8-Kbyte embedded trace buffer
3072-bit fuses including 96-bit unique ID,
up to 1184-bit available for user
• 1 × temperature sensor
• 2 × 12-bit D/A converters (1 MHz)
All packages are ECOPACK2 compliant
• 1 × digital filters for sigma delta modulator
(DFSDM) with 8 channels/6 filters
• Internal or external ADC/DAC reference V
REF+
Graphics
®
®
• 3D GPU: Vivante - OpenGL ES 2.0
– Up to 26 Mtriangle/s, 133 Mpixel/s
• LCD-TFT controller, up to 24-bit // RGB888
– up to WXGA (1366 × 768) @60 fps or up to
Full HD (1920 × 1080) @30 fps
2/260
DS12505 Rev 5
STM32MP157C/F
Contents
Contents
1
2
3
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.1
Dual-core Arm® Cortex®-A7 subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.1.1
3.1.2
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.2
3.3
3.4
Arm® Cortex®-M4 with FPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Graphic processing unit (GPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.4.1
3.4.2
External SDRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Embedded SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.5
3.6
3.7
3.8
DDR3/DDR3L/LPDDR2/LPDDR3 controller (DDRCTRL) . . . . . . . . . . . . 26
TrustZone address space controller for DDR (TZC) . . . . . . . . . . . . . . . . 27
Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Power supply management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.8.1
3.8.2
Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
3.9
Low-power strategy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
3.10 Reset and clock controller (RCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
3.10.1 Clock management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
3.10.2 System reset sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
3.11 Hardware semaphore (HSEM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
3.12 Inter-processor communication controller (IPCC) . . . . . . . . . . . . . . . . . . 34
3.12.1 IPCC main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
3.13 General-purpose input/outputs (GPIOs) . . . . . . . . . . . . . . . . . . . . . . . . . . 35
3.14 TrustZone protection controller (ETZPC) . . . . . . . . . . . . . . . . . . . . . . . . . 35
3.15 Bus-interconnect matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
3.16 DMA controllers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
3.17 Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . . 38
3.18 Extended interrupt and event controller (EXTI) . . . . . . . . . . . . . . . . . . . . 38
DS12505 Rev 5
3/260
7
Contents
STM32MP157C/F
3.19 Cyclic redundancy check calculation unit (CRC1, CRC2) . . . . . . . . . . . . 39
3.20 Flexible memory controller (FMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
3.21 Dual Quad-SPI memory interface (QUADSPI) . . . . . . . . . . . . . . . . . . . . . 39
3.22 Analog-to-digital converters (ADCs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
3.23 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
3.24 Digital temperature sensor (DTS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
3.25
VBAT operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
3.26 Digital-to-analog converters (DAC1, DAC2) . . . . . . . . . . . . . . . . . . . . . . . 41
3.27 Voltage reference buffer (VREFBUF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
3.28 Digital filter for sigma delta modulators (DFSDM1) . . . . . . . . . . . . . . . . . 42
3.29 Digital camera interface (DCMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
3.30 LCD-TFT display controller (LTDC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
3.31 Display serial interface (DSI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
3.32 True random number generator (RNG1, RNG2) . . . . . . . . . . . . . . . . . . . 45
3.33 Cryptographic and hash processors (CRYP1, CRYP2 and
HASH1, HASH2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
3.34 Boot and security and OTP control (BSEC) . . . . . . . . . . . . . . . . . . . . . . . 46
3.35 Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
3.35.1 Advanced-control timers (TIM1, TIM8) . . . . . . . . . . . . . . . . . . . . . . . . . 48
3.35.2 General-purpose timers (TIM2, TIM3, TIM4, TIM5, TIM12, TIM13,
TIM14, TIM15, TIM16, TIM17) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
3.35.3 Basic timers TIM6 and TIM7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
3.35.4 Low-power timer (LPTIM1, LPTIM2, LPTIM3, LPTIM4, LPTIM5) . . . . . 49
3.35.5 Independent watchdog (IWDG1, IWDG2) . . . . . . . . . . . . . . . . . . . . . . . 49
3.35.6 System window watchdog (WWDG1) . . . . . . . . . . . . . . . . . . . . . . . . . . 49
3.35.7 SysTick timer (Cortex-M4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
3.35.8 Generic timers (Cortex-A7 CNT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
3.36 System timer generation (STGEN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
3.37 Real-time clock (RTC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
3.38 Tamper and backup registers (TAMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
3.39 Inter-integrated circuit interface (I2C1, I2C2, I2C3, I2C4, I2C5, I2C6) . . . 53
3.40 Universal synchronous asynchronous receiver transmitter
(USART1, USART2, USART3, USART6 and UART4, UART5,
UART7, UART8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
3.41 Serial peripheral interface (SPI1, SPI2, SPI3, SPI4, SPI5,
SPI6)– inter- integrated sound interfaces (I2S1, I2S2, I2S3) . . . . . . . . . . 54
4/260
DS12505 Rev 5
STM32MP157C/F
Contents
3.42 Serial audio interfaces (SAI1, SAI2, SAI3, SAI4) . . . . . . . . . . . . . . . . . . . 55
3.43 SPDIF receiver interface (SPDIFRX) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
3.44 Management data input/output (MDIOS) . . . . . . . . . . . . . . . . . . . . . . . . . 56
3.45 Secure digital input/output MultiMediaCard interface
(SDMMC1, SDMMC2, SDMMC3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
3.46 Controller area network (FDCAN1, FDCAN2) . . . . . . . . . . . . . . . . . . . . . 56
3.47 Universal serial bus high-speed host (USBH) . . . . . . . . . . . . . . . . . . . . . 57
3.48 USB on-the-go high-speed (OTG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
3.49 Gigabit Ethernet MAC interface (ETH1) . . . . . . . . . . . . . . . . . . . . . . . . . . 58
3.50 High-definition multimedia interface (HDMI) – Consumer
electronics control (CEC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
3.51 Debug infrastructure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Pinouts, pin description and alternate functions . . . . . . . . . . . . . . . . . 60
Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
4
5
6
6.1
Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
6.1.1
6.1.2
6.1.3
6.1.4
6.1.5
6.1.6
6.1.7
Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . 125
6.2
6.3
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
6.3.1
6.3.2
6.3.3
6.3.4
6.3.5
6.3.6
6.3.7
6.3.8
General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . 129
Embedded reset and power control block characteristics . . . . . . . . . . 131
Embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
Embedded regulators characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 134
Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
Wakeup time from low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . 147
External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 149
DS12505 Rev 5
5/260
7
Contents
STM32MP157C/F
6.3.9
External clock source security characteristics . . . . . . . . . . . . . . . . . . . 155
6.3.10 Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 155
6.3.11 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
6.3.12 PLL spread spectrum clock generation (SSCG) characteristics . . . . . 161
6.3.13 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
6.3.14 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
6.3.15 Absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . 165
6.3.16 I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
6.3.17 I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
6.3.18 NRST and NRST_CORE pin characteristics . . . . . . . . . . . . . . . . . . . . 175
6.3.19 FMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
6.3.20 QUADSPI interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
6.3.21 Delay block (DLYB) characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
6.3.22 16-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
6.3.23 DAC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204
6.3.24 Voltage reference buffer characteristics . . . . . . . . . . . . . . . . . . . . . . . 207
6.3.25 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
6.3.26 DTS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
6.3.27 VBAT ADC monitoring characteristics and charging characteristics . . 210
6.3.28 Temperature and VBAT monitoring characteristics for
tamper detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210
6.3.29 VDDCORE monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 211
6.3.30 Voltage booster for analog switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
6.3.31 Compensation cell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
6.3.32 Digital filter for sigma-delta modulators (DFSDM) characteristics . . . . 211
6.3.33 Camera interface (DCMI) characteristics . . . . . . . . . . . . . . . . . . . . . . . 214
6.3.34 LCD-TFT controller (LTDC) characteristics . . . . . . . . . . . . . . . . . . . . . 215
6.3.35 Timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217
6.3.36 Communications interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217
6.3.37 USART interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235
6.3.38 USB High-Speed PHY characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 235
6.3.39 DSI PHY characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237
6.3.40 JTAG/SWD interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 237
7
Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239
7.1
7.2
TFBGA257 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239
LFBGA354 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243
6/260
DS12505 Rev 5
STM32MP157C/F
Contents
7.3
7.4
7.5
TFBA361 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246
LFBGA448 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250
Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253
7.5.1
Reference documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254
8
9
Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256
DS12505 Rev 5
7/260
7
List of tables
STM32MP157C/F
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
STM32MP157C/F features and peripheral counts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Boot modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
System versus domain power mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Timer feature comparison. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
USART features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Legend/abbreviations used in the pinout table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
STM32MP157C/F pin and ball definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Alternate function AF0 to AF7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Alternate function AF8 to AF15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
Embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . 131
Embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
Embedded reference voltage calibration value. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
REG1V1 embedded regulator (USB_PHY) characteristics . . . . . . . . . . . . . . . . . . . . . . . 134
REG1V2 embedded regulator (DSI) characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
REG1V8 embedded regulator (USB+DSI) characteristics . . . . . . . . . . . . . . . . . . . . . . . . 135
Current consumption (IDDCORE) in Run mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
Current consumption (IDD) in Run mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
Current consumption in Stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
Current consumption in LPLV-Stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
Current consumption in Standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
Current consumption in VBAT mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
Low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
Wakeup time using USART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
High-speed external user clock characteristics
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
Table 26.
Table 27.
Table 28.
Table 29.
(digital bypass) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
High-speed external user clock characteristics
(analog bypass) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
Low-speed external user clock characteristics
Table 30.
Table 31.
(analog bypass) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
Low-speed external user clock characteristics (digital bypass) . . . . . . . . . . . . . . . . . . . . 151
8-48 MHz HSE oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
High-speed external user clock security system (HSE CSS) . . . . . . . . . . . . . . . . . . . . . . 155
HSI oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
CSI oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
PLL1_1600, PLL2_1600 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
PLL3_800, PLL4_800 characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
USB_PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
DSI_PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
SSCG parameters constraint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
OTP characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
DC specifications – DDR3 or DDR3L mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
Table 32.
Table 33.
Table 34.
Table 35.
Table 36.
Table 37.
Table 38.
Table 39.
Table 40.
Table 41.
Table 42.
Table 43.
Table 44.
Table 45.
8/260
DS12505 Rev 5
STM32MP157C/F
List of tables
Table 46.
Table 47.
Table 48.
Table 49.
Table 50.
Table 51.
Table 52.
Table 53.
Table 54.
Table 55.
Table 56.
Table 57.
Table 58.
Table 59.
Table 60.
Table 61.
Table 62.
Table 63.
Table 64.
Table 65.
Table 66.
Table 67.
Table 68.
Table 69.
Table 70.
Table 71.
Table 72.
Table 73.
Table 74.
Table 75.
Table 76.
Table 77.
DC specifications – LPDDR2 or LPDDR3 mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
Output voltage characteristics for all I/Os except PC13, PC14, PC15 and PI8 . . . . . . . . 169
Output voltage characteristics for PC13, PC14, PC15 and PI8 . . . . . . . . . . . . . . . . . . . . 170
Output timing characteristics (HSLV OFF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
Output timing characteristics (HSLV ON, _h IO structure) . . . . . . . . . . . . . . . . . . . . . . . . 173
Output timing characteristics (HSLV ON, _vh IO structure) . . . . . . . . . . . . . . . . . . . . . . . 174
NRST and NRST_CORE pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings . . . . . . . . . . . . . . . . . 178
Asynchronous non-multiplexed SRAM/PSRAM/NOR read - NWAIT timings . . . . . . . . . . 178
Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings . . . . . . . . . . . . . . . . . 179
Asynchronous non-multiplexed SRAM/PSRAM/NOR write - NWAIT timings. . . . . . . . . . 180
Asynchronous multiplexed PSRAM/NOR read timings. . . . . . . . . . . . . . . . . . . . . . . . . . . 181
Asynchronous multiplexed PSRAM/NOR read-NWAIT timings . . . . . . . . . . . . . . . . . . . . 181
Asynchronous multiplexed PSRAM/NOR write timings . . . . . . . . . . . . . . . . . . . . . . . . . . 183
Asynchronous multiplexed PSRAM/NOR write-NWAIT timings . . . . . . . . . . . . . . . . . . . . 183
Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
Synchronous multiplexed PSRAM write timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . 188
Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
Switching characteristics for NAND Flash read cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
Switching characteristics for NAND Flash write cycles. . . . . . . . . . . . . . . . . . . . . . . . . . . 193
QUADSPI characteristics in SDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
QUADSPI characteristics in DDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
Dynamics characteristics: Delay block characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
Minimum sampling time versus RAIN with 47 pF PCB capacitor
up to 125 °C and VDDA = 1.6 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198
ADC accuracy. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
Minimum delay for interleaved conversion versus resolution . . . . . . . . . . . . . . . . . . . . . . 201
DAC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204
DAC accuracy. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206
VREFBUF characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
Temperature sensor calibration values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
DTS characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
Table 78.
Table 79.
Table 80.
Table 81.
Table 82.
Table 83.
Table 84.
Table 85.
Table 86.
Table 87.
Table 88.
Table 89.
Table 90.
Table 91.
Table 92.
Table 93.
Table 94.
Table 95.
Table 96.
V
V
ADC monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210
charging characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210
BAT
BAT
Temperature and VBAT monitoring characteristics for temper detection . . . . . . . . . . . . . 210
monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
V
DDCORE
Voltage booster for analog switch characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
Compensation cell characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
DFSDM measured timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212
DCMI characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214
LTDC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217
LPTIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217
DS12505 Rev 5
9/260
10
List of tables
STM32MP157C/F
Table 97.
Table 98.
Table 99.
Minimum i2c_ker_ck frequency in all I2C modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218
I2C analog filter characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218
I2C FM+ pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219
Table 100. SPI dynamic characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220
Table 101. I2S dynamic characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223
Table 102. SAI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225
Table 103. MDIOS timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227
Table 104. Dynamic characteristics: SD / MMC / e•MMC characteristics,
VDD = 2.7 V to 3.6 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228
Table 105. Dynamic characteristics: SD / MMC / e•MMC characteristics
VDD = 1.71 V to 1.9 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228
Table 106. USB OTG_FS electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230
Table 107. Dynamics characteristics: Ethernet MAC timings for MDIO/SMA. . . . . . . . . . . . . . . . . . . 231
Table 108. Dynamics characteristics: Ethernet MAC timings for RMII . . . . . . . . . . . . . . . . . . . . . . . . 231
Table 109. Dynamics characteristics: Ethernet MAC timings for MII . . . . . . . . . . . . . . . . . . . . . . . . . 232
Table 110. Dynamics characteristics: Ethernet MAC signals for GMII . . . . . . . . . . . . . . . . . . . . . . . 233
Table 111. Dynamics characteristics: Ethernet MAC signals for RGMII . . . . . . . . . . . . . . . . . . . . . . 234
Table 112. USART characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235
Table 113. USB High-Speed PHY characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235
Table 114. DSI PHY characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237
Table 115. Dynamics characteristics: JTAG characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237
Table 116. Dynamics characteristics: SWD characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238
Table 117. TFBGA257 - Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240
Table 118. TFBGA257 - Recommended PCB design rules (0.5/0.65 mm pitch, BGA) . . . . . . . . . . . 241
Table 119. LFBGA354 - Mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243
Table 120. LFBGA354 - Recommended PCB design rules (0.8 mm pitch, BGA) . . . . . . . . . . . . . . . 245
Table 121. TFBGA361 - Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247
Table 122. TFBGA361 - Recommended PCB design rules (0.5/0.65 mm pitch BGA). . . . . . . . . . . . 248
Table 123. LFBGA448 - Mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250
Table 124. LFBGA448 - Recommended PCB design rules (0.8 mm pitch, BGA) . . . . . . . . . . . . . . . 251
Table 125. Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253
Table 126. STM32MP157C/F ordering information scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255
Table 127. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256
10/260
DS12505 Rev 5
STM32MP157C/F
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
STM32MP157C/F block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Power-up/down sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
STM32MP157C/F bus matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Voltage reference buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
STM32MP157C/FADxx TFBGA257 pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
STM32MP157C/FABxx LFBGA354 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
STM32MP157C/FACxx TFBGA361 pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
STM32MP157C/FAAxx LFBGA448 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Pin loading conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
Figure 10. Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
Figure 11. Power supply scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
Figure 12. Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Figure 13. VDDCORE rise time from reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
Figure 14. VDDCORE rise time from LPLV-Stop. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
Figure 15. High-speed external clock source AC timing diagram (digital bypass). . . . . . . . . . . . . . . 149
Figure 16. High-speed external clock source AC timing diagram (analog bypass) . . . . . . . . . . . . . . 150
Figure 17. Low-speed external clock source AC timing diagram (analog bypass) . . . . . . . . . . . . . . 151
Figure 18. Low-speed external clock source AC timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
Figure 19. Typical application with a 24 MHz crystal. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
Figure 20. Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
Figure 21. PLL output clock waveforms in center spread mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
Figure 22. PLL output clock waveforms in down spread mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
Figure 23. VIL/VIH for FT I/Os . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
Figure 24. Recommended NRST and NRST_CORE pin protection . . . . . . . . . . . . . . . . . . . . . . . . . 176
Figure 25. Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms . . . . . . . . . . . . . . 177
Figure 26. Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms . . . . . . . . . . . . . . 179
Figure 27. Asynchronous multiplexed PSRAM/NOR read waveforms. . . . . . . . . . . . . . . . . . . . . . . . 180
Figure 28. Asynchronous multiplexed PSRAM/NOR write waveforms . . . . . . . . . . . . . . . . . . . . . . . 182
Figure 29. Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
Figure 30. Synchronous multiplexed PSRAM write timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
Figure 31. Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . 188
Figure 32. Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
Figure 33. NAND controller waveforms for read access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
Figure 34. NAND controller waveforms for write access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
Figure 35. NAND controller waveforms for common memory read access . . . . . . . . . . . . . . . . . . . . 192
Figure 36. NAND controller waveforms for common memory write access. . . . . . . . . . . . . . . . . . . . 192
Figure 37. QUADSPI timing diagram - SDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
Figure 38. QUADSPI timing diagram - DDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
Figure 39. ADC accuracy characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
Figure 40. Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
Figure 41. 12-bit buffered /non-buffered DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
Figure 42. Channel transceiver timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213
Figure 43. DCMI timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214
Figure 44. LCD-TFT horizontal timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216
Figure 45. LCD-TFT vertical timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216
Figure 46. SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221
(1)
Figure 47. SPI timing diagram - slave mode and CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222
(1)
Figure 48. SPI timing diagram - master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222
DS12505 Rev 5
11/260
12
List of figures
STM32MP157C/F
(1)
Figure 49. I2S slave timing diagram (Philips protocol) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224
(1)
Figure 50. I2S master timing diagram (Philips protocol) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224
Figure 51. SAI master timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226
Figure 52. SAI slave timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226
Figure 53. MDIOS timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227
Figure 54. SDIO high-speed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229
Figure 55. SD default mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229
Figure 56. DDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230
Figure 57. Ethernet MDIO/SMA timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231
Figure 58. Ethernet RMII timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232
Figure 59. Ethernet MII timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233
Figure 60. Ethernet GMII timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234
Figure 61. Ethernet RGMII timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234
Figure 62. JTAG timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238
Figure 63. SWD timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238
Figure 64. TFBGA257 - Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239
Figure 65. TFBGA257 - Recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241
Figure 66. TFBGA257 marking (package top view). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242
Figure 67. LFBGA354 - Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243
Figure 68. LFBGA354 - Recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244
Figure 69. LFBGA354 marking (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245
Figure 70. TFBGA361 - Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246
Figure 71. TFBGA361 - Recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248
Figure 72. TFBGA361 marking (package top view). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249
Figure 73. LFBGA448 - Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250
Figure 74. LFBGA448 - Recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251
Figure 75. LFBGA448 marking (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252
12/260
DS12505 Rev 5
STM32MP157C/F
Introduction
1
Introduction
This datasheet provides the ordering information and mechanical device characteristics of
the STM32MP157C/F microprocessors.
This document should be read in conjunction with the STM32MP157 reference manual
(RM0436), available from the STMicroelectronics website www.st.com.
®(a)
®
®
®
For information on the Arm
Cortex -A7 and Cortex -M4 cores, refer to the Cortex -A7
®
and Cortex -M4 Technical Reference Manuals.
a. Arm is a registered trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere.
DS12505 Rev 5
13/260
59
Description
STM32MP157C/F
2
Description
®
The STM32MP157C/F devices are based on the high-performance dual-core Arm
®
Cortex -A7 32-bit RISC core operating at up to 800 MHz. The Cortex-A7 processor
includes a 32-Kbyte L1 instruction cache for each CPU, a 32-Kbyte L1 data cache for each
CPU and a 256-Kbyte level2 cache. The Cortex-A7 processor is a very energy-efficient
application processor designed to provide rich performance in high-end wearables, and
other low-power embedded and consumer applications. It provides up to 20% more single
thread performance than the Cortex-A5 and provides similar performance than the Cortex-
A9.
The Cortex-A7 incorporates all features of the high-performance Cortex-A15 and Cortex-
™
®
A17 processors, including virtualization support in hardware, NEON , and 128-bit AMBA 4
AXI bus interface.
®
The STM32MP157C/F devices also embed a Cortex -M4 32-bit RISC core operating at up
to 209 MHz frequency. Cortex-M4 core features a floating point unit (FPU) single precision
®
which supports Arm single-precision data-processing instructions and data types. The
®
Cortex -M4 supports a full set of DSP instructions and a memory protection unit (MPU)
which enhances application security.
The STM32MP157C/F devices also embed a 3D graphic processing unit
®
®
(Vivante - OpenGL ES 2.0) running at up to 533 MHz, with performances up to 26
Mtriangle/s, 133 Mpixel/s.
The STM32MP157C/F devices provide an external SDRAM interface supporting external
memories up to 8-Gbit density (1 Gbyte), 16 or 32-bit LPDDR2/LPDDR3 or DDR3/DDR3L
up to 533 MHz.
The STM32MP157C/F devices incorporate high-speed embedded memories with
708 Kbytes of Internal SRAM (including 256 Kbytes of AXI SYSRAM, 3 banks of 128 Kbytes
each of AHB SRAM, 64 Kbytes of AHB SRAM in backup domain and 4 Kbytes of SRAM in
backup domain), as well as an extensive range of enhanced I/Os and peripherals connected
to APB buses, AHB buses, a 32-bit multi-AHB bus matrix and a 64-bit multi layer AXI
interconnect supporting internal and external memories access.
14/260
DS12505 Rev 5
STM32MP157C/F
Description
All the devices offer two ADCs, two DACs, a low-power RTC, 12 general-purpose 16-bit
timers, two PWM timers for motor control, five low-power timers, a true random number
generator (RNG), and a cryptographic acceleration cell. The devices support six digital
filters for external sigma delta modulators (DFSDM). They also feature standard and
advanced communication interfaces.
•
Standard peripherals
2
–
–
–
Six I Cs
Four USARTs and four UARTs
2
Six SPIs, three I Ss full-duplex master/slave. To achieve audio class accuracy, the
2
I S peripherals can be clocked via a dedicated internal audio PLL or via an
external clock to allow synchronization.
Four SAI serial audio interfaces
One SPDIF Rx interface
–
–
–
–
–
Management data input/output slave (MDIOS)
Three SDMMC interfaces
An USB high-speed Host with two ports two high-speed PHYs and a USB OTG
high-speed with full-speed PHY or high-speed PHY shared with second port of
USB Host.
–
–
–
Two FDCAN interface, including one supporting TTCAN mode
A Gigabit Ethernet interface
HDMI-CEC
•
Advanced peripherals including
–
–
–
–
–
A flexible memory control (FMC) interface
A Quad-SPI Flash memory interface
A camera interface for CMOS sensors
An LCD-TFT display controller
A DSI Host interface.
Refer to Table 1: STM32MP157C/F features and peripheral counts for the list of peripherals
available on each part number.
A comprehensive set of power-saving mode allows the design of low-power applications.
The STM32MP157C/F devices are proposed in 4 packages ranging from 257 to 448 balls
with pitch 0.5 mm to 0.8 mm. The set of included peripherals changes with the device
chosen.
These features make the STM32MP157C/F suitable for a wide range of consumer,
industrial, white goods and medical applications.
Figure 1 shows the general block diagram of the device family.
DS12505 Rev 5
15/260
59
Description
STM32MP157C/F
Table 1. STM32MP157C/F features and peripheral counts
Features
TFBGA257
LFBGA354
TFBGA361
LFBGA448
Body size (mm)
10x10
0.5(1)
0.30
<1.2
257
16x16
0.8
12x12
0.5(1)
0.30
<1.2
361
18x18
0.8
Pitch (mm)
Package
CPU
Ball size (mm)
Thickness (mm)
Ball count
0.40
<1.4
354
0.40
<1.4
448
-
Dual-core Cortex-A7 FPU Neon TrustZone
2 × 32-Kbyte L1 data cache
Caches size
Frequency
2 × 32-Kbyte L1 instruction cache
256-Kbyte level 2 unified coherent cache
-
-
STM32MP157C: 2 × 650 MHz
STM32MP157F: 2 × 800 MHz
GPU
Vivante - Open GL ES 2.0
for 3D graphics
MCU core
Frequency
Frequency
533 MHz
Cortex-M4 FPU
209 MHz
-
-
ROM
128 Kbytes (secure)
256 Kbytes (securable)
384 Kbytes
CPU system
MCU subsystem
MCU retention
Backup
Embedded SRAM
64 Kbytes
4 Kbytes (securable, tamper protected)
Up to 1 Gbyte, single rank
-
16-bit 533 MHz
32-bit 533 MHz
16-bit 533 MHz
32-bit 533 MHz
LPDDR2/3
-
-
-
-
Up to 1 Gbyte, single rank
-
DDR3/3L
Backup registers
128 bytes (32x32-bit, securable, tamper protected)
16/260
DS12505 Rev 5
STM32MP157C/F
Description
Table 1. STM32MP157C/F features and peripheral counts (continued)
Features
TFBGA257
LFBGA354
TFBGA361
LFBGA448
Advanced 16 bits
2
8
2
2
5
16 bits
General
purpose
32 bits
Basic
16 bits
Low power 16 bits
A7 timers 64 bits
2 × 4 (secure, non-secure, virtual, hypervisor)
1
M4
24 bits
SysTick
RTC/AWU
1 (securable)
Watchdog
SPI
3 (independent, independent secure, window)
-
-
6 (1 securable)
3
Having I2S
I2C (with SMB/PMB support)
6 (2 securable)
-
USART (smartcard, SPI, IrDA, LIN)
+ UART (IrDA, LIN)
4 + 4 (including 1 securable USART)
some can be a boot source
Boot
4 (up to 8 audio channels), with I2S master/slave, PCM input,
SPDIF-TX
SAI
-
2 ports
-
-
EHCI/OHCI Host
Embedded HS PHY with BCD
USB
OTG HS/FS
Yes, embedded FS or HS PHY with BCD, can be a boot source Boot
(dual role port)
Embedded PHYs
SPDIF-RX
3 (2 × high-speed + 1 × full-speed)
-
-
-
-
4 inputs
FDCAN
2 (1 × TTCAN), clock calibration, 10 Kbyte shared buffer
1
HDMI-CEC
1 × USART, 1 × SPI, 2 × I2C
1 × USART, 1 × SPI, 2 × I2C
Including the following securable
-
on securable GPIOs
SDMMC (SD, SDIO, e•MMC)
QuadSPI
3 (8 + 8 + 4 bits), e•MMC or SD can be a boot source
Boot
Boot
Yes (dual-quad), can be a boot source
DS12505 Rev 5
17/260
59
Description
STM32MP157C/F
Table 1. STM32MP157C/F features and peripheral counts (continued)
Features
TFBGA257
LFBGA354
TFBGA361
LFBGA448
Parallel address/data 8/16-bit
FMC Parallel AD-Mux 8/16-bit
NAND 8/16-bit
-
4 × CS, up to 4 × 64 Mbyte
4 × CS, up to 4 × 64 Mbytes
No
boot
Yes, 1 × CS, SLC, BCH4/8, can be a boot source
Boot
-
Gigabit Ethernet
-
MII, RMII, GMII, RGMII with
PTP and EEE
10/100M Ethernet
MII, RMII with PTP and EEE
Up to 24-bit data, up to 90 MHz pixel clock
(up to 1366 × 768 60 fps or up to 1920 × 1080 30 fps)
LCD-TFT
Parallel interface
-
2 × data lanes 1 GHz each
(up to 1366 × 768 60 fps or up to 1920 × 1080 30 fps)
Display serial interface (DSI)
DMA
-
-
-
3 instances (1 securable), 48 physical channels in total
DES, TDES, AES-256
dual instances (secure and non-secure)
Cryptography
SHA-256, MD5, HMAC
dual instances (secure and non-secure)
Hash
-
True random number generator
Fuses (one-time programmable)
Camera interface Bus width
GPIOs with interrupt (total count)
Securable GPIOs
True-RNG, dual instances (secure and non-secure)
3072 effective bits (secure, >1500 bits available for user)
14-bit
-
-
-
98
-
148
176
8
6
-
-
-
Wakeup pins
4
Tamper pins (active tamper)
DFSDM
2 (1)
3 (1)
8 input channels with 6 filters
2 (up to 3.6/4/4.5/5/6 Msps on 16/14/12/10/8-bit each)
Up to 16-bit synchronized ADC
Low noise 16 bit (differential)
16 bit (differential)
-
2 (1)
20 (9)
22
17 (7)
17
ADC channels in total(2)
12-bit DAC
2
-
-
Internal ADC/DAC VREF
VREF+ input pin
1.5 V, 1.8 V, 2.048 V, 2.5 V or VREF+ input
Yes
1. With inner matrix balls having 0.65 mm pitch to allow optimized PCB routing for supplies.
18/260
DS12505 Rev 5
STM32MP157C/F
Description
2. In addition, there is also 6 internal channels for temperature, internal voltage reference, VDDCORE, VBAT/4, DAC1 or DAC2
acquisitions.
DS12505 Rev 5
19/260
59
Description
STM32MP157C/F
Figure 1. STM32MP157C/F block diagram
HSI
LSI
@VDD
HSE (XTAL)
PLL1/2/3/4
IC Supplies
2
ETM
CNT (Timer)
@VDD_ANA
T
T
CSI
@VDD_PLL
Cortex-A7 CPU
650/800(1) MHz + MMU +
RCC
PWR
EXTI
5
9
T
T
T
FPU + NEON
T
32K D$
debug TimeStamp
32K I$
GENerator TSGEN
16ext
14b
176
128 bits
T
GIC
DAP
T
(JTAG / SWD)
DCMI
17
Cortex-A7 CPU
(Camera I/F)
650/800(1) MHz + MMU +
SYSRAM 256KB
ROM 128KB
BKPSRAM 4KB
RNG1
DLYBSD3
(SDMMC3 DLY control)
FPU + NEON
T
32K D$
SDMMC3
4b
10
4
T
T
T
T
T
32K I$
OTG
(HS/FS)
CNT (Timer)
ETM
ETH1 GMAC
10/100/1000
T
T
@VDDA
16b
16b
ADC1
ADC2
20
14
HASH1
29
77
CRYP1
GPIOA
GPIOB
GPIOC
GPIOD
GPIOE
GPIOF
GPIOG
GPIOH
GPIOI
GPIOJ
GPIOK
TIM2
16b
16b
16b
16b
16b
16b
16b
16b
16b
16b
8b
16
16
16
16
16
16
16
16
16
16
8
DDRCTRL
DLYBQS
LPDDR2/3
DDR3/3L
(QUADSPI DLY control)
CRC1
8b
QUADSPI (dual)
FMC
13
37
14
14
DLYBSD1
(SDMMC1 DLY control)
16b
8b
DLYBSD2
(SDMMC2 DLY control)
SDMMC1
T
8b
SDMMC2
T
Shader
(533 MHz)
2
2
USBH
GPU
T
(2 x HS Host)
PLLUSB
MDMA
32 Channels
LTDC
24b
8b
31
8
(LCD)
STM
GPIOZ
T
async
16b
Trace port
I2C4 / SMBUS
I2C6 / SMBUS
SPI6
17
3
32b
16b
16b
32b
16b
16b
16b
16b
16b
16b
5
T
T
T
T
T
T
Cortex-M4 CPU 209 MHz
+ MPU + FPU
TIM3
5
AHB2APB
3
D-Bus
I-Bus
TIM4
5
4
TIM5
5
Smartcard
USART1
5
IrDA
TIM6
S-Bus
ETZPC
NVIC
SYSTICK
TIM7
IWDG1
TIM12
TIM13
TIM14
LPTIM1
MDIOS
USART2
USART3
UART4
UART5
UART7
UART8
2
1
1
4
2
5
5
4
4
4
4
BSEC
T
SRAM1 128KB
SRAM2 128KB
OTP Fuses
RTC / AWU
SRAM3/SRAM4 64K/64K
RETSRAM 64KB
HSEM
2
3
2
T
T
TAMP / Backup Regs
LSE (32kHz XTAL)
Smartcard
IrDA
T
T
Smartcard
IrDA
STGENC
IPCC
CRC2
Sys. Timing
STGENR
GENeration
PLLDSI
DSI
6
RNG2
HASH2
CRYP2
USBPHYC
(USB 2 x PHY control)
IWDG2
@VDDA
DDRPHYC
DDRPERFM
VREFBUF
DAC1
DAC2
12b
12b
1
1
AHB2APB
I2C1 / SMBUS
I2C2 / SMBUS
I2C3 / SMBUS
I2C5 / SMBUS
3
3
3
3
1
4
5
5
1
4
DMA1
16b
LPTIM2
LPTIM3
LPTIM4
LPTIM5
SAI4
8 Streams
16b
16b
16b
DMAMUX1
1
DMA2
1
8 Streams
CEC (HDMI-CEC)
SPDIFRX
1
2x2
4ch
Matrix
13
3
SPI2 / I2S2
SPI3 / I2S3
WWDG1
BOOT
pins
SYSCFG
HDP
DTS
(Digital temperature sensor)
AHB2APB
8b
8
16b
16b
16b
16b
16b
TIM1 / PWM
TIM8 / PWM
TIM15
10
10
4
Smartcard
IrDA
@VDD
Voltage Regulators
AHB2APB
USART6
SPI4
5
4
@VDD_ANA
Supply Supervision
SPI5
4
TIM16
3
64 bits
64bits
SPI1 / I2S1
DFSDM1
FDCAN1 (TT)
AXI
AXI master
AHB master
5
TIM17
3
32 bits
32 bits
8ch
AHB
17
2
SAI1
13
8
TrustZone® security protection
32 bits
APB
T
SAI2
Buffer 10KB
FDCAN2
CCU
SAI3
APB2 (104.5 MHz)
8
2
MSv47445V4
1. STM32MP157C: 650 MHz, STM32MP157F: 800 MHz
20/260
DS12505 Rev 5
STM32MP157C/F
Functional overview
3
Functional overview
3.1
Dual-core Arm® Cortex®-A7 subsystem
3.1.1
Features
•
•
•
•
•
•
•
•
•
•
•
•
•
ARMv7-A architecture
32-Kbyte L1 instruction cache for each CPU
32-Kbyte L1 data cache for each CPU
256-Kbyte level2 cache
®
®
Arm + Thumb -2 instruction set
®
®
Arm TrustZone security technology
®
Arm NEON™ Advanced SIMD
DSP and SIMD extensions
VFPv4 floating-point
Hardware virtualization support
Embedded trace module (ETM)
Integrated generic interrupt controller (GIC) with 256 shared peripheral interrupts
Integrated generic timer (CNT)
3.1.2
Overview
The Cortex-A7 processor is a very energy-efficient applications processor designed to
provide rich performance in high-end wearables, and other low-power embedded and
consumer applications. It provides up to 20 % more single thread performance than the
Cortex-A5 and provides similar performance than the Cortex-A9.
The Cortex-A7 incorporates all features of the high-performance Cortex-A15 and Cortex-
™
®
A17 processors, including virtualization support in hardware, NEON , and 128-bit AMBA 4
AXI bus interface.
The Cortex-A7 processor builds on the energy-efficient 8-stage pipeline of the Cortex-A5
processor. It also benefits from an integrated L2 cache designed for low-power, with lower
transaction latencies and improved OS support for cache maintenance. On top of this, there
is improved branch prediction and improved memory system performance, with 64-bit load-
store path, 128-bit AMBA 4 AXI buses and increased TLB size (256 entry, up from 128 entry
for Cortex-A9 and Cortex-A5), increasing performance for large workloads such as web
browsing.
Thumb-2 technology
®
Delivers the peak performance of traditional Arm code while also providing up to a 30 %
reduction in memory requirement for instructions storage.
TrustZone technology
Ensures reliable implementation of security applications ranging from digital rights
management to electronic payment. Broad support from technology and industry partners.
DS12505 Rev 5
21/260
59
Functional overview
NEON
STM32MP157C/F
NEON technology can accelerate multimedia and signal processing algorithms such as
video encode/decode, 2D/3D graphics, gaming, audio and speech processing, image
processing, telephony, and sound synthesis. The Cortex-A7 provides an engine that offers
both the performance and functionality of the Cortex-A7 floating-point unit (FPU) and an
implementation of the NEON advanced SIMD instruction set for further acceleration of
media and signal processing functions. The NEON extends the Cortex-A7 processor FPU to
provide a quad-MAC and additional 64-bit and 128-bit register set supporting a rich set of
SIMD operations over 8-, 16- and 32-bit integer and 32-bit floating-point data quantities.
Hardware virtualization
Highly efficient hardware support for data management and arbitration, whereby multiple
software environments and their applications are able to simultaneously access the system
capabilities. This enables the realization of devices that are robust, with virtual environments
that are well isolated from each other.
Optimized L1 caches
Performance and power optimized L1 caches combine minimal access latency techniques
to maximize performance and minimize power consumption. There is also the option of
cache coherence for enhanced inter-processor communication, or support of a rich SMP
capable OS for simplified multicore software development.
Integrated L2 cache controller
Provides low-latency and high-bandwidth access to cached memory in high-frequency, or to
reduce the power consumption associated with off-chip memory access.
Cortex-A7 floating-point unit (FPU)
The FPU provides high-performance single and double precision floating-point instructions
compatible with the Arm VFPv4 architecture that is software compatible with previous
generations of Arm floating-point coprocessor.
Snoop control unit (SCU)
The SCU is responsible for managing the interconnect, arbitration, communication, cache to
cache and system memory transfers, cache coherence and other capabilities for the
processor.
This system coherence also reduces software complexity involved in maintaining software
coherence within each OS driver.
Generic interrupt controller (GIC)
Implementing the standardized and architected interrupt controller, the GIC provides a rich
and flexible approach to inter-processor communication and the routing and prioritization of
system interrupts.
Supporting up to 288 independent interrupts, under software control, each interrupt can be
distributed across A7 cores, hardware prioritized, and routed between the operating system
and TrustZone software management layer.
22/260
DS12505 Rev 5
STM32MP157C/F
Functional overview
This routing flexibility and the support for virtualization of interrupts into the operating
system, provides one of the key features required to enhance the capabilities of a solution
utilizing a hypervisor.
3.2
Arm® Cortex®-M4 with FPU
®
®
The Arm Cortex -M4 with FPU core is a 32-bit RISC processor that features exceptional
code-efficiency, delivering the high-performance expected from an Arm core in the memory
size usually associated with 8- and 16-bit devices.
The processor supports a set of DSP instructions which allow efficient signal processing and
complex algorithm execution.
Its single precision FPU (floating point unit) speeds up software development by using
metalanguage development tools, while avoiding saturation.
Note:
Cortex-M4 with FPU core is binary compatible with the Cortex-M3 core.
Memory protection unit (MPU)
®
The memory protection unit (MPU) manages the Cortex -M4 access rights and the
attributes of the system resources. It has to be programmed and enabled before use. Its
main purposes are to prevent an untrusted user program to accidentally corrupt data used
by the OS and/or by a privileged task, but also to protect data processes or read-protect
memory regions.
The MPU defines access rules for privileged accesses and user program accesses. It
allows the definition of up to 16 protected regions that can in turn be divided into up to 8
independent subregions, where region address, size, and attributes can be configured. The
protection area ranges from 32 bytes to 4 Gbytes of addressable memory.
When an unauthorized access is performed, a memory management exception is
generated.
3.3
Graphic processing unit (GPU)
The STM32MP157C/F includes a 3D graphics engine (Vivante).
The GPU is a dedicated graphics processing unit accelerating numerous 3D graphics
applications such as graphical user interface (GUI), menu display or animations.
It works together with an optimized software stack design for industry-standard APIs with
®
support for Android™ and Linux embedded development platforms.
DS12505 Rev 5
23/260
59
Functional overview
STM32MP157C/F
Hardware features:
•
•
•
•
•
•
•
•
•
•
•
•
•
•
OpenGL ES 2.0 / 1.1 compliance, including extensions; OpenVG 1.1
IEEE 32-bit floating-point pipeline
Ultra-threaded, unified vertex and fragment (pixel) shaders
Low memory bandwidth at both high and low data rates
Low CPU loading
Up to 12 programmable elements per vertex
Dependent texture operation with high-performance
Alpha blending
Depth and stencil compare
Support for 8 fragment shader simultaneous textures
Support for 4 vertex shader simultaneous textures
Point sampling, bi-linear sampling, tri-linear filtering, and cubic textures
8 k x 8 k texture size and 8 k x 8 k rendering target
4 Vertex DMA streams
API support:
•
•
•
•
OpenGL ES 1.1 and 2.0
OpenVG 1.1
EGL 1.4
OpenGL 2.1
Performance up to:
•
•
26 Mtriangle/s
133 Mpixel/s
24/260
DS12505 Rev 5
STM32MP157C/F
Functional overview
3.4
Memories
3.4.1
External SDRAM
The STM32MP157C/F devices embed a controller for external SDRAM which support the
following devices
•
•
LPDDR2 or LPDDR3, 16- or 32-bit data, up to 1 Gbyte, up to 533 MHz clock.
DDR3 or DDR3L, 16- or 32-bit data, up to 1 Gbyte, up to 533 MHz clock.
3.4.2
Embedded SRAM
All devices feature:
•
•
•
•
•
•
SYSRAM in MPU domain: 256 Kbytes
SRAM1 in MCU domain: 128 Kbytes
SRAM2 in MCU domain: 128 Kbytes
SRAM3 in MCU domain: 64 Kbytes
SRAM4 in MCU domain: 64 Kbytes
RETRAM (retention RAM): 64 Kbytes
The content of this area can be retained in Standby or V
BKPSRAM (backup SRAM): 4 Kbytes
mode.
BAT
•
The content of this area is protected against possible unwanted write accesses, and
can be retained in Standby or V mode.
BAT
BKPSRAM can be defined (in ETZPC) as accessible by secure software only.
DS12505 Rev 5
25/260
59
Functional overview
STM32MP157C/F
3.5
DDR3/DDR3L/LPDDR2/LPDDR3 controller (DDRCTRL)
DDRCTRL combined with DDRPHYC provides a complete memory interface solution for
DDR memory subsystem.
•
•
•
Two 64-bit AMBA 4 AXI4 ports interface (XPI)
AXI clock asynchronous to the controller
Supported standards:
–
–
–
JEDEC DDR3 SDRAM specification, JESD79-3E for DDR3/3L with 32-bit
interface
JEDEC LPDDR2 SDRAM specification, JESD209-2E for LPDDR2 with 32-bit
interface
JEDEC LPDDR3 SDRAM specification, JESD209-3B for LPDDR3 with 32-bit
interface
•
•
•
•
•
Advanced scheduler and SDRAM command generator
Programmable full data width (32-bit) or half data width (16-bit)
Advanced QoS support with 3 traffic class on read and 2 traffic classes on write
Options to avoid starvation of lower priority traffic
Guaranteed coherency for write-after-read (WAR) and read-after-write (RAW) on AXI
ports
•
•
Programmable support for burst length options (4, 8,16)
Write combine to allow multiple writes to the same address to be combined into a
single write
•
•
Single rank configuration
Supports automatic SDRAM power-down entry and exit caused by lack of transaction
arrival for programmable time
•
•
Supports automatic clock stop (LPDDR2/3) entry and exit caused by lack of transaction
arrival
Supports automatic low power mode operation caused by lack of transaction arrival for
programmable time via hardware low power interface
•
•
•
•
•
Programmable paging policy
Supports automatic or under software control self-refresh entry and exit
Support for deep power-down entry and exit under software control (LPDDR2)
Support for explicit SDRAM mode register updates under software control
Flexible address mapper logic to allow application specific mapping of row, column,
bank bits
•
•
User-selectable refresh control options
DDRPERFM associated block to help for performance monitoring and tuning
DDRCTRL and DDRPHYC can be defined (in ETZPC) as accessible by secure software
only.
26/260
DS12505 Rev 5
STM32MP157C/F
Functional overview
3.6
TrustZone address space controller for DDR (TZC)
TZC is used to filter read/write accesses to DDR controller according to TrustZone rights
and according to non-secure master (NSAID) on up to 9 programmable regions.
•
•
•
Configuration is supported by trusted software only
2 filter units working concurrently
9 regions:
–
–
region 0 is always enabled and covers the whole address range.
regions 1 to 8 have programmable base/end address and can be assigned to any
one or both filters.
•
•
•
•
•
•
•
Secure and non-secure access permissions programmed per region
Non-secure accesses are filtered according to NSAID
Regions controlled by same filter must not overlap
Fail modes with error and/or interrupt
Acceptance capability = 256
Gate keeper logic to enable and disable of each filter
Speculative accesses
DS12505 Rev 5
27/260
59
Functional overview
STM32MP157C/F
3.7
Boot modes
At startup, the boot source used by the internal BootROM is selected by the BOOT pin and
OTP bytes.
Table 2. Boot modes
BOOT2 BOOT1 BOOT0
Initial boot mode
Comments
Wait incoming connection on:
0
0
0
UART and USB(1)
– USART2/3/6 and UART4/5/7/8 on default pins
– USB high-speed device(2)
0
0
0
1
1
0
1
1
0
0
1
0
1
0
1
Serial NOR Flash(3)
e•MMC(3)
Serial NOR Flash on QUADSPI(4)
e•MMC on SDMMC2 (default)(4)(5)
NAND Flash(3)
Reserved (NoBoot)
SD card(3)
SLC NAND Flash on FMC
Used to get debug access without boot from Flash memory
SD card on SDMMC1 (default)(4)(5)
Wait incoming connection on:
1
1
1
1
0
1
UART and USB(1)(3)
– USART2/3/6 and UART4/5/7/8 on default pins
– USB high-speed device on OTG_HS_DP/DM pins(2)
Serial NAND Flash(3) Serial NAND Flash on QUADSPI(4)
1. can be disabled by OTP settings.
2. USB requires 24 MHz HSE clock/crystal if OTP is not programmed for different frequency.
3. Boot source can be changed by OTP settings (e.g. initial boot on SD card, then e•MMC with OTP settings).
4. Default pins can be altered by OTP.
5. Alternatively, another SDMMC1 or SDMMC2 interface than this default can be selected by OTP.
28/260
DS12505 Rev 5
STM32MP157C/F
Functional overview
3.8
Power supply management
3.8.1
Power supply scheme
•
•
The V is the main supply for I/Os and internal part kept powered during Standby
mode. Useful voltage range is 1.71 V to 3.6 V (e.g. 1.8 V, 2.5 V, 3.0 V or 3.3 V typ.)
DD
–
V
, V
and V
must be star-connected to V
.
DD
DD_DSI
DD_PLL
DD_ANA
The V
is the main digital voltage and is usually shutdown during Standby mode.
DDCORE
Voltage range during Run mode is 1.18 V to 1.25/1.38 V (1.2/1.34 V typ.), see
Table 13: General operating conditions.
•
•
The VBAT pin can be connected to the external battery (1.2 V < V
< 3.6 V). If no
BAT
external battery is used, it is mandatory to connect this pin to V
.
DD
The VDDA pin is the analog (ADC/DAC/VREF), supply voltage range is 1.71 V to 3.6 V.
DAC can only be used when V is above or equal 1.8 V. Using Internal V
DDA
REF+
requires V
equal to or higher than V
+ 0.3 V.
DDA
REF+
•
The VDDA1V8_REG pin is the output of internal regulator and connected internally to
USB PHY and USB PLL. Internal V regulator is enabled by default and can
DDA1V8_REG
be controlled by software. It is always shut down during Standby mode.
There is specific BYPASS_REG1V8 pin that must be connected either to V or V to
SS
DD
activate or deactivate the voltage regulator. It is mandatory to bypass the 1.8 V
regulator when V is below 2.25 V (BYPASS_REG1V8 = V . In that case,
DD
DD)
VDDA1V8_REG pin must be connected to V (if below 1.98 V) or to a dedicated
DD
1.65 V - 1.98 V supply (1.8 V typ.).
•
•
V
is the analog DSI supply. Voltage range is 1.65 V to 1.98 V. (1.8 V typ.)
DDA1V8_DSI
Should be connected to V
.
DDA1V8_REG
VDDA1V1_REG pin is the output of internal regulator connected internally to USB PHY.
Internal V regulator is enabled by default and can be controlled by
DDA1V1_REG
software. It is always shut down during Standby mode.
•
•
•
VDDA1V2_DSI_REG pin is the output of internal regulator and connected internally to
DSI PLL.
V
V
is the analog DSI PHY supply and should be connected to
.
DDA1V2_DSI_PHY
DDA1V2_DSI_REG
V
and V
are respectively the USB high-speed and full-speed
DD3V3_USBFS
DD3V3_USBHS
PHY supply. Voltage range is 3.07 V to 3.6 V. V
is used to supply
DD3V3_USBFS
OTG_VBUS and ID pins. So, V
must be supplied as well when USB high-
DD3V3_USBFS
speed OTG device is used. If not used, must be connected to V
DD.
Caution:
V
must not be present unless V
is present, otherwise permanent
DDA1V8_REG
DD3V3_USBHS
STM32MP157C/F damage could occur. Must be ensured by PMIC ranking order or with
external component in case of discrete component power supply implementation.
•
V
–
–
–
is the DDR IO supply.
DDQ_DDR
Voltage range is 1.425 V to 1.575 V for interfacing DDR3 memories (1.5 V typ.).
Voltage range is 1.283 V to 1.45 V for interfacing DDR3L memories (1.35 V typ.).
Voltage range is 1.14 V to 1.3 V for interfacing LPDDR2 or LPDDR3 memories
(1.2 V typ.).
DS12505 Rev 5
29/260
59
Functional overview
STM32MP157C/F
During power-up and power-down phases, the following power sequence requirements
must be respected:
• When V is below 1 V, other power supplies (V
, V
, V
,
DD
DDCORE
DDA
DDA1V8_REG
V
V
, V
+ 300 mV.
, V
, V
) must remain below
DDA1V8_DSI
DDA1V1_REG
DD3V3_USBHS/FS
DDQ_DDR
DD
• When V is above 1 V, all power supplies are independent.
DD
During the power-down phase, V can temporarily become lower than other supplies only
DD
if the energy provided to the STM32MP157C/F device remains below 1 mJ; this allows
external decoupling capacitors to be discharged with different time constants during the
power- down transient phase.
Figure 2. Power-up/down sequence
V
3.6
(1)
VDDX
VDD
VBOR0
1
0.3
Power-on
Operating mode
VDDX < VDD + 300 mV
Power-down
time
Invalid supply area
VDDX independent from VDD
MSv47490V1
1. VDDX refers to any power supply among VDDCORE, VDDA, VDDA1V8_REG, VDDA1V8_DSI, VDDA1V1_REG
VDD3V3_USBHS/FS, VDDQ_DDR
,
.
30/260
DS12505 Rev 5
STM32MP157C/F
Functional overview
3.8.2
Power supply supervisor
The devices have an integrated power-on reset (POR)/ power-down reset (PDR) circuitry
coupled with a Brownout reset (BOR) circuitry:
•
Power-on reset (POR)
The POR supervisor monitors V power supply and compares it to a fixed threshold.
DD
The devices remain in reset mode when V is below this threshold,
DD
•
Power-down reset (PDR)
The PDR supervisor monitors V power supply. A reset is generated when V drops
DD
DD
below a fixed threshold.
The PDR supervisor can be enabled/disabled through PDR_ON pin.
Brownout reset (BOR)
•
•
•
The BOR supervisor monitors V power supply. Three BOR thresholds (from 2.1 to
DD
2.7 V) can be configured through option bytes. A reset is generated when V drops
below this threshold.
DD
Power-on reset V
(POR_VDDCORE)
DDCORE
The POR_VDDCORE supervisor monitors V
power supply and compares it to
DDCORE
a fixed threshold. The V
this threshold,
domain remain in reset mode when V
is below
DDCORE
DDCORE
Power-down reset V
(PDR_VDDCORE)
DDCORE
The PDR_VDDCORE supervisor monitors V
power supply. A V
DDCORE
domain
DDCORE
reset is generated when V
drops below a fixed threshold.
DDCORE
The PDR_VDDCORE supervisor can be enabled/disabled through PDR_ON_CORE
pin.
DS12505 Rev 5
31/260
59
Functional overview
STM32MP157C/F
3.9
Low-power strategy
There are several ways to reduce power consumption on STM32MP157C/F:
•
Decrease dynamic power consumption by slowing down the CPU clocks and/or the
bus matrix clocks and/or controlling individual peripheral clocks.
•
Save power consumption when the CPU is IDLE, by selecting among the available low-
power mode according to the user application needs. This allows the best compromise
between short startup time, low-power consumption, as well as available wakeup
sources, to be achieved.
The CPUs feature several low-power modes:
•
•
•
•
•
•
CSleep (CPU clock stopped)
CStop (CPU sub-system clock stopped)
Stop (bus matrix clocks stalled, the oscillators can be stopped)
CStandby (MPU sub-system clock stopped and wakeup via reset)
Standby (system powered down)
LP-Stop and LPLV-Stop (bus matrix clocks stalled, the oscillators can be stopped, low-
power mode signaled to external regulator)
CSleep and CStop low-power modes are entered by the CPU when executing the WFI (wait
for interrupt) or WFE (Wait for Event) instructions, or when the SLEEPONEXIT bit of the
Cortex-M4 core is set after returning from an interrupt service routine.
If part of the domain is not in low-power mode, the domain remains in the current mode.
Finally the system can enter Stop or Standby when all EXTI wakeup sources are cleared
and the CPUs are in CStop or CStandby mode.
Table 3. System versus domain power mode
System power mode
MPU
MCU
CRun or CSleep
CStop or CStandby
CRun or CSleep
CRun or CSleep
CStop
Run mode
Stop mode
LP-Stop mode
LPLV-Stop mode
CStop or CStandby
CStop
CStandby or (CStop and
MPU PDDS = 1 and MPU CSTBYDIS = 1)
CStop and
MCU PDDS = 1
Standby mode
32/260
DS12505 Rev 5
STM32MP157C/F
Functional overview
3.10
Reset and clock controller (RCC)
The clock and reset controller manages the generation of all the clocks, as well as the clock
gating and the control of the system and peripheral resets. It provides a high flexibility in the
choice of clock sources and allows application of clock ratios to improve the power
consumption. In addition, on some communication peripherals that are capable to work with
two different clock domains (either a bus interface clock or a kernel peripheral clock), the
system frequency can be changed without modifying the baudrate.
3.10.1
Clock management
The devices embed four internal oscillators, two oscillators with external crystal or
resonator, three internal oscillators with fast startup time and four PLLs.
The RCC receives the following clock source inputs:
•
•
Internal oscillators:
–
–
–
64 MHz HSI clock (1% accuracy)
4 MHz CSI clock
32 kHz LSI clock
External oscillators:
–
–
8-48 MHz HSE clock
32.768 kHz LSE clock
The RCC provides four PLLs:
•
•
The PLL1 is dedicated to the MPU clocking
The PLL2 provides:
–
–
–
The clocks for the AXI-SS (including APB4, APB5, AHB5 and AHB6 bridges)
The clocks for the DDR interface
The clocks for the GPU
•
•
The PLL3 provides:
–
The clocks for the MCU, and its bus matrix (including the APB1, APB2, APB3,
AHB1, AHB2, AHB3 and AHB4)
–
The kernel clocks for peripherals
The PLL4 is dedicated to the generation of the kernel clocks for various peripherals
The system starts on the HSI clock. The user application can then select the clock
configuration.
DS12505 Rev 5
33/260
59
Functional overview
STM32MP157C/F
3.10.2
System reset sources
The power-on reset initializes all registers while the system reset reinitializes the system
except for the debug, part of the RCC and power controller status registers, as well as the
backup power domain.
An application reset is generated from one of the following sources:
–
–
–
–
–
–
–
–
a reset from NRST pad
a reset from POR and PDR signal (generally called power-on reset)
a reset from BOR (generally called brownout)
a reset from the independent watchdogs 1
a reset from the independent watchdogs 2
a software reset from the Cortex-M4 (MCU)
a software reset from the Cortex-A7 (MPU)
a failure on HSE, when the clock security system feature is activated
A system reset is generated from one of the following sources:
–
–
–
An application reset,
A reset from POR_VDDCORE signal,
Every time the system exits from Standby.
3.11
Hardware semaphore (HSEM)
The HW semaphore block provides 64 (32-bit) register-based semaphores.
The semaphores can be used to ensure synchronization between different processes
running on a core and between different cores. The HSEM provides a non blocking
mechanism to lock semaphores in an atomic way. The following functions are provided:
•
Locking a semaphore can be done in 2 ways:
–
2-step lock: by writing CoreID and ProcessID to the semaphore, followed by a
read check.
–
1-step lock: by reading the CoreID from the semaphore.
•
•
•
Interrupt generation when a semaphore is freed.
Each semaphore may generated an interrupt on one of the interrupt lines.
Semaphore clear protection.
A semaphore is only cleared when CoreID and ProcessID matches.
Global semaphore clear per CoreID.
–
–
3.12
Inter-processor communication controller (IPCC)
The inter-processor communication controller (IPCC) is used for communicating data
between two processors.
The IPCC block provides a non blocking signaling mechanism to post and retrieve
communication data in an atomic way. It provides the signaling for four channels:
•
•
two channels in the direction from processor 1 to processor 2
two channels in the opposite direction.
34/260
DS12505 Rev 5
STM32MP157C/F
Functional overview
It is then possible to have two different communication types in each direction.
The IPCC communication data must be located in a common memory, which is not part of
the IPCC block.
3.12.1
IPCC main features
•
Status signaling for the four channels
Channel occupied/free flag, also used as lock
Two interrupt lines per processor
–
•
–
–
One for RX channel occupied (communication data posted by sending processor)
One for TX channel free (communication data retrieved by receiving processor)
•
•
Interrupt masking per channel
–
–
Channel occupied mask
Channel free mask
Two channel operation modes
–
–
Simplex (each channel has its own communication data memory location)
Half duplex (a single channel in associated to a bidirectional communication data
information memory location)
3.13
General-purpose input/outputs (GPIOs)
Each of the GPIO pins can be configured by software as output (push-pull or open-drain,
with or without pull-up or pull-down), as input (with or without pull-up or pull-down) or as
peripheral alternate function. Most of the GPIO pins are shared with digital or analog
alternate functions. All GPIOs are high-current-capable and have speed selection to better
manage internal noise, power consumption and electromagnetic emission.
After reset, all GPIOs are in analog mode to reduce power consumption.
The I/O configuration can be locked if needed by following a specific sequence in order to
avoid spurious writing to the I/Os registers.
Additionally, GPIO pins on port Z can be individually set as secure, which would mean that
software accesses to these GPIOs and associated peripherals defined as secure are
restricted to secure software running on Cortex-A7.
3.14
TrustZone protection controller (ETZPC)
ETZPC is used to configure TrustZone security of bus masters and slaves with
programmable-security attributes (securable resources) such as:
•
•
On-chip SYSRAM with programmable secure region size
AHB and APB peripherals to be made secure
Notice that by default, SYSRAM and peripheral are set to secure access only, so, not
accessible by non-secure masters such as Cortex-M4 or DMA1/DMA2.
ETZPC can also allocate peripherals and SRAM to be accessible only by the Cortex-M4
and/or DMA1/DMA2. This ensures the safe execution of the Cortex-M4 firmware, protected
from other masters (e.g. Cortex-A7) unwanted accesses.
DS12505 Rev 5
35/260
59
Functional overview
STM32MP157C/F
3.15
Bus-interconnect matrix
The devices feature an AXI bus matrix, one main AHB bus matrix and bus bridges that allow
bus masters to be interconnected with bus slaves (see Figure 3, the dots represent the
enabled master/slave connections).
36/260
DS12505 Rev 5
STM32MP157C/F
Functional overview
Figure 3. STM32MP157C/F bus matrix
M10
M0
M1 M2
M3
M4
M5
M6
M7
M8
M9
MPU_AXI_DDR1
MPU_AXI_DDR2
MPU_AHB6
S0
S1
DDRCTRL 533 MHz
S2
AHB bridge to AHB6
To MCU interconnect
FMC/NAND
MPU_AHB_MCU
MPU_AXI_FMC
S3
S4
MPU_AXI_QUADSPI
MPU_AXI_SYSRAM
MPU_AXI_ROM
MPU_AXI_STM
MPU_AHB5
S5
QUADSPI
S6
SYSRAM 256 KB
ROM 128 KB
S7
S8
STM
S9
AHB bridge to AHB5
APB bridge to APB5
APB bridge to DBG APB
MPU_APB5
S10
S11
MPU_DBG_APB
Default
slave
AXIMC
Masters access S0 XOR S1 layer
AXI 64 synchronous master port
AXI 64 synchronous slave port
AXI 64 asynchronous master port
AXI 64 asynchronous slave port
AHB 32 synchronous master port
AHB 32 synchronous slave port
AHB 32 asynchronous master port
AHB 32 asynchronous slave port
NIC-400 AXI 64 bits 266 MHz - 11 masters / 12 slaves
M0
M1 M2
M3 M4
M5
M6
M7 M8 M9
MCU_AHB_MEM0
S0
S1
S2
SRAM1
SRAM2
SRAM3
MCU_AHB_MEM1
MCU_AHB_MEM2
MCU_AHB_MEM3
MCU_AHB3
S8
S3
SRAM4
Bridge to AHB3
MCU_AHB2
S4
S5
S6
S7
Bridge to AHB2
To MPU interconnect
RetentionRAM
MCU_AHB_MPU
MCU_AHB_RET
MCU_AHB4
Bridge to AHB4
Interconnect AHB 32 bits 209 MHz - 10 masters / 9 slaves
MSv47453V2
DS12505 Rev 5
37/260
59
Functional overview
STM32MP157C/F
3.16
DMA controllers
The devices features three DMA modules to unload CPU activity:
• A master direct memory access (MDMA)
The MDMA is a high-speed DMA controller, which is in charge of all types of memory
transfers (peripheral to memory, memory to memory, memory to peripheral), without
any CPU action. It features a master AXI interface.
The MDMA is located in MPU domain. It is able to interface with the other DMA
controllers located in MCU domain to extend the standard DMA capabilities, or can
manage peripheral DMA requests directly.
Each of the 32 channels can perform block transfers, repeated block transfers and
linked list transfers.
The MDMA can be set to make secure transfers to secured memories.
•
Two DMA controllers (DMA1, DMA2), located in MCU domain. Each controller is a
dual-port AHB, for a total of 16 DMA channels to perform FIFO-based block transfers.
The DMAMUX is an extension of the DMA1 and DMA2 controllers. It multiplexes and routes
the DMA peripheral requests to the DMA1 or DMA2 controllers, with a high flexibility,
maximizing the number of DMA requests that run concurrently, as well as generating DMA
requests from peripheral output trigger or DMA event.
3.17
Nested vectored interrupt controller (NVIC)
The devices embed a nested vectored interrupt controller able to manage 16 priority levels,
®
and handle up to 150 maskable interrupt channels plus the 16 interrupt lines of the Cortex -
M4 with FPU core.
•
•
•
•
•
•
•
Closely coupled NVIC gives low-latency interrupt processing
Interrupt entry vector table address passed directly to the core
Allows early processing of interrupts
Processing of late arriving, higher-priority interrupts
Support tail chaining
Processor context automatically saved
Interrupt entry restored on interrupt exit with no instruction overhead
This hardware block provides flexible interrupt management features with minimum interrupt
latency.
3.18
Extended interrupt and event controller (EXTI)
The extended interrupt and event controller (EXTI) manages individual CPU and system
wakeup through configurable and direct event inputs. It provides wake-up requests to the
power control, and generates an interrupt request to the CPUs NVIC or GIC and events to
the CPUs event inputs. For each CPU an additional event generation block (EVG) is needed
to generate the CPU event signal.
The EXTI wake-up requests allow the system to be woken up from Stop mode, and the
CPUs to be woken up from CStop and CStandby modes.
The interrupt request and event request generation can also be used in Run mode.
38/260
DS12505 Rev 5
STM32MP157C/F
Functional overview
The block also includes the EXTI IOport selection.
Each interrupt or event can be set as secure in order to restrict access to secure software
only.
3.19
3.20
Cyclic redundancy check calculation unit (CRC1, CRC2)
The CRC (cyclic redundancy check) calculation unit is used to get a CRC code using a
programmable polynomial.
Among other applications, CRC-based techniques are used to verify data transmission or
storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of
verifying the Flash memory integrity. The CRC calculation unit helps computing a signature
of the software during runtime, to be compared with a reference signature generated at link-
time and stored at a given memory location.
Flexible memory controller (FMC)
The FMC controller main features are the following:
•
Interface with static-memory mapped devices including:
–
–
–
NOR Flash memory
Static or pseudo-static random access memory (SRAM, PSRAM)
NAND Flash memory with 4-bit/8-bit BCH hardware ECC
•
•
•
•
8-,16-bit data bus width
Independent chip select control for each memory bank
Independent configuration for each memory bank
Write FIFO
3.21
Dual Quad-SPI memory interface (QUADSPI)
The QUADSPI is a specialized communication interface targeting single, dual or quad SPI
Flash memories. It can operate in any of the three following modes:
•
•
indirect mode: all the operations are performed using the QUADSPI registers
status polling mode: the external Flash memory status register is periodically read and
an interrupt can be generated in case of flag setting
•
memory-mapped mode: the external Flash memory is mapped to the address space
and is seen by the system as if it was an internal memory
Both throughput and capacity can be increased two-fold using dual-flash mode, where two
Quad-SPI Flash memories are accessed simultaneously.
QUADSPI is coupled with a delay block (DLYBQS) allowing the support of external data
frequency above 100 MHz.
DS12505 Rev 5
39/260
59
Functional overview
STM32MP157C/F
3.22
Analog-to-digital converters (ADCs)
The STM32MP157C/F devices embed two analog-to-digital converters, which resolution
can be configured to 16, 14, 12, 10 or 8 bits. Each ADC shares up to 20 external channels,
performing conversions in the single-shot or scan mode. In scan mode, automatic
conversion is performed on a selected group of analog inputs.
Additional logic functions embedded in the ADC interface allow:
•
•
simultaneous ADC1/ADC2 conversion
interleaved ADC1/ADC2 conversion.
The ADC can be served by the DMA controller, thus allowing the automatic transfer of ADC
converted values to a destination location without any software action.
In addition, an analog watchdog feature can accurately monitor the converted voltage of
one, some or all selected channels. An interrupt is generated when the converted voltage is
outside the programmed thresholds.
In order to synchronize A/D conversion and timers, the ADCs can be triggered by any of
TIM1, TIM2, TIM3, TIM4, TIM6, TIM8, TIM15, LPTIM1, LPTIM2 and LPTIM3 timers.
3.23
Temperature sensor
The STM32MP157C/F devices embed a temperature sensor that generates a voltage (V
)
TS
that varies linearly with the temperature. This temperature sensor is internally connected to
ADC2_INP12. It can measure the device ambient temperature ranging from –40 to +125 °C
with a precision of ±2%.
The temperature sensor has a good linearity, but it has to be calibrated to obtain a good
overall accuracy of the temperature measurement. As the temperature sensor offset varies
from chip to chip due to process variation, the uncalibrated internal temperature sensor is
suitable for applications that detect temperature changes only. To improve the accuracy of
the temperature sensor measurement, each device is individually factory-calibrated by ST.
The temperature sensor factory calibration data are stored by ST in the OTP area, which is
accessible in read-only mode.
3.24
Digital temperature sensor (DTS)
The device embeds a frequency output temperature sensor. This block counts the
frequency based on the LSE or PCLK to provide the temperature information.
Following functions can be supported:
•
•
Interrupt generation by temperature threshold.
Wakeup signal generation by temperature threshold.
3.25
VBAT operation
The V
power domain contains the RTC, the backup registers, the retention RAM and the
BAT
backup SRAM.
40/260
DS12505 Rev 5
STM32MP157C/F
Functional overview
In order to optimize battery duration, this power domain is supplied by V when available
DD
or by the voltage applied on VBAT pin (when V supply is not present). V
power is
DD
BAT
switched when the PDR detects that V has dropped below the PDR level.
DD
The voltage on the VBAT pin could be provided by an external battery, a supercapacitor or
directly by V . In the later case, VBAT mode is not functional.
DD
V
operation is activated when V is not present.
DD
BAT
The V
pin supplies the RTC, the backup registers, the retention RAM and the backup
BAT
SRAM.
None of these events: external interrupts, TAMP event, or RTC alarm/events are able to
directly restore the V supply and force the STM32MP157C/F device out of the V
Note:
DD
BAT
operation. Nevertheless, TAMP events and RTC alarm/events can be used to generate a
signal to an external circuitry (typically a PMIC) that can restore the STM32MP157C/F V
supply.
DD
When PDR_ON pin is connected to V (internal reset OFF), the V
functionality is no
BAT
SS
more available and VBAT pin must be connected to V
.
DD
3.26
Digital-to-analog converters (DAC1, DAC2)
The two 12-bit buffered DAC channels can be used to convert two digital signals into two
analog voltage signal outputs.
This dual digital interface supports the following features:
•
•
•
•
•
•
•
•
•
•
•
Two DAC converters: one for each output channel
8-bit or 12-bit monotonic output
Left or right data alignment in 12-bit mode
Synchronized update capability
Noise-wave generation
Triangular-wave generation
Sample and hold mode to reduce the power consumption
Dual DAC channel independent or simultaneous conversions
DMA capability for each channel including DMA underrun error detection
External triggers for conversion
input voltage reference V
or internal VREFBUF reference.
REF+
The DAC channels are triggered through the timer update outputs that are also connected
to different DMA streams.
DS12505 Rev 5
41/260
59
Functional overview
STM32MP157C/F
3.27
Voltage reference buffer (VREFBUF)
The STM32MP157C/F devices embed a voltage reference buffer which can be used as
voltage reference for ADC, DACs and also as voltage reference for external components
through the VREF+ pin.
The internal voltage reference buffer supports four voltages:
•
•
•
•
1.5 V
1.8 V
2.048 V
2.5 V
An external voltage reference can be provided through the VREF+ pin when the internal
voltage reference buffer is off.
Figure 4. Voltage reference buffer
VREFBUF
VDDA DAC, ADC
Bandgap
+
-
VREF+
Low frequency
cut-off capacitor
100 nF
MSv40197V1
3.28
Digital filter for sigma delta modulators (DFSDM1)
The device embeds one DFSDM with support for 6 digital filters modules and 8 external
input serial channels (transceivers) or alternately 8 internal parallel inputs.
The DFSDM peripheral is dedicated to interface external Σ∆ modulators to
STM32MP157C/F and perform digital filtering of the received data streams. Σ∆ modulators
are used to convert analog signals into digital serial streams that constitute the inputs of the
DFSDM. The DFSDM can also interface PDM (pulse density modulation) microphones and
perform the PDM to PCM conversion and filtering (hardware accelerated). The DFSDM
features optional parallel data stream inputs from internal ADC peripherals or
STM32MP157C/F memory (through DMA/CPU transfers into DFSDM).
The DFSDM transceivers support several serial interface formats (to support various Σ∆
modulators). DFSDM digital filter modules perform digital processing according user-defined
filter parameters with up to 24-bit final ADC resolution.
42/260
DS12505 Rev 5
STM32MP157C/F
Functional overview
The DFSDM peripheral supports:
•
8 multiplexed input digital serial channels:
–
–
–
–
–
configurable SPI interface to connect various SD modulator(s)
configurable Manchester coded 1-wire interface support
PDM (pulse density modulation) microphone input support
maximum input clock frequency up to 20 MHz (10 MHz for Manchester coding)
clock output for SD modulator(s): 0…20 MHz
•
•
Alternative inputs from 8 internal digital parallel channels (up to 16-bit input resolution):
internal sources: ADC data or memory data streams (DMA)
–
6 digital filter modules with adjustable digital signal processing:
x
–
–
Sinc filter: filter order/type (1…5), oversampling ratio (1…1024)
integrator: oversampling ratio (1…256)
•
•
•
•
Up to 24-bit output data resolution, signed output data format
Automatic data offset correction (offset stored in register by user)
Continuous or single conversion
Start-of-conversion triggered by:
–
–
–
–
software trigger
internal timers
external events
start-of-conversion synchronously with first digital filter module (DFSDM0)
•
Analog watchdog feature:
–
–
low value and high value data threshold registers
x
dedicated configurable Sinc digital filter (order = 1…3, oversampling ratio =
1…32)
–
–
input from final output data or from selected input digital serial channels
continuous monitoring independently from standard conversion
•
Short circuit detector to detect saturated analog input values (bottom and top range):
–
–
up to 8-bit counter to detect 1…256 consecutive 0’s or 1’s on serial data stream
monitoring continuously each input serial channel
•
•
Break signal generation on analog watchdog event or on short circuit detector event
Extremes detector:
–
–
storage of minimum and maximum values of final conversion data
refreshed by software
•
•
DMA capability to read the final conversion data
Interrupts: end of conversion, overrun, analog watchdog, short circuit, input serial
channel clock absence
•
“Regular” or “injected” conversions:
–
“regular” conversions can be requested at any time or even in continuous mode
without having any impact on the timing of “injected” conversions
–
“injected” conversions for precise timing and with high conversion priority
DS12505 Rev 5
43/260
59
Functional overview
STM32MP157C/F
3.29
Digital camera interface (DCMI)
The devices embed a camera interface that can connect with camera modules and CMOS
sensors through an 8-bit to 14-bit parallel interface, to receive video data. The camera
interface can achieve a data transfer rate up to 140 Mbyte/s using a 80 MHz pixel clock and
14-bit of data. It features:
•
•
•
Programmable polarity for the input pixel clock and synchronization signals
Parallel data communication can be 8-, 10-, 12- or 14-bit
Supports 8-bit progressive video monochrome or raw Bayer format, YC C 4:2:2
b
r
progressive video, RGB 565 progressive video or compressed data (like JPEG)
Supports continuous mode or snapshot (a single frame) mode
Capability to automatically crop the image
•
•
3.30
LCD-TFT display controller (LTDC)
The LCD-TFT display controller provides a 24-bit parallel digital RGB (Red, Green, Blue)
and delivers all signals to interface directly to a broad range of LCD and TFT panels up to
WXGA (1366 × 768) @60 fps or up to Full HD (1920 × 1080) @30 fps resolution with the
following features:
•
•
•
•
•
•
•
•
•
Up to 90 MHz pixel clock
2 display layers with dedicated FIFO
Color look-up table (CLUT) up to 256 colors (256×24-bit) per layer
Up to 8 input color formats selectable per layer
Flexible blending between two layers using alpha value (per pixel or constant)
Flexible programmable parameters for each layer
Color keying (transparency color)
Up to 4 programmable interrupt events
AXI master interface
44/260
DS12505 Rev 5
STM32MP157C/F
Functional overview
3.31
Display serial interface (DSI)
The display serial interface (DSI) is part of a group of communication protocols defined by
®
®
the MIPI Alliance. The MIPI DSI host controller is a digital core that implements all
®
protocol functions defined in the MIPI DSI specification.
®
It provides an interface between the system and the MIPI D-PHY, allowing the
communication with a DSI-compliant display.
®
•
•
•
•
•
•
•
•
•
•
•
Compliant with MIPI Alliance standards
®
Interface with MIPI D-PHY
®
Supports all commands defined in the MIPI Alliance specification for DCS
Supports up to two D-PHY data lanes at 1 Gbps
Bidirectional communication and escape mode support through data lane 0
Supports non-continuous clock in D-PHY clock lane for additional power saving
Supports ultra-low-power mode with PLL disabled
ECC and checksum capabilities
Support for end of transmission packet (EoTp)
Fault recovery schemes
Configurable selection of system interfaces:
–
–
–
–
AMBA APB for control and optional support for generic and DCS commands
Video mode interface through LTDC
Adapted command mode interface through LTDC
Independently programmable virtual channel ID in video mode, adapted command
mode and APB slave
•
Video mode interfaces features:
–
–
–
LTDC interface color coding mappings into 16, 18 and 24-bit interface
Programmable polarity of all LTDC interface signals
Maximum resolution is limited by available DSI physical link bandwidth
•
•
Adapted interface features:
–
Support for sending large amounts of data through the memory_write_start (WMS)
and memory_write_continue (WMC) DCS commands
–
LTDC interface color coding mappings into 16, 18 and 24-bit interface
Video mode pattern generator
3.32
True random number generator (RNG1, RNG2)
All the devices embed two RNG that deliver 32-bit random numbers generated by an
integrated analog circuit.
RNG1 can be defined (in ETZPC) as accessible by secure software only.
DS12505 Rev 5
45/260
59
Functional overview
STM32MP157C/F
3.33
Cryptographic and hash processors (CRYP1, CRYP2 and
HASH1, HASH2)
The devices embed two cryptographic processors that support the advanced cryptographic
algorithms usually required to ensure confidentiality, authentication, data integrity and non-
repudiation when exchanging messages with a peer:
•
Encryption/decryption
–
DES/TDES (data encryption standard/triple data encryption standard): ECB
(electronic codebook) and CBC (cipher block chaining) chaining algorithms, 64-,
128- or 192-bit key
–
AES (advanced encryption standard): ECB, CBC, GCM, CCM, and CTR (counter
mode) chaining algorithms, 128, 192 or 256-bit key
•
Universal HASH
–
–
–
SHA-1, SHA224 and SHA256 (secure HASH algorithms)
MD5
HMAC
The cryptographic accelerator supports DMA request generation.
CRYP1 and HASH1 can be defined (in ETZPC) as accessible by secure software only.
3.34
3.35
Boot and security and OTP control (BSEC)
The BSEC (boot and security and OTP control) is intended to control an OTP (one time
programmable) fuse box, used for embedded non-volatile storage for device configuration
and security parameters. Some part of BSEC should be configured as accessible by secure
software only.
Timers and watchdogs
The devices include two advanced-control timers, ten general-purpose timers, two basic
timers, five low-power timers, three watchdogs, a SysTick timer in Cortex-M4 and 4 system
timers in each Cortex-A7.
All timer counters can be frozen in debug mode.
Table 4 compares the features of the advanced-control, general-purpose, basic and low-
power timers.
46/260
DS12505 Rev 5
STM32MP157C/F
Functional overview
Table 4. Timer feature comparison
Max
Max
DMA
request
Capture/ Comple-
compare mentary
Timer
Timer
type
Counter Counter Prescaler
interface timer
clock
(MHz)
resolution
type
factor
clock
generation channels output
(MHz)(1)
Up,
down,
up/down and 65536
Any integer
between 1
Advanced TIM1,
16-bit
32-bit
16-bit
16-bit
16-bit
16-bit
16-bit
16-bit
Yes
Yes
Yes
No
6
4
4
2
1
2
1
0
4
104.5
104.5
104.5
104.5
104.5
104.5
104.5
104.5
209
209
209
209
209
209
209
209
-control
TIM8
Up,
down,
up/down and 65536
Any integer
between 1
TIM2,
TIM5
No
No
No
No
1
Up,
down,
up/down and 65536
Any integer
between 1
TIM3,
TIM4
Any integer
between 1
and 65536
TIM12
Up
Up
Up
Up
Up
General
purpose
Any integer
between 1
and 65536
TIM13,
TIM14
No
Any integer
between 1
and 65536
TIM15
Yes
Yes
Yes
Any integer
between 1
and 65536
TIM16,
TIM17
1
Any integer
between 1
and 65536
TIM6,
TIM7
Basic
No
LPTIM1,
LPTIM2,
LPTIM3,
LPTIM4,
LPTIM5
1, 2, 4, 8,
16, 32, 64,
128
Low-
power
16-bit
Up
No
1(2)
No
104.5
209
1. The maximum timer clock is up to 209 MHz depending on TIMGxPRE bit in the RCC.
2. No capture channel on LPTIM.
DS12505 Rev 5
47/260
59
Functional overview
STM32MP157C/F
3.35.1
Advanced-control timers (TIM1, TIM8)
The advanced-control timers (TIM1, TIM8) can be seen as three-phase PWM generators
multiplexed on 6 channels. They have complementary PWM outputs with programmable
inserted dead times. They can also be considered as complete general-purpose timers.
Their 4 independent channels can be used for:
•
•
•
•
Input capture
Output compare
PWM generation (edge- or center-aligned modes)
One-pulse mode output
If configured as standard 16-bit timers, they have the same features as the general-purpose
timers. If configured as 16-bit PWM generators, they have full modulation capability (0-
100%).
The advanced-control timer can work together with the general-purpose timers via the timer
link feature for synchronization or event chaining.
TIM1 and TIM8 support independent DMA request generation.
3.35.2
General-purpose timers (TIM2, TIM3, TIM4, TIM5, TIM12, TIM13,
TIM14, TIM15, TIM16, TIM17)
There are ten synchronizable general-purpose timers embedded in the STM32MP157C/F
devices (see Table 4 for differences).
•
TIM2, TIM3, TIM4, TIM5
The devices include 4 full-featured general-purpose timers: TIM2, TIM3, TIM4 and
TIM5. TIM2 and TIM5 are based on a 32-bit auto-reload up/downcounter and a 16-bit
prescaler while TIM3 and TIM4 are based on a 16-bit auto-reload up/downcounter and
a 16-bit prescaler. All timers feature 4 independent channels for input capture/output
compare, PWM or one-pulse mode output. This gives up to 16 input capture/output
compare/PWMs on the largest packages.
TIM2, TIM3, TIM4 and TIM5 general-purpose timers can work together, or with the
other general-purpose timers and the advanced-control timers TIM1 and TIM8 via the
timer link feature for synchronization or event chaining.
Any of these general-purpose timers can be used to generate PWM outputs.
TIM2, TIM3, TIM4, TIM5 all have independent DMA request generation. They are
capable of handling quadrature (incremental) encoder signals and the digital outputs
from 1 to 4 hall-effect sensors.
•
TIM12, TIM13, TIM14, TIM15, TIM16, TIM17
These timers are based on a 16-bit auto-reload upcounter and a 16-bit prescaler.
TIM13, TIM14, TIM16 and TIM17 feature one independent channel, whereas TIM12
and TIM15 have two independent channels for input capture/output compare, PWM or
one-pulse mode output. They can be synchronized with the TIM2, TIM3, TIM4, TIM5
full-featured general-purpose timers or used as simple timebases.
48/260
DS12505 Rev 5
STM32MP157C/F
Functional overview
3.35.3
Basic timers TIM6 and TIM7
These timers are mainly used for DAC trigger and waveform generation. They can also be
used as a generic 16-bit time base.
TIM6 and TIM7 support independent DMA request generation.
3.35.4
Low-power timer (LPTIM1, LPTIM2, LPTIM3, LPTIM4, LPTIM5)
The low-power timer has an independent clock and is running also in Stop mode if it is
clocked by LSE, LSI or an external clock. It is able to wakeup the device from Stop mode.
These low-power timer supports the following features:
•
•
•
•
•
•
•
•
16-bit up counter with 16-bit autoreload register
16-bit compare register
Configurable output: pulse, PWM
Continuous / one-shot mode
Selectable software / hardware input trigger
Selectable clock source:
Internal clock source: LSE, LSI, HSI or APB clock
External clock source over LPTIM input (working even with no internal clock source
running, used by the pulse counter application)
•
•
Programmable digital glitch filter
Encoder mode
3.35.5
Independent watchdog (IWDG1, IWDG2)
The independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. It is
clocked from an independent 32 kHz internal RC(LSI) and as it operates independently from
the main clock, it can operate in Stop and Standby modes. It can be used either as a
watchdog to reset the device when a problem occurs, or as a free-running timer for
application timeout management. It is hardware- or software-configurable through the option
bytes.
IWDG1 can be defined (in ETZPC) as accessible by secure software only.
3.35.6
3.35.7
System window watchdog (WWDG1)
The window watchdog is based on a 7-bit downcounter that can be set as free-running. It
can be used as a watchdog to reset the device when a problem occurs. It is clocked from
the APB clock. It has an early warning interrupt capability and the counter can be frozen in
debug mode.
SysTick timer (Cortex-M4)
This timer is embedded inside Cortex-M4 core and dedicated to real-time operating
systems, but can also be used as a standard downcounter. It features:
•
•
•
•
A 24-bit downcounter
Autoreload capability
Maskable system interrupt generation when the counter reaches 0
Programmable clock source.
DS12505 Rev 5
49/260
59
Functional overview
STM32MP157C/F
3.35.8
Generic timers (Cortex-A7 CNT)
Cortex-A7 generic timers embedded inside Cortex-A7 are fed by value from system timing
generation (STGEN).
The Cortex-A7 processor provides a set of four timers for each processor:
•
Physical timer for use in secure and non-secure modes. The registers for the physical
timer are banked to provide secure and non-secure copies.
•
•
Virtual timer for use in non-secure modes.
Physical timer for use in hypervisor mode.
Generic timers are not memory mapped peripherals, they are accessible only by specific
Cortex-A7 coprocessor instructions (cp15).
3.36
System timer generation (STGEN)
The system timing generation (STGEN) generates a time count value that provides a
consistent view of time for all Cortex-A7 generic timers.
The system timing generation has the following key features:
•
•
•
64-bit wide to avoid roll-over issues.
Starts from zero or a programmable value.
A control APB interface (STGENC) enables the timer to be saved and restored across
powerdown events.
•
•
Read-only APB interface (STGENR) enables the timer value to be read by non-secure
software and debug tools.
The timer value incrementing can be stopped during system debug.
STGENC can be defined (in ETZPC) as accessible by secure software only.
3.37
Real-time clock (RTC)
The RTC provides an automatic wakeup to manage all low-power modes.
The real-time clock (RTC) is an independent BCD timer/counter. The RTC provides a time-
of-day clock/calendar with programmable alarm interrupts.
The RTC includes also a periodic programmable wakeup flag with interrupt capability.
Two 32-bit registers contain the seconds, minutes, hours (12- or 24-hour format), day (day
of week), date (day of month), month, and year, expressed in binary coded decimal format
(BCD). The sub-seconds value is also available in binary format.
Compensations for 28-, 29- (leap year), 30-, and 31-day months are performed
automatically. Daylight saving time compensation can also be performed.
Additional 32-bit registers contain the programmable alarm subseconds, seconds, minutes,
hours, day, and date.
A digital calibration feature is available to compensate for any deviation in crystal oscillator
accuracy.
After backup domain reset, all RTC registers are protected against possible parasitic write
accesses.
50/260
DS12505 Rev 5
STM32MP157C/F
Functional overview
As long as the supply voltage remains in the operating range, the RTC never stops,
regardless of the device status (Run mode, Low-power mode or under reset).
The RTC unit main features are the following:
•
Calendar with subseconds, seconds, minutes, hours (12 or 24 format), day (day of
week), date (day of month), month, and year.
•
•
Daylight saving compensation programmable by software.
Programmable alarm with interrupt function. The alarm can be triggered by any
combination of the calendar fields.
•
•
Automatic wakeup unit generating a periodic flag that triggers an automatic wakeup
interrupt.
Reference clock detection: a more precise second source clock (50 or 60 Hz) can be
used to enhance the calendar precision.
•
•
Accurate synchronization with an external clock using the subsecond shift feature.
Digital calibration circuit (periodic counter correction): 0.95 ppm accuracy, obtained in a
calibration window of several seconds
•
•
Timestamp function for event saving
Maskable interrupts/events:
–
–
–
–
Alarm A
Alarm B
Wakeup interrupt
Timestamp
•
TrustZone support:
–
–
RTC fully securable
Alarm A, alarm B, wakeup timer and timestamp individual secure or non-secure
configuration
3.38
Tamper and backup registers (TAMP)
32 x 32-bit backup registers are retained in all low-power modes and also in VBAT mode.
They can be used to store sensitive data as their content is protected by an tamper
detection circuit. 3 tamper pins and 5 internal tampers are available for anti-tamper
detection. The external tamper pins can be configured for edge detection, edge and level,
level detection with filtering, or active tamper which increases the security level by auto
checking that the tamper pins are not externally opened or shorted.
DS12505 Rev 5
51/260
59
Functional overview
STM32MP157C/F
TAMP main features
•
32 backup registers:
the backup registers (TAMP_BKPxR) are implemented in the RTC domain that
remains powered-on by VBAT when the V power is switched off.
–
DD
•
3 external tamper detection events.
–
–
Each external event can be configured to be active or passive.
External passive tampers with configurable filter and internal pull-up.
•
•
•
•
5 internal tamper events.
Any tamper detection can generate a RTC timestamp event.
Any tamper detection erases the backup registers.
TrustZone support:
–
–
Tamper secure or non-secure configuration.
Backup registers configuration in 3 configurable-size areas:
1 read/write secure area.
1 write secure/read non-secure area.
1 read/write non-secure area.
•
Monotonic counter.
52/260
DS12505 Rev 5
STM32MP157C/F
Functional overview
3.39
Inter-integrated circuit interface (I2C1, I2C2, I2C3, I2C4, I2C5,
I2C6)
2
The STM32MP157C/F embeds six I C interfaces.
2
The I C bus interface handles communications between the STM32MP157C/F and the
2
2
serial I C bus. It controls all I C bus-specific sequencing, protocol, arbitration and timing.
The I2C peripheral supports:
•
I2C-bus specification and user manual rev. 5 compatibility:
–
–
–
–
–
–
–
Slave and master modes, multimaster capability
Standard-mode (Sm), with a bitrate up to 100 kbit/s
Fast-mode (Fm), with a bitrate up to 400 kbit/s
Fast-mode Plus (Fm+), with a bitrate up to 1 Mbit/s and 20 mA output drive I/Os
7-bit and 10-bit addressing mode, multiple 7-bit slave addresses
Programmable setup and hold times
Optional clock stretching
•
System management bus (SMBus) specification rev 2.0 compatibility:
–
Hardware PEC (packet error checking) generation and verification with ACK
control
–
–
Address resolution protocol (ARP) support
SMBus alert
•
•
Power system management protocol (PMBus™) specification rev 1.1 compatibility
Independent clock: a choice of independent clock sources allowing the I2C
communication speed to be independent from the PCLK reprogramming.
•
•
•
Wakeup from Stop mode on address match
Programmable analog and digital noise filters
1-byte buffer with DMA capability
I2C4 and I2C6 can be defined (in ETZPC) as accessible by secure software only.
3.40
Universal synchronous asynchronous receiver transmitter
(USART1, USART2, USART3, USART6 and UART4, UART5,
UART7, UART8)
The STM32MP157C/F devices have four embedded universal synchronous receiver
transmitters (USART1, USART2, USART3 and USART6) and four universal asynchronous
receiver transmitters (UART4, UART5, UART7 and UART8). Refer to Table 5 for a summary
of USARTx and UARTx features.
These interfaces provide asynchronous communication, IrDA SIR ENDEC support,
multiprocessor communication mode, single-wire half-duplex communication mode and
have LIN master/slave capability. They provide hardware management of the CTS and RTS
signals, and RS485 Driver Enable. They are able to communicate at speeds of up to
10 Mbit/s.
USART1, USART2, USART3 and USART6 also provide Smartcard mode (ISO 7816
compliant) and SPI-like communication capability.
DS12505 Rev 5
53/260
59
Functional overview
STM32MP157C/F
All USART have a clock domain independent from the CPU clock, allowing the USARTx to
wake up the STM32MP157C/F from Stop mode using baudrates up to 200 Kbaud.The wake
up events from Stop mode are programmable and can be:
•
•
•
Start bit detection
Any received data frame
A specific programmed data frame
All USART interfaces can be served by the DMA controller.
Table 5. USART features
USART modes/features(1)
USART1/2/3/6
UART4/5/7/8
Hardware flow control for modem
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
-
Continuous communication using DMA
Multiprocessor communication
Synchronous mode (master/slave)
Smartcard mode
-
Single-wire half-duplex communication
IrDA SIR ENDEC block
X
X
X
X
X
X
X
X
LIN mode
Dual clock domain and wakeup from low power mode
Receiver timeout interrupt
Modbus communication
Auto baud rate detection
Driver Enable
USART data length
7, 8 and 9 bits
1. X = supported.
USART1 can be defined (in ETZPC) as accessible by secure software only.
3.41
Serial peripheral interface (SPI1, SPI2, SPI3, SPI4, SPI5,
SPI6)– inter- integrated sound interfaces (I2S1, I2S2, I2S3)
The devices feature up to six SPIs (SPI2S1, SPI2S2, SPI2S3, SPI4, SPI5 and SPI6) that
allow communication at up to 50 Mbit/s in master and slave modes, in half-duplex, full-
duplex and simplex modes. The 3-bit prescaler gives 8 master mode frequencies and the
frame is configurable from 4 to 16 bits. All SPI interfaces support NSS pulse mode, TI mode,
hardware CRC calculation and 8x 8-bit embedded Rx and Tx FIFOs with DMA capability.
2
Three standard I S interfaces (I2S1, I2S2, I2S3, multiplexed with SPI1, SPI2 and SPI3) are
available. They can be operated in master or slave mode, in full-duplex and half-duplex
communication modes, and can be configured to operate with a 16-/32-bit resolution as an
input or output channel. Audio sampling frequencies from 8 kHz up to 192 kHz are
2
supported. When either or both of the I S interfaces is/are configured in master mode, the
master clock can be output to the external DAC/CODEC at 256 times the sampling
54/260
DS12505 Rev 5
STM32MP157C/F
Functional overview
2
frequency. All I S interfaces support 16x 8-bit embedded Rx and Tx FIFOs with DMA
capability.
SPI6 can be defined (in ETZPC) as accessible by secure software only.
3.42
Serial audio interfaces (SAI1, SAI2, SAI3, SAI4)
The devices embed 4 SAIs that allow the design of many stereo or mono audio protocols
such as I2S, LSB or MSB-justified, PCM/DSP, TDM or AC’97. An SPDIF output is available
when the audio block is configured as a transmitter. To bring this level of flexibility and
reconfigurability, the SAI contains two independent audio sub-blocks. Each block has it own
clock generator and I/O line controller.
Audio sampling frequencies up to 192 kHz are supported.
In addition, up to 8 microphones can be supported thanks to an embedded PDM interface.
The SAI can work in master or slave configuration. The audio sub-blocks can be either
receiver or transmitter and can work synchronously or asynchronously (with respect to the
other one). The SAI can be connected with other SAIs to work synchronously.
3.43
SPDIF receiver interface (SPDIFRX)
The SPDIFRX peripheral is designed to receive an S/PDIF flow compliant with IEC-60958
and IEC-61937. These standards support simple stereo streams up to high sample rate,
and compressed multi-channel surround sound, such as those defined by Dolby or DTS (up
to 5.1).
The main SPDIFRX features are the following:
•
•
•
•
•
•
•
•
•
Up to 4 inputs available
Automatic symbol rate detection
Maximum symbol rate: 12.288 MHz
Stereo stream from 32 to 192 kHz supported
Supports audio IEC-60958 and IEC-61937, consumer applications
Parity bit management
Communication using DMA for audio samples
Communication using DMA for control and user channel information
Interrupt capabilities
The SPDIFRX receiver provides all the necessary features to detect the symbol rate, and
decode the incoming data stream. The user can select the wanted SPDIF input, and when a
valid signal is available, the SPDIFRX re-samples the incoming signal, decode the
Manchester stream, recognize frames, sub-frames and blocks elements. It delivers to the
CPU decoded data, and associated status flags.
The SPDIFRX also offers a signal named spdif_frame_sync, which toggles at the S/PDIF
sub-frame rate that is used to compute the exact sample rate for clock drift algorithms.
DS12505 Rev 5
55/260
59
Functional overview
STM32MP157C/F
3.44
Management data input/output (MDIOS)
The devices embed a MDIO slave interface. It includes the following features:
•
32 MDIO register addresses, each of which is managed using separate input and
output data registers:
–
–
32 x 16-bit firmware read/write, MDIO read-only output data registers
32 x 16-bit firmware read-only, MDIO write-only input data registers
•
•
Configurable slave (port) address
Independently maskable interrupts/events:
–
–
–
MDIO register write
MDIO register read
MDIO protocol error
•
Able to operate in and wake up from Stop mode
3.45
Secure digital input/output MultiMediaCard interface
(SDMMC1, SDMMC2, SDMMC3)
Three secure digital input/output MultiMediaCard interfaces (SDMMC) provide an interface
between the AHB bus and SD memory cards, SDIO cards and MMC devices.
The SDMMC features include the following:
•
Full compliance with MultiMediaCard System Specification Version 4.51.
Card support for three different databus modes: 1-bit (default), 4-bit and 8-bit.
•
•
Full compatibility with previous versions of MultiMediaCards (backward compatibility).
Full compliance with SD memory card specifications version 4.1.
(SDR104 SDMMC_CK speed limited to maximum allowed I/O speed, SPI mode and
UHS-II mode not supported).
•
Full compliance with SDIO card specification version 4.0.
Card support for two different databus modes: 1-bit (default) and 4-bit.
(SDR104 SDMMC_CK speed limited to maximum allowed I/O speed, SPI mode and
UHS-II mode not supported).
•
Data transfer up to 208 Mbyte/s for the 8-bit mode.
(depending maximum allowed I/O speed).
•
•
Data and command output enable signals to control external bidirectional drivers.
The SDMMC host interface embeds a dedicated DMA controller allowing high-speed
transfers between the interface and the SRAM.
•
IDMA linked list support
Each SDMMC is coupled with a delay block (DLYBSD) allowing support of an external data
frequency above 100 MHz.
3.46
Controller area network (FDCAN1, FDCAN2)
The controller area network (CAN) subsystem consists of two CAN modules, a shared
message RAM memory and a clock calibration unit.
56/260
DS12505 Rev 5
STM32MP157C/F
Functional overview
Both CAN modules (FDCAN1 and FDCAN2) are compliant with ISO 11898-1 (CAN protocol
specification version 2.0 part A, B) and CAN FD protocol specification version 1.0.
FDCAN1 supports time triggered CAN (TTCAN) specified in ISO 11898-4, including event
synchronized time-triggered communication, global system time, and clock drift
compensation. The FDCAN1 contains additional registers, specific to the time triggered
feature. The CAN FD option can be used together with event-triggered and time-triggered
CAN communication.
A 10 Kbyte message RAM memory implements filters, receive FIFOs, receive buffers,
transmit event FIFOs, transmit buffers (and triggers for TTCAN). This message RAM is
shared between the two FDCAN1 and FDCAN2 modules.
The common clock calibration unit is optional. It can be used to generate a calibrated clock
for both FDCAN1 and FDCAN2 from the HSI internal RC oscillator and the PLL, by
evaluating CAN messages received by the FDCAN1.
3.47
3.48
Universal serial bus high-speed host (USBH)
The devices embed one USB high-speed host (up to 480 Mbit/s) with two physical ports.
USBH supports both low, full-speed (OHCI) as well as high-speed (EHCI) operations
independently on each port. It integrates two transceivers which can be used for either low-
speed (1.2 Mbit/s), full-speed (12 Mbit/s) or high-speed operation (480 Mbit/s), the second
high-speed transceiver is shared with OTG high-speed.
The USB HS is compliant with the USB 2.0 specification. The USB HS controllers require
dedicated clocks that are generated by a PLL inside the USB high-speed PHY.
USB on-the-go high-speed (OTG)
The devices embed one USB OTG high-speed (up to 480 Mbit/s) device/host/OTG
peripheral. OTG supports both full-speed and high-speed operations. It integrates the
transceivers for full-speed operation (12 Mbit/s) and high-speed operation (480 Mbit/s)
shared with USB Host second port.
The USB OTG HS is compliant with the USB 2.0 specification and with the OTG 2.0
specification. It has software-configurable endpoint setting and supports suspend/resume.
The USB OTG controllers require a dedicated 48 MHz clock that is generated by a PLL
inside RCC or inside the USB high-speed PHY.
DS12505 Rev 5
57/260
59
Functional overview
STM32MP157C/F
The main features are:
•
•
•
•
•
•
•
•
•
•
•
Combined Rx and Tx FIFO size of 4 Kbyte with dynamic FIFO sizing
Supports the session request protocol (SRP) and host negotiation protocol (HNP)
8 bidirectional endpoints
16 host channels with periodic OUT support
Software configurable to OTG1.3 and OTG2.0 modes of operation
USB 2.0 LPM (link power management) support
Battery charging specification revision 1.2 support
Internal FS or HS OTG PHY support
Internal USB DMA
HNP/SNP/IP inside (no need for any external resistor)
For OTG/Host modes, a power switch is needed in case bus-powered devices are
connected
3.49
Gigabit Ethernet MAC interface (ETH1)
The devices provide an IEEE-802.3-2002-compliant gigabit media access controller
(GMAC) for Ethernet LAN communications through an industry-standard medium-
independent interface (MII), a reduced medium-independent interface (RMII), a gigabit
medium-independent interface (GMII) or a reduced gigabit medium-independent interface
(RGMII).
The STM32MP157C/F requires an external physical interface device (PHY) to connect to
the physical LAN bus (twisted-pair, fiber, etc.). The PHY is connected to the device port
using 17 signals for MII, 7 signals for RMII, 26 signals for GMII or 13 signals for RGMII, and
can be clocked using the 25 MHz (MII, RMII, GMII, RGMII) or 125 MHz (GMII, RGMII) from
the STM32MP157C/F or from the PHY.
The devices include the following features:
•
Operation modes and PHY interfaces
–
–
–
10, 100, and 1000 Mbps data transfer rates
Support of both full-duplex and half-duplex operations
MII, RMII, GMII and RGMII PHY interfaces
•
Multiple queues support and audio video bridging (AVB) management
–
–
–
–
Separate channels or queues for AV data transfer in 100 and 1000 Mbps modes
Two queues on the Rx paths and two queues on the Tx path for AV traffic
One DMA for Rx path and two DMA for Tx path (one per transmit channels)
Several arbitration algorithms between queues: weighted round robin (WRR),
strict priority (SP), weighted strict priority (WSP), IEEE 802.1-Qav specified credit-
based shaper (CBS) algorithm for Transmit channels
•
Processing control
Multi-layer Packet filtering: MAC filtering on source (SA) and destination (DA)
address with perfect and hash filter, VLAN tag-based filtering with perfect and
–
58/260
DS12505 Rev 5
STM32MP157C/F
Functional overview
hash filter, Layer 3 filtering on IP source (SA) or destination (DA) address, Layer 4
filtering on source (SP) or destination (DP) port
–
Double VLAN processing: insertion of up to two VLAN tags in transmit path, tag
filtering in receive path
–
–
IEEE 1588-2008/PTPv2 support
Supports network statistics with RMON/MIB counters (RFC2819/RFC2665)
•
•
Hardware offload processing
–
–
Preamble and start-of-frame data (SFD) insertion or deletion
Integrity Checksum offload engine for IP header and TCP/UDP/ICMP payload:
transmit checksum calculation and insertion, receive checksum calculation and
comparison
–
–
Automatic ARP request response with the device's MAC address
TCP Segmentation: Automatic split of large transmit TCP packet into multiple
small packets
Low-power mode
–
–
Energy efficient Ethernet (Standard IEEE 802.3az-2010)
Remote wakeup packet and AMD Magic Packet™ detection
3.50
High-definition multimedia interface (HDMI) – Consumer
electronics control (CEC)
The device embeds a HDMI-CEC controller that provides hardware support for the
consumer electronics control (CEC) protocol (supplement 1 to the HDMI standard).
This protocol provides high-level control functions between all audiovisual products in an
environment. It is specified to operate at low speeds with minimum processing and memory
overhead. It has a clock domain independent from the CPU clock, allowing the HDMI-CEC
controller to wake up the STM32MP157C/F from Stop mode on data reception.
3.51
Debug infrastructure
The devices offer a comprehensive set of debug and trace features to support software
development and system integration.
•
•
•
•
•
•
•
•
•
Breakpoint debugging
Code execution tracing
Software instrumentation
JTAG debug port
Serial-wire debug port
Trigger input and output
Serial-wire trace port
Trace port
®
Arm CoreSight™ debug and trace components
The debug can be controlled via a JTAG/serial-wire debug access port, using industry
standard debugging tools.
A trace port allows data to be captured for logging and analysis.
DS12505 Rev 5
59/260
59
Pinouts, pin description and alternate functions
STM32MP157C/F
4
Pinouts, pin description and alternate functions
Figure 5. STM32MP157C/FADxx TFBGA257 pinout
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
JTDO-
TRACES
WO
DSI_
CKP
DSI_
D1P
JTCK-
SWCLK
DDR_
DQ0
DDR_
DQ1
VSS
PD1
PB7
PC6
VSS
PD3
PC8
PE4
VSS
A
DSI_
D0P
DSI_
CKN
DSI_
D1N
NJT
RST
DDR_
DQ3
DDR_
DQ7
DDR_
DDR_
PG15
PE12
PG12
PD8
PE6
PE0
PD7
PD4
PA15
PD5
PG6
PD0
PB4
PA9
PE5
PB3
PA8
PC9
PB9
PC10
PC7
JTDI
B
C
D
E
F
DQS0N
DQS0P
DSI_
D0N
VDD_
DSI
JTMS-
SWDIO
DDR_
RESETN
DDR_
DQM0
DDR_
DQ2
DDR_
DQ6
PB15
PC11
VSS
DDR_
DQ4
DDR_
DQ5
PE11
NRST
PE15
PE13
VSS
VSS
1
2
3
4
5
6
7
8
9
VDD1V2_
DSI_REG
PE1
PD10
PE14
PD15
VSS
PE3
PB14
PD2
VSS
DDR_ZQ
DDR_A7
1A
1B
1C
1D
1E
1F
1G
1H
1J
DDR_A13 DDR_A9
PC15-
OSC32_
OUT
DDR_A2
VSS
VSS
DDR_A3
VDD
CORE
VDD
CORE
VDDA
1V8_DSI
VDD1V2_
DSI_PHY
VDDQ_
DDR
PD6
PC12
VSS
PC14-
OSC32_
IN
DDR_
BA0
VSS
PC13
BOOT0
DDR_A0
G
H
J
VDD
CORE
VDD
CORE
DDR_
DTO1
PD9
VSS
VSS
VSS
DDR_A5
PH0-
OSC_IN
DDR_
BA2
DDR_
ODT
BOOT2
VDD
CORE
VDD
CORE
VDD
DDR_
DTO0
VDDQ_
DDR
VBAT
PD14
VDDA
VSSA
PA5
VSS
VSS
PH1-
OSC_
OUT
CORE
NRST_
CORE
DDR_
CSN
DDR_
WEN
DDR_
CASN
PDR_ON
_CORE
VDD
CORE
VDD
CORE
VDD
CORE
DDR_
RASN
DDR_
CLKN
PWR_LP
PA14
BOOT1
PDR_ON
VREF+
PA0
VDD
VSS
VDD
VDD
VSS
VDD
VSS
VSS
VSS
VSS
K
L
DDR_
CLKP
PA13
PWR_ON
PA3
DDR_A15
VDD
CORE
VDD
DDR_
ATO
VDDQ_
DDR
VDDA
VSS
VSS
VDD
VSS
PE9
VSS
CORE
DDR_A10 DDR_A12 DDR_A1
M
N
P
R
T
VDD
CORE
VDD
CORE
VSS
VSS
DDR_A6
VSS
PE2
VSS
DDR_A14 DDR_A11
VDDA
1V8_REG
VDD3V3_
USB
VDDQ_
DDR
VSS
VSS
VSS
DDR_
CKE
DDR_
BA1
PC2
PC3
DDR_
VSS
PG14
PC1
PG13
PA2
DDR_A4
DDR_A8
VDDA
1V1_REG
USB_
RREF
DQ8
PA4
PB13
VSS
PF10
VSS
DDR_
DQ13
DDR_
DQ10
PA1
PB1
PC5
VSS
BYPASS
_REG1V8
DDR_
DQ14
DDR_
DQS1N
DDR_
DQ9
PB0
PB11
PB12
PA6
PC0
PB8
PB10
PG11
PG10
PE7
PD11
PF8
VSS
PF6
PE8
PD13
PB2
PD12
PA11
PA12
PA10
U
V
W
USB_
DP2
USB_
DP1
OTG_
VBUS
DDR_
DQ15
DDR_
DQM1
DDR_
DQS1P
PC4
PB5
VSS
PG8
PF9
PG7
PE10
USB_
DM2
USB_
DM1
DDR_
VREF
DDR_
DQ12
DDR_
DQ11
PA7
PF11
PF7
PG9
PB6
VSS
VSS
MSv47440V2
The above figure shows the package top view.
60/260
DS12505 Rev 5
STM32MP157C/F
Pinouts, pin description and alternate functions
Figure 6. STM32MP157C/FABxx LFBGA354 pinout
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
VDD1V2_
DSI_PHY
DDR_
DQ0
DDR_
DQ1
VSS
PG15
PD0
PD1
PE3
PG6
PB3
PB15
PC7
PC9
PC11
VDD_DSI DSI_D0N DSI_CKN DSI_D1N
VSS
A
B
C
D
E
F
VDD
1V2_DSI
_REG
VDDA
DDR_
DQ3
DDR_
DQ7
DDR_
DQS0N
PE1
PE11
VSS
VSS
PE13
PE12
VSS
PD8
PE6
VSS
PD7
PE0
VSS
VSS
PB7
PD10
VSS
VSS
VSS
VSS
PD3
PD4
VSS
PE5
PA15
PD5
PA8
PA9
VSS
VSS
PB4
PB14
PB9
PD2
PC12
PC6
PE4
PC8
DSI_D0P DSI_CKP DSI_D1P
1V8_DSI
DDR_
DQM0
DDR_
DQS0P
VSS_DSI VSS_DSI VSS_DSI VSS_DSI VSS_DSI
VSS
JTDO-
JTMS-
JTCK-
SWCLK
DDR_
DQ5
DDR_
DQ2
DDR_
DQ6
PE14
PD6
PC10
NJTRST
VSS
JTDI
TRACE
SWO
SWDIO
VDD
CORE
VDD
CORE
VDD
CORE
VDD
CORE
VDDQ_
DDR
DDR_
DQ4
PE15
PG12
PD15
VSS
VSS
VSS
DDR_A7
VDD
CORE
VDD
CORE
VDD
CORE
VDD
CORE
VDD
CORE
VSS_
PLL2
VDDQ_
DDR
PD14
PD9
VSS
VSS
VSS
VSS
DDR_A13 DDR_ZQ
DDR_A3
VDD
CORE
VDD
CORE
VDD
CORE
VDD
CORE
VDD_
PLL2
VDDQ_
DDR
DDR_
RESETN
DDR_
BA0
VSS
VSS
VSS
VSS
VSS
VSS
VSS
DDR_A9
DDR_A5
DDR_A2
DDR_A0
G
H
J
PC14-
OSC32_
IN
PC15-
OSC32_
OUT
VDD
CORE
VDD
CORE
VDD
CORE
VDD
CORE
VDD
CORE
VDDQ_
DDR
DDR_
ODT
VBAT
VSS
VSS
VSS
VSS
VSS
VSS
VSS
NRST_
CORE
VDD
CORE
VDD
CORE
VDD
CORE
VDD
CORE
VDDQ_
DDR
DDR_
BA2
DDR_
WEN
DDR_
CSN
DDR_
DTO1
NRST
BOOT0
VSS_PLL VDD_PLL
VSS
VDD
VSS
VDD
VSS
VDD
VSS
PA7
VSS
VSS
VSS
VSS
VDD
CORE
VDD
CORE
VDD
CORE
VDDQ_
DDR
DDR_
CASN
DDR_
DTO0
DDR_
CLKN
VSS
PC13
BOOT1
VSS
VDD
VSS
VSS
VDD
VSS
VDD
VSS
VDD
PC0
PG8
PG10
PE9
VSS
VSS
VSS
VSS
K
L
VDD_
ANA
VSS_
ANA
VDD
CORE
VDD
CORE
VDD
CORE
VDDQ_
DDR
DDR_
RASN
DDR_
CLKP
PWR_ON
BOOT2
VSS
VDD
VSS
VDD
VSS
PB5
VSS
PD11
PF7
VSS
VSS
VSS
DDR_A15 DDR_A12
PH1-
OSC_
OUT
PH0-
OSC_IN
VDD
CORE
VDD
CORE
VDDQ_
DDR
VREF-
VREF+
PA3
VDDA
VSSA
PA5
VSS
VDD
VSS
VDD
PB13
PF10
PF6
VSS
VSS
VSS
DDR_A1 DDR_A11 DDR_A10
M
N
P
R
T
PDR_ON
_CORE
VDD
CORE
VDD
CORE
VDDQ_
DDR
DDR_
BA1
DDR_
ATO
PDR_ON
PA13
VSS
VDD
VSSA
VSSA
PA6
VSS
VDD
VSS
PE7
PF8
VSS
VSS
DDR_A6
DDR_A14
VDD
CORE
VDDQ_
DDR
DDR_
DQ8
DDR_
CKE
PWR_LP
PA14
PE2
VSS
VDD
PE8
VSS
VSS
DDR_A4
DDR_A8
VDD
VDDQ_
DDR
DDR_
DQ10
PA0
PA4
VSS
PB6
VSS
PG9
VSS
PA10
PA12
CORE
BYPASS
_REG1V8
DDR_
DQ9
DDR_
DQ13
DDR_
DQS1N
PC2
PC3
VSS
PA1
PB2
VSS_
USBHS
VSS_
USBHS
OTG_
VBUS
DDR_
DQM1
DDR_
DQS1P
PG14
PB11
VSS
PG13
PC1
VSS
PF11
PB12
PB10
VSS
PG11
PB8
PD12
PD13
VSS
U
V
W
VDDA
1V8_REG
VSS_
USBHS
USB_
DM2
USB_
DP1
VSS_
USBHS
USB_
RREF
DDR_
DQ14
DDR_
DQ11
PB1
PC5
PC4
PE10
PG7
PA11
VDDA
1V1_REG
VDD3V3_
USBHS
USB_
DP2
USB_
DM1
VDD3V3_
USBFS
DDR_
VREF
DDR_
DQ15
DDR_
DQ12
PA2
PB0
PF9
VSS
MSv47439V2
The above figure shows the package top view.
DS12505 Rev 5
61/260
122
Pinouts, pin description and alternate functions
STM32MP157C/F
Figure 7. STM32MP157C/FACxx TFBGA361 pinout
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23
JTDO-
DSI_
CKN
DSI_
D1N
DDR_
DQ20
DDR_
DQ23
VSS
PH5
PE13
PE11
PF1
PD5
PA9
PG6
PB9
PE6
PD7
PB3
PC7
PE5
PB7
PA8
PF2
TRACE
SWO
JTDI
VSS
A
B
DSI_
D0N
DSI_
CKP
DSI_
D1P
VDD_
DSI
NJ
TRST
JTCK-
SWCLK
DDR_
DQ19
DDR_
DQ16
DDR_
DQS2N
PH15
PI0
PH12
PH10
PD6
PI2
PH4
PH14
PE15
PI1
PE12
PH11
VSS
PI4
PD10
PH9
PH8
PD4
PE14
PE0
PG15
VSS
PF5
PD0
PE1
PF0
PD1
PE3
PF4
PB15
VSS
PD2
PB4
PC6
VDD1
VDD1
VDDA1
V8_DSI
DSI_
D0P
VSS_
DSI
JTMS-
SWDIO
DDR_
DQS2P
DDR_
DQM2
PB14
PC12
V2_DSI V2_DSI
PA15
PE4
VSS
C
D
E
_PHY
_REG
DDR_
RESET
N
DDR_
DQ22
DDR_
DQ17
DDR_
DQ18
PH13
PI3
PD3
PC10
PC11
PC9
PC8
DDR_
A7
DDR_
DQ3
DDR_
DQ0
DDR_
DQ21
DDR_
A13
DDR_
DQ1
PI7
PI5
PI6
VSS
F
1
2
3
VSS
4
5
VSS
6
7
VSS
8
9
VDD
VDD
VDD
VDDQ_
DDR
1A
1B
1C
1D
1E
1F
1G
1H
1J
DDR_
A9
DDR_
DQ7
DDR_
DQS0P DQS0N
DDR_
CORE
CORE
CORE
PZ1
PZ6
PZ4
PZ5
PD15
PZ0
PZ3
PI9
G
H
J
DDR_
A5
DDR_
DQ2
DDR_
DQ6
DDR_
DQM0
VDD
CORE
VDD
CORE
VDD
CORE
VDDQ_
DDR
VDDQ_
DDR
VSS
PZ7
VSS
VSS
VSS
VSS
DDR_
A2
DDR_
DQ4
DDR_
DQ5
PZ2
PG12
PI8
VDD
CORE
VDD
CORE
VDD
CORE
VDDQ_
DDR
VSS
VSS
VSS
VSS
VSS
DDR_
DTO0
DDR_
A3
DDR_
ZQ
PD9
PC13
PD8
PD14
NRST
VSS
K
VDD
CORE
VDD
CORE
VDD
CORE
VDD
CORE
VDDQ_
DDR
VSS
VSS
VSS
VSS
PC15-
PC14-
DDR_
A0
DDR_
TO1
DDR_
ODT
DDR_
BA0
OSC32 OSC32
L
_OUT
_IN
VDD
CORE
VDDCO
RE
VDD
CORE
VDDQ_
DDR
NRST_
CORE
DDR_
WEN
DDR_
BA2
DDR_
CSN
VSS
VSS
VDD
VSS
VDD
VSS
VSS
VSS
VSS
BOOT2
M
N
P
PWR_
LP
DDR_
CASN
DDR_
RASN
DDR_
CLKP
DDR_
CLKN
BOOT0
PA13
BOOT1
PI11
VDD
CORE
VDD
CORE
VDDQ_
DDR
VBAT
VSS
VSS
VDD
VSS
VDD
VSS
VSS
PH1-
OSC_
OUT
PH0-
OSC_IN
DDR_
A15
DDR_
A1
DDR_
A12
VSS
VSS
VSS_
ANA
VDD_
ANA
VDD
CORE
VDDQ_
DDR
VSS
VDD
VSS
VSS
VSS
PWR_
ON
PDR_
ON
DDR_
A11
DDR_
A14
DDR_
A10
VREF+
PG3
R
T
VDD
CORE
VDDQ_
DDR
PDR_
ON_
CORE
VDDA
VSSA
VDD
VSS
VDD
VSS
DDR_
CKE
DDR_
DQ8
DDR_
DQ10
DDR_
DQ13
PI10
PF3
PA14
PA3
DDR_
BA1
DDR_
DQ9
DDR_
DQS1P DQS1N
DDR_
ANA0
PA5
ANA1
PA4
VDDQ_
DDR
U
V
VSS
DDR_
A4
DDR_
DQM1
PG2
PC3
PC2
PG13
PG4
PG0
VSS
DDR_
A6
DDR_
DQ11
DDR_
DQ14
DDR_
DQ12
PG1
PE2
VSS
PB10
PH3
PA0
PH7
W
Y
DDR_
ATO
DDR_
A8
DDR_
DQ15
DDR_
DQ25
DDR_
DQ24
PF15
PA1
PF13
VSS
PG5
PC1
PB0
PG11
PB1
PC5
PC4
PB5
VSS
PA7
PA6
PF12
PF11
PB13
PB8
PH6
PF10
VSS
PF7
PG9
PB6
PE10
PB2
PA10
PD12
PA11
VDD
3V3_
VDD
3V3_
USBFS
VSS_
USBHS
DDR_
DQM3
DDR_
DQ31
DDR_
DQ30
PG14
PB11
VSS
PE9
PG8
PE7
PG10
PF8
PF6
PF9
PD13
PA12
VSS
AA
AB
AC
USBHS
BYPAS
VDD
VDD
A1V1_
REG
USB_
DM2
USB_
DM1
USB_
RREF
DDR_
DQ27
DDR_
DQ26
DDR_
DQS3P DQS3N
DDR_
PH2
PC0
S_REG A1V8_
1V8
REG
USB_
DP2
USB_
DP1
OTG_
VBUS
DDR_
VREF
DDR_
DQ29
DDR_
VSS
PA2
PF14
PB12
PD11
PE8
PG7
DQ28
MSv47430V3
The above figure shows the package top view.
62/260
DS12505 Rev 5
STM32MP157C/F
Pinouts, pin description and alternate functions
Figure 8. STM32MP157C/FAAxx LFBGA448 pinout
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22
VDD1
VDD_
DSI
DSI_
D0N
DSI_
CKN
DSI_
D1N
DDR_
DQ20
DDR_
DQ23
VSS
PH5
PH4
PE13
PK6
PK4
PJ13
PD10
PD5
PE3
PD1
PD0
PG15
PF0
PA9
PD3
VSS
PG6
PA15
PB7
PB3
PB15
PE5
PB14
PA8
PB4
PC7
PC6
PF2
V2_DSI
_PHY
VSS
VSS
VSS
VSS
A
B
VDDA
1V8_
DSI
VDD1V
2_DSI_
REG
DSI_
D0P
DSI_
CKP
DSI_
D1P
DDR_
DQ19
DDR_
DQ16
DDR_
DQS2N
PH10
PH15
PI0
VSS
PH14
PI14
PI1
PH11
VSS
PH13
PI3
PE14
PE15
VSS
PK7
PE0
PE11
VSS
PH12
PI6
PK3
PK5
PH8
PH9
VSS
VSS
PJ8
PJ14
PJ15
PE1
PK1
VSS
PJ12
VSS
PK0
PK2
VSS
VSS
PF1
PD4
PF5
PE6
PF4
VSS_
DSI
VSS_
DSI
VSS_
DSI
VSS_
DSI
VSS_
DSI
DDR_
DQS2P
DDR_
DQM2
VSS
C
D
E
JTCK-
SWCLK
VDD_
PLL2
VSS_
PLL2
DDR_
DQ22
DDR_
DQ17
DDR_
DQ18
PD2
PC12
PB9
PC9
PC8
PC11
JTDI
JTDO-
TRACE
SWO
NJTRS
T
JTMS-
SWDIO
VDDQ_
DDR
DDR_
DQ3
DDR_
DQ0
DDR_
DQ21
PI2
PE12
PZ3
VSS
DDR_
RESET
N
VDDQ_
DDR
DDR_
A7
DDR_
DQ1
PI7
PI5
PI15
PZ6
PD7
VSS
PC10
VSS
PE4
VSS
VSS
F
VDDQ_
DDR
DDR_
A13
DDR_
DQ7
DDR_
DQM0
DDR_
DQS0N DQS0P
DDR_
PZ4
PI13
PJ3
PZ0
PI12
PJ0
VSS
VSS
VSS
G
H
J
VDD
CORE
VDD
CORE
VDD
CORE
VDD
CORE
VDDQ_
DDR
DDR_
A9
DDR_
A5
DDR_
DQ5
DDR_
DQ2
DDR_
DQ6
PZ7
PZ5
PZ1
PI9
VSS
VSS
VSS
VSS
VDD
CORE
VDD
CORE
VDD
CORE
VDD
CORE
VDDQ_
DDR
DDR_
A2
DDR_
A3
DDR_
DQ4
PJ10
VSS
PD6
PG12
PJ2
PI4
VSS
VSS
VSS
VSS
VSS
VDD
CORE
VDD
CORE
VDD
CORE
VDD
CORE
VDDQ_
DDR
DDR_
BA2
DDR_
A0
DDR_
BA0
DDR_
DTO1
DDR_
ZQ
PJ5
PJ4
PZ2
PJ6
PJ11
PJ1
VSS
VSS
VSS
K
VDD
CORE
VDD
CORE
VDD
CORE
VDD
CORE
VDDQ_
DDR
DDR_
CSN
DDR_
ODT
DDR_
DTO0
PD15
PD8
PI8
PJ9
PJ7
VSS
VDD
VSS
VDD
VSS
VSS
VSS
VSS
VSS
L
VSS_
PLL
VDD_
PLL
VDD
CORE
VDD
CORE
VDD
CORE
VDDQ_
DDR
DDR_
A1
DDR_
A15
DDR_
RASN
DDR_
WEN
DDR_
CASN
PD9
PC13
PD14
BOOT0
VSS
PA14
PI11
PC3
VBAT
BOOT1
BOOT2
ANA0
PA3
VSS
VDD
VSS
VDD
VSS
VSS
M
N
P
VDD_
ANA
VDD
CORE
VDD
CORE
VDDQ_
DDR
DDR_
A10
DDR_
A12
DDR_
CLKP
DDR_
CLKN
DDR_
DQ8
VREF-
VREF+
VSSA
VSSA
VSSA
PA4
VDD
VSS
VSS
VDD
VSS
VSS
PC14-
OSC32
_IN
PC15-
OSC32
_OUT
VSS_
ANA
VDD
CORE
VDD
CORE
VDDQ_
DDR
DDR_
A14
DDR_
A11
DDR_
DQ10
VSS
VDD
VSS
VSS
NRST_
CORE
VDD
CORE
VDDQ_
DDR
DDR_
BA1
DDR_
CKE
DDR_
DQ13
DDR_
DQ9
DDR_
DQS1N
NRST
VDDA
ANA1
PA5
VSS
R
T
PH1-
OSC_
OUT
PH0-
OSC_IN
VDD
CORE
VDDQ_
DDR
DDR_
A4
DDR_
DQ11
DDR_
DQM1
DDR_
DQS1P
VSS
VSS
PF14
PF13
VSS
PB12
PH2
VSS
VDD
PB10
PA6
VSS
PG11
PH6
PE9
PG7
PF6
VDD
VSS
PB2
VSS
PDR_
ON_
CORE
PWR_
LP
VDDQ_
DDR
DDR_
A8
DDR_
A6
DDR_
DQ14
PG3
PG5
PF12
PF11
PG8
PB5
PC0
PB13
PE7
VSS
PF7
VDD
PF10
PD12
PE8
VDD
VSS
VSS
VSS
U
V
PWR_
ON
PDR_
ON
OTG_
VBUS
VDDQ_
DDR
DDR_
DQ12
DDR_
DQ15
DDR_
DQ24
PF3
PA1
VSS
PG0
PB11
PB1
PD13
VSS
PA12
PA11
VSS
VSS
VSS
VDDQ_
DDR
DDR_
DQ25
DDR_
DQ31
DDR_
DQ30
PI10
PC2
PH7
PE2
PA13
VSS
PA0
PG2
PF15
PH3
PB6
PE10
VSS_
PG9
VSS
W
Y
VSS_
VSS_
VDDQ_
DDR
DDR_
DQS3P DQS3N
DDR_
PG1
PA7
PA10
VSS
VSS
VSS
VSS
USBHS USBHS USBHS
BYPAS
S_REG
1V8
VSS_
USBHS
USB_
DM2
USB_
DP1
VSS_
USBHS
USB_
RREF
DDR_
ATO
DDR_
DQ29
DDR_
DQ28
DDR_
DQM3
PG13
VSS
PG14
PA2
VSS
PC5
PG10
PD11
AA
AB
VDDA
1V8_
REG
VDD
3V3_
USBHS
VDD
3V3_
USBFS
VDDA
1V1_
REG
USB_
DP2
USB_
DM1
DDR_
VREF
DDR_
DQ27
DDR_
DQ26
PC1
PG4
PB0
PC4
PB8
PF8
PF9
VSS
MSv47431V3
The above figure shows the package top view.
DS12505 Rev 5
63/260
122
Pinouts, pin description and alternate functions
STM32MP157C/F
Table 6. Legend/abbreviations used in the pinout table
Abbreviation Definition
Name
Unless otherwise specified, the pin function during and after reset is the same as the actual pin
name
Pin name
S
Supply pin
I
Input only pin
Pin type
O
Output only pin
I/O
Input / output pin
A
FT(U/D/PD)
TT
Analog or special level pin
5 V tolerant I/O (with fixed pull-up / pull-down / programmable pull-down)
3.6 V tolerant I/O directly connected to DAC
1.5 V, 1.35 V or 1.2 V I/O for DDR3, DDR3L, LPDDR2/LPDDR3 interface
1.2 V I/O for DSI interface
DDR
DSI
A
Analog signal
RST
Reset pin with weak pull-up resistor
Option for TT or FT I/Os
I/O structure
_f(1)
_a(2)
_u(3)
_h(4)
I2C FM+ option
Analog option (supplied by VDDA for the analog part of the I/O)
USB option (supplied by VDD3V3_USBxx for the USB part of the I/O)
High-speed output for 1.8V typ. VDD (for SPI, SDMMC, QUADSPI, TRACE)
Very-high-speed option for 1.8V typ. VDD (for ETH, SPI, SDMMC, QUADSPI,
TRACE)
_vh(5)
Notes
Unless otherwise specified by a note, all I/Os are set as floating inputs during and after reset
Functions selected through GPIOx_AFR registers
Alternate
functions
Additional
functions
Functions directly selected/enabled through peripheral registers
1. The related I/O structures in Table 7 are: FT_f, FT_favh, FT_fh, FT_fha, FT_uf
2. The related I/O structures in Table 7 are: FT_a, TT_a, FT_avh, FT_favh, FT_fha, FT_ha, TT_ha
3. The related I/O structures in Table 7 are: FT_u, FT_uf
4. The related I/O structures in Table 7 are: FT_h, FT_fh, FT_fha, FT_ha, TT_ha
5. The related I/O structures in Table 7 are: FT_vh, FT_avh, FT_favh
64/260
DS12505 Rev 5
STM32MP157C/F
Pin Number
Pinouts, pin description and alternate functions
Table 7. STM32MP157C/F pin and ball definitions
Pin functions
Pin name
(function after
reset)
Additional
functions
Alternate functions
I2C2_SDA, SPI5_NSS,
SAI4_SD_B, EVENTOUT
-
-
-
-
A2
C2
A2
B1
PH5
I/O
I/O
FT_f
FT
-
-
-
TIM5_CH1, I2C4_SMBA,
- I2C1_SMBA, DCMI_D1, LCD_R4,
EVENTOUT
PH10
HDP2, TIM5_CH3, I2C4_SDA,
-
-
-
-
B2
D1
F5
D3
PH12
PH13
I/O
I/O
FT_f
FT
-
-
I2C1_SDA, DCMI_D3, LCD_R6,
EVENTOUT
-
-
TIM8_CH1N, UART4_TX,
FDCAN1_TX, LCD_G2,
EVENTOUT
1E2 K6
1F3
A1
M9
A1
VDD
VSS
S
S
-
-
-
-
-
-
-
-
A1
A1
TIM8_CH2N, UART4_RX,
FDCAN1_RX, DCMI_D4,
LCD_G3, EVENTOUT
-
-
C3
B1
-
C2
C1
H6
PH14
PH15
PJ8
I/O
I/O
I/O
FT
FT
-
-
-
-
-
-
TIM8_CH3N, DCMI_D11,
LCD_G4, EVENTOUT
-
-
-
-
TRACED14, TIM1_CH3N,
TIM8_CH1, UART8_TX,
LCD_G1, EVENTOUT
FT_h
TRACECLK, LCD_CLK,
EVENTOUT
-
-
-
-
-
-
D2
F3
PI14
PI15
I/O
I/O
FT_h
FT
-
-
-
-
LCD_G2, LCD_R0, EVENTOUT
TIM5_CH4, SPI2_NSS/I2S2_WS,
DCMI_D13, LCD_G5,
EVENTOUT
-
-
-
-
-
-
C1
E3
D1
E2
PI0
PI1
I/O
I/O
FT
-
-
-
-
TIM8_BKIN2,
SPI2_SCK/I2S2_CK, DCMI_D8,
LCD_G6, EVENTOUT
FT_h
TIM8_CH4,
FT_h - SPI2_MISO/I2S2_SDI,DCMI_D9,
LCD_G7, EVENTOUT
E2
1A2
E1
E1
H9
E3
PI2
VDDCORE
PI3
I/O
S
-
-
-
1B3 E7
-
-
-
TIM8_ETR,
SPI2_MOSI/I2S2_SDO,
DCMI_D10, EVENTOUT
-
-
-
-
-
-
-
-
I/O
FT_h
-
TIM8_BKIN, SAI2_MCLK_A,
DCMI_D5, LCD_B4, EVENTOUT
E4
F3
F4
J6
F2
G5
PI4
PI5
PI6
I/O
I/O
I/O
FT
FT
FT
-
-
-
-
-
-
TIM8_CH1, SAI2_SCK_A,
DCMI_VSYNC, LCD_B5,
EVENTOUT
TIM8_CH2, SAI2_SD_A,
DCMI_D6, LCD_B6, EVENTOUT
DS12505 Rev 5
65/260
122
Pinouts, pin description and alternate functions
STM32MP157C/F
Table 7. STM32MP157C/F pin and ball definitions (continued)
Pin functions
Pin Number
Pin name
(function after
reset)
Additional
functions
Alternate functions
TIM8_CH3, SAI2_FS_A,
DCMI_D7, LCD_B7, EVENTOUT
-
-
-
F2
F1
PI7
I/O
S
FT
-
-
-
-
-
A19 A23
A19
VSS
-
I2C6_SDA, I2C2_SDA,
I2C5_SDA,
-
-
-
-
G1
G4
H5
F4
PZ1
PZ3
I/O FT_fh
-
-
SPI1_MISO/I2S1_SDI,
I2C4_SDA, USART1_RX,
SPI6_MISO, EVENTOUT
-
-
I2C6_SDA, I2C2_SDA,
I2C5_SDA, SPI1_NSS/I2S1_WS,
I2C4_SDA,
USART1_CTS/USART1_NSS,
SPI6_NSS, EVENTOUT
I/O
I/O
FT_f
FT
HDP1, UART4_RX,
FDCAN1_RX, LCD_VSYNC,
EVENTOUT
-
-
-
-
H4
G3
J5
PI9
-
-
-
-
I2C6_SCL, I2C2_SCL,
SPI1_SCK/I2S1_CK,
USART1_CK, SPI6_SCK,
EVENTOUT
G2
PZ0
I/O FT_fh
I/O FT_fh
I2C6_SCL, I2C2_SCL,
I2C5_SMBA,
SPI1_MOSI/I2S1_SDO,
I2C4_SMBA, USART1_TX,
SPI6_MOSI, EVENTOUT
-
-
-
-
J4
K5
PZ2
-
-
I2C6_SCL, I2C2_SCL,
I2C5_SCL, I2C4_SCL,
EVENTOUT
G2
-
G1
PZ4
VSS
I/O
S
FT_f
-
-
-
-
-
G1 B2
A22
-
LPTIM1_IN1, SPI6_MISO,
SAI4_CK2,
USART6_RTS/USART6_DE,
SPDIFRX_IN2, LCD_B4,
SAI4_SCK_A, ETH1_PHY_INTN,
FMC_NE4, LCD_B1, EVENTOUT
D1
F1
K4
J4
PG12
I/O
FT_h
-
-
I2C6_SDA, I2C2_SDA,
I2C5_SDA, I2C4_SDA,
USART1_RTS/USART1_DE,
EVENTOUT
-
-
-
-
E9
-
H2
-
H4
-
PZ5
VDDCORE
PZ6
I/O
S
FT_f
-
-
-
-
-
-
-
-
I2C6_SCL, I2C2_SCL,
USART1_CK, I2S1_MCK,
I2C4_SMBA, USART1_RX,
EVENTOUT
H1
G3
I/O
FT_f
I2C6_SDA, I2C2_SDA,
USART1_TX, EVENTOUT
-
-
J3
H3
PZ7
I/O
FT_f
-
-
66/260
DS12505 Rev 5
STM32MP157C/F
Pin Number
Pinouts, pin description and alternate functions
Table 7. STM32MP157C/F pin and ball definitions (continued)
Pin functions
Pin name
(function after
reset)
Additional
functions
Alternate functions
TRACED0, HDP0, LCD_HSYNC,
EVENTOUT
-
-
-
-
-
B6
-
-
C7
-
H2
B2
PI12
VSS
I/O
S
FT_h
-
-
-
-
-
-
-
-
-
FT_h
-
-
TRACED1, HDP1, LCD_VSYNC,
EVENTOUT
H1
PI13
I/O
S
-
1A4
H11
VDDCORE
-
TIM1_CH2N, TIM8_CH2,
SPI5_MOSI, LCD_G3,
EVENTOUT
-
-
-
-
-
-
J3
PJ10
PJ11
I/O
I/O
FT_h
-
-
-
TIM1_CH2, TIM8_CH2N,
SPI5_MISO, LCD_G4,
EVENTOUT
K6
FT_h
FT_h
-
-
TRACED8, LCD_R7, LCD_R1,
EVENTOUT
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
J2
L6
K4
-
PJ0
PJ1
I/O
I/O
I/O
S
-
-
-
-
-
-
-
-
-
FT_h - TRACED9, LCD_R2, EVENTOUT
TRACED10, DSI_TE, LCD_R3,
-
PJ2
FT_h
-
-
-
-
-
-
-
EVENTOUT
L5
-
VDD
-
-
TRACED11, LCD_R4,
EVENTOUT
J1
B19
K2
-
PJ3
I/O
S
FT_h
-
N1 C3
VSS
-
TRACED12, LCD_R5,
EVENTOUT
-
-
PJ4
I/O
S
FT_h
-
1D3 E11
VDDCORE
PJ5
-
TRACED2, HDP2, LCD_R6,
EVENTOUT
-
-
-
-
-
K1
I/O
FT_h
TRACED3, HDP3, TIM8_CH2,
LCD_R7, EVENTOUT
-
-
L5
PJ6
I/O
FT_h
-
-
TRACED13, TIM8_CH2N,
LCD_G0, EVENTOUT
-
-
L4
PJ7
I/O
S
FT_h
-
-
-
-
-
C17 C12
C3
VSS
-
TIM16_CH1N, SAI1_D1,
DFSDM1_CKIN4,
DFSDM1_DATIN1,
1B1 E3
D2
L3
PD6
I/O FT_ha
-
SPI3_MOSI/I2S3_SDO,
SAI1_SD_A, USART2_RX,
FMC_NWAIT, DCMI_D10,
LCD_B2, EVENTOUT
-
-
-
E13
-
-
-
H13
L2
VDDCORE
PJ9
S
-
-
-
-
-
-
TRACED15, TIM1_CH3,
TIM8_CH1N, UART8_RX,
LCD_G2, EVENTOUT
I/O
FT_h
DS12505 Rev 5
67/260
122
Pinouts, pin description and alternate functions
STM32MP157C/F
Table 7. STM32MP157C/F pin and ball definitions (continued)
Pin functions
Pin Number
Pin name
(function after
reset)
Additional
functions
Alternate functions
-
-
J5
J4
-
-
M6
M5
VDD_PLL
VSS_PLL
S
S
-
-
-
-
-
-
-
-
TIM4_CH3, SAI3_MCLK_B,
UART8_CTS,
FMC_AD0/FMC_D0, EVENTOUT
1E1 F3
1C2 G1
L3
J2
M3
L1
PD14
PD15
I/O
I/O
FT_a
FT_a
-
-
-
-
TIM4_CH4, SAI3_MCLK_A,
UART8_CTS,
FMC_AD1/FMC_D1, LCD_R1,
EVENTOUT
DFSDM1_CKIN3, SAI3_SCK_B,
USART3_TX, SPDIFRX_IN2,
FMC_AD13/FMC_D13, LCD_B7,
EVENTOUT
E1
F2
K3
M1
M2
PD8
PD9
I/O
I/O
FT_a
FT_a
-
-
-
-
DFSDM1_DATIN3, SAI3_SD_B,
USART3_RX,
1C1 G3
K1
-
FMC_AD14/FMC_D14,
DCMI_HSYNC, LCD_B0,
EVENTOUT
-
-
N8
C8
-
VDD
VSS
S
S
S
S
S
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
W1 D1 C21
-
-
1A6
1F1
-
VDDCORE
VBAT
1D1 H3
M4
C11
-
-
D4
-
VSS
RTC_OUT2/
RTC_LSCO,
TAMP_IN2/
TAMP_OUT3,
WKUP4
(1)
L4
N1
PI8
I/O
FT
EVENTOUT
RTC_OUT1/
RTC_TS/
RTC_LSCO,
TAMP_IN1/
TAMP_OUT2/
TAMP_OUT3,
WKUP3
(1)
G3 K3
K2
N2
PC13
VSS
I/O
FT
EVENTOUT
F3
F2
-
D5
H2
F4
D4
L1
C19
P2
S
-
-
-
-
PC15-
OSC32_OUT
(1)
I/O
FT
EVENTOUT
OSC32_OUT
-
H15
-
VDDCORE
VDDCORE
S
S
-
-
-
-
-
-
-
-
1C4 F6
G2 H1
1B1
PC14-
OSC32_IN
(1)
L2
P1
I/O
FT
EVENTOUT
OSC32_IN
68/260
DS12505 Rev 5
STM32MP157C/F
Pin Number
Pinouts, pin description and alternate functions
Table 7. STM32MP157C/F pin and ball definitions (continued)
Pin functions
Pin name
(function after
reset)
Additional
functions
Alternate functions
E2
J3
J1
J2
M3
M4
N1
N4
M2
P1
-
R2
R1
N3
N4
P4
T1
J8
NRST
NRST_CORE
BOOT0
I/O
RST
RST
FTPD
FTPD
FTPD
FT
-
-
-
-
-
-
-
-
-
I
I
I
I
-
-
H3 K1
-
-
K3
H1
K4
L2
BOOT1
-
-
BOOT2
-
-
H2 M1
PH0-OSC_IN I/O
EVENTOUT
-
OSC_IN
-
-
J2
-
-
VDDCORE
S
-
PH1-
OSC_OUT
M2
D8
P2
T2
I/O
FT
-
EVENTOUT
OSC_OUT
-
C20
V1
VSS
S
O
O
-
-
-
-
-
-
-
-
M2 L1
K1 P1
R2
N3
PWR_ON
PWR_LP
FT
FT
PWR_ONLP
-
U1
PDR_ON_
CORE
K2 N1
T3
U2
I
FT
-
-
-
L3
-
N2
L3
L4
R3
V2
N5
P5
PDR_ON
VDD_ANA
VSS_ANA
I
FT
-
-
-
-
-
-
-
-
-
1G2
1G1
S
S
-
-
-
DBTRGO, DBTRGI, MCO1,
UART4_TX, EVENTOUT
L2
L1
-
P2
R1
-
N2
T2
P4
W3
R3
T3
PA13
PA14
PI11
I/O
I/O
I/O
FT_a
FT_a
FT
-
-
-
BOOTFAILN
DBTRGO, DBTRGI, MCO2,
EVENTOUT
-
MCO1, I2S_CKIN, LCD_G6,
EVENTOUT
WKUP5
HDP0,
USART3_CTS/USART3_NSS,
ETH1_GMII_RX_ER/
ETH1_MII_RX_ER,
LCD_HSYNC, EVENTOUT
-
-
-
T1
W1
PI10
I/O
FT
-
-
L7
1G4
F21
-
-
-
VDD
VSS
S
S
S
S
S
S
S
S
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
W5 E2
F8
-
-
VDDCORE
VDDA
1F1 M4 1H1
R5
-
1F2
-
-
VDDA
M3 N3
R4
P6
R6
T6
VREF+
VSSA
1G1 N4 1H2
P5
-
-
VSSA
DS12505 Rev 5
69/260
122
Pinouts, pin description and alternate functions
STM32MP157C/F
Table 7. STM32MP157C/F pin and ball definitions (continued)
Pin functions
Pin Number
Pin name
(function after
reset)
Additional
functions
Alternate functions
-
-
R5
M3
-
-
U6
N6
VSSA
S
S
-
-
-
-
-
-
-
-
VREF-
I2C3_SCL, SPI5_MISO,
ETH1_GMII_RXD3/
ETH1_MII_RXD3/
ETH1_RGMII_RXD3,
MDIOS_MDC, DCMI_D9,
EVENTOUT
-
-
W4
W2
PH7
I/O FT_fh
-
-
-
ETH1_GMII_TX_ER, FMC_A3,
EVENTOUT
-
-
U1
V3
U3
PF3
PC3
I/O FT_vh
I/O FT_ha
-
-
TRACECLK, DFSDM1_DATIN1,
SPI2_MOSI/I2S2_SDO,
ADC1_INP13,
ADC1_INN12
P3
T3
W2
ETH1_GMII_TX_CLK/
ETH1_MII_TX_CLK, EVENTOUT
TRACED3, TIM8_BKIN2,
DFSDM1_CKIN1,
ETH1_GMII_TXD7, FMC_A13,
EVENTOUT
-
-
T4
Y1
U4
Y2
PG3
PE2
I/O FT_vh
-
-
-
TRACECLK, SAI1_CK1,
I2C4_SCL, SPI4_SCK,
SAI1_MCLK_A,
QUADSPI_BK1_IO2,
ETH1_GMII_TXD3/
ETH1_MII_TXD3/
P1
T1
I/O FT_favh -
ETH1_RGMII_TXD3, FMC_A23,
EVENTOUT
-
-
-
-
N10
D4
VDD
VSS
S
S
-
-
-
-
-
-
-
-
E4
H3
TIM2_CH4, TIM5_CH4,
LPTIM5_OUT, TIM15_CH2,
USART2_RX, LCD_B2,
ETH1_GMII_COL/
ADC1_INP15,
PVD_IN
N2 P3
U2
T4
PA3
I/O
FT_a
-
ETH1_MII_COL, LCD_B5,
EVENTOUT
DFSDM1_CKIN1,
SPI2_MISO/I2S2_SDI,
DFSDM1_CKOUT,
ETH1_GMII_TXD2/
ETH1_MII_TXD2/
ADC1_INP12,
ADC1_INN11
P2
T2
Y2
V2
Y1
PC2
PG2
I/O FT_avh
I/O FT_vh
-
-
ETH1_RGMII_TXD2,
DCMI_PIXCLK, EVENTOUT
TRACED2, MCO2, TIM8_BKIN,
ETH1_GMII_TXD6, FMC_A12,
EVENTOUT
-
-
W4
-
70/260
DS12505 Rev 5
STM32MP157C/F
Pin Number
Pinouts, pin description and alternate functions
Table 7. STM32MP157C/F pin and ball definitions (continued)
Pin functions
Pin name
(function after
reset)
Additional
functions
Alternate functions
TRACED1, LPTIM1_ETR,
SPI6_MOSI, SAI4_D1,
USART6_TX,
QUADSPI_BK2_IO3,
R2 U1 AA1 AA2
PG14
PG1
I/O FT_vh
I/O FT_vh
-
-
SAI4_SD_A, ETH1_GMII_TXD1/
ETH1_MII_TXD1/
ETH1_RGMII_TXD1/
ETH1_RMII_TXD1, FMC_A25,
LCD_B0, EVENTOUT
-
-
TRACED1, ETH1_GMII_TXD5,
FMC_A11, EVENTOUT
-
-
W1
Y4
TRACED0, LPTIM1_OUT,
SAI1_CK2, SAI4_CK1,
SPI6_SCK, SAI1_SCK_A,
USART6_CTS/USART6_NSS,
SAI4_MCLK_A,
R3 U2 AA2 AA1
PG13
I/O FT_vh
-
-
ETH1_GMII_TXD0/
ETH1_MII_TXD0/
ETH1_RGMII_TXD0/
ETH1_RMII_TXD0, FMC_A24,
LCD_R0, EVENTOUT
ADC1_INP0,
ADC1_INN1,
ADC2_INP0,
ADC2_INN1
-
-
U3
R4
ANA0
PA0
A
A
-
-
-
TIM2_CH1/TIM2_ETR,
TIM5_CH1, TIM8_ETR,
TIM15_BKIN,
ADC1_INP16,
WKUP1
N3 R3 AB3 AA3
I/O FT_ha
USART2_CTS/USART2_NSS,
UART4_TX, SDMMC2_CMD,
SAI2_SD_B, ETH1_GMII_CRS/
ETH1_MII_CRS, EVENTOUT
-
-
E5
-
-
E5
T5
VSS
S
A
-
-
-
-
-
ADC1_INP1,
ADC2_INP1
U4
ANA1
A
-
ETH_CLK, TIM2_CH2,
TIM5_CH2, LPTIM3_OUT,
TIM15_CH1N,
USART2_RTS/USART2_DE,
UART4_RX,
QUADSPI_BK1_IO3,
SAI2_MCLK_B,
ADC1_INP17,
ADC1_INN16
T1
U4 AA4
V4
PA1
I/O FT_ha
-
ETH1_GMII_RX_CLK/
ETH1_MII_RX_CLK/
ETH1_RGMII_RX_CLK/
ETH1_RMII_REF_CLK, LCD_R2,
EVENTOUT
DS12505 Rev 5
71/260
122
Pinouts, pin description and alternate functions
STM32MP157C/F
Table 7. STM32MP157C/F pin and ball definitions (continued)
Pin functions
Pin Number
Pin name
(function after
reset)
Additional
functions
Alternate functions
TIM2_CH1/TIM2_ETR,
TIM8_CH1N, SAI4_CK1,
ADC1_INP19,
ADC1_INN18,
1H1 P4
V3
U5
PA5
I/O TT_ha
-
SPI1_SCK/I2S1_CK, SPI6_SCK, ADC2_INP19,
SAI4_MCLK_A, LCD_R4,
EVENTOUT
ADC2_INN18,
DAC_OUT2
HDP0, TIM5_ETR, SAI4_D2,
SPI1_NSS/I2S1_WS,
ADC1_INP18,
ADC2_INP18,
DAC_OUT1
SPI3_NSS/I2S3_WS,
1J1 R4
V4
V6
PA4
I/O
TT_a
-
-
USART2_CK, SPI6_NSS,
SAI4_FS_A, DCMI_HSYNC,
LCD_VSYNC, EVENTOUT
TRACED0, DFSDM1_DATIN0,
ETH1_GMII_TXD4, FMC_A10,
EVENTOUT
-
-
AC2
W5
PG0
I/O FT_vh
-
-
TIM2_CH4, LPTIM2_ETR,
I2C2_SDA, DFSDM1_CKIN7,
USART3_RX,
ETH1_GMII_TX_EN/
ETH1_MII_TX_EN/
U3 V1 AB1
Y5
PB11
PG4
I/O FT_favh -
ETH1_RGMII_TX_CTL/
ETH1_RMII_TX_EN, DSI_TE,
LCD_G5, EVENTOUT
TIM1_BKIN2,
ETH1_GMII_GTX_CLK/
ETH1_RGMII_GTX_CLK,
FMC_A14, EVENTOUT
-
-
AB2 AB4
I/O FT_vh
I/O FT_ha
-
-
TIM2_CH3, TIM5_CH3,
LPTIM4_OUT, TIM15_CH1,
USART2_TX, SAI2_SCK_B,
SDMMC2_D0DIR, ETH1_MDIO,
MDIOS_MDIO, LCD_R1,
EVENTOUT
ADC1_INP14,
WKUP2
T3 W2 AC3 AB2
PA2
-
-
1F3 M6
-
-
VDD
S
-
-
-
TRACED0, SAI1_D1,
DFSDM1_DATIN0,
DFSDM1_CKIN4,
ADC1_INP11,
ADC1_INN10,
ADC2_INP11,
ADC2_INN10,
TAMP_IN3,
T2
V2 AA6 AB3
PC1
I/O FT_ha
-
SPI2_MOSI/I2S2_SDO,
SAI1_SD_A, SDMMC2_CK,
ETH1_MDC, MDIOS_MDC,
EVENTOUT
WKUP6
A6
-
-
K21
Y6
E19
U8
VSS
PG5
S
I/O
S
-
FT
-
-
-
-
-
-
-
-
TIM1_ETR,
ETH1_GMII_CLK125/
ETH1_RGMII_CLK125,
FMC_A15, EVENTOUT
-
-
F10 1B3
J10
VDDCORE
-
72/260
DS12505 Rev 5
STM32MP157C/F
Pin Number
Pinouts, pin description and alternate functions
Table 7. STM32MP157C/F pin and ball definitions (continued)
Pin functions
Pin name
(function after
reset)
Additional
functions
Alternate functions
DFSDM1_CKIN4,
QUADSPI_BK2_IO1,
SAI2_MCLK_B,
-
-
AA3
Y6
PH3
PB0
I/O
I/O
FT_h
FT_a
-
-
-
ETH1_GMII_COL/
ETH1_MII_COL, LCD_R1,
EVENTOUT
TIM1_CH2N, TIM3_CH3,
TIM8_CH2N, DFSDM1_CKOUT,
UART4_CTS, LCD_R3,
ETH1_GMII_RXD2/
ADC1_INP9,
ADC1_INN5,
ADC2_INP9,
ADC2_INN5
U2 W3 AB6 AB5
ETH1_MII_RXD2/
ETH1_RGMII_RXD2,
MDIOS_MDIO, LCD_G1,
EVENTOUT
TRACED7, I2C4_SDA,
I2C1_SDA, ETH1_GMII_RXD7,
FMC_A9, EVENTOUT
-
-
Y4
W6
PF15
PB1
I/O FT_fh
-
-
-
TIM1_CH3N, TIM3_CH4,
TIM8_CH3N, DFSDM1_DATIN1,
LCD_R6, ETH1_GMII_RXD3/
ETH1_MII_RXD3/
ADC1_INP5,
ADC2_INP5
U1 V3 AA7 AA5
I/O
S
FT_a
ETH1_RGMII_RXD3,
MDIOS_MDC, LCD_G0,
EVENTOUT
-
-
E6
-
-
F6
V7
VSS
-
-
-
-
-
TRACED6, DFSDM1_CKIN6,
I2C4_SCL, I2C1_SCL,
ETH1_GMII_RXD6, FMC_A8,
EVENTOUT
ADC2_INP6,
ADC2_INN2
AC4
PF14
I/O FT_fha
I/O FT_ha
TRACED5, DFSDM1_DATIN6,
I2C4_SMBA, I2C1_SMBA,
DFSDM1_DATIN3,
ETH1_GMII_RXD5, FMC_A7,
EVENTOUT
-
-
-
-
Y5
W7
PF13
PH2
-
-
ADC2_INP2
LPTIM1_IN2,
QUADSPI_BK2_IO0,
SAI2_SCK_B, ETH1_GMII_CRS/
ETH1_MII_CRS, LCD_R0,
EVENTOUT
AB4 AB7
I/O
I/O
FT_h
FT_a
-
SAI1_D3, DFSDM1_DATIN2,
SAI4_D4, SAI1_D4,
SPDIFRX_IN4,
ETH1_GMII_RXD1/
ETH1_MII_RXD1/
ETH1_RGMII_RXD1/
ETH1_RMII_RXD1, SAI4_D3,
EVENTOUT
ADC1_INP8,
ADC1_INN4,
ADC2_INP8,
ADC2_INN4
V1
V4 AB7 AA6
PC5
-
DS12505 Rev 5
73/260
122
Pinouts, pin description and alternate functions
STM32MP157C/F
Table 7. STM32MP157C/F pin and ball definitions (continued)
Pin functions
Pin Number
Pin name
(function after
reset)
Additional
functions
Alternate functions
DFSDM1_CKIN2, I2S1_MCK,
SPDIFRX_IN3,
ETH1_GMII_RXD0/
ETH1_MII_RXD0/
ADC1_INP4,
ADC2_INP4
V2 W4 AC7 AB6
PC4
I/O
FT_a
-
ETH1_RGMII_RXD0/
ETH1_RMII_RXD0, EVENTOUT
-
M8
-
P9
F7
U9
VDD
VSS
VDD
S
S
S
-
-
-
-
-
-
-
-
-
-
-
-
1D2 E8
1J3 R7
P3
1J2
TRACED4, ETH1_GMII_RXD4,
FMC_A6, EVENTOUT
ADC1_INP6,
ADC1_INN2
-
-
-
Y9
-
V8
-
PF12
I/O FT_ha
-
-
1E4
VDDCORE
S
-
-
-
SPI5_MOSI, SAI2_SD_B,
DCMI_D12, LCD_G5,
EVENTOUT
W4 U5
E10
Y10
-
W8
F8
PF11
VSS
I/O FT_ha
-
-
ADC1_INP2
-
-
S
-
-
TIM1_CH1N, TIM3_CH2,
TIM8_CH1N, SAI4_D1,
SPI1_MOSI/I2S1_SDO,
SPI6_MOSI, TIM14_CH1,
QUADSPI_CLK,
ADC1_INP7,
ADC1_INN3,
ADC2_INP7,
ADC2_INN3
W2 T6
AB8
Y9
PA7
I/O FT_ha
-
ETH1_GMII_RX_DV/
ETH1_MII_RX_DV/
ETH1_RGMII_RX_CTL/
ETH1_RMII_CRS_DV,
SAI4_SD_A, EVENTOUT
-
F12
-
J12
W9
-
VDDCORE
PA6
S
-
-
-
-
-
TIM1_BKIN, TIM3_CH1,
TIM8_BKIN, SAI4_CK2,
SPI1_MISO/I2S1_SDI,
SPI6_MISO, TIM13_CH1,
MDIOS_MDC, SAI4_SCK_A,
DCMI_PIXCLK, LCD_G2,
EVENTOUT
ADC1_INP3,
ADC2_INP3
W3 T5 AC8
I/O FT_ha
-
-
1H3
VDD
PC0
VSS
S
-
-
-
-
-
-
DFSDM1_CKIN0, LPTIM2_IN2,
DFSDM1_DATIN4, SAI2_FS_B, ADC1_INP10,
QUADSPI_BK2_NCS, LCD_R5,
EVENTOUT
U4
T7
AB5 U10
I/O FT_ha
ADC2_INP10
1G2 E12 P21
F16
S
-
-
-
74/260
DS12505 Rev 5
STM32MP157C/F
Pin Number
Pinouts, pin description and alternate functions
Table 7. STM32MP157C/F pin and ball definitions (continued)
Pin functions
Pin name
(function after
reset)
Additional
functions
Alternate functions
TIM2_CH3, LPTIM2_IN1,
I2C2_SCL, SPI2_SCK/I2S2_CK,
DFSDM1_DATIN7, USART3_TX,
QUADSPI_BK1_NCS,
ETH1_GMII_RX_ER/
ETH1_MII_RX_ER, LCD_G4,
EVENTOUT
U5 W5
Y3
V9
-
PB10
I/O FT_fha
-
-
-
-
-
V3
-
-
1B5
VDDCORE
S
-
-
TIM1_BKIN, I2C6_SMBA,
I2C2_SMBA,
SPI2_NSS/I2S2_WS,
DFSDM1_DATIN1, USART3_CK,
USART3_RX, FDCAN2_RX,
ETH1_GMII_TXD0/
V5 AC5 AA7
PB12
VDDCORE
PB13
I/O FT_avh
-
-
-
-
-
-
-
-
-
-
ETH1_MII_TXD0/
ETH1_RGMII_TXD0/
ETH1_RMII_TXD0, UART5_RX,
EVENTOUT
G5
-
J14
S
-
-
TIM1_CH1N, DFSDM1_CKOUT,
LPTIM2_OUT,
SPI2_SCK/I2S2_CK,
DFSDM1_CKIN1,
USART3_CTS/USART3_NSS,
FDCAN2_TX, ETH1_GMII_TXD1/
ETH1_MII_TXD1/
ETH1_RGMII_TXD1/
ETH1_RMII_TXD1, UART5_TX,
EVENTOUT
1J2 T9 AA10 V10
I/O FT_vh
-
E14 V21
F20
VSS
S
-
-
ETH_CLK, TIM17_BKIN,
TIM3_CH2, SAI4_D1,
I2C1_SMBA,
SPI1_MOSI/I2S1_SDO,
I2C4_SMBA,
V5
T8
Y8
AA8
PB5
I/O FT_vh
SPI3_MOSI/I2S3_SDO,
SPI6_MOSI, FDCAN2_RX,
SAI4_SD_A, ETH1_PPS_OUT,
UART5_RX, DCMI_D10,
LCD_G7, EVENTOUT
TRACED11, USART1_TX,
UART4_TX, SPDIFRX_IN1,
ETH1_GMII_TX_EN/
U6 V6
Y7
U11
PG11
I/O FT_vh
-
ETH1_MII_TX_EN/
-
ETH1_RGMII_TX_CTL/
ETH1_RMII_TX_EN, DCMI_D3,
LCD_B3, EVENTOUT
DS12505 Rev 5
75/260
122
Pinouts, pin description and alternate functions
STM32MP157C/F
Table 7. STM32MP157C/F pin and ball definitions (continued)
Pin functions
Pin Number
Pin name
(function after
reset)
Additional
functions
Alternate functions
1B5 G7 1C2
-
VDDCORE
PH6
S
I/O
S
-
FT_h
-
-
-
-
-
-
-
-
TIM12_CH1, I2C2_SMBA,
SPI5_SCK, ETH1_GMII_RXD2/
ETH1_MII_RXD2/
-
-
Y11
-
V11
G4
ETH1_RGMII_RXD2,
MDIOS_MDIO, DCMI_D8,
EVENTOUT
1H2 E16
VSS
-
HDP6, TIM16_CH1, TIM4_CH3,
DFSDM1_CKIN7, I2C1_SCL,
SDMMC1_CKIN, I2C4_SCL,
SDMMC2_CKIN, UART4_RX,
FDCAN1_RX, SDMMC2_D4,
ETH1_GMII_TXD3/
V4 W6 AB10 AB8
PB8
I/O FT_favh -
-
ETH1_MII_TXD3/
ETH1_RGMII_TXD3,
SDMMC1_D4, DCMI_D6,
LCD_B6, EVENTOUT
-
-
-
K9
Y8
VDDCORE
PG8
S
-
-
-
-
-
-
TRACED15,
TIM2_CH1/TIM2_ETR,
ETH_CLK, TIM8_ETR,
SPI6_NSS, SAI4_D2,
V6 U7 AB9
I/O FT_vh
USART6_RTS/USART6_DE,
USART3_RTS/USART3_DE,
SPDIFRX_IN3, SAI4_FS_A,
ETH1_PPS_OUT, LCD_G7,
EVENTOUT
-
N5
-
P11
VDD
PG10
VSS
S
I/O
S
-
FT_h
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
TRACED10, UART8_CTS,
LCD_G3, SAI2_SD_B,
QUADSPI_BK2_IO2, FMC_NE3,
DCMI_D2, LCD_B2, EVENTOUT
U7 V7 AB11 AA9
-
F5
W3
-
-
TIM1_CH1, DFSDM1_CKOUT,
UART7_RTS/UART7_DE,
QUADSPI_BK2_IO2,
1J4 W7 AA9 W11
PE9
I/O FT_ha
FMC_AD6/FMC_D6, EVENTOUT
-
G9
-
-
VDDCORE
PE7
S
I/O
S
-
FT_h
-
-
TIM1_ETR, TIM3_ETR,
DFSDM1_DATIN2, UART7_RX,
QUADSPI_BK2_IO0,
V7 T10 AA11 W10
FMC_AD4/FMC_D4, EVENTOUT
1C3 F7
76/260
-
G6
VSS
-
DS12505 Rev 5
STM32MP157C/F
Pin Number
Pinouts, pin description and alternate functions
Table 7. STM32MP157C/F pin and ball definitions (continued)
Pin functions
Pin name
(function after
reset)
Additional
functions
Alternate functions
LPTIM2_IN2, I2C4_SMBA,
I2C1_SMBA,
USART3_CTS/USART3_NSS,
QUADSPI_BK1_IO0,
SAI2_SD_A,
U8 V8 AC10 AB9
PD11
I/O
S
FT_h
-
-
FMC_A16/FMC_CLE,
EVENTOUT
1D5 G11 1C4
-
VDDCORE
PF7
-
-
-
-
-
-
TIM17_CH1, SPI5_SCK,
SAI1_MCLK_B, UART7_TX,
QUADSPI_BK1_IO2, EVENTOUT
W7 W8 AB12 AA10
I/O FT_ha
TRACED12, TIM16_CH1N,
SPI5_MISO, SAI1_SCK_B,
UART7_RTS/UART7_DE,
TIM13_CH1,
V8 U10 AC11 AB10
PF8
I/O FT_ha
-
-
QUADSPI_BK1_IO0, EVENTOUT
-
-
-
K11
V12
G8
VDDCORE
PF10
S
I/O
S
-
FT_h
-
-
-
-
-
-
-
-
-
-
-
-
TIM16_BKIN, SAI1_D3, SAI4_D4,
SAI1_D4, QUADSPI_CLK,
SAI4_D3, DCMI_D11, LCD_DE,
EVENTOUT
1J7 U9
Y12
AA5
-
F9
VSS
-
TIM16_CH1, SPI5_NSS,
SAI1_SD_B, UART7_RX,
QUADSPI_BK1_IO3,
U10 V9 AA13 AA11
PF6
I/O FT_ha
SAI4_SCK_B, EVENTOUT
-
H4
-
-
VDDCORE
S
-
-
LPTIM1_IN1, TIM4_CH1,
LPTIM2_IN1, I2C4_SCL,
I2C1_SCL,
USART3_RTS/USART3_DE,
QUADSPI_BK1_IO1,
SAI2_FS_A,
U14 U11 Y18 W12
PD12
I/O FT_fha
-
-
FMC_A17/FMC_ALE,
EVENTOUT
-
F11 AA8 G10
VSS
PF9
S
-
-
-
-
-
-
-
-
TRACED13, TIM17_CH1N,
SPI5_MOSI, SAI1_FS_B,
UART7_CTS, TIM14_CH1,
QUADSPI_BK1_IO1, EVENTOUT
V9 W9 AA14 AB11
I/O FT_ha
-
H6 1C6
K13
VDDCORE
S
-
-
DS12505 Rev 5
77/260
122
Pinouts, pin description and alternate functions
STM32MP157C/F
Table 7. STM32MP157C/F pin and ball definitions (continued)
Pin functions
Pin Number
Pin name
(function after
reset)
Additional
functions
Alternate functions
TRACED5, SAI1_MCLK_A,
USART6_CK,
UART8_RTS/UART8_DE,
QUADSPI_CLK,
V11 W10 AC14 Y11
PG7
I/O
FT_h
-
-
QUADSPI_BK2_IO3, DCMI_D13,
LCD_CLK, EVENTOUT
1E3 F15
1F5
-
-
G12
-
VSS
S
S
-
-
-
-
-
-
-
-
-
VDDCORE
TIM16_CH1N, TIM4_CH1,
I2C1_SCL, CEC, I2C4_SCL,
USART1_TX, FDCAN2_TX,
QUADSPI_BK1_NCS,
DFSDM1_DATIN5, UART5_TX,
DCMI_D5, EVENTOUT
W11 T12 Y14 W13
PB6
PE8
I/O FT_fha
-
-
-
TIM1_CH1N, DFSDM1_CKIN2,
FT_h - UART7_TX,QUADSPI_BK2_IO1,
FMC_AD5/FMC_D5, EVENTOUT
U12 T11 AC13 Y12
V12 V10 Y15 W14
I/O
TIM1_CH2N, DFSDM1_DATIN4,
UART7_CTS,
QUADSPI_BK2_IO3,
FMC_AD7/FMC_D7, EVENTOUT
PE10
I/O FT_ha
-
-
-
-
-
H8 1D1
K15
V13
-
VDDCORE
S
-
-
TRACED4, RTC_OUT2,
SAI1_D1, DFSDM1_CKIN1,
USART1_RX, I2S_CKIN,
SAI1_SD_A,
SPI3_MOSI/I2S3_SDO,
UART4_RX, QUADSPI_CLK,
EVENTOUT
V13 T13 Y16
PB2
I/O FT_ha
-
-
-
H10
-
VDDCORE
PD13
S
-
-
-
-
-
-
LPTIM1_OUT, TIM4_CH2,
I2C4_SDA, I2C1_SDA,
I2S3_MCK, QUADSPI_BK1_IO3,
SAI2_SCK_A, FMC_A18,
DSI_TE, EVENTOUT
U13 U12 AA19 V14
I/O FT_fha
-
-
N7
-
-
VDD
VSS
S
S
A
-
-
-
-
-
-
-
-
-
-
-
G2 AA12 G14
1J8 V16 AB18 AA17 USB_RREF
VDD3V3_
A
-
W12 AA15 AB13
S
S
A
-
-
-
-
-
-
-
-
-
-
USBHS
VDD3V3_
USB
1H7
-
-
-
USBH_HS_DP2,
OTG_HS_DP
V10 W13 AC16 AB14
USB_DP2
FT_u
78/260
DS12505 Rev 5
STM32MP157C/F
Pin Number
Pinouts, pin description and alternate functions
Table 7. STM32MP157C/F pin and ball definitions (continued)
Pin functions
Pin name
(function after
reset)
Additional
functions
Alternate functions
USBH_HS_DM2,
OTG_HS_DM
W10 V13 AB16 AA14
USB_DM2
A
FT_u
-
-
-
-
U13 AA16 Y13 VSS_USBHS
S
S
-
-
-
-
-
-
-
-
-
-
Y14 VSS_USBHS
BYPASS_
U11 T15 AB13 AA12
I
FT
-
-
-
REG1V8
DBTRGO, USART6_RX,
SPDIFRX_IN4,
QUADSPI_BK2_IO2,
SAI2_FS_B,
W8 T14 Y13 W15
PG9
I/O
FT_h
-
-
FMC_NE2/FMC_NCE,
DCMI_VSYNC, LCD_R1,
EVENTOUT
1G3
-
-
1H5
-
R10
-
VDD
VDD
S
S
-
-
-
-
-
-
-
-
N9
VDDA1V8_
REG
1H5 V11 AB14 AB12
1H3 G17
1J6 W11 AB15 AB17
S
S
S
-
-
-
-
-
-
-
-
-
-
-
-
-
-
VSS
VDDA1V1_
REG
-
-
-
-
-
G4 AA21
H7
R12
-
VSS
VDD
VDD
S
S
S
S
S
S
S
A
A
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
P6
-
-
U14
V12
Y15 VSS_USBHS
AA13 VSS_USBHS
-
-
-
-
1D4 G6 AC1
V15
J9
VSS
-
-
-
-
AA16 VSS_USBHS
-
-
W14 W14 AB17 AB15
V14 V14 AC17 AA15
USB_DM1
USB_DP1
FT_u
FT_u
USBH_HS_DM1
USBH_HS_DP1
TIM1_ETR, I2C6_SDA,
I2C5_SDA, UART4_TX,
USART1_RTS/USART1_DE,
SAI2_FS_B, FDCAN1_TX,
LCD_R5, EVENTOUT
V15 U16 AB19 W16
PA12
I/O FT_uf
-
OTG_FS_DP
-
-
G8
-
-
-
J11
L8
VSS
S
S
-
-
-
-
-
-
-
-
VDDCORE
DS12505 Rev 5
79/260
122
Pinouts, pin description and alternate functions
STM32MP157C/F
Table 7. STM32MP157C/F pin and ball definitions (continued)
Pin functions
Pin Number
Pin name
(function after
reset)
Additional
functions
Alternate functions
TIM1_CH4, I2C6_SCL,
I2C5_SCL, SPI2_NSS/I2S2_WS,
UART4_RX,
USART1_CTS/USART1_NSS,
FDCAN1_RX, LCD_R4,
EVENTOUT
U15 V17 AA18 Y16
PA11
I/O FT_uf
-
OTG_FS_DM
1C6 H12 1D3
1F4 G10 AC23
-
-
VDDCORE
VSS
S
S
-
-
-
-
-
-
-
-
VDD3V3_
USBFS
-
W15 AA17 AB16
S
A
-
-
-
-
-
-
OTG_FS_VBUS,
OTG_HS_VBUS
V16 U15 AC19 V15
OTG_VBUS
FT_u
TIM1_CH3, SPI3_NSS/I2S3_WS,
USART1_RX, MDIOS_MDIO,
SAI4_FS_B, DCMI_D1, LCD_B1,
EVENTOUT
OTG_FS_ID,
OTG_HS_ID
U16 T16 Y17
Y17
PA10
I/O
FT_u
-
-
-
AB20 AB20 DDR_DQ27
1B9 E15 1A8 E18 VDDQ_DDR
AB21 AB21 DDR_DQ26
J13 VSS
AC22 AA21 DDR_DQ28
J17 VSS
AC21 AA20 DDR_DQ29
Y22 W20 DDR_DQ25
I/O
S
DDR
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
G12
-
I/O
S
DDR
-
-
I/O
S
DDR
1H4 G14 1A3
-
DDR
DDR
DDR
-
-
-
-
-
-
-
-
-
-
-
-
-
-
I/O
I/O
-
AB22 Y21 DDR_DQS3P I/O
J20 VSS
AB23 Y22 DDR_DQS3N I/O
H5
-
-
S
DDR
-
-
-
F17
VDDQ_DDR
S
O
-
AA20 AA22 DDR_DQM3
DDR
-
F14 1B7
-
VDDQ_DDR
DDR_DQ31
VSS
S
-
H7
-
AA22 W21
1A5 K3
AA23 W22
I/O
S
DDR
-
DDR_DQ30
VSS
I/O
S
DDR
-
U9 H9
1A7
Y23
-
K7
-
-
-
-
V22
DDR_DQ24
I/O
S
DDR
-
G16 VDDQ_DDR
80/260
DS12505 Rev 5
STM32MP157C/F
Pin Number
Pinouts, pin description and alternate functions
Table 7. STM32MP157C/F pin and ball definitions (continued)
Pin functions
Pin name
(function after
reset)
Additional
functions
Alternate functions
-
-
-
L10
VDDCORE
S
A
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
W16 W16 AC20 AB19 DDR_VREF
A
-
H11
-
K10
VSS
S
-
W17 W18 W23 V20
DDR_DQ12
VSS
I/O
S
DDR
1C5 H13 1B2
V17 W17 Y21
K12
V21
K14
-
DDR_DQ15
VSS
I/O
S
DDR
-
H15
-
-
U17 V18 W22 U21
W18 V19 W21 T20
DDR_DQ14
DDR_DQ11
VDDQ_DDR
I/O
I/O
S
DDR
DDR
-
G15 1B9
V19 U19 U22
1E5 1B4
H17
-
T22 DDR_DQS1P I/O
L9 VSS
R22 DDR_DQS1N I/O
DDR
-
S
-
U18 T19 U23
V18 U18 V22
DDR
T21
J16
R20
-
DDR_DQM1
VDDQ_DDR
DDR_DQ13
VSS
O
S
DDR
1D9
T18 T18 T23
J3 1B6
U19 T17 U21
1G5 J6
T19 R18 T22
H14
R18 P18 T21
-
-
-
I/O
S
DDR
-
-
R21
L11
P21
-
DDR_DQ9
VSS
I/O
S
DDR
-
-
DDR_DQ10
VDDQ_DDR
DDR_DQ8
VSS
I/O
S
DDR
-
-
-
N22
L13
L17
I/O
S
DDR
-
J8
1B8
-
-
1J5 J10
VSS
S
-
1F8 N19 Y19 AA19
DDR_ATO
VDDCORE
VDDQ_DDR
DDR_A6
VDDQ_DDR
DDR_A8
VSS
A
A
-
-
J7
-
-
-
-
S
-
1C8
S
-
1G9 N16 W20 U19
O
S
DDR
-
-
-
-
K17
U18
L19
T18
T17 R17 Y20
J12 1C1
R17 P17 V20
O
S
DDR
-
-
DDR_A4
O
DDR
DS12505 Rev 5
81/260
122
Pinouts, pin description and alternate functions
STM32MP157C/F
Table 7. STM32MP157C/F pin and ball definitions (continued)
Pin functions
Pin Number
Pin name
(function after
reset)
Additional
functions
Alternate functions
1A6 J14 1C3
P17 P19 T20
P18 N17 U20
L20
R19
R18
L16
P18
M7
VSS
DDR_CKE
DDR_BA1
VDDQ_DDR
DDR_A14
VSS
S
O
O
S
O
S
O
S
S
O
S
S
O
O
S
O
S
O
S
O
O
S
O
S
O
O
O
S
S
S
O
O
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
DDR
DDR
-
J15
N18 N18 R21
K2
N19 M18 R20
K5
1D6 K7
M17 M19 R22
-
-
DDR
-
-
-
P19
DDR_A11
VSS
DDR
-
1C5 M10
-
-
M12
N18
L12
-
VSS
-
DDR_A10
VDDCORE
VDDQ_DDR
DDR_A12
DDR_A1
VSS
DDR
-
-
J9
-
1D5
1D9
-
-
M18 L17 P23
M19 M17 P22
N19
M18
DDR
DDR
-
-
K9
J19 K17 N20 M22
1F6 K11 N9
J18 J17 M20 M21
K14
1E9 L18 N21 M20
1C7 M14
DDR_CASN
VSS
DDR
-
-
DDR_WEN
DDR
-
-
-
M17 VDDQ_DDR
DDR_RASN
DDR_CLKP
VSS
DDR
DDR
-
L17 L19 N22
K13 1C9
K18 K19 N23
1F9 1E8
N20
-
-
N21
N16
L22
K21
M19
N11
-
DDR_CLKN
VDDQ_DDR
DDR_DTO0
DDR_DTO1
DDR_A15
VSS
DDR
-
-
1D8 K18 K20
1C8 J19 L21
L18 L16 P20
DDR
DDR
DDR
-
1H6
1E6
-
-
-
1D2
-
-
VDDCORE
VSS
-
K15
N13
L18
L21
-
J17 J18 M22
H18 H19 L22
DDR_CSN
DDR_ODT
DDR
DDR
82/260
DS12505 Rev 5
STM32MP157C/F
Pin Number
Pinouts, pin description and alternate functions
Table 7. STM32MP157C/F pin and ball definitions (continued)
Pin functions
Pin name
(function after
reset)
Additional
functions
Alternate functions
H17 J16 M21 K18
DDR_BA2
VSS
O
S
O
S
O
O
S
O
S
O
S
DDR
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
1C7 L6
G18 H18 L20
L15
1D4
N17
K19
P17
K20
G18
P3
-
DDR
-
DDR_A0
VDDQ_DDR
DDR_BA0
DDR_A13
VSS
-
-
G19 G19 L23
E17 F17 F20
DDR
DDR
-
-
L8
-
F17 G18 J20
1E7 L10 1D6
F19 F19 K22
J18
P7
DDR_A2
VSS
DDR
-
J19
-
DDR_A3
VDDQ_DDR
DDR
-
-
-
1F9
DDR_
RESETN
C16 G16 D20
F19
O
DDR
-
-
-
-
M14
1C9 H17 H20
L12 1D8
1A9 E17 E20
L14
1A8 F18 K23
-
R16
H19
P10
F18
P12
K22
VDDQ_DDR
DDR_A5
VSS
S
O
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
DDR
-
S
-
DDR_A7
VSS
O
DDR
-
-
S
-
DDR_ZQ
DDR_A9
VSS
A
A
E18 G17 G20 H18
O
DDR
1G7 M5 1E1
J11 1D7
D18 E18 J21
M7
P14
L14
J21
P20
H20
-
S
-
-
VDDCORE
DDR_DQ4
VSS
S
-
I/O
S
DDR
-
-
-
D19 D17 J22
W13 M9 1E3
C18 D18 H21
DDR_DQ5
VSS
I/O
S
DDR
-
H21
T17
H22
-
DDR_DQ2
VDDQ_DDR
DDR_DQ6
VDDQ_DDR
I/O
S
DDR
-
-
-
-
C19 D19 H22
1G8
I/O
S
DDR
-
-
-
DDR
-
B19 C19 G22 G22 DDR_DQS0P I/O
M11 R8 VSS
-
-
S
DS12505 Rev 5
83/260
122
Pinouts, pin description and alternate functions
STM32MP157C/F
Table 7. STM32MP157C/F pin and ball definitions (continued)
Pin functions
Pin Number
Pin name
(function after
reset)
Additional
functions
Alternate functions
B18 B19 G23 G21 DDR_DQS0N I/O
DDR
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
N15
C17 C18 H23
1H9
B17 B18 G21 G19
-
-
VDDQ_DDR
S
O
-
G20 DDR_DQM0
DDR
-
-
U16
VDDQ_DDR
DDR_DQ7
VSS
S
-
I/O
S
DDR
1B8 M13 1E5
A18 A18 F22
R17
F21
T7
-
DDR_DQ1
VSS
I/O
S
DDR
-
M15 1E7
-
A17 A17 E22
B16 B17 E21
E21
E20
V17
T9
DDR_DQ0
DDR_DQ3
VDDQ_DDR
VSS
I/O
I/O
S
DDR
DDR
-
P14 1H9
-
1H8
-
J13
-
-
S
-
-
-
-
-
-
-
VDDCORE
DDR_DQ21
VSS
S
-
E23
1E9
D21
-
E22
T11
D20
T19
D21
D22
I/O
S
DDR
-
N6
-
DDR_DQ22
VSS
I/O
S
DDR
-
C14 N8
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
D22
D23
-
DDR_DQ17
DDR_DQ18
I/O
I/O
S
DDR
DDR
-
W18 VDDQ_DDR
C22
C21 DDR_DQS2P I/O
U7 VSS
B22 DDR_DQS2N I/O
DDR
-
N10 1F2
B23
R15 1J8
S
-
DDR
-
-
VDDQ_DDR
DDR_DQM2
VDDQ_DDR
DDR_DQ16
VSS
S
O
-
-
-
C23
-
C22
Y19
B21
U13
A21
U15
B20
A20
DDR
-
S
B22
I/O
S
DDR
-
N12 1F4
-
A22
-
DDR_DQ23
VSS
I/O
S
DDR
-
1J9 N14
-
-
-
-
B21
A21
DDR_DQ19
DDR_DQ20
I/O
I/O
DDR
DDR
84/260
DS12505 Rev 5
STM32MP157C/F
Pin Number
Pinouts, pin description and alternate functions
Table 7. STM32MP157C/F pin and ball definitions (continued)
Pin functions
Pin name
(function after
reset)
Additional
functions
Alternate functions
-
-
-
-
P7
-
1J4
1F6
-
-
-
VDD
VSS
S
S
S
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
M11
VDDCORE
-
C15 D15 C20
A16 D16 B20
E17 JTMS-SWDIO I/O
FTU
FTD
D17 JTCK-SWCLK
I
JTDO-
E16
A15 D14 A19
B15 D13 A20
O
FTU
-
-
-
TRACESWO
D16
-
JTDI
I
FTU
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
1G6 K8
1E2
VDDCORE
NJTRST
S
I
-
B14 D12 B19
E15
D18
D19
FTU
-
-
G13
F13
-
-
VDD_PLL2
VSS_PLL2
S
S
S
S
S
A
A
-
-
1B6 B12 C14
B14 VDDA1V8_DSI
-
-
-
-
C12 C16
C13
C14
C15
B17
A17
VSS_DSI
VSS_DSI
DSI_D1P
DSI_D1N
-
-
A13 B15 B17
B13 A15 A17
DSI
DSI
VDD1V2_DSI_
PHY
1B7 A16 C17
A18
S
-
-
-
-
B12 A14 A16
A12 B14 B16
A16
B16
C16
C17
C18
B15
A15
T13
A14
DSI_CKN
DSI_CKP
VSS_DSI
VSS_DSI
VSS_DSI
DSI_D0P
DSI_D0N
VDD
A
A
S
S
S
A
A
S
S
DSI
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
DSI
-
-
-
C14
C15
C16
-
-
-
-
-
-
DSI
DSI
-
B11 B13 C15
C12 A13 B15
-
P8
-
C13 A12 B18
1A7 B16 C18
VDD_DSI
-
VDD1V2_DSI_
REG
B18
U17
S
S
-
-
-
-
-
-
-
-
D17 P9
-
VSS
DS12505 Rev 5
85/260
122
Pinouts, pin description and alternate functions
STM32MP157C/F
Table 7. STM32MP157C/F pin and ball definitions (continued)
Pin functions
Pin Number
Pin name
(function after
reset)
Additional
functions
Alternate functions
TRACED3, DFSDM1_DATIN5,
SPI3_MISO/I2S3_SDI,
USART3_RX, UART4_RX,
QUADSPI_BK2_NCS,
SAI4_SCK_B, SDMMC1_D3,
DCMI_D4, EVENTOUT
C11 A11 D16
D15
-
PC11
I/O FT_ha
-
-
-
-
-
K10
-
VDDCORE
S
I/O
S
-
FT_h
-
-
TRACED1, SAI1_D2,
DFSDM1_DATIN3,TIM15_CH1N,
SPI4_NSS, SAI1_FS_A,
A10 B11 D19
F15
PE4
-
SDMMC2_CKIN,
-
SDMMC1_CKIN, SDMMC2_D4,
SDMMC1_D4, FMC_A20,
DCMI_D4, LCD_B0, EVENTOUT
-
-
-
M13
E14
U20
F14
-
VDDCORE
PC8
-
-
-
-
-
-
-
-
-
-
-
TRACED0, TIM3_CH3,
TIM8_CH3, UART4_TX,
USART6_CK,
UART5_RTS/UART5_DE,
SDMMC1_D0, DCMI_D2,
EVENTOUT
A9 C11 D18
I/O FT_ha
-
P11 1F8
VSS
S
-
-
TRACED2, DFSDM1_CKIN5,
SPI3_SCK/I2S3_CK,
USART3_TX, UART4_TX,
QUADSPI_BK1_IO1,
SAI4_MCLK_B, SDMMC1_D2,
DCMI_D8, LCD_R2, EVENTOUT
B10 D11 D15
1D7 K12 1E4
PC10
I/O FT_ha
VDDCORE
S
-
-
TRACED8, TIM16_BKIN,
TIM3_CH1, SAI4_CK2,
SPI1_MISO/I2S1_SDI,
SPI3_MISO/I2S3_SDI,
SPI2_NSS/I2S2_WS,
SPI6_MISO, SDMMC2_D3,
SAI4_SCK_A, UART7_TX,
EVENTOUT
B6
B9
B13
C13
PB4
I/O FT_ha
-
-
TRACED1, TIM3_CH4,
TIM8_CH4, I2C3_SDA,
I2S_CKIN, UART5_CTS,
QUADSPI_BK1_IO0,
SDMMC1_D1, DCMI_D3,
LCD_B2, EVENTOUT
B9 A10 D17
G17 P13 1G3
D14
V5
PC9
VSS
I/O FT_fh
-
-
-
-
S
-
-
86/260
DS12505 Rev 5
STM32MP157C/F
Pin Number
Pinouts, pin description and alternate functions
Table 7. STM32MP157C/F pin and ball definitions (continued)
Pin functions
Pin name
(function after
reset)
Additional
functions
Alternate functions
HDP4, TIM3_CH2, TIM8_CH2,
DFSDM1_DATIN3, I2S3_MCK,
USART6_RX,
C10 A9
B11
-
D13
M15
E13
PC7
VDDCORE
PC6
I/O FT_ha
-
-
SDMMC1_D123DIR,
SDMMC2_D123DIR,
SDMMC2_D7, SDMMC1_D7,
DCMI_D1, LCD_G6, EVENTOUT
-
-
-
-
L9
S
-
-
HDP1, TIM3_CH1, TIM8_CH1,
DFSDM1_CKIN3, I2S2_MCK,
USART6_TX, SDMMC1_D0DIR,
A4 D10 B14
I/O FT_ha - SDMMC2_D0DIR, SDMMC2_D6,
DSI_TE, SDMMC1_D6,
DCMI_D0, LCD_HSYNC,
EVENTOUT
I2C2_SMBA, SDMMC2_D0DIR,
SDMMC3_D0DIR,
SDMMC1_D0DIR, FMC_A2,
EVENTOUT
-
-
A14
F13
D12
PF2
PD2
I/O
FT_h
-
-
-
-
TIM3_ETR, I2C5_SMBA,
UART4_RX, UART5_RX,
SDMMC1_CMD, DCMI_D11,
EVENTOUT
1A5 B10 D12
I/O FT_ha
1G4 P10
-
-
-
V16
-
VDD
VSS
S
S
S
-
-
-
-
-
-
-
-
-
-
-
-
-
-
P15
-
1E6
VDDCORE
MCO1, TIM1_CH1, TIM8_BKIN2,
I2C3_SCL,
SPI3_MOSI/I2S3_SDO,
USART1_CK, SDMMC2_CKIN,
SDMMC2_D4,
B8
B8
A13
B13
PA8
I/O FT_fh
-
-
OTG_FS_SOF/OTG_HS_SOF,
SAI4_SD_B, UART7_RX,
LCD_R6, EVENTOUT
TIM1_CH2N, TIM12_CH1,
TIM8_CH2N, USART1_TX,
SPI2_MISO/I2S2_SDI,
DFSDM1_DATIN2,
USART3_RTS/USART3_DE,
SDMMC2_D0, EVENTOUT
1A4 C9 C13
A13
E12
PB14
PC12
I/O
I/O
FT_h
FT_h
-
-
-
-
TRACECLK, MCO2, SAI4_D3,
SPI3_MOSI/I2S3_SDO,
USART3_CK, UART5_TX,
SAI4_SD_B, SDMMC1_CK,
DCMI_D9, EVENTOUT
1B4 C10 D13
DS12505 Rev 5
87/260
122
Pinouts, pin description and alternate functions
STM32MP157C/F
Table 7. STM32MP157C/F pin and ball definitions (continued)
Pin functions
Pin Number
Pin name
(function after
reset)
Additional
functions
Alternate functions
K17 R2 1G5
V18
B12
N12
VSS
PB15
S
I/O
S
-
FT_h
-
-
-
-
-
-
-
-
RTC_REFIN, TIM1_CH3N,
TIM12_CH2, TIM8_CH3N,
USART1_RX,
C8 A8
B12
-
SPI2_MOSI/I2S2_SDO,
DFSDM1_CKIN2, SDMMC2_D1,
EVENTOUT
-
B7
-
L11
B7
-
VDDCORE
-
TRACED3, SAI1_CK2,
DFSDM1_CKIN3, TIM15_CH1,
SPI4_MISO, SAI1_SCK_A,
SDMMC2_D0DIR,
SDMMC1_D0DIR, SDMMC2_D6,
SDMMC1_D6, FMC_A21,
DCMI_D6, LCD_G0, EVENTOUT
C11
C12
PE5
I/O
FT_h
-
-
-
U12
A12
VDD
PB3
S
-
-
-
-
-
-
TRACED9, TIM2_CH2,
SAI4_CK1, SPI1_SCK/I2S1_CK,
SPI3_SCK/I2S3_CK, SPI6_SCK,
SDMMC2_D2, SAI4_MCLK_A,
UART7_RX, EVENTOUT
C7 A7
A11
I/O
FT_h
-
R6
A6
-
-
A10
-
V19
D11
-
VSS
PG6
S
I/O
S
-
FT_h
-
-
-
-
-
-
-
-
TRACED14, TIM17_BKIN,
SDMMC2_CMD, DCMI_D12,
LCD_R7, EVENTOUT
B5
1F7
VDDCORE
-
HDP5, DFSDM1_CKOUT,
SPI2_SCK/I2S2_CK,
DFSDM1_DATIN0,
USART2_CTS/USART2_NSS,
SDMMC1_D123DIR,
SDMMC2_D7,
SDMMC2_D123DIR,
SDMMC1_D7, FMC_CLK,
DCMI_D5, LCD_G7, EVENTOUT
A7 C6 D14
B11
F12
PD3
I/O
FT_h
-
-
-
HDP7, TIM17_CH1, TIM4_CH4,
DFSDM1_DATIN7, I2C1_SDA,
SPI2_NSS/I2S2_WS, I2C4_SDA,
SDMMC2_CDIR, UART4_TX,
FDCAN1_TX, SDMMC2_D5,
SDMMC1_CDIR, SDMMC1_D5,
DCMI_D7, LCD_B7, EVENTOUT
C9 D9
B10
PB9
I/O FT_fh
-
88/260
DS12505 Rev 5
STM32MP157C/F
Pin Number
Pinouts, pin description and alternate functions
Table 7. STM32MP157C/F pin and ball definitions (continued)
Pin functions
Pin name
(function after
reset)
Additional
functions
Alternate functions
DBTRGI, TIM2_CH1/TIM2_ETR,
SAI4_D2, SDMMC1_CDIR, CEC,
SPI1_NSS/I2S1_WS,
SPI3_NSS/I2S3_WS, SPI6_NSS,
UART4_RTS/UART4_DE,
SDMMC2_D5, SDMMC2_CDIR,
SDMMC1_D5, SAI4_FS_A,
UART7_TX, LCD_R1,
B4 C7 C19
E11
PA15
I/O
FT_h
-
-
EVENTOUT
N17
-
1G7 W17
VSS
PA9
S
-
-
-
-
-
-
TIM1_CH2, I2C3_SMBA,
SPI2_SCK/I2S2_CK,
USART1_TX, SDMMC2_CDIR,
SDMMC2_D5, DCMI_D0,
LCD_R5, EVENTOUT
C6 C8
A8
A11
I/O
FT_h
TIM17_CH1N, TIM4_CH2,
I2C1_SDA, I2C4_SDA,
A3
-
B5
D11
F11
N14
B10
-
PB7
VDDCORE
PD1
I/O FT_fh
-
-
-
-
USART1_RX, SDMMC2_D1,
DFSDM1_CKIN5, FMC_NL,
DCMI_VSYNC, EVENTOUT
-
-
-
-
L13 1F5
S
-
-
I2C6_SCL, DFSDM1_DATIN6,
I2C5_SCL, SAI3_SD_A,
UART4_TX, FDCAN1_TX,
SDMMC3_D0, DFSDM1_CKIN7,
FMC_AD3/FMC_D3, EVENTOUT
A2
-
A4
R9
B9
I/O FT_fh
1J6
VDD
S
-
-
I2C6_SDA, DFSDM1_CKIN6,
I2C5_SDA, SAI3_SCK_A,
UART4_RX, FDCAN1_RX,
SDMMC3_CMD,
C5 A3
B8
C10
PD0
I/O FT_fh
-
-
DFSDM1_DATIN7,
FMC_AD2/FMC_D2, EVENTOUT
-
R8
-
W19
A10
VSS
PE3
S
-
-
-
-
-
-
TRACED0, TIM15_BKIN,
SAI1_SD_B, SDMMC2_CK,
FMC_A19, EVENTOUT
1A3 A5
C4 D7
C9
I/O
FT_h
USART2_TX, SDMMC3_D2,
FMC_NWE, EVENTOUT
A7
A9
PD5
I/O
FT_h
-
-
TRACED6, DFSDM1_DATIN4,
I2C2_SCL, DFSDM1_CKIN1,
USART2_CK, SPDIFRX_IN1,
SDMMC3_D3, FMC_NE1,
EVENTOUT
B3
-
B4
D10
-
F10
-
PD7
I/O FT_fh
-
-
-
-
M10
VDDCORE
S
-
-
DS12505 Rev 5
89/260
122
Pinouts, pin description and alternate functions
STM32MP157C/F
Table 7. STM32MP157C/F pin and ball definitions (continued)
Pin functions
Pin Number
Pin name
(function after
reset)
Additional
functions
Alternate functions
TRACED7, SAI1_D2, I2C2_SDA,
SAI1_FS_A,
B1
B2
A2
B3
B7
D10
E9
PG15
PE6
I/O FT_fh
-
-
USART6_CTS/USART6_NSS,
SDMMC3_CK, DCMI_D13,
EVENTOUT
-
-
TRACED2, TIM1_BKIN2,
SAI1_D1, TIM15_CH2,
SPI4_MOSI, SAI1_SD_A,
SDMMC2_D0, SDMMC1_D2,
SAI2_MCLK_B, FMC_A22,
DCMI_D7, LCD_G1, EVENTOUT
C10
I/O
S
FT_h
-
-
-
-
-
R10 1G9
Y3
E10
P13
B9
-
VSS
PF0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
I2C2_SDA, SDMMC3_D0,
SDMMC3_CKIN, FMC_A0,
EVENTOUT
-
-
-
D8
-
I/O FT_fh
VDDCORE
PF1
S
-
-
I2C2_SCL, SDMMC3_CMD,
SDMMC3_CDIR, FMC_A1,
EVENTOUT
A5
I/O FT_fh
F18 R12 1H4
D9
1E8 M12 1F7
VSS
S
I/O
S
-
FT_h
-
-
USART2_RX, SDMMC3_D1,
SDMMC3_D123DIR, FMC_A4,
EVENTOUT
-
-
F9
-
PF4
VDDCORE
-
SAI3_FS_A,
USART2_RTS/USART2_DE,
SDMMC3_D1, DFSDM1_CKIN0,
FMC_NOE, EVENTOUT
C3 D6
B6
C9
PD4
I/O
FT_h
-
-
-
-
-
-
-
-
D7
-
U14
D9
VDD
PF5
VSS
S
I/O
S
-
FT_h
-
-
-
-
-
-
-
-
USART2_TX, SDMMC3_D2,
FMC_A5, EVENTOUT
R14
Y7
-
RTC_REFIN, TIM16_BKIN,
DFSDM1_CKOUT, I2C5_SMBA,
SPI3_MISO/I2S3_SDI,
SAI3_FS_B, USART3_CK,
FMC_AD15/FMC_D15, LCD_B3,
EVENTOUT
1A2 C5
B5
A8
PD10
I/O
FT_h
-
-
-
-
-
-
N11
-
-
-
-
P15
B8
VDDCORE
PJ12
S
-
-
-
-
-
-
-
-
-
-
-
-
-
I/O
I/O
I/O
FT
FT
FT
LCD_G3, LCD_B0, EVENTOUT
LCD_G4, LCD_B1, EVENTOUT
LCD_B2, EVENTOUT
A7
PJ13
B7
PJ14
90/260
DS12505 Rev 5
STM32MP157C/F
Pin Number
Pinouts, pin description and alternate functions
Table 7. STM32MP157C/F pin and ball definitions (continued)
Pin functions
Pin name
(function after
reset)
Additional
functions
Alternate functions
A19 R16 1H6
Y10
C7
-
VSS
PJ15
S
I/O
S
-
FT
-
-
-
-
-
-
-
-
-
-
-
-
-
LCD_B3, EVENTOUT
-
1G6
VDDCORE
TIM1_CH1N, TIM8_CH3,
SPI5_SCK, LCD_G5,
EVENTOUT
-
-
-
-
-
-
-
-
-
D8
E7
E8
PK0
PK1
PK2
I/O
I/O
I/O
FT_h
FT_h
FT_h
-
-
-
-
-
-
TRACED4, TIM1_CH1, HDP4,
TIM8_CH3N, SPI5_NSS,
LCD_G6, EVENTOUT
TRACED5, TIM1_BKIN, HDP5,
TIM8_BKIN, LCD_G7,
EVENTOUT
-
-
-
-
-
R11
T4
N13
-
-
-
-
-
-
-
VDD
VSS
S
S
-
-
-
-
-
-
-
-
-
-
-
-
-
Y18
R14
B6
-
VDDCORE
PK3
S
-
-
I/O
I/O
FT
FT
LCD_B4, EVENTOUT
LCD_B5, EVENTOUT
-
A6
PK4
TRACED6, HDP6, LCD_B6,
EVENTOUT
-
-
-
C6
Y20
A5
PK5
VSS
PK6
I/O
S
FT_h
-
-
-
-
-
-
-
K19 U3 1H8
-
TRACED7, HDP7, LCD_B7,
EVENTOUT
-
-
-
I/O
FT_h
1G8 P12
-
-
-
VDDCORE
PK7
S
-
-
-
-
-
-
-
-
B5
I/O
FT
LCD_DE, EVENTOUT
LPTIM1_ETR, TIM4_ETR,
LPTIM2_ETR,
SPI3_SCK/I2S3_CK,
C2 C4
D6
C5
PE0
I/O
FT_h
-
-
SAI4_MCLK_B, UART8_RX,
SAI2_MCLK_A, FMC_NBL0,
DCMI_D2, EVENTOUT
LPTIM1_IN2, I2S2_MCK,
SAI3_SD_B, UART8_TX,
FMC_NBL1, DCMI_D3,
EVENTOUT
1A1 B1
C8
D7
PE1
I/O
FT
-
-
-
-
U6
-
1J3
D5
AA4
D6
VSS
PH8
S
-
-
-
-
-
-
TIM5_ETR, I2C3_SDA,
DCMI_HSYNC, LCD_R2,
EVENTOUT
I/O
FT_f
-
-
-
-
1H7
C5
T15
E6
VDDCORE
PH9
S
-
-
-
-
-
-
TIM12_CH2, I2C3_SMBA,
DCMI_D0, LCD_R3, EVENTOUT
I/O
FT
DS12505 Rev 5
91/260
122
Pinouts, pin description and alternate functions
STM32MP157C/F
Table 7. STM32MP157C/F pin and ball definitions (continued)
Pin functions
Pin Number
Pin name
(function after
reset)
Additional
functions
Alternate functions
TIM1_CH2, DFSDM1_CKIN4,
SPI4_NSS, USART6_CK,
SAI2_SD_B,
FMC_AD8/FMC_D8, DCMI_D4,
LCD_G3, EVENTOUT
D2 C1
A4
B4
A3
D5
E4
A4
PE11
PE12
PE13
I/O
I/O
I/O
FT
-
-
-
-
-
-
TIM1_CH3N, DFSDM1_DATIN5,
SPI4_SCK, SDMMC1_D0DIR,
SAI2_SCK_B,
FMC_AD9/FMC_D9, LCD_B4,
EVENTOUT
C1 D2
FT_h
FT_h
HDP2, TIM1_CH3,
DFSDM1_CKIN5, SPI4_MISO,
SAI2_FS_B,
E3 C2
FMC_AD10/FMC_D10,
DCMI_D6, LCD_DE, EVENTOUT
-
-
R13
-
-
C4
-
-
VDDCORE
PH11
S
-
-
-
-
-
-
TIM5_CH2, I2C4_SCL,
I2C1_SCL, DCMI_D2, LCD_R5,
EVENTOUT
B3
I/O
FT_f
R19 U8
AA18
AB1
VSS
VSS
VSS
VSS
S
S
S
S
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
U17 1J5
W19 W1
-
AB18
-
W19 1J7 AB22
TIM1_CH4, SPI4_MOSI,
UART8_RTS/UART8_DE,
SAI2_MCLK_B,
1B2 D3
C6
B4
PE14
I/O
FT_h
-
-
SDMMC1_D123DIR,
FMC_AD11/FMC_D11, LCD_G0,
LCD_CLK, EVENTOUT
HDP3, TIM1_BKIN, TIM15_BKIN,
USART2_CTS/USART2_NSS,
UART8_CTS, FMC_NCE2,
FMC_AD12/FMC_D12, LCD_R7,
EVENTOUT
D3 E1
D3
B3
C4
A3
PE15
PH4
I/O
I/O
FT
-
-
-
-
I2C2_SCL, LCD_G5, LCD_G4,
EVENTOUT
-
-
FT_f
1. IO supplied by VSW domain.
92/260
DS12505 Rev 5
(1)
Table 8. Alternate function AF0 to AF7
AF0
AF1
AF2
AF3
AF4
AF5
AF6
AF7
SPI1/I2S1/
SPI2/I2S2/
SPI3/I2S3/
SPI4/5/6/I2C1/
SDMMC1/3/
CEC
SPI2/I2S2/
SPI3/I2S3/
SPI6/
USART1/2/3/6/
UART7/
SAI4/I2C2/
TIM8/
LPTIM2/3/4/5/
DFSDM1
SAI4/
I2C1/2/3/4/5/
USART1/
TIM15/LPTIM2/
DFSDM1/CEC
SPI3/I2S3/
SAI1/3/4/
I2C4/UART4/
DFSDM1
TIM1/2/16/17/
HDP/SYS/RTC LPTIM1/SYS/
RTC
SAI1/4/I2C6/
TIM3/4/5/12/
HDP/SYS
Port
/SDMMC1
SDMMC2
TIM2_CH1/
TIM2_ETR
USART2_CTS/
USART2_NSS
PA0
PA1
-
TIM5_CH1
TIM5_CH2
TIM8_ETR
TIM15_BKIN
TIM15_CH1N
-
-
-
-
USART2_RTS/
USART2_DE
ETH_CLK
TIM2_CH2
LPTIM3_OUT
PA2
PA3
-
-
TIM2_CH3
TIM2_CH4
TIM5_CH3
TIM5_CH4
LPTIM4_OUT
LPTIM5_OUT
TIM15_CH1
TIM15_CH2
-
-
-
-
USART2_TX
USART2_RX
SPI1_NSS/
I2S1_WS
SPI3_NSS/
I2S3_WS
PA4
PA5
PA6
PA7
PA8
PA9
HDP0
-
TIM5_ETR
-
SAI4_D2
SAI4_CK1
SAI4_CK2
SAI4_D1
I2C3_SCL
I2C3_SMBA
-
USART2_CK
TIM2_CH1/
TIM2_ETR
SPI1_SCK/I2S1
_CK
-
-
TIM8_CH1N
-
-
SPI1_MISO/
I2S1_SDI
-
TIM1_BKIN
TIM1_CH1N
TIM1_CH1
TIM1_CH2
TIM1_CH3
TIM1_CH4
TIM1_ETR
TIM3_CH1
TIM8_BKIN
-
-
Port A
SPI1_MOSI/
I2S1_SDO
-
TIM3_CH2
TIM8_CH1N
-
-
SPI3_MOSI/
I2S3_SDO
MCO1
-
TIM8_BKIN2
-
USART1_CK
USART1_TX
USART1_RX
SPI2_SCK/
I2S2_CK
-
-
-
-
-
-
-
-
-
-
SPI3_NSS/
I2S3_WS
PA10
PA11
PA12
-
-
SPI2_NSS/
I2S2_WS
USART1_CTS/
USART1_NSS
I2C6_SCL
I2C6_SDA
I2C5_SCL
I2C5_SDA
UART4_RX
UART4_TX
USART1_RTS/
USART1_DE
-
(1)
Table 8. Alternate function AF0 to AF7 (continued)
AF0
AF1
AF2
AF3
AF4
AF5
AF6
AF7
SPI1/I2S1/
SPI2/I2S2/
SPI3/I2S3/
SPI4/5/6/I2C1/
SDMMC1/3/
CEC
SPI2/I2S2/
SPI3/I2S3/
SPI6/
USART1/2/3/6/
UART7/
SAI4/I2C2/
TIM8/
LPTIM2/3/4/5/
DFSDM1
SAI4/
I2C1/2/3/4/5/
USART1/
TIM15/LPTIM2/
DFSDM1/CEC
SPI3/I2S3/
SAI1/3/4/
I2C4/UART4/
DFSDM1
TIM1/2/16/17/
HDP/SYS/RTC LPTIM1/SYS/
RTC
SAI1/4/I2C6/
TIM3/4/5/12/
HDP/SYS
Port
/SDMMC1
SDMMC2
PA13
DBTRGO
DBTRGO
DBTRGI
DBTRGI
MCO1
MCO2
-
-
-
-
-
-
-
-
-
-
PA14
PA15
Port A
TIM2_CH1/
TIM2_ETR
SDMMC1_
CDIR
SPI1_NSS/
I2S1_WS
SPI3_NSS/
I2S3_WS
DBTRGI
-
SAI4_D2
TIM3_CH3
TIM3_CH4
SAI1_D1
-
CEC
-
SPI6_NSS
DFSDM1_
CKOUT
PB0
PB1
PB2
PB3
PB4
PB5
TIM1_CH2N
TIM1_CH3N
RTC_OUT2
TIM2_CH2
TIM8_CH2N
TIM8_CH3N
-
-
-
DFSDM1_
DATIN1
-
-
-
DFSDM1_
CKIN1
SPI3_MOSI/
I2S3_SDO
TRACED4
TRACED9
TRACED8
ETH_CLK
USART1_RX
SAI4_CK1
SAI4_CK2
I2C1_SMBA
I2S_CKIN
SAI1_SD_A
SPI1_SCK/
I2S1_CK
SPI3_SCK/
I2S3_CK
-
-
SPI1_MISO/
I2S1_SDI
SPI3_MISO/
I2S3_SDI
SPI2_NSS/
I2S2_WS
TIM16_BKIN
TIM17_BKIN
TIM3_CH1
TIM3_CH2
-
Port B
SPI1_MOSI/
I2S1_SDO
SPI3_MOSI/
I2S3_SDO
SAI4_D1
I2C4_SMBA
PB6
PB7
-
-
TIM16_CH1N
TIM17_CH1N
TIM4_CH1
TIM4_CH2
-
-
I2C1_SCL
I2C1_SDA
CEC
-
I2C4_SCL
I2C4_SDA
USART1_TX
USART1_RX
DFSDM1_
CKIN7
SDMMC1_
CKIN
SDMMC2_
CKIN
PB8
PB9
HDP6
HDP7
-
TIM16_CH1
TIM17_CH1
TIM2_CH3
TIM4_CH3
TIM4_CH4
-
I2C1_SCL
I2C1_SDA
I2C2_SCL
I2C4_SCL
I2C4_SDA
DFSDM1_
DATIN7
SPI2_NSS/
I2S2_WS
SDMMC2_
CDIR
SPI2_SCK/
I2S2_CK
DFSDM1_
DATIN7
PB10
LPTIM2_IN1
USART3_TX
(1)
Table 8. Alternate function AF0 to AF7 (continued)
AF0
AF1
AF2
AF3
AF4
AF5
AF6
AF7
SPI1/I2S1/
SPI2/I2S2/
SPI3/I2S3/
SPI4/5/6/I2C1/
SDMMC1/3/
CEC
SPI2/I2S2/
SPI3/I2S3/
SPI6/
USART1/2/3/6/
UART7/
SAI4/I2C2/
TIM8/
LPTIM2/3/4/5/
DFSDM1
SAI4/
I2C1/2/3/4/5/
USART1/
TIM15/LPTIM2/
DFSDM1/CEC
SPI3/I2S3/
SAI1/3/4/
I2C4/UART4/
DFSDM1
TIM1/2/16/17/
HDP/SYS/RTC LPTIM1/SYS/
RTC
SAI1/4/I2C6/
TIM3/4/5/12/
HDP/SYS
Port
/SDMMC1
SDMMC2
DFSDM1_
CKIN7
PB11
-
TIM2_CH4
-
LPTIM2_ETR
-
I2C2_SDA
I2C2_SMBA
LPTIM2_OUT
USART1_TX
USART1_RX
LPTIM2_IN2
-
USART3_RX
USART3_CK
SPI2_NSS/
I2S2_WS
DFSDM1_
DATIN1
PB12
Port B PB13
PB14
-
TIM1_BKIN
I2C6_SMBA
DFSDM1_
CKOUT
SPI2_SCK/
I2S2_CK
DFSDM1_
CKIN1
USART3_CTS/
USART3_NSS
-
TIM1_CH1N
-
SPI2_MISO/
I2S2_SDI
DFSDM1_
DATIN2
USART3_RTS/
USART3_DE
-
TIM1_CH2N
TIM12_CH1
TIM8_CH2N
TIM8_CH3N
SPI2_MOSI/
I2S2_SDO
DFSDM1_
CKIN2
PB15
RTC_REFIN
TIM1_CH3N
TIM12_CH2
-
DFSDM1_
CKIN0
DFSDM1_
DATIN4
PC0
-
-
-
-
-
-
-
-
-
-
-
DFSDM1_
DATIN0
DFSDM1_
CKIN4
SPI2_MOSI/
I2S2_SDO
PC1
TRACED0
SAI1_D1
SAI1_SD_A
-
DFSDM1_
CKIN1
SPI2_MISO/
I2S2_SDI
DFSDM1_
CKOUT
PC2
-
-
-
-
DFSDM1_
DATIN1
SPI2_MOSI/
I2S2_SDO
Port C PC3
PC4
TRACECLK
-
-
-
-
DFSDM1_
CKIN2
-
-
-
-
I2S1_MCK
-
-
-
DFSDM1_
DATIN2
PC5
SAI1_D3
TIM3_CH1
SAI4_D4
SAI1_D4
-
-
DFSDM1_
CKIN3
PC6
HDP1
TIM8_CH1
I2S2_MCK
USART6_TX
(1)
Table 8. Alternate function AF0 to AF7 (continued)
AF0
AF1
AF2
AF3
AF4
AF5
AF6
AF7
SPI1/I2S1/
SPI2/I2S2/
SPI3/I2S3/
SPI4/5/6/I2C1/
SDMMC1/3/
CEC
SPI2/I2S2/
SPI3/I2S3/
SPI6/
USART1/2/3/6/
UART7/
SAI4/I2C2/
TIM8/
LPTIM2/3/4/5/
DFSDM1
SAI4/
I2C1/2/3/4/5/
USART1/
TIM15/LPTIM2/
DFSDM1/CEC
SPI3/I2S3/
SAI1/3/4/
I2C4/UART4/
DFSDM1
TIM1/2/16/17/
HDP/SYS/RTC LPTIM1/SYS/
RTC
SAI1/4/I2C6/
TIM3/4/5/12/
HDP/SYS
Port
/SDMMC1
SDMMC2
DFSDM1_
DATIN3
PC7
HDP4
-
TIM3_CH2
TIM8_CH2
-
I2S3_MCK
USART6_RX
PC8
PC9
TRACED0
TRACED1
-
-
TIM3_CH3
TIM3_CH4
TIM8_CH3
TIM8_CH4
-
-
UART4_TX
-
USART6_CK
-
I2C3_SDA
I2S_CKIN
DFSDM1_
CKIN5
SPI3_SCK/
I2S3_CK
PC10
PC11
PC12
TRACED2
TRACED3
TRACECLK
-
-
-
-
-
-
-
-
-
USART3_TX
USART3_RX
USART3_CK
Port C
DFSDM1_
DATIN5
SPI3_MISO/
I2S3_SDI
-
SPI3_MOSI/
I2S3_SDO
MCO2
SAI4_D3
-
PC13
PC14
PC15
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
DFSDM1_
CKIN6
PD0
-
-
I2C6_SDA
I2C5_SDA
-
SAI3_SCK_A
-
DFSDM1_
DATIN6
PD1
PD2
PD3
-
-
-
-
-
I2C6_SCL
TIM3_ETR
-
I2C5_SCL
I2C5_SMBA
-
-
-
SAI3_SD_A
UART4_RX
-
-
-
Port D
DFSDM1_
CKOUT
SPI2_SCK/
I2S2_CK
DFSDM1_
DATIN0
USART2_CTS/
USART2_NSS
HDP5
USART2_RTS/
USART2_DE
PD4
PD5
-
-
-
-
-
-
-
-
-
-
-
-
SAI3_FS_A
-
USART2_TX
(1)
Table 8. Alternate function AF0 to AF7 (continued)
AF0
AF1
AF2
AF3
AF4
AF5
AF6
AF7
SPI1/I2S1/
SPI2/I2S2/
SPI3/I2S3/
SPI4/5/6/I2C1/
SDMMC1/3/
CEC
SPI2/I2S2/
SPI3/I2S3/
SPI6/
USART1/2/3/6/
UART7/
SAI4/I2C2/
TIM8/
LPTIM2/3/4/5/
DFSDM1
SAI4/
I2C1/2/3/4/5/
USART1/
TIM15/LPTIM2/
DFSDM1/CEC
SPI3/I2S3/
SAI1/3/4/
I2C4/UART4/
DFSDM1
TIM1/2/16/17/
HDP/SYS/RTC LPTIM1/SYS/
RTC
SAI1/4/I2C6/
TIM3/4/5/12/
HDP/SYS
Port
/SDMMC1
SDMMC2
DFSDM1_
CKIN4
DFSDM1_
DATIN1
SPI3_MOSI/
I2S3_SDO
PD6
-
TIM16_CH1N
SAI1_D1
SAI1_SD_A
USART2_RX
USART2_CK
USART3_TX
USART3_RX
USART3_CK
DFSDM1_
DATIN4
DFSDM1_
CKIN1
PD7
PD8
TRACED6
-
-
I2C2_SCL
-
-
-
-
DFSDM1_
CKIN3
-
-
-
SAI3_SCK_B
DFSDM1_
DATIN3
PD9
-
-
-
-
SAI3_SD_B
DFSDM1_
CKOUT
SPI3_MISO/
I2S3_SDI
Port D
PD10
PD11
PD12
RTC_REFIN
TIM16_BKIN
-
-
I2C5_SMBA
I2C4_SMBA
I2C4_SCL
SAI3_FS_B
USART3_CTS/
USART3_NSS
-
-
-
LPTIM2_IN2
LPTIM2_IN1
I2C1_SMBA
I2C1_SCL
-
-
USART3_RTS/
USART3_DE
LPTIM1_IN1
TIM4_CH1
PD13
PD14
PD15
-
-
-
LPTIM1_OUT
TIM4_CH2
TIM4_CH3
TIM4_CH4
-
-
-
I2C4_SDA
I2C1_SDA
I2S3_MCK
-
-
-
-
-
-
-
-
-
SAI3_MCLK_B
SAI3_MCLK_A
SPI3_SCK/
I2S3_CK
PE0
-
LPTIM1_ETR
TIM4_ETR
-
LPTIM2_ETR
SAI4_MCLK_B
-
PE1
PE2
PE3
-
LPTIM1_IN2
-
-
-
-
-
I2S2_MCK
SPI4_SCK
-
SAI3_SD_B
SAI1_MCLK_A
SAI1_SD_B
-
-
-
Port E
TRACECLK
TRACED0
-
-
SAI1_CK1
-
I2C4_SCL
TIM15_BKIN
(1)
Table 8. Alternate function AF0 to AF7 (continued)
AF0
AF1
AF2
AF3
AF4
AF5
AF6
AF7
SPI1/I2S1/
SPI2/I2S2/
SPI3/I2S3/
SPI4/5/6/I2C1/
SDMMC1/3/
CEC
SPI2/I2S2/
SPI3/I2S3/
SPI6/
USART1/2/3/6/
UART7/
SAI4/I2C2/
TIM8/
LPTIM2/3/4/5/
DFSDM1
SAI4/
I2C1/2/3/4/5/
USART1/
TIM15/LPTIM2/
DFSDM1/CEC
SPI3/I2S3/
SAI1/3/4/
I2C4/UART4/
DFSDM1
TIM1/2/16/17/
HDP/SYS/RTC LPTIM1/SYS/
RTC
SAI1/4/I2C6/
TIM3/4/5/12/
HDP/SYS
Port
/SDMMC1
SDMMC2
DFSDM1_
DATIN3
SDMMC2_
CKIN
PE4
TRACED1
-
SAI1_D2
TIM15_CH1N
SPI4_NSS
SAI1_FS_A
DFSDM1_
CKIN3
SDMMC2_
D0DIR
PE5
PE6
PE7
TRACED3
TRACED2
-
-
SAI1_CK2
SAI1_D1
TIM15_CH1
TIM15_CH2
-
SPI4_MISO
SPI4_MOSI
-
SAI1_SCK_A
TIM1_BKIN2
TIM1_ETR
-
SAI1_SD_A
-
SDMMC2_D0
UART7_RX
DFSDM1_
DATIN2
TIM3_ETR
DFSDM1_
CKIN2
PE8
PE9
-
-
-
-
-
TIM1_CH1N
TIM1_CH1
TIM1_CH2N
TIM1_CH2
TIM1_CH3N
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
UART7_TX
DFSDM1_
CKOUT
UART7_RTS/
UART7_DE
-
Port E
DFSDM1_
DATIN4
PE10
PE11
PE12
-
UART7_CTS
USART6_CK
-
DFSDM1_
CKIN4
SPI4_NSS
SPI4_SCK
DFSDM1_
DATIN5
DFSDM1_
CKIN5
PE13
PE14
PE15
HDP2
-
TIM1_CH3
TIM1_CH4
TIM1_BKIN
-
-
-
-
SPI4_MISO
SPI4_MOSI
-
-
-
-
-
-
-
-
-
USART2_CTS/
USART2_NSS
HDP3
TIM15_BKIN
PF0
PF1
-
-
-
-
-
-
-
-
I2C2_SDA
I2C2_SCL
-
-
-
-
-
-
Port F
(1)
Table 8. Alternate function AF0 to AF7 (continued)
AF0
AF1
AF2
AF3
AF4
AF5
AF6
AF7
SPI1/I2S1/
SPI2/I2S2/
SPI3/I2S3/
SPI4/5/6/I2C1/
SDMMC1/3/
CEC
SPI2/I2S2/
SPI3/I2S3/
SPI6/
USART1/2/3/6/
UART7/
SAI4/I2C2/
TIM8/
LPTIM2/3/4/5/
DFSDM1
SAI4/
I2C1/2/3/4/5/
USART1/
TIM15/LPTIM2/
DFSDM1/CEC
SPI3/I2S3/
SAI1/3/4/
I2C4/UART4/
DFSDM1
TIM1/2/16/17/
HDP/SYS/RTC LPTIM1/SYS/
RTC
SAI1/4/I2C6/
TIM3/4/5/12/
HDP/SYS
Port
/SDMMC1
SDMMC2
PF2
PF3
PF4
PF5
PF6
PF7
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
I2C2_SMBA
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
USART2_RX
USART2_TX
UART7_RX
UART7_TX
-
-
-
TIM16_CH1
TIM17_CH1
SPI5_NSS
SPI5_SCK
SAI1_SD_B
SAI1_MCLK_B
UART7_RTS/
UART7_DE
PF8
PF9
TRACED12
TIM16_CH1N
-
-
-
SPI5_MISO
SAI1_SCK_B
Port F
TRACED13
TIM17_CH1N
-
-
-
-
-
-
SPI5_MOSI
SAI1_FS_B
UART7_CTS
PF10
PF11
PF12
-
TIM16_BKIN
SAI1_D3
SAI4_D4
-
SAI1_D4
-
-
-
-
-
-
-
-
-
-
SPI5_MOSI
-
-
-
TRACED4
DFSDM1_
DATIN6
DFSDM1_
DATIN3
PF13
TRACED5
-
-
I2C4_SMBA
I2C1_SMBA
-
DFSDM1_
CKIN6
PF14
PF15
PG0
TRACED6
TRACED7
TRACED0
-
-
-
-
-
-
I2C4_SCL
I2C4_SDA
-
I2C1_SCL
I2C1_SDA
-
-
-
-
-
-
-
-
DFSDM1_
DATIN0
Port G
PG1
PG2
TRACED1
TRACED2
-
-
-
-
-
-
-
-
-
-
-
-
MCO2
TIM8_BKIN
(1)
Table 8. Alternate function AF0 to AF7 (continued)
AF0
AF1
AF2
AF3
AF4
AF5
AF6
AF7
SPI1/I2S1/
SPI2/I2S2/
SPI3/I2S3/
SPI4/5/6/I2C1/
SDMMC1/3/
CEC
SPI2/I2S2/
SPI3/I2S3/
SPI6/
USART1/2/3/6/
UART7/
SAI4/I2C2/
TIM8/
LPTIM2/3/4/5/
DFSDM1
SAI4/
I2C1/2/3/4/5/
USART1/
TIM15/LPTIM2/
DFSDM1/CEC
SPI3/I2S3/
SAI1/3/4/
I2C4/UART4/
DFSDM1
TIM1/2/16/17/
HDP/SYS/RTC LPTIM1/SYS/
RTC
SAI1/4/I2C6/
TIM3/4/5/12/
HDP/SYS
Port
/SDMMC1
SDMMC2
DFSDM1_
CKIN1
PG3
TRACED3
-
-
TIM8_BKIN2
-
-
-
PG4
PG5
PG6
PG7
-
TIM1_BKIN2
TIM1_ETR
TIM17_BKIN
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
TRACED14
TRACED5
-
-
SAI1_MCLK_A
USART6_CK
TIM2_CH1/
TIM2_ETR
USART6_RTS/
USART6_DE
PG8
TRACED15
ETH_CLK
TIM8_ETR
-
SPI6_NSS
SAI4_D2
PG9
PG10
PG11
DBTRGO
TRACED10
TRACED11
-
-
-
-
-
-
-
-
-
-
-
-
-
-
USART6_RX
Port G
-
-
-
-
USART1_TX
UART4_TX
USART6_RTS/
USART6_DE
PG12
-
LPTIM1_IN1
-
-
-
SPI6_MISO
SAI4_CK2
USART6_CTS/
USART6_NSS
PG13
PG14
PG15
PH0
TRACED0
TRACED1
TRACED7
LPTIM1_OUT
SAI1_CK2
-
-
-
-
SAI4_CK1
-
SPI6_SCK
SPI6_MOSI
-
SAI1_SCK_A
SAI4_D1
LPTIM1_ETR
-
USART6_TX
USART6_CTS/
USART6_NSS
SAI1_D2
I2C2_SDA
SAI1_FS_A
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Port H PH1
PH2
-
LPTIM1_IN2
(1)
Table 8. Alternate function AF0 to AF7 (continued)
AF0
AF1
AF2
AF3
AF4
AF5
AF6
AF7
SPI1/I2S1/
SPI2/I2S2/
SPI3/I2S3/
SPI4/5/6/I2C1/
SDMMC1/3/
CEC
SPI2/I2S2/
SPI3/I2S3/
SPI6/
USART1/2/3/6/
UART7/
SAI4/I2C2/
TIM8/
LPTIM2/3/4/5/
DFSDM1
SAI4/
I2C1/2/3/4/5/
USART1/
TIM15/LPTIM2/
DFSDM1/CEC
SPI3/I2S3/
SAI1/3/4/
I2C4/UART4/
DFSDM1
TIM1/2/16/17/
HDP/SYS/RTC LPTIM1/SYS/
RTC
SAI1/4/I2C6/
TIM3/4/5/12/
HDP/SYS
Port
/SDMMC1
SDMMC2
DFSDM1_
CKIN4
PH3
-
-
-
-
-
-
-
PH4
PH5
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
I2C2_SCL
I2C2_SDA
I2C2_SMBA
I2C3_SCL
I2C3_SDA
I2C3_SMBA
I2C4_SMBA
I2C4_SCL
I2C4_SDA
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
SPI5_NSS
PH6
-
TIM12_CH1
-
SPI5_SCK
PH7
-
-
-
SPI5_MISO
PH8
-
TIM5_ETR
-
-
Port H
PH9
-
TIM12_CH2
-
-
PH10
PH11
PH12
PH13
PH14
PH15
-
TIM5_CH1
-
I2C1_SMBA
-
TIM5_CH2
-
I2C1_SCL
HDP2
TIM5_CH3
-
I2C1_SDA
-
-
-
-
-
-
TIM8_CH1N
TIM8_CH2N
TIM8_CH3N
-
-
-
-
-
SPI2_NSS/
I2S2_WS
PI0
PI1
PI2
PI3
-
-
-
-
-
-
-
-
TIM5_CH4
-
-
-
-
-
-
-
-
-
-
-
-
-
SPI2_SCK/
I2S2_CK
-
-
-
TIM8_BKIN2
TIM8_CH4
TIM8_ETR
Port I
SPI2_MISO/
I2S2_SDI
SPI2_MOSI/
I2S2_SDO
(1)
Table 8. Alternate function AF0 to AF7 (continued)
AF0
AF1
AF2
AF3
AF4
AF5
AF6
AF7
SPI1/I2S1/
SPI2/I2S2/
SPI3/I2S3/
SPI4/5/6/I2C1/
SDMMC1/3/
CEC
SPI2/I2S2/
SPI3/I2S3/
SPI6/
USART1/2/3/6/
UART7/
SAI4/I2C2/
TIM8/
LPTIM2/3/4/5/
DFSDM1
SAI4/
I2C1/2/3/4/5/
USART1/
TIM15/LPTIM2/
DFSDM1/CEC
SPI3/I2S3/
SAI1/3/4/
I2C4/UART4/
DFSDM1
TIM1/2/16/17/
HDP/SYS/RTC LPTIM1/SYS/
RTC
SAI1/4/I2C6/
TIM3/4/5/12/
HDP/SYS
Port
/SDMMC1
SDMMC2
PI4
PI5
PI6
PI7
PI8
PI9
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
TIM8_BKIN
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
TIM8_CH1
-
-
-
TIM8_CH2
-
-
-
TIM8_CH3
-
-
-
-
-
HDP1
-
-
-
Port I
PI10
PI11
PI12
PI13
PI14
PI15
PJ0
PJ1
PJ2
PJ3
PJ4
PJ5
PJ6
PJ7
HDP0
-
-
-
MCO1
-
-
I2S_CKIN
TRACED0
TRACED1
TRACECLK
-
HDP0
-
-
-
-
-
-
-
-
-
-
-
-
-
HDP1
-
-
-
-
-
TRACED8
TRACED9
TRACED10
TRACED11
TRACED12
TRACED2
TRACED3
TRACED13
-
-
-
-
-
-
-
-
Port J
-
-
HDP2
HDP3
-
-
TIM8_CH2
TIM8_CH2N
(1)
Table 8. Alternate function AF0 to AF7 (continued)
AF0
AF1
AF2
AF3
AF4
AF5
AF6
AF7
SPI1/I2S1/
SPI2/I2S2/
SPI3/I2S3/
SPI4/5/6/I2C1/
SDMMC1/3/
CEC
SPI2/I2S2/
SPI3/I2S3/
SPI6/
USART1/2/3/6/
UART7/
SAI4/I2C2/
TIM8/
LPTIM2/3/4/5/
DFSDM1
SAI4/
I2C1/2/3/4/5/
USART1/
TIM15/LPTIM2/
DFSDM1/CEC
SPI3/I2S3/
SAI1/3/4/
I2C4/UART4/
DFSDM1
TIM1/2/16/17/
HDP/SYS/RTC LPTIM1/SYS/
RTC
SAI1/4/I2C6/
TIM3/4/5/12/
HDP/SYS
Port
/SDMMC1
SDMMC2
PJ8
PJ9
TRACED14
TIM1_CH3N
-
TIM8_CH1
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
TRACED15
TIM1_CH3
-
TIM8_CH1N
-
PJ10
PJ11
PJ12
PJ13
PJ14
PJ15
PK0
PK1
PK2
PK3
PK4
PK5
PK6
PK7
-
TIM1_CH2N
-
TIM8_CH2
SPI5_MOSI
-
TIM1_CH2
-
TIM8_CH2N
SPI5_MISO
Port J
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
TIM1_CH1N
-
TIM8_CH3
SPI5_SCK
TRACED4
TIM1_CH1
HDP4
TIM8_CH3N
SPI5_NSS
TRACED5
TIM1_BKIN
HDP5
TIM8_BKIN
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Port K
-
-
TRACED6
TRACED7
-
HDP6
HDP7
-
SPI1_SCK/
I2S1_CK
PZ0
PZ1
-
-
-
-
I2C6_SCL
I2C6_SDA
I2C2_SCL
I2C2_SDA
-
-
USART1_CK
USART1_RX
Port Z
SPI1_MISO/
I2S1_SDI
I2C5_SDA
I2C4_SDA
(1)
Table 8. Alternate function AF0 to AF7 (continued)
AF0
AF1
AF2
AF3
AF4
AF5
AF6
AF7
SPI1/I2S1/
SPI2/I2S2/
SPI3/I2S3/
SPI4/5/6/I2C1/
SDMMC1/3/
CEC
SPI2/I2S2/
SPI3/I2S3/
SPI6/
USART1/2/3/6/
UART7/
SAI4/I2C2/
TIM8/
LPTIM2/3/4/5/
DFSDM1
SAI4/
I2C1/2/3/4/5/
USART1/
TIM15/LPTIM2/
DFSDM1/CEC
SPI3/I2S3/
SAI1/3/4/
I2C4/UART4/
DFSDM1
TIM1/2/16/17/
HDP/SYS/RTC LPTIM1/SYS/
RTC
SAI1/4/I2C6/
TIM3/4/5/12/
HDP/SYS
Port
/SDMMC1
SDMMC2
SPI1_MOSI/
I2S1_SDO
PZ2
-
-
I2C6_SCL
I2C2_SCL
I2C5_SMBA
I2C4_SMBA
USART1_TX
SPI1_NSS/
I2S1_WS
USART1_CTS/
USART1_NSS
PZ3
PZ4
PZ5
-
-
-
-
-
-
I2C6_SDA
I2C6_SCL
I2C6_SDA
I2C2_SDA
I2C2_SCL
I2C2_SDA
I2C5_SDA
I2C5_SCL
I2C5_SDA
I2C4_SDA
I2C4_SCL
I2C4_SDA
-
-
-
Port Z
USART1_RTS/
USART1_DE
PZ6
PZ7
-
-
-
-
I2C6_SCL
I2C6_SDA
I2C2_SCL
I2C2_SDA
USART1_CK
-
I2S1_MCK
-
I2C4_SMBA
-
USART1_RX
USART1_TX
1. Refer to Table 9 for AF8 to AF15.
(1)
Table 9. Alternate function AF8 to AF15
AF8
AF9
AF10
AF11
AF12
AF13
AF14
AF15
SYS
SAI2/4/
QUADSPI/
FMC/
SDMMC2/3/
OTG_FS/
OTG_HS
SPI6/SAI2/
USART3/
UART4/5/8/
SDMMC1/2/
SPDIFRX
FDCAN1/2/
TIM13/14/
QUADSPI/
SDMMC2/3/
LCD/SPDIFRX
DFSDM1/
QUADSPI/
SDMMC1/
MDIOS/ETH1/
DSI
SAI4/UART5/
FMC/SDMMC1/
MDIOS
Port
UART7/DCMI/
LCD/DSI/RNG
UART5/LCD
ETH1_GMII_
CRS/
ETH1_MII_CRS
PA0
PA1
UART4_TX
SDMMC2_CMD
SAI2_SD_B
-
-
-
-
-
EVENTOUT
EVENTOUT
ETH1_GMII_RX
_CLK/
ETH1_MII_RX_
CLK/
ETH1_RGMII_
RX_CLK/
QUADSPI_
BK1_IO3
UART4_RX
SAI2_MCLK_B
LCD_R2
ETH1_RMII_
REF_CLK
SDMMC2_
D0DIR
PA2
PA3
SAI2_SCK_B
-
-
ETH1_MDIO
MDIOS_MDIO
-
-
-
LCD_R1
LCD_B5
EVENTOUT
EVENTOUT
ETH1_GMII_
COL/
Port A
LCD_B2
-
ETH1_MII_COL
PA4
PA5
PA6
SPI6_NSS
SPI6_SCK
SPI6_MISO
-
-
-
-
-
SAI4_FS_A
SAI4_MCLK_A
SAI4_SCK_A
DCMI_HSYNC
LCD_VSYNC
LCD_R4
EVENTOUT
EVENTOUT
EVENTOUT
-
-
-
TIM13_CH1
MDIOS_MDC
DCMI_PIXCLK
LCD_G2
ETH1_GMII_RX
_DV/
ETH1_MII_RX_
DV/
ETH1_RGMII_
RX_CTL/
PA7
SPI6_MOSI
TIM14_CH1
QUADSPI_CLK
SAI4_SD_A
-
-
EVENTOUT
ETH1_RMII_
CRS_DV
(1)
Table 9. Alternate function AF8 to AF15 (continued)
AF8
AF9
AF10
AF11
AF12
AF13
AF14
AF15
SYS
SAI2/4/
QUADSPI/
FMC/
SDMMC2/3/
OTG_FS/
OTG_HS
SPI6/SAI2/
USART3/
UART4/5/8/
SDMMC1/2/
SPDIFRX
FDCAN1/2/
TIM13/14/
QUADSPI/
SDMMC2/3/
LCD/SPDIFRX
DFSDM1/
QUADSPI/
SDMMC1/
MDIOS/ETH1/
DSI
SAI4/UART5/
FMC/SDMMC1/
MDIOS
Port
UART7/DCMI/
LCD/DSI/RNG
UART5/LCD
SDMMC2_
CKIN
OTG_FS_SOF/
OTG_HS_SOF
PA8
PA9
SDMMC2_D4
-
-
-
SAI4_SD_B
-
UART7_RX
DCMI_D0
LCD_R6
LCD_R5
EVENTOUT
EVENTOUT
SDMMC2_
CDIR
SDMMC2_D5
PA10
PA11
PA12
PA13
PA14
-
-
-
-
-
-
-
MDIOS_MDIO
SAI4_FS_B
DCMI_D1
LCD_B1
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
-
FDCAN1_RX
-
-
-
-
-
-
-
-
-
-
-
-
LCD_R4
Port A
SAI2_FS_B
UART4_TX
-
FDCAN1_TX
LCD_R5
-
-
-
-
UART4_RTS/
UART4_DE
SDMMC2_
CDIR
PA15
SDMMC2_D5
SDMMC1_D5
SAI4_FS_A
UART7_TX
LCD_R1
EVENTOUT
ETH1_GMII_
RXD2/
ETH1_MII_
RXD2/
ETH1_RGMII_
RXD2
PB0
UART4_CTS
LCD_R3
-
-
MDIOS_MDIO
-
LCD_G1
EVENTOUT
ETH1_GMII_
RXD3/
ETH1_MII_
RXD3/
Port B
PB1
-
LCD_R6
MDIOS_MDC
-
LCD_G0
EVENTOUT
ETH1_RGMII_
RXD3
PB2
PB3
UART4_RX
SPI6_SCK
QUADSPI_CLK
SDMMC2_D2
-
-
-
-
-
-
-
-
EVENTOUT
EVENTOUT
SAI4_MCLK_A
UART7_RX
(1)
Table 9. Alternate function AF8 to AF15 (continued)
AF8
AF9
AF10
AF11
AF12
AF13
AF14
AF15
SYS
SAI2/4/
QUADSPI/
FMC/
SDMMC2/3/
OTG_FS/
OTG_HS
SPI6/SAI2/
USART3/
UART4/5/8/
SDMMC1/2/
SPDIFRX
FDCAN1/2/
TIM13/14/
QUADSPI/
SDMMC2/3/
LCD/SPDIFRX
DFSDM1/
QUADSPI/
SDMMC1/
MDIOS/ETH1/
DSI
SAI4/UART5/
FMC/SDMMC1/
MDIOS
Port
UART7/DCMI/
LCD/DSI/RNG
UART5/LCD
PB4
SPI6_MISO
SPI6_MOSI
SDMMC2_D3
FDCAN2_RX
-
-
SAI4_SCK_A
UART5_RX
UART7_TX
DCMI_D10
-
EVENTOUT
EVENTOUT
ETH1_PPS_
OUT
PB5
PB6
PB7
SAI4_SD_A
LCD_G7
QUADSPI_BK1
_NCS
DFSDM1_
DATIN5
-
-
FDCAN2_TX
-
UART5_TX
FMC_NL
DCMI_D5
-
-
EVENTOUT
EVENTOUT
DFSDM1_
CKIN5
SDMMC2_D1
DCMI_VSYNC
ETH1_GMII_
TXD3/
ETH1_MII_
TXD3/
ETH1_RGMII_
TXD3
PB8
UART4_RX
FDCAN1_RX
FDCAN1_TX
SDMMC2_D4
SDMMC1_D4
DCMI_D6
LCD_B6
EVENTOUT
Port B
SDMMC1_CDI
R
PB9
UART4_TX
-
SDMMC2_D5
-
SDMMC1_D5
-
DCMI_D7
-
LCD_B7
LCD_G4
EVENTOUT
EVENTOUT
ETH1_GMII_
RX_ER/
ETH1_MII_
RX_ER
QUADSPI_
BK1_NCS
PB10
ETH1_GMII_
TX_EN/
ETH1_MII_
TX_EN/
ETH1_RGMII_
TX_CTL/
PB11
-
-
-
-
DSI_TE
LCD_G5
EVENTOUT
ETH1_RMII_
TX_EN
(1)
Table 9. Alternate function AF8 to AF15 (continued)
AF8
AF9
AF10
AF11
AF12
AF13
AF14
AF15
SYS
SAI2/4/
QUADSPI/
FMC/
SDMMC2/3/
OTG_FS/
OTG_HS
SPI6/SAI2/
USART3/
UART4/5/8/
SDMMC1/2/
SPDIFRX
FDCAN1/2/
TIM13/14/
QUADSPI/
SDMMC2/3/
LCD/SPDIFRX
DFSDM1/
QUADSPI/
SDMMC1/
MDIOS/ETH1/
DSI
SAI4/UART5/
FMC/SDMMC1/
MDIOS
Port
UART7/DCMI/
LCD/DSI/RNG
UART5/LCD
ETH1_GMII_
TXD0/
ETH1_MII_
TXD0/
ETH1_RGMII_
TXD0/
PB12 USART3_RX
FDCAN2_RX
-
-
-
UART5_RX
EVENTOUT
ETH1_RMII_
TXD0
ETH1_GMII_
TXD1/
Port B
ETH1_MII_
TXD1/
ETH1_RGMII_
TXD1/
PB13
-
FDCAN2_TX
-
-
-
UART5_TX
EVENTOUT
ETH1_RMII_
TXD1
PB14
PB15
-
-
SDMMC2_D0
SDMMC2_D1
-
-
-
-
-
-
-
-
-
-
EVENTOUT
EVENTOUT
QUADSPI_BK2
_NCS
PC0
PC1
SAI2_FS_B
-
-
-
-
-
-
LCD_R5
-
EVENTOUT
EVENTOUT
SDMMC2_CK
-
ETH1_MDC
MDIOS_MDC
ETH1_GMII_
TXD2/
Port C
ETH1_MII_
TXD2/
PC2
-
-
-
-
DCMI_PIXCLK
-
EVENTOUT
ETH1_RGMII_
TXD2
(1)
Table 9. Alternate function AF8 to AF15 (continued)
AF8
AF9
AF10
AF11
AF12
AF13
AF14
AF15
SYS
SAI2/4/
QUADSPI/
FMC/
SDMMC2/3/
OTG_FS/
OTG_HS
SPI6/SAI2/
USART3/
UART4/5/8/
SDMMC1/2/
SPDIFRX
FDCAN1/2/
TIM13/14/
QUADSPI/
SDMMC2/3/
LCD/SPDIFRX
DFSDM1/
QUADSPI/
SDMMC1/
MDIOS/ETH1/
DSI
SAI4/UART5/
FMC/SDMMC1/
MDIOS
Port
UART7/DCMI/
LCD/DSI/RNG
UART5/LCD
ETH1_GMII_
TX_CLK/
ETH1_MII_
TX_CLK
PC3
-
-
-
-
-
-
-
-
-
-
-
EVENTOUT
EVENTOUT
ETH1_GMII_
RXD0/
ETH1_MII_
RXD0/
ETH1_RGMII_
RXD0/
PC4
SPDIFRX_IN3
ETH1_RMII_
RXD0
ETH1_GMII_
RXD1/
ETH1_MII_
RXD1/
ETH1_RGMII_
RXD1/
Port C
PC5
-
SPDIFRX_IN4
-
SAI4_D3
-
-
EVENTOUT
ETH1_RMII_
RXD1
SDMMC1_
D0DIR
SDMMC2_
D0DIR
PC6
PC7
PC8
PC9
SDMMC2_D6
DSI_TE
SDMMC1_D6
SDMMC1_D7
SDMMC1_D0
SDMMC1_D1
DCMI_D0
DCMI_D1
DCMI_D2
DCMI_D3
LCD_HSYNC
LCD_G6
-
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
SDMMC1_
D123DIR
SDMMC2_
D123DIR
SDMMC2_D7
-
-
-
UART5_RTS/
UART5_DE
-
-
-
QUADSPI_BK1
_IO0
UART5_CTS
LCD_B2
(1)
Table 9. Alternate function AF8 to AF15 (continued)
AF8
AF9
AF10
AF11
AF12
AF13
AF14
AF15
SYS
SAI2/4/
QUADSPI/
FMC/
SDMMC2/3/
OTG_FS/
OTG_HS
SPI6/SAI2/
USART3/
UART4/5/8/
SDMMC1/2/
SPDIFRX
FDCAN1/2/
TIM13/14/
QUADSPI/
SDMMC2/3/
LCD/SPDIFRX
DFSDM1/
QUADSPI/
SDMMC1/
MDIOS/ETH1/
DSI
SAI4/UART5/
FMC/SDMMC1/
MDIOS
Port
UART7/DCMI/
LCD/DSI/RNG
UART5/LCD
QUADSPI_
BK1_IO1
PC10
UART4_TX
UART4_RX
SAI4_MCLK_B
SAI4_SCK_B
-
-
SDMMC1_D2
SDMMC1_D3
DCMI_D8
DCMI_D4
LCD_R2
-
EVENTOUT
EVENTOUT
QUADSPI_
BK2_NCS
PC11
Port C
PC12
PC13
PC14
PC15
UART5_TX
-
-
-
-
SAI4_SD_B
-
-
-
-
SDMMC1_CK
DCMI_D9
-
-
-
-
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
-
-
-
-
-
-
-
-
-
-
-
-
(1)
Table 9. Alternate function AF8 to AF15 (continued)
AF8
AF9
AF10
AF11
AF12
AF13
AF14
AF15
SYS
SAI2/4/
QUADSPI/
FMC/
SDMMC2/3/
OTG_FS/
OTG_HS
SPI6/SAI2/
USART3/
UART4/5/8/
SDMMC1/2/
SPDIFRX
FDCAN1/2/
TIM13/14/
QUADSPI/
SDMMC2/3/
LCD/SPDIFRX
DFSDM1/
QUADSPI/
SDMMC1/
MDIOS/ETH1/
DSI
SAI4/UART5/
FMC/SDMMC1/
MDIOS
Port
UART7/DCMI/
LCD/DSI/RNG
UART5/LCD
DFSDM1_
DATIN7
FMC_AD2/
FMC_D2
PD0
UART4_RX
FDCAN1_RX SDMMC3_CMD
-
-
EVENTOUT
DFSDM1_
CKIN7
FMC_AD3/
FMC_D3
PD1
PD2
PD3
UART4_TX
UART5_RX
FDCAN1_TX
SDMMC3_D0
-
-
-
EVENTOUT
EVENTOUT
EVENTOUT
-
-
SDMMC1_CMD
FMC_CLK
DCMI_D11
DCMI_D5
-
SDMMC1_
D123DIR
SDMMC2_
D123DIR
SDMMC2_D7
SDMMC1_D7
LCD_G7
DFSDM1_
CKIN0
PD4
-
-
SDMMC3_D1
FMC_NOE
-
-
EVENTOUT
Port D
PD5
PD6
PD7
-
-
-
-
SDMMC3_D2
-
-
-
FMC_NWE
FMC_NWAIT
FMC_NE1
-
-
EVENTOUT
EVENTOUT
EVENTOUT
-
-
DCMI_D10
-
LCD_B2
-
SPDIFRX_IN1
SDMMC3_D3
FMC_AD13/
FMC_D13
PD8
PD9
-
-
SPDIFRX_IN2
-
-
-
-
-
-
LCD_B7
LCD_B0
EVENTOUT
EVENTOUT
FMC_AD14/
FMC_D14
DCMI_HSYNC
(1)
Table 9. Alternate function AF8 to AF15 (continued)
AF8
AF9
AF10
AF11
AF12
AF13
AF14
AF15
SYS
SAI2/4/
QUADSPI/
FMC/
SDMMC2/3/
OTG_FS/
OTG_HS
SPI6/SAI2/
USART3/
UART4/5/8/
SDMMC1/2/
SPDIFRX
FDCAN1/2/
TIM13/14/
QUADSPI/
SDMMC2/3/
LCD/SPDIFRX
DFSDM1/
QUADSPI/
SDMMC1/
MDIOS/ETH1/
DSI
SAI4/UART5/
FMC/SDMMC1/
MDIOS
Port
UART7/DCMI/
LCD/DSI/RNG
UART5/LCD
FMC_AD15/
FMC_D15
PD10
-
-
-
-
-
-
-
-
-
-
-
-
-
LCD_B3
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
QUADSPI_
BK1_IO0
FMC_A16/
FMC_CLE
PD11
PD12
PD13
SAI2_SD_A
-
-
QUADSPI_
BK1_IO1
FMC_A17/FMC
_ALE
SAI2_FS_A
-
-
Port D
QUADSPI_
BK1_IO3
SAI2_SCK_A
FMC_A18
DSI_TE
-
FMC_AD0/
FMC_D0
PD14 UART8_CTS
PD15 UART8_CTS
-
-
-
-
-
-
-
FMC_AD1/
FMC_D1
LCD_R1
(1)
Table 9. Alternate function AF8 to AF15 (continued)
AF8
AF9
AF10
AF11
AF12
AF13
AF14
AF15
SYS
SAI2/4/
QUADSPI/
FMC/
SDMMC2/3/
OTG_FS/
OTG_HS
SPI6/SAI2/
USART3/
UART4/5/8/
SDMMC1/2/
SPDIFRX
FDCAN1/2/
TIM13/14/
QUADSPI/
SDMMC2/3/
LCD/SPDIFRX
DFSDM1/
QUADSPI/
SDMMC1/
MDIOS/ETH1/
DSI
SAI4/UART5/
FMC/SDMMC1/
MDIOS
Port
UART7/DCMI/
LCD/DSI/RNG
UART5/LCD
PE0
UART8_RX
UART8_TX
-
-
SAI2_MCLK_A
-
-
-
FMC_NBL0
FMC_NBL1
DCMI_D2
DCMI_D3
-
-
EVENTOUT
EVENTOUT
PE1
ETH1_GMII_
TXD3/
QUADSPI_
BK1_IO2
ETH1_MII_
TXD3/
ETH1_RGMII_
TXD3
PE2
-
-
-
FMC_A23
-
-
EVENTOUT
Port E
PE3
PE4
SDMMC2_CK
SDMMC2_D4
-
-
-
FMC_A19
FMC_A20
-
-
EVENTOUT
EVENTOUT
SDMMC1_
CKIN
SDMMC1_D4
DCMI_D4
LCD_B0
SDMMC1_
D0DIR
PE5
PE6
SDMMC2_D6
-
-
SDMMC1_D6
-
FMC_A21
FMC_A22
DCMI_D6
DCMI_D7
LCD_G0
LCD_G1
EVENTOUT
EVENTOUT
SDMMC1_D2
SAI2_MCLK_B
(1)
Table 9. Alternate function AF8 to AF15 (continued)
AF8
AF9
AF10
AF11
AF12
AF13
AF14
AF15
SYS
SAI2/4/
QUADSPI/
FMC/
SDMMC2/3/
OTG_FS/
OTG_HS
SPI6/SAI2/
USART3/
UART4/5/8/
SDMMC1/2/
SPDIFRX
FDCAN1/2/
TIM13/14/
QUADSPI/
SDMMC2/3/
LCD/SPDIFRX
DFSDM1/
QUADSPI/
SDMMC1/
MDIOS/ETH1/
DSI
SAI4/UART5/
FMC/SDMMC1/
MDIOS
Port
UART7/DCMI/
LCD/DSI/RNG
UART5/LCD
QUADSPI_
BK2_IO0
FMC_AD4/
FMC_D4
PE7
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
QUADSPI_
BK2_IO1
FMC_AD5/
FMC_D5
PE8
PE9
-
-
-
QUADSPI_
BK2_IO2
FMC_AD6/
FMC_D6
-
-
-
QUADSPI_
BK2_IO3
FMC_AD7/
FMC_D7
PE10
-
-
-
LCD_G3
LCD_B4
LCD_DE
LCD_CLK
LCD_R7
-
FMC_AD8/
FMC_D8
Port E PE11
PE12
-
SAI2_SD_B
SAI2_SCK_B
SAI2_FS_B
DCMI_D4
SDMMC1_
D0DIR
FMC_AD9/
FMC_D9
-
-
FMC_AD10/
FMC_D10
PE13
-
-
DCMI_D6
UART8_RTS/
UART8_DE
SDMMC1_
D123DIR
FMC_AD11/
FMC_D11
PE14
-
SAI2_MCLK_B
FMC_NCE2
LCD_G0
FMC_AD12/
FMC_D12
PE15 UART8_CTS
-
-
-
-
-
-
-
-
SDMMC3_
CKIN
PF0
Port F PF1
PF2
-
-
-
SDMMC3_D0
SDMMC3_CMD
FMC_A0
FMC_A1
FMC_A2
SDMMC3_
CDIR
-
SDMMC2_
D0DIR
SDMMC3_
D0DIR
SDMMC1_
D0DIR
-
(1)
Table 9. Alternate function AF8 to AF15 (continued)
AF8
AF9
AF10
AF11
AF12
AF13
AF14
AF15
SYS
SAI2/4/
QUADSPI/
FMC/
SDMMC2/3/
OTG_FS/
OTG_HS
SPI6/SAI2/
USART3/
UART4/5/8/
SDMMC1/2/
SPDIFRX
FDCAN1/2/
TIM13/14/
QUADSPI/
SDMMC2/3/
LCD/SPDIFRX
DFSDM1/
QUADSPI/
SDMMC1/
MDIOS/ETH1/
DSI
SAI4/UART5/
FMC/SDMMC1/
MDIOS
Port
UART7/DCMI/
LCD/DSI/RNG
UART5/LCD
ETH1_GMII_
TX_ER
PF3
-
-
-
FMC_A3
-
-
EVENTOUT
SDMMC3_
D123DIR
PF4
PF5
PF6
-
-
-
SDMMC3_D1
SDMMC3_D2
-
-
-
FMC_A4
FMC_A5
-
-
-
-
-
-
EVENTOUT
EVENTOUT
EVENTOUT
-
-
QUADSPI_
BK1_IO3
SAI4_SCK_B
QUADSPI_
BK1_IO2
PF7
PF8
PF9
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
EVENTOUT
EVENTOUT
EVENTOUT
QUADSPI_
BK1_IO0
TIM13_CH1
TIM14_CH1
Port F
QUADSPI_
BK1_IO1
PF10
PF11
-
-
QUADSPI_CLK
-
-
-
-
SAI4_D3
-
DCMI_D11
DCMI_D12
LCD_DE
LCD_G5
EVENTOUT
EVENTOUT
SAI2_SD_B
ETH1_GMII_
RXD4
PF12
PF13
PF14
-
-
-
-
-
-
-
-
-
-
-
-
FMC_A6
FMC_A7
FMC_A8
FMC_A9
-
-
-
-
-
-
-
-
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
ETH1_GMII_
RXD5
ETH1_GMII_
RXD6
ETH1_GMII_
RXD7
Port F PF15
(1)
Table 9. Alternate function AF8 to AF15 (continued)
AF8
AF9
AF10
AF11
AF12
AF13
AF14
AF15
SYS
SAI2/4/
QUADSPI/
FMC/
SDMMC2/3/
OTG_FS/
OTG_HS
SPI6/SAI2/
USART3/
UART4/5/8/
SDMMC1/2/
SPDIFRX
FDCAN1/2/
TIM13/14/
QUADSPI/
SDMMC2/3/
LCD/SPDIFRX
DFSDM1/
QUADSPI/
SDMMC1/
MDIOS/ETH1/
DSI
SAI4/UART5/
FMC/SDMMC1/
MDIOS
Port
UART7/DCMI/
LCD/DSI/RNG
UART5/LCD
ETH1_GMII_
TXD4
PG0
-
-
-
-
-
-
-
-
-
-
-
-
FMC_A10
FMC_A11
FMC_A12
FMC_A13
-
-
-
-
-
-
-
-
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
ETH1_GMII_
TXD5
PG1
PG2
PG3
ETH1_GMII_
TXD6
ETH1_GMII_
TXD7
ETH1_GMII_
GTX_CLK/
ETH1_RGMII_
GTX_CLK
PG4
PG5
-
-
-
-
-
FMC_A14
FMC_A15
-
-
-
-
EVENTOUT
EVENTOUT
Port G
ETH1_GMII_
CLK125/
ETH1_RGMII_
CLK125
-
-
PG6
PG7
-
SDMMC2_CMD
-
-
-
-
DCMI_D12
DCMI_D13
LCD_R7
EVENTOUT
EVENTOUT
UART8_RTS/
UART8_DE
QUADSPI_
BK2_IO3
QUADSPI_CLK
LCD_CLK
USART3_RTS/
USART3_DE
ETH1_PPS_
OUT
PG8
SPDIFRX_IN3
SAI4_FS_A
SAI2_FS_B
-
-
LCD_G7
LCD_R1
EVENTOUT
EVENTOUT
QUADSPI_
BK2_IO2
FMC_NE2/FMC
_NCE
PG9 SPDIFRX_IN4
-
DCMI_VSYNC
(1)
Table 9. Alternate function AF8 to AF15 (continued)
AF8
AF9
AF10
AF11
AF12
AF13
AF14
AF15
SYS
SAI2/4/
QUADSPI/
FMC/
SDMMC2/3/
OTG_FS/
OTG_HS
SPI6/SAI2/
USART3/
UART4/5/8/
SDMMC1/2/
SPDIFRX
FDCAN1/2/
TIM13/14/
QUADSPI/
SDMMC2/3/
LCD/SPDIFRX
DFSDM1/
QUADSPI/
SDMMC1/
MDIOS/ETH1/
DSI
SAI4/UART5/
FMC/SDMMC1/
MDIOS
Port
UART7/DCMI/
LCD/DSI/RNG
UART5/LCD
QUADSPI_
BK2_IO2
PG10 UART8_CTS
PG11 SPDIFRX_IN1
PG12 SPDIFRX_IN2
LCD_G3
SAI2_SD_B
FMC_NE3
DCMI_D2
LCD_B2
LCD_B3
LCD_B1
LCD_R0
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
ETH1_GMII_
TX_EN/
ETH1_MII_
TX_EN/
ETH1_RGMII_
TX_CTL/
ETH1_RMII_
TX_EN
-
-
-
DCMI_D3
ETH1_PHY_
INTN
LCD_B4
SAI4_SCK_A
SAI4_MCLK_A
FMC_NE4
FMC_A24
-
-
ETH1_GMII_
TXD0/
ETH1_MII_
TXD0/
ETH1_RGMII_
TXD0/
Port G
PG13
-
-
ETH1_RMII_
TXD0
ETH1_GMII_
TXD1/
ETH1_MII_
TXD1/
ETH1_RGMII_
TXD1/
QUADSPI_
BK2_IO3
PG14
-
SAI4_SD_A
FMC_A25
-
LCD_B0
EVENTOUT
ETH1_RMII_
TXD1
(1)
Table 9. Alternate function AF8 to AF15 (continued)
AF8
AF9
AF10
AF11
AF12
AF13
AF14
AF15
SYS
SAI2/4/
QUADSPI/
FMC/
SDMMC2/3/
OTG_FS/
OTG_HS
SPI6/SAI2/
USART3/
UART4/5/8/
SDMMC1/2/
SPDIFRX
FDCAN1/2/
TIM13/14/
QUADSPI/
SDMMC2/3/
LCD/SPDIFRX
DFSDM1/
QUADSPI/
SDMMC1/
MDIOS/ETH1/
DSI
SAI4/UART5/
FMC/SDMMC1/
MDIOS
Port
UART7/DCMI/
LCD/DSI/RNG
UART5/LCD
Port G PG15
PH0
-
-
-
-
-
-
SDMMC3_CK
-
-
-
-
-
-
DCMI_D13
-
-
-
EVENTOUT
EVENTOUT
EVENTOUT
-
-
-
-
PH1
ETH1_GMII_
CRS/
ETH1_MII_CRS
QUADSPI_
BK2_IO0
PH2
PH3
-
-
SAI2_SCK_B
-
-
-
-
LCD_R0
LCD_R1
EVENTOUT
EVENTOUT
ETH1_GMII_
COL/
ETH1_MII_COL
QUADSPI_
BK2_IO1
SAI2_MCLK_B
PH4
PH5
-
-
LCD_G5
-
-
-
-
-
-
-
-
LCD_G4
-
EVENTOUT
EVENTOUT
SAI4_SD_B
Port H
ETH1_GMII_
RXD2/
ETH1_MII_
RXD2/
PH6
-
-
-
MDIOS_MDIO
DCMI_D8
-
EVENTOUT
ETH1_RGMII_
RXD2
ETH1_GMII_
RXD3/
ETH1_MII_
RXD3/
ETH1_RGMII_
RXD3
PH7
PH8
-
-
-
-
-
-
MDIOS_MDC
DCMI_D9
-
EVENTOUT
EVENTOUT
-
-
DCMI_HSYNC
LCD_R2
(1)
Table 9. Alternate function AF8 to AF15 (continued)
AF8
AF9
AF10
AF11
AF12
AF13
AF14
AF15
SYS
SAI2/4/
QUADSPI/
FMC/
SDMMC2/3/
OTG_FS/
OTG_HS
SPI6/SAI2/
USART3/
UART4/5/8/
SDMMC1/2/
SPDIFRX
FDCAN1/2/
TIM13/14/
QUADSPI/
SDMMC2/3/
LCD/SPDIFRX
DFSDM1/
QUADSPI/
SDMMC1/
MDIOS/ETH1/
DSI
SAI4/UART5/
FMC/SDMMC1/
MDIOS
Port
UART7/DCMI/
LCD/DSI/RNG
UART5/LCD
PH9
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
DCMI_D0
DCMI_D1
DCMI_D2
DCMI_D3
-
LCD_R3
LCD_R4
LCD_R5
LCD_R6
LCD_G2
LCD_G3
LCD_G4
LCD_G5
LCD_G6
LCD_G7
-
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
PH10
PH11
Port H PH12
PH13
PH14
PH15
PI0
-
-
-
-
-
-
-
-
-
UART4_TX
FDCAN1_TX
-
UART4_RX
FDCAN1_RX
-
DCMI_D4
DCMI_D11
DCMI_D13
DCMI_D8
DCMI_D9
DCMI_D10
DCMI_D5
DCMI_VSYNC
DCMI_D6
DCMI_D7
-
-
-
-
-
-
-
PI1
-
-
-
PI2
-
-
-
PI3
-
-
-
PI4
-
-
SAI2_MCLK_A
SAI2_SCK_A
SAI2_SD_A
SAI2_FS_A
-
LCD_B4
LCD_B5
LCD_B6
LCD_B7
-
PI5
-
-
Port I
PI6
PI7
PI8
PI9
-
-
-
-
-
-
UART4_RX
FDCAN1_RX
-
-
LCD_VSYNC
ETH1_GMII_
RX_ER/
ETH1_MII_
RX_ER
USART3_CTS/
USART3_NSS
PI10
-
-
-
-
LCD_HSYNC
EVENTOUT
(1)
Table 9. Alternate function AF8 to AF15 (continued)
AF8
AF9
AF10
AF11
AF12
AF13
AF14
AF15
SYS
SAI2/4/
QUADSPI/
FMC/
SDMMC2/3/
OTG_FS/
OTG_HS
SPI6/SAI2/
USART3/
UART4/5/8/
SDMMC1/2/
SPDIFRX
FDCAN1/2/
TIM13/14/
QUADSPI/
SDMMC2/3/
LCD/SPDIFRX
DFSDM1/
QUADSPI/
SDMMC1/
MDIOS/ETH1/
DSI
SAI4/UART5/
FMC/SDMMC1/
MDIOS
Port
UART7/DCMI/
LCD/DSI/RNG
UART5/LCD
PI11
-
LCD_G6
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
PI12
Port I PI13
PI14
-
-
-
LCD_HSYNC
LCD_VSYNC
LCD_CLK
LCD_R0
LCD_R1
LCD_R2
LCD_R3
LCD_R4
LCD_R5
LCD_R6
LCD_R7
LCD_G0
LCD_G1
LCD_G2
LCD_G3
LCD_G4
LCD_B0
LCD_B1
LCD_B2
-
-
-
-
-
-
PI15
-
LCD_G2
-
PJ0
-
LCD_R7
-
PJ1
-
-
-
PJ2
-
-
DSI_TE
PJ3
-
-
-
-
-
-
-
-
-
-
-
-
-
-
PJ4
-
-
PJ5
-
-
PJ6
-
-
Port J PJ7
PJ8
-
-
UART8_TX
-
PJ9
UART8_RX
-
PJ10
-
-
-
-
-
-
PJ11
-
PJ12
LCD_G3
LCD_G4
-
PJ13
PJ14
(1)
Table 9. Alternate function AF8 to AF15 (continued)
AF8
AF9
AF10
AF11
AF12
AF13
AF14
AF15
SYS
SAI2/4/
QUADSPI/
FMC/
SDMMC2/3/
OTG_FS/
OTG_HS
SPI6/SAI2/
USART3/
UART4/5/8/
SDMMC1/2/
SPDIFRX
FDCAN1/2/
TIM13/14/
QUADSPI/
SDMMC2/3/
LCD/SPDIFRX
DFSDM1/
QUADSPI/
SDMMC1/
MDIOS/ETH1/
DSI
SAI4/UART5/
FMC/SDMMC1/
MDIOS
Port
UART7/DCMI/
LCD/DSI/RNG
UART5/LCD
Port J PJ15
PK0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
LCD_B3
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
-
LCD_G5
PK1
-
LCD_G6
PK2
-
LCD_G7
PK3
Port K
-
LCD_B4
PK4
-
LCD_B5
PK5
PK6
PK7
PZ0
PZ1
PZ2
-
LCD_B6
-
LCD_B7
-
LCD_DE
SPI6_SCK
-
-
-
-
-
-
-
-
SPI6_MISO
SPI6_MOSI
PZ3
Port Z
SPI6_NSS
PZ4
-
-
-
-
PZ5
PZ6
PZ7
1. Refer to Table 8 for AF0 to AF7.
Memory mapping
STM32MP157C/F
5
Memory mapping
Refer to the product line reference manual for details on the memory mapping as well as the
boundary addresses for all peripherals.
122/260
DS12505 Rev 5
STM32MP157C/F
Electrical characteristics
6
Electrical characteristics
6.1
Parameter conditions
Unless otherwise specified, all voltages are referenced to V
.
SS
6.1.1
Minimum and maximum values
Unless otherwise specified the minimum and maximum values are guaranteed in the worst
conditions of junction temperature, supply voltage and frequencies by tests in production on
100% of the devices with an junction temperature at T = 25 °C and T = T (given by the
J
J
Jmax
selected temperature range).
Data based on characterization results, design simulation and/or technology characteristics
are indicated in the table footnotes and are not tested in production. Based on
characterization, the minimum and maximum values refer to sample tests and represent the
mean value plus or minus three times the standard deviation (mean±3σ).
6.1.2
6.1.3
Typical values
Unless otherwise specified, typical data are based on T = 25 °C, V = 3.3 V, V
1.2 V. They are given only as design guidelines and are not tested.
=
J
DD
DDCORE
Typical ADC accuracy values are determined by characterization of a batch of samples from
a standard diffusion lot over the full temperature range, where 95% of the devices have an
error less than or equal to the value indicated (mean±2σ).
Typical curves
Unless otherwise specified, all typical curves are given only as design guidelines and are
not tested.
6.1.4
6.1.5
Loading capacitor
The loading conditions used for pin parameter measurement are shown in Figure 9.
Pin input voltage
The input voltage measurement on a pin of the device is described in Figure 10.
Figure 9. Pin loading conditions
Figure 10. Pin input voltage
Device pin
Device pin
VIN
C = 50 pF
MSv47493V1
MSv47494V1
DS12505 Rev 5
123/260
238
Electrical characteristics
STM32MP157C/F
6.1.6
Power supply scheme
Figure 11. Power supply scheme
USB FS
IOs
DDR
PHY
USB HS
PHY
1V8
DSI
regulator
1V1
regulator
VSS
DSI PHY
VSS_DSI
regulator
VSS
VSS
VSS
DSI
PLL
Core domain
VDDCORE
VSS
(MPU,
peripherals,
RAM)
(MCU,
peripherals,
RAM)
IO
logic
IOs
IOports
(System logic, Peripherals)
VDD (VDD_ANA
)
VDD
HSI, CSI, HSE,
LSI, WKUP,
IWDG
VSW domain
VDD
IOs
IO
logic
Retention domain
Retention
regulator
IOports
Power switch
VRET
VSS
VSW
Retention
RAM
Backup domain
Power switch
VBAT
VDD_PLL
VSS_PLL
Backup
regulator
PLLs
VBKP
VDD domain
Backup RAM
LSE, RTC, AWU,
Tamper, backup
registers, Reset
BKUP
IOs
IO
IOports
VDDA
logic
VSS
VSS
Analog domain
REF_BUF
ADC, DAC
VREF+
VREF+
VREF-
VSSA
VREF-
MSv46507V2
Caution:
Each power supply pair (V /V , V
/V , V
/V
...) must be decoupled with
DD SS
DDCORE SS
DDA SSA
filtering ceramic capacitors. These capacitors must be placed as close as possible to, or
below, the appropriate pins on the underside of the PCB to ensure good operation of the
124/260
DS12505 Rev 5
STM32MP157C/F
Electrical characteristics
device. It is not recommended to remove filtering capacitors to reduce PCB size or cost.
This might cause incorrect operation of the device.
The number of needed capacitances and their values are provided in AN5031 “Getting
started with STM32MP1 Series hardware development” available from the ST website
www.st.com.
6.1.7
Current consumption measurement
Figure 12. Current consumption measurement scheme
IDD_CORE
VDDCORE
IDD_VBAT
VBAT
IDD
VDD
VDDA
VDD_ANA
VDD_PLL
MSv50921V2
6.2
Absolute maximum ratings
Stresses above the absolute maximum ratings listed in Table 10: Voltage characteristics,
Table 11: Current characteristics, and Table 12: Thermal characteristics may cause
permanent damage to the device. These are stress ratings only and the functional operation
of the device at these conditions is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability. Device mission profile (application conditions)
is compliant with JEDEC JESD47 qualification standard, extended mission profiles are
available on demand.
(1)
Table 10. Voltage characteristics
Symbols
Ratings
Min
Max
Unit
External main supply voltage (including VDD
,
V
DDX - VSSX VDD_ANA, VDD_PLL, VDD_DSI, VDDA
,
-0.3
3.9
V
VDD3V3_USB, VBAT, VREF+
)
VDDCORE
VSS
-
External core supply voltage
DDR IO supply voltage
-0.3
-0.3
-0.3
1.5
1.98
3.9
V
V
V
VDDA_DDR
VSS
-
VDDA1V8
VSS
-
1.8 V supply (including VDDA1V8_REG
,
VDDA1V8_DSI
)
DS12505 Rev 5
125/260
238
Electrical characteristics
Symbols
STM32MP157C/F
(1)
Table 10. Voltage characteristics (continued)
Ratings
Min
Max
Unit
VDDA1V2
VSS
-
1.2 V supply (including VDDA1V2_DSI_REG,
-0.3
1.98
V
VDDA1V2_DSI_PHY
)
Min(VDD, VDDA
,
Input voltage on FT_xxx pins
VDD3V3_USB
,
V
VBAT) +3.9(3)(4)
Input voltage on TT_xx pins
3.9
6.0(5)
5.25
5.5(5)
3.9
V
V
V
V
V
(2)
VIN
VSS - 0.3
Input voltage on OTG_VBUS pin
Input voltage on USB/OTG_HS_DP/DM pins
Input voltage on OTG_FS_DP/DM pins
Input voltage on any other pins
Variations between different VDDX power pins of
the same domain
|∆VDDX
|
-
50
mV
|VSSx-VSS
|
Variations between all the different ground pins
-
-
50
mV
V
VREF+ - VDDA Allowed voltage difference for VREF+ > VDDA
0.4
1. All power (VDD, VDDA, VDD3V3_USB, VDDCORE, VBAT) and ground (VSS, VSSA, VSSX) pins must always be
connected to the external/internal power supply, in the permitted range.
2. VIN maximum must always be respected. Refer to Table 51 for the maximum allowed injected current
values.
3. This formula has to be applied on power supplies related to the IO structure described by the pin definition
table.
4. To sustain a voltage higher than 3.9 V the internal pull-up/pull-down resistors must be disabled.
5. Voltage should be also below Min(VDD, VDD3V3_USBFS) + 3.9 V
Table 11. Current characteristics
Symbols
ΣIVDD
Ratings
Max
Unit
Total current into sum of all VDD power lines (source)(1)
Total current out of sum of all VSS ground lines (sink)(1)
Maximum current into each VDD power pin (source)(1)
Maximum current out of each VSS ground pin (sink)(1)
Output current sunk by any I/O and control pin
440
440
100
100
20
ΣIVSS
IVDD
IVSS
IIO
mA
Total output current sunk by sum of all I/Os and control pins(2)
Total output current sourced by sum of all I/Os and control pins(2)
Injected current on FT_xxx, TT_xx, NRST pins except PA4, PA5
Injected current on PA4, PA5
140
140
-5/+0
-0/0
±25
ΣI(PIN)
(3)(4)
IINJ(PIN)
ΣIINJ(PIN)
Total injected current (sum of all I/Os and control pins)(5)
1. All power (VDD, VDDA, VDD3V3_USB, VDDCORE) and ground (VSS, VSSA, VSSX) pins must always be
connected to the external/internal power supply, in the permitted range.
2. This current consumption must be correctly distributed over all I/Os and control pins. The total output
current must not be sunk/sourced between two consecutive power supply pins.
3. Positive injection is not possible on these I/Os and does not occur for input voltages lower than the
specified maximum value.
126/260
DS12505 Rev 5
STM32MP157C/F
Electrical characteristics
4. A positive injection is induced by VIN>VDD while a negative injection is induced by VIN<VSS. IINJ(PIN) must
never be exceeded. Refer also to Table 10: Voltage characteristics for the maximum allowed input voltage
values.
5. When several inputs are submitted to a current injection, the maximum ∑IINJ(PIN) is the absolute sum of the
positive and negative injected currents (instantaneous values).
Table 12. Thermal characteristics
Symbol
Ratings
Value
Unit
TSTG
TJ
Storage temperature range
-65 to +150
105
Maximum junction temperature (suffix 1)
Maximum junction temperature (suffix 3)
°C
125
6.3
Operating conditions
6.3.1
General operating conditions
Table 13. General operating conditions
Symbol
Parameter
Operating conditions
STM32MP157C
Min.
Typ
Max.
Unit
0
0
-
-
650
800
Fmpuss_ck
Cortex-A7 subsystem
STM32MP157F
Internal AXI, AHB5,
AHB6 clock
frequency
Faxiss_ck, Fhclk5
Fhclk6
,
-
0
-
266
Internal MCU AHB
clock frequency
Fmcu_ck
Fpclk1
Fpclk2
Fpclk3
Fpclk4
Fpclk5
-
-
-
-
-
-
0
0
0
0
0
-
-
-
-
-
209
104.5
104.5
104.5
133
Internal APB1 clock
frequency
MHz
Internal APB2 clock
frequency
Internal APB3 clock
frequency
Internal APB4 clock
frequency
Internal APB5 clock
frequency
0
-
-
133
3.6
I/Os and embedded SYSCFG_IOCTRLSETR = 0
regulators (REG1V1,
REG1V8) supply
1.71(1)(2)
VDD
V
SYSCFG_IOCTRLSETR ≠ 0
1.71
-
2.7
voltage
System analog
supply voltage
(3)
VDD_ANA
-
1.71
1.71
-
-
3.6
3.6
V
V
VDD_PLL
,
PLL supply voltage
-
(4)
VDD_PLL2
DS12505 Rev 5
127/260
238
Electrical characteristics
STM32MP157C/F
Table 13. General operating conditions (continued)
Symbol
Parameter
Operating conditions
Min.
Typ
Max.
Unit
DSI regulator supply
voltage
(11)
VDD_DSI
-
1.71
-
3.6
V
Run mode
1.30
1.18
1.34
1.20
1.38
1.25
(Fmpuss_ck above 650 MHz)(5)
Run mode
(Fmpuss_ck up to 650 MHz)
Digital core domain
supply voltage
VDDCORE
V
Stop, LP-Stop mode
LPLV-Stop mode
1.10
0.85
0
1.20
1.25
1.25(6)
0.75
2
0.90
Standby mode
0
-
ADC used with VREF < 2 V
ADC used with VREF > 2 V
DAC used
1.62
2
-
3.6
1.8
-
3.6
VREFBUF with VREF = 1.5 V(7)
-
3.6
1.8
Analog operating
voltage
VREFBUF with VREF = 1.5 V
and ADC used
VDDA
-
2
V
VREFBUF with VREF = 1.8 V(8)
VREFBUF with VREF = 2.048 V
VREFBUF with VREF = 2.5 V
ADC, DAC, VREF not used
64 KB retention SRAM not used
64 KB retention SRAM used
USB OTG FS used
2.1
2.35
2.8
0
-
-
-
-
3.6
3.6
3.6
3.6
1.2
1.4
3
Backup operating
voltage
VBAT
-
3.6
V
V
3.3
-
3.6
3.6
3.6
USB FS I/O supply
voltage
(9)
VDD3V3_USBFS
USB OTG FS not used
0
USBH or USB OTG HS used
3.07
3.3
USB HS I/O supply
voltage
(9)(10)
VDD3V3_USBHS
V
V
USBH and USB OTG HS not
used
0
-
3.6
USB used
3.07
0
3.3
-
3.6
3.6
USB I/O supply
voltage
(9)
VDD3V3_USB
USB not used
1.2 V DSI PHY
supply voltage
(11)
VDD1V2_DSI_PHY
-
-
1.15
1.65
1.2
1.8
1.26
1.95
V
V
1.8 V DSI PHY
supply voltage
(11)
VDDA1V8_DSI
DDR3 memory
1.425
1.283
1.14
1.5
1.35
1.2
1.575
1.45
1.3
DDR PHY supply
voltage
(11)
VDDQ_DDR
DDR3L memory
LPDDR2 or LPDDR3
V
128/260
DS12505 Rev 5
STM32MP157C/F
Electrical characteristics
Table 13. General operating conditions (continued)
Symbol
Parameter
Operating conditions
Min.
Typ
Max.
Unit
USB HS PHY voltage
supply with 1.8 V
regulator in bypass
mode
VDDA1V8_REG
BYPASS_REG1V8 = VDD
1.65
1.8
1.95
V
TTxa I/O
-0.3
-0.3
-0.3
-1
-
-
-
-
-
-
-
VDD+0.3
6(12)
OTG_VBUS I/O
DDR I/O
VIN
I/O Input voltage
VDDQ_DDR
5.25
V
USB HS I/O
All I/O except TTxa
Suffix 1 version
Suffix 3 version
-0.3
-20
-40
See(13)
105
Junction temperature
range
TJ
oC
125
1. Once nRST is released functionality is guaranteed down to VBOR falling edge max.
2. Min VDD is 2.25 V when REG1V8 is used BYPASS_REG1V8 = 0.
3. Should be connected to same power supply voltage as VDD
.
4. It is recommended to connect VDD_PLL and VDD_PLL2 to same power supply as VDD
5. Only for STM32MP157Fxx1 devices
.
6. 1.25 V is the max allowed voltage, however LPLV-Stop mode is only relevant for VDDCORE up to 0.95 V. In LPLV-Stop
mode, if VDDQ_DDR is not shutdown, to avoid overconsumption on VDDQ_DDR, the DDR memory must be put in
SelfRefresh and DDR PHY must be set in retention mode (setting bit DDRRETEN: DDR retention enable of PWR control
register 3 (PWR_CR3)).
7. DAC cannot be used with VREF below 1.8 V.
8. ADC cannot be used with VREF below 2 V and VDDA above 2 V.
9. Depending on package selected, either VDD3V3_USBFS and VDD3V3_USBHS or only VDD3V3_USB are available.
10. For operation with voltage higher than Min (VDD, VDDA, VDD3V3_USBFS) + 0.3 V, the internal Pull-up and Pull-Down resistors
must be disabled.
11. Independent from any other supply, see details in Section 3.8.1: Power supply scheme.
12. Min(VDD, VDD3V3_USBFS) + 3.6 V < 6 V.
13. Min(VDD, VDDA, VDD3V3_USBFS) + 3.6 V < 5.5 V. This formula has to be applied on power supplies related to the IO
structure described by the pin definition table.
6.3.2
Operating conditions at power-up / power-down
Subject to general operating conditions.
DS12505 Rev 5
129/260
238
Electrical characteristics
Symbol
STM32MP157C/F
Table 14. Operating conditions at power-up / power-down
Parameter
VDD rise time rate
DD fall time rate
VDDA rise time rate
DDA fall time rate
Min
Max
Unit
0
10
0
∞
∞
∞
∞
∞
(1)
tVDD
V
tVDDA
V
10
0
(2)
tVDD3V3_USB
VDD3V3_USBxx rise time rate
VDD3V3_USBxx fall time rate
tVDD3V3_USBHS
tVDD3V3_USBFS
µs/V
10
-
∞
VDDCORE rise time rate (from
reset to RUN mode)
2000(3)
tVDDCORE
VDDCORE rise time rate (from
LPLV-Stop to RUN mode)
-
1000(4)
∞
VDDCORE fall time rate
7.33
1. VDD must be present before VDDCORE
.
2. VDDA1V8_REG must be present before VDD3V3_USBHS
.
3. In case VDDCORE rise time is larger than 2 ms/V, user should control the NRST_CORE signal with a Power
Good (PG) control signal from the external regulator to avoid dysfunction of the device due to VDDCORE
potentially not yet established when internal reset signal is de-activated after tVDDCORETEMPO (cf.Table 14
and Figure 13).
4. In case VDDCORE rise time at exit of LPLV-Stop is larger than 1 ms/V, there is a risk of unwanted reset due
to VDDCORE potentially not yet established after tSEL_VDDCORETEMPO (cf.Table 14 and Figure 14). In such a
case, the VDDCORE supply should not be decreased during LPLV-Stop mode.
Figure 13. V
rise time from reset
DDCORE
average rise time rate should be less than
tVDDCORE Max (from reset to Run mode)
VDDCORE should be above
VDDCORE Min when vddcore_ok is
enabled
VDDCORE
V
VDDCORE Min
VPVDCORE_0 (rising edge)
t
tVDDCORETEMPO
pvdcore_out
vddcore_ok
Run mode
VDDCORE Min = VPVDCORE_0 Min (rising edge) + tVDDCORETEMPO Min / tVDDCORE Max
MSv47497V2
130/260
DS12505 Rev 5
STM32MP157C/F
Electrical characteristics
Figure 14. V
rise time from LPLV-Stop
DDCORE
average rise time rate should be less than
tVDDCORE Max (from LPLV-Stop to Run
mode)
VDDCORE should be above
VDDCORE Min at the end of
tSEL_VDDCORETEMPO
VDDCORE
V
VDDCORE Min
VPVDCORE_1 (falling edge)
t
tSEL_VDDCORETEMPO
PWR_LP
LPLV-
Stop
mode
Wait
Run mode
VDDCORE Min = VPVDCORE_1 Min (falling edge) + tVSEL_VDDCORETEMPO Min / tVDDCORE Max
MSv47499V2
6.3.3
Embedded reset and power control block characteristics
The parameters given in Table 15 are derived from tests performed under ambient
temperature and V supply voltage conditions summarized in Table 13: General operating
DD
conditions.
Table 15. Embedded reset and power control block characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Reset temporization. after
BOR0 released
(1)
tRSTTEMPO
-
-
377
550
µs
Rising edge
Falling edge
Rising edge
Falling edge
Rising edge
Falling edge
Rising edge
Falling edge
Rising edge
Falling edge
1.62
1.58
1.67
1.63
2.1
1.71
1.67
(1)
VBOR0
Brown-out reset threshold 0
Brown-out reset threshold 1
Brown-out reset threshold 2
Brown-out reset threshold 3
V
V
V
V
V
2.055
1.955
2.355
2.255
2.655
2.555
1.905
1.805
2.145
2.045
2.445
2.345
2.745
2.645
1.995
1.895
VBOR1
VBOR2
VBOR3
VPVD0
2
2.4
2.3
2.7
2.6
1.95
1.85
Programmable Voltage
Detector threshold 0
DS12505 Rev 5
131/260
238
Electrical characteristics
STM32MP157C/F
Table 15. Embedded reset and power control block characteristics (continued)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Rising edge
Falling edge
Rising edge
Falling edge
Rising edge
Falling edge
Rising edge
Falling edge
Rising edge
Falling edge
Rising edge
2.055
1.955
2.205
2.105
2.355
2.255
2.505
2.405
2.655
2.555
2.805
2.1
2
2.145
2.045
2.295
2.195
2.445
2.345
2.595
2.495
2.745
2.645
2.895
Programmable Voltage
Detector threshold 1
VPVD1
V
2.25
2.15
2.4
Programmable Voltage
Detector threshold 2
VPVD2
VPVD3
VPVD4
VPVD5
V
V
V
V
Programmable Voltage
Detector threshold 3
2.3
2.55
2.45
2.7
Programmable Voltage
Detector threshold 4
Programmable Voltage
Detector threshold 5
2.6
2.85
Programmable Voltage
Detector threshold 6
VPVD6
V
Falling edge in
RUN mode
2.705
2.75
2.795
Hysteresis in
RUN mode
Vhyst_BOR0
Vhyst_BOR
Hysteresis voltage of BOR0
Hysteresis voltage of BOR
-
-
40
-
-
mV
mV
mV
Unless BOR0
100
100
Hysteresis voltage of BOR
(unless BOR0) and PVD(2)
Hysteresis in
RUN mode
Vhyst_BOR_PVD
-
-
BOR (unless BOR0) and PVD
consumption from VDD
(1)(3)
IDD_BOR_PVD
-
0.246
-
0.626
µA
V
Rising edge
Falling edge
Rising edge
Falling edge
Rising edge
Falling edge
Rising edge
Falling edge
1.655
1.555
2.055
1.955
2.455
2.355
2.755
2.655
1.7
1.6
2.1
2
1.745
1.645
2.145
2.045
2.545
2.445
2.845
2.745
Analog voltage (VDDA) detector
threshold 0
VAVM_0
Analog voltage (VDDA) detector
threshold 1
VAVM_1
V
V
V
2.5
2.4
2.8
2.7
Analog voltage (VDDA) detector
threshold 2
VAVM_2
Analog voltage (VDDA) detector
threshold 3
VAVM_3
Hysteresis of analog voltage
(VDDA) detector
Vhyst_VDDA
-
-
-
100
-
-
0.248
-
mV
µA
µA
Analog Voltage Monitoring
(VDDA) consumption on VDD
(1)
IVDD_AVM
-
Analog Voltage Monitoring
(VDDA) consumption on VDDA
(1)
IVDDA_AVM
Resistor bridge
-
2.12
Digital core domain supply
voltage (VDDCORE) detector
threshold 0 (Run)
Rising edge
Falling edge
0.95
0.91
0.995
0.955
1.04
1
(4)
VPVDCORE_0
V
132/260
DS12505 Rev 5
STM32MP157C/F
Electrical characteristics
Table 15. Embedded reset and power control block characteristics (continued)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Digital core domain supply
voltage (VDDCORE) detector
threshold 1 (LPLV_Stop)
(5)
VPVDCORE_1
Falling edge
0.71
0.755
0.8
V
Hysteresis of Digital core
domain supply voltage
(VDDCORE) detector
Vhyst_VDDCORE
-
-
-
40
-
mV
µs
Tempo on VPVDCORE_0 at
rising edge of VDDCORE to
ensure that VDDCORE is fully
established
tVDDCORETEMPO
200
340
550
Tempo on VPVDCORE_1 at rising
tSEL_VDDCORETE edge of VDDCORE to ensure that
-
234
380
606
µs
VDDCORE is fully established on
exit of LPLV-Stop mode
MPO
IVDD_VDDCOREVM VDDCORE Voltage Monitoring
-
-
1.7
-
2.6
4.2
-
µA
V
(1)
consumption on VDD
USB_VTH
USB Threshold voltage
1.21
1. Guaranteed by design.
2. No hysteresis when using PVD_IN pin.
3. BOR0 is enabled in all modes and its consumption is therefore included in the supply current characteristics tables.
4. During the first rising edge of VDDCORE, the slope should be less than 2 ms/V to ensure VDDCORE is fully established before
the end of the tVDDCORETEMPO
.
5. When exiting from LPLV-Stop mode to RUN mode the rising slope for VDDCORE should be less than 1 ms/V to ensure
VDDCORE is fully established before the end of the tVDDCORETEMPO
.
6.3.4
Embedded reference voltage
The parameters given in Table 16, Table 17 are derived from tests performed under ambient
temperature and V supply voltage conditions summarized in Table 13: General operating
DD
conditions.
Table 16. Embedded reference voltage
Symbol
VREFINT
Parameter
Conditions
Min
Typ
Max
Unit
Internal reference voltages
-40 °C < TJ < 125 °C
1.175
1.210
1.241
V
ADC sampling time when
reading the internal reference
voltage
(1)(2)
tS_vrefint
-
4.3
9.8
-
-
-
-
VBAT sampling time when
reading the internal VBAT
reference voltage
µs
(1)
tS_vbat
-
-
Start time of reference voltage
buffer when ADC is enable
tstart_vrefint
0.8
9.1
-
4.6
Reference Buffer consumption
for ADC
(2)
Irefbuf
V
DDA = 3.3 V
13.6
27.7
µA
DS12505 Rev 5
133/260
238
Electrical characteristics
STM32MP157C/F
Table 16. Embedded reference voltage (continued)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Internal reference voltage
spread over the temperature
range
(2)
ΔVREFINT
-40 °C < TJ < 125 °C
-
4.3
15
mV
Average temperature
coefficient
Average temperature
coefficient
Tcoeff_VREFINT
VDDcoeff
-
-
19
10
67
ppm/°C
ppm/V
Average Voltage coefficient
3.0 V < VDD < 3.6 V
1370
1. The shortest sampling time for the application can be determined by multiple iterations.
2. Guaranteed by design.
Table 17. Embedded reference voltage calibration value
Parameter
Symbol
Memory address
0x5C00 5250[31:16](1)(2)
VREFIN_CAL
Raw data acquired at temperature of 30 °C, VDDA = VREF+ = 3.3 V
1. Mandatory to read in 32-bits word and do relevant mask and shift to isolate required bits.
2. These address is inside BSEC which should be enabled in RCC to allow access.
6.3.5
Embedded regulators characteristics
The parameters given in Table 18, Table 19, Table 20 are derived from tests performed
under ambient temperature and V supply voltage conditions summarized in Table 13:
DD
General operating conditions.
REG1V1 embedded regulator (USB_PHY)
(1)
Table 18. REG1V1 embedded regulator (USB_PHY) characteristics
Symbol
Parameter
Condition
Min
Typ
Max
Unit
VDDA1V1_
Regulated output voltage
-
1.045
1.1
1.155
V
REG
CL
Load Capacitor
-
-
-
1.1
0.1
0
2.2(2)
25
3.3
600
30
-
µF
mΩ
mA
esr
Iload
Equivalent Serial Resistor of Cload
Static load current(3)
-
Start-up time. from
PWR_CR3.REG11EN = 1 to
PWR_CR3.REG11RDY = 1
CL=2.2uF
CL=3.3uF
-
93
tSTART
µs
-
-
-
180
60
VDD Inrush Current to load external
capacitor at start
IINRUSH
-
50
mA
Regulator Enabled and Iload
0 mA
=
=
-
-
150
176
205
242
Regulator Current consumption on
VDD
IVDD
µA
Regulator Enabled and Iload
30 mA
1. Guaranteed by design.
2. For better dynamic performances a 2.2 μF typical value external capacitor is recommended.
3. Load is for internal STM32MP157C/F analog blocks, no additional external load is accepted unless mentioned.
134/260
DS12505 Rev 5
STM32MP157C/F
Electrical characteristics
REG_1V2 embedded regulator (DSI)
(1)
Table 19. REG1V2 embedded regulator (DSI) characteristics
Symbol
Parameter
Condition
Min
Typ
Max
Unit
VDD1V2_D
Regulated output voltage
-
1.15
1.2
1.26
V
SI_REG
CL
Load Capacitor
-
-
-
0.5
0.1
-
2.2(2)
25
3.3
600
50
-
µF
mΩ
mA
esr
Iload
Equivalent Serial Resistor of Cload
Static load current(3)
-
Start-up time. from
DSI_WRPCR.REGEN = 1 to
DSI_WISR.RRS = 1
CL=2.2uF
CL=3.3uF
-
84
tSTART
µs
-
-
-
164
60
VDD Inrush Current to load external
capacitor at start
IINRUSH
-
45
mA
Regulator Enabled and Iload
0 mA
=
=
-
-
150
178
203
243
Regulator Current consumption on
VDD
IVDD
µA
Regulator Enabled and Iload
50 mA
1. Guaranteed by design.
2. For better dynamic performances a 2.2 μF typical value external capacitor is recommended.
3. Load is for internal STM32MP157C/F analog blocks, no additional external load is accepted unless mentioned.
REG1V8 embedded regulator (USB+DSI)
(1)
Table 20. REG1V8 embedded regulator (USB+DSI) characteristics
Symbol
VDD
Parameter
Condition
Min
Typ
Max
Unit
Regulator input voltage
-
2.25
3.3
3.6
V
VDDA1V8_
Regulated output voltage
after trimming
1.7
1.8
1.9
V
REG
CL
Load Capacitor
-
-
-
0.5
0.1
-
2.2(2)
25
3.3
600
70
-
µF
mΩ
mA
esr
Iload
Equivalent Serial Resistor of Cload
Static load current(3)
-
Start-up time. from
PWR_CR3.REG11EN = 1 to
PWR_CR3.REG11RDY = 1
CL=2.2uF
CL=3.3uF
-
81
tSTART
µs
-
-
-
150
100
VDD Inrush Current to load external
capacitor at start
IINRUSH
-
80
mA
Regulator Enabled and Iload
0 mA
=
=
-
-
130
170
181
231
Regulator Current consumption on
VDD
IVDD
µA
Regulator Enabled and Iload
70 mA
1. Guaranteed by design.
2. For better dynamic performances a 2.2 μF typical value external capacitor is recommended.
DS12505 Rev 5
135/260
238
Electrical characteristics
STM32MP157C/F
3. Load is for internal STM32MP157C/F analog blocks, no additional external load is accepted unless mentioned.
6.3.6
Supply current characteristics
The current consumption is a function of several parameters and factors such as the
operating voltage, ambient temperature, I/O pin loading, device software configuration,
operating frequencies, I/O pin switching rate, program location in memory and executed
binary code.
The current consumption is measured as described in Figure 12: Current consumption
measurement scheme.
All the Run mode current consumption measurements given in this section are performed
with a CoreMark code unless otherwise specified.
Typical and maximum current consumption
The device is placed under the following conditions:
•
•
•
All I/O pins are in analog input mode except when explicitly mentioned.
All peripherals are disabled except when explicitly mentioned.
The maximum values are obtained for V /V
= 3.6 V and V
= 1.25 V, and
DDCORE
DD BAT
the typical values for V /V
= 3.3 V and V
= 1.2 V unless otherwise
DD BAT
DDCORE
specified.
The parameters given in Table 22 to Table 26 are derived from tests performed under
supply voltage conditions summarized in Table 13: General operating conditions.
136/260
DS12505 Rev 5
(1)
Table 21. Current consumption (I
Conditions
) in Run mode
DDCORE
Typ
Max
MCU
SS
mode
MPU
clk
(MHz) (MHz)
MCU
clk
Symbol Parameter
Unit
MPU SS
mode
Tj =
25 °C
Tj =
25 °C
Tj =
Tj =
Tj =
-
Oscillator
85 °C 105 °C 125 °C
800(3)
744(3)
575
560
400
385
340
560
545
385
375
325
415
400
275
270
235
620
605
485
475
420
605
590
475
460
405
460
445
345
335
295
865
850
675
660
610
850
835
660
650
595
710
695
535
525
470
1050
1035
815
805
750
1040
1025
805
795
740
895
880
680
665
615
-
-
Supply
IDDCORE current in
Run mode
CRun
(P0Run,
P1Run)
All peripherals
enabled(2)
CRun
CStop
CStop
HSE+HSI+LSI+PLL
648
600
209
209
209
1000
1000
945
-
mA
400
800(3)
744(3)
648
-
Supply
IDDCORE current in
Run mode
CRun
(P0Run,
P1Run)
All peripherals
enabled(2)
HSE+HSI+LSI+PLL
HSE+HSI+LSI+PLL
1000
985
935
-
mA
mA
600
400
800(3)
744(3)
648
-
Supply
IDDCORE current in
Run mode
CRun
(P0Run,
P1Run)
All peripherals
disabled
880
865
810
600
400
(1)
Table 21. Current consumption (I
Conditions
) in Run mode (continued)
DDCORE
Typ
Max
MCU
SS
mode
MPU
clk
(MHz) (MHz)
MCU
clk
Symbol Parameter
Unit
MPU SS
mode
Tj =
25 °C
Tj =
25 °C
Tj =
Tj =
Tj =
-
Oscillator
85 °C 105 °C 125 °C
HSE+HSI+PLL
800(3)
744(3)
648
600
300
150
64
-
-
-
-
-
-
-
-
-
-
-
-
275
265
180
175
135
92
320
310
240
230
190
135
105
90
575
565
425
420
380
330
295
280
265
275
270
270
760
750
570
565
520
470
440
425
410
420
415
410
-
HSE+HSI+PLL
HSE+HSI+PLL
HSE+HSI+PLL
HSE+HSI+PLL
HSE+HSI+PLL
HSE+HSI+PLL
HSE+HSI+PLL
HSE+HSI
-
770
765
725
675
645
630
615
625
620
615
Supply
IDDCORE current in
Run mode
CRun
(P0Run,
P1Stop)
All peripherals
disabled
CStop
mA
65
24
51
24
35.5
65
70
HSI+PLL
64
85
HSI+PLL
24
51
75
HSI
64
49
75
(1)
Table 21. Current consumption (I
Conditions
) in Run mode (continued)
DDCORE
Typ
Max
MCU
SS
mode
MPU
clk
(MHz) (MHz)
MCU
clk
Symbol Parameter
Unit
MPU SS
mode
Tj =
25 °C
Tj =
25 °C
Tj =
Tj =
Tj =
-
Oscillator
85 °C 105 °C 125 °C
HSE+HSI+PLL
800(3)
744(3)
648
600
300
150
64
-
-
-
-
-
-
-
-
-
-
-
-
165
160
110
110
100
74
210
205
160
155
150
115
95
465
465
350
350
340
310
290
280
265
275
270
265
650
650
495
490
485
450
430
420
405
415
410
405
-
HSE+HSI+PLL
HSE+HSI+PLL
HSE+HSI+PLL
HSE+HSI+PLL
HSE+HSI+PLL
HSE+HSI+PLL
HSE+HSI+PLL
HSE+HSI
-
695
695
685
655
635
625
610
620
615
610
MPU in
CSleep with
WFI (CLK
OFF). All
peripherals
disabled
Supply
IDDCORE current in
Run mode
CSleep
(P0Stop,
P1Stop)
CStop
mA
57
24
48.5
32.5
57
85
24
70
HSI+PLL
64
80
HSI+PLL
24
48
75
HSI
64
41
70
(1)
Table 21. Current consumption (I
Conditions
) in Run mode (continued)
DDCORE
Typ
Max
MCU
SS
mode
MPU
clk
(MHz) (MHz)
MCU
clk
Symbol Parameter
Unit
MPU SS
mode
Tj =
25 °C
Tj =
25 °C
Tj =
Tj =
Tj =
-
Oscillator
85 °C 105 °C 125 °C
HSE+HSI+PLL
-
-
-
-
-
-
-
-
-
-
-
-
-
-
209
100
64
24
10
4
71
53
115
95
100
95
75
75
65
85
80
65
85
80
70
60
305
285
295
285
270
270
260
280
275
260
280
275
265
255
450
430
435
430
410
410
400
420
415
400
420
415
405
395
650
635
640
635
615
615
605
625
620
605
625
620
610
600
HSE+HSI+PLL
HSE+HSI+PLL
HSE+HSI+PLL
HSE+HSI+PLL
HSE+HSI+PLL
HSE+HSI
59.5
53
38.5
37.5
27.5
59
Supply
IDDCORE current in
Run mode
CStop
(P0Stop,
P1Stop)
24
64
24
64
64
24
4
All peripherals
disabled
CRun
mA
HSI+PLL
HSI+PLL
53
HSI
33.5
59.5
53
CSI+HSI+PLL
CSI+HSI+PLL
CSI+HSI+PLL
CSI+HSI
37
4
24
(1)
Table 21. Current consumption (I
Conditions
) in Run mode (continued)
DDCORE
Typ
Max
MCU
SS
mode
MPU
clk
(MHz) (MHz)
MCU
clk
Symbol Parameter
Unit
MPU SS
mode
Tj =
25 °C
Tj =
25 °C
Tj =
Tj =
Tj =
-
Oscillator
85 °C 105 °C 125 °C
HSE+HSI+PLL
-
-
-
-
-
-
-
-
-
-
-
-
-
-
209
100
64
24
10
4
59.5
47.5
56
100
90
95
90
75
75
65
80
80
65
85
80
70
60
295
280
290
285
270
270
260
275
275
260
275
275
265
255
435
420
430
425
410
410
400
415
410
400
420
415
405
395
640
625
635
630
615
615
605
620
620
605
625
620
610
600
HSE+HSI+PLL
HSE+HSI+PLL
HSE+HSI+PLL
HSE+HSI+PLL
HSE+HSI+PLL
HSE+HSI
52
38
MCU in
37
CSleep with
WFI (CLK
OFF). All
peripherals
disabled
Supply
IDDCORE current in
Run mode
CStop
(P0Stop,
P1Stop)
24
64
24
64
64
24
4
26
CSleep
mA
HSI+PLL
55.5
51.5
30
HSI+PLL
HSI
CSI+HSI+PLL
CSI+HSI+PLL
CSI+HSI+PLL
CSI+HSI
56
51.5
37
4
23.5
1. HSE = 24 MHz, AXI clk (Faxiss_ck) = Max(Fmpuss_ck, 264).
2. Activity on peripherals and bus masters other than processors, could lead to additional power consumption above these values, largely dependent on the amount of
initialized peripherals and their activity.
3. Typical value given with VDDCORE = 1.34 V, maximum values given with VDDCORE = 1.38 V.
(1)
Table 22. Current consumption (I ) in Run mode
DD
Conditions
Typ
Max
MCU
SS
mode
Symbol
Parameter
Unit
Tj =
25 °C
Tj =
25 °C
Tj =
Tj =
Tj =
MPU SS mode
Oscillator
85 °C 105 °C 125 °C
CRun
(P0Run, P1Run)
IDD
Supply current in Run mode
Supply current in Run mode
CRun
CStop
HSE+HSI+LSI+PLL1,2,3,4
3.95
6.14
6.40
6.50
6.60
mA
mA
HSI+PLL1,2
HSE+HSI
HSI
3.00
1.75
1.25
4.67
3.45
2.46
4.90
3.48
2.48
5.00
3.49
2.49
5.10
3.50
2.50
CRun
(P0Run, P1Stop)
IDD
1. HSE = 24 MHz.
(1)
Table 23. Current consumption in Stop mode
Conditions Typ
Max
Symbol
Parameter
Unit
MPU SS MCU SS
mode mode
Tj =
25 °C
Tj =
85 °C
Tj =
105 °C
Tj =
125 °C
Tj =
25 °C
Tj =
85 °C
Tj =
Tj =
-
105 °C 125 °C
CStop
(P0Stop,
P1Stop)
All peripherals
disabled
CStop
980
980
985
985
985
995
995
1500
1560
1580
1580
1600
1600
IDD
CStandby
(P0Stop,
P1Stop)
All peripherals
disabled
CStop
CStop
CStop
985
1500
1560
Supply
current in
Stop mode
µA
CStop
(P0Stop,
P1Stop)
All peripherals
disabled
19000
19000
90500 150000 230000 55000 261000 425000 585000
90000 150000 225000 54500 261000 425000 585000
IDDCORE
CStandby
(P0Stop,
P1Stop)
All peripherals
disabled
1. HSE = 24 MHz.
(1)
Table 24. Current consumption in LPLV-Stop mode
Conditions
Typ(2)
Max(3)
Tj =
Symbol
Parameter
Unit
MPU SS MCU SS
mode mode
Tj =
25 °C
Tj =
85 °C
Tj =
Tj =
Tj =
25 °C
Tj =
Tj =
-
105 °C 125 °C
85 °C
105 °C 125 °C
CStop
(P0Stop,
P1Stop)
All Peripheral
disabled
CStop
980
980
985
985
985
995
995
1500
1500
1560
1580
1580
1600
1600
IDD
CStandby
(P0Stop,
P1Stop)
All Peripheral
disabled
CStop
CStop
CStop
985
1560
Supply
current in
LPLV-Stop
mode
µA
CStop
(P0Stop,
P1Stop)
All Peripheral
disabled
7150
7150
39000
39000
67500 105000 25000 122000 190000 290000
67500 105000 25000 122000 190000 290000
IDDCORE
CStandby
(P0Stop,
P1Stop)
All Peripheral
disabled
1. HSE = 24 MHz.
2. VDDCORE = 0.9 V.
3. VDDCORE = 0.95 V.
(1)
Table 25. Current consumption in Standby mode
Conditions Typ
Max
MCU
SS
mode
Symbol Parameter
Unit
MPU SS
mode
Tj =
25 °C
Tj =
85 °C
Tj =
Tj =
Tj =
25 °C
Tj =
85 °C
Tj =
Tj=
-
105 °C 125 °C
105 °C 125 °C
Backup
SRAM
OFF,
RTC
OFF,
LSE
CStandby
(P0Stop,
P1Stop)
CStop
1.95
4.00
7.60
13.5
4
12
18
32
Retention
RAM OFF
OFF
Supply
current in
Standby
mode
Backup
SRAM
ON,
RTC
ON, LSE
ON,
medium
_high
drive
CStandby
(P0Stop,
P1Stop)
IDD
µA
CStop
CStop
9.6
74
38.5
460
64.5
800
105
17.5
130
70
110
180
CStandby
(P0Stop,
P1Stop)
Retention
RAM ON
1300
850
1500
2300
1. IWDG OFF, LSI OFF, VDDCORE = 0 V.
Table 26. Current consumption in V
mode
BAT
Conditions
Typ
Max
Symbol
Parameter
Unit
Tj =
25 °C
Tj =
85 °C
Tj =
Tj =
Tj =
25 °C
Tj =
85 °C
Tj =
Tj =
-
VBAT (V)
105 °C 125 °C
105 °C 125 °C
1.6
2.4
3
0.007
0.008
0.012
0.041
0.073
0.84
1.05
1.25
1.4
0.13
0.14
0.175
0.52
0.62
1.05
1.3
0.39
0.415
0.495
1.45
1.65
1.35
1.6
1.1
1.15
1.35
3.9
-
-
-
-
-
-
-
-
Backup SRAM OFF,
RTC OFF, LSE OFF
-
-
-
-
3.3
3.6
1.6
2.4
3
-
-
-
-
4.25
2.1
0.11
1
-
2.2
6
-
-
-
-
2.45
2.8
-
-
-
Backup SRAM OFF,
RTC ON, LSE ON,
medium_high drive
1.5
1.9
-
-
-
-
3.3
3.6
1.6
2.4
3
2
3.05
3.35
54
5.7
-
-
-
5.5
-
-
Supply
1.55
7.75
8.25
8.45
9.5
2.25
31
6.25
87.5
88.5
91.5
95.5
98
2
-
3.5
-
9
Retention
RAM OFF
IDDVBAT current in
VBAT mode
µA
-
31.5
33
55
-
-
-
-
Backup SRAM ON,
RTC ON,. LSE ON,
medium_high drive
57
-
-
-
-
3.3
3.6
1.6
2.4
3
34
59
-
-
-
-
9.55
7.9
35
60.5
55
15
-
62
-
93
-
151
31.5
32.5
33.5
35
89
-
8.4
56
90
-
-
-
-
Backup SRAM ON,
RTC ON,. LSE ON,
high drive
8.6
58
93
-
-
-
-
-
3.3
3.6
9.2
60.5
62.5
97.5
100
-
-
-
9.85
36
15
63
93
151
Table 26. Current consumption in V
Conditions
mode (continued)
BAT
Typ
Max
Symbol
Parameter
Unit
Tj =
25 °C
Tj =
85 °C
Tj =
Tj =
Tj =
25 °C
Tj =
85 °C
Tj =
Tj =
-
VBAT (V)
105 °C 125 °C
105 °C 125 °C
1.6
2.4
3
74
76
405
410
420
430
435
405
410
425
435
440
760
765
785
795
815
770
770
790
805
820
1250
1250
1300
1300
1350
1250
1250
1300
1300
1350
-
-
-
-
-
-
-
-
Backup SRAM ON,
RTC ON,. LSE ON,
medium_high drive
81
-
-
-
-
3.3
3.6
1.6
2.4
3
79
-
-
-
-
Supply
84.5
75.5
75.5
76
180
850
1350
2000
Retention
RAM ON
IDDVBAT current in
VBAT mode
µA
-
-
-
-
-
-
-
-
Backup SRAM ON,
RTC ON, LSE ON,
high drive
-
-
-
-
-
-
-
-
3.3
3.6
78
84.5
180
870
1350
2000
STM32MP157C/F
Electrical characteristics
I/O system current consumption
The current consumption of the I/O system has two components: static and dynamic.
I/O static current consumption
All the I/Os used as inputs with pull-up generate a current consumption when the pin is
externally held low. The value of this current consumption can be simply computed by using
the pull-up/pull-down resistors values given in Table 52: I/O static characteristics.
For the output pins, any external pull-down or external load must also be considered to
estimate the current consumption.
An additional I/O current consumption is due to I/Os configured as inputs if an intermediate
voltage level is externally applied. This current consumption is caused by the input Schmitt
trigger circuits used to discriminate the input value. Unless this specific configuration is
required by the application, this supply current consumption can be avoided by configuring
these I/Os in analog mode. This is notably the case of ADC input pins which should be
configured as analog inputs.
Caution:
Any floating input pin can also settle to an intermediate voltage level or switch inadvertently,
as a result of external electromagnetic noise. To avoid a current consumption related to
floating pins, they must either be configured in analog mode, or forced internally to a definite
digital value. This can be done either by using pull-up/down resistors or by configuring the
pins in output mode.
I/O dynamic current consumption
The I/Os used by an application contribute to the current consumption. When an I/O pin
switches, it uses the current from the MCU supply voltage to supply the I/O pin circuitry and
to charge/discharge the capacitive load (internal or external) connected to the pin.
The theoretical formula is provided below:
ISW = VDDx × fSW × CL
where
I
is the current sunk by a switching I/O to charge/discharge the capacitive load
SW
V
is the MCU supply voltage
DDx
f
is the I/O switching frequency
SW
C is the total capacitance seen by the I/O pin: C = CINT+ CEXT
L
6.3.7
Wakeup time from low-power modes
The wakeup times given in Table 27 are measured starting from the wakeup event trigger up
to the first instruction executed by the MPU or MCU:
•
•
For CSleep modes:
the MPU or MCU goes in low-power mode after WFE (Wait For Event) instruction.
For CStop modes:
–
–
–
MCU goes in low-power mode after WFE (Wait For Event) instruction.
MPU goes in low-power mode after WFI (Wait For Interrupt) instruction.
•
WKUPx pin is used to wakeup from low-power modes.
DS12505 Rev 5
147/260
238
Electrical characteristics
STM32MP157C/F
All timings are derived from tests performed under ambient temperature and V = 3.3 V.
DD
Table 27. Low-power mode wakeup timings
System
mode
Max(
Symbol
Parameter
Conditions (after wakeup)
Typ(1)
Unit
1)
MPU wakeup
mpuss_
32 ckclock
cycles
tWUCSLEEP_M MPU wakeup from
Run
HSE 24 MHz, SYSRAM
31
CSleep, MCU in CSleep
PU
HSI 64 MHz, SYSRAM
5.7
112
9
220
1
MPU wakeup from
CStop, MCU in CStop
Stop
Run
HSE + PLL 648 MHz, SYSRAM
HSI 64 MHz, SYSRAM
tWUCSTOP_MP
U
0.54
0.083
MPU wakeup from
CStop, MCU in CRun
µs
HSE + PLL 648 MHz, SYSRAM
0.17
MPU wakeup from
CStop with system in
LPLV-Stop (LVDS=1),
MCU in CStop
tWULPLV-
LPLV-
Stop
HSI 64 MHz, SYSRAM
HSE 24 MHz, SRAM
410
640
Stop_MPU
MCU wakeup
mcu_ck
clock
cycles
tWUCSLEEP_M MCU wakeup from
Run
6
7
8
CSleep, MPU in CSleep
CU
HSI 64 MHz, SRAM,
MCTMPSKP = 1
5.3
1.4
5.3
µs
MCU wakeup from
CStop with system in
LPLV-Stop (LVDS=1),
MPU in CStop
tWULPLV-
LPLV-
Stop
HSI 64 MHz, SRAM,
MCTMPSKP = 0, PWR_LP
delay = 1 ms
Stop_MCU
2.2
8
ms
tWUCSTOP_
MCU wakeup from
CStop, MPU in CStop
Stop
HSI 64 MHz, SRAM
HSI 64 MHz, SRAM
HSI 64 MHz, SRAM
MCU
MCU wakeup from
CStop, HSI active
(HSIKERON=1), MPU in
CStop
Stop
(HSI
active)
tWUCSTOP_
0.33
0.5
MCU2
µs
tWUCSTOP_
MCU wakeup from
CStop, MPU in CRun
Run
0.12
0.18
MCU3
tWUSTANDBY_ MCU wakeup from
STANDBY
Standby HSI 64 MHz, RETRAM
2550
3000
MCU
1. Guaranteed by characterization results unless otherwise specified.
(1)
Table 28. Wakeup time using USART
Symbol
Parameter
Conditions
Typ
Max
Unit
Wakeup time needed to calculate the
maximum USART baud rate allowing the
wakeup from Stop mode when USART
clock source is HSI.
tWUUSART
Stop
-
6.7
µs
1. Guaranteed by design.
148/260
DS12505 Rev 5
STM32MP157C/F
Electrical characteristics
6.3.8
External clock source characteristics
High-speed external user clock generated from an external source
In bypass mode the HSE oscillator is switched off and the input pin is a standard I/O.
Digital and analog bypass modes are available.
The external clock signal has to respect the Table 52: I/O static characteristics. However,
the recommended clock input waveform is shown in Figure 15 for digital bypass mode and
in Figure 16 for analog bypass mode. In analog bypass mode the clock can be a sinusoidal
waveform.
Table 29. High-speed external user clock characteristics
(1)
(digital bypass)
Symbol
fHSE_ext
Parameter
Min
Typ
Max
Unit
User external clock source frequency
8
0.7×VDD
VSS
24
-
48
VDD
MHz
VSW (VHSEH -VHSEL) OSC_IN amplitude
V
VDC
OSC_IN input voltage
-
0.3×VSS
-
tW(HSE)
OSC_IN high or low time
7
-
ns
1. Guaranteed by design.
Figure 15. High-speed external clock source AC timing diagram (digital bypass)
V
HSEH
90%
10 %
V
HSEL
t
t
W(HSE)
t
t
t
W(HSE)
r(HSE)
f(HSE)
T
HSE
f
HSE_ext
External
I
L
OSC _I N
clock source
STM32
ai17528b
Table 30. High-speed external user clock characteristics
(1)
(analog bypass)
Symbol
Parameter
Min
Typ
Max
Unit
User external clock source frequency
8
45
0
24
50
48
55
MHz
%
fHSE_ext duty cycle (Square wave)
duty cycle deterioration
±10(2)
±20(3)
%
VHSE
Absolute input range
0
-
VDD
-
DS12505 Rev 5
149/260
238
Electrical characteristics
STM32MP157C/F
Table 30. High-speed external user clock characteristics
(1)
(analog bypass) (continued)
Symbol
VPP
Parameter
OSC_IN peak-to-peak amplitude
Min
Typ
Max
Unit
0.2(4)
-
-
0.67×VDD
10(6)
V
(5)
tSU
Time to start
1
µs
Rise and Fall time
tr/tf(HSE)
0.05 ×THSE
-
0.3 ×THSE
500(8)
ns
(10% to 90% threshold levels of the
input peak-to-peak amplitude)
I(HSE)
Power consumption
-
150(7)
µA
1. Guaranteed by design.
2. Guaranteed by design with a square wave signal (@25 °C, VDD=3.3 V /VPP = 400 mV / VDC=1 V) where
V
DC is the DC component of the input signal.
3. Guaranteed by design with a square wave signal (@25 °C, VDD=1.71 V /VPP = 200 mV / VDC=0.8 V) where
V
DC is the DC component of the input signal.
4. minimum peak-to-peak amplitude (@25 °C, 0.1<VDC<VDD-0.1 V) where VDC is the DC component of the
input signal.
5. tSU(HSE) is the startup time measured from the moment it is enabled (by software) to a stabilized analog
bypass clock interface is reached. This value is measured with 200 mV peak-to-peak amplitude.
6. Maximum start-up time is obtained with 200 mV peak-to-peak amplitude.
7. with a sine wave signal (VPP = 400 mV / VDC=0.4 V) where VDC is the DC component of the input signal.
8. with a sine wave signal (VDD = 3.6 V / VPP = 800 mV / VDC = 1.8 V) where VDC is the DC component of the
input signal.
Figure 16. High-speed external clock source AC timing diagram (analog bypass)
VHSE
90%
VPP
10%
t
THSE
tr(HSE)
External
clock source
fHSE_ext
OSC_IN
IL
STM32
MSv47498V1
Table 31. Low-speed external user clock characteristics
(1)
(analog bypass)
Symbol
fLSE_ext User external clock source frequency
VLSE Absolute input range
Parameter
Min
Typ
Max
Unit
-
32.768
-
-
kHz
-
(2)
0
VSW
150/260
DS12505 Rev 5
STM32MP157C/F
Electrical characteristics
Table 31. Low-speed external user clock characteristics
(1)
(analog bypass) (continued)
Symbol
Parameter
Min
Typ
Max
Unit
VPP
OSC32_IN peak-to-peak amplitude
Power consumption
0.2(3)
-
1
-
-
V
I(LSE)
120
nA
1. Guaranteed by design.
2. VSW is equal to VDD when present or VBAT otherwise
3. Minimum peak-to-peak amplitude (@25 °C, 0.1 < VDC < VSW - 0.1 V) where VDC is the DC component of
the input signal.
Figure 17. Low-speed external clock source AC timing diagram (analog bypass)
VLSE
VPP
t
TLSE
External
clock source
fLSE_ext
OSC32_IN
IL
STM32
MSv63037V1
Low-speed external user clock generated from an external source
In bypass mode the LSE oscillator is switched off and the input pin is a standard I/O. The
external clock signal has to respect the Table 52: I/O static characteristics. However, the
recommended clock input waveform is shown in Figure 18 for digital bypass and Figure 17
for analog bypass.
(1)
Table 32. Low-speed external user clock characteristics (digital bypass)
Symbol
Parameter
Min
Typ
Max
Unit
fLSE_ext
VLSEH
VLSEL
User external clock source frequency
OSC32_IN input pin high level voltage
OSC32_IN input pin low level voltage
-
32.768
1000
VDD
kHz
0.7 × VDD
VSS
-
-
V
0.3 VDD
tw(LSEH)
tw(LSEL)
OSC32_IN high or low time
250
-
-
ns
1. Guaranteed by design.
Note:
For information on selecting the crystal, refer to the application note AN2867 “Oscillator
design guide for ST microcontrollers” available from the ST website www.st.com.
DS12505 Rev 5
151/260
238
Electrical characteristics
STM32MP157C/F
Figure 18. Low-speed external clock source AC timing diagram
V
LSEH
90%
10%
V
LSEL
t
t
W(LSE)
t
t
t
W(LSE)
r(LSE)
f(LSE)
T
LSE
f
LSE_ext
External
I
L
OSC32_IN
clock source
STM32
ai17529b
High-speed external clock generated from a crystal/ceramic resonator
The high-speed external (HSE) clock can be supplied with a 8 to 48 MHz crystal/ceramic
resonator oscillator. All the information given in this paragraph are based on
characterization results obtained with typical external components specified in Table 33. In
the application, the resonator and the load capacitors have to be placed as close as
possible to the oscillator pins in order to minimize output distortion and startup stabilization
time. Refer to the crystal resonator manufacturer for more details on the resonator
characteristics (frequency, package, accuracy).
(1)
Table 33. 8-48 MHz HSE oscillator characteristics
Symbol
Parameter
Operating conditions(2)
Min
Typ
Max
Unit
F
Oscillator frequency
Feedback resistor
-
8
-
24
200
-
48
-
MHz
kΩ
RF
-
During startup(3)
-
4
V
DD = 3 V, Rm = 150 Ω
-
-
-
-
-
0.35
0.40
0.45
0.65
0.95
-
-
-
-
-
CL = 12 pF at 4 MHz
VDD = 3 V, Rm = 120 Ω
CL = 12 pF at 16 MHz
IDD(HSE)
HSE current consumption
mA
VDD = 3 V, Rm = 100 Ω
CL = 10 pF at 24 MHz
VDD = 3 V, Rm = 80 Ω
CL = 8 pF at 32 MHz
VDD = 3 V, Rm = 80 Ω
CL = 8 pF at 48 MHz
Gmcritmax
Maximum critical crystal gm
Start-up time
Startup
-
-
-
1.5
-
mA/V
ms
(4)
tSU
VDD is stabilized
2
1. Guaranteed by design.
2. Resonator characteristics given by the crystal/ceramic resonator manufacturer.
152/260
DS12505 Rev 5
STM32MP157C/F
Electrical characteristics
3. This consumption level occurs during the first 2/3 of the tSU(HSE) startup time.
4. tSU(HSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 8 MHz oscillation is
reached. This value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer.
For C and C , it is recommended to use high-quality external ceramic capacitors in the
L1
L2
5 pF to 25 pF range (typical), designed for high-frequency applications, and selected to
match the requirements of the crystal or resonator (see Figure 19). C and C are usually
L1
L2
the same size. The crystal manufacturer typically specifies a load capacitance which is the
series combination of C and C . The PCB and MCU pin capacitance must be included
L1
L2
(10 pF can be used as a rough estimate of the combined pin and board capacitance) when
sizing C and C .
L1
L2
Note:
For information on selecting the crystal, refer to the application note AN2867 “Oscillator
design guide for ST microcontrollers” available from the ST website www.st.com.
Figure 19. Typical application with a 24 MHz crystal
CL1
fHSE
OSC_IN
Bias
controlled
gain
24 MHz
crystal
RF
OSC_OUT
STM32
CL2
MSv63062V1
Low-speed external clock generated from a crystal/ceramic resonator
The low-speed external (LSE) clock can be supplied with a 32.768 kHz crystal/ceramic
resonator oscillator. All the information given in this paragraph are based on
characterization results obtained with typical external components specified in Table 34. In
the application, the resonator and the load capacitors have to be placed as close as
possible to the oscillator pins in order to minimize output distortion and startup stabilization
time. Refer to the crystal resonator manufacturer for more details on the resonator
characteristics (frequency, package, accuracy).
DS12505 Rev 5
153/260
238
Electrical characteristics
STM32MP157C/F
(1)
Table 34. Low-speed external user clock characteristics
Symbol
Parameter
Operating conditions(2)
Min
Typ
Max
Unit
F
Oscillator frequency
-
-
32.768
290
-
kHz
LSEDRV[1:0] = 00,
Low drive capability
-
-
-
-
-
-
-
-
-
LSEDRV[1:0] = 01,
Medium Low drive capability
390
LSE current
consumption
IDD
nA
LSEDRV[1:0] = 10,
Medium high drive capability
550
-
LSEDRV[1:0] = 11,
High drive capability
900
-
LSEDRV[1:0] = 00,
Low drive capability
-
-
-
0.5
0.75
1.7
LSEDRV[1:0] = 01,
Medium Low drive capability
Maximum critical crystal
gm
Gmcritmax
µA/V
LSEDRV[1:0] = 10,
Medium high drive capability
LSEDRV[1:0] = 11,
High drive capability
-
-
-
2.7
-
(3)
tSU
Startup time
VDD is stabilized
2
s
1. Guaranteed by design.
2. Refer to the note and caution paragraphs below the table, and to the application note AN2867 “Oscillator design guide for
ST microcontrollers.
3. tSU is the startup time measured from the moment it is enabled (by software) to a stabilized 32.768 k Hz oscillation is
reached. This value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer.
Note:
For information on selecting the crystal, refer to the application note AN2867 “Oscillator
design guide for ST microcontrollers” available from the ST website www.st.com.
Figure 20. Typical application with a 32.768 kHz crystal
Resonator with
integrated capacitors
CL1
fHSE
OSC32_IN
Bias
controlled
gain
32.768 kHz
resonator
RF
OSC32_OUT
STM32
CL2
ai17531c
1. Adding an external resistor between OSC32_IN and OSC32_OUT is forbidden.
154/260
DS12505 Rev 5
STM32MP157C/F
Electrical characteristics
6.3.9
External clock source security characteristics
(1)
Table 35. High-speed external user clock security system (HSE CSS)
Symbol
Parameter
Min
Typ
Max
Unit
tDCM(HSE_CSS) Time to detect clock missing
-
-
-
2
-
-
μs
ns
tDCP(HSE_CSS)
IVDD(HSE_CSS)
Time to detect clock presence
250
50
Power consumption (fHSE = 48 MHz)
-
μA
1. Guaranteed by design.
6.3.10
Internal clock source characteristics
The parameters given in Table 36, Table 37 and Table 38 are derived from tests performed
under ambient temperature and V supply voltage conditions summarized in Table 13:
DD
General operating conditions.
64 MHz high-speed internal RC oscillator (HSI)
(1)
Table 36. HSI oscillator characteristics
Symbol
Parameter
HSI frequency
Conditions
Min
Typ Max Unit
64 64.3 MHz
(2)
fHSI
VDD = 3.3 V, TJ = 30 °C
63.7
Trimming is not a multiple
of 32
-
-
-
0.24 0.33
Trimming is 128, 256 and
384
-2.43
-0.70
-
-
Trimming is 64, 192, 320
and 448
TRIM
HSI user trimming step
%
Other trimming are a
multiple of 32 (not
including multiple of 64
and 128)
-
-0.30
-
DuCy(HSI)
ΔVDD (HSI)
Duty Cycle
-
45
-
-
55
%
%
HSI oscillator frequency drift over VDD
(reference is 3.3 V)
VDD = 1.71 to 3.6 V
-0.12
0.03
TJ = -20 to 110 °C
TJ = -40 to 125 °C
-1.25
-1.75
-
-
0.75
0.95
HSI oscillator frequency drift over
temperature after factory calibration
(3)
ΔTEMP (HSI)
%
HSI oscillator start-up time (Time
between Enable rising and First output
clock edge.)
tsu(HSI)
-
-
1.47
2
µs
tstab(HSI)
HSI oscillator stabilization time
HSI oscillator power consumption
at 1% of target frequency
-
-
-
3
-
µs
I
DD(HSI)
300
400
µA
1. Guaranteed by design unless otherwise specified.
2. Guaranteed by test in production.
3. Guaranteed by characterization results.
DS12505 Rev 5
155/260
238
Electrical characteristics
STM32MP157C/F
4 MHz low-power internal RC oscillator (CSI)
(1)
Table 37. CSI oscillator characteristics
Symbol
Parameter
CSI frequency
Conditions
Min Typ Max Unit
(2)
fCSI
VDD = 3.3 V, TJ = 30 °C
3.98
-
4
4.02 MHz
Trimming code is not a
multiple of 16
0.85
1
%
TRIM
Trimming step
Trimming code is a multiple of
16
-
45
-
-1.65
-
-
55
-
-
%
DuCy(CSI)
Duty Cycle
-
VDD = 1.71 to 3.6 V
TJ = 0 to 85 °C
∆
∆
VDD (CSI) +
CSI oscillator frequency drift over
VDD & drift over temperature
±1.43
1.5
5
%
TEMP (CSI)(3)
tsu(CSI)
CSI oscillator startup time
-
-
2.4
-
µs
CSI oscillator stabilization time
tstab(CSI)
IDD(CSI)
TJ = 0 to 85 °C
-
-
cycle
µA
(to reach ±5% of fCSI
)
CSI oscillator power consumption
-
30
-
1. Guaranteed by design.
2. Guaranteed by test in production.
3. Guaranteed by characterization results.
32 kHz low-speed internal (LSI) RC oscillator
(1)
Table 38. LSI oscillator characteristics
Parameter Conditions
TJ = 30 °C,(2)
Symbol
Min
Typ
Max
Unit
31.4
29
32
32
32.6
33.6
VDD = 3.3 V
fLSI
LSI frequency
kHz
TJ = -40 to 125 °C,
VDD = 1.71 to 3.6 V
LSI oscillator startup time (Time
between Enable rising and First
output clock edge.)
tsu(LSI)
-
-
64
125
µs
LSI oscillator stabilization time
(5% of final value)
tstab(LSI)
IDD(LSI)
-
-
-
-
110
120
170
230
LSI oscillator power
consumption
nA
1. Guaranteed by design.
2. Guaranteed by test in production.
6.3.11
PLL characteristics
The parameters given in Table 39, Table 40, Table 41, Table 42 are derived from tests
performed under temperature and V supply voltage conditions summarized in Table 13:
DD
General operating conditions.
156/260
DS12505 Rev 5
STM32MP157C/F
Electrical characteristics
PLL1_1600, PLL2_1600 characteristics
(1)
Table 39. PLL1_1600, PLL2_1600 characteristics
Parameter Conditions
Symbol
Min
Typ
Max Unit
PLL input clock
Normal mode and Sigma delta mode
-
8
-
16
90
MHz
%
fPLL_IN
PLL input clock
duty cycle
10
-
-
PLL P,Q,R
multiplier output
clock
-
3.125
800(2) MHz
Division by 1
45
45
50
50
55
55
fPLL_P_Q_R_
Even divisions
OUT
(N multiple of 2)
PLL P,Q,R clock
duty cycle
%
[100,
[100,
(N+1)/ (N+1)/
2N] - 5 2N]
[100,
Odd divisions
(N+1)/
2N] +
5
(N not multiple of 2)
fVCO_OUT
tLOCK
PLL VCO output
PLL lock time
Lock Accuracy
-
Normal mode
800
-
1600 MHz
-
-
50
65
150
µs
170
Sigma-delta mode (CKIN ≥ 8 MHz)
(Ratio VCO
ALOCK
-
-
-
±2
%
frequency versus
target frequency at
lock)
DS12505 Rev 5
157/260
238
Electrical characteristics
STM32MP157C/F
(1)
Table 39. PLL1_1600, PLL2_1600 characteristics (continued)
Symbol
Parameter
Conditions
Min
Typ
Max Unit
VCO = 800 MHz
VCO = 1066 MHz
VCO = 1600 MHz
-
-
-
-
18(3)
14(3)
12(3)
20(3)
-
-
fPLL_P_Q_R_OUT division = 1
to 16
Without Fractional mode
RMS cycle-to-
cycle jitter
-
±ps
fPLL_P_Q_R_OUT division = 1 VCO = 1066 MHz
to 16
-
-
VCO = 1600 MHz
-
18(3)
With Fractional mode
VCO = 800 MHz
-
-
-
-
16(3)
12(3)
10(3)
16(3)
-
-
fPLL_P_Q_R_OUT division = 1
to 16
VCO = 1066 MHz
Without Fractional mode
VCO = 1600 MHz
-
RMS period jitter
±ps
Jitter
f
PLL_P_Q_R_OUT division = 1 VCO = 1066 MHz
-
-
to 16
VCO = 1600 MHz
-
15(3)
With Fractional mode
fPLL_P_Q_R_OUT division = 1 VCO = 800 MHz
-
-
225(4)
200(4)
-
-
to 16
VCO = 1066 MHz
fPLL_IN = 8 MHz
VCO = 1600 MHz
-
100(4)
-
Without Fractional mode
Long term jitter
ps
f
PLL_P_Q_R_OUT division = 1 VCO = 800 MHz
-
-
350(4)
250(4)
-
to 16
VCO = 1066 MHz
VCO = 1600 MHz
-
-
-
fPLL_IN = 8 MHz
With Fractional mode
-
-
-
-
-
150(4)
930
PLL power
consumption on
VDD_PLL (Analog)
VCO freq = 1600 MHz
VCO freq = 800 MHz
VCO freq = 1600 MHz
VCO freq = 800 MHz
(2)
IVDD_PLL
µA
-
560
PLL power
consumption on
VDDCORE (Digital)
4200
2100
-
(2)
IVDDCORE
μA
-
1. Guaranteed by design unless otherwise specified.
2. Guaranteed by characterization results.
3. Measured on DDR high speed IO.
4. Measured on DDR high speed IO for 10000 output clock cycles.
PLL3_800, PLL4_800 characteristics
(1)
Table 40. PLL3_800, PLL4_800 characteristics
Conditions
Symbol
Parameter
Min
Typ
Max Unit
PLL input clock
-
Normal mode
4
8
-
-
16
MHz
16
Sigma delta mode
fPLL_IN
PLL input clock
duty cycle
-
10
-
90
%
158/260
DS12505 Rev 5
STM32MP157C/F
Electrical characteristics
(1)
Table 40. PLL3_800, PLL4_800 characteristics (continued)
Symbol
Parameter
Conditions
Min
Typ
Max Unit
PLL P,Q,R
multiplier output
clock
-
3.125
-
800(2) MHz
Even divisions
fPLL_P_Q_R_
45
50
55
(N multiple of 2)
OUT
PLL P,Q,R clock
duty cycle
[100,
(N+1)/
2N] +
5
%
[100,
(N+1)/ (N+1)/
2N] - 5 2N]
[100,
Odd divisions
(N not multiple of 2)
fVCO_OUT
tLOCK
PLL VCO output
PLL lock time
Lock accuracy
-
400
15
-
800
150
170
MHz
µs
Normal mode
50
65
Sigma-delta mode (CKIN ≥ 8 MHz)
25
(Ratio VCO
ALOCK
-
-
-
±2
%
frequency versus
target frequency at
lock)
VCO = 400 MHz
-
-
-
-
80(3)
50(3)
45(3)
65(3)
-
-
-
-
fPLL_P_Q_R_OUT division =
25 to 100
VCO = 600 MHz
VCO = 800 MHz
VCO = 600 MHz
Without Fractional mode
RMS cycle-to-
cycle jitter
±ps
fPLL_P_Q_R_OUT division =
25 to 100
VCO = 800 MHz
-
60(3)
-
With Fractional mode
VCO = 400 MHz
VCO = 600 MHz
VCO = 800 MHz
VCO = 600 MHz
-
-
-
-
75(3)
38(3)
30(3)
55(3)
-
-
-
-
f
PLL_P_Q_R_OUT division =
25 to 100
Without Fractional mode
RMS period jitter
±ps
Jitter
fPLL_P_Q_R_OUT division =
25 to 100
VCO = 800 MHz
-
50(3)
-
With Fractional mode
f
PLL_P_Q_R_OUT division =
VCO = 400 MHz
VCO = 600 MHz
-
-
225(4)
150(4)
-
-
25 to 100
fPLL_IN = 8 MHz
Without Fractional mode
VCO = 800 MHz
-
125(4)
-
Long term jitter
ps
f
PLL_P_Q_R_OUT division =
VCO = 400 MHz
VCO = 600 MHz
-
-
300(4)
200(4)
-
-
25 to 100
fPLL_IN = 8 MHz
With Fractional mode
VCO = 800 MHz
-
-
-
150(4)
600
-
PLL power
consumption on
VDD_PLL (Analog)
VCO freq = 800 MHz
VCO freq = 400 MHz
610
350
IVDD_PLL
µA
320
DS12505 Rev 5
159/260
238
Electrical characteristics
STM32MP157C/F
(1)
Table 40. PLL3_800, PLL4_800 characteristics (continued)
Symbol
Parameter
Conditions
VCO freq = 800 MHz
Min
Typ
Max Unit
PLL power
consumption on
VDDCORE (Digital)
-
-
2200 5250
IVDDCORE
µA
VCO freq = 400 MHz
1130
4550
1. Guaranteed by design unless otherwise specified.
2. Guaranteed by characterization results.
3. Measured on GPIO.
4. Measured on GPIO for 10000 output clock cycles.
PLL_USB (2880 MHz) characteristics
(1)
Table 41. USB_PLL characteristics
Symbol Parameter
Condition
Min
Typ
Max
Unit
fPLL_IN
PLL input clock
19.2
24
24
480
2880
-
38.4
38.4
-
MHz
MHz
MHz
MHz
µs
fPLL_INFIN PFD input clock
19.2
fPLL_OUT
PLL multiplier output clock
-
-
fVCO_OUT PLL VCO output
-
tLOCK
tPDN
PLL lock time
-
100
-
PLL power down time
10
-
-
µs
PLL in power down
5
425
5.6
2
µA
IDDA1V1_R PLL power consumption on
VDDA1V1_REG (internal connection)
EG(PLL)
f
VCO_OUT = 2880 MHz
PLL in power down
fVCO_OUT = 2880 MHz
-
4.4
-
mA
µA
-
IDDA1V8_R PLL power consumption on
VDDA1V8_REG (internal connection)
EG(PLL)
-
2
2.5
mA
1. Guaranteed by design unless otherwise specified.
PLL_DSI (2000 MHz) characteristics
(1)
Table 42. DSI_PLL characteristics
Condition
Symbol Parameter
Min
Typ
Max
Unit
fPLL_IN
PLL input clock
8
-
200
50
MHz
MHz
fPLL_INFIN PFD input clock
8
-
fPLL_OUT
PLL multiplier output clock
62.5
-
-
1000 MHz
2000 MHz
fVCO_OUT PLL VCO output
1000
tLOCK
tPDN
PLL lock time
-
5
-
-
100
-
µs
µs
PLL power down time
-
PLL in power down
2.5
400
20
500
IDD1V2_DSI PLL power consumption on
µA
VDD1V2_DSI_REG (internal connection)
_REG(PLL)
fVCO_OUT = 2000 MHz
-
1. Guaranteed by design unless otherwise specified.
160/260
DS12505 Rev 5
STM32MP157C/F
Electrical characteristics
6.3.12
PLL spread spectrum clock generation (SSCG) characteristics
The spread spectrum clock generation (SSCG) feature allows the reduction of
electromagnetic interferences (see Table 48: EMI characteristics). It is available only on the
PLL1_1600 and PLL2_1600.
Table 43. SSCG parameters constraint
Symbol
Parameter
Modulation frequency
Min
Typ
Max(1)
Unit
fMod
md
20
0.25
-
-
-
-
60
2
kHz
%
Peak modulation depth
-
MODEPER * INCSTEP
1. Guaranteed by design.
215-1
-
Equation 1
The frequency modulation period (MODEPER) is given by the equation below:
MODEPER = round[fPLL_IN ⁄ (4 × fMod)]
f
and fMod must be expressed in Hz.
PLL_IN
As an example:
If f = 1 MHz, and f
= 1 kHz, the modulation depth (MODEPER) is given by
MOD
PLL_IN
equation 1:
MODEPER = round[106 ⁄ (4 × 103)] = 250
Equation 2
Equation 2 allows the increment step (INCSTEP) calculation:
INCSTEP = round[((215 – 1) × md × PLLN) ⁄ (100 × 5 × MODEPER)]
f
must be expressed in MHz.
VCO_OUT
With a modulation depth (md) = ±2% (4% peak-to-peak), and PLLN = 240 (in MHz):
INCSTEP = round[((215 – 1) × 2 × 240) ⁄ (100 × 5 × 250)] = 126md(quantitazed)%
An amplitude quantization error may be generated because the linear modulation profile is
obtained by taking the quantized values (rounded to the nearest integer) of MODPER and
INCSTEP. As a result, the achieved modulation depth is quantized. The percentage
quantized modulation depth is given by the following formula:
mdquantized% = (MODEPER × INCSTEP × 100 × 5) ⁄ ((215 – 1) × PLLN)
As a result:
mdquantized% = (250 × 126 × 100 × 5) ⁄ ((215 – 1) × 240) = 2.002%(peak)
DS12505 Rev 5
161/260
238
Electrical characteristics
STM32MP157C/F
Figure 21 and Figure 22 show the main PLL output clock waveforms in center spread and
down spread modes, where:
F0 is f
nominal.
PLL_OUT
T
is the modulation period.
mode
md is the modulation depth.
Figure 21. PLL output clock waveforms in center spread mode
Frequency (PLL_OUT)
md
F0
md
Time
tmode
2xtmode
ai17291
Figure 22. PLL output clock waveforms in down spread mode
Frequency (PLL_OUT)
F0
2xmd
Time
tmode
2xtmode
ai17292b
6.3.13
Memory characteristics
OTP characteristics
The characteristics are given at T = -40 to 125 °C unless otherwise specified.
J
Table 44. OTP characteristics
Symbol
Parameter
Conditions
Min
Max
Unit
Programming
Reading
-
-
-
450
490
4.2
µA
µA
µA
IVDDCORE
OTP consumption on VDDCORE
PowerDown
162/260
DS12505 Rev 5
STM32MP157C/F
Electrical characteristics
Table 44. OTP characteristics (continued)
Symbol
Parameter
Conditions
Min
Max
Unit
Programming
-
-
-
-
-
10000
2200
1
µA
µA
IVDD
OTP consumption on VDD
Reading
PowerDown
µA
(1)
FOTP
OTP operating Frequency
-
-
67
MHz
Million
NB_CYCLE (2)
Maximum number of reading cycles
500
1. Guaranteed by design.
2. Guaranteed by characterization results.
DDR characteristics
DDR3, DDR3L I/O DC specifications
The following table provides input and output DC threshold values and on-die-termination
(ODT) recommended values. The conditions for the output threshold values are un-
terminated outputs loaded with 1 pF capacitor load. The ODT values are measured after
impedance calibration.
(1)
Table 45. DC specifications – DDR3 or DDR3L mode
Symbol
Parameter
DC input voltage high
Min
Typ
Max
Unit
VIH(DC)
VIL(DC)
VOH
VREF + 0.09
VSSQ - 0.3
0.8 × VDDQ
-
-
-
-
-
VDDQ
VREF - 0.09
-
V
V
V
V
DC input voltage low
DC output logic high
DC output logic low
VOL
0.2 × VDDQ
100
54
36
120
60
40
140
66
44
RTT
ILS
Input termination resistance (ODT) to VDDQ/2
Input leakage current, SSTL mode, unterminated
Ω
-
0.01
4.8
μA
1. Guaranteed by design.
LPDDR2, LPDDR3 I/O DC specifications
The following table provides input and output DC threshold values. The conditions for the
output threshold values are un-terminated outputs loaded with 1 pF capacitor load.
(1)
Table 46. DC specifications – LPDDR2 or LPDDR3 mode
Symbol
Parameter
DC input voltage high
Min
Typ
Max
Unit
VIH(DC)
VIL(DC)
VOH
VREF + 0.13
-
VDDQ
VREF - 0.13
-
V
V
DC input voltage low
DC output logic high
DC output logic low
Input leakage current
VSSQ
-
0.9 × VDDQ
-
-
V
VOL
-
-
0.1 × VDDQ
4.51
V
ILEAK
0.01
μA
DS12505 Rev 5
163/260
238
Electrical characteristics
STM32MP157C/F
1. Guaranteed by design.
6.3.14
EMC characteristics
Susceptibility tests are performed on a sample basis during device characterization.
Functional EMS (electromagnetic susceptibility)
While a simple application is executed on the device (toggling 2 LEDs through I/O ports).
the device is stressed by two electromagnetic events until a failure occurs. The failure is
indicated by the LEDs:
•
Electrostatic discharge (ESD) (positive and negative) is applied to all device pins until
a functional disturbance occurs. This test is compliant with the IEC 61000-4-2 standard.
•
FTB: a burst of fast transient voltage (positive and negative) is applied to V and V
through a 100 pF capacitor, until a functional disturbance occurs. This test is compliant
with the IEC 61000-4-4 standard.
DD
SS
A device reset allows normal operations to be resumed.
The test results are given in Table 47. They are based on the EMS levels and classes
defined in application note AN1709 available from the ST website www.st.com.
Table 47. EMS characteristics
Level/
Class
Symbol
Parameter
Conditions
Voltage limits to be applied on any I/O pin to induce a
functional disturbance
V
DD = 3.3 V, TA = +25 °C, LFBGA448,
Fmpuss_ck = 650 or 800 MHz,
Fmcu_ck = 209 MHz,
VFESD
2B
5A
Fast transient voltage burst limits to be applied
through 100 pF on VDD and VSS pins to induce a
functional disturbance
M4 core not running,
conforms to IEC 61000-4-2
VFTB
As a consequence, it is recommended to add a serial resistor (1 kΩ) located as close as
possible to the MCU to the pins exposed to noise (connected to tracks longer than 50 mm
on PCB).
Designing hardened software to avoid noise problems
EMC characterization and optimization are performed at component level with a typical
application environment and simplified MCU software. It should be noted that good EMC
performance is highly dependent on the user application and the software in particular.
Therefore it is recommended that the user applies EMC software optimization and
prequalification tests in relation with the EMC level requested for his application.
Software recommendations
The software flowchart must include the management of runaway conditions such as:
•
•
•
Corrupted program counter
Unexpected reset
Critical Data corruption (control registers...)
164/260
DS12505 Rev 5
STM32MP157C/F
Electrical characteristics
Prequalification trials
Most of the common failures (unexpected reset and program counter corruption) can be
reproduced by manually forcing a low state on the NRST pin or the Oscillator pins for 1
second.
To complete these trials, ESD stress can be applied directly on the device, over the range of
specification values. When unexpected behavior is detected, the software can be hardened
to prevent unrecoverable errors occurring (see application note AN1015 available from the
ST website www.st.com.).
Electromagnetic Interference (EMI)
The electromagnetic field emitted by the device are monitored while a simple application,
executing EEMBC code, is running. This emission test is compliant with SAE IEC61967-2
standard which specifies the test board and the pin loading.
Table 48. EMI characteristics
Max vs. [fHSE/Fmpuss_ck
]
Monitored
Symbol Parameter
Conditions
Unit
frequency band
24/650 MHz 24/800 MHz
0.1 to 30 MHz
30 to 130 MHz
130 MHz to 1 GHz
1 GHz to 2 GHz
EMI Level
5
-2
5
V
DD = 3.6 V, TA = 25 °C,
LFBGA448 package,
Fmcu_ck = 209 MHz,
M4 core not running,
-1
dBµV
-
SEMI
Peak level
19
9
22
10
3.5
conforming to IEC61967-2
3.5
6.3.15
Absolute maximum ratings (electrical sensitivity)
Based on three different tests (ESD, LU) using specific measurement methods, the device is
stressed in order to determine its performance in terms of electrical sensitivity.
Electrostatic discharge (ESD)
Electrostatic discharges (a positive then a negative pulse) are applied to the pins of each
sample according to each pin combination. This test conforms to the ANSI/ESDA/JEDEC
JS-001 and ANSI/ESDA/JEDEC JS-002 standards.
Table 49. ESD absolute maximum ratings
Maximum
Symbol
Ratings
Conditions
Packages
Class
Unit
value(1)
Electrostatic discharge
VESD(HBM) voltage (human body
model)
TA = +25 °C conforming
to ANSI/ESDA/JEDEC
JS-001
All
2
2000
V
Electrostatic discharge
VESD(CDM) voltage (charge device
model)
TA = +25 °C conforming
to ANSI/ESDA/JEDEC
JS-002
All
C1
250
1. Guaranteed by characterization results.
DS12505 Rev 5
165/260
238
Electrical characteristics
Static latchup
STM32MP157C/F
Two complementary static tests are required on three parts to assess the latchup
performance:
•
•
A supply overvoltage is applied to each power supply pin
A current injection is applied to each input, output and configurable I/O pin
These tests are compliant with JESD78 IC latchup standard.
Table 50. Electrical sensitivities
Symbol
LU
Parameter
Conditions
Class
Static latchup class
TA = +25 °C conforming to JESD78
II level A
6.3.16
I/O current injection characteristics
As a general rule, a current injection to the I/O pins, due to external voltage below V or
SS
above V (for standard, 3.3 V-capable I/O pins) should be avoided during the normal
DD
product operation. However, in order to give an indication of the robustness of the device in
cases when an abnormal injection accidentally happens, susceptibility tests are performed
on a sample basis during the device characterization.
Functional susceptibility to I/O current injection
While a simple application is executed on the device, the device is stressed by injecting
current into the I/O pins programmed in floating input mode. While current is injected into
the I/O pin, one at a time, the device is checked for functional failures.
The failure is indicated by an out of range parameter: ADC error above a certain limit (higher
than 5 LSB TUE), out of conventional limits of induced leakage current on adjacent pins (out
of –5 µA/+0 µA range), or other functional failure (for example reset, oscillator frequency
deviation).
The following tables are the compilation of the SIC1/SIC2 and functional ESD results.
Negative induced A negative induced leakage current is caused by negative injection and
positive induced leakage current by positive injection.
(1)
Table 51. I/O current injection susceptibility
Negative
injection
Positive
injection
Symbol
Description
Unit
ANA0, ANA1, DSI_D0_P, DSI_D0_N, DSI_CK_P,
DSI_CK_N, DSI_D1_P, DSI_D1_N, PA4, PA5
0
0
IINJ
mA
PG2, PG3, PG4, PH2
All other FTxx I/Os
0
5
N/A
N/A
1. Guaranteed by characterization.
6.3.17
I/O port characteristics
General input/output characteristics
166/260
DS12505 Rev 5
STM32MP157C/F
Electrical characteristics
Unless otherwise specified, the parameters given in Table 52: I/O static characteristics are
derived from tests performed under the conditions summarized in Table 13: General
operating conditions. All I/Os are CMOS and TTL compliant.
Table 52. I/O static characteristics
Symbol
Parameter
Condition
Min
Typ
Max
Unit
1.71 V < VDD < 2.7 V
2.7 V < VDD < 3.6 V
-
-
-
-
0.35 × VDD
0.3 × VDD
(1)
VIL
I/O input low level voltage
I/O input high level voltage
V
0.45 × VDD
+ 0.35
1.71 V < VDD < 3.6 V
1.71 V < VDD < 3.6 V
-
-
-
(1)
VIH
0.7 × VDD
-
-
V
TT_xx, FT_xxx and NRST I/O
input hysteresis
0.1 ×
VDD
(1)
VHYS
1.71 V < VDD < 3.6 V
-
-
mV
(6)
0 < VIN ≤ Max(VDD
)
-
-
250
3500
500
5000(4)
100
55
FT_xx input leakage current(1)
Max(VDD) < VIN ≤ 5.5 V
-
(6)(2)(3)
(6)
Ileak
0 < VIN ≤ Max(VDD
)
-
-
nA
FT_u, IO
Max(VDD) < VIN ≤ 5.5 V
-
-
(6)(3)
(6)
TT_xx input leakage current
0 < VIN ≤ Max(VDD
VIN=VSS
)
-
-
Weak pull-up equivalent
resistor(5)
RPU
25
40
kΩ
pF
Weak pull-down equivalent
resistor(5)
(6)
RPD
CIO
VIN=VDD
25
-
40
5
55
-
I/O pin capacitance
-
1. Guaranteed by design.
2. All FT_xx IO except FT_uf, FT_u.
3. VIN must be less than Max(VDD) + 3.6 V.
4. To sustain a voltage higher than MIN(VDD, VDDA, VDD3V3_USBxxx) +0.3 V, the internal pull-up and pull-down resistors must
be disabled.
5. The pull-up and pull-down resistors are designed with a true resistance in series with a switchable PMOS/NMOS. This
PMOS/NMOS contribution to the series resistance is minimal (~10% order).
6. Max(VDD) is the maximum value of all the I/O supplies.
All I/Os are CMOS and TTL compliant (no software configuration required). Their
characteristics cover more than the strict CMOS-technology or TTL parameters. The
coverage of these requirements for FT I/Os is shown in Figure 23.
DS12505 Rev 5
167/260
238
Electrical characteristics
STM32MP157C/F
Figure 23. VIL/VIH for FT I/Os
Output driving current
The GPIOs (general purpose input/outputs) can sink or source up to ±8 mA, and sink or
source up to ±20 mA (with a relaxed V /V ).
OL OH
In the user application, the number of I/O pins which can drive current must be limited to
respect the absolute maximum rating specified in Section 6.2. In particular:
•
The sum of the currents sourced by all the I/Os on V , plus the maximum Run mode
DD
consumption of the MCU sourced on V , cannot exceed the absolute maximum rating
DD
∑I
(see Table 11).
VDD
•
The sum of the currents sunk by all the I/Os on V plus the maximum Run mode
SS
consumption of the MCU sunk on V cannot exceed the absolute maximum rating
SS
∑I
(see Table 11).
VSS
Output voltage levels
Unless otherwise specified, the parameters given in Table 53 are derived from tests
performed under ambient temperature and V supply voltage conditions summarized in
DD
Table 13: General operating conditions. All I/Os are CMOS and TTL compliant.
168/260
DS12505 Rev 5
STM32MP157C/F
Electrical characteristics
(1)
Table 53. Output voltage characteristics for all I/Os except PC13, PC14, PC15 and PI8
Symbol
Parameter
Conditions(3)
Min
Max
Unit
CMOS port(2)
VOL
Output low level voltage
IIO = 8 mA
-
0.4
2.0 V ≤ VDD ≤ 3.6 V
CMOS port(2)
IIO = -8 mA
VOH
Output high level voltage
Output low level voltage
Output high level voltage
V
DD-0.4
-
0.4
-
2.0 V ≤ VDD ≤ 3.6 V
TTL port(2)
(3)
VOL
IIO = 8 mA
-
2.0 V ≤ VDD ≤ 3.6 V
TTL port(2)
(3)
VOH
IIO = -8 mA
2.4
-
2.0 V ≤ VDD ≤ 3.6 V
V
IIO = 20 mA
(3)
VOL
Output low level voltage
Output high level voltage
Output low level voltage
Output high level voltage
1.3
-
2.7 V ≤ VDD ≤ 3.6 V
I
IO = -20 mA
2.7 V ≤ VDD ≤ 3.6 V
IO = 4 mA
1.71 V ≤ VDD ≤ 3.6 V
IO = -4 mA
(3)
VOH
VDD-1.3
I
(3)
VOL
-
0.45
-
I
(3)
VOH
VDD-0.45
1.71 V ≤ VDD ≤ 3.6 V
IIO = 20 mA
-
-
0.4
0.4
2.7 V ≤ VDD ≤ 3.6 V
Output low level voltage for an FT_f
IO pin in FM+ mode
(3)
VOLFM+
I
IO = 10 mA
1.71 V ≤ VDD ≤ 3.6 V
1. The IIO current sourced or sunk by the device must always respect the absolute maximum rating specified in Table 10:
Voltage characteristics, and the sum of the currents sourced or sunk by all the I/Os (I/O ports and control pins) must always
respect the absolute maximum ratings ∑IIO.
2. TTL and CMOS outputs are compatible with JEDEC standards JESD36 and JESD52.
3. Guaranteed by design.
DS12505 Rev 5
169/260
238
Electrical characteristics
STM32MP157C/F
(1)
Table 54. Output voltage characteristics for PC13, PC14, PC15 and PI8
Symbol
Parameter
Conditions(3)
Min
Max
Unit
CMOS port(2)
VOL
Output low level voltage
IIO = 3 mA
-
0.4
2.7 V ≤ VDD ≤ 3.6 V
CMOS port(2)
IIO = -3 mA
VOH
Output high level voltage
Output low level voltage
Output high level voltage
V
DD − 0.4
-
0.4
-
2.7 V ≤ VDD ≤ 3.6 V
TTL port(2)
(3)
VOL
IIO = 3 mA
-
V
2.7 V ≤ VDD ≤ 3.6 V
TTL port(2)
(2)
VOH
IIO = -3 mA
2.4
-
2.7 V ≤ VDD ≤ 3.6 V
IIO = 1.5 mA
(2)
VOL
Output low level voltage
Output high level voltage
0.4
-
1.62 V ≤ VDD ≤ 3.6 V
I
IO = -1.5 mA
(2)
VOH
VDD − 0.4
1.62 V ≤ VDD ≤ 3.6 V
1. The IIO current sourced or sunk by the device must always respect the absolute maximum rating specified in Table 10:
Voltage characteristics, and the sum of the currents sourced or sunk by all the I/Os (I/O ports and control pins) must always
respect the absolute maximum ratings ΣIIO.
2. TTL and CMOS outputs are compatible with JEDEC standards JESD36 and JESD52.
3. Guaranteed by design.
170/260
DS12505 Rev 5
STM32MP157C/F
Speed Symbol
Electrical characteristics
Output buffer timing characteristics (HSLV option disabled)
(1)(2)
Table 55. Output timing characteristics (HSLV OFF)
Parameter
conditions
Min
Max
Unit
C = 50 pF, 2.7 V ≤ VDD ≤ 3.6 V
C = 30 pF, 2.7 V ≤ VDD ≤ 3.6 V
C = 20 pF, 2.7 V ≤ VDD ≤ 3.6 V
C = 10 pF, 2.7 V ≤ VDD ≤ 3.6 V
C = 50 pF, 1.71 V ≤ VDD ≤ 2.7 V
C = 30 pF, 1.71 V ≤ VDD ≤ 2.7 V
C = 20 pF, 1.71 V ≤ VDD ≤ 2.7 V
C = 10 pF, 1.71 V ≤ VDD ≤ 2.7 V
C = 50 pF, 2.7 V ≤ VDD ≤ 3.6 V
C = 30 pF, 2.7 V ≤ VDD ≤ 3.6 V
C = 20 pF, 2.7 V ≤ VDD ≤ 3.6 V
C = 10 pF, 2.7 V ≤ VDD ≤ 3.6 V
C = 50 pF, 1.71 V ≤ VDD ≤ 2.7 V
C = 30 pF, 1.71 V ≤ VDD ≤ 2.7 V
C = 20 pF, 1.71 V ≤ VDD ≤ 2.7 V
C = 10 pF, 1.71 V ≤ VDD ≤ 2.7 V
C = 50 pF, 2.7 V ≤ VDD ≤ 3.6 V
C = 30 pF, 2.7 V ≤ VDD ≤ 3.6 V
C = 20 pF, 2.7 V ≤ VDD ≤ 3.6 V
C = 10 pF, 2.7 V ≤ VDD ≤ 3.6 V
C = 50 pF, 1.71 V ≤ VDD ≤ 2.7 V
C = 30 pF, 1.71 V ≤ VDD ≤ 2.7 V
C = 20 pF, 1.71 V ≤ VDD ≤ 2.7 V
C = 10 pF, 1.71 V ≤ VDD ≤ 2.7 V
C = 50 pF, 2.7 V ≤ VDD ≤ 3.6 V
C = 30 pF, 2.7 V ≤ VDD ≤ 3.6 V
C = 20 pF, 2.7 V ≤ VDD ≤ 3.6 V
C = 10 pF, 2.7 V ≤ VDD ≤ 3.6 V
C = 50 pF, 1.71 V ≤ VDD ≤ 2.7 V
C = 30 pF, 1.71 V ≤ VDD ≤ 2.7 V
C = 20 pF, 1.71 V ≤ VDD ≤ 2.7 V
C = 10 pF, 1.71 V ≤ VDD ≤ 2.7 V
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
20
24
26
30
(3)
Fmax
Maximum frequency
MHz
10
11
12
13
00
13.3
11.4
10.2
8.8
23
Output high to low level
fall time and output low
to high level rise time
tr/tf(4)
ns
20
18.3
16
68
83
88
103
25
(3)
Fmax
Maximum frequency
MHz
28
30
36
01
4.9
3.9
3.3
2.7
8.1
6.5
5.7
4.6
Output high to low level
fall time and output low
to high level rise time
tr/tf(4)
ns
DS12505 Rev 5
171/260
238
Electrical characteristics
STM32MP157C/F
(1)(2)
Table 55. Output timing characteristics (HSLV OFF)
(continued)
Speed Symbol
Parameter
conditions
Min
Max
Unit
C = 50 pF, 2.7 V ≤ VDD ≤ 3.6 V(5)
C = 30 pF, 2.7 V ≤ VDD ≤ 3.6 V(5)
C = 20 pF, 2.7 V ≤ VDD ≤ 3.6 V(5)
C = 10 pF, 2.7 V ≤ VDD ≤ 3.6 V(5)
C = 50 pF, 1.71 V ≤ VDD ≤ 2.7 V(5)
C = 30 pF, 1.71 V ≤ VDD ≤ 2.7 V(5)
C = 20 pF, 1.71 V ≤ VDD ≤ 2.7 V(5)
C = 10 pF, 1.71 V ≤ VDD ≤ 2.7 V(5)
C = 50 pF, 2.7 V ≤ VDD ≤ 3.6 V(5)
C = 30 pF, 2.7 V ≤ VDD ≤ 3.6 V(5)
C = 20 pF, 2.7 V ≤ VDD ≤ 3.6 V(5)
C = 10 pF, 2.7 V ≤ VDD ≤ 3.6 V(5)
C = 50 pF, 1.71 V ≤ VDD ≤ 2.7 V(5)
C = 30 pF, 1.71 V ≤ VDD ≤ 2.7 V(5)
C = 20 pF, 1.71 V ≤ VDD ≤ 2.7 V(5)
C = 10 pF, 1.71 V ≤ VDD ≤ 2.7 V(5)
C = 50 pF, 2.7 V ≤ VDD ≤ 3.6 V(5)
C = 30 pF, 2.7 V ≤ VDD ≤ 3.6 V(5)
C = 20 pF, 2.7 V ≤ VDD ≤ 3.6 V(5)
C = 10 pF, 2.7 V ≤ VDD ≤ 3.6 V(5)
C = 50 pF, 1.71 V ≤ VDD ≤ 2.7 V(5)
C = 30 pF, 1.71 V ≤ VDD ≤ 2.7 V(5)
C = 20 pF, 1.71 V ≤ VDD ≤ 2.7 V(5)
C = 10 pF, 1.71 V ≤ VDD ≤ 2.7 V(5)
C = 50 pF, 2.7 V ≤ VDD ≤ 3.6 V(5)
C = 30 pF, 2.7 V ≤ VDD ≤ 3.6 V(5)
C = 20 pF, 2.7 V ≤ VDD ≤ 3.6 V(5)
C = 10 pF, 2.7 V ≤ VDD ≤ 3.6 V(5)
C = 50 pF, 1.71 V ≤ VDD ≤ 2.7 V(5)
C = 30 pF, 1.71 V ≤ VDD ≤ 2.7 V(5)
C = 20 pF, 1.71 V ≤ VDD ≤ 2.7 V(5)
C = 10 pF, 1.71 V ≤ VDD ≤ 2.7 V(5)
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
94
124
144
166
53
(3)
Fmax
Maximum frequency
MHz
66
72
81
10
3.5
2.7
2.2
1.7
6.3
4.8
4
Output high to low level
fall time and output low
to high level rise time
tr/tf(4)
ns
MHz
ns
3.2
110
150
185
210
62
(3)
Fmax
Maximum frequency
70
79
94
11
3
2.2
1.8
1.3
5.3
4
Output high to low level
fall time and output low
to high level rise time
tr/tf(4)
3.3
2.5
1. Guaranteed by design.
2. GPIO under VSW domain (PC13, PC14, PC15, PI8) are frequency limited. The maximum frequency is 2 MHz with a
maximum load of 30 pF. Only one I/O at a time can be used as GPIO output and these I/Os must not be used as a current
source (e.g to drive a LED). For theses IOs, the speed value must be kept to (default) 00.
172/260
DS12505 Rev 5
STM32MP157C/F
Electrical characteristics
3. The maximum frequency is defined with the following conditions: (tr+tf) ≤ 2/3, skew ≤ 1/20 T and 45% < duty cycle < 55%.
4. The fall and rise times are defined between 90% and 10% and between 10% and 90% of the output waveform,
respectively.
5. Compensation system enabled.
Output buffer timing characteristics (IO structure with _h, HSLV option
enabled)
The HSLVEN_xx bits of SYSCFG_IOCTRLSETR register (together with OTP bit
PRODUCT_BELOW_2V5) can be used to optimize the I/O speed when the product voltage
is below 2.5 V typ. (2.7 V max.).
(1)
Table 56. Output timing characteristics (HSLV ON, _h IO structure)
Speed Symbol
Parameter
conditions
Min
Max
Unit
C = 50 pF, 1.71 V ≤ VDD ≤ 2.7 V
C = 30 pF, 1.71 V ≤ VDD ≤ 2.7 V
C = 20 pF, 1.71 V ≤ VDD ≤ 2.7 V
C = 10 pF, 1.71 V ≤ VDD ≤ 2.7 V
C = 50 pF, 1.71 V ≤ VDD ≤ 2.7 V
C = 30 pF, 1.71 V ≤ VDD ≤ 2.7 V
C = 20 pF, 1.71 V ≤ VDD ≤ 2.7 V
C = 10 pF, 1.71 V ≤ VDD ≤ 2.7 V
C = 50 pF, 1.71 V ≤ VDD ≤ 2.7 V
C = 30 pF, 1.71 V ≤ VDD ≤ 2.7 V
C = 20 pF, 1.71 V ≤ VDD ≤ 2.7 V
C = 10 pF, 1.71 V ≤ VDD ≤ 2.7 V
C = 50 pF, 1.71 V ≤ VDD ≤ 2.7 V
C = 30 pF, 1.71 V ≤ VDD ≤ 2.7 V
C = 20 pF, 1.71 V ≤ VDD ≤ 2.7 V
C = 10 pF, 1.71 V ≤ VDD ≤ 2.7 V
C = 50 pF, 1.71 V ≤ VDD ≤ 2.7 V(4)
C = 30 pF, 1.71 V ≤ VDD ≤ 2.7 V(4)
C = 20 pF, 1.71 V ≤ VDD ≤ 2.7 V(4)
C = 10 pF, 1.71 V ≤ VDD ≤ 2.7 V(4)
C = 50 pF, 1.71 V ≤ VDD ≤ 2.7 V(4)
C = 30 pF, 1.71 V ≤ VDD ≤ 2.7 V(4)
C = 20 pF, 1.71 V ≤ VDD ≤ 2.7 V(4)
C = 10 pF, 1.71 V ≤ VDD ≤ 2.7 V(4)
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
20
22
(2)
Fmax
Maximum frequency
MHz
24
28
00
9.9
8.1
7.1
5.8
58
Output high to low level
fall time and output low
to high level rise time
tr/tf(3)
ns
MHz
ns
79
(2)
Fmax
Maximum frequency
90
100
5.7
4.2
3.5
2.7
71
01
Output high to low level
fall time and output low
to high level rise time
tr/tf(3)
101
126
162
4.7
3.3
2.7
1.9
(2)
Fmax
Maximum frequency
MHz
10
Output high to low level
fall time and output low
to high level rise time
tr/tf(3)
ns
DS12505 Rev 5
173/260
238
Electrical characteristics
STM32MP157C/F
(1)
Table 56. Output timing characteristics (HSLV ON, _h IO structure) (continued)
Speed Symbol
Parameter
conditions
Min
Max
Unit
C = 50 pF, 1.71 V ≤ VDD ≤ 2.7 V(4)
C = 30 pF, 1.71 V ≤ VDD ≤ 2.7 V(4)
C = 20 pF, 1.71 V ≤ VDD ≤ 2.7 V(4)
C = 10 pF, 1.71 V ≤ VDD ≤ 2.7 V(4)
C = 50 pF, 1.71 V ≤ VDD ≤ 2.7 V(4)
C = 30 pF, 1.71 V ≤ VDD ≤ 2.7 V(4)
C = 20 pF, 1.71 V ≤ VDD ≤ 2.7 V(4)
C = 10 pF, 1.71 V ≤ VDD ≤ 2.7 V(4)
-
-
-
-
-
-
-
-
77
111
145
172
4.3
3
(2)
Fmax
Maximum frequency
MHz
11
Output high to low level
fall time and output low
to high level rise time
tr/tf(3)
ns
2.3
1.6
1. Guaranteed by design.
2. The maximum frequency is defined with the following conditions: (tr+tf) ≤ 2/3, skew ≤ 1/20 T and 45% < duty cycle < 55%.
3. The fall and rise times are defined between 90% and 10% and between 10% and 90% of the output waveform,
respectively.
4. Compensation system enabled.
Output buffer timing characteristics (IO structure with _vh, HSLV option
enabled)
The HSLVEN_xx bits of SYSCFG_IOCTRLSETR register (together with OTP bit
PRODUCT_BELOW_2V5) can be used to optimize the I/O speed when the product voltage
is below 2.5 V typ. (2.7 V max.).
(1)
Table 57. Output timing characteristics (HSLV ON, _vh IO structure)
Speed Symbol
Parameter
conditions
Min
Max
Unit
C = 50 pF, 1.71 V ≤ VDD ≤ 2.7 V
C = 30 pF, 1.71 V ≤ VDD ≤ 2.7 V
C = 20 pF, 1.71 V ≤ VDD ≤ 2.7 V
C = 10 pF, 1.71 V ≤ VDD ≤ 2.7 V
C = 50 pF, 1.71 V ≤ VDD ≤ 2.7 V
C = 30 pF, 1.71 V ≤ VDD ≤ 2.7 V
C = 20 pF, 1.71 V ≤ VDD ≤ 2.7 V
C = 10 pF, 1.71 V ≤ VDD ≤ 2.7 V
-
-
-
-
-
-
-
-
36
41
(2)
Fmax
Maximum frequency
MHz
46
55
00
9.2
7.4
6.5
5.2
Output high to low level
fall time and output low
to high level rise time
tr/tf(3)
ns
174/260
DS12505 Rev 5
STM32MP157C/F
Electrical characteristics
(1)
Table 57. Output timing characteristics (HSLV ON, _vh IO structure) (continued)
Speed Symbol
Parameter
conditions
Min
Max
Unit
C = 50 pF, 1.71 V ≤ VDD ≤ 2.7 V
C = 30 pF, 1.71 V ≤ VDD ≤ 2.7 V
C = 20 pF, 1.71 V ≤ VDD ≤ 2.7 V
C = 10 pF, 1.71 V ≤ VDD ≤ 2.7 V
C = 50 pF, 1.71 V ≤ VDD ≤ 2.7 V
C = 30 pF, 1.71 V ≤ VDD ≤ 2.7 V
C = 20 pF, 1.71 V ≤ VDD ≤ 2.7 V
C = 10 pF, 1.71 V ≤ VDD ≤ 2.7 V
C = 50 pF, 1.71 V ≤ VDD ≤ 2.7 V(4)
C = 30 pF, 1.71 V ≤ VDD ≤ 2.7 V(4)
C = 20 pF, 1.71 V ≤ VDD ≤ 2.7 V(4)
C = 10 pF, 1.71 V ≤ VDD ≤ 2.7 V(4)
C = 50 pF, 1.71 V ≤ VDD ≤ 2.7 V(4)
C = 30 pF, 1.71 V ≤ VDD ≤ 2.7 V(4)
C = 20 pF, 1.71 V ≤ VDD ≤ 2.7 V(4)
C = 10 pF, 1.71 V ≤ VDD ≤ 2.7 V(4)
C = 50 pF, 1.71 V ≤ VDD ≤ 2.7 V(4)
C = 30 pF, 1.71 V ≤ VDD ≤ 2.7 V(4)
C = 20 pF, 1.71 V ≤ VDD ≤ 2.7 V(4)
C = 10 pF, 1.71 V ≤ VDD ≤ 2.7 V(4)
C = 50 pF, 1.71 V ≤ VDD ≤ 2.7 V(4)
C = 30 pF, 1.71 V ≤ VDD ≤ 2.7 V(4)
C = 20 pF, 1.71 V ≤ VDD ≤ 2.7 V(4)
C = 10 pF, 1.71 V ≤ VDD ≤ 2.7 V(4)
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
55
71
(2)
Fmax
Maximum frequency
MHz
85
100
6.1
4.7
3.9
3
01
Output high to low level
fall time and output low
to high level rise time
tr/tf(3)
ns
MHz
ns
68
95
(2)
Fmax
Maximum frequency
118
162
4.9
3.5
2.8
2.1
80
10
Output high to low level
fall time and output low
to high level rise time
tr/tf(3)
121
162
245
4.2
2.8
2.1
1.4
(2)
Fmax
Maximum frequency
MHz
11
Output high to low level
fall time and output low
to high level rise time
tr/tf(3)
ns
1. Guaranteed by design.
2. The maximum frequency is defined with the following conditions: (tr+tf) ≤ 2/3, skew ≤ 1/20 T and 45% < Duty cycle < 55%.
3. The fall and rise times are defined between 90% and 10% and between 10% and 90% of the output waveform,
respectively.
4. Compensation system enabled.
6.3.18
NRST and NRST_CORE pin characteristics
The NRST and NRST_CORE pins input driver uses CMOS technology. It is connected to a
permanent pull-up resistor, R (see Table 52: I/O static characteristics).
PU
Unless otherwise specified, the parameters given in Table 58 are derived from tests
performed under the ambient temperature and V supply voltage conditions summarized
DD
in Table 13: General operating conditions.
DS12505 Rev 5
175/260
238
Electrical characteristics
Symbol
STM32MP157C/F
Table 58. NRST and NRST_CORE pin characteristics
Parameter
Conditions
Min
Typ
Max Unit
Weak pull-up equivalent
resistor(1)
(2)
RPU
VIN = VSS
30
40
-
50
50
-
kΩ
NRST/NRST_CORE Input
filtered pulse
(2)
VF(NRST)
1.71 V < VDD < 3.6 V
1.71 V < VDD < 3.6 V
-
ns
NRST/NRST_CORE Input
not filtered pulse
(2)
VNF(NRST)
350
-
1. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution to
the series resistance must be minimum (~10% order).
2. Guaranteed by design.
Figure 24. Recommended NRST and NRST_CORE pin protection
V
DD
External
reset circuit
(1)
R
PU
(2)
Internal Reset
NRST
Filter
0.1 μF
STM32
ai14132d
1. The reset network protects the device against parasitic resets.
2. The user must ensure that the level on the NRST/NRST_CORE pin can go below the VIL(NRST) max level
specified in Table 58. Otherwise the reset is not taken into account by the device.
6.3.19
FMC characteristics
Unless otherwise specified, the parameters given in Table 59 to Table 72 for the FMC
interface are derived from tests performed under the ambient temperature, F
(F
)
hclk6
mc_hclk
frequency and V supply voltage conditions summarized in Table 13: General operating
DD
conditions, with the following configuration:
•
•
Output speed is set to OSPEEDRy[1:0] = 11
Measurement points are done at CMOS levels: 0.5×V
DD
Refer to Section 6.3.17: I/O port characteristics for more details on the input/output
characteristics.
176/260
DS12505 Rev 5
STM32MP157C/F
Electrical characteristics
Asynchronous waveforms and timings
Figure 25 through Figure 28 represent asynchronous waveforms and Table 59 through
Table 66 provide the corresponding timings. The results shown in these tables are obtained
with the following FMC configuration:
•
•
•
•
AddressSetupTime = 0x1
AddressHoldTime = 0x1
DataSetupTime = 0x1 (except for asynchronous NWAIT mode, DataSetupTime = 0x5)
DataHoldTime = 0x1 (1×T
operations)
for read operations and 2×T
for write
fmc_ker_ck
fmc_ker_ck
•
•
•
ByteLaneSetup = 0x1
BusTurnAroundDuration = 0x0
Capacitive load C = 30 pF
L
In all the timing tables, the T
is the fmc_ker_ck clock period.
fmc_ker_ck
Figure 25. Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms
t
w(NE)
FMC_NE
t
t
t
h(NE_NOE)
w(NOE)
v(NOE_NE)
FMC_NOE
FMC_NWE
tv(A_NE)
t
h(A_NOE)
FMC_A[25:0]
Address
tv(BL_NE)
t
h(BL_NOE)
FMC_NBL[1:0]
t
h(Data_NE)
t
t
su(Data_NOE)
h(Data_NOE)
t
su(Data_NE)
Data
FMC_D[15:0]
t
v(NADV_NE)
t
w(NADV)
(1)
FMC_NADV
FMC_NWAIT
th(NE_NWAIT)
tsu(NWAIT_NE)
MS32753V1
1. Mode 2/B, C and D only. In Mode 1, FMC_NADV is not used.
DS12505 Rev 5
177/260
238
Electrical characteristics
STM32MP157C/F
(1)
Table 59. Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings
Symbol
tw(NE)
tv(NOE_NE)
tw(NOE)
th(NE_NOE)
tv(A_NE)
Parameter
Min
Max
Unit
FMC_NE low time
3Tfmc_ker_ck-1
3Tfmc_ker_ck+0.5
FMC_NEx low to FMC_NOE low
FMC_NOE low time
0
1
2Tfmc_ker_ck-1
2Tfmc_ker_ck+1
FMC_NOE high to FMC_NE high hold time
FMC_NEx low to FMC_A valid
Address hold time after FMC_NOE high
Data to FMC_NEx high setup time
Data to FMC_NOEx high setup time
Data hold time after FMC_NOE high
Data hold time after FMC_NEx high
FMC_NEx low to FMC_NADV low
FMC_NADV low time
Tfmc_ker_ck-1
-
-
1
th(A_NOE)
2Tfmc_ker_ck-1
-
ns
tsu(Data_NE)
tsu(Data_NOE)
th(Data_NOE)
th(Data_NE)
tv(NADV_NE)
tw(NADV)
Tfmc_ker_ck+15
-
16
0
0
-
-
-
-
0
-
Tfmc_ker_ck+1
1. Guaranteed by characterization results.
(1)(2)
Table 60. Asynchronous non-multiplexed SRAM/PSRAM/NOR read - NWAIT timings
Symbol Parameter Min Max
tw(NE)
Unit
FMC_NE low time
7Tfmc_ker_ck-0.5 7Tfmc_ker_ck+1
6Tfmc_ker_ck-0.5 6Tfmc_ker_ck+1
tw(NOE)
FMC_NWE low time
tw(NWAIT)
FMC_NWAIT low time
Tfmc_ker_ck
7Tfmc_ker_ck+2
5Tfmc_ker_ck
-
-
-
ns
tsu(NWAIT_NE)
th(NE_NWAIT)
FMC_NWAIT valid before FMC_NEx high
FMC_NEx hold time after FMC_NWAIT invalid
1. Guaranteed by characterization results.
2. NWAIT pulse width is equal to 1 AHB cycle.
178/260
DS12505 Rev 5
STM32MP157C/F
Electrical characteristics
Figure 26. Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms
t
w(NE)
FMC_NEx
FMC_NOE
FMC_NWE
t
t
w(NWE)
t
h(NE_NWE)
v(NWE_NE)
t
th(A_NWE)
v(A_NE)
FMC_A[25:0]
Address
t
t
v(BL_NE)
h(BL_NWE)
FMC_NBL[1:0]
NBL
t
t
v(Data_NE)
h(Data_NWE)
Data
FMC_D[15:0]
t
v(NADV_NE)
t
w(NADV)
(1)
FMC_NADV
FMC_NWAIT
th(NE_NWAIT)
tsu(NWAIT_NE)
MS32754V1
1. Mode 2/B, C and D only. In Mode 1, FMC_NADV is not used.
(1)
Table 61. Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings
Symbol Parameter Min Max
tw(NE) 4Tfmc_ker_ck-0.5 4Tfmc_ker_ck+1
tv(NWE_NE) Tfmc_ker_ck-0.5 Tfmc_ker_ck+1
tw(NWE) Tfmc_ker_ck-0.5 Tfmc_ker_ck+0.5
th(NE_NWE)
tv(A_NE)
th(A_NWE)
tv(BL_NE)
Unit
FMC_NE low time
FMC_NEx low to FMC_NWE low
FMC_NWE low time
FMC_NWE high to FMC_NE high hold time
FMC_NEx low to FMC_A valid
Address hold time after FMC_NWE high
FMC_NEx low to FMC_BL valid
FMC_BL hold time after FMC_NWE high
Data to FMC_NEx low to Data valid
Data hold time after FMC_NWE high
FMC_NEx low to FMC_NADV low
FMC_NADV low time
2Tfmc_ker_ck-0.5
-
-
0
3Tfmc_ker_ck-1
-
ns
-
0.5
th(BL_NWE)
tv(Data_NE)
th(Data_NWE)
tv(NADV_NE)
tw(NADV)
3Tfmc_ker_ck-0.5
-
-
2.5
3Tfmc_ker_ck-1
-
0.5
-
-
Tfmc_ker_ck+0.5
1. Guaranteed by characterization results.
DS12505 Rev 5
179/260
238
Electrical characteristics
STM32MP157C/F
(1)(2)
Table 62. Asynchronous non-multiplexed SRAM/PSRAM/NOR write - NWAIT timings
Symbol
tw(NE)
Parameter
FMC_NE low time
Min
Max
Unit
8Tfmc_ker_ck-0.5
5Tfmc_ker_ck-0.5
8Tfmc_ker_ck+4
6Tfmc_ker_ck
8Tfmc_ker_ck+0.5
tw(NWE)
FMC_NWE low time
5Tfmc_ker_ck+1
ns
tsu(NWAIT_NE)
th(NE_NWAIT)
FMC_NWAIT valid before FMC_NEx high
FMC_NEx hold time after FMC_NWAIT invalid
-
-
1. Guaranteed by characterization results.
2. NWAIT pulse width is equal to 1 AHB cycle.
Figure 27. Asynchronous multiplexed PSRAM/NOR read waveforms
t
w(NE)
FMC_ NE
FMC_NOE
t
t
h(NE_NOE)
v(NOE_NE)
t
w(NOE)
t
FMC_NWE
t
h(A_NOE)
v(A_NE)
FMC_ A[25:16]
Address
NBL
t
t
v(BL_NE)
h(BL_NOE)
FMC_ NBL[1:0]
t
h(Data_NE)
t
su(Data_NE)
t
t
t
h(Data_NOE)
v(A_NE)
Address
su(Data_NOE)
Data
FMC_ AD[15:0]
t
t
h(AD_NADV)
v(NADV_NE)
t
w(NADV)
FMC_NADV
FMC_NWAIT
th(NE_NWAIT)
tsu(NWAIT_NE)
MS32755V1
180/260
DS12505 Rev 5
STM32MP157C/F
Electrical characteristics
(1)
Table 63. Asynchronous multiplexed PSRAM/NOR read timings
Symbol
tw(NE)
tv(NOE_NE)
ttw(NOE)
th(NE_NOE)
tv(A_NE)
tv(NADV_NE)
tw(NADV)
Parameter
Min
Max
Unit
FMC_NE low time
4Tfmc_ker_ck-0.5
2Tfmc_ker_ck-0.5
Tfmc_ker_ck-0.5
Tfmc_ker_ck-1
-
4Tfmc_ker_ck+1
FMC_NEx low to FMC_NOE low
FMC_NOE low time
2Tfmc_ker_ck+1
Tfmc_ker_ck+0.5
FMC_NOE high to FMC_NE high hold time
FMC_NEx low to FMC_A valid
FMC_NEx low to FMC_NADV low
FMC_NADV low time
-
3
1.5
0.5
Tfmc_ker_ck
Tfmc_ker_ck+1
ns
FMC_AD(address) valid hold time after
FMC_NADV high
th(AD_NADV)
T
fmc_ker_ck-3
-
-
Address held
until next read
operation
th(A_NOE)
Address hold time after FMC_NOE high
tsu(Data_NE)
tsu(Data_NOE)
th(Data_NE)
Data to FMC_NEx high setup time
Data to FMC_NOE high setup time
Data hold time after FMC_NEx high
Data hold time after FMC_NOE high
Tfmc_ker_ck+15
-
-
16
0
-
th(Data_NOE)
0
-
1. Guaranteed by characterization results.
(1)
Table 64. Asynchronous multiplexed PSRAM/NOR read-NWAIT timings
Symbol
tw(NE)
Parameter
FMC_NE low time
Min
Max
Unit
7Tfmc_ker_ck-0.5
5Tfmc_ker_ck-0.5
7Tfmc_ker_ck+2
8Tfmc_ker_ck+1
tw(NOE)
FMC_NWE low time
6Tfmc_ker_ck+1
-
ns
tsu(NWAIT_NE)
FMC_NWAIT valid before FMC_NEx high
FMC_NEx hold time after FMC_NWAIT
invalid
th(NE_NWAIT)
5Tfmc_ker_ck
-
1. Guaranteed by characterization results.
DS12505 Rev 5
181/260
238
Electrical characteristics
STM32MP157C/F
Figure 28. Asynchronous multiplexed PSRAM/NOR write waveforms
t
w(NE)
FMC_ NEx
FMC_NOE
t
t
w(NWE)
t
h(NE_NWE)
v(NWE_NE)
FMC_NWE
t
t
h(A_NWE)
v(A_NE)
FMC_ A[25:16]
Address
t
t
v(BL_NE)
h(BL_NWE)
FMC_ NBL[1:0]
NBL
v(Data_NADV)
Data
t
t
h(Data_NWE)
t
v(A_NE)
Address
FMC_ AD[15:0]
t
t
h(AD_NADV)
v(NADV_NE)
t
w(NADV)
FMC_NADV
FMC_NWAIT
th(NE_NWAIT)
tsu(NWAIT_NE)
MS32756V1
182/260
DS12505 Rev 5
STM32MP157C/F
Electrical characteristics
(1)
Table 65. Asynchronous multiplexed PSRAM/NOR write timings
Parameter Min
5Tfmc_ker_ck-0.5 5Tfmc_ker_ck+1
Tfmc_ker_ck-0.5 Tfmc_ker_ck+1
2Tfmc_ker_ck-1 2Tfmc_ker_ck+0.5
Symbol
tw(NE)
tv(NWE_NE)
tw(NWE)
th(NE_NWE)
tv(A_NE)
Max
Unit
FMC_NE low time
FMC_NEx low to FMC_NWE low
FMC_NWE low time
FMC_NWE high to FMC_NE high hold time
FMC_NEx low to FMC_A valid
2Tfmc_ker_ck-0.5
-
-
0.5
tv(NADV_NE) FMC_NEx low to FMC_NADV low
tw(NADV) FMC_NADV low time
0
1
Tfmc_ker_ck+0.5
Tfmc_ker_ck+1
-
ns
th(AD_NADV) FMC_AD(address) valid hold time after FMC_NADV high Tfmc_ker_ck+0.5
Address held
th(A_NWE)
Address hold time after FMC_NWE high
until next write
operation
-
th(BL_NWE)
tv(BL_NE)
FMC_BL hold time after FMC_NWE high
FMC_NEx low to FMC_BL valid
3Tfmc_ker_ck+0.5
-
-
0.5
tv(Data_NADV) FMC_NADV high to Data valid
th(Data_NWE) Data hold time after FMC_NWE high
1. Guaranteed by characterization results.
-
Tfmc_ker_ck+4
-
3Tfmc_ker_ck+0.5
(1)
Table 66. Asynchronous multiplexed PSRAM/NOR write-NWAIT timings
Symbol
Parameter
Min
Max
Unit
tw(NE)
FMC_NE low time
9Tfmc_ker_ck-0.5
9Tfmc_ker_ck+0.5
ns
tw(NWE)
FMC_NWE low time
6Tfmc_ker_ck-0.5
8Tfmc_ker_ck+4
6Tfmc_ker_ck
6Tfmc_ker_ck+1
tsu(NWAIT_NE)
th(NE_NWAIT)
FMC_NWAIT valid before FMC_NEx high
FMC_NEx hold time after FMC_NWAIT invalid
-
-
1. Guaranteed by characterization results.
Synchronous waveforms and timings
Figure 29 through Figure 32 represent synchronous waveforms and Table 67 through
Table 70 provide the corresponding timings. The results shown in these tables are obtained
with the following FMC configuration:
•
•
•
•
•
BurstAccessMode = FMC_BurstAccessMode_Enable
MemoryType = FMC_MemoryType_CRAM
WriteBurst = FMC_WriteBurst_Enable
CLKDivision = 1
DataLatency = 1 for NOR Flash; DataLatency = 0 for PSRAM
DS12505 Rev 5
183/260
238
Electrical characteristics
STM32MP157C/F
In all the timing tables, the T
is the fmc_ker_ck clock period, with the following
fmc_ker_ck
FMC_CLK maximum values:
•
•
For 2.7 V < V < 3.6 V, FMC_CLK = 130 MHz at 20 pF
DD
For 1.71 V < V < 1.9 V, FMC_CLK = 95 MHz at 20 pF
DD
Figure 29. Synchronous multiplexed NOR/PSRAM read timings
BUSTURN = 0
t
t
w(CLK)
w(CLK)
FMC_CLK
Data latency = 0
d(CLKL-NExL)
t
td(CLKH-NExH)
FMC_NEx
t
t
d(CLKL-NADVL)
d(CLKL-NADVH)
FMC_NADV
t
td(CLKH-AIV)
d(CLKL-AV)
FMC_A[25:16]
t
td(CLKH-NOEH)
d(CLKL-NOEL)
FMC_NOE
t
t
t
h(CLKH-ADV)
su(ADV-CLKH)
d(CLKL-ADIV)
t
t
t
su(ADV-CLKH)
d(CLKL-ADV)
h(CLKH-ADV)
FMC_AD[15:0]
AD[15:0]
t
D1
D2
t
su(NWAITV-CLKH)
h(CLKH-NWAITV)
FMC_NWAIT
(WAITCFG = 1b,
WAITPOL + 0b)
t
t
su(NWAITV-CLKH)
h(CLKH-NWAITV)
FMC_NWAIT
(WAITCFG = 0b,
WAITPOL + 0b)
t
t
h(CLKH-NWAITV)
su(NWAITV-CLKH)
MS32757V1
184/260
DS12505 Rev 5
STM32MP157C/F
Symbol
Electrical characteristics
(1)
Table 67. Synchronous multiplexed NOR/PSRAM read timings
Parameter
Min
Max
Unit
tw(CLK)
FMC_CLK period
R×Tfmc_ker_ck-1(2)
-
td(CLKL-NExL) FMC_CLK low to FMC_NEx low (x=0..2)
td(CLKH_NExH) FMC_CLK high to FMC_NEx high (x= 0…2)
td(CLKL-NADVL) FMC_CLK low to FMC_NADV low
td(CLKL-NADVH) FMC_CLK low to FMC_NADV high
-
1
R×Tfmc_ker_ck/2+0.5(2)
-
-
1.5
1
-
1
-
td(CLKL-AV)
td(CLKH-AIV)
FMC_CLK low to FMC_Ax valid (x=16…25)
FMC_CLK high to FMC_Ax invalid (x=16…25)
-
R×Tfmc_ker_ck/2+1.5(2)
td(CLKL-NOEL) FMC_CLK low to FMC_NOE low
td(CLKH-NOEH) FMC_CLK high to FMC_NOE high
-
2
-
ns
R×Tfmc_ker_ck/2+0.5(2)
td(CLKL-ADV)
FMC_CLK low to FMC_AD[15:0] valid
-
1
1.5
-
td(CLKL-ADIV) FMC_CLK low to FMC_AD[15:0] invalid
tsu(ADV-CLKH) FMC_A/D[15:0] valid data before FMC_CLK high
th(CLKH-ADV) FMC_A/D[15:0] valid data after FMC_CLK high
tsu(NWAIT-CLKH) FMC_NWAIT valid before FMC_CLK high
th(CLKH-NWAIT) FMC_NWAIT valid after FMC_CLK high
3
-
1
-
3
-
1.5
-
1. Guaranteed by characterization results.
2. Clock ratio R = (FMC_CLK period / fmc_ker_ck period).
DS12505 Rev 5
185/260
238
Electrical characteristics
STM32MP157C/F
Figure 30. Synchronous multiplexed PSRAM write timings
BUSTURN = 0
t
t
w(CLK)
w(CLK)
FMC_CLK
Data latency = 0
d(CLKL-NExL)
t
t
d(CLKH-NExH)
FMC_NEx
t
t
d(CLKL-NADVL)
d(CLKL-NADVH)
FMC_NADV
t
d(CLKH-AIV)
t
t
d(CLKL-AV)
FMC_A[25:16]
t
d(CLKH-NWEH)
d(CLKL-NWEL)
FMC_NWE
t
t
t
d(CLKL-ADIV)
t
d(CLKL-Data)
d(CLKL-Data)
d(CLKL-ADV)
FMC_AD[15:0]
AD[15:0]
D1
D2
FMC_NWAIT
(WAITCFG = 0b,
WAITPOL + 0b)
t
t
h(CLKH-NWAITV)
su(NWAITV-CLKH)
t
d(CLKH-NBLH)
FMC_NBL
MS32758V1
186/260
DS12505 Rev 5
STM32MP157C/F
Symbol
Electrical characteristics
(1)
Table 68. Synchronous multiplexed PSRAM write timings
Parameter
Min
Max
Unit
tw(CLK)
FMC_CLK period, VDD range = 2.7 to 3.6 V
FMC_CLK low to FMC_NEx low (x=0..2)
FMC_CLK high to FMC_NEx high (x= 0…2)
FMC_CLK low to FMC_NADV low
R×Tfmc_ker_ck-1(2)
-
1
-
td(CLKL-NExL)
td(CLKH-NExH)
td(CLKL-NADVL)
-
R×Tfmc_ker_ck/2+0.5(2)
-
1.5
-
td(CLKL-NADVH) FMC_CLK low to FMC_NADV high
1
td(CLKL-AV)
td(CLKH-AIV)
FMC_CLK low to FMC_Ax valid (x=16…25)
FMC_CLK high to FMC_Ax invalid (x=16…25)
FMC_CLK low to FMC_NWE low
-
1
-
R×Tfmc_ker_ck/2+1.5(2)
td(CLKL-NWEL)
t(CLKH-NWEH)
td(CLKL-ADV)
td(CLKL-ADIV)
td(CLKL-DATA)
td(CLKL-NBLL)
td(CLKH-NBLH)
-
1
-
ns
FMC_CLK high to FMC_NWE high
R×Tfmc_ker_ck/2+0.5(2)
FMC_CLK low to FMC_AD[15:0] valid
FMC_CLK low to FMC_AD[15:0] invalid
FMC_A/D[15:0] valid data after FMC_CLK low
FMC_CLK low to FMC_NBL low
-
1.5
-
1
-
3
-
1
FMC_CLK high to FMC_NBL high
R×Tfmc_ker_ck/2+0.5(2)
-
tsu(NWAIT-CLKH) FMC_NWAIT valid before FMC_CLK high
th(CLKH-NWAIT) FMC_NWAIT valid after FMC_CLK high
3
-
1.5
-
1. Guaranteed by characterization results.
2. Clock ratio R = (FMC_CLK period / fmc_ker_ck period).
DS12505 Rev 5
187/260
238
Electrical characteristics
STM32MP157C/F
Figure 31. Synchronous non-multiplexed NOR/PSRAM read timings
t
t
w(CLK)
w(CLK)
FMC_CLK
t
t
d(CLKH-NExH)
d(CLKL-NExL)
Data latency = 0
d(CLKL-NADVH)
FMC_NEx
t
t
d(CLKL-NADVL)
FMC_NADV
FMC_A[25:0]
t
t
d(CLKH-AIV)
d(CLKL-AV)
t
t
d(CLKH-NOEH)
d(CLKL-NOEL)
FMC_NOE
t
t
su(DV-CLKH)
h(CLKH-DV)
su(DV-CLKH)
t
t
h(CLKH-DV)
FMC_D[15:0]
FMC_NWAIT
D1
D2
t
t
su(NWAITV-CLKH)
h(CLKH-NWAITV)
(WAITCFG = 1b,
WAITPOL + 0b)
t
t
h(CLKH-NWAITV)
su(NWAITV-CLKH)
FMC_NWAIT
(WAITCFG = 0b,
WAITPOL + 0b)
t
t
su(NWAITV-CLKH)
h(CLKH-NWAITV)
MS32759V1
(1)
Table 69. Synchronous non-multiplexed NOR/PSRAM read timings
Symbol
tw(CLK)
Parameter
Min
Max
Unit
FMC_CLK period
R×Tfmc_ker_ck-1(2)
-
1
-
t(CLKL-NExL)
FMC_CLK low to FMC_NEx low (x=0..2)
FMC_CLK high to FMC_NEx high (x= 0…2)
FMC_CLK low to FMC_NADV low
-
td(CLKH-NExH)
td(CLKL-NADVL)
R×Tfmc_ker_ck/2+0.5(2)
-
1.5
-
td(CLKL-NADVH) FMC_CLK low to FMC_NADV high
1
td(CLKL-AV)
FMC_CLK low to FMC_Ax valid (x=16…25)
FMC_CLK high to FMC_Ax invalid (x=16…25)
FMC_CLK low to FMC_NOE low
-
1
-
td(CLKH-AIV)
td(CLKL-NOEL)
td(CLKH-NOEH)
tsu(DV-CLKH)
th(CLKH-DV)
R×Tfmc_ker_ck/2+1.5(2)
ns
-
2
-
FMC_CLK high to FMC_NOE high
R×Tfmc_ker_ck/2+1.5(2)
FMC_D[15:0] valid data before FMC_CLK high
FMC_D[15:0] valid data after FMC_CLK high
FMC_NWAIT valid before FMC_CLK high
3
1
-
-
t(NWAIT-CLKH)
3
-
th(CLKH-NWAIT) FMC_NWAIT valid after FMC_CLK high
1. Guaranteed by characterization results.
1.5
-
188/260
DS12505 Rev 5
STM32MP157C/F
Electrical characteristics
2. Clock ratio R = (FMC_CLK period / fmc_ker_ck period).
Figure 32. Synchronous non-multiplexed PSRAM write timings
t
t
w(CLK)
w(CLK)
FMC_CLK
t
t
d(CLKL-NExL)
FMC_NEx
d(CLKH-NExH)
Data latency = 0
d(CLKL-NADVH)
t
t
d(CLKL-NADVL)
FMC_NADV
FMC_A[25:0]
FMC_NWE
t
d(CLKH-AIV)
t
t
d(CLKL-AV)
td(CLKH-NWEH)
d(CLKL-NWEL)
t
t
d(CLKL-Data)
d(CLKL-Data)
FMC_D[15:0]
D1
D2
FMC_NWAIT
(WAITCFG = 0b, WAITPOL + 0b)
FMC_NBL
t
t
d(CLKH-NBLH)
su(NWAITV-CLKH)
t
h(CLKH-NWAITV)
MS32760V1
DS12505 Rev 5
189/260
238
Electrical characteristics
STM32MP157C/F
(1)
Table 70. Synchronous non-multiplexed PSRAM write timings
Symbol
t(CLK)
Parameter
Min
Max
Unit
FMC_CLK period
R×Tfmc_ker_ck -1(2)
-
1
-
td(CLKL-NExL)
t(CLKH-NExH)
td(CLKL-NADVL)
FMC_CLK low to FMC_NEx low (x=0..2)
FMC_CLK high to FMC_NEx high (x= 0…2)
FMC_CLK low to FMC_NADV low
-
R×Tfmc_ker_ck/2+0.5(2)
-
1.5
-
td(CLKL-NADVH) FMC_CLK low to FMC_NADV high
1
td(CLKL-AV)
FMC_CLK low to FMC_Ax valid (x=16…25)
FMC_CLK high to FMC_Ax invalid (x=16…25)
FMC_CLK low to FMC_NWE low
-
1
-
td(CLKH-AIV)
td(CLKL-NWEL)
td(CLKH-NWEH)
td(CLKL-Data)
td(CLKL-NBLL)
td(CLKH-NBLH)
R×Tfmc_ker_ck/2+1.5(2)
ns
-
1
-
FMC_CLK high to FMC_NWE high
FMC_D[15:0] valid data after FMC_CLK low
FMC_CLK low to FMC_NBL low
R×Tfmc_ker_ck/2+0.5(2)
-
3
-
1
FMC_CLK high to FMC_NBL high
R×Tfmc_ker_ck/2+0.5(2)
-
tsu(NWAIT-CLKH) FMC_NWAIT valid before FMC_CLK high
th(CLKH-NWAIT) FMC_NWAIT valid after FMC_CLK high
3
-
1.5
-
1. Guaranteed by characterization results.
2. Clock ratio R = (FMC_CLK period / fmc_ker_ck period).
NAND controller waveforms and timings
Figure 33 through Figure 36 represent synchronous waveforms, and Table 71 and Table 72
provide the corresponding timings. The results shown in this table are obtained with the
following FMC configuration:
•
•
•
•
•
•
•
•
•
•
•
FMC_SetupTime = 0x01
FMC_WaitSetupTime = 0x03
FMC_HoldSetupTime = 0x02
FMC_HiZSetupTime = 0x01
Bank = FMC_Bank_NAND
MemoryDataWidth = FMC_MemoryDataWidth_16b
ECC = FMC_ECC_Enable
ECCPageSize = FMC_ECCPageSize_512Bytes
TCLRSetupTime = 0
TARSetupTime = 0
C = 30 pF
L
In all timing tables, the T
is the fmc_ker_ck clock period.
fmc_ker_ck
190/260
DS12505 Rev 5
STM32MP157C/F
Electrical characteristics
Figure 33. NAND controller waveforms for read access
FMC_NCEx
ALE (FMC_A17)
CLE (FMC_A16)
FMC_NWE
t
th(NOE-ALE)
d(ALE-NOE)
FMC_NOE (NRE)
FMC_D[15:0]
t
t
h(NOE-D)
su(D-NOE)
MS32767V1
Figure 34. NAND controller waveforms for write access
FMC_NCEx
ALE (FMC_A17)
CLE (FMC_A16)
t
t
h(NWE-ALE)
d(ALE-NWE)
FMC_NWE
FMC_NOE (NRE)
FMC_D[15:0]
t
t
h(NWE-D)
v(NWE-D)
MS32768V1
DS12505 Rev 5
191/260
238
Electrical characteristics
STM32MP157C/F
Figure 35. NAND controller waveforms for common memory read access
FMC_NCEx
ALE (FMC_A17)
CLE (FMC_A16)
t
t
h(NOE-ALE)
d(ALE-NOE)
FMC_NWE
FMC_NOE
t
w(NOE)
t
t
h(NOE-D)
su(D-NOE)
FMC_D[15:0]
MS32769V1
Figure 36. NAND controller waveforms for common memory write access
FMC_NCEx
ALE (FMC_A17)
CLE (FMC_A16)
t
t
t
h(NOE-ALE)
d(ALE-NOE)
w(NWE)
FMC_NWE
FMC_N OE
t
d(D-NWE)
t
t
v(NWE-D)
h(NWE-D)
FMC_D[15:0]
MS32770V1
(1)
Table 71. Switching characteristics for NAND Flash read cycles
Symbol
tw(N0E)
tsu(D-NOE)
th(NOE-D)
td(ALE-NOE)
th(NOE-ALE)
Parameter
FMC_NOE low width
Min
Max
Unit
4Tfmc_ker_ck-1
4Tfmc_ker_ck+1
FMC_D[15-0] valid data before FMC_NOE high
FMC_D[15-0] valid data after FMC_NOE high
FMC_ALE valid before FMC_NOE low
FMC_NWE high to FMC_ALE invalid
11
-
0
-
ns
-
2Tfmc_ker_ck+1
-
3Tfmc_ker_ck+0.5
1. Guaranteed by characterization results.
192/260
DS12505 Rev 5
STM32MP157C/F
Electrical characteristics
(1)
Table 72. Switching characteristics for NAND Flash write cycles
Symbol
tw(NWE)
Parameter
FMC_NWE low width
Min
Max
Unit
4Tfmc_ker_ck-1
0
4Tfmc_ker_ck+1
tv(NWE-D)
FMC_NWE low to FMC_D[15-0] valid
FMC_NWE high to FMC_D[15-0] invalid
FMC_D[15-0] valid before FMC_NWE high
FMC_ALE valid before FMC_NWE low
FMC_NWE high to FMC_ALE invalid
-
th(NWE-D)
td(D-NWE)
td(ALE-NWE)
th(NWE-ALE)
3Tfmc_ker_ck
4Tfmc_ker_ck-3
-
-
ns
-
2Tfmc_ker_ck+1
-
3Tfmc_ker_ck+0.5
1. Guaranteed by characterization results.
6.3.20
QUADSPI interface characteristics
Unless otherwise specified, the parameters given in Table 73 and Table 74 for QUADSPI
are derived from tests performed under the ambient temperature, F frequency and
axiss_ck
V
supply voltage conditions summarized in Table 13: General operating conditions, with
DD
the following configuration:
•
•
•
•
Output speed is set to OSPEEDRy[1:0] = 11
Measurement points are done at CMOS levels: 0.5×V
I/O compensation cell enabled
DD
HSLV activated when V ≤ 2.7 V
DD
Refer to Section 6.3.17: I/O port characteristics for more details on the input/output alternate
function characteristics.
Table 73. QUADSPI characteristics in SDR mode
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
2.7 V ≤ VDD < 3.6 V
CL = 20 pF
-
-
166
Fck1/t(CLK)
QUADSPI clock frequency
MHz
1.71 V < VDD <3.6 V
CL = 15 pF
-
-
90
tw(CLKH)
tw(CLKL)
ts(IN)
t(CLK)/2 - 0.5
-
-
t(CLK)/2 + 0.5
QUADSPI clock high and low
time
-
t(CLK)/2 - 0.5
t(CLK)/2 + 0.5
Data input setup time
Data input hold time
Data output valid time
Data output hold time
-
-
-
-
1.25
2.75
-
-
-
-
ns
th(IN)
-
tv(OUT)
th(OUT)
1
-
1.5
-
0
DS12505 Rev 5
193/260
238
Electrical characteristics
STM32MP157C/F
Table 74. QUADSPI characteristics in DDR mode
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
2.7 V < VDD < 3.6 V
CL=20 pF
-
-
90
QUADSPI clock
frequency
Fck1/t(CLK)
MHz
1.71 V < VDD < 3.6 V
CL=15 pF
-
-
90
tw(CLKH)
tw(CLKL)
-
t(CLK)/2 - 0.5
-
-
t(CLK)/2 + 0.5
QUADSPI clock high and
low time
-
t(CLK)/2 - 0.5
t(CLK)/2 + 0.5
tsr(IN), tsf(IN) Data input setup time
hr(IN), thf(IN) Data input hold time
-
-
0.5
2.75
-
-
-
-
t
-
DHHC = 0
1
1.5
ns
tvr(OUT)
,
Data output valid time
Data output hold time
DHHC = 1
tvf(OUT)
-
t(CLK)/4+1
t(CLK)/4+1.5
Pres = 1, 2...
DHHC = 0
0
-
-
-
-
thr(OUT)
,
DHHC = 1
thf(OUT)
t
(CLK)/4
Pres = 1, 2...
Figure 37. QUADSPI timing diagram - SDR mode
tr(CLK)
t(CLK)
tw(CLKH)
tw(CLKL)
tf(CLK)
Clock
tv(OUT)
th(OUT)
Data output
IO0
IO1
IO2
ts(IN)
th(IN)
Data input
IO0
IO1
IO2
MSv36878V2
Figure 38. QUADSPI timing diagram - DDR mode
tr(CLK)
t(CLK)
tw(CLKH)
tw(CLKL)
tf(CLK)
Clock
tvf(OUT) thr(OUT)
IO0
tvr(OUT)
thf(OUT)
IO3
Data output
IO1
IO2
IO4
tsr(IN)thr(IN)
IO5
tsf(IN) thf(IN)
Data input
IO0
IO1
IO2
IO3
IO4
IO5
MSv36879V3
194/260
DS12505 Rev 5
STM32MP157C/F
Electrical characteristics
6.3.21
Delay block (DLYB) characteristics
Unless otherwise specified, the parameters given in Table 75 for the delay block are derived
from tests performed under the ambient temperature, f
frequency and V supply
rcc_c_ck
DD
voltage summarized in Table 13: General operating conditions.
Table 75. Dynamics characteristics: Delay block characteristics
Symbol
Parameter
Initial delay
Unit Delay
Conditions
Min
Typ
Max
Unit
tinit
t∆
-
-
900
42
1200
46
1500
50
ps
6.3.22
16-bit ADC characteristics
Unless otherwise specified, the parameters given in Table 76 are derived from tests
performed under the ambient temperature, f frequency and V supply voltage
pclk2
DDA
conditions summarized in Table 13: General operating conditions.
(1)(2)
Table 76. ADC characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VDDA
Analog power supply
-
1.62
2
-
3.6
VDDA ≥ 2 V
-
VDDA
VREF+
VREF-
fADC
Positive reference voltage
Negative reference voltage
ADC clock frequency
V
VDDA < 2 V
VDDA
-
VSSA
BOOST = 1
BOOST = 0
0.12
0.12
-
-
36
20
2 V ≤ VDDA ≤3.3 V
MHz
DS12505 Rev 5
195/260
238
Electrical characteristics
STM32MP157C/F
(1)(2)
Table 76. ADC characteristics
Conditions
(continued)
Min
Symbol
Parameter
Typ
Max
Unit
16-bit resolution
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
3.60
4.00
4.50
5.00
6.00
2.00
2.20
2.50
2.80
3.30
2.55
2.80
3.11
3.50
4.00
1.82
2.00
2.22
2.50
2.86
3.6
14-bit resolution
12-bit resolution
10-bit resolution
8-bit resolution
16-bit resolution
14-bit resolution
12-bit resolution
10-bit resolution
8-bit resolution
16-bit resolution
14-bit resolution
12-bit resolution
10-bit resolution
8-bit resolution
16-bit resolution
14-bit resolution
12-bit resolution
10-bit resolution
8-bit resolution
Sampling rate for Fast
channels, BOOST = 1,
fADC = 36 MHz,
sampling time = 1.5 cycles
Sampling rate for Fast
channels, BOOST = 0,
fADC = 20 MHz,
sampling time = 1.5 cycles
fS
MSPS
Sampling rate for Slow
channels, BOOST = 1,
fADC = 28 MHz,
sampling time = 2.5 cycles
Sampling rate for Slow
channels, BOOST = 0,
fADC = 20 MHz,
sampling time = 2.5 cycles
f
ADC = 36 MHz
MHz
fTRIG
External trigger frequency
Conversion voltage range
16-bit resolution
10
1/fADC
(3)
VAIN
-
VREF+
V
Common mode input
voltage
VREF/2-
10%
VREF/2+
10%
VCMIV
-
VREF/2
4
Internal sample and hold
capacitor
CADC
-
-
-
-
pF
tADCREG_
ADC LDO startup time
ADC power-up time
-
5
1
10
µs
STUP
tSTAB
LDO already started
1/fADC
196/260
DS12505 Rev 5
STM32MP157C/F
Symbol
Electrical characteristics
(1)(2)
Table 76. ADC characteristics
Conditions
(continued)
Min
Parameter
Typ
Max
Unit
Offset and linearity
calibration time
tCAL
-
16384
tOFF_CAL Offset calibration time
-
1280
CKMODE = 00
CKMODE = 01
CKMODE = 10
CKMODE = 11
CKMODE = 00
CKMODE = 01
CKMODE = 10
CKMODE = 11
1.5
2
-
2.5
2.5
Trigger conversion latency
-
for regular and injected
tLATR
channels without aborting
-
-
2.5
the conversion
-
2.5
-
-
2.25
3.5
1/fADC
3
-
Trigger conversion latency
for regular and injected
channels when a regular
conversion is aborted
3.5
tLATRINJ
-
-
3.5
-
-
3.25
810.5
tS
Sampling time
-
1.5
-
Total conversion time
(including sampling time)
tCONV
N-bit resolution
ts + N/2(4)
FS = 3.6 Msps, BOOST = 1
FS = 1 Msps, BOOST = 0
FS = 3.6 Msps, BOOST = 1
FS = 1 Msps, BOOST = 0
FS = 3.6 Msps, BOOST = 1
FS = 1 Msps, BOOST = 0
FS = 3.6 Msps, BOOST = 1
-
-
-
-
-
-
-
1900
460
260
140
1700
445
160
-
-
-
-
-
-
-
ADC consumption from
VDDA supply (differential)
IDDA(ADC)
IDDA(REF)
IDDA(ADC)
ADC consumption from
VREF+ (differential)
μA
ADC consumption from
VDDA supply (single-ended)
ADC consumption from
IDDA(REF) VREF+ supply (single-
ended)
FS = 1 Msps, BOOST = 0
-
75
-
1. Guaranteed by design.
2. Voltage BOOSTER on ADC switches must be used for VDDA < 2.4 V (switches inside IO).
3. Depending on the package, VREF- can be internally connected to VSSA
4. 9 to 818 cycles @ 14-bit mode.
.
DS12505 Rev 5
197/260
238
Electrical characteristics
STM32MP157C/F
Table 77. Minimum sampling time versus RAIN with 47 pF PCB capacitor
(1)
up to 125 °C and V
= 1.6 V
DDA
Fast
Slow
Resolution(2)
RAIN (Ω)
channels(3) (ns)
channels(4) (ns)
16 bits
47(5)
47
107
90.8
967
108
128
161
76.7
81.5
89.8
107
132
177
2.36
329
462
62.5
66.2
72.7
85.4
106
140
187
258
367
537
776
1130
1600
166
144
151
157
171
192
125
127
134
146
169
205
264
345
488
103
106
112
121
137
168
209
279
381
552
786
1140
1600
68
14 bits
100
150
220(5)
47
68
100
150
220
330
470
680
1000(5)
47
12 bits
68
100
150
220
330
470
680
1000
1500
2200
3300
4700(5)
10 bits
198/260
DS12505 Rev 5
STM32MP157C/F
Electrical characteristics
Table 77. Minimum sampling time versus RAIN with 47 pF PCB capacitor
(1)
up to 125 °C and V
= 1.6 V (continued)
DDA
Fast
Slow
Resolution(2)
RAIN (Ω)
channels(3) (ns)
channels(4) (ns)
47
68
48.7
51.4
56.4
65.8
80.4
106
82.4
84.6
88.7
95.7
108
100
150
220
330
130
470
139
160
680
189
208
8 bits
1000
1500
2200
3300
4700
6800
10000
15000
2200(5)
269
284
390
405
562
572
827
840
1170
1670
2440
3660
5360
1170
1670
2430
3630
5310
1. Guaranteed by design.
2. The tolerance is 8 LSB for 16-bit, 4 LSB for 14-bit, 2 LSB for 12-bit, 10-bit and 8-bit conversions.
3. On ADC1, fast channels are PA6, PA7, PB0, PB1, PC4, PC5, PF11, PF12.
On ADC2, fast channels are PA6, PA7, PB0, PB1, PC4, PC5, PF13, PF14.
4. Slow channels are all ADC inputs except the fast channels.
5. Maximum external input impedance value authorized for the given resolution.
DS12505 Rev 5
199/260
238
Electrical characteristics
STM32MP157C/F
(1)(2)(3)(4)(5)(6)(7)
Min
Table 78. ADC accuracy
Conditions(8)
Symbol
Parameter
Typ(9)
Max
Unit
BOOST = 1
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
±5
±7
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Single ended
Total
unadjusted
error
BOOST = 0
BOOST = 1
BOOST = 0
BOOST = 1
BOOST = 0
BOOST = 1
BOOST = 0
BOOST = 1
BOOST = 0
BOOST = 1
BOOST = 0
BOOST = 1
BOOST = 0
BOOST = 1
BOOST = 0
BOOST = 1
BOOST = 0
BOOST = 1
BOOST = 0
BOOST = 1
BOOST = 0
BOOST = 1
BOOST = 0
BOOST = 1
BOOST = 0
BOOST = 1
BOOST = 0
ET(10)
±6
Differential
±5
3
Single ended
Differential
1
Differential
linearity error
ED
±LSB
8
2
±6
Single ended
Differential
±4
Integral
linearity error
EL
±6
±4
12.5
12.75
13.3
13.7
77.5
78.75
82
Effective
number of
bits
Single ended
Differential
ENOB(11)
SINAD(11)
SNR(11)
THD(11)
bits
(2 MSPS)
Signal-to-
noise and
distortion
ratio
Single ended
Differential
(2 MSPS)
84.2
77.6
79
Single ended
Differential
Signal-to-
noise ratio
dB
82.4
84.3
-85
-88
-90
-93
(2 MSPS)
Single ended
Differential
Total
harmonic
distortion
1. Guaranteed by characterization.
2. ADC DC accuracy values are measured after internal calibration.
3. ADC accuracy versus negative injection current: injecting negative current on any analog input pins should be avoided as
this significantly reduces the accuracy of the conversion being performed on another analog input. It is recommended to
add a Schottky diode (pin to ground) to analog pins which may potentially inject negative current.
4. The above table gives the ADC performance in 16-bit mode.
5. Dual Simultaneous mode is limited to 12-bit.
6. Dual mode consisting in an injected conversion (reset) occurring during another (regular) conversion is forbidden.
7. Dual Interleaved 16-bit/14-bit/12-bit modes can work if the delay between the 2 ADCs is as specified in Table 79.
200/260
DS12505 Rev 5
STM32MP157C/F
Electrical characteristics
8. ADC clock frequency ≤36 MHz, 2 V ≤ VDDA ≤ 3.3 V, 1.6 V ≤ VREF+ ≤ VDDA, BOOSTEN (for I/O) = 1.
9. VDDA = VREF+ = 3.3 V, 25 °C.
10. ET, ED, EL are specified for [2 V ≤ VDDA ≤ 3.3 V with 2 V ≤ VREF+ ≤ VDDA] and [1.6V ≤ VDDA ≤ 2 V with 1.6V ≤ VREF+
≤
V
DDA].
11. ENOB, SINAD, SNR and THD are specified for VDDA = VREF+ = 3.3 V.
Table 79. Minimum delay for interleaved conversion versus resolution
16-bit Mode
14-bit mode
12-bit Mode
Delay
ADC1/ADC2
(clock cycles)
Delay
ADC1/ADC2
(clock cycles)
Delay
ADC1/ADC2
(clock cycles)
Data rate
(MSPS)
Data rate
(MSPS)
Data rate
(MSPS)
Boost Fclk (MHz)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1.5
1.5
1.5
1.5
1.5
1.5
2.5
2.5
3.5
3.5
4.5
4.5
4.5
4.5
5.5
5.5
5.5
5.5
5.5
5.5
4.5
4.5
4.5
4.5
4.5
4.5
5.5
1.0
2.0
1.5
2.0
1.7
2.0
1.8
2.0
1.8
2.0
1.8
2.0
2.2
2.3
2.1
2.3
2.4
2.6
2.7
2.9
3.5
3.7
3.8
4.0
4.2
4.3
3.9
1.5
1.5
1.5
1.5
1.5
1.5
1.5
2.5
2.5
3.5
3.5
4.5
4.5
4.5
4.5
4.5
4.5
4.5
4.5
4.5
3.5
3.5
3.5
4.5
4.5
4.5
4.5
1.0
2.0
1.5
2.0
1.7
2.0
2.3
2.0
2.3
2.0
2.2
2.0
2.2
2.3
2.5
2.7
2.8
3.0
3.2
3.3
4.2
4.4
4.6
4.0
4.2
4.3
4.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
2.5
2.5
2.5
3.5
3.5
3.5
3.5
3.5
3.5
3.5
3.5
3.5
3.5
3.5
3.5
3.5
3.5
3.5
3.5
1.0
2.0
1.5
2.0
2.5
2.0
2.3
2.7
2.3
2.5
2.8
2.4
2.6
2.8
3.0
3.2
3.4
3.6
3.8
4.0
4.2
4.4
4.6
4.8
5.0
5.2
5.4
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
DS12505 Rev 5
201/260
238
Electrical characteristics
STM32MP157C/F
Table 79. Minimum delay for interleaved conversion versus resolution (continued)
16-bit Mode 14-bit mode 12-bit Mode
Delay
ADC1/ADC2
(clock cycles)
Delay
ADC1/ADC2
(clock cycles)
Delay
ADC1/ADC2
(clock cycles)
Data rate
(MSPS)
Data rate
(MSPS)
Data rate
(MSPS)
Boost Fclk (MHz)
1
1
1
1
1
1
1
1
1
28
29
30
31
32
33
34
35
36
5.5
5.5
5.5
5.5
5.5
5.5
5.5
5.5
5.5
4.0
4.1
4.3
4.4
4.6
4.7
4.9
5.0
5.1
4.5
4.5
4.5
4.5
4.5
4.5
4.5
4.5
4.5
4.7
4.8
5.0
5.2
5.3
5.5
5.7
5.8
6.0
3.5
3.5
3.5
3.5
3.5
3.5
3.5
3.5
3.5
5.6
5.8
6.0
6.2
6.4
6.6
6.8
7.0
7.2
Note:
ADC accuracy vs. negative injection current: injecting a negative current on any analog
input pins should be avoided as this significantly reduces the accuracy of the conversion
being performed on another analog input. It is recommended to add a Schottky diode (pin to
ground) to analog pins which may potentially inject negative currents.
Any positive injection current within the limits specified for I
and ∑I
in
INJ(PIN)
INJ(PIN)
Section 6.2 does not affect the ADC accuracy.
202/260
DS12505 Rev 5
STM32MP157C/F
Electrical characteristics
Figure 39. ADC accuracy characteristics
V
V
DDA
4096
REF+
[1LSB
=
(or
depending on package)]
IDEAL
4096
E
G
4095
4094
4093
(2)
E
T
(3)
7
6
5
4
3
2
1
(1)
E
E
O
L
E
D
1L SB
IDEAL
7
0
V
1
2
3
456
4093 4094 4095 4096
V
DDA
SSA
ai14395c
1. Example of an actual transfer curve.
2. Ideal transfer curve.
3. End point correlation line.
4. ET = Total Unadjusted Error: maximum deviation between the actual and the ideal transfer curves.
EO = Offset Error: deviation between the first actual transition and the first ideal one.
EG = Gain Error: deviation between the last ideal transition and the last actual one.
ED = Differential Linearity Error: maximum deviation between actual steps and the ideal one.
EL = Integral Linearity Error: maximum deviation between any actual transition and the end point
correlation line.
Figure 40. Typical connection diagram using the ADC
STM32
V
DD
Sample and hold ADC
V
T
converter
0.6 V
(1)
AIN
(1)
R
R
ADC
AINx
12-bit
converter
V
0.6 V
T
V
AIN
C
(1)
ADC
C
parasitic
I
1 μA
L
ai17534b
1. Refer to Table 76 for the values of RAIN, RADC and CADC.
2. Cparasitic represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the
pad capacitance (roughly 5 pF). A high Cparasitic value downgrades conversion accuracy. To remedy this,
f
ADC should be reduced.
DS12505 Rev 5
203/260
238
Electrical characteristics
STM32MP157C/F
General PCB design guidelines
PCB design guidelines are provided in AN5031 “Getting started with STM32MP1 Series
hardware development.” available from the ST website www.st.com.
6.3.23
DAC electrical characteristics
(1)(2)
Table 80. DAC characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VDDA
Analog supply voltage
-
-
1.8
3.3
-
3.6
VREF+
Positive reference voltage
1.80
VDDA
V
Negative reference
voltage
VREF-
-
-
5
VSSA
-
-
-
connected to
VSSA
DAC output
-
-
buffer ON, Not
valid in Sample
& Hold mode
RL
Resistive Load
connected to
VDDA
kΩ
25
RO
Output Impedance
DAC output buffer OFF
10.3
-
13
-
16
Output impedance sample
and hold mode, output
buffer ON
VDD = 2.7 V
1.6
DAC output
buffer ON
RBON
kΩ
kΩ
VDD = 2.0 V
VDD = 2.7 V
VDD = 2.0 V
-
-
-
-
-
-
2.6
Output impedance sample
and hold mode, output
buffer OFF
17.8
18.7
DAC output
buffer OFF
RBOFF
CL
DAC output buffer OFF
Sample and Hold mode
-
-
-
50
1
pF
µF
Capacitive Load
CSH
0.1
VDDA
-
DAC output buffer ON
0.2
0
-
-
0.2(3)
Voltage on DAC_OUT
output
VDAC_OUT
V
VREF
DAC output buffer OFF
Normal mode,
+
Settling time (full scale: for
a 12-bit code transition
between the lowest and
the highest input codes
when DAC_OUT reaches
the final value of ±1LSB)
DAC output
buffer ON
±1 LSB
-
2
-
tSETTLING
µs
Normal mode,
DAC output buffer OFF,
+/-1LSB, Cload ≤ 10 pF
-
-
2
Normal mode,
DAC output buffer ON
Wakeup time from off
-
-
-
5
2
7.5
5
state (setting the Enx bit in
the DAC Control register)
until the ±1LSB final value
(4)
tWAKEUP
µs
Normal mode,
DAC output buffer OFF
Normal mode
DAC output buffer ON
PSRR
VDDA supply rejection ratio
-80
-28
dB
204/260
DS12505 Rev 5
STM32MP157C/F
Symbol
Electrical characteristics
(1)(2)
Table 80. DAC characteristics
Parameter Conditions
(continued)
Min
Typ
Max
Unit
DACMCR.MODEx[2:0] =
100/101
Sampling time in Sample
and Hold mode
-
0.7
-
(BUFFER ON)
CSH=100nF
(Code transition between
the lowest input code and
the highest input code
when DAC_OUT reaches
final value ± 1LSB)
DACMCR.MODEx[2:0] = 110
(BUFFER OFF)
tSAMP
ms
-
-
-
11.5
0.3
-
-
-
DACMCR.MODEx[2:0] = 111
(INTERNAL BUFFER OFF)
Internal sample and hold
capacitor
CIint
-
2.2
pF
µV
VREF+ = 3.6 V
VREF+ = 1.8 V
-
-
450
213
-
-
Middle code offset for 1
trim code step
Voffset
No load, middle
code (0x800)
-
-
360
490
-
-
DAC output
buffer ON
No load, worst
code (0xF1C)
DAC quiescent
No load,
middle/worst
code (0x800)
IDDA(DAC)
DAC output
buffer OFF
consumption from VDDA
-
-
20
-
-
360×TON/
Sample and Hold mode,
CSH = 100 nF
(TON+TOFF)
(5)
No load, middle
code (0x800)
-
-
170
170
-
-
µA
DAC output
buffer ON
No load, worst
code (0xF1C)
No load,
middle/worst
code (0x800)
DAC output
buffer OFF
-
-
-
160
-
-
-
DAC consumption from
VREF+
IDDV(DAC)
170×TON/
Sample and Hold mode, Buffer
ON, CSH = 100 nF (worst code)
(TON+TOFF)
(5)
170×TON/
Sample and Hold mode, Buffer
OFF, CSH = 100 nF (worst code)
(TON+TOFF)
(5)
1. Guaranteed by design.
2. Unless otherwise noted, CL ≤ 50 pF with RL ≥ 5 kΩ when DAC output buffer is ON, or CL ≤ 10 pF with no RL when DAC
output buffer is OFF.
3. Since VREF+ must always be ≤ VDDA, maximum VDAC_OUT = minimum value between Max(VREF+) and Max(VDDA-0.2)
4. In buffered mode, the output can overshoot above the final value for low input code (starting from the minimum value).
5. TON is the refresh phase duration, while TOFF is the hold phase duration. Refer to the product reference manual for more
details.
DS12505 Rev 5
205/260
238
Electrical characteristics
STM32MP157C/F
(1)
Table 81. DAC accuracy
Symbol
Parameter
Conditions
Min
Typ(2)
Max
Unit
Differential
non
DNL
-
-
-
±2
-
LSB
linearity(3)
Integral non
linearity(4)
INL
-
-
±4
±5
-
-
LSB
LSB
VREF+
3.6 V
=
=
DAC output
buffer ON
Offset error
at code
Offset
VREF+
1.8 V
-
-
±7
±8
-
-
0x800 (4)
DAC output buffer OFF
Offset error
at code
Offset1
Gain
DAC output buffer OFF
-
-
±5
-
LSB
%
0x001(5)
Gain error(6)
-
-
±1
-
-
Total
unadjusted
error
VREF+=3.6 V
VREF+=1.8 V
±10
DAC output
buffer ON
TUECal
LSB
-
-
±8
-
-
Signal-to-
SNR
THD
1 kHz, BW = 500 kHz
1kHz
67.8
dB
dB
noise ratio(7)
Total
harmonic
-
-
-
-78.6
67.5
10.9
-
-
-
distorsion(7)
Signal-to-
noise and
distortion
ratio(7)
SINAD
ENOB
1 kHz
1 kHz
dB
Effective
number of
bits
bits
1. Unless otherwise noted, CL ≤ 50 pF with RL ≥ 5 kΩ when DAC output buffer is ON, or CL ≤ 10 pF with no RL when DAC
output buffer is OFF.
2. Guaranteed by characterization.
3. Difference between two consecutive codes minus 1 LSB.
4. Difference between measured the value at Code i and the value measured at Code i on a line drawn between Code 0 and
last Code 4095.
5. Difference between the value measured at Code (0x001) and the ideal value.
6. Difference between the ideal slope of the transfer function and the measured slope computed from code 0x000 and 0xFFF
when the buffer is OFF, and from code giving 0.2 V and (VREF+ - 0.2 V) when the buffer is ON.
7. Signal is -0.5dBFS with Fsampling=1 MHz.
206/260
DS12505 Rev 5
STM32MP157C/F
Electrical characteristics
Figure 41. 12-bit buffered /non-buffered DAC
Buffered/Non-buffered DAC
Buffer(1)
R
L
DAC_OUTx
12-bit
digital to
analog
converter
C
L
ai17157V3
1. The DAC integrates an output buffer that can be used to reduce the output impedance and to drive external
loads directly without the use of an external operational amplifier. The buffer can be bypassed by
configuring the BOFFx bit in the DAC_CR register.
6.3.24
Voltage reference buffer characteristics
(1)
Table 82. VREFBUF characteristics
Symbol
Parameter
Conditions
VSCALE = 000
Min
Typ
Max
Unit
2.8
2.4
3.3
3.6
3.6
VSCALE = 001
VSCALE = 010
VSCALE = 011
VSCALE = 000
VSCALE = 001
VSCALE = 010
VSCALE = 011
VSCALE = 000
VSCALE = 001
VSCALE = 010
VSCALE = 011
-
Normal mode
2.1
-
3.6
1.8
-
3.6
VDDA
Analog supply voltage
1.62
1.62
1.62
1.62
2.498
2.047
1.800
1.500
-
-
2.80
2.40
2.10
1.80
2.502
2.051
1.807
1.507
Degraded mode(2)
-
-
2.500
2.049
1.804
1.504
Normal mode
@30 °C
V
@Iload = 10 uA
VDDA = 3.3 V
VDDA
220 mV
-
VSCALE = 000
VSCALE = 001
VSCALE = 010
VSCALE = 011
-
-
-
-
VDDA
VDDA
VDDA
VDDA
VREFBUF Voltage Reference
Buffer Output
_OUT
VDDA
-
220 mV
Degraded mode(2)
VDDA
-
220 mV
VDDA
-
220 mV
TRIM
CL
Trim step resolution
Load capacitor
-
-
-
-
-
±0.05
1
-
%
0.5
1.50
uF
DS12505 Rev 5
207/260
238
Electrical characteristics
STM32MP157C/F
(1)
Table 82. VREFBUF characteristics (continued)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Equivalent Serial
Resistor of CL
esr
-
-
-
-
-
-
2
Ω
Iload
Static load current
-
-
-
-
4
-
mA
I
load = 500 µA
200
100
Iline_reg
Line regulation
2.8 V ≤ VDDA ≤ 3.6 V
ppm/V
Iload = 4 mA
-
500 µA ≤ ILOAD
4 mA
≤
ppm/
mA
Iload_reg Load regulation
Normal Mode
-
50
-
Tcoeff_
Temperature
Tcoeff
ppm/
°C
VREF
-40 °C < TJ < +125 °C
-
-
-
coefficient
INT
+75
DC
-
-
-
-
-
-
-
-
-
-
60
40
-
PSRR
tSTART
Power supply rejection
dB
µs
100 kHz
CL = 0.5 µF
CL = 1 µF
CL = 1.5 µF
-
300
500
650
350
650
800
Start-up time(3)
Control of maximum
DC current drive on
VREFBUF_OUT during
startup phase(4)
IINRUSH
-
-
8
13.5
mA
ILOAD = 0 µA
-
-
-
-
-
-
15
16
32
16
21
41
VREFBUF
consumption from
VDDA
IDDA(VRE
I
LOAD = 500 µA
µA
Ω
FBUF)
ILOAD = 4 mA
RVREF
Pull-down resistor
when ENVR = HIZ = 0
-
-
100
-
BUF_PullD
own
1. Guaranteed by design.
2. In degraded mode, the voltage reference buffer cannot accurately maintain the output voltage (VDDA-drop voltage).
3. if VREF+ pin has residual voltage when VREFBUF is enabled (VREFBUF_CSR.ENVR=1), this might create an overshoot
on VREFBUF output longer than tSTART
.
To avoid this, it is necessary that VREF+ pin is correctly discharged before being enabled (below VREFBUF_OUT minus
1 V, for example below 1.5 V for VSCALE = 000)
This could be achieved by ensuring VREFBUF is in OFF mode (VREFBUF_CSR.ENVR=0 and VREFBUF_CSR.HIZ=0) for
sufficient time to discharge CL through VREFBUF pull-down.
4. To properly control VREFBUF IINRUSH current during the startup phase and the change of scaling, VDDA voltage should be
in the range of 1.8 V-3.6 V, 2.1 V-3.6 V, 2.4 V-3.6 V and 2.8 V-3.6 V for VSCALE = 011, 010, 001 and 000, respectively.
208/260
DS12505 Rev 5
STM32MP157C/F
Electrical characteristics
6.3.25
Temperature sensor characteristics
Table 83. Temperature sensor characteristics
Symbol
Parameter
Min Typ Max Unit
VSENSE linearity with temperature (from Vsensor
voltage)
-
-
3
(1)
TL
°C
VSENSE linearity with temperature (from ADC counter)
Average slope (from Vsensor voltage)
Average slope (from ADC counter)
Voltage at 30 °C ± 5 °C
-
-
-
3
2
-
Avg_Slope(2)
mV/°C
V
-
2
-
(3)
V30
-
0.62
-
40.5
-
(1)
tstart_run
Startup time in Run mode (buffer startup)
ADC sampling time when reading the temperature
Sensor consumption
5.3
9.8
-
-
µs
(1)
tS_temp
(1)
Isens
0.11 0.18 0.31
2.3 3.8 6.1
µA
(1)
Isensbuf
Sensor buffer consumption
1. Guaranteed by design.
2. Guaranteed by characterization.
3. Measured at VDDA = 3.3 V ± 10 mV. The V30 ADC conversion result is stored in the TS_CAL1 byte.
Table 84. Temperature sensor calibration values
Symbol
Parameter
Memory address
TS ADC raw data acquired at temperature of
30 °C ±5 °C
TS_CAL1
0x5C00 525C[15:0](1)(2)
0x5C00 525C[31:16](1)(2)
VDDA = VREF+ = 3.3 V ±10 mV
TS ADC raw data acquired at temperature of
130 °C ±2 °C
TS_CAL2
VDDA = VREF+ = 3.3 V ±10 mV
1. It is mandatory to read a 32-bit word and to do relevant masking and shifting to isolate the required bits.
2. This address is located inside the BSEC and the access is allowed after being enabled in the RCC.
6.3.26
DTS characteristics
(1)
Table 85. DTS characteristics
Symbol
Parameter
Conditions
Min Typ Max
Unit
Output Clock frequency (PTAT
clock)
fDTS
-
-
-
-
500
1600
-
-
-
kHz
Hz/°C
°C
TSLOPE
TL
Average slope
-
Linearity with temperature (from
Output clock frequency).
VDDCORE = 1.2 V
3.8
V
DDCORE = 1.2 V
TTOTAL_
Temperature measurement error Temperature:
-40 to 125 °C
-5
-
+5
°C
ERROR
DS12505 Rev 5
209/260
238
Electrical characteristics
STM32MP157C/F
(1)
Table 85. DTS characteristics (continued)
Symbol
Parameter
Conditions
Min Typ Max
Unit
TVDD
Additional error due to VDDCORE
variation
-
-
-
-
-
2
-
10
-
-
-
-
-
°C/V
ms
μs
CORE
tTRIM
Calibration time
Wake-up time from off state until
DTS ready signal = 1
tWAKE_UP
50
20
IDDCORE_DTS DTS consumption on VDDCORE
1. Guaranteed by design.
-
µA
6.3.27
6.3.28
210/260
V
ADC monitoring characteristics and charging characteristics
BAT
Table 86. V
ADC monitoring characteristics
BAT
Symbol
Parameter
Resistor bridge for VBAT
Min
Typ
Max
Unit
R
Q
-
-
26
4
-
-
kΩ
-
Ratio on VBAT measurement
Error on Q
-
+10
-
Er(1)
–10
9.8
%
µs
(1)
tS_vbat
ADC sampling time when reading VBAT input
-
1. Guaranteed by design.
Table 87. V
charging characteristics
BAT
Symbol
Parameter
Condition
Min
Typ
Max
Unit
VBRS in PWR_CR3= 0
VBRS in PWR_CR3= 1
-
-
5
-
-
RBC
Battery charging resistor
kΩ
1.5
Temperature and V
tamper detection
monitoring characteristics for
BAT
Table 88. Temperature and V
monitoring characteristics for temper detection
BAT
Symbol
Parameter
Min
Typ
Max
Unit
TEMPhigh High temperature monitoring
105
-42
116
-31
126
-20
oC
TEMPlow
Low temperature monitoring
High supply monitoring
Low supply monitoring
(1)
VBAThigh
3.47
1.3
3.59
1.34
3.73
1.43
V
(1)
VBATlow
1. Monitored supply is VSW (i.e. VDD if VDD is present, VBAT otherwise)
DS12505 Rev 5
STM32MP157C/F
Electrical characteristics
6.3.29
V
monitoring characteristics
DDCORE
Table 89. V
monitoring characteristics
DDCORE
Symbol
Parameter
Min
Typ
Max
Unit
ADC sampling time when reading VDDCORE
input
(1)
tS_vddcore
100
-
-
ns
1. Guaranteed by design.
6.3.30
Voltage booster for analog switch
Table 90. Voltage booster for analog switch characteristics
Symbol
VDD
Parameter
Supply voltage
Condition
Min Typ Max Unit
-
-
1.71
-
-
-
-
3.6
50
V
tSU(BOOST) Booster startup time
-
-
-
µs
1.71 V ≤ VDD ≤ 2.7 V
2.7 V < VDD < 3.6 V
125
250
IDD(BOOST) Booster consumption
µA
6.3.31
Compensation cell
Table 91. Compensation cell characteristics
Symbol
Parameter
Condition
Min Typ Max Unit
1.71 V ≤ VDD ≤ 2.7 V
2.7 V < VDD < 3.6 V
1.71 V ≤ VDD ≤ 2.7 V
2.7 V < VDD < 3.6 V
-
-
-
-
-
-
-
-
3.5
10
VDD current consumption
during code calculation
ICOMPCELL
mA
µs
300
250
Time needed for code
calculation
TREADY
6.3.32
Digital filter for sigma-delta modulators (DFSDM) characteristics
Unless otherwise specified, the parameters given in Table 92 for DFSDM are derived from
tests performed under the ambient temperature, f frequency and V supply voltage
pclkx
DD
summarized in Table 13: General operating conditions, with the following configuration:
•
•
•
Output speed is set to OSPEEDRy[1:0] = 10
Capacitive load C = 30 pF
Measurement points are done at CMOS levels: 0.5×V
DD
Refer to Section 6.3.17: I/O port characteristics for more details on the input/output alternate
function characteristics (DFSDMx_CKINx, DFSDMx_DATINx, DFSDMx_CKOUT for
DFSDMx).
DS12505 Rev 5
211/260
238
Electrical characteristics
STM32MP157C/F
Table 92. DFSDM measured timing
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
fDFSDMCLK DFSDM clock
1.71 V < VDD < 3.6 V
-
-
fSYSCLK
SPI mode (SITP[1:0]=0,1),
External clock mode
(SPICKSEL[1:0]=0),
1.71 V < VDD < 3.6 V
20
-
-
-
-
-
-
-
-
(fDFSDMCLK/4)
SPI mode (SITP[1:0]=0,1),
External clock mode
(SPICKSEL[1:0]=0),
2.7 < VDD < 3.6 V
20
(fDFSDMCLK/4)
fCKIN
(1/TCKIN
Input clock
frequency
)
MHz
SPI mode (SITP[1:0]=0,1),
Internal clock mode
(SPICKSEL[1:0]≠0),
1.71 < VDD < 3.6 V
20
(fDFSDMCLK/4)
SPI mode (SITP[1:0]=0,1),
Internal clock mode
(SPICKSEL[1:0]≠0),
2.7 < VDD < 3.6 V
20
(fDFSDMCLK/4)
Output clock
frequency
fCKOUT
1.71 < VDD < 3.6 V
1.71 < VDD < 3.6 V
-
-
20
55
Output clock
DuCyCKOUT frequency duty
cycle
45
50
%
SPI mode (SITP[1:0]=0,1),
External clock mode
(SPICKSEL[1:0]=0),
1.71 < VDD < 3.6 V
twh(CKIN)
twl(CKIN)
Input clock high
and low time
TCKIN/2 - 0.5
TCKIN/2
-
SPI mode (SITP[1:0]=0,1),
Data input setup External clock mode
tsu
1
0.5
-
-
-
time
(SPICKSEL[1:0]=0),
1.71 < VDD < 3.6 V
ns
SPI mode (SITP[1:0]=0,1),
External clock mode
(SPICKSEL[1:0]=0),
1.71 < VDD < 3.6 V
Data input hold
time
th
-
Manchester mode
Manchester data (SITP[1:0]=2,3),
TManchester period (recovered Internal clock mode
(CKOUTDIV+1)
×TDFSDMCLK
(2×CKOUTDIV)
× TDFSDMCLK
-
(1)
(1)
clock period)
(SPICKSEL[1:0]¹0),
1.71 < VDD < 3.6 V
1. See DFSDM section in RM0436 reference manual for definition of CKOUTDIV.
212/260
DS12505 Rev 5
STM32MP157C/F
Electrical characteristics
Figure 42. Channel transceiver timing diagrams
(SPICKSEL=0)
SITP = 00
tr
tf
twl
twh
tsu
th
tsu
th
SITP = 01
SPICKSEL=3
SPICKSEL=2
SPICKSEL=1
tr
tf
twl
twh
tsu
th
SITP = 0
SITP = 1
tsu
th
SITP = 2
SITP = 3
recovered clock
recovered data
0
0
1
1
0
MS30766V2
DS12505 Rev 5
213/260
238
Electrical characteristics
STM32MP157C/F
6.3.33
Camera interface (DCMI) characteristics
Unless otherwise specified, the parameters given in Table 93 for DCMI are derived from
tests performed under the ambient temperature, F
frequency and V supply voltage
mcu_ck
DD
summarized in Table 13: General operating conditions, with the following configuration:
•
•
•
•
•
DCMI_PIXCLK polarity: falling
DCMI_VSYNC and DCMI_HSYNC polarity: high
Data formats: 14 bits
Capacitive load C = 30 pF
Measurement points are done at CMOS levels: 0.5×V
DD
(1)
Table 93. DCMI characteristics
Parameter
Symbol
Min
Max
Unit
-
Frequency ratio DCMI_PIXCLK/Fmcu_ck
-
-
0.4
80
70
-
-
DCMI_PIXCLK Pixel clock input
MHz
%
DPixel
Pixel clock input duty cycle
30
2
tsu(DATA)
th(DATA)
tsu(HSYNC)
tsu(VSYNC)
th(HSYNC)
th(VSYNC)
Data input setup time
Data input hold time
0.5
-
ns
DCMI_HSYNC/DCMI_VSYNC input setup time
DCMI_HSYNC/DCMI_VSYNC input hold time
2
1
-
-
1. Guaranteed by characterization results.
Figure 43. DCMI timing diagram
1/DCMI_PIXCLK
DCMI_PIXCLK
DCMI_HSYNC
DCMI_VSYNC
DATA[0:13]
th(HSYNC)
tsu(HSYNC)
th(HSYNC)
tsu(VSYNC)
tsu(DATA) th(DATA)
MS32414V2
214/260
DS12505 Rev 5
STM32MP157C/F
Electrical characteristics
6.3.34
LCD-TFT controller (LTDC) characteristics
Unless otherwise specified, the parameters given in Table 94 for LCD-TFT are derived from
tests performed under the ambient temperature, F
frequency and V supply voltage
pclk4
DD
summarized in Table 13: General operating conditions, with the following configuration:
•
•
•
•
•
•
•
•
LCD_CLK polarity: high
LCD_DE polarity: low
LCD_VSYNC and LCD_HSYNC polarity: high
Pixel formats: 24 bits
Output speed is set to OSPEEDRy[1:0] = 11
Capacitive load C = 30 pF
Measurement points are done at CMOS levels: 0.5×V
I/O compensation cell enabled
DD
(1)
Table 94. LTDC characteristics
Symbol
Parameter
Conditions
Min
Max
Unit
2.7 V < VDD < 3.6 V
OSPEEDR[1:0] = 11, 10
-
90
1.71 V < VDD < 3.6 V
OSPEEDR[1:0] = 11
fCLK
LTDC clock output frequency
-
45
MHz
%
1.71 V < VDD < 3.6 V
OSPEEDR[1:0] = 10
-
38
55
DCLK
LTDC clock output duty cycle
Clock High time, low time
-
-
45
tw(CLKH),
tw(CLKL)
tw(CLK)/2 - 0.5 tw(CLK)/2 + 0.5
OSPEEDR[1:0] = 11
OSPEEDR[1:0] = 10
-
-
-
3
4
tv(DATA)
Data output valid time
Data output hold time
th(DATA)
0
-
-
ns
tv(HSYNC),
OSPEEDR[1:0] = 11
2.5
tv(VSYNC), HSYNC/VSYNC/DE output valid time
tv(DE)
OSPEEDR[1:0] = 10
-
3.5
th(HSYNC),
th(VSYNC)
,
HSYNC/VSYNC/DE output hold time
-
0
-
th(DE)
1. Guaranteed by characterization results.
DS12505 Rev 5
215/260
238
Electrical characteristics
STM32MP157C/F
Figure 44. LCD-TFT horizontal timing diagram
tCLK
LCD_CLK
LCD_VSYNC
tv(HSYNC)
tv(HSYNC)
LCD_HSYNC
th(DE)
tv(DE)
LCD_DE
tv(DATA)
LCD_R[0:7]
LCD_G[0:7]
LCD_B[0:7]
Pixel Pixel
1
Pixel
N
2
th(DATA)
Active width
HSYNCHorizontal
width back porch
Horizontal
back porch
One line
MS32749V1
Figure 45. LCD-TFT vertical timing diagram
tCLK
LCD_CLK
tv(VSYNC)
tv(VSYNC)
LCD_VSYNC
LCD_R[0:7]
LCD_G[0:7]
LCD_B[0:7]
M lines data
VSYNC Vertical
width back porch
Active width
One frame
Vertical
back porch
MS32750V1
216/260
DS12505 Rev 5
STM32MP157C/F
Electrical characteristics
6.3.35
Timer characteristics
The parameters given in Table 95 are guaranteed by design.
Refer to Section 6.3.17: I/O port characteristics for details on the input/output alternate
function characteristics (output compare, input capture, external clock, PWM output).
(1)(2)
Table 95. TIMx characteristics
Symbol
tres(TIM)
fTIMxCLK
fEXT
Parameter
Timer resolution time
Min
Max
Unit
1
0
0
-
-
tTIMxCLK
Timer kernel clock
209
MHz
bit
Timer external clock frequency on CH1 to CH4
Timer resolution
fTIMxCLK/2
16/32
ResTIM
Maximum possible count with 16-bit counters
65536
tMAX_COUNT
-
tTIMxCLK
Maximum possible count with 32-bit counter
(TIM2, TIM5)
65536 ×
65536
1. TIMx is used as a general term to refer to the TIM1 to TIM17 timers.
2. Guaranteed by design.
(1)(2)
Table 96. LPTIMx characteristics
Symbol
tres(TIM)
fLPTIMxCLK
Parameter
Timer resolution time
Min
Max
Unit
1
0
-
tTIMxCLK
Timer kernel clock
104.5
MHz
Timer external clock frequency on Input1 and
Input2
fLPTIMxCLK
2
/
fEXT
0
ResTIM
Timer resolution
-
-
16
bit
tMAX_COUNT Maximum possible count
65536
tTIMxCLK
1. LPTIMx is used as a general term to refer to the LPTIM1 to LPTIM5 timers.
2. Guaranteed by design.
6.3.36
Communications interfaces
I2C interface characteristics
2
The I2C interface meets the timings requirements of the I C-bus specification for:
•
•
•
Standard-mode (Sm): with a bit rate up to 100 kbit/s
Fast-mode (Fm): with a bit rate up to 400 kbit/s.
Fast-mode Plus (Fm+): with a bit rate up to 1 Mbit/s.
2
The I C timings requirements are guaranteed by design when the I2C peripheral is properly
configured and when the i2c_ker_ck frequency is greater than the minimum shown in the
table below:
DS12505 Rev 5
217/260
238
Electrical characteristics
STM32MP157C/F
Unit
Table 97. Minimum i2c_ker_ck frequency in all I2C modes
Symbol
Parameter
Condition
Min
Standard-mode
Fast-mode
-
2
Analog filter ON
DNF=0
8
9
Analog filter OFF
DNF=1
I2CCLK
frequency
f(I2CCLK)
MHz
Analog filter ON
DNF=0
19
16
Fast-mode Plus
Analog filter OFF
DNF=1
The SDA and SCL I/O requirements are met with the following restrictions:
•
The SDA and SCL I/O pins are not “true” open-drain. When configured as open-drain,
the PMOS connected between the I/O pin and V is disabled, but is still present.
DD
•
The 20 mA output drive requirement in Fast-mode Plus is not supported. This limits the
maximum load C
supported in Fm+, which is given by these formulas:
load
t
= 0.8473 × R × C
p
r(SDA/SCL)
load
DD OL(max) OL(max)
R
= (V -V
)/I
p(min)
Where R is the I2C lines pull-up. Refer to Section 6.3.17: I/O port characteristics for the I2C
p
I/Os characteristics.
All I2C SDA and SCL I/Os embed an analog filter. Refer to Table 98 for the analog filter
characteristics:
(1)
Table 98. I2C analog filter characteristics
Symbol
tAF
Parameter
Min
Max
Unit
Maximum pulse width of spikes that
are suppressed by the analog filter
40(2)
260(3)
ns
1. Guaranteed by design.
2. Spikes with widths below tAF(min) are filtered.
3. Spikes with widths above tAF(max) are not filtered.
The I2C pins can be set in FM+ mode in SYSCFG_PMCR register.
Unless otherwise specified, the parameters given in Table 55 are derived from tests
performed under the ambient temperature and V supply voltage conditions summarized
DD
in Table 13: General operating conditions.
218/260
DS12505 Rev 5
STM32MP157C/F
Electrical characteristics
Table 99. I2C FM+ pin characteristics
Parameter Conditions
Symbol
Min
Max
Unit
(1)
Fmax
Tf(2)
Maximum frequency
-
-
1
5
MHz
ns
C = 50 pF
1.71 ≤ VDD ≤ 3.6 V
Output high to low level fall time
1. The maximum frequency is defined with the following conditions:
- (Tr + Tf) ≤ ⅔T
- 45% < duty cycle < 55%.
2. The fall time is defined between 70% and 30% of the output waveform accordingl to I2C specification NXP
UM10204 rev- Oct 2012.
SPI interface characteristics
Unless otherwise specified, the parameters given in Table 100 for the SPI interface are
derived from tests performed under the ambient temperature, f
frequency and V
pclkx
DD
supply voltage conditions summarized in Table 13: General operating conditions, with the
following configuration:
•
•
•
•
•
Output speed is set to OSPEEDRy[1:0] = 11
Capacitive load C = 30 pF
Measurement points are done at CMOS levels: 0.5×V
I/O compensation cell enabled
DD
HSLV activated when V ≤ 2.7 V
DD
Refer to Section 6.3.17: I/O port characteristics for more details on the input/output alternate
function characteristics (NSS, SCK, MOSI, MISO for SPI).
DS12505 Rev 5
219/260
238
Electrical characteristics
STM32MP157C/F
(1)
Table 100. SPI dynamic characteristics
Conditions Min
Master mode
Symbol
Parameter
Typ
Max
Unit
1.71 V ≤ VDD ≤ 3.6 V
SPI1
70
Master mode
2.7 V ≤ VDD ≤ 3.6 V
SPI1
80
80
Master mode
1.71 V ≤ VDD ≤ 3.6 V
SPI2, SPI3
Master mode
2.7 V ≤ VDD ≤ 3.6 V
SPI2, SPI3
100
66
fSCK
SPI clock frequency
Master mode
-
-
MHz
1.71 V ≤ VDD ≤ 3.6 V
SPI4, SPI5, SPI6
Slave receiver mode
1.71 V ≤ VDD ≤ 3.6 V
SPI1, SPI2, SPI3
100
66
Slave receiver mode
1.71 V ≤ VDD ≤ 3.6 V
SPI4, SPI5, SPI6
Slave mode transmitter/full duplex
2.7 V ≤ VDD ≤ 3.6 V
38(2)
35(2)
Slave mode transmitter/full duplex
1.71 V ≤ VDD ≤ 3.6 V
tsu(NSS) NSS setup time
2
1
-
-
-
-
Slave mode
th(NSS)
NSS hold time
ns
tw(SCKH)
tw(SCKL)
,
SCK high and low time
Master mode
Tpclk - 1
Tpclk
Tpclk + 1
220/260
DS12505 Rev 5
STM32MP157C/F
Electrical characteristics
(1)
Table 100. SPI dynamic characteristics (continued)
Symbol
Parameter
Conditions
Master mode
Min
Typ
Max
Unit
tsu(MI)
tsu(SI)
th(MI)
1
2
3
1
9
3
-
-
-
-
Data input setup time
Data input hold time
Slave mode
Master mode
Slave mode
-
-
th(SI)
-
-
ta(SO)
tdis(SO)
Data output access time Slave mode
Data output disable time Slave mode
Slave mode
11
5
16
7.5
ns
-
11
13
2.7 V ≤ VDD ≤ 3.6 V
tv(SO)
Data output valid time
Slave mode
-
-
11
1.5
-
14
2.5
-
1.71 V ≤ VDD ≤ 3.6 V
Master mode
tv(MO)
th(SO)
th(MO)
Slave mode
1.71 V ≤ VDD ≤ 3.6 V
8
1
Data output hold time
Master mode
-
-
1. Guaranteed by characterization results.
2. Maximum frequency in slave transmitter mode is determined by the sum of tv(SO) and tsu(MI) which has to fit into SCK low or
high phase preceding the SCK sampling edge. This value can be achieved when the SPI communicates with a master
having tsu(MI) = 0 while Duty(SCK) = 50%.
Figure 46. SPI timing diagram - slave mode and CPHA = 0
NSS input
tc(SCK)
th(NSS)
tsu(NSS)
tw(SCKH)
tr(SCK)
CPHA=0
CPOL=0
CPHA=0
CPOL=1
ta(SO)
tw(SCKL)
tv(SO)
th(SO)
tf(SCK)
Last bit OUT
tdis(SO)
MISO output
MOSI input
First bit OUT
th(SI)
Next bits OUT
tsu(SI)
First bit IN
Next bits IN
Last bit IN
MSv41658V1
DS12505 Rev 5
221/260
238
Electrical characteristics
STM32MP157C/F
(1)
Figure 47. SPI timing diagram - slave mode and CPHA = 1
NSS input
tc(SCK)
tsu(NSS)
tw(SCKH)
tf(SCK)
th(NSS)
CPHA=1
CPOL=0
CPHA=1
CPOL=1
ta(SO)
tw(SCKL)
tv(SO)
First bit OUT
tsu(SI) th(SI)
First bit IN
th(SO)
Next bits OUT
tr(SCK)
tdis(SO)
MISO output
MOSI input
Last bit OUT
Next bits IN
Last bit IN
MSv41659V1
1. Measurement points are done at 0.5×VDD and with external CL = 30 pF.
(1)
Figure 48. SPI timing diagram - master mode
High
NSS input
t
c(SCK)
CPHA=0
CPOL=0
CPHA=0
CPOL=1
CPHA=1
CPOL=0
CPHA=1
CPOL=1
t
t
t
t
w(SCKH)
w(SCKL)
r(SCK)
f(SCK)
t
su(MI)
MISO
INPUT
BIT6 IN
LSB IN
MSB IN
t
h(MI)
MOSI
OUTPUT
BIT1 OUT
LSB OUT
MSB OUT
t
t
h(MO)
v(MO)
ai14136c
1. Measurement points are done at 0.5×VDD and with external CL = 30 pF.
I2S interface characteristics
Unless otherwise specified, the parameters given in Table 101 for the I2S interface are
derived from tests performed under the ambient temperature, f frequency and V
pclkx
DD
222/260
DS12505 Rev 5
STM32MP157C/F
Electrical characteristics
supply voltage conditions summarized in Table 13: General operating conditions, with the
following configuration:
•
•
•
•
Output speed is set to OSPEEDRy[1:0] = 10
Capacitive load C = 30 pF
Measurement points are done at CMOS levels: 0.5×V
I/O compensation cell enabled
DD
Refer to Section 6.3.17: I/O port characteristics for more details on the input/output alternate
function characteristics (CK, SD, WS).
(1)
Table 101. I2S dynamic characteristics
Symbol
Parameter
Conditions
Min
Max
Unit
fMCK
I2S main clock output
-
256×8K
256×Fs
MHz
Master data
Slave data
Master mode
Master mode
Slave mode
Slave mode
-
-
64×Fs
fCK
I2S clock frequency
MHz
64×Fs
tv(WS)
WS valid time
WS hold time
WS setup time
WS hold time
-
6.5
th(WS)
0.5
1
-
-
tsu(WS)
th(WS)
0
-
tsu(SD_MR)
tsu(SD_SR)
th(SD_MR)
th(SD_SR)
tv(SD_ST)
tv(SD_MT)
th(SD_ST)
th(SD_MT)
Master receiver
2
-
Data input setup time
Data input hold time
Data output valid time
Data output hold time
Slave receiver
1.5
2
-
ns
Master receiver
-
Slave receiver
0.5
-
-
Slave transmitter (after enable edge)
Master transmitter (after enable edge)
Slave transmitter (after enable edge)
Master transmitter (after enable edge)
15
1
-
-
8.5
0
-
1. Guaranteed by characterization results.
DS12505 Rev 5
223/260
238
Electrical characteristics
STM32MP157C/F
(1)
Figure 49. I2S slave timing diagram (Philips protocol)
1. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first
byte.
(1)
Figure 50. I2S master timing diagram (Philips protocol)
1. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first
byte.
SAI characteristics
Unless otherwise specified, the parameters given in Table 102 for SAI are derived from tests
performed under the ambient temperature, F
frequency and V supply voltage
pclk2
DD
224/260
DS12505 Rev 5
STM32MP157C/F
Electrical characteristics
conditions summarized in Table 13: General operating conditions, with the following
configuration:
•
•
•
Output speed is set to OSPEEDRy[1:0] = 10
Capacitive load C = 30 pF
Measurement points are performed at CMOS levels: 0.5×V
DD
Refer to Section 6.3.17: I/O port characteristics for more details on the input/output alternate
function characteristics (SCK,SD,WS).
(1)
Table 102. SAI characteristics
Symbol
fMCK
Parameter
Conditions
Min
Max
Unit
SAI Main clock output
-
-
50
MHz
Master transmitter
2.7 V ≤ VDD ≤ 3.6 V
-
-
-
-
-
-
-
45
27
27
45
31
50
11
Master transmitter
1.71 V ≤ VDD ≤ 3.6 V
Master receiver
1.71 V ≤ VDD ≤ 3.6 V
SAI bit clock
frequency(2)
FCK
MHz
Slave transmitter
2.7 V ≤ VDD ≤ 3.6 V
Slave transmitter
1.71 V ≤ VDD ≤ 3.6 V
Slave receiver
1.71 ≤ VDD ≤ 3.6 V
Master mode
2.7 V ≤ VDD ≤ 3.6 V
tv(FS)
FS valid time
Master mode
-
18
1.71 V ≤ VDD ≤ 3.6 V
tsu(FS)
th(FS)
FS setup time
FS hold time
Slave mode
7
2
-
-
-
-
-
-
-
Master mode
Slave mode
ns
2.5
2
tsu(SD_A_MR)
tsu(SD_B_SR)
th(SD_A_MR)
th(SD_B_SR)
Master receiver
Slave receiver
Master receiver
Slave receiver
Data input setup time
Data input hold time
1.5
3
0.5
DS12505 Rev 5
225/260
238
Electrical characteristics
STM32MP157C/F
(1)
Table 102. SAI characteristics (continued)
Symbol
Parameter
Conditions
Min
Max
Unit
Slave transmitter (after enable edge)
2.7 V ≤ VDD ≤ 3.6 V
-
11
tv(SD_B_ST)
th(SD_B_ST)
tv(SD_A_MT)
th(SD_A_MT)
Data output valid time
Slave transmitter (after enable edge)
1.71 V ≤ VDD ≤ 3.6 V
-
8.5
-
16
-
Data output hold time Slave transmitter (after enable edge)
ns
Master transmitter (after enable edge)
10
2.7 V ≤ VDD ≤ 3.6 V
Data output valid time
Master transmitter (after enable edge)
-
18
-
1.71 V ≤ VDD ≤ 3.6 V
Data output hold time Master transmitter (after enable edge)
7
1. Guaranteed by characterization results.
2. APB clock frequency must be at least twice SAI clock frequency.
Figure 51. SAI master timing waveforms
1/f
SCK
SAI_SCK_X
t
h(FS)
SAI_FS_X
(output)
t
t
t
h(SD_MT)
v(FS)
v(SD_MT)
SAI_SD_X
(transmit)
Slot n
Slot n+2
t
t
h(SD_MR)
su(SD_MR)
SAI_SD_X
(receive)
Slot n
MS32771V1
Figure 52. SAI slave timing waveforms
SAI_SCK_X
t
t
t
h(FS)
w(CKH_X)
w(CKL_X)
SAI_FS_X
(input)
t
t
t
h(SD_ST)
su(FS)
v(SD_ST)
SAI_SD_X
(transmit)
Slot n
Slot n+2
t
t
h(SD_SR)
su(SD_SR)
SAI_SD_X
(receive)
Slot n
MS32772V1
226/260
DS12505 Rev 5
STM32MP157C/F
Electrical characteristics
MDIOS characteristics
Table 103. MDIOS timing parameters
Symbol
Parameter
Management data clock
Min
Typ
Max
Unit
FMDC
-
-
8
-
30
19
-
MHz
td(MDIOS) Management data input/output output valid time
tsu(MDIOS) Management data input/output setup time
th(MDIOS) Management data input/output hold time
6.5
1
ns
0.5
-
-
The MDIOS controller is mapped on APB1 domain. The frequency of the APB bus should at
least 1.5 times the MDC frequency: F ≥ 1.5 * F
.
MDC
pclk1
Figure 53. MDIOS timing diagram
TMDC
MDIOS_MDC
td(MDIOS)
MDIOS_MDIO(O)
tsu(MDIOS)
th(MDIOS)
MDIOS_MDIO(I)
MSv50900V1
SD/SDIO MMC card host interface (SDMMC) characteristics
Unless otherwise specified, the parameters given in Table 104 for the SDIO/MMC interface
are derived from tests performed under the ambient temperature, F frequency and V
hclk6
DD
supply voltage conditions summarized in Table 13: General operating conditions, with the
following configuration:
•
•
•
•
•
•
Output speed is set to OSPEEDRy[1:0] = 11
Capacitive load C = 30 pF
Measurement points are done at CMOS levels: 0.5×V
I/O compensation cell enabled
DD
HSLV activated when V ≤ 2.7 V
DD
Delay block disabled
Refer to Section 6.3.17: I/O port characteristics for more details on the input/output
characteristics.
DS12505 Rev 5
227/260
238
Electrical characteristics
STM32MP157C/F
Table 104. Dynamic characteristics: SD / MMC / e•MMC characteristics,
(1)(2)
V
= 2.7 V to 3.6 V
DD
Symbol
fPP
Parameter
Conditions
Min
Typ
Max
Unit
Clock frequency in data transfer mode
SDIO_CK/fpclk2 frequency ratio
Clock low time
-
-
0
-
-
130
MHz
-
-
-
8/3
tW(CKL)
tW(CKH)
8.5
9.5
9.5
-
-
fPP = 52 MHz
ns
Clock high time
8.5
CMD, D inputs (referenced to CK) in MMC and SD HS/SDR(3)/DDR(3) mode
tISU
tIH
Input setup time HS
1.5
1.5
2.5
-
-
-
-
-
-
Input hold time HS
-
ns
(4)
tIDW
Input valid window (variable window)
CMD, D outputs (referenced to CK) in MMC and SD HS/SDR(3)/DDR(3) mode
tOV
tOH
Output valid time HS
Output hold time HS
-
5
-
6.5
-
-
-
-
ns
ns
ns
2.5
CMD, D inputs (referenced to CK) in SD default mode
tISUD
tIHD
Input setup time SD
Input hold time SD
1.5
1.5
-
-
-
-
CMD, D outputs (referenced to CK) in SD default mode
tOVD
tOHD
Output valid default time SD
Output hold default time SD
-
0.5
-
1.5
-
0
1. Guaranteed by characterization results.
2. Above 100 MHz, CL = 20 pF.
3. For SD 1.8 V support, an external voltage converter is required.
4. The minimum window of time where the data needs to be stable for proper sampling in tuning mode.
Table 105. Dynamic characteristics: SD / MMC / e•MMC characteristics
(1)(2)
V
= 1.71 V to 1.9 V
DD
Symbol
fPP
Parameter
Conditions
Min
Typ
Max
Unit
Clock frequency in data transfer mode
SDIO_CK/fpclk2 frequency ratio
Clock low time
-
-
0
-
-
105
MHz
-
-
-
8/3
tW(CKL)
tW(CKH)
8.5
8.5
9.5
9.5
-
-
fPP = 52 MHz
ns
Clock high time
CMD, D inputs (referenced to CK) in e•MMC mode
tISU
tIH
Input setup time HS
1.5
2.5
3
-
-
-
-
-
-
Input hold time HS
-
ns
(3)
tIDW
Input valid window (variable window)
CMD, D outputs (referenced to CK) in e•MMC mode
228/260
DS12505 Rev 5
STM32MP157C/F
Electrical characteristics
Table 105. Dynamic characteristics: SD / MMC / e•MMC characteristics
(1)(2)
V
= 1.71 V to 1.9 V
(continued)
DD
Symbol
tOV
tOH
Parameter
Output valid time HS
Output hold time HS
Conditions
Min
Typ
Max
Unit
-
5
-
6
-
-
ns
4
1. Guaranteed by characterization results.
2. CL = 20 pF.
3. The minimum window of time where the data needs to be stable for proper sampling in tuning mode.
Figure 54. SDIO high-speed mode
Figure 55. SD default mode
CK
t
t
OVD
OHD
D, CMD
(output)
DS12505 Rev 5
229/260
238
Electrical characteristics
STM32MP157C/F
Figure 56. DDR mode
tr(CK)
t(CK)
tw(CKH)
tw(CKL)
tf(CK)
Clock
tvf(OUT) thr(OUT)
D0
tvr(OUT)
thf(OUT)
D3
Data output
D1
D2
D4
tsr(IN)thr(IN)
D5
tsf(IN) thf(IN)
Data input
D0
D1
D2
D3
D4
D5
MSv63044V1
FDCAN (controller area network) interface
Refer to Section 6.3.17: I/O port characteristics for more details on the input/output alternate
function characteristics (FDCANx_TX and FDCANx_RX).
USB OTG_FS characteristics
The USB interface is fully compliant with the USB specification version 2.0 and is USB-IF
certified (for Full-speed device operation).
Table 106. USB OTG_FS electrical characteristics
Symbol
Parameter
Condition
Min
Typ
Max
Unit
USB transceiver operating
voltage
VDD33USB
-
3.0(1)
-
3.6
V
Embedded USB_DP pull-up
value during idle
RPUI
-
900
1250
1600
Embedded USB_DP pull-up
value during reception
Ω
RPUR
ZDRV
-
1400
28
2300
36
3200
44
Output driver impedance(2)
Driver high and low
1. The USB functionality is ensured down to 2.7 V but not the full USB electrical characteristics which are degraded in the 2.7
to 3.0 V voltage range.
2. No external termination series resistors are required on USB_DP (D+) and USB_DM (D-); the matching impedance is
already included in the embedded driver.
Note:
When VBUS sensing feature is enabled, a typical 200 μA input current (required to
determine the different sessions validity according to USB standard) can be observed.
Ethernet (ETH) characteristics
Unless otherwise specified, the parameters given in Table 107, Table 108, Table 109,
Table 110 and Table 111 for MDIO/SMA, RMII, GMII, RGMII and MII are derived from tests
performed under the ambient temperature, F
frequency summarized in Table 13:
axiss_ck
General operating conditions, with the following configuration:
•
•
•
Output speed is set to OSPEEDRy[1:0] = 10
Capacitive load C = 20 pF
Measurement points are done at CMOS levels: 0.5×V
.
DD
230/260
DS12505 Rev 5
STM32MP157C/F
Electrical characteristics
Refer to Section 6.3.17: I/O port characteristics for more details on the input/output
characteristics.
Table 107 gives the list of Ethernet MAC timings for the MDIO/SMA and Figure 57 shows
the corresponding timing diagram.
(1)
Table 107. Dynamics characteristics: Ethernet MAC timings for MDIO/SMA
Symbol
tMDC
Parameter
Min
Typ
Max
Unit
MDC cycle time(2.5 MHz)
Write data valid time
Read data setup time
Read data hold time
399
0.5
13.5
0
400
401
Td(MDIO)
tsu(MDIO)
th(MDIO)
1
-
3
-
ns
-
-
1. Guaranteed by characterization results.
Figure 57. Ethernet MDIO/SMA timing diagram
tMDC
ETH_MDC
td(MDIO)
ETH_MDIO(O)
ETH_MDIO(I)
tsu(MDIO)
th(MDIO)
MS31384V1
Table 108 gives the list of Ethernet MAC timings for the RMII and Figure 58 shows the
corresponding timing diagram.
(1)
Table 108. Dynamics characteristics: Ethernet MAC timings for RMII
Symbol
Parameter
Min
Typ
Max
Unit
tsu(RXD)
tih(RXD)
tsu(CRS)
tih(CRS)
td(TXEN)
td(TXD)
Receive data setup time
Receive data hold time
2
-
-
-
-
1.5
1.5
1.5
5.5
6
Carrier sense setup time
Carrier sense hold time
-
-
ns
-
-
Transmit enable valid delay time
Transmit data valid delay time
6.5
6.5
9.5
10
1. Guaranteed by characterization results.
DS12505 Rev 5
231/260
238
Electrical characteristics
STM32MP157C/F
Figure 58. Ethernet RMII timing diagram
RMII_REF_CLK
t
t
d(TXEN)
d(TXD)
RMII_TX_EN
RMII_TXD[1:0]
t
t
t
t
su(RXD)
su(CRS)
ih(RXD)
ih(CRS)
RMII_RXD[1:0]
RMII_CRS_DV
ai15667b
Table 109 gives the list of Ethernet MAC timings for MII and Figure 59 shows the
corresponding timing diagram.
(1)
Table 109. Dynamics characteristics: Ethernet MAC timings for MII
Symbol
Parameter
Min
Typ
Max
Unit
tsu(RXD)
tih(RXD)
tsu(DV)
tih(DV)
Receive data setup time
Receive data hold time
Data valid setup time
Data valid hold time
2
1
-
-
-
-
1
-
-
0.5
1
-
-
-
ns
tsu(ER)
tih(ER)
td(TXEN)
td(TXD)
Error setup time
-
Error hold time
0.5
6
-
-
Transmit enable valid delay time
Transmit data valid delay time
7.5
8
10.5
11
7
1. Guaranteed by characterization results.
232/260
DS12505 Rev 5
STM32MP157C/F
Electrical characteristics
Figure 59. Ethernet MII timing diagram
MII_RX_CLK
t
t
t
t
t
t
su(RXD)
su(ER)
su(DV)
ih(RXD)
ih(ER)
ih(DV)
MII_RXD[3:0]
MII_RX_DV
MII_RX_ER
MII_TX_CLK
t
t
d(TXEN)
d(TXD)
MII_TX_EN
MII_TXD[3:0]
ai15668b
(1)
Table 110. Dynamics characteristics: Ethernet MAC signals for GMII
Symbol
Parameter
Min
Typ
Max
Unit
tsu(RXD)
tih(RXD)
tsu(DV)
tih(DV)
Receive data setup time
Receive data hold time
Data valid setup time
Data valid hold time
1
0.5
1
-
-
-
-
-
-
0.5
1
-
-
ns
tsu(ER)
tih(ER)
td(TXEN)
td(TXD)
Error setup time
-
-
Error hold time
0.5
1
-
-
Transmit enable valid delay time
Transmit data valid delay time
1.5
2
2
3
1
1. Guaranteed by characterization results.
DS12505 Rev 5
233/260
238
Electrical characteristics
STM32MP157C/F
Figure 60. Ethernet GMII timing diagram
GMII_RX_CLK
tsu(RXD)
tsu(ER)
tsu(DV)
tih(RXD)
tih(ER)
tih(DV)
GMII_RXD[7:0]
GMII_RX_DV
GMII_RX_ER
GTX_CLK
td(TXEN)
td(TXD)
GMII_TX_EN
GMII_TXD[7:0]
MSv50970V1
(1)
Table 111. Dynamics characteristics: Ethernet MAC signals for RGMII
Symbol
tsu(RXD)
Rating
Min
Typ
Max
Unit
Receive data setup time
1.12(2)
0.83(2)
1.12(2)
0.83(2)
-0.25
-
-
-
tih(RXD)
Receive data hold time
-
-
tsu(RX_CTL)
tih(RX_CTL)
TskewT(TX_CTL)
TskewT(TXD)
Receive control valid setup time
Receive control valid hold time
Transmit control valid delay time
Transmit data valid delay time
-
ns
-
-
0.25
0.25
0.5
0.5
-0.25
1. Guaranteed by characterization results.
2. Guaranteed by design.
Figure 61. Ethernet RGMII timing diagram
tskewT
RGMII_GTX_CLK
RGMII_TXD[3:0]
RGMII_TX_CTL
tsu
tih
RGMII_RX_CLK
RGMII_RXD[3:0]
RGMII_RX_CTL
MSv50971V2
234/260
DS12505 Rev 5
STM32MP157C/F
Electrical characteristics
6.3.37
USART interface characteristics
Unless otherwise specified, the parameters given in Table 112 for USART are derived from
tests performed under the ambient temperature, f
frequency and V supply voltage
HCLK
DD
conditions summarized in Table 112, with the following configuration:
•
•
•
Output speed is set to OSPEEDRy[1:0] = 10
Capacitive load C = 30 pF
Measurement points are done at CMOS levels: 0.5×V
DD
Refer to Section 6.3.17: I/O port characteristics for more details on the input/output alternate
function characteristics (NSS, CK, TX, RX for USART).
(1)
Table 112. USART characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Master mode
USART2,3,6
12.5
-
-
fCK
USART clock frequency
Master mode
USART1
MHz
16.5
Slave mode
Slave mode
Slave mode
-
tker+2
2
-
-
-
27
-
tsu(NSS)
th(NSS)
tw(CKH),
NSS setup time
NSS hold time
ns
ns
-
CK high and low time
Data input setup time
Master mode
1/fCK/2 - 1
1/fck/2
1/fCK/2 + 1
ns
ns
tw(CKL)
Master mode
Slave mode
Master mode
Slave mode
Slave mode
Master mode
Slave mode
Master mode
t
ker+3
-
-
-
-
tsu(RX)
2
1
1
-
-
-
thRX)
Data input hold time
Data output valid time
Data output hold time
ns
ns
ns
-
-
10
0.5
-
18
1
-
tv(TX)
-
8
0
th(TX)
-
-
1. 1.Guaranteed by characterization results.
6.3.38
USB High-Speed PHY characteristics
(1)
Table 113. USB High-Speed PHY characteristics
Symbol
Parameter
Conditions
Min Typ Max Unit
RREF
Reference resistor on USB_RREF pin
-
2.97 3.00 3.03 kΩ
DS12505 Rev 5
235/260
238
Electrical characteristics
STM32MP157C/F
(1)
Table 113. USB High-Speed PHY characteristics (continued)
Parameter Conditions Min Typ Max Unit
One USB port
Symbol
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
1.4
2.4
5.4
10.4
0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
High-Speed TX(2)
Two USB ports
One USB port
Two USB ports
IDDA1V1_REG(PHY)
mA
High-Speed RX(3) / Idle
Ful-Speed and Low-Speed mode (Suspend, TX or RX)
One USB port
High-Speed TX(2)
25.5
50.5
2.5
5.5
0
Two USB ports
IDDA1V8_REG(PHY)
One USB port
High-Speed RX(3) / Idle
mA
Two USB ports
Ful-Speed and Low-Speed mode (Suspend, TX or RX)
One USB port
High-Speed TX(2)
5
Two USB ports
7
One USB port
High-Speed RX(3) / Idle
6
Two USB ports
10
One USB port
Full-Speed Suspend (host mode)
Two USB ports
0
0
One USB port
Full-Speed Suspend (peripheral mode)
Two USB ports
0.2
0.4
6.5
10.5
6.5
11.5
7
IDDA3V3_USBHS(PHY)
mA
One USB port
Full-Speed TX(2)
Two USB ports
One USB port
Full-Speed RX(3)
Two USB ports
One USB port
Low-Speed TX(2)
Two USB ports
11.5
4.3
6.1
One USB port
Low-Speed RX(3)
Two USB ports
1. Guaranteed by design unless otherwise specified.
2. USB link 100% of the time in transmission
3. USB link 100% of the time in reception
236/260
DS12505 Rev 5
STM32MP157C/F
Electrical characteristics
6.3.39
DSI PHY characteristics
(1)
Table 114. DSI PHY characteristics
Symbol
Parameter
Power down
Conditions
Min
Typ Max Unit
-
-
-
-
-
-
-
-
-
185
17.35
3.35
0.8
1
-
-
-
-
-
-
-
-
µA
High-Speed TX 2 lanes in High-Speed mode
IDDA1V2_DSI_PHY(PH
Y)
LPDT transmit
LPDT receive
Power down
All data lanes in LPDT mode
mA
All data lanes in LPDT mode
-
High-Speed TX 2 lanes in High-Speed mode
400
1
IDDA1V8_DSI(PHY)
µA
LPDT transmit
LPDT receive
All data lanes in LPDT mode
All data lanes in LPDT mode
1
1. Guaranteed by design unless otherwise specified.
6.3.40
JTAG/SWD interface characteristics
Unless otherwise specified, the parameters given in Table 115 and Table 116 for JTAG/SWD
are derived from tests performed under the ambient temperature, f frequency and
rcc_c_ck
V
supply voltage summarized in Table 13: General operating conditions, with the
DD
following configuration:
•
•
•
Output speed is set to OSPEEDRy[1:0] = 0x10
Capacitive load C = 30 pF
Measurement points are done at CMOS levels: 0.5×V
DD
Refer to Section 6.3.17: I/O port characteristics for more details on the input/output
characteristics.
Table 115. Dynamics characteristics: JTAG characteristics
Symbol
Fpp
1/tc(TCK)
Parameter
Conditions
Min
Typ
Max
Unit
2.7 V < VDD < 3.6 V
1.71 V < VDD < 3.6 V
-
-
-
-
35
27
TCK clock
frequency
MHz
TMS input
setup time
tisu(TMS)
-
-
-
-
2.5
1
-
-
-
-
-
-
-
-
TMS input
hold time
tih(TMS)
tisu(TDI)
tih(TDI)
TDI input
setup time
2
ns
TDI input
hold time
1
2.7 V < VDD < 3.6 V
1.71 V < VDD< 3.6 V
-
-
8
8
14
18
TDO output
valid time
tov (TDO)
TDO output
hold time
toh(TDO)
-
7
-
-
DS12505 Rev 5
237/260
238
Electrical characteristics
STM32MP157C/F
Table 116. Dynamics characteristics: SWD characteristics
Symbol
Fpp
Parameter
Conditions
Min
Typ
Max
71
Unit
SWCLK
clock
frequency
2.7 V < VDD < 3.6 V
1.71 V < VDD < 3.6 V
-
-
-
-
MHz
1/tc(SWCLK)
55
SWDIO input
setup time
tisu(SWDIO)
tih(SWDIO)
-
-
2.5
1
-
-
-
-
SWDIO input
hold time
SWDIO
output valid
time
2.7 V < VDD < 3.6 V
1.71 V < VDD < 3.6 V
-
-
8.5
8.5
14
18
ns
tov (SWDIO)
SWDIO
output hold
time
toh(SWDIO)
-
8
-
-
Figure 62. JTAG timing diagram
tc(TCK)
TCK
TDI/TMS
TDO
tsu(TMS/TDI)
th(TMS/TDI)
tw(TCKL)
tw(TCKH)
tov(TDO)
toh(TDO)
MSv40458V1
Figure 63. SWD timing
tc(SWCLK)
SWCLK
tsu(SWDIO)
th(SWDIO)
twSWCLKL)
tw(SWCLKH)
SWDIO
(receive)
tov(SWDIO)
toh(SWDIO)
SWDIO
(transmit)
MSv40459V1
238/260
DS12505 Rev 5
STM32MP157C/F
Package information
7
Package information
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK packages, depending on their level of environmental compliance. ECOPACK
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK is an ST trademark.
7.1
TFBGA257 package information
This TFBGA is a 257 balls, 10x10 mm, 0.5/0.65 mm pitch, low profile fine pitch ball grid
array package
Figure 64. TFBGA257 - Outline
b (257 balls)
eee M C
fff M C
A
B
A1 ball pad corner
Peripheral ball matrix pitch 0.5 mm
F2
D
B
8
18 16 14 12 10
19 17 15 13 11
6
4
2
e1
9
7
5
3
1
A
B
C
D
E
F
1A
1B
1C
1D
1E
1F
1G
1H
1J
G
H
J
E
K
E1 E2
e2
L
M
N
P
R
T
U
V
F1
W
8
6
4
2
e1
9
7
5
3
1
F1
Central ball matrix pitch 0.65 mm
A
F2
e2
D2
D1
SEATING
PLANE
BOTTOM VIEW
TOP VIEW
C
ddd C
A2
A
A1
SIDE VIEW
B02Y_ME_V1
1. Drawing is not to scale.
2. The tolerance of position that controls the location of the pattern of balls with respect to datums A and B.
For each ball there is a cylindrical tolerance zone eee perpendicular to datum C and located on true
position with respect to datums A and B as defined by e. The axis perpendicular to datum C of each ball
must lie within this tolerance zone
DS12505 Rev 5
239/260
254
Package information
STM32MP157C/F
Table 117. TFBGA257 - Mechanical data
millimeters
inches(1)
Symbol
Min
Typ
Max
Min
Typ
Max
A
A1(2)
A2
-
-
1.200
-
-
0.0472
0.170
-
-
0.007
-
-
-
0.810
0.300
10.000
9.000
10.000
9.000
5.200
5.200
0.500
0.650
0.500
2.400
-
-
-
0.0319
0.012
0.3937
0.3543
0.3937
0.3543
0.2047
0.2047
0.0197
0.0256
0.0197
0.0945
-
-
b(3)
0.250
0.350
0.010
0.0157
D
9.850
10.150
0.3878
0.3996
D1
E
-
-
-
-
9.850
10.150
0.3878
0.3996
E1
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
D2
E2
-
-
-
-
e1
-
-
e2
-
-
F1
-
-
F2
-
-
ddd
eee(4)
fff(5)
0.100
0.150
0.050
0.0039
0.0059
0.0020
-
-
-
-
1. Values in inches are converted from mm and rounded to 4 decimal digits.
2. - The terminal A1 corner must be identified on the top surface by using a corner chamfer,
ink or metalized markings, or other feature of package body or integral heat slug.
- A distinguishing feature is allowable on the bottom surface of the package to identify the terminal A1
corner. Exact shape of each corner is optional.
3. Initial ball equal 0.300 mm.
4. The tolerance of position that controls the location of the pattern of balls with respect to datums A and B.
For each ball there is a cylindrical tolerance zone eee perpendicular to datum C and located on true
position with respect to datums A and B as defined by e. The axis perpendicular to datum C of each ball
must lie within this tolerance zone.
5. The tolerance of position that controls the location of the balls within the matrix with respect to each other.
For each ball there is a cylindrical tolerance zone fff perpendicular to datum C and located on true position
as defined by e. The axis perpendicular to datum C of each ball must lie within this tolerance zone. Each
tolerance zone fff in the array is contained entirely in the respective zone eee above The axis of each ball
must lie simultaneously in both tolerance zones.
240/260
DS12505 Rev 5
STM32MP157C/F
Package information
Figure 65. TFBGA257 - Recommended footprint
Dpad
Dsm
B02Y_FP_V1
1. Dimensions are expressed in millimeters.
Table 118. TFBGA257 - Recommended PCB design rules (0.5/0.65 mm pitch, BGA)
Dimension Recommended values
Pitch
0.5/0.65 mm
0.230 mm
Dpad
Dsm
0.390 mm typ.
Stencil opening
Stencil thickness
0.230 mm
0.125 mm to 0.100 mm
DS12505 Rev 5
241/260
254
Package information
STM32MP157C/F
Device marking
The following figure gives an example of topside marking orientation versus ball A1 identifier
location.
The printed markings may differ depending on the supply chain.
Other optional marking or inset/upset marks, which identify the parts throughout supply
chain operations, are not indicated below.
Figure 66. TFBGA257 marking (package top view)
Product
identification
STM32MP15x
xADxx
Revision
R
Y WW
MSv60330V1
1. Parts marked as ES or E or accompanied by an Engineering Sample notification letter are not yet qualified
and therefore not approved for use in production. ST is not responsible for any consequences resulting
from such use. In no event will ST be liable for the customer using any of these engineering samples in
production. ST’s Quality department must be contacted prior to any decision to use these engineering
samples to run a qualification activity.
242/260
DS12505 Rev 5
STM32MP157C/F
Package information
7.2
LFBGA354 package information
This LFBGA is a 354 balls, 16x16 mm, 0.8 mm pitch, low profile fine pitch ball grid array
package
Figure 67. LFBGA354 - Outline
b (354 balls)
A1 ball pad corner
eee M C
A B
fff M C
8
18 16 14 12 10
19 17 15 13 11
6
4
2
e
9
7
5
3
1
A
C
D
E
F
G
H
J
K
L
D1
D
M
N
P
R
T
U
V
W
F
F
e
E1
A
B
E
BOTTOM VIEW
TOP VIEW
SEATING
PLANE
C
ddd C
A1
A
A2
SIDE VIEW
B02Z_ME_V1
1. Drawing is not to scale.
2. The tolerance of position that controls the location of the balls within the matrix with respect to each other.
For each ball there is a cylindrical tolerance zone fff perpendicular to datum C and located on true position
as defined by e. The axis perpendicular to datum C of each ball must lie within this tolerance zone.
Each tolerance zone fff in the array is contained entirely in the respective zone eee above. The axis of each
ball must lie simultaneously in both tolerance zones.
Table 119. LFBGA354 - Mechanical data
millimeters
Typ
inches(1)
Typ
Symbol
Min
Max
Min
Max
A(2)
A1(3)
A2
-
-
1.290
-
-
0.0508
0.250
-
-
-
0.0098
-
-
-
0.900
0.400
16.000
-
0.0354
0.0157
0.6299
-
b(4)
0.350
15.850
0.450
16.150
0.0138
0.6240
0.0177
0.6358
D
DS12505 Rev 5
243/260
254
Package information
STM32MP157C/F
Table 119. LFBGA354 - Mechanical data (continued)
millimeters
Typ
inches(1)
Symbol
Min
Max
Min
Typ
Max
D1
E
-
14.400
16.000
14.400
0.800
0.800
-
-
-
0.5669
0.6299
0.5669
0.0315
0.0315
-
-
15.850
16.150
0.6240
0.6358
E1
-
-
-
-
-
-
-
-
-
-
-
-
-
-
e
-
-
F
-
-
ddd
eee(5)
fff(6)
0.120
0.150
0.080
0.0050
0.0059
0.0031
-
-
-
-
1. Values in inches are converted from mm and rounded to 4 decimal digits.
2. LFBGA stands for Low profile Fine pitch Ball Grid Array package.
Low profile: 1.20mm < A ≤ 1.70mm / Fine pitch: e < 1.00mm pitch. The total profile height (Dim A) is
measured from the seating plane to the top of the component The maximum total package height is
calculated by the RSS method (Root Sum Square).
A Max = A1 Typ + A2 Typ + A4 Typ + √(A1² + A2² + A4² tolerance values).
3. The terminal A1 corner must be identified on the top surface by using a corner chamfer, ink or metalized
markings, or other feature of package body or integral heat slug.
A distinguishing feature is allowable on the bottom surface of the package to identify the terminal A1
corner. Exact shape of each corner is optional.
4. Initial ball equal 0.400 mm.
5. The tolerance of position that controls the location of the pattern of balls with respect to datums A and B.
For each ball there is a cylindrical tolerance zone eee perpendicular to datum C and located on true
position with respect to datums A and B as defined by e. The axis perpendicular to datum C of each ball
must lie within this tolerance zone.
6. The tolerance of position that controls the location of the balls within the matrix with respect to each other.
For each ball there is a cylindrical tolerance zone fff perpendicular to datum C and located on true position
as defined by e. The axis perpendicular to datum C of each ball must lie within this tolerance zone.
Each tolerance zone fff in the array is contained entirely in the respective zone eee above The axis of each
ball must lie simultaneously in both tolerance zones.
Figure 68. LFBGA354 - Recommended footprint
Dpad
Dsm
B02Z_FP_V1
1. Dimensions are expressed in millimeters.
244/260
DS12505 Rev 5
STM32MP157C/F
Package information
Table 120. LFBGA354 - Recommended PCB design rules (0.8 mm pitch, BGA)
Dimension Recommended values
Pitch
0.8 mm
Dpad
0.320 mm
Dsm
0.520 mm typ.
Stencil opening
Stencil thickness
0.320 mm
0.125 mm to 0.100 mm
Device marking
The following figure gives an example of topside marking orientation versus ball A1 identifier
location.
The printed markings may differ depending on the supply chain.
Other optional marking or inset/upset marks, which identify the parts throughout supply
chain operations, are not indicated below.
Figure 69. LFBGA354 marking (package top view)
Product
identification
STM32MP15xxABx
Revision
R
Y WW
MSv60332V1
1. Parts marked as ES or E or accompanied by an Engineering Sample notification letter are not yet qualified
and therefore not approved for use in production. ST is not responsible for any consequences resulting
from such use. In no event will ST be liable for the customer using any of these engineering samples in
production. ST’s Quality department must be contacted prior to any decision to use these engineering
samples to run a qualification activity.
DS12505 Rev 5
245/260
254
Package information
STM32MP157C/F
7.3
TFBA361 package information
This TFBGA is a 361 ball, 12x12 mm, 0.5/0.65 mm pitch, thin profile fine pitch ball grid array
package.
Figure 70. TFBGA361 - Outline
eee
fff
M
M
C
C
A B
b (361 balls)
A1 ball pad corner
Peripheral ball matrix pitch 0.5 mm
22 20 18 16 14 12 10
23 21 19 17 15 13 11
8
6
4
2
e1
9
7
5
3
1
A
B
C
D
E
F
G
H
J
1A
1B
1C
1D
1E
1F
1G
1H
1J
K
L
M
N
P
e2
E1 E2
F2
E
A
R
T
U
V
W
Y
AA
AB
AC
8
6
4
2
9
7
5
3
1
F1
F1
Central ball matrix pitch 0.65 mm
e1
e2
B
D2
F2
D
D1
BOTTOM VIEW
TOP VIEW
SEATING
PLANE
C
ddd
C
A1
A
A2
SIDE VIEW
B031_ME_V1
1. Drawing is not to scale.
2. The terminal A1 corner must be identified on the top surface by using a corner chamfer,
ink or metalized markings, or other feature of package body or integral heat slug.
A distinguishing feature is allowable on the bottom surface of the package to identify the terminal A1
corner. Exact shape of each corner is optional.
246/260
DS12505 Rev 5
STM32MP157C/F
Package information
inches(1)
Table 121. TFBGA361 - Mechanical data
millimeters
Symbol
Min
Typ
Max
Min
Typ
Max
A(2)
A1
-
-
1.200
-
-
0.0472
0.150
-
-
0.0059
-
-
A2
-
0.810
0.300
12.000
11.000
12.000
11.000
5.200
5.200
0.500
0.650
0.500
3.400
-
-
-
0.0319
0.012
0.4724
0.4331
0.4724
0.4331
0.2047
0.2047
0.0197
0.0256
0.0197
0.1339
-
-
b(3)
0.250
0.350
0.010
0.0157
D
11.850
12.150
0.4665
0.4783
D1
E
-
-
-
-
11.850
12.150
0.4665
0.4783
E1
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
D2
E2
-
-
-
-
e1
-
-
e2
-
-
F1
-
-
F2
-
-
ddd
eee(4)
fff(5)
0.080
0.150
0.080
0.0031
0.0059
0.0031
-
-
-
-
1. Values in inches are converted from mm and rounded to 4 decimal digits.
2. TFBGA stands for Thin Profile Fine Pitch Ball Grid Array. The total profile height (dim A) is measured from
the seating plane to the top of the component.
3. Initial ball equal to 0.300 mm.
4. The tolerance of position that controls the location of the pattern of balls with respect to datums A and B.
For each ball there is a cylindrical tolerance zone eee perpendicular to datum C and located on true
position with respect to datums A and B as defined by e. The axis perpendicular to datum C of each ball
must lie within this tolerance zone.
5. The tolerance of position that controls the location of the balls within the matrix with respect to each other.
For each ball there is a cylindrical tolerance zone fff perpendicular to datum C and located on true position
as defined by e. The axis perpendicular to datum C of each ball must lie within this tolerance zone. Each
tolerance zone fff in the array is contained entirely in the respective zone eee above The axis of each ball
must lie simultaneously in both tolerance zones.
DS12505 Rev 5
247/260
254
Package information
STM32MP157C/F
Figure 71. TFBGA361 - Recommended footprint
Dpad
Dsm
B031_FP_V2
Table 122. TFBGA361 - Recommended PCB design rules (0.5/0.65 mm pitch BGA)
Dimension Recommended values
Pitch
0.5/0.65 mm
0.230 mm
Dpad
Dsm
0.390 mm typ.
Stencil opening
Stencil thickness
0.230 mm
0.125 mm to 0.100 mm
248/260
DS12505 Rev 5
STM32MP157C/F
Package information
Device marking
The following figure gives an example of topside marking orientation versus ball A1 identifier
location.
The printed markings may differ depending on the supply chain.
Other optional marking or inset/upset marks, which identify the parts throughout supply
chain operations, are not indicated below.
Figure 72. TFBGA361 marking (package top view)
Product
identification
STM32MP15x
xACxx
Revision
R
Y WW
MSv60331V1
1. Parts marked as ES or E or accompanied by an Engineering Sample notification letter are not yet qualified
and therefore not approved for use in production. ST is not responsible for any consequences resulting
from such use. In no event will ST be liable for the customer using any of these engineering samples in
production. ST’s Quality department must be contacted prior to any decision to use these engineering
samples to run a qualification activity.
DS12505 Rev 5
249/260
254
Package information
STM32MP157C/F
7.4
LFBGA448 package information
This LFBGA is a 448 balls, 18x18 mm, 0.8 mm pitch, low profile fine pitch ball grid array
package.
Figure 73. LFBGA448 - Outline
C
C
A B
eee
fff
A1 corner index area
B
b (448 Balls)
A
E
8
22 20 18 16 14 12 10
21 19 17 15 13 11
6
4
2
9
7
5
3
1
e
A
B
C
D
E
F
G
H
J
D
K
L
D1
M
N
P
R
T
U
V
W
Y
AA
AB
e
F
F
E1
BOTTOM VIEW
TOP VIEW
SEATING
PLANE
A
C
A4
A3
A1
SIDE VIEW
B032_LFBGA448_ME_V1
1. Drawing is not to scale.
2. The terminal A1 corner must be identified on the top surface by using a corner chamfer, ink or metalized
markings, or other feature of package body or integral heat slug.
A distinguishing feature is allowed on the surface of the package to identify the terminal A1 corner.The
exact shape and size of this feature are optional.
Table 123. LFBGA448 - Mechanical data
millimeters
Typ
inches(1)
Typ
Symbol
Min
Max
Min
Max
A(2)
A1
A3
A4
b(3)
D
-
0.210
-
-
1.320
-
-
-
0.0520
-
0.290
0.400
-
0.0083
-
0.0114
0.0157
-
-
-
-
0.650
0.450
18.150
-
0.0256
0.0177
0.7146
0.350
17.850
0.400
18.000
0.0138
0.7028
0.0157
0.7087
250/260
DS12505 Rev 5
STM32MP157C/F
Package information
Table 123. LFBGA448 - Mechanical data (continued)
millimeters
Typ
inches(1)
Symbol
Min
Max
Min
Typ
Max
D1
E
-
16.800
18.000
16.800
0.800
0.600
0.120
0.150
0.080
-
-
0.6614
0.7087
0.6614
0.0315
0.0236
0.0047
0.0059
0.0031
-
17.850
18.150
0.7028
0.7146
E1
-
-
-
-
-
-
-
-
-
-
-
-
e
F
ddd
eee(4)
fff(5)
1. Values in inches are converted from mm and rounded to 4 decimal digits.
2. Low profile: 1.20 mm < A ≤ 1.70 mm / Fine pitch: e < 1.00 mm pitch.
The total profile height (Dim.A) is measured from the seating plane “C” to the top of the component. The
maximum total package height is calculated by the RSS method (Root Sum Square).
A Max = A1 Typ + A3 Typ + A4 Typ + √(A1² + A3² + A4² tolerance values).
3. The typical ball diameter before mounting is 0.40 mm
4. The tolerance of position that controls the location of the pattern of balls with respect to datums A and B.
For each ball there is a cylindrical tolerance zone eee perpendicular to datum C and located on true
position with respect to datums A and B as defined by e. The axis perpendicular to datum C of each ball
must lie within this tolerance zone.
5. The tolerance of position that controls the location of the balls within the matrix with respect to each other.
For each ball there is a cylindrical tolerance zone fff perpendicular to datum C and located on true position
as defined by e. The axis perpendicular to datum C of each ball must lie within this tolerance zone. Each
tolerance zone fff in the array is contained entirely in the respective zone eee above.
The axis of each ball must lie simultaneously in both tolerance zones.
Figure 74. LFBGA448 - Recommended footprint
Dpad
Dsm
BGA_WLCSP_FT_V1
Table 124. LFBGA448 - Recommended PCB design rules (0.8 mm pitch, BGA)
Dimension
Recommended values
Pitch
Dpad
0.8 mm
0.320 mm
DS12505 Rev 5
251/260
254
Package information
STM32MP157C/F
Table 124. LFBGA448 - Recommended PCB design rules (0.8 mm pitch, BGA)
Dimension Recommended values
0.520 mm typ.
Dsm
Stencil opening
Stencil thickness
0.320 mm
0.125 mm to 0.100 mm
Device marking
The following figure gives an example of topside marking orientation versus ball A1 identifier
location.
The printed markings may differ depending on the supply chain.
Other optional marking or inset/upset marks, which identify the parts throughout supply
chain operations, are not indicated below.
Figure 75. LFBGA448 marking (package top view)
Product
identification
STM32MP15xxAAx
Revision
R
Y WW
MSv60333V1
1. Parts marked as ES or E or accompanied by an Engineering Sample notification letter are not yet qualified
and therefore not approved for use in production. ST is not responsible for any consequences resulting
from such use. In no event will ST be liable for the customer using any of these engineering samples in
production. ST’s Quality department must be contacted prior to any decision to use these engineering
samples to run a qualification activity.
252/260
DS12505 Rev 5
STM32MP157C/F
Package information
7.5
Thermal characteristics
Package thermal characteristics in Table 125 are specified with conditions as per JEDEC
JESD51-6, JESD51-8, JESD51-9, and JESD51-12. These typical values will vary in function
of board thermal characteristics and other components on the board.
Θ
Θ :
Θ
Θjb:
Ψjt:
:
Thermal resistance junction-ambient.
Thermal resistance junction-board.
Thermal resistance junction-top-case.
Thermal parameter junction-board.
Thermal parameter junction-top-case.
JA
JB
:
JC
Motherboard type: four layers, JEDEC 2S2P
Table 125. Thermal characteristics
Value
Natural convection
Symbol
Parameter
Unit
1m/s (200 ft/mn)
TFBGA257 - 257-ball 10x10 mm 0.50/0.65 mm pitch
TFBGA361 - 361-ball 12x12 mm 0.50/0.65 mm pitch
LFBGA354 - 354-ball 16x16 mm 0.80 mm pitch
LFBGA448 - 448-ball 18x18 mm 0.80 mm pitch
TFBGA257 - 257-ball 10x10 mm 0.50/0.65 mm pitch
TFBGA361 - 361-ball 12x12 mm 0.50/0.65 mm pitch
LFBGA354 - 354-ball 16x16 mm 0.80 mm pitch
LFBGA448 - 448-ball 18x18 mm 0.80 mm pitch
TFBGA257 - 257-ball 10x10 mm 0.50/0.65 mm pitch
TFBGA361 - 361-ball 12x12 mm 0.50/0.65 mm pitch
LFBGA354 - 354-ball 16x16 mm 0.80 mm pitch
TLFBGA448 - 448-ball 18x18 mm 0.80 mm pitch
TFBGA257 - 257-ball 10x10 mm 0.50/0.65 mm pitch
TFBGA361 - 361-ball 12x12 mm 0.50/0.65 mm pitch
LFBGA354 - 354-ball 16x16 mm 0.80 mm pitch
LFBGA448 - 448-ball 18x18 mm 0.80 mm pitch
TFBGA257 - 257-ball 10x10 mm 0.50/0.65 mm pitch
TFBGA361 - 361-ball 12x12 mm 0.50/0.65 mm pitch
LFBGA354 - 354-ball 16x16 mm 0.80 mm pitch
LFBGA448 - 448-ball 18x18 mm 0.80 mm pitch
36.079
35.151
34.145
28.545
31.79
30.953
30.121
24.797
(1)
ΘJA
°C/W
19.487
20.555
22.038
17.409
10.768
10.049
9.675
(2)
ΘJB
°C/W
°C/W
°C/W
°C/W
(3)
ΘJC
8.439
18.949
20.002
21.456
16.946
0.383
18.332
19.398
20.894
16.574
0.812
Ψjb (4)
0.354
0.735
Ψjt (5)
0.339
0.658
0.297
0.542
1. Per JEDEC JESD51-9
2. Per JEDEC JESD51-8
3. Per JEDEC JESD51-12 best practice guidelines
4. Per JEDEC JESD51-12.
5. Per JEDEC JESD51-12.
DS12505 Rev 5
253/260
254
Package information
STM32MP157C/F
7.5.1
Reference documents
JESD51-6 Integrated Circuit Thermal Test Method Environmental Conditions - Forced
Convection (Moving Air). Available from www.jedec.org.
JESD51-8 Integrated Circuit Thermal Test Method Environmental Conditions —Junction-to-
Board. Available from www.jedec.org.
JESD51-9 Test Boards for Area Array Surface. Mount Package Thermal. Measurements.
Available from www.jedec.org.
JESD51-12 Guidelines for Reporting and Using Electronic Package Thermal Information.
Available from www.jedec.org.
254/260
DS12505 Rev 5
STM32MP157C/F
Ordering information
8
Ordering information
Table 126. STM32MP157C/F ordering information scheme
STM32 MP 157 AA
Example:
F
1
T
Device family
STM32 = Arm-based 32-bit processor
Product type
MP = MPU product
Device subfamily
157 = STM32MP157 Line
Security option
C = Secure boot, cryptography hardware, 650 MHz
F = Secure boot, cryptography hardware, 800 MHz
Package and pin count
AD = TFBGA257 10x10, 257 balls pitch 0.5 mm
AB = LFBGA354 16x16, 354 balls pitch 0.8 mm
AC = TFBGA361 12x12, 361 balls pitch 0.5 mm
AA = LFBGA448 18x18, 448 balls pitch 0.8 mm
Junction temperature range
1 = -20 °C < TJ < +105 °C
3 = -40 °C < TJ < +125 °C
Options
Blank = no options
Packing
T = tape and reel
No character = tray or tube
For a list of available options (speed, package, etc.) or for further information on any aspect
of this device, please contact your nearest ST sales office.
DS12505 Rev 5
255/260
255
Revision history
STM32MP157C/F
9
Revision history
Table 127. Document revision history
Date
Revision
Changes
07-Feb-2019
1
Initial release.
Updated ADC characteristics on cover page.
Updated Table 1: STM32MP157C/F features and
peripheral counts
Updated Section 3.8.1: Power supply scheme.
Updated Table 7: STM32MP157C/F pin and ball
definitions.
Updated Table 8: Alternate function AF0 to AF7.
Updated Table 10: Voltage characteristics.
Updated Table 13: General operating conditions.
Updated Table 14: Operating conditions at power-up /
power-down.
Updated Table 15: Embedded reset and power control
block characteristics.
Updated Figure 13: VDDCORE rise time from reset.
Updated Table 15: Embedded reset and power control
block characteristics.
Updated Table 16: Embedded reference voltage.
Updated Table 18: REG1V1 embedded regulator
(USB_PHY) characteristics.
Updated Table 19: REG1V2 embedded regulator (DSI)
characteristics.
01-Aug-2019
2
Updated Table 20: REG1V8 embedded regulator
(USB+DSI) characteristics.
Updated Table 21: Current consumption (IDDCORE) in
Run mode.
Updated Table 22: Current consumption (IDD) in Run
mode.
Updated Table 23: Current consumption in Stop mode.
Updated Table 24: Current consumption in LPLV-Stop
mode.
Updated Table 26: Current consumption in VBAT mode.
Updated Table 29: High-speed external user clock
characteristics (digital bypass).
Updated Table 30: High-speed external user clock
characteristics (analog bypass).
Added Table 31: Low-speed external user clock
characteristics (analog bypass).
Added Figure 17: Low-speed external clock source AC
timing diagram (analog bypass).
Updated Table 33: 8-48 MHz HSE oscillator
characteristics.
Updated Figure 19: Typical application with a 24 MHz
crystal.
256/260
DS12505 Rev 5
STM32MP157C/F
Revision history
Table 127. Document revision history
Date
Revision
Changes
Updated Figure 20: Typical application with a
32.768 kHz crystal.
Updated Table 36: HSI oscillator characteristics.
Updated Table 37: CSI oscillator characteristics.
Updated Table 38: LSI oscillator characteristics.
Updated Table 39: PLL1_1600, PLL2_1600
characteristics.
Updated Table 36: HSI oscillator characteristics.
Updated Table 37: CSI oscillator characteristics.
Updated Table 38: LSI oscillator characteristics.
Updated Table 39: PLL1_1600, PLL2_1600
characteristics.
Updated Table 40: PLL3_800, PLL4_800
characteristics.
Updated Table 41: USB_PLL characteristics.
Updated Table 42: DSI_PLL characteristics.
Updated Table 48: EMI characteristics.
Updated Table 49: ESD absolute maximum ratings.
Updated Section : Static latchup
Updated Table 51: I/O current injection susceptibility.
Updated Table 52: I/O static characteristics.
2
01-Aug-2019
Updated Table 53: Output voltage characteristics for all
I/Os except PC13, PC14, PC15 and PI8.
(continued)
Added Table 54: Output voltage characteristics for
PC13, PC14, PC15 and PI8.
Updated Table 55: Output timing characteristics (HSLV
OFF).
Added Figure 23: VIL/VIH for FT I/Os.
Updated Table 76: ADC characteristics.
Updated Table 77: Minimum sampling time versus RAIN
with 47 pF PCB capacitor up to 125 °C and VDDA =
1.6 V.
Updated Table 80: DAC characteristics.
Updated Table 85: DTS characteristics.
Updated Table 86: VBAT ADC monitoring characteristics.
Updated Table 88: Temperature and VBAT monitoring
characteristics for temper detection.
Added Section 6.3.31: Compensation cell.
Updated Table 98: I2C analog filter characteristics.
Added Section 6.3.38: USB High-Speed PHY
characteristics.
Added Section 6.3.39: DSI PHY characteristics.
Added Section 7.5: Thermal characteristics.
Introduced STM32MP157F corresponding to the
800 MHz upgrade of the microprocessor, in all the
document.
04-Feb-2020
3
DS12505 Rev 5
257/260
259
Revision history
STM32MP157C/F
Table 127. Document revision history
Date
Revision
Changes
Updated Table 1: STM32MP157C/F features and
peripheral counts.
Updated Figure 1: STM32MP157C/F block diagram.
Updated Table 4: Timer feature comparison.
Updated Table 7: STM32MP157C/F pin and ball
definitions.
Updated Table 8: Alternate function AF0 to AF7.
Updated Table 9: Alternate function AF8 to AF15.
Updated Table 10: Voltage characteristics.
Updated Table 12: Thermal characteristics.
Updated Table 13: General operating conditions.
Updated Table 21: Current consumption (IDDCORE) in
Run mode.
Updated Table 39: PLL1_1600, PLL2_1600
characteristics.
Updated Section 6.3.12: PLL spread spectrum clock
generation (SSCG) characteristics.
3
04-Feb-2020
(continued)
Updated Table 47: EMS characteristics.
Updated Table 48: EMI characteristics.
Updated Table 76: ADC characteristics.
Updated Table 80: DAC characteristics.
Updated Table 81: DAC accuracy.
Updated Table 82: VREFBUF characteristics.
Updated Table 111: Dynamics characteristics: Ethernet
MAC signals for RGMII.
Updated Figure 61: Ethernet RGMII timing diagram.
Updated Table 113: USB High-Speed PHY
characteristics.
Updated Table 115: Dynamics characteristics: JTAG
characteristics.
Updated Table 116: Dynamics characteristics: SWD
characteristics.
Updated Table 126: STM32MP157C/F ordering
information scheme.
Updated Table 1: STM32MP157C/F features and
peripheral counts.
Updated Table 4: Timer feature comparison.
Updated Table 6: Legend/abbreviations used in the
pinout table.
Updated Table 7: STM32MP157C/F pin and ball
definitions.
08-Sep-2020
4
Updated Table 10: Voltage characteristics.
Updated Table 13: General operating conditions.
Updated Table 27: Low-power mode wakeup timings.
Updated Section : Output buffer timing characteristics
(IO structure with _vh, HSLV option enabled).
258/260
DS12505 Rev 5
STM32MP157C/F
Revision history
Table 127. Document revision history
Date
Revision
Changes
Updated Table 57: Output timing characteristics (HSLV
ON, _vh IO structure).
Added Note to Section : USB OTG_FS characteristics.
Updated Section 7.1: TFBGA257 package information.
Added Note to Figure 64: TFBGA257 - Outline.
Updated Table 117: TFBGA257 - Mechanical data.
Updated Section 7.2: LFBGA354 package information.
Updated Table 119: LFBGA354 - Mechanical data.
Updated Section 7.3: TFBA361 package information.
Updated Table 121: TFBGA361 - Mechanical data.
Updated Section 7.4: LFBGA448 package information.
Added Note for Figure 73: LFBGA448 - Outline..
Updated Table 123: LFBGA448 - Mechanical data.
4
08-Sep-2020
(continued)
Updated Table 124: LFBGA448 - Recommended PCB
design rules (0.8 mm pitch, BGA).
Updated Section 8: Ordering information.
Updated Graphics on cover page.
Updated LCD-TFT and DSI in Table 1:
STM32MP157C/F features and peripheral counts.
15-Dec-2020
5
Updated Table 3.30: LCD-TFT display controller (LTDC).
DS12505 Rev 5
259/260
259
STM32MP157C/F
IMPORTANT NOTICE – PLEASE READ CAREFULLY
STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and
improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on
ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order
acknowledgement.
Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or
the design of Purchasers’ products.
No license, express or implied, to any intellectual property right is granted by ST herein.
Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product.
ST and the ST logo are trademarks of ST. For additional information about ST trademarks, please refer to www.st.com/trademarks. All other
product or service names are the property of their respective owners.
Information in this document supersedes and replaces information previously supplied in any prior versions of this document.
© 2020 STMicroelectronics – All rights reserved
260/260
DS12505 Rev 5
相关型号：
STM32MP157CAC3
1-Gbps Ethernet (RGMII) compliant with IEEE-802.3abWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
STMICROELECTR
STM32MP157CAC3T
Arm® dual Cortex®-A7 800 MHz Cortex®-M4 MPU, 3D GPU, TFT/DSI, 37 comm. interfaces, 29 timers, adv. analog, cryptoWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
STMICROELECTR
STM32MP157CAD1T
Arm® dual Cortex®-A7 800 MHz Cortex®-M4 MPU, 3D GPU, TFT/DSI, 37 comm. interfaces, 29 timers, adv. analog, cryptoWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
STMICROELECTR
STM32MP157CAD3T
Arm® dual Cortex®-A7 800 MHz Cortex®-M4 MPU, 3D GPU, TFT/DSI, 37 comm. interfaces, 29 timers, adv. analog, cryptoWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
STMICROELECTR
STM32MP157D
Arm® dual Cortex®-A7 800 MHz Cortex®-M4 MPU, 3D GPU, TFT/DSI, 37 comm. interfaces, 29 timers, adv. analogWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
STMICROELECTR
STM32MP157DAA1T
Arm® dual Cortex®-A7 800 MHz Cortex®-M4 MPU, 3D GPU, TFT/DSI, 37 comm. interfaces, 29 timers, adv. analogWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
STMICROELECTR
STM32MP157DAA3T
Arm® dual Cortex®-A7 800 MHz Cortex®-M4 MPU, 3D GPU, TFT/DSI, 37 comm. interfaces, 29 timers, adv. analogWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
STMICROELECTR
STM32MP157DAB1T
Arm® dual Cortex®-A7 800 MHz Cortex®-M4 MPU, 3D GPU, TFT/DSI, 37 comm. interfaces, 29 timers, adv. analogWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
STMICROELECTR
STM32MP157DAB3T
Arm® dual Cortex®-A7 800 MHz Cortex®-M4 MPU, 3D GPU, TFT/DSI, 37 comm. interfaces, 29 timers, adv. analogWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
STMICROELECTR
STM32MP157DAC1T
Arm® dual Cortex®-A7 800 MHz Cortex®-M4 MPU, 3D GPU, TFT/DSI, 37 comm. interfaces, 29 timers, adv. analogWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
STMICROELECTR
STM32MP157DAC3T
Arm® dual Cortex®-A7 800 MHz Cortex®-M4 MPU, 3D GPU, TFT/DSI, 37 comm. interfaces, 29 timers, adv. analogWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
STMICROELECTR
STM32MP157DAD1T
Arm® dual Cortex®-A7 800 MHz Cortex®-M4 MPU, 3D GPU, TFT/DSI, 37 comm. interfaces, 29 timers, adv. analogWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
STMICROELECTR
©2020 ICPDF网 联系我们和版权申明