STM32WB35CC [STMICROELECTRONICS]

Ultra-low-power dual core Arm Cortex-M4 MCU 64 MHz, Cortex-M0+ 32 MHz with 256 Kbytes of Flash memory, Bluetooth LE 5.3, 802.15.4, Zigbee, Thread, Matter, USB, AES-256;


型号：	STM32WB35CC
厂家：	ST
描述：	Ultra-low-power dual core Arm Cortex-M4 MCU 64 MHz, Cortex-M0+ 32 MHz with 256 Kbytes of Flash memory, Bluetooth LE 5.3, 802.15.4, Zigbee, Thread, Matter, USB, AES-256
文件：	总165页 (文件大小：2509K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

STM32WB55xx

Multiprotocol wireless 32-bit MCU Arm^®-based Cortex^®-M4

with FPU, Bluetooth^®Low Energy and 802.15.4 radio solution

Datasheet - preliminary data

Features

• Includes ST state-of-the-art patented

technology

• Radio

UFQFPN48

7 mm x 7 mm

solder pad

WLCSP100

0.4 mm pitch

VFQFPN68

8 mm x 8 mm

solder pad

– 2.4 GHz

– RF transceiver supporting Bluetooth

specification v5.0 and

IEEE 802.15.4-2011 PHY and MAC

– High efficiency embedded SMPS

step-down converter with intelligent bypass

mode

– RX Sensitivity: -96 dBm (Bluetooth Low

Energy at 1 Mbps), -100 dBm (802.15.4)

– Ultra-safe, low-power BOR (brownout

reset) with five selectable thresholds

– Programmable output power up to +6 dBm

with 1 dB steps

– Ultra-low-power POR/PDR

– Integrated balun to reduce BOM

– Support for 2 Mbps

– Programmable voltage detector (PVD)

– V

mode with RTC and backup registers

– Dedicated Arm 32-bit Cortex M0 + CPU

for real-time Radio layer

BAT

• Clock sources

– Accurate RSSI to enable power control

– 32 MHz crystal oscillator with integrated

trimming capacitors (Radio and CPU clock)

– Suitable for systems requiring compliance

with radio frequency regulations ETSI EN

300 328, EN 300 440, FCC CFR47 Part 15

and ARIB STD-T66

– 32 kHz crystal oscillator for RTC (LSE)

– Internal low-power 32 kHz (±5%) RC (LSI1)

– Internal low-power 32 kHz (stability ±500

ppm) RC (LSI2)

– Support for external PA

• Ultra-low-power platform

– Internal multispeed 100 kHz to 48 MHz

oscillator, auto-trimmed by LSE (better than

±0.25% accuracy)

– 1.71 V to 3.6 V power supply

– – 40 °C to 85 / 105 °C temperature ranges

– 13 nA shutdown mode

– High Speed internal 16 MHz factory

trimmed RC (±1%)

– 600 nA Standby mode + RTC + 32 KB RAM

– 2.1 µA Stop mode + RTC + 256 KB RAM

– 2x PLL for system clock, USB, SAI and

ADC

– Active-mode MCU + RF (SMPS On)

< 53 µA / MHz

• Memories

– Up to 1 MB Flash memory with sector

protection (PCROP) against R/W

– RX: 3.8 mA

– TX at 0 dBm: 5.5 mA

operations, enabling authentic Bluetooth

Low Energy and 802.15.4 SW stack

• Core: Arm 32-bit Cortex -M4 CPU with FPU,

Adaptive real-time accelerator (ART

– Up to 256 KB SRAM, including 64 KB with

hardware parity check

Accelerator™) allowing 0-wait-state execution

from Flash memory, frequency up to 64 MHz,

MPU, 80 DMIPS and DSP instructions

– 20x32-bit Backup register

– Boot loader supporting, USART, SPI, I2C

and USB interfaces

• Supply and Reset management

October 2018

DS11929 Rev 3

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This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to

change without notice.

www.st.com

STM32WB55xx

– OTA (Over the Air) Bluetooth Low Energy

– 1x independent watchdog

– 1x window watchdog

and 802.15.4 update

– Quad SPI memory interface with XIP

• Security & ID

• Rich Analog peripherals (down to 1.62 V)

– Secure Firmware Installation (SFI) for

– 12-bit ADC 4.26Msps, up to 16-bit with

hardware oversampling, 200 µA/Msps

Bluetooth Low Energy and 802.15.4 SW

stack

– 2x ultra-low-power comparator

– 3x Hardware Encryption AES maximum

256-bit for the application, the Bluetooth

Low Energy and IEEE802.15.4

– Accurate 2.5 V or 2.048 V reference

voltage buffered output

– Customer key storage / key manager

services

• System peripherals

– Inter Processor Communication Controller

– HW Public Key Authority (PKA)

(IPCC) for communication with Bluetooth

– Cryptographic algorithms: RSA, Diffie-

Helman, ECC over GF(p)

Low Energy and 802.15.4

– HW semaphores for resources sharing

between CPUs

– True random number generator (RNG)

– Sector protection against R/W operation

(PCROP)

– 2x DMA controllers (7x channels each)

supporting ADC, SPI, I2C, USART, QSPI,

SAI, AES, Timers

– CRC calculation unit

– 1x USART (ISO 7816, IrDA, SPI Master,

Modbus and Smartcard mode)

– 96-bit unique ID

– 64-bit unique ID. Possibility to derive

– 1x LPUART (Low Power)

– 2x SPI 32 Mbit/s

802.15.5 64-bit and Bluetooth Low Energy

48-bit EUI

– 2x I2C (SMBus/PMBus)

– 1x SAI (dual channel high quality audio)

• Up to 72 fast I/Os, 70 of them 5 V-tolerant

• Development support

– 1x USB 2.0 FS device, crystal-less, BCD

and LPM

– Serial wire debug (SWD), JTAG for the

Application processor

– Touch Sensing controller, up to 28

channels

– Application cross trigger with input and

output

– LCD 8x40 with step-up converter

– 1x 16-bit, four channels advanced timer

– 2x 16-bits, two channels timer

– 1x 32-bits, four channels timer

– 2x 16-bits ultra-low-power timer

– 1x independent Systick

– Embedded Trace Macrocell™ for

application

• All packages are ECOPACK2 compliant

Table 1. Device summary

Reference

Part numbers

STM32WB55CC, STM32WB55RC, STM32WB55VC

STM32WB55CE, STM32WB55RE, STM32WB55VE

STM32WB55CG, STM32WB55RG, STM32WB55VG

STM32WB55xx

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Contents

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

3.1

3.2

3.3

Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Arm^®Cortex^®-M4 core with FPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

3.3.1

3.3.2

3.3.3

3.3.4

Adaptive real-time memory accelerator (ART Accelerator™) . . . . . . . . 17

Memory protection unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Embedded Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Embedded SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

3.4

3.5

3.6

Security and safety . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Boot modes and FW update . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

RF subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

3.6.1

3.6.2

3.6.3

3.6.4

3.6.5

RF front-end block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

BLE general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

802.15.4 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

RF pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Typical RF application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

3.7

Power supply management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

3.7.1

3.7.2

3.7.3

3.7.4

3.7.5

3.7.6

Power supply distribution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Linear voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Reset mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

3.8

3.9

VBAT operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Interconnect matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

3.10 Clocks and startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

3.11 General-purpose inputs/outputs (GPIOs) . . . . . . . . . . . . . . . . . . . . . . . . . 40

3.12 Direct memory access controller (DMA) . . . . . . . . . . . . . . . . . . . . . . . . . . 41

3.13 Interrupts and events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

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3.13.1 Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . 41

3.13.2 Extended Interrupts and Events Controller (EXTI) . . . . . . . . . . . . . . . . . 42

3.14 Analog to digital converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

3.14.1 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

3.14.2 Internal voltage reference (VREFINT) . . . . . . . . . . . . . . . . . . . . . . . . . . 43

3.15 Voltage reference buffer (VREFBUF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

3.16 Comparators (COMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

3.17 Touch sensing controller (TSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

3.18 Liquid crystal display controller (LCD) . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

3.19 True random number generator (RNG) . . . . . . . . . . . . . . . . . . . . . . . . . . 45

3.20 Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

3.20.1 Advanced-control timer (TIM1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

3.20.2 General-purpose timers (TIM2, TIM16, TIM17) . . . . . . . . . . . . . . . . . . . 46

3.20.3 Low-power timer (LPTIM1 and LPTIM2) . . . . . . . . . . . . . . . . . . . . . . . . 47

3.20.4 Independent watchdog (IWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

3.20.5 System window watchdog (WWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

3.20.6 SysTick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

3.21 Real-time clock (RTC) and backup registers . . . . . . . . . . . . . . . . . . . . . . 48

3.22 Inter-integrated circuit interface (I²C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

3.23 Universal synchronous/asynchronous receiver transmitter (USART) . . . 50

3.24 Low-power universal asynchronous receiver transmitter (LPUART) . . . . 50

3.25 Serial peripheral interface (SPI1, SPI2) . . . . . . . . . . . . . . . . . . . . . . . . . . 51

3.26 Serial audio interfaces (SAI1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

3.27 Quad-SPI memory interface (QUADSPI) . . . . . . . . . . . . . . . . . . . . . . . . . 52

3.28 Development support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

3.28.1 Serial wire JTAG debug port (SWJ-DP) . . . . . . . . . . . . . . . . . . . . . . . . . 53

3.28.2 Embedded Trace Macrocell™ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Pinouts and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

6.1

Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

6.1.1

Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

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6.1.2

6.1.3

6.1.4

6.1.5

6.1.6

6.1.7

Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

6.2

6.3

Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

6.3.1

6.3.2

6.3.3

6.3.4

6.3.5

6.3.6

6.3.7

6.3.8

6.3.9

Summary of main performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

RF BLE characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

RF 802.15.4 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . 83

Embedded reset and power control block characteristics . . . . . . . . . . . 83

Embedded voltage reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

Wakeup time from Low-power modes and voltage scaling

transition times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

6.3.10 External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 107

6.3.11 Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 109

6.3.12 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

6.3.13 Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

6.3.14 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118

6.3.15 Electrical sensitivity characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

6.3.16 I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 120

6.3.17 I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121

6.3.18 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124

6.3.19 Analog switches booster . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126

6.3.20 Analog-to-Digital converter characteristics . . . . . . . . . . . . . . . . . . . . . 127

6.3.21 Voltage reference buffer characteristics . . . . . . . . . . . . . . . . . . . . . . . . 137

6.3.22 Comparator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139

6.3.23 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 140

6.3.24

monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140

BAT

6.3.25 SMPS step-down converter characteristics . . . . . . . . . . . . . . . . . . . . . 141

6.3.26 LCD controller characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141

6.3.27 Timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142

6.3.28 Communication interfaces characteristics . . . . . . . . . . . . . . . . . . . . . . 143

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Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153

7.1

7.2

7.3

7.4

WLCSP100 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153

VFQFPN68 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153

UFQFPN48 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155

Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158

7.4.1

7.4.2

Reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158

Selecting the product temperature range . . . . . . . . . . . . . . . . . . . . . . 158

Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161

Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162

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List of tables

Table 1.

Table 2.

Table 3.

Table 4.

Table 5.

Table 6.

Table 7.

Table 8.

Device summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

STM32WB55xx family device features and peripheral counts . . . . . . . . . . . . . . . . . . . . . . 13

Access status vs. readout protection level and execution modes . . . . . . . . . . . . . . . . . . . 18

RF pin list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Typical external components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Power supply typical components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Features over all modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

STM32WB55xx modes overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

STM32WB55xx CPU1 peripherals interconnect matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

DMA implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Temperature sensor calibration values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Internal voltage reference calibration values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Timer features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

I2C implementation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Legend/abbreviations used in the pinout table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

STM32WB55xx pin and ball definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

Main performance at VDD = 3.3 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

RF transmitter BLE characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

RF transmitter BLE characteristics (1 Mbps) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

RF transmitter BLE characteristics (2 Mbps) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

RF receiver BLE characteristics (1 Mbps) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

RF receiver BLE characteristics (2 Mbps) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

RF BLE power consumption for VDD = 3.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

RF transmitter 802.15.4 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

RF receiver 802.15.4 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

RF 802.15.4 power consumption for VDD = 3.3 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

Embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 83

Embedded internal voltage reference. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

Current consumption in Run and Low-power run modes, code with data processing

running from Flash, ART enable (Cache ON Prefetch OFF), VDD = 3.3 V . . . . . . . . . . . . 87

Current consumption in Run and Low-power run modes, code with data processing

running from SRAM1, VDD = 3.3 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

Typical current consumption in Run and Low-power run modes, with different codes

running from Flash, ART enable (Cache ON Prefetch OFF), VDD= 3.3 V. . . . . . . . . . . . . 89

Typical current consumption in Run and Low-power run modes,

Table 9.

Table 10.

Table 11.

Table 12.

Table 13.

Table 14.

Table 15.

Table 16.

Table 17.

Table 18.

Table 19.

Table 20.

Table 21.

Table 22.

Table 23.

Table 24.

Table 25.

Table 26.

Table 27.

Table 28.

Table 29.

Table 30.

Table 31.

Table 32.

Table 33.

Table 34.

Table 35.

Table 36.

Table 37.

Table 38.

with different codes running from SRAM1, VDD = 3.3 V . . . . . . . . . . . . . . . . . . . . . . . . . . 90

Current consumption in Sleep and Low-power sleep modes, Flash memory ON . . . . . . . 91

Current consumption in Low-power sleep modes, Flash memory in Power down . . . . . . . 91

Current consumption in Stop 2 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

Current consumption in Stop 1 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

Current consumption in Stop 0 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

Current consumption in Standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

Table 39.

Table 40.

Table 41.

Table 42.

Table 43.

Table 44.

DS11929 Rev 3

7/165

List of tables

STM32WB55xx

Table 45.

Table 46.

Table 47.

Table 48.

Table 49.

Table 50.

Table 51.

Table 52.

Table 53.

Table 54.

Table 55.

Table 56.

Table 57.

Table 58.

Table 59.

Table 60.

Table 61.

Table 62.

Table 63.

Table 64.

Table 65.

Table 66.

Table 67.

Table 68.

Table 69.

Table 70.

Table 71.

Table 72.

Table 73.

Table 74.

Table 75.

Table 76.

Table 77.

Table 78.

Table 79.

Table 80.

Table 81.

Table 82.

Table 83.

Table 84.

Table 85.

Table 86.

Table 87.

Table 88.

Table 89.

Table 90.

Table 91.

Table 92.

Table 93.

Table 94.

Table 95.

Current consumption in Shutdown mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

Current consumption in VBAT mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

Current under Reset condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

Low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

Regulator modes transition times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

Wakeup time using LPUART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

HSE crystal requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

HSE oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

HSI16 oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

MSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

HSI48 oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114

LSI1 oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

LSI2 oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

PLL, PLLSAI1 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

Flash memory endurance and data retention. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118

EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120

I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120

I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121

Output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

I/O AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125

Analog switches booster characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126

ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127

Maximum ADC RAIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129

ADC accuracy - Limited test conditions 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130

ADC accuracy - Limited test conditions 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132

ADC accuracy - Limited test conditions 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133

ADC accuracy - Limited test conditions 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135

VREFBUF characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137

COMP characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139

TS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140

monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140

charging characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140

BAT

SMPS step-down converter characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141

LCD controller characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141

TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142

IWDG min/max timeout period at 32 kHz (LSI1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143

Minimum I2CCLK frequency in all I2C modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143

I2C analog filter characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144

SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144

Quad-SPI characteristics in SDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147

Quad-SPI characteristics in DDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148

SAI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150

USB electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152

VFQFPN68, 8 x 8 mm, 0.4 mm pitch, very thin fine pitch quad flat

mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154

8/165

DS11929 Rev 3

STM32WB55xx

List of tables

Table 96.

UFQFPN48 - 48-lead, 7 x 7 mm, 0.5 mm pitch, ultra thin fine pitch quad flat

package mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156

Package thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158

STM32WB55xx ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161

Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162

Table 97.

Table 98.

Table 99.

DS11929 Rev 3

9/165

List of figures

STM32WB55xx

List of figures

Figure 1.

Figure 2.

Figure 3.

Figure 4.

Figure 5.

Figure 6.

Figure 7.

Figure 8.

Figure 9.

STM32WB55xx block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

STM32WB55xx RF front-end block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

STM32WB55xx external components for the RF part . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Power distribution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Power-up/down sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Power supply overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Clock tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

(1)(2)

STM32WB55xxCx UFQFPN48 pinout

STM32WB55xxRx VFQFPN68 pinout

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

(1)(2)

(1)

Figure 10. STM32WB55xxVx WLCSP100 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Figure 11. Pin loading conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

Figure 12. Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

Figure 13. Power supply scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

Figure 14. Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

Figure 15. Typical link quality indicator code vs. Rx level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

Figure 16. Typical energy detection (T = 27°C, VDD = 3.3 V). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

Figure 17. VREFINT vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

Figure 18. Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

Figure 19. HSI16 frequency vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

Figure 20. Typical current consumption vs. MSI frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114

Figure 21. HSI48 frequency vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

Figure 22. I/O input characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

Figure 23. Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125

Figure 24. ADC accuracy characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136

Figure 25. Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137

Figure 26. SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145

Figure 27. SPI timing diagram - slave mode and CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146

Figure 28. SPI timing diagram - master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146

Figure 29. Quad-SPI timing diagram - SDR mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149

Figure 30. Quad-SPI timing diagram - DDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149

Figure 31. SAI master timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151

Figure 32. SAI slave timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151

Figure 33. VFQFPN68, 8 x 8 mm, 0.4 mm pitch, very thin fine pitch quad flat

package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153

Figure 34. VFQFPN68, 8 x 8 mm, 0.4 mm pitch, very thin fine pitch quad flat

recommended footprint. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154

Figure 35. UFQFPN48 - 48-lead, 7 x 7 mm, 0.5 mm pitch, ultra thin fine pitch quad flat

package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155

Figure 36. UFQFPN48 - 48-lead, 7 x 7 mm, 0.5 mm pitch, ultra thin fine pitch quad flat

package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156

Figure 37. UFQFPN48 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157

10/165

DS11929 Rev 3

STM32WB55xx

Introduction

This datasheet provides the ordering information and mechanical device characteristics of

(a)

the STM32WB55xx microcontrollers, based on Arm cores

This document should be read in conjunction with the STM32WB55xx reference manual

(RM0434).

For information on the Arm Cortex -M4 and Cortex -M0+ cores, refer, respectively, to the

Cortex -M4 Technical Reference Manual and to the Cortex -M0+ Technical Reference

Manual, both available on the www.arm.com website.

For information on 802.15.4 refer to the IEEE website (www.ieee.org).

For information on Bluetooth refer to www.bluetooth.com.

a. Arm is a registered trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere.

DS11929 Rev 3

11/165

Description

STM32WB55xx

Description

The STM32WB55xx multiprotocol wireless and ultra-low-power devices embed a powerful

and ultra-low-power radio compliant with the Bluetooth Low Energy SIG specification v5.0

and with IEEE 802.15.4-2011. They contain a dedicated Arm Cortex -M0+ for performing

all the real-time low layer operation.

The STM32WB55xx devices are designed to be extremely low-power and are based on the

high-performance Arm Cortex -M4 32-bit RISC core operating at a frequency of up to

64 MHz. The Cortex -M4 core features a Floating point unit (FPU) single precision that

supports all Arm single-precision data-processing instructions and data types. It also

implements a full set of DSP instructions and a memory protection unit (MPU) that

enhances application security.

Enhanced inter-processor communication is provided by the IPCC with six bidirectional

channels. The HSEM provides hardware semaphores used to share common resources

between the two processors.

The STM32WB55xx devices embed high-speed memories (Flash memory up to 1 Mbyte,

up to 256 Kbyte of SRAM), a Quad-SPI Flash memory interface (available on all packages)

and an extensive range of enhanced I/Os and peripherals.

Direct data transfer between memory and peripherals and from memory to memory is

supported by fourteen DMA channels with a full flexible channel mapping by the DMAMUX

peripheral.

The STM32WB55xx devices embed several mechanisms for embedded Flash memory and

SRAM: readout protection, write protection and proprietary code readout protection.

Portions of the memory can be secured for Cortex -M0+ exclusive access.

The two AES encryption engines, PKA and RNG enable lower layer MAC and upper layer

cryptography. A customer key storage feature may be used to keep the keys hidden.

The devices offer one fast 16-bit ADC and two ultra-low-power comparators associated with

a high accuracy reference voltage generator

The STM32WB55xx devices embed a low-power RTC, one advanced 16-bit timer, one

general-purpose 32-bit timer, two general-purpose 16-bit timers, and two 16-bit low-power

timers.

In addition, up to 28 capacitive sensing channels are available. The devices also embed an

integrated LCD driver up to 8x40 or 4x44, with internal step-up converter.

They also feature standard and advanced communication interfaces:

•

one USART (ISO 7816, IrDA, Modbus and Smartcard mode)

one Low Power UART (LPUART)

two I2C (SMBus/PMBus)

two SPI (up to 32 MHz)

one Serial Audio Interface with two channels and three PDMs (SAI)

one USB 2.0 FS device with embedded crystal-less oscillator, supporting BCD and

LPM

•

one Quad-SPI with Execute in Place (XIP) capability

12/165

DS11929 Rev 3

STM32WB55xx

Description

The STM32WB55xx operate in the -40 to +105 °C (+125 °C junction) temperature range

from a 1.71 to 3.6 V power supply. A comprehensive set of power-saving modes enables

the design of low-power applications.

The STM32WB55xx integrate a high efficiency SMPS step-down converter with automatic

bypass mode capability when the V falls below V

(x=1, 2, 3, 4) voltage level (default

BORx

is 2.0 V). It includes independent power supplies for analog input for ADC and comparators,

as well as a 3.3 V dedicated supply input for USB.

A V

dedicated supply allows the devices to back up the LSE 32.768KHz oscillator, the

BAT

RTC and the backup registers, thus enabling the STM32WB55xx to supply these functions

even if the main V is not present through a CR2032-like battery, a Supercap or a small

rechargeable battery.

The STM32WB55xx family offers three packages, from 48 to 100 pins.

Table 2. STM32WB55xx family device features and peripheral counts

Feature

STM32WB55Cx

STM32WB55Rx

STM32WB55Vx

Flash memory density

SRAM density

BLE

256 KB 512 KB 1 MB 256 KB 512 KB 1 MB 256 KB 512 KB 1 MB

128 KB 256 KB 256 KB 128 KB 256 KB 256 KB 128 KB 256 KB 256 KB

V5.0 (2 Mbps)

802.15.4

Yes

1 (16 bits)

Advanced

General purpose

2 (16 bits) + 1 (32 bits)

2 (16 bits)

Timers

Low power

SysTick

SPI

I2C

USART⁽¹⁾

LPUART

SAI

Comm

interface

2 channels

USB FS

QSPI

Yes

RTC

Tamper pin

Wakeup pin

Yes, 4x13

LCD, COMxSEG

GPIOs

Yes, 7x23 or 4x26

Yes, 8x40 or 4x44

Capacitive sensing

1x4

3x4

7x4

16-bit ADC

13 channels

19 channels

Number of channels

(incl. 3 internal)

Internal V_ref

Yes

Analog comparator

DS11929 Rev 3

13/165

Description

STM32WB55xx

Table 2. STM32WB55xx family device features and peripheral counts (continued)

Feature

STM32WB55Cx

STM32WB55Rx

STM32WB55Vx

Max CPU frequency

Operating temperature

Operating voltage

64 MHz

Ambient operating temperature:-40 to +105 °C

Junction temperature: -40 to 125 °C

1.71 to 3.6 V

UFQFPN48

7 mm x 7 mm

0.5 mm pitch, solder pad

VFQFPN68

8 mm x 8 mm

0.4 mm pitch, solder pad

WLCSP100

0.4 mm pitch

Package

1. USART peripheral can be used as SPI.

14/165

DS11929 Rev 3

STM32WB55xx

Description

Figure 1. STM32WB55xx block diagram

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DS11929 Rev 3

15/165

Functional overview

STM32WB55xx

Functional overview

3.1

Architecture

The STM32WB55xx multiprotocol wireless devices embed a BLE and an 802.15.4

RF subsystem that interfaces with a generic microcontroller subsystem using an Arm

Cortex -M4 CPU (called CPU1) on which the host application resides.

The RF subsystem is composed of a RF Analog Front end, BLE and 802.15.4 digital MAC

blocks as well as of a dedicated Arm Cortex -M0+ microcontroller (called CPU2) plus

some proprietary peripherals. The RF subsystem performs all of the BLE and 802.15.4 low

layer stack, reducing the interaction with the CPU1 to high level exchanges.

Some functions are shared between the RF subsystem CPU (CPU2) and the Host CPU

(CPU1):

•

Flash memories

SRAM1, SRAM2a and SRAM2b (SRAM2a can be retained in Standby mode)

Security peripherals (RNG, AES1, PKA)

Clock RCC

Power control (PWR)

The communication and the sharing of peripherals between the RF subsystem and the

Cortex -M4 CPU is performed through a dedicated Inter Processor Communication

Controller (IPCC) and semaphore mechanism (HSEM).

3.2

Arm^®Cortex^®-M4 core with FPU

The Arm Cortex -M4 with FPU processor is a processor for embedded systems. It has

been developed to provide a low-cost platform that meets the needs of MCU

implementation, with a reduced pin count and low-power consumption, while delivering

outstanding computational performance and an advanced response to interrupts.

The Arm Cortex -M4 with FPU 32-bit RISC processor features exceptional

code-efficiency, delivering the high-performance expected from an Arm core in the

memory size usually associated with 8- and 16-bit devices.

The processor supports a set of DSP instructions which allow efficient signal processing and

complex algorithm execution.

Its single precision FPU speeds up software development by using metalanguage

development tools, while avoiding saturation.

With its embedded Arm core, the STM32WB55xx family is compatible with all Arm tools

and software.

Figure 1 shows the general block diagram of the STM32WB55xx family devices.

16/165

DS11929 Rev 3

STM32WB55xx

Functional overview

3.3

Memories

3.3.1

Adaptive real-time memory accelerator (ART Accelerator™)

The ART Accelerator™ is a memory accelerator which is optimized for STM32 industry-

standard Arm Cortex -M4 processors. It balances the inherent performance advantage of

the Arm Cortex -M4 over Flash memory technologies, that normally require the processor

to wait for the Flash memory at higher frequencies.

To release the processor near 80 DMIPS performance at 64 MHz, the accelerator

implements an instruction prefetch queue and branch cache, which increases program

execution speed from the 64-bit Flash memory. Based on CoreMark benchmark, the

performance achieved thanks to the ART accelerator is equivalent to 0 wait state program

execution from Flash memory at a CPU frequency up to 64 MHz.

3.3.2

Memory protection unit

The memory protection unit (MPU) is used to manage the CPU1 accesses to memory to

prevent one task to accidentally corrupt the memory or resources used by any other active

task. This memory area is organized into up to 8 protected areas that can in turn be divided

up into 8 subareas. The protection area sizes are between 32 bytes and the whole 4

gigabytes of addressable memory.

The MPU is especially helpful for applications where some critical or certified code has to be

protected against the misbehavior of other tasks. It is usually managed by an RTOS (real-

time operating system). If a program accesses a memory location that is prohibited by the

MPU, the RTOS can detect it and take action. In an RTOS environment, the kernel can

dynamically update the MPU area setting, based on the process to be executed.

The MPU is optional and can be bypassed for applications that do not need it.

3.3.3

Embedded Flash memory

STM32WB55xx devices feature up to 1 Mbyte of embedded Flash memory available for

storing programs and data, as well as some customer keys.

Flexible protections can be configured thanks to option bytes:

•

Readout protection (RDP) to protect the whole memory. Three levels are available:

–

Level 0: no readout protection

Level 1: memory readout protection: the Flash memory cannot be read from or

written to if either debug features are connected, boot in SRAM or bootloader is

selected

–

Level 2: chip readout protection: debug features (Cortex -M4 and Cortex -M0+

JTAG and serial wire), boot in SRAM and bootloader selection are disabled (JTAG

fuse). This selection is irreversible.

DS11929 Rev 3

17/165

Functional overview

STM32WB55xx

Table 3. Access status vs. readout protection level and execution modes

Debug, boot from SRAM or boot

from system memory (loader)

User execution

Write

Protection

level

Area

Read

Erase

Read

Write

Erase

Yes

N/A

Yes

N/A

Yes

N/A

Main

memory

System

memory

N/A

Yes

N/A

Yes

No⁽¹⁾

Yes

Option

bytes

No⁽¹⁾

N/A⁽²⁾

N/A

N/A⁽²⁾

N/A

No⁽²⁾

N/A

Backup

registers

N/A

Yes⁽²⁾

SRAM2a

SRAM2b

Yes

N/A

1. The option byte can be modified by the RF subsystem.

2. Erased when RDP changes from Level 1 to Level 0.

•

Write protection (WRP): the protected area is protected against erasing and

programming. Two areas can be selected, with 4 Kbyte granularity.

Proprietary code readout protection (PCROP): two parts of the Flash memory can be

protected against read and write from third parties. The protected area is execute-only:

it can only be reached by the STM32 CPU, as an instruction code, while all other

accesses (DMA, debug and CPU data read, write and erase) are strictly prohibited.

Two areas can be selected, with 2 KByte granularity. An additional option bit

(PCROP_RDP) allows to select if the PCROP area is erased or not when the RDP

protection is changed from Level 1 to Level 0.

A section of the Flash memory is secured for the RF subsystem CPU2, and cannot be

accessed by the host CPU1.

The whole non-volatile memory embeds the error correction code (ECC) feature supporting:

•

single error detection and correction

double error detection

the address of the ECC fail can be read in the ECC register

The embedded Flash memory is shared between CPU1 and CPU2 on a time sharing basis.

A dedicated HW mechanism allows both CPUs to perform Write/Erase operations.

18/165

DS11929 Rev 3

STM32WB55xx

Functional overview

3.3.4

Embedded SRAM

STM32WB55xx devices feature up to 256 KB of embedded SRAM, split in three blocks:

•

SRAM1: 192 KB mapped at address 0x2000 0000

SRAM2a: 32 KB located at address 0x2003 0000 (contiguous to SRAM1) also mirrored

at 0x1000 0000, with hardware parity check (this SRAM can be retained in Standby

mode)

•

SRAM2b: 32 KB located at address 0x2003 8000 (contiguous with SRAM2a) and

mirrored at 0x1000 8000 with hardware parity check

SRAM2a and SRAM2b can be write-protected, with 1 KB granularity, A section of the

SRAM2a and SRAM2b is secured for the RF sub-system and cannot be accessed by the

host CPU1.

The SRAMs can be accessed in read/write with 0 wait states for all CPU1 and CPU2 clock

speeds.

3.4

Security and safety

The STM32WB55xx contains many security blocks both for the BLE or IEEE 802.14.5 and

the Host application.

It includes:

•

Customer storage of the BLE and 802.14.5 Keys

Secure Flash memory partition for RF subsystem only access

Secure SRAM partition, that can be accessed only by the RF subsystem

True Random Number Generator (RNG)

Advance Encryption Standard hadware accelerators (AES-128bit and AES-256bit,

supporting chaining modes ECB, CBC, CTR, GCM, GMAC, CCM)

•

Private Key Acceleration (PKA) including:

–

Modular arithmetic including exponentiation with maximum modulo size of 3136

bits

–

Elliptic curves over prime field scalar multiplication, ECDSA signature, ECDSA

verification with maximum modulo size of 521 bits

•

Cyclic redundancy check calculation unit (CRC)

A specific mechanism is in place to ensure that all the code executed by the RF subsystem

CPU2 can be secure, whatever the Host application. For the AES1 a customer key can be

managed by the CPU2 and used by the CPU1 to encrypt/decrypt data.

3.5

Boot modes and FW update

At startup, BOOT0 pin and BOOT1 option bit are used to select one of three boot options:

•

Boot from user Flash

Boot from system memory

Boot from embedded SRAM

DS11929 Rev 3

19/165

Functional overview

STM32WB55xx

The STM32WB55xx always boot on CPU1 core. The embedded bootloader code makes it

possible to boot from various peripherals:

•

USB

UART

I2C

SPI

Secure Firmware update (especially BLE and 802.15.4) from system boot and over the air is

provided.

3.6

RF subsystem

The STM32WB55xx embed an ultra-low power multi-standard radio Bluetooth Low Energy

(BLE) and 802.15.4 network processor, compliant with Bluetooth specification v5.0 and

IEEE 802.15.4-2011. The BLE features 1 Mbps and 2 Mbps transfer rates, supports

multiple roles simultaneously acting at the same time as Bluetooth Low Energy sensor and

hub device, embeds Elliptic Curve Diffie-Hellman (ECDH) key agreement protocol, thus

ensuring a secure connection.

The Bluetooth Low Energy stack and 802.15.4 Low Level layer run on an embedded Arm

Cortex -M0+ core (CPU2). The stack is stored on the embedded Flash memory, which is

also shared with the Arm Cortex -M4 (CPU1) application, making it possible in-field stack

update.

3.6.1

RF front-end block diagram

The RF front-end is based on a direct modulation of the carrier in Tx, and uses a low IF

architecture in Rx mode.

Thanks to an internal transformer at RF pins, the circuit directly interfaces the antenna

(single ended connection, impedance close to 50 Ω). The natural bandpass behavior of the

internal transformer, simplifies outside circuitry aimed for harmonic filtering and out of band

interferer rejection.

In Transmit mode, the maximum output power is user selectable through the programmable

LDO voltage of the power amplifier. A linearized, smoothed analog control offers clean

power ramp-up.

In receive mode the circuit can be used in standard high performance or in reduced power

consumption (user programmable). The Automatic Gain Control (AGC) is able to reduce the

chain gain at both RF and IF locations, for optimized interferers rejection. Thanks to the use

of complex filtering and highly accurate I/Q architecture, high sensitivity and excellent

linearity can be achieved.

The bill of material is reduced thanks to the high degree of integration. The radio frequency

source is synthesized form an external 32 MHz crystal that does not need any external

trimming capacitor network thanks to a dual network of user programmable integrated

capacitors.

20/165

DS11929 Rev 3

STM32WB55xx

Functional overview

Figure 2. STM32WB55xx RF front-end block diagram

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3.6.2

BLE general description

The BLE block is a master/slave processor, compliant with Bluetooth specification 5.0

standard (2 Mbps).

It integrates a 2.4 GHz RF transceiver and a powerful Cortex -M0+ core, on which a

complete power-optimized stack for Bluetooth Low Energy protocol runs, providing

master / slave role support

•

GAP: central, peripheral, observer or broadcaster roles

ATT/GATT: client and server

SM: privacy, authentication and authorization

L2CAP

Link Layer: AES-128 encryption and decryption

DS11929 Rev 3

21/165

Functional overview

STM32WB55xx

In addition, according to Bluetooth specification v5.0, the BLE block provides:

•

Multiple roles simultaneously support

Master/slave and multiple roles simultaneously

LE Data Packet Length Extension (making it possible to reach 800 kbps at application

level)

•

LE Privacy 1.2

LE Secure Connections

Flexible Internet Connectivity Options

High data rate (2 Mbps)

The device allows the applications to meet the tight peak current requirements imposed by

the use of standard coin cell batteries. When the high efficiency embedded SMPS step-

down converter is used, the RF front end consumption (I

output power (+6 dBm).

) is only 8.1 mA at the highest

tmax

The power efficiency of the subsystem is optimized: while running with the radio and the

applicative cores simultaneously using the SMPS, the Cortex -M4 core consumption

reaches 53 µA / MHz in active mode.

Ultra-low-power sleep modes and very short transition time between operating modes result

in very low average current consumption during real operating conditions, resulting in longer

battery life.

The BLE block integrates a full bandpass balun, thus reducing the need for external

components.

The link between the Cortex -M4 application processor (CPU1) running the application, and

the BLE stack running on the dedicated Cortex -M0+ (CPU2) is performed through a

normalized API, using a dedicated Inter Processor Communication Controller.

22/165

DS11929 Rev 3

STM32WB55xx

Functional overview

3.6.3

802.15.4 general description

The STM32WB55xx embed a dedicated 802.15.4 Hardware MAC

•

Support for 802.15.4 release 2011

Advanced MAC frame filtering; hardwired firewall: Programmable filters based on

source/destination addresses, frame version, security enabled, frame type

•

256-byte RX FIFO; Up to 8 frames capacity, additional frame information (timing, mean

RSSI,LQI)

128-byte TX FIFO with retention

–

Content not lost, retransmissions possible under CPU2 control

•

Automatic frame Acknowledgment, with programmable delay

Advanced channel access features

–

Full CSMA-CA support

Superframe timer

Beaconing support (require LSE),

Flexible TX control with programmable delay

•

Configuration registers with retention available down to Standby mode for

software/auto-restore

•

Autonomous Sniffer, Wakeup based on timer or CPU2 request

Automatic frame transmission/reception/sleep periods, Interrupt to the CPU2 on

particular events

3.6.4

RF pin description

The RF block contains dedicated pins, listed in Table 4.

Table 4. RF pin list

Name

Type

Description

RF1

RF Input/output, must be connected to the antenna through a low pass matching network

OSC_OUT

OSC_IN

I/O

32 MHz main oscillator, also used as HSE source

EXT_PA_TX

External PA transmit control

VDDRF

V_DDDedicated supply, must be connected to V_DD

V_SSTo be connected to GND

VSSRF⁽¹⁾

1. On packages with exposed pad, this pad must be connected to GND plane for correct RF operation.

3.6.5

Typical RF application schematic

The schematic in Figure 3 and the external components listed in Table 4 are purely

indicative. For more details refer to the “Reference design” provided in separate documents.

DS11929 Rev 3

23/165

Functional overview

STM32WB55xx

Figure 3. STM32WB55xx external components for the RF part

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Table 5. Typical external components

Description

Component

Value

Decoupling capacitance for RF

32 MHz crystal⁽¹⁾

100 nf // 100 pF

32 MHz

Antenna filter

Antenna

Antenna filter and matching network

2.4 GHz band antenna

Refer to AN5165

1. e.g. NDK refernce: NX2016SA 32 MHz EXS00A-CS06654.

3.7

Power supply management

3.7.1

Power supply distribution

The device integrate an SMPS step-down converter to improve low power performance

when the V voltage is high enough. This converter has an intelligent mode that

automatically enters in bypass mode when the V voltage falls below a specific BORx

(x = 1, 2, 3 or 4) voltage.

By default, at Reset the SMPS is in bypass mode.

The device can be operated without the SMPS by just wiring its output to V . This is the

case for applications where the voltage is low, or where the power consumption is not

critical.

24/165

DS11929 Rev 3

STM32WB55xx

Functional overview

Figure 4. Power distribution

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Description

Component

Value

SMPS output capacitor⁽¹⁾

4.7 µF

2.2 µH

10 µH

For 8 MHz⁽²⁾

For 4 MHz⁽³⁾

SMPS inductance

1. e.g. GRM155R60J475KE19.

2. e.g. Wurtz 74479774222.

3. e.g. Murata LQM21FN100M70L.

The SMPS can also be switched On or set in bypass mode at any time by the application

software, for example when very accurate ADC measurement are needed.

3.7.2

Power supply schemes

The STM32WB55xx devices have different voltage supplies (see Figure 6) and can operate

within the following voltage ranges:

•

= 1.71 V to 3.6 V: external power supply for I/Os (V

), the internal regulator and

DDIO

system functions such as RF, SMPS, reset, power management and internal clocks. It

is provided externally through VDD pins. V

connected to VDD pins.

and V

must be always

DDRF

DDSMPS

•

= 1.62 V (ADC/COMPs) to 3.6 V: external analog power supply for ADC,

DDA

comparators and voltage reference buffer. The V

voltage level can be independent

DDA

from the V voltage. When not used V

should be connected to V

DDA

•

= 3.0 V to 3.6 V: external independent power supply for USB transceivers.

DDUSB

When not used V

should be connected to V

DDUSB

= 2.5 V to 3.6 V: the LCD controller can be powered either externally through the

LCD

VLCD pin, or internally from an internal voltage generated by the embedded step-up

converter. This converter can generate a V

2.0 V.

voltage up to 3.6 V if V is higher than

LCD

DS11929 Rev 3

25/165

Functional overview

STM32WB55xx

During power up/ down, the following power sequence requirements must be respected:

•

When V is below 1 V, other power supplies (V

, V

), must remain

LCD

DDA

DDUSB

below V + 300 mV

•

When V is above 1 V, all power supplies are independent.

Figure 5. Power-up/down sequence

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if the energy provided to the MCU remains below 1 mJ. This allows the external decoupling

capacitors to be discharged with different time constants during the power down transient

phase.

Note:

, V

and V must be wired together, so they follow the same voltage

DDSMPS

DDRF

sequence.

26/165

DS11929 Rev 3

STM32WB55xx

Functional overview

Figure 6. Power supply overview

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DS11929 Rev 3

27/165

Functional overview

STM32WB55xx

3.7.3

Linear voltage regulator

Three embedded linear voltage regulators supply most of the digital and RF circuitries, the

main regulator (MR), the low-power regulator (LPR) and the RF regulator (RFR).

•

The MR is used in the Run and Sleep modes and in the Stop 0 mode.

The LPR is used in Low-Power Run, Low-Power Sleep, Stop 1 and Stop 2 modes. It is

also used to supply the SRAM2a in Standby with retention.

•

The RFR is used to supply the RF analog part, its activity is automatically managed by

the RF subsystem.

All the three regulators are in power-down in Standby and Shutdown modes: the regulator

output is in high impedance, and the kernel circuitry is powered down thus inducing zero

consumption.

The ultralow-power STM32WB55xx supports dynamic voltage scaling to optimize its power

consumption in run mode. The voltage from the Main Regulator that supplies the logic

(VCORE) can be adjusted according to the system’s maximum operating frequency.

There are two voltage and frequency ranges:

•

Range 1 with the CPU running up to 64 MHz.

Range 2 with a maximum CPU frequency of 16 MHz (note that HSE can be active in

this mode). All peripheral clocks are also limited to 16 MHz.

The VCORE can also be supplied by the low-power regulator, the main regulator being

switched off. The system is then in Low-power run mode. In this case the CPU is running at

up to 2 MHz, and peripherals with independent clock can be clocked by HSI16 (in this mode

the RF subsystem is not available).

3.7.4

Power supply supervisor

The device has an integrated ultra-low-power brown-out reset (BOR) active in all modes

except Shutdown and ensuring proper operation after power-on and during power down.

The device remains in reset mode when the monitored supply voltage V is below a

specified threshold, without the need for an external reset circuit.

The lowest BOR level is 1.71 V at power on, and other higher thresholds can be selected

through option bytes.The device features an embedded programmable voltage detector

(PVD) that monitors the V power supply and compares it with the V

threshold. An

PVD

interrupt can be generated when V drops below the V

threshold and/or when V is

PVD

higher than the V

threshold. The interrupt service routine can then generate a warning

PVD

message and/or put the MCU into a safe state. The PVD is enabled by software.

In addition, the devices embeds a Peripheral Voltage Monitor that compares the

independent supply voltage V

functional supply range.

with a fixed threshold to ensure that the peripheral is in its

DDA

Any BOR level can also be used to automatically switch the SMPS step-down converter in

bypass mode when the V voltage drops below a given voltage level. The mode of

operation is selectable by register bit, the BOR level is selectable by option byte.

3.7.5

Low-power modes

The ultra-low-power STM32WB55xx supports eight low-power modes to achieve the best

compromise between low-power consumption, short startup time, available peripherals and

available wakeup sources.

28/165

DS11929 Rev 3

STM32WB55xx

Functional overview

By default, the microcontroller is in Run mode, range 1, after a system or a power on Reset.

It is up to the user to select one of the low-power modes described below:

•

Sleep

In Sleep mode, only the CPU1 is stopped. All peripherals, including the RF subsystem,

continue to operate and can wake up the CPU when an interrupt/event occurs.

•

Low-power run

This mode is achieved with VCORE supplied by the low-power regulator to minimize

the regulator's operating current. The code can be executed from SRAM or from Flash,

and the CPU1 frequency is limited to 2 MHz. The peripherals with independent clock

can be clocked by HSI16. The RF subsystem is not available in this mode and must be

OFF.

•

Low-power sleep

This mode is entered from the low-power run mode. Only the CPU1 clock is stopped.

When wakeup is triggered by an event or an interrupt, the system reverts to the

low-power run mode. The RF subsystem is not available in this mode and must be

OFF.

Stop 0, Stop 1 and Stop 2

Stop mode achieves the lowest power consumption while retaining the content of all

the SRAM and registers. The LSE (or LSI) is still running.

The RTC can remain active (Stop mode with RTC, Stop mode without RTC).

Some peripherals with wakeup capability can enable the HSI16 RC during Stop mode

to detect their wakeup condition.

Three Stop modes are available: Stop 0, Stop 1 and Stop 2 modes. In Stop 2 mode,

most of the VCORE domain is put in a lower leakage mode.

Stop 1 offers the largest number of active peripherals and wakeup sources, a smaller

wakeup time but a higher consumption than Stop 2. In Stop 0 mode, the main regulator

remains ON, allowing a very fast wakeup time but with much higher consumption.

In these modes the RF subsystem can wait for incoming events in all Stop modes 0, 1,

and 2.

The system clock when exiting from Stop 0, Stop1 or Stop2 modes can be either MSI

up to 48 MHz or HSI16 if the RF subsystem is disabled. If the RF subsystem or the

SMPS is used the exits must be set to HSI16 only. If used, the SMPS is restarted

automatically.

•

Standby

The Standby mode is used to achieve the lowest power consumption with BOR. The

internal regulator is switched off so that the VCORE domain is powered off.

The RTC can remain active (Standby mode with RTC).

The brown-out reset (BOR) always remains active in Standby mode.

The state of each I/O during standby mode can be selected by software: I/O with

internal pull-up, internal pull-down or floating.

After entering Standby mode, SRAM1, SRAM2b and register contents are lost except

for registers in the Backup domain and Standby circuitry. Optionally, SRAM2a can be

retained in Standby mode, supplied by the low-power Regulator (Standby with 32 KB

SRAM2a retention mode).

The device exits Standby mode when an external reset (NRST pin), an IWDG reset,

WKUP pin event (configurable rising or falling edge), or an RTC event occurs (alarm,

DS11929 Rev 3

29/165

Functional overview

STM32WB55xx

periodic wakeup, timestamp, tamper) or a failure is detected on LSE (CSS on LSE, or

from the RF system wakeup).

The system clock after wakeup is 16 MHz, derived from the HSI16. If used, the SMPS

is restarted automatically.

In this mode the RF can be used.

•

Shutdown

The Shutdown mode allows to achieve the ultimate lowest power consumption. The

internal regulator is switched off so that the VCORE domain is powered off.

The RTC can remain active (Shutdown mode with RTC, Shutdown mode without RTC).

The BOR is not available in Shutdown mode. No power voltage monitoring is possible

in this mode, therefore the switch to Backup domain is not supported.

SRAM1, SRAM2a, SRAM2b and register contents are lost except for registers in the

Backup domain.

The device exits Shutdown mode when an external reset (NRST pin), a WKUP pin

event (configurable rising or falling edge), or an RTC event occurs (alarm, periodic

wakeup, timestamp, tamper).

The system clock after wakeup is 4 MHz, derived from the MSI.

In this mode the RF is no longer operational.

When the RF subsystem is active, it will change the power state according to its needs

(Run, Stop, Standby). This operation is transparent for the CPU1 host application and

managed by a dedicated HW state machine. At any given time the effective power state

reached is the higher one needed by both the CPU1 and RF sub-system.

Table 7 summarizes the peripheral features over all available modes. Wakeup capability is

detailed in gray cells.

(1)

Table 7. Features over all modes

Stop0/Stop1

Stop 2

Standby Shutdown

Peripheral

CPU1

CPU2

Radio System

(BLE, 802.15.4)

Y⁽²⁾

Y⁽³⁾Y⁽³⁾

Flash memory (up to 1 MB)

SRAM1 (up to 192 KB)

SRAM2a (32 KB)

SRAM2b (32 KB)

Quad-SPI

Y ⁽⁴⁾

Y⁽⁶⁾

O⁽⁵⁾O⁽⁵⁾

Y⁽⁶⁾

R⁽⁷⁾

Backup Registers

30/165

DS11929 Rev 3

STM32WB55xx

Functional overview

Standby Shutdown

(1)

Table 7. Features over all modes (continued)

Stop0/Stop1 Stop 2

Peripheral

Brown-out reset (BOR)

Programmable Voltage

Detector (PVD)

Peripheral Voltage Monitor

PVMx (x=1, 2)

SMPS

O⁽⁸⁾

DMAx (x = 1, 2)

High Speed Internal

(HSI16)

O⁽⁹⁾

Oscillator HSI48

High Speed External

(HSE)⁽¹⁰⁾

Low Speed Internal

(LSI1 or LSI2)

Low Speed External (LSE)

Multi-Speed Internal

(MSI)⁽¹¹⁾

PLLx VCO maximum

frequency

344 128

Clock Security System

(CSS)

O⁽¹²⁾

Clock Security System on

LSE

RTC / Auto wakeup

Number of RTC Tamper

pins

LCD

USB FS

USART1

O⁽¹³⁾O⁽¹³⁾

Low-power UART

(LPUART1)

O⁽¹³⁾O⁽¹³⁾O⁽¹³⁾O⁽¹³⁾

O⁽¹⁴⁾O⁽¹⁴⁾

O⁽¹⁴⁾O⁽¹⁴⁾O⁽¹⁴⁾O⁽¹⁴⁾

I2C1

I2C3

SPIx (x=1, 2)

DS11929 Rev 3

31/165

Functional overview

STM32WB55xx

(1)

Table 7. Features over all modes (continued)

Stop0/Stop1 Stop 2

Standby Shutdown

Peripheral

SAI1

ADC1

VREFBUF

COMPx (x=1, 2)

Temperature sensor

Timers TIMx

(x=1, 2, 16, 17)

Low-power Timer 1

(LPTIM1)

Low-power Timer 2

(LPTIM2)

Independent watchdog

(IWDG)

Window watchdog

(WWDG)

SysTick timer

Touch sensing controller

(TSC)

True random number

generator (RNG)

AES2 hardware accelerator

CRC calculation unit

IPCC

HSEM

pins

(15)

(16)

GPIOs

1. Legend: Y = Yes (Enabled), O = Optional (Disabled by default, can be enabled by software), R = Data retained,

- = Not available.

2. Bluetooth^®Low Energy not possible in this mode.

3. Standby with SRAM2a Retention mode only.

4. Flash memory programming only possible in Range 1 voltage, not in Range 2 and not in Low Power mode.

5. The Flash memory can be configured in Power-down mode. By default, it is not in Power-down mode.

6. The SRAM clock can be gated on or off.

7. SRAM2a content is preserved when the bit RRS is set in PWR_CR3 register.

8. Stop 0 only. SMPS is automatically switched to Bypass or Open mode during Low power operation.

32/165

DS11929 Rev 3

STM32WB55xx

Functional overview

9. Some peripherals with wakeup from Stop capability can request HSI16 to be enabled. In this case, HSI16 is woken up by

the peripheral, and only feeds the peripheral which requested it. HSI16 is automatically put off when the peripheral does not

need it anymore.

10. The HSE can be used by the RF subsystem according with the need to perform RF operation (Tx or Rx).

11. MSI maximum frequency.

12. In case RF will be used and HSE will fail.

13. UART and LPUART reception is functional in Stop mode, and generates a wakeup interrupt on Start, address match or

received frame event.

14. I2C address detection is functional in Stop mode, and generates a wakeup interrupt in case of address match.

15. I/Os can be configured with internal pull-up, pull-down or floating in Standby mode.

16. I/Os can be configured with internal pull-up, pull-down or floating in Shutdown mode but the configuration is lost when

exiting the Shutdown mode.

DS11929 Rev 3

33/165

Table 8. STM32WB55xx modes overview

Mode

Regulator CPU1

Flash

SRAM

Clocks

DMA and Peripherals

Wakeup source

Consumption⁽¹⁾Wakeup time⁽²⁾

Range 1

Yes

Range2

All

107 µA/MHz

N/A

100 µA/MHz

Run

ON⁽³⁾⁽⁴⁾

Any

N/A

All except RNG and USB-FS⁽⁵⁾

LPRun

Sleep

LPR

Yes

ON⁽³⁾

except All except RF, RNG and USB-FS

PLL

N/A

103 µA/MHz

15.33 µs

9 cycles

Range 1

Range 2

All

41 µA/MHz

46 µA/MHz

Any interrupt

or event

ON⁽⁶⁾

Any

All except RNG and USB-FS⁽⁵⁾

Any

Any interrupt

or event

LPSleep

LPR

All except RF, RNG and USB-FS

except

PLL

45 µA/MHz

Reset pin, all I/Os,

RF, BOR, PVD, PVM

RF⁽⁵⁾, BOR, PVD, PVM

RTC, LCD, IWDG

Range 1

RTC, LCD, IWDG

COMPx (x=1, 2)

USART1

COMPx (x=1, 2)

LSE,

USART1⁽⁹⁾

LSI,

Stop 0

OFF

100 µA

1.7 µs

HSE⁽⁷⁾

LPUART1⁽⁹⁾

I2Cx (x=1, 3)⁽¹⁰⁾

LPUART1

HSI16⁽⁸⁾

Range 2

I2Cx (x=1, 3)

LPTIMx (x=1, 2)

USB

LPTIMx (x=1, 2), SMPS

All other peripherals are frozen.

Reset pin, all I/Os

RF, BOR, PVD, PVM

RTC, LCD, IWDG

COMPx (x=1, 2)

USART1

RF, BOR, PVD, PVM

RTC, LCD, IWDG

COMPx (x=1, 2)

USART1⁽¹³⁾

LPUART1⁽¹³⁾

I2Cx (x=1, 3)⁽¹⁴⁾

LSE,

LSI,

9.2 µA w/o RTC

9.6 µA w RTC

Stop 1

LPR

OFF

4.7 µs

HSE⁽⁷⁾

HSI16⁽⁸⁾

LPUART1

I2Cx (x=1, 3)

LPTIMx (x=1, 2)

USB

LPTIMx (x=1, 2)

All other peripherals are frozen.

Table 8. STM32WB55xx modes overview (continued)

Mode

Regulator CPU1

Flash

SRAM

Clocks

DMA and Peripherals

Wakeup source

Consumption⁽¹⁾Wakeup time⁽²⁾

RF, BOR, PVD, PVM

RTC, LCD, IWDG

COMPx (x=1, 2)

USART1⁽¹³⁾

Reset pin, all I/Os

RF, BOR, PVD, PVM

RTC, LCD, IWDG

COMPx (x=1, 2)

LPUART1

1.85 µA w/o RTC

5.55 µs

LSE,

LSI

Stop 2

LPR

OFF

LPUART1⁽¹³⁾

2.1 µA w RTC

I2C3⁽¹⁰⁾

I2C3

LPTIM1

All other peripherals are frozen.

RF, BOR, RTC, IWDG

0.32 µA w/o RTC

0.6 µA w RTC

SRAM2a

ON⁽¹¹⁾

LPR

OFF

RF, Reset pin

5 I/Os (WKUPx)⁽¹²⁾

BOR, RTC, IWDG

All other peripherals are

powered off.

LSE,

LSI

Standby

OFF

TBD

TBD µA w/o RTC

I/O configuration can be floating,

pull-up or pull-down

OFF

TBD µA w RTC

RTC

All other peripherals are

powered off.

5 I/Os (WKUPx)⁽¹²⁾

RTC

0.028 µA w/o RTC

TBD

Shutdown

OFF

LSE

0.315 µA w/ RTC

I/O configuration can be floating,

pull-up or pull-down⁽¹³⁾

1. Typical current at V_DD= 1.8 V, 25 °C. for STOPx, SHUTDOWN and Standby, else V_DD= 3.3 V, 25 °C.

2. Add TBD μs when using SMPS, except Sleep, LPSleep and Stop 0 where the SMPS is not stopped.

3. The Flash memory controller can be placed in power-down mode if the RF subsystem is not in use and all the program is run from the SRAM.

4. Flash memory programming is only possible in Range 2 voltage.

5. Bluetooth^®Low Energy not possible in this mode.

6. The SRAM1 and SRAM2 clocks can be gated off independently.

7. HSE (32 MHz) automatically used when RF activity is needed by the RF subsystem.

8. HSI16 (16 MHz) automatically used by some peripherals.

9. U(S)ART and LPUART reception is functional in Stop mode, and generates a wakeup interrupt on Start, Address match or Received frame event.

10. I2C address detection is functional in Stop mode, and generates a wakeup interrupt in case of address match.

11. SRAM1 and SRAM2b are OFF.

12. The I/Os with wakeup from Standby/Shutdown capability are: PA0, PC13, PC12, PA2, PC5.

13. I/Os can be configured with internal pull-up, pull-down or floating but the configuration is lost immediately when exiting the Shutdown mode.

Functional overview

STM32WB55xx

3.7.6

Reset mode

In order to improve the consumption under reset, the I/Os state under and after reset is

“analog state” (the I/O Schmitt trigger is disabled). In addition, the internal reset pull-up is

deactivated when the reset source is internal.

3.8

VBAT operation

The VBAT pin allows to power the device VBAT domain (RTC, LSE and Backup registers)

from an external battery, an external supercapacitor, or from V when no external battery

nor an external supercapacitor are present. Three anti-tamper detection pins are available

in VBAT mode.

VBAT operation is automatically activated when V is not present.

An internal VBAT battery charging circuit is embedded and can be activated when V is

present.

Note:

When the microcontroller is supplied only from VBAT, external interrupts and RTC

alarm/events do not exit it from VBAT operation.

3.9

Interconnect matrix

Several peripherals have direct connections between them. This allows autonomous

communication between peripherals, saving CPU1 resources and, consequently, reducing

power supply consumption. In addition, these hardware connections allow fast and

predictable latency.

Depending on peripherals, these interconnections can operate in Run, Sleep, low-power run

and sleep, Stop 0, Stop 1 and Stop 2 modes.

Table 9. STM32WB55xx CPU1 peripherals interconnect matrix

Source

Destination

Action

TIMx

ADC1

DMA

Timers synchronization or chaining

Conversion triggers

TIMx

Memory to memory transfer trigger

Comparator output blanking

COMPx

TIM1

TIM2

Timer input channel, trigger, break

from analog signals comparison

COMPx

ADCx

Low-power timer triggered by analog

signals comparison

LPTIMERx

TIM1

Y⁽¹⁾

Timer triggered by analog watchdog

DS11929 Rev 3

36/165

STM32WB55xx

Functional overview

Table 9. STM32WB55xx CPU1 peripherals interconnect matrix (continued)

Source

Destination

Action

TIM16

Timer input channel from RTC events

RTC

Low-power timer triggered by RTC

alarms or tampers

LPTIMERx

Y⁽¹⁾

All clocks sources

(internal and external)

TIM2

TIM16, 17

Clock source used as input channel

for RC measurement and trimming

USB

TIM2

Timer triggered by USB SOF

CSS

CPU (hard fault)

SRAM (parity error)

Flash memory (ECC error)

COMPx

TIM1

TIM16,17

Timer break

PVD

TIMx

External trigger

Y⁽¹⁾

GPIO

LPTIMERx External trigger

ADC1 Conversion external trigger

1. LPTIM1 only.

DS11929 Rev 3

37/165

Functional overview

STM32WB55xx

3.10

Clocks and startup

The STM32WB55xx devices integrate many sources of clocks:

•

LSE: 32.768KHz external oscillator, for accurate RTC and calibration with other

embedded RC oscillators

•

LSI1: 32 KHz on-chip low-consumption RC oscillator

LSI2: almost 32 KHz on-chip high-stability RC oscillator, used by the RF subsystem

HSE: high quality 32 MHz external oscillator with trimming, needed by the RF

subsystem

•

HSI16: 16 MHz high accuracy on-chip RC oscillator

MSI: 100 KHz to 48 MHz multiple speed on-chip low power oscillator, can be trimmed

using the LSE signal

•

HSI48: 48 MHz on-chip RC oscillator, for USB crystal-less purpose

The clock controller (see Figure 7) distributes the clocks coming from the different

oscillators to the core and the peripherals including the RF subsystem. It also manages

clock gating for low power modes and ensures clock robustness. It features:

•

Clock prescaler: to get the best trade-off between speed and current consumption,

the clock frequency to the CPU and peripherals can be adjusted by a programmable

prescaler

•

Safe clock switching: clock sources can be changed safely on the fly in run mode

through a configuration register.

Clock management: to reduce power consumption, the clock controller can stop the

clock to the core, individual peripherals or memory.

System clock source: four different clock sources can be used to drive the master

clock SYSCLK:

–

16 MHz high-speed internal RC oscillator (HSI16), trimmable by software, that can

supply a PLL

Multispeed internal RC oscillator (MSI), trimmable by software, able to generate

12 frequencies from 100 kHz to 48 MHz. When a 32.768 kHz clock source is

available in the system (LSE), the MSI frequency can be automatically trimmed by

hardware to reach better than ±0.25% accuracy. The MSI can supply a PLL.

–

System PLL that can be fed by HSE, HSI16 or MSI, with a maximum frequency of

64 MHz.

•

Auxiliary clock source: two ultralow-power clock sources that can be used to drive

the LCD controller and the real-time clock:

–

32.768 kHz low-speed external crystal (LSE), supporting four drive capability

modes. The LSE can also be configured in bypass mode for an external clock.

32 kHz low-speed internal RC (LSI), also used to drive the independent watchdog.

The LSI clock accuracy is ±5%. The LSI source can be either the LSI1 or the LSI2

on-chip oscillator.

Peripheral clock sources: Several peripherals (RNG, SAI, USARTs, I2Cs, LPTimers,

ADC) have their own independent clock whatever the system clock. Two PLLs, each

38/165

DS11929 Rev 3

STM32WB55xx

Functional overview

having three independent outputs allowing the highest flexibility, can generate

independent clocks for the ADC, the RNG and the SAI.

•

Startup clock: after reset, the microcontroller restarts by default with an internal 4 MHz

clock (MSI). The prescaler ratio and clock source can be changed by the application

program as soon as the code execution starts.

Clock security system (CSS): this feature can be enabled by software. If an HSE

clock failure occurs, the master clock is automatically switched to HSI16 and a software

interrupt is generated if enabled. LSE failure can also be detected and an interrupt

generated.

•

Clock-out capability:

–

MCO: microcontroller clock output: it outputs one of the internal clocks for

external use by the application. Low frequency clocks (LSIx, LSE) are available

down to Stop 1 low power state.

–

LSCO: low speed clock output: it outputs LSI or LSE in all low-power modes

down to Standby.

Several prescalers allow the user to configure the AHB frequencies, the high speed APB

(APB2) and the low speed APB (APB1) domains. The maximum frequency of the AHB and

the APB domains is 64 MHz.

DS11929 Rev 3

39/165

Functional overview

STM32WB55xx

Figure 7. Clock tree

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3.11

General-purpose inputs/outputs (GPIOs)

Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as

input (with or without pull-up or pull-down) or as peripheral alternate function. Most of the

GPIO pins are shared with digital or analog alternate functions. Fast I/O toggling can be

achieved thanks to their mapping on the AHB2 bus.

The I/Os alternate function configuration can be locked if needed following a specific

sequence in order to avoid spurious writing to the I/Os registers.

40/165

DS11929 Rev 3

STM32WB55xx

Functional overview

3.12

Direct memory access controller (DMA)

The device embeds two DMAs. Refer to Table 10: DMA implementation for the features

implementation.

Direct memory access (DMA) is used in order to provide high-speed data transfer between

peripherals and memory as well as memory to memory. Data can be quickly moved by DMA

without any CPU actions. This keeps CPU resources free for other operations.

The two DMA controllers have 14 channels in total, a full cross matrix allows any peripheral

to be mapped on any of the available DMA channels. Each has an arbiter for handling the

priority between DMA requests.

The DMA supports:

•

14 independently configurable channels (requests)

A full cross matrix between peripherals and all 14 channels exist. There is also a HW

trigger possibility through the DMAMUX

•

Priorities between requests from channels of one DMA are software programmable (4

levels consisting of very high, high, medium, low) or hardware in case of equality

(request 1 has priority over request 2, etc.)

Independent source and destination transfer size (byte, half word, word), emulating

packing and unpacking. Source/destination addresses must be aligned on the data

size.

•

Support for circular buffer management

3 event flags (DMA Half Transfer, DMA Transfer complete and DMA Transfer Error)

logically ORed together in a single interrupt request for each channel

•

Memory-to-memory transfer

Peripheral-to-memory and memory-to-peripheral, and peripheral-to-peripheral

transfers

•

Access to Flash, SRAM, APB and AHB peripherals as source and destination

Programmable number of data to be transferred: up to 65536.

Table 10. DMA implementation

DMA features

DMA1

DMA2

Number of regular channels

A DMAMUX block makes it possible to route any peripheral source to any DMA channel.

3.13

Interrupts and events

3.13.1

Nested vectored interrupt controller (NVIC)

The devices embed a nested vectored interrupt controller able to manage 16 priority levels,

and handle up to 63 maskable interrupt channels plus the 16 interrupt lines of the

Cortex -M4 with FPU.

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Functional overview

STM32WB55xx

The NVIC benefits are the following:

•

Closely coupled NVIC gives low latency interrupt processing

Interrupt entry vector table address passed directly to the core

Allows early processing of interrupts

Processing of late arriving higher priority interrupts

Support for tail chaining

Processor state automatically saved

Interrupt entry restored on interrupt exit with no instruction overhead

The NVIC hardware block provides flexible interrupt management features with minimal

interrupt latency.

3.13.2

Extended Interrupts and Events Controller (EXTI)

The Extended Interrupts and Events Controller (EXTI) manages wakeup through

configurable and direct event inputs. It provides wake-up requests to the Power Control, and

generates interrupt requests to the CPUx NVIC and events to the CPUx event input.

Configurable events/interrupt come from peripherals able to generate a pulse and allow to

select the Event/Interrupt trigger edge and/or a SW trigger

Direct events/interrupt are coming from peripherals having their own clearing mechanism.

3.14

Analog to digital converter (ADC)

The device embeds a successive approximation analog-to-digital converter with the

following features:

•

12-bit native resolution, with built-in calibration

up to 16-bit resolution with 64 decimation ratio

4.26 Msps maximum conversion rate with full resolution

–

Down to 39 ns sampling time

Increased conversion rate for lower resolution (up to 7.11 Msps for 6-bit

resolution)

•

Up to 16 external channels and three internal channels: internal reference voltages,

temperature sensor

•

Single-ended and differential mode inputs

Low-power design

–

Capable of low-current operation at low conversion rate (consumption decreases

linearly with speed)

–

Dual clock domain architecture: ADC speed independent from CPU frequency

•

Highly versatile digital interface

–

Single-shot or continuous/discontinuous sequencer-based scan mode: two groups

of analog signals conversions can be programmed to differentiate background and

high-priority real-time conversions

–

The ADC supports multiple trigger inputs for synchronization with on-chip timers

and external signals

Results stored into three data register or in SRAM with DMA controller support

42/165

DS11929 Rev 3

STM32WB55xx

Functional overview

–

Data pre-processing: left/right alignment and per channel offset compensation

Built-in oversampling unit for enhanced SNR

Channel-wise programmable sampling time

Three analog watchdog for automatic voltage monitoring, generating interrupts

and trigger for selected timers

–

Hardware assistant to prepare the context of the injected channels to allow fast

context switching

3.14.1

Temperature sensor

The temperature sensor (TS) generates a voltage V that varies linearly with temperature.

The temperature sensor is internally connected to the ADC1_IN17 input channel, which is

used to convert the sensor output voltage into a digital value.

To improve the accuracy of the temperature sensor measurement, each device is

individually factory-calibrated by ST. The temperature sensor factory calibration data are

stored by ST in the system memory area, accessible in read-only mode.

Table 11. Temperature sensor calibration values

Calibration value name

Description

Memory address

TS ADC raw data acquired at a

temperature of 30 °C (± 5 °C),

V_DDA= V_REF+= 3.0 V (± 10 mV)

TS_CAL1

0x1FFF 75A8 - 0x1FFF 75A9

3.14.2

Internal voltage reference (V

)

REFINT

The internal voltage reference (VREFINT) provides a stable (bandgap) voltage output for

the ADC and Comparators. VREFINT is internally connected to the ADC1_IN0 input

channel. The precise voltage of VREFINT is individually measured for each part by ST

during production test and stored in the system memory area. It is accessible in read-only

mode.

Table 12. Internal voltage reference calibration values

Calibration value name

Description

Memory address

Raw data acquired at a

VREFINT

temperature of 30 °C (± 5 °C),

0x1FFF 75AA - 0x1FFF 75AB

V_DDA= V_REF+= 3.6 V (± 10 mV)

3.15

Voltage reference buffer (VREFBUF)

The STM32WB55xx devices embed an voltage reference buffer which can be used as

voltage reference for ADC and also as voltage reference for external components through

the VREF+ pin. The internal voltage reference buffer supports two voltages:

•

2.048 V

2.5 V.

An external voltage reference can be provided through the VREF+ pin when the internal

voltage reference buffer is off. The VREF+ pin is double-bonded with VDDA on UFQFPN48

DS11929 Rev 3

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Functional overview

STM32WB55xx

package, hence the internal voltage reference buffer is not available on a dedicated pin, but

user can still use the VDDA value.

3.16

Comparators (COMP)

The STM32WB55xx devices embed two rail-to-rail comparators with programmable

reference voltage (internal or external), hysteresis and speed (low speed for low-power) and

with selectable output polarity.

The reference voltage can be one of the following:

•

External I/O

Internal reference voltage or submultiple (1/4, 1/2, 3/4).

All comparators can wake up from Stop mode, generate interrupts and breaks for the timers

and can be also combined into a window comparator.

3.17

Touch sensing controller (TSC)

The touch sensing controller provides a simple solution for adding capacitive sensing

functionality to any application. Capacitive sensing technology is able to detect finger

presence near an electrode which is protected from direct touch by a dielectric such as

glass or plastic. The capacitive variation introduced by the finger (or any conductive object)

is measured using a proven implementation based on a surface charge transfer acquisition

principle.

The touch sensing controller is fully supported by the STMTouch touch sensing firmware

library (free to use) and enables reliable touch sensing functionality in the end application.

The main features of the touch sensing controller are the following:

•

Proven and robust surface charge transfer acquisition principle

Supports up to 28 capacitive sensing channels

Up to three capacitive sensing channels can be acquired in parallel offering a very

good response time

•

Spread spectrum feature to improve system robustness in noisy environments

Full hardware management of the charge transfer acquisition sequence

Programmable charge transfer frequency

Programmable sampling capacitor I/O pin

Programmable channel I/O pin

Programmable max count value to avoid long acquisition when a channel is faulty

Dedicated end of acquisition and max count error flags with interrupt capability

One sampling capacitor for up to three capacitive sensing channels to reduce the

system components

•

Compatible with proximity, touchkey, linear and rotary touch sensor implementation

Designed to operate with STMTouch touch sensing firmware library

Note:

The number of capacitive sensing channels is dependent on the size of the packages and

subject to I/O availability.

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Functional overview

3.18

Liquid crystal display controller (LCD)

All device embed an LCD controller with the following characteristics:

•

Highly flexible frame rate control.

Supports Static, 1/2, 1/3, 1/4 and 1/8 duty.

Supports Static, 1/2, 1/3 and 1/4 bias.

Double buffered memory allows data in LCD_RAM registers to be updated at any time

by the application firmware without affecting the integrity of the data displayed.

–

LCD data RAM of up to 16 x 32-bit registers which contain pixel information

(active/inactive)

•

Software selectable LCD output voltage (contrast) from VLCD

No need for external analog components:

to VLCD

max

min

–

A step-up converter is embedded to generate an internal VLCD voltage higher

than V (up to 3.6 V if V > 2.0 V)

–

Software selection between external and internal VLCD voltage source. In case of

an external source, the internal boost circuit is disabled to reduce power

consumption

–

A resistive network is embedded to generate intermediate VLCD voltages

The structure of the resistive network is configurable by software to adapt the

power consumption to match the capacitive charge required by the LCD panel

–

Integrated voltage output buffers for higher LCD driving capability.

•

The contrast can be adjusted using two different methods:

–

When using the internal step-up converter, the software can adjust VLCD between

VLCD and VLCD

min

max

–

Programmable dead time (up to eight phase periods) between frames.

•

Full support of low-power modes: the LCD controller can be displayed in Sleep,

Low-power run, Low-power sleep and Stop modes, or can be fully disabled to reduce

power consumption.

Built in phase inversion for reduced power consumption and EMI (electromagnetic

interference).

•

Start of frame interrupt to synchronize the software when updating the LCD data RAM.

Blink capability:

–

1, 2, 3, 4, 8 or all pixels can be programmed to blink at a configurable frequency

Software adjustable blink frequency to achieve around 0.5 Hz, 1 Hz, 2 Hz or 4 Hz.

Used LCD segment and common pins should be configured as GPIO alternate functions

and unused segment and common pins can be used for general purpose I/O or for another

peripheral alternate function.

Note:

When the LCD relies on the internal step-up converter, the VLCD pin should be connected

to V with a capacitor. Its typical value is 1 μF.

3.19

True random number generator (RNG)

All devices embed a true RNG that delivers 32-bit random numbers generated by an

integrated analog circuit.

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Functional overview

STM32WB55xx

3.20

Timers and watchdogs

The STM32WB55xx includes one advanced 16-bit timer, one general-purpose 32-bit timer,

two 16-bit basic timers, two low-power timers, two watchdog timers and a SysTick timer.

Table 13 compares the features of the advanced control, general purpose and basic timers.

Table 13. Timer features

DMA

request

generation

Capture/

compare

channels

Timer

type

Counter

resolution

Counter

type

Prescaler

factor

Complementary

outputs

Timer

Advanced

control

Up, down,

Up/down

TIM1

TIM2

16-bits

32-bits

16-bits

General

purpose

Up, down,

Up/down

Any integer

between 1

and 65536

General

purpose

TIM16

TIM17

Yes

General

purpose

LPTIM1

LPTIM2

Low power

3.20.1

Advanced-control timer (TIM1)

The advanced-control timer can be seen as a three-phase PWM multiplexed on six

channels. They have complementary PWM outputs with programmable inserted

dead-times. They can also be seen as complete general-purpose timers. The four

independent channels can be used for:

•

Input capture

Output compare

PWM generation (edge or center-aligned modes) with full modulation capability (0-

100%)

•

One-pulse mode output

In debug mode, the advanced-control timer counter can be frozen and the PWM outputs

disabled to turn off any power switches driven by these outputs.

Many features are shared with those of the general-purpose TIMx timers (described in

Section 3.20.2) using the same architecture, so the advanced-control timers can work

together with the TIMx timers via the Timer Link feature for synchronization or event

chaining.

3.20.2

General-purpose timers (TIM2, TIM16, TIM17)

There are up to three synchronizable general-purpose timers embedded in the

STM32WB55xx (see Table 13 for differences). Each general-purpose timer can be used to

generate PWM outputs, or act as a simple time base.

•

TIM2

Full-featured general-purpose timer

–

46/165

DS11929 Rev 3

STM32WB55xx

Functional overview

–

Features four independent channels for input capture/output compare, PWM or

one-pulse mode output. Can work together, or with the other general-purpose

timers via the Timer Link feature for synchronization or event chaining.

–

The counter can be frozen in debug mode.

Independent DMA request generation, support of quadrature encoders.

•

TIM16 and TIM17

–

General-purpose timers with mid-range features:

16-bit auto-reload upcounters and 16-bit prescalers.

1 channel and 1 complementary channel

All channels can be used for input capture/output compare, PWM or one-pulse

mode output.

–

The timers can work together via the Timer Link feature for synchronization or

event chaining. The timers have independent DMA request generation.

The counters can be frozen in debug mode

3.20.3

Low-power timer (LPTIM1 and LPTIM2)

The devices embed two low-power timers. These timers have an independent clock and are

running in Stop mode if they are clocked by LSE, LSIx or by an external clock. They are able

to wakeup the system from Stop mode.

LPTIM1 is active in Stop 0, Stop 1 and Stop 2 modes.

LPTIM2 is active in Stop 0 and Stop 1 mode.

This low-power timer supports the following features:

•

16-bit up counter with 16-bit autoreload register

16-bit compare register

Configurable output: pulse, PWM

Continuous/ one shot mode

Selectable software/hardware input trigger

Selectable clock source

–

Internal clock sources: LSE, either LSI1 or LSI2, HSI16 or APB clock

External clock source over LPTIM input (working even with no internal clock

source running, used by pulse counter application).

•

Programmable digital glitch filter

Encoder mode (LPTIM1 only)

3.20.4

Independent watchdog (IWDG)

The independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. It is

clocked from an independent 32 kHz internal RC (LSI) and as it operates independently

from the main clock, it can operate in Stop and Standby modes. It can be used either as a

watchdog to reset the device when a problem occurs, or as a free running timer for

application timeout management. It is hardware or software configurable through the option

bytes. The counter can be frozen in debug mode.

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Functional overview

STM32WB55xx

3.20.5

System window watchdog (WWDG)

The window watchdog is based on a 7-bit downcounter that can be set as free running. It

can be used as a watchdog to reset the device when a problem occurs. It is clocked from

the main clock. It has an early warning interrupt capability and the counter can be frozen in

debug mode.

3.20.6

SysTick timer

This timer is dedicated to real-time operating systems, but could also be used as a standard

down counter. It features:

•

A 24-bit down counter

Autoreload capability

Maskable system interrupt generation when the counter reaches 0.

Programmable clock source

3.21

Real-time clock (RTC) and backup registers

The RTC is an independent BCD timer/counter. It supports the following features:

•

Calendar with subsecond, seconds, minutes, hours (12 or 24 format), week day, date,

month, year, in BCD (binary-coded decimal) format

•

Automatic correction for 28, 29 (leap year), 30, and 31 days of the month

Two programmable alarms

On-the-fly correction from 1 to 32767 RTC clock pulses. This can be used to

synchronize it with a master clock.

•

Reference clock detection: a more precise second source clock (50 or 60 Hz) can be

used to enhance the calendar precision

Digital calibration circuit with 0.95 ppm resolution, to compensate for quartz crystal

inaccuracy

•

Three anti-tamper detection pins with programmable filter

Timestamp feature which can be used to save the calendar content. This function can

be triggered by an event on the timestamp pin, or by a tamper event, or by a switch to

VBAT mode

•

17-bit auto-reload wakeup timer (WUT) for periodic events with programmable

resolution and period.

The RTC and the 20 backup registers are supplied through a switch that takes power either

from the V supply (when present) or from the VBAT pin.

The backup registers are 32-bit registers used to store 80 bytes of user application data

when V power is not present. They are not reset by a system or power reset, or when the

device wakes up from Standby or Shutdown mode.

The RTC clock sources can be:

•

A 32.768 kHz external crystal (LSE)

An external resonator or oscillator (LSE)

One of the internal low power RC oscillators (LSI1 or LSI2, with typical frequency of

32 kHz)

•

The high-speed external clock (HSE) divided by 32

48/165

DS11929 Rev 3

STM32WB55xx

Functional overview

The RTC is functional in VBAT mode and in all low-power modes when it is clocked by the

LSE. When clocked by one of the LSIs, the RTC is not functional in VBAT mode, but is

functional in all low-power modes except Shutdown mode.

All RTC events (Alarm, WakeUp Timer, Timestamp or Tamper) can generate an interrupt

and wakeup the device from the low-power modes.

3.22

Inter-integrated circuit interface (I2C)

The device embeds two I2Cs. Refer to Table 14 for the features implementation.

The I C bus interface handles communications between the microcontroller and the serial

I C bus. It controls all I C bus-specific sequencing, protocol, arbitration and timing.

The I2C peripheral supports:

•

I²C-bus specification and user manual rev. 5 compatibility:

–

Slave and master modes, multimaster capability

Standard-mode (Sm), with a bitrate up to 100 kbit/s

Fast-mode (Fm), with a bitrate up to 400 kbit/s

Fast-mode Plus (Fm+), with a bitrate up to 1 Mbit/s and 20 mA output drive I/Os

7-bit and 10-bit addressing mode, multiple 7-bit slave addresses

Programmable setup and hold times

Optional clock stretching

•

System Management Bus (SMBus) specification rev 2.0 compatibility:

–

Hardware PEC (Packet Error Checking) generation and verification with ACK

control

–

Address resolution protocol (ARP) support

SMBus alert

•

Power System Management Protocol (PMBus ) specification rev 1.1 compatibility

Independent clock: a choice of independent clock sources allowing the I2C

communication speed to be independent from the PCLK reprogramming. Refer to

Figure 7: Clock tree.

•

Wakeup from Stop mode on address match

Programmable analog and digital noise filters

1-byte buffer with DMA capability

Table 14. I2C implementation

I2C features⁽¹⁾

I2C1

I2C3

Standard-mode (up to 100 kbit/s)

Fast-mode (up to 400 kbit/s)

Fast-mode Plus with 20mA output drive I/Os (up to 1 Mbit/s)

Programmable analog and digital noise filters

SMBus/PMBus hardware support

DS11929 Rev 3

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Functional overview

STM32WB55xx

I2C3

Table 14. I2C implementation (continued)

I2C features⁽¹⁾

I2C1

Independent clock

Wakeup from Stop 0 / Stop 1 mode on address match

Wakeup from Stop 2 mode on address match

1. X: supported

3.23

Universal synchronous/asynchronous receiver transmitter

(USART)

The STM32WB55xx devices feature one universal synchronous receiver transmitter.

This interface provides asynchronous communication, IrDA SIR ENDEC support,

multiprocessor communication mode, single-wire half-duplex communication mode and has

LIN Master/Slave capability. It provides hardware management of the CTS and RTS signals,

and RS485 Driver Enable.

The USART is able to communicate at speeds of up to 4 Mbit/s, and also provides Smart

Card mode (ISO 7816 compliant) and SPI-like communication capability.

The USART supports synchronous operation (SPI mode), and can be used as an SPI

master.

The USART has a clock domain independent from the CPU clock, allowing the it to wake up

the MCU from Stop mode using baudrates up to 200 Kbaud.The wake up events from Stop

mode are programmable and can be:

•

Start bit detection

Any received data frame

A specific programmed data frame

The USART interface can be served by the DMA controller.

3.24

Low-power universal asynchronous receiver transmitter

(LPUART)

The device embeds two Low-Power UARTs, enabling asynchronous serial communication

with minimum power consumption. The LPUARTs support half duplex single wire

communication and modem operations (CTS/RTS), allowing multiprocessor

communication.

The two LPUARTs have a clock domain independent from the CPU clock, and can wakeup

the system from Stop mode using baudrates up to 220 Kbaud. The wake up events from

Stop mode are programmable and can be:

•

Start bit detection

Any received data frame

A specific programmed data frame

Only a 32.768 kHz clock (LSE) is needed to allow LPUART communication up to 9600

baud. Therefore, even in Stop mode, the LPUARTs can wait for an incoming frame while

50/165

DS11929 Rev 3

STM32WB55xx

Functional overview

having an extremely low energy consumption. Higher speed clock can be used to reach

higher baudrates.

The LPUART interfaces can be served by the DMA controller.

3.25

3.26

Serial peripheral interface (SPI1, SPI2)

Two SPI interfaces allow communication up to 32 Mbit/s in master and up to 24 Mbit/s in

slave modes, in half-duplex, full-duplex and simplex modes. The 3-bit prescaler gives 8

master mode frequencies and the frame size is configurable from 4 bits to 16 bits. The SPI

interfaces support NSS pulse mode, TI mode and Hardware CRC calculation.

All SPI interfaces can be served by the DMA controller.

Serial audio interfaces (SAI1)

The device embeds a dual channel SAI peripheral that supports full duplex audio operation.

The SAI bus interface handles communications between the microcontroller and the serial

audio protocol.

The SAI peripheral supports:

•

One independent audio sub-block that can be a transmitter or a receiver, with the

respective FIFO

•

8-word integrated FIFOs

Synchronous or asynchronous mode

Master or slave configuration

Clock generator to target independent audio frequency sampling when audio sub-block

is configured in master mode

•

Data size configurable: 8-, 10-, 16-, 20-, 24-, 32-bit

Peripheral with large configurability and flexibility allowing to target as example the

following audio protocol: I2S, LSB or MSB-justified, PCM/DSP, TDM, AC’97 and SPDIF

out

•

Up to 16 slots available with configurable size and with the possibility to select which

ones are active in the audio frame

•

Number of bits by frame may be configurable

Frame synchronization active level configurable (offset, bit length, level)

First active bit position in the slot is configurable

LSB first or MSB first for data transfer

Mute mode

Stereo/Mono audio frame capability

Communication clock strobing edge configurable (SCK)

Error flags with associated interrupts if enabled respectively

–

Overrun and underrun detection

Anticipated frame synchronization signal detection in slave mode

Late frame synchronization signal detection in slave mode

Codec not ready for the AC’97 mode in reception

DS11929 Rev 3

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Functional overview

STM32WB55xx

•

Interruption sources when enabled:

–

Errors

FIFO requests

DMA interface with two dedicated channels to handle access to the dedicated

integrated FIFO of the SAI audio sub-block.

The PDM (Pulse Density Modulation) block allows the user to manage up to three digital

microphone pairs (with two different clocks). This block performs Right and Left microphone

de-interleaving and time alignment through programmable delay lines in order to properly

feed the SAI.

3.27

Quad-SPI memory interface (QUADSPI)

The Quad-SPI is a specialized communication interface targeting single, dual or quad SPI

Flash memories. It can operate in any of the three following modes:

•

Indirect mode: all the operations are performed using the QUADSPI registers

Status polling mode: the external memory status register is periodically read and an

interrupt can be generated in case of flag setting

•

Memory-mapped mode: the external Flash memory is mapped and is seen by the

system as if it were an internal memory. This mode can be used for the Execute In

Place (XIP)

The Quad-SPI interface supports:

•

Three functional modes: indirect, status-polling, and memory-mapped

SDR and DDR support

Fully programmable opcode for both indirect and memory mapped mode

Fully programmable frame format for both indirect and memory mapped mode

Each of the five following phases can be configured independently (enable, length,

single/dual/quad communication)

–

Instruction phase

Address phase

Alternate bytes phase

Dummy cycles phase

Data phase

•

Integrated FIFO for reception and transmission

8, 16, and 32-bit data accesses are allowed

DMA channel for indirect mode operations

Programmable masking for external Flash memory flag management

Timeout management

Interrupt generation on FIFO threshold, timeout, status match, operation complete, and

access error

52/165

DS11929 Rev 3

STM32WB55xx

Functional overview

3.28

Development support

3.28.1

Serial wire JTAG debug port (SWJ-DP)

The Arm SWJ-DP interface is embedded, and is a combined JTAG and serial wire debug

port that enables either a serial wire debug or a JTAG probe to be connected to the target.

Debug is performed using only two pins instead of the five required by the JTAG (JTAG pins

can then be reused as GPIOs with alternate function): the JTAG TMS and TCK pins are

shared with SWDIO and SWCLK, respectively, and a specific sequence on the TMS pin is

used to switch between JTAG-DP and SW-DP.

3.28.2

Embedded Trace Macrocell™

The Arm Embedded Trace Macrocell provides a greater visibility of the instruction and data

flow inside the CPU core by streaming compressed data at a very high rate from the

STM32WB55xx through a small number of ETM pins to an external hardware trace port

analyzer (TPA) device. Real-time instruction and data flow activity be recorded and then

formatted for display on the host computer that runs the debugger software. TPA hardware

is commercially available from common development tool vendors.

The Embedded Trace Macrocell operates with third party debugger software tools.

DS11929 Rev 3

53/165

Pinouts and pin description

STM32WB55xx

Pinouts and pin description

(1)(2)

Figure 8. STM32WB55xxCx UFQFPN48 pinout

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54/165

DS11929 Rev 3

STM32WB55xx

Pinouts and pin description

(1)

Figure 10. STM32WB55xxVx WLCSP100 ballout

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1. The above figure shows the package top view.

Table 15. Legend/abbreviations used in the pinout table

Abbreviation Definition

Name

Unless otherwise specified in brackets below the pin name, the pin function during and after

reset is the same as the actual pin name

Pin name

Supply pin

Pin type

Input only pin

I/O

RST

Input / output pin

5 V tolerant I/O

3.6 V tolerant I/O

RF I/O

Bidirectional reset pin with weak pull-up resistor

Option for TT or FT I/Os

I/O, Fm+ capable

I/O structure

_f ⁽¹⁾

_l ⁽²⁾

_u⁽³⁾

_a⁽⁴⁾

I/O, with LCD function supplied by V_LCD

I/O, with USB function supplied by V_DDUSB

I/O, with Analog switch function supplied by V_DDA

DS11929 Rev 3

55/165

Pinouts and pin description

STM32WB55xx

Table 15. Legend/abbreviations used in the pinout table (continued)

Abbreviation Definition

Name

Notes

Unless otherwise specified by a note, all I/Os are set as analog inputs during and after reset.

Functions selected through GPIOx_AFR registers

Alternate

functions

Additional

functions

Functions directly selected/enabled through peripheral registers

1. The related I/O structures in Table 16 are: FT_f, FT_fa, FT_fl, FT_fla.

2. The related I/O structures in Table 16 are: FT_l, FT_fl, FT_lu.

3. The related I/O structures in Table 16 are: FT_u, FT_lu.

4. The related I/O structures in Table 16 are: FT_a, FT_la, FT_fa, FT_fla, TT_a, TT_la.

Table 16. STM32WB55xx pin and ball definitions

Pin number

Pin name

(function after

reset)

Alternate functions

Additional functions

TRACECK, SAI1_PDM_CK1,

TSC_G7_IO1, LCD_SEG38,

SAI1_MCLK_A,

PE2

I/O FT_l

CM4_EVENTOUT

TSC_G6_IO4, LCD_SEG33,

LPTIM2_OUT,

CM4_EVENTOUT

PD13

PD14

TIM1_CH1, LCD_SEG34,

CM4_EVENTOUT

I/O FT_l

TIM1_CH2, LCD_SEG35,

CM4_EVENTOUT

C10

PD15

VBAT

PC13

(1)

(2)

RTC_TAMP1/RTC_TS/

RTC_OUT/WKUP2

I/O

CM4_EVENTOUT

(1)

(2)

PC14-

OSC32_IN

D10

I/O

CM4_EVENTOUT

OSC32_IN

(1)

(2)

PC15-

OSC32_OUT

E10

PH0

PH1

I/O

CM4_EVENTOUT

PH3-BOOT0

CM4_EVENTOUT, LSCO

56/165

DS11929 Rev 3

STM32WB55xx

Pin number

Pinouts and pin description

Table 16. STM32WB55xx pin and ball definitions (continued)

Pin name

(function after

reset)

Alternate functions

Additional functions

TIM1_CH2N, SAI1_PDM_CK1,

I2C1_SCL,

PB8

PB9

I/O FT_fl

I/O FT_fla

QUADSPI_BK1_IO1,

LCD_SEG16, SAI1_MCLK_A,

TIM16_CH1, CM4_EVENTOUT

TIM1_CH3N, SAI1_PDM_DI2,

I2C1_SDA, SPI2_NSS,

IR_OUT, TSC_G7_IO4,

QUADSPI_BK1_IO0,

LCD_COM3, SAI1_FS_A,

TIM17_CH1, CM4_EVENTOUT

F10

NRST

PC0

I/O RST

I/O FT_fla

LPTIM1_IN1, I2C3_SCL,

LPUART1_RX, LCD_SEG18,

LPTIM2_IN1,

ADC1_IN1

CM4_EVENTOUT

LPTIM1_OUT, SPI2_MOSI,

I2C3_SDA, LPUART1_TX,

LCD_SEG19,

10 G8

11 G9

12 G10

PC1

PC2

PC3

I/O FT_fla

I/O FT_la

I/O FT_a

ADC1_IN2

ADC1_IN3

ADC1_IN4

CM4_EVENTOUT

LPTIM1_IN2, SPI2_MISO,

LCD_SEG20,

CM4_EVENTOUT

LPTIM1_ETR, SAI1_PDM_DI1,

SPI2_MOSI, LCD_VLCD,

SAI1_SD_A, LPTIM2_ETR,

CM4_EVENTOUT

H10

VSSA

VREF+

VDDA

VSS

13 H8

14 H9

VREFBUF_OUT

(3)

J10

VDD

TIM2_CH1, COMP1_OUT,

SAI1_EXTCLK, TIM2_ETR,

CM4_EVENTOUT

COMP1_INM, ADC1_IN5,

RTC_TAMP2/WKUP1

15 G7

PA0

PA1

I/O FT_a

I/O FT_la

TIM2_CH2, I2C1_SMBA,

SPI1_SCK, LCD_SEG0,

CM4_EVENTOUT

10 16 G8

COMP1_INP, ADC1_IN6

DS11929 Rev 3

57/165

Pinouts and pin description

STM32WB55xx

Table 16. STM32WB55xx pin and ball definitions (continued)

Pin number

Pin name

(function after

reset)

Alternate functions

Additional functions

LSCO, TIM2_CH3,

LPUART1_TX,

COMP2_INM, ADC1_IN7,

WKUP4/LSCO

11 17 F6

PA2

PA3

I/O FT_la

QUADSPI_BK1_NCS,

LCD_SEG1, COMP2_OUT,

CM4_EVENTOUT

TIM2_CH4, SAI1_PDM_CK1,

LPUART1_RX,

12 18 J8

QUADSPI_CLK, LCD_SEG2,

SAI1_MCLK_A,

COMP2_INP, ADC1_IN8

CM4_EVENTOUT

SPI1_NSS, SAI1_FS_B,

LPTIM2_OUT, LCD_SEG5,

CM4_EVENTOUT

COMP1_INM, COMP2_INM,

ADC1_IN9

13 19 K10

14 20 K9

PA4

PA5

I/O FT_a

TIM2_CH1, TIM2_ETR,

SPI1_SCK, LPTIM2_ETR,

SAI1_SD_B, CM4_EVENTOUT

COMP1_INM, COMP2_INM,

ADC1_IN10

TIM1_BKIN, SPI1_MISO,

LPUART1_CTS,

15 21 H7

PA6

PA7

I/O FT_la

I/O FT_fla

QUADSPI_BK1_IO3,

LCD_SEG3, TIM16_CH1,

CM4_EVENTOUT

ADC1_IN11

ADC1_IN12

ADC1_IN15

TIM1_CH1N, I2C3_SCL,

SPI1_MOSI,

QUADSPI_BK1_IO2,

LCD_SEG4, COMP2_OUT,

TIM17_CH1, CM4_EVENTOUT

16 22 H6

MCO, TIM1_CH1,

SAI1_PDM_CK2,

USART1_CK, LCD_COM0,

SAI1_SCK_A, LPTIM2_OUT,

CM4_EVENTOUT

17 23 J7

PA8

PA9

I/O FT_la

I/O FT_fla

TIM1_CH2, SAI1_PDM_DI2,

I2C1_SCL, SPI2_SCK,

USART1_TX, LCD_COM1,

SAI1_FS_A, CM4_EVENTOUT

18 24 K8

COMP1_INM, ADC1_IN16

COMP1_INM, ADC1_IN13

LCD_SEG22,

CM4_EVENTOUT

25 G4

26 H5

PC4

PC5

I/O FT_la

SAI1_PDM_DI3, LCD_SEG23, COMP1_INP, ADC1_IN14,

CM4_EVENTOUT

WKUP5

58/165

DS11929 Rev 3

STM32WB55xx

Pin number

Pinouts and pin description

Table 16. STM32WB55xx pin and ball definitions (continued)

Pin name

(function after

reset)

Alternate functions

Additional functions

RTC_OUT, LPTIM1_OUT,

I2C3_SMBA, SPI1_NSS,

LCD_VLCD, SAI1_EXTCLK,

CM4_EVENTOUT

19 27 K7

PB2

I/O FT_a

I/O FT_fl

COMP1_INP

TIM2_CH3, I2C3_SCL,

SPI2_SCK, LPUART1_RX,

TSC_SYNC, QUADSPI_CLK,

LCD_SEG10, COMP1_OUT,

SAI1_SCK_A,

28 K6

PB10

CM4_EVENTOUT

TIM2_CH4, I2C3_SDA,

LPUART1_TX,

QUADSPI_BK1_NCS,

LCD_SEG11, COMP2_OUT,

CM4_EVENTOUT

29 J6

PB11

I/O FT_fl

20 30 K5

21 31 K4

22 32 K3

VDD

RF1

I/O

(4)

VSSRF

VDDRF

VSSRF

OSC_OUT

OSC_IN

AT0

23 33 J3

(5)

24 34 J2

25 35 J1

26 36 H3

27 37 H4

(5)

(6)

AT1

COMP1_OUT,

CM4_EVENTOUT, EXT_PA_TX

(7)

28 38 H2

29 39 H1

PB0

PB1

I/O

LPUART1_RTS_DE,

LPTIM2_IN1,

CM4_EVENTOUT

VSS

PE3

I/O

CM4_EVENTOUT

30 40 G1

31 41 F2

32 42 F1

PE4

CM4_EVENTOUT

VFBSMPS

VSSSMPS

DS11929 Rev 3

59/165

Pinouts and pin description

STM32WB55xx

Table 16. STM32WB55xx pin and ball definitions (continued)

Pin number

Pin name

(function after

reset)

Alternate functions

Additional functions

33 43 E1

34 44 D1

35 45 B1

VLXSMPS

VDDSMPS

VDD

TIM1_BKIN, I2C3_SMBA,

SPI2_NSS, LPUART1_RTS,

TSC_G1_IO1, LCD_SEG12,

SAI1_FS_A, CM4_EVENTOUT

46 G3

47 C1

48 E2

PB12

PB13

I/O FT_l

I/O FT_fl

TIM1_CH1N, I2C3_SCL,

SPI2_SCK, LPUART1_CTS,

TSC_G1_IO2, LCD_SEG13,

SAI1_SCK_A,

CM4_EVENTOUT

TIM1_CH2N, I2C3_SDA,

SPI2_MISO, TSC_G1_IO3,

LCD_SEG14, SAI1_MCLK_A,

CM4_EVENTOUT

PB14

PB15

I/O FT_fl

I/O FT_l

RTC_REFIN, TIM1_CH3N,

SPI2_MOSI, TSC_G1_IO4,

LCD_SEG15, SAI1_SD_A,

CM4_EVENTOUT

49 F3

50 D2

TSC_G4_IO1, LCD_SEG24,

CM4_EVENTOUT

PC6

PC7

PC8

I/O FT_l

TSC_G4_IO2, LCD_SEG25,

CM4_EVENTOUT

TSC_G4_IO3, LCD_SEG26,

CM4_EVENTOUT

TIM1_BKIN, TSC_G4_IO4,

USB_NOE, LCD_SEG27,

SAI1_SCK_B,

PC9

VSS

I/O FT_l

CM4_EVENTOUT

TIM1_CH3, SAI1_PDM_DI1,

I2C1_SDA, USART1_RX,

USB_CRS_SYNC,

LCD_COM2, SAI1_SD_A,

TIM17_BKIN,

36 51 B5

PA10

PA11

I/O FT_fl

I/O FT_u

CM4_EVENTOUT

TIM1_CH4, TIM1_BKIN2,

SPI1_MISO, USART1_CTS,

USB_DM, CM4_EVENTOUT

37 52 A1

60/165

DS11929 Rev 3

STM32WB55xx

Pin number

Pinouts and pin description

Table 16. STM32WB55xx pin and ball definitions (continued)

Pin name

(function after

reset)

Alternate functions

Additional functions

TIM1_ETR, SPI1_MOSI,

LPUART1_RX,

USART1_RTS_DE, USB_DP,

CM4_EVENTOUT

38 53 A2

PA12

I/O FT_u

JTMS-SWDIO, IR_OUT,

USB_NOE, SAI1_SD_B,

CM4_EVENTOUT

PA13

(JTMS_SWDIO)

(8)

39 54 A5

40 55 B3

41 56 A3

VDDUSB

JTCK-SWCLK, LPTIM1_OUT,

I2C1_SMBA, LCD_SEG5,

SAI1_FS_B, CM4_EVENTOUT

PA14

(JTCK_SWCLK)

(8)

I/O FT_l

JTDI, TIM2_CH1, TIM2_ETR,

SPI1_NSS, TSC_G3_IO1,

LCD_SEG17,

PA15

(JTDI)

(8)

42 57 A4

CM4_EVENTOUT

TRACED1, TSC_G3_IO2,

LCD_COM4/LCD_SEG28/

LCD_SEG40,

58 A6

59 B6

60 C5

PC10

PC11

PC12

I/O FT_l

CM4_EVENTOUT

TSC_G3_IO3,

LCD_COM5/LCD_SEG29/

LCD_SEG41,

CM4_EVENTOUT

TRACED3, TSC_G3_IO4,

LCD_COM6/LCD_SEG30/

LCD_SEG42,

RTC_TAMP3/WKUP3

CM4_EVENTOUT

61 C4

62 C3

PD0

PD1

I/O

SPI2_NSS, CM4_EVENTOUT

SPI2_SCK, CM4_EVENTOUT

TRACED2, TSC_SYNC,

PD2

PD3

PD4

I/O FT_l

LCD_COM7/LCD_SEG31/LCD

_SEG43, CM4_EVENTOUT

SPI2_SCK, SPI2_MISO,

QUADSPI_BK1_NCS,

CM4_EVENTOUT

I/O

SPI2_MOSI, TSC_G5_IO1,

QUADSPI_BK1_IO0,

CM4_EVENTOUT

DS11929 Rev 3

61/165

Pinouts and pin description

STM32WB55xx

Table 16. STM32WB55xx pin and ball definitions (continued)

Pin number

Pin name

(function after

reset)

Alternate functions

Additional functions

TSC_G5_IO2,

QUADSPI_BK1_IO1,

SAI1_MCLK_B,

CM4_EVENTOUT

PD5

PD6

PD7

I/O

SAI1_PDM_DI1, TSC_G5_IO3,

QUADSPI_BK1_IO2,

SAI1_SD_A, CM4_EVENTOUT

TSC_G5_IO4,

QUADSPI_BK1_IO3,

LCD_SEG39,

I/O FT_l

CM4_EVENTOUT

TIM1_BKIN2, LCD_SEG28,

CM4_EVENTOUT

PD8

PD9

I/O FT_l

TRACED0, LCD_SEG29,

CM4_EVENTOUT

TRIG_INOUT, TSC_G6_IO1,

LCD_SEG30,

CM4_EVENTOUT

PD10

PD11

PD12

I/O FT_l

TSC_G6_IO2, LCD_SEG31,

LPTIM2_ETR,

CM4_EVENTOUT

TSC_G6_IO3, LCD_SEG32,

LPTIM2_IN1,

CM4_EVENTOUT

JTDO-TRACESWO,

TIM2_CH2, SPI1_SCK,

USART1_RTS_DE,

LCD_SEG7, SAI1_SCK_B,

CM4_EVENTOUT

PB3

(JTDO)

(8)

43 63 A9

I/O FT_la

I/O FT_fla

COMP2_INM

COMP2_INP

NJTRST, I2C3_SDA,

SPI1_MISO, USART1_CTS,

TSC_G2_IO1, LCD_SEG8,

SAI1_MCLK_B, TIM17_BKIN,

CM4_EVENTOUT

PB4

(NJTRST)

44 64 C7

LPTIM1_IN1, I2C1_SMBA,

SPI1_MOSI, USART1_CK,

LPUART1_TX, TSC_G2_IO2,

LCD_SEG9, COMP2_OUT,

SAI1_SD_B, TIM16_BKIN,

CM4_EVENTOUT

45 65 D6

PB5

I/O FT_l

62/165

DS11929 Rev 3

STM32WB55xx

Pin number

Pinouts and pin description

Table 16. STM32WB55xx pin and ball definitions (continued)

Pin name

(function after

reset)

Alternate functions

Additional functions

LPTIM1_ETR, I2C1_SCL,

USART1_TX, TSC_G2_IO3,

LCD_SEG6, SAI1_FS_B,

TIM16_CH1N, MCO,

46 66 F5

PB6

PB7

I/O FT_fla

COMP2_INP

CM4_EVENTOUT

LPTIM1_IN2, TIM1_BKIN,

I2C1_SDA, USART1_RX,

TSC_G2_IO4, LCD_SEG21,

TIM17_CH1N,

47 67 D7

COMP2_INM, PVD_IN

CM4_EVENTOUT

VSS

VDD

48 68 A10

TIM1_ETR, TSC_G7_IO3,

LCD_SEG36, TIM16_CH1,

CM4_EVENTOUT

PE0

PE1

I/O FT_l

TSC_G7_IO2, LCD_SEG37,

TIM17_CH1, CM4_EVENTOUT

B10

1. PC13, PC14 and PC15 are supplied through the power switch. As this switch only sinks a limited amount of current (3 mA),

the use of the PC13, PC14 and PC15 GPIOs in output mode is limited:

- the speed should not exceed 2 MHz with a maximum load of 30 pF

- these GPIOs must not be used as current sources (e.g. to drive an LED).

2. After a Backup domain power-up, PC13, PC14 and PC15 operate as GPIOs. Their function then depends on the content of

the RTC registers that are not reset by the system reset. For details on how to manage these GPIOs, refer to the Backup

domain and RTC register descriptions in the reference manual RM0351, available on www.st.com.

3. On UFQFPN48 VDDA is connected to VREF+.

4. RF pin, use the nominal PCB layout.

5. 32 MHz oscillator pins, use the nominal PCB layout according to reference design (see AN5165).

6. Reserved for production, must be kept unconnected.

7. High frequency (above 100 KHz) may impact the RF performances.

8. After reset, these pins are configured as JTAG/SW debug alternate functions, and the internal pull-up on PA15, PA13 and

PB4 pins and the internal pull-down on PA14 pin are activated.

DS11929 Rev 3

63/165

Table 17. Alternate functions

AF0

AF1

AF2

AF3

AF4

AF5 AF6

AF7

AF8

AF9

AF10

AF11

AF12

AF13

AF14

AF15

TIM2/

TIM16/

TIM17/

LPTIM2

Port

TIM1/

TIM2/

LPTIM1

SPI2/

SAI1/

TIM1

COMP1/

COMP2/

TIM1

TIM1/

TIM2

I2C1/

I2C3

SPI1/

USB/

QUADSPI

SYS_AF

USART1 LPUART1

TSC

LCD

SAI1

EVENTOUT

SPI2

TIM2_

CH1

COMP1_

OUT

SAI1_

EXTCLK

TIM2_

ETR

CM4_

EVENTOUT

PA0

TIM2_

CH2

I2C1_

SMBA

SPI1_

SCK

CM4_

EVENTOUT

LCD_SEG0

LCD_SEG1

LCD_SEG2

LCD_SEG5

PA1

TIM2_

CH3

LPUART1

_TX

QUADSPI_

BK1_NCS

COMP2_

OUT

CM4_

EVENTOUT

LSCO

PA2

TIM2_

CH4

SAI1_

PDM_CK1

LPUART1

_RX

QUADSPI_

CLK

SAI1

_MCLK_A

CM4_

EVENTOUT

PA3

SPI1_

NSS

SAI1

_FS_B

LPTIM2_

OUT

CM4_

EVENTOUT

PA4

TIM2_

CH1

TIM2_

ETR

SPI1_

SCK

SAI1

_SD_B

LPTIM2_

ETR

CM4_

EVENTOUT

PA5

TIM1_

BKIN

SPI1_

MISO

LPUART1

_CTS

QUADSPI_

BK1_IO3

TIM1_

BKIN

TIM16

_CH1

CM4_

EVENTOUT

LCD_SEG3

LCD_SEG4

LCD_COM0

LCD_COM1

LCD_COM2

PA6

TIM1_

CH1N

I2C3_

SCL

SPI1_

MOSI

QUADSPI_

BK1_IO2

COMP2_

OUT

TIM17

_CH1

CM4_

EVENTOUT

PA7

TIM1_

CH1

SAI1_

PDM_CK2

USART1_

SAI1

_SCK_A

LPTIM2_

OUT

CM4_

EVENTOUT

PA8

MCO

TIM1_

CH2

SAI1_

PDM_DI2

I2C1_

SCL

SPI2_

SCK

USART1_

SAI1

_FS_A

CM4_

EVENTOUT

PA9

TIM1_

CH3

SAI1_

PDM_DI1

I2C1_

SDA

USART1_

USB_CRS

_SYNC

SAI1

_SD_A

TIM17

_BKIN

CM4_

EVENTOUT

PA10

PA11

PA12

PA13

PA14

PA15

TIM1_

CH4

TIM1_

BKIN2

SPI1_

MISO

USART1_

CTS

TIM1_

BKIN2

CM4_

EVENTOUT

USB_DM

TIM1_

ETR

SPI1_

MOSI

USART1_ LPUART1

RTS_DE

CM4_

EVENTOUT

USB_DP

_RX

JTMS-

SWDIO

SAI1

_SD_B

CM4_

EVENTOUT

IR_OUT

USB_NOE

JTCK-

SWCLK

LPTIM1_

OUT

I2C1_

SMBA

SAI1

_FS_B

CM4_

EVENTOUT

LCD_SEG5

LCD_SEG17

TIM2_

CH1

TIM2_

ETR

SPI1_

NSS

TSC_G3

_IO1

CM4_

EVENTOUT

JTDI

Table 17. Alternate functions (continued)

AF0

AF1

AF2

AF3

AF4

AF5 AF6

AF7

AF8

AF9

AF10

AF11

AF12

AF13

AF14

AF15

TIM2/

TIM16/

TIM17/

LPTIM2

Port

TIM1/

TIM2/

LPTIM1

SPI2/

SAI1/

TIM1

COMP1/

COMP2/

TIM1

TIM1/

TIM2

I2C1/

I2C3

SPI1/

USB/

QUADSPI

SYS_AF

USART1 LPUART1

TSC

LCD

SAI1

EVENTOUT

SPI2

EXT

_PA

_TX

COMP1_

OUT

CM4_

EVENTOUT

PB0

LPUART1

_RTS_DE

LPTIM2_

IN1

CM4_

EVENTOUT

PB1

PB2

RTC_

OUT

LPTIM1_

OUT

I2C3_

SMBA

SPI1_

NSS

SAI1_

EXTCLK

CM4_

EVENTOUT

LCD_VLCD

JTDO-

TRACE

SWO

TIM2_

CH2

SPI1_

SCK

USART1_

RTS_DE

SAI1_

SCK_B

CM4_

EVENTOUT

LCD_SEG7

PB3

I2C3_

SDA

SPI1_

MISO

USART1_

CTS

TSC_G2

_IO1

SAI1_

MCLK_B

TIM17_

BKIN

CM4_

EVENTOUT

PB4

NJTRST

LCD_SEG8

LCD_SEG9

LCD_SEG6

LCD_SEG21

LCD_SEG16

LCD_COM3

LCD_SEG10

LCD_SEG11

LCD_SEG12

LCD_SEG13

LCD_SEG14

LCD_SEG15

LPTIM1_

IN1

I2C1_

SMBA

SPI1_

MOSI

USART1_ LPUART1 TSC_G2

COMP2_

OUT

SAI1_

SD_B

TIM16_

BKIN

CM4_

EVENTOUT

PB5

_TX

_IO2

LPTIM1_

ETR

I2C1_

SCL

USART1_

TSC_G2

_IO3

SAI1_

FS_B

TIM16_

CH1N

CM4_

EVENTOUT

MCO

PB6

LPTIM1_

IN2

TIM1_

BKIN

I2C1_

SDA

USART1_

TSC_G2

_IO4

TIM17_

CH1N

CM4_

EVENTOUT

PB7

TIM1_

CH2N

SAI1_

PDM_CK1

I2C1_

SCL

QUADSPI_

BK1_IO1

SAI1_

MCLK_A

TIM16_

CH1

CM4_

EVENTOUT

PB8

TIM1_

CH3N

SAI1_

PDM_DI2

I2C1_

SDA

SPI2_

NSS

TSC_G7 QUADSPI_

_IO4

SAI1_

FS_A

TIM17_

CH1

CM4_

EVENTOUT

IR_OUT

PB9

BK1_IO0

TIM2_

CH3

I2C3_

SCL

SPI2_SC

LPUART1

_RX

TSC

_SYNC

QUADSPI_

CLK

COMP1_

OUT

SAI1_

SCK_A

CM4_

EVENTOUT

PB10

PB11

PB12

PB13

PB14

PB15

TIM2_

CH4

I2C3_

SDA

LPUART1

_TX

QUADSPI_

BK1_NCS

COMP2_

OUT

CM4_

EVENTOUT

TIM1_

BKIN

TIM1_

BKIN

I2C3_

SMBA

SPI2_

NSS

LPUART1 TSC_G1

_RTS _IO1

SAI1_

FS_A

CM4_

EVENTOUT

TIM1_

CH1N

I2C3_

SCL

SPI2_

SCK

LPUART1 TSC_G1

SAI1_

SCK_A

CM4_

EVENTOUT

_CTS

_IO2

TIM1_

CH2N

I2C3_

SDA

SPI2_

MISO

TSC_G1

_IO3

SAI1_

MCLK_A

CM4_

EVENTOUT

RTC_

REFIN

TIM1_

CH3N

SPI2_

MOSI

TSC_G1

_IO4

SAI1_

SD_A

CM4_

EVENTOUT

Table 17. Alternate functions (continued)

AF0

AF1

AF2

AF3

AF4

AF5 AF6

AF7

AF8

AF9

AF10

AF11

AF12

AF13

AF14

AF15

TIM2/

TIM16/

TIM17/

LPTIM2

Port

TIM1/

TIM2/

LPTIM1

SPI2/

SAI1/

TIM1

COMP1/

COMP2/

TIM1

TIM1/

TIM2

I2C1/

I2C3

SPI1/

USB/

QUADSPI

SYS_AF

USART1 LPUART1

TSC

LCD

SAI1

EVENTOUT

SPI2

LPTIM1_

IN1

I2C3

_SCL

LPUART1

_RX

LPTIM2_

IN1

CM4_

EVENTOUT

LCD_SEG18

LCD_SEG19

LCD_SEG20

LCD_VLCD

LCD_SEG22

LCD_SEG23

LCD_SEG24

LCD_SEG25

LCD_SEG26

PC0

LPTIM1_

OUT

SPI2_

MOSI

I2C3

_SDA

LPUART1

_TX

CM4_

EVENTOUT

PC1

PC2

PC3

PC4

PC5

PC6

PC7

PC8

PC9

LPTIM1_

IN2

SPI2_

MISO

CM4_

EVENTOUT

LPTIM1_

ETR

SAI1_

PDM_DI1

SPI2_

MOSI

SAI1

_SD_A

LPTIM2_

ETR

CM4_

EVENTOUT

CM4_

EVENTOUT

SAI1_

PDM_DI3

CM4_

EVENTOUT

TSC_G4

_IO1

CM4_

EVENTOUT

TSC_G4

_IO2

CM4_

EVENTOUT

TSC_G4

_IO3

CM4_

EVENTOUT

TIM1

_BKIN

TSC_G4

_IO4

SAI1

_SCK_B

CM4_

EVENTOUT

USB_NOE LCD_SEG27

LCD_COM4

TRACE

TSC_G3

_IO2

CM4_

EVENTOUT

PC10

PC11

PC12

LCD_SEG28

LCD_SEG40

LCD_COM5

LCD_SEG29

LCD_SEG41

TSC_G3

_IO3

CM4_

EVENTOUT

LCD_COM6

LCD_SEG30

LCD_SEG42

TRACE

TSC_G3

_IO4

CM4_

EVENTOUT

CM4_

EVENTOUT

PC13

PC14

PC15

CM4_

EVENTOUT

CM4_

EVENTOUT

Table 17. Alternate functions (continued)

AF0

AF1

AF2

AF3

AF4

AF5 AF6

AF7

AF8

AF9

AF10

AF11

AF12

AF13

AF14

AF15

TIM2/

TIM16/

TIM17/

LPTIM2

Port

TIM1/

TIM2/

LPTIM1

SPI2/

SAI1/

TIM1

COMP1/

COMP2/

TIM1

TIM1/

TIM2

I2C1/

I2C3

SPI1/

USB/

QUADSPI

SYS_AF

USART1 LPUART1

TSC

LCD

SAI1

EVENTOUT

SPI2

SPI2_

CM4_

EVENTOUT

PD0

NSS

SPI2_

CM4_

EVENTOUT

PD1

PD2

SCK

LCD_COM7

LCD_SEG31

LCD_SEG43

TRACE

TSC_

SYNC

CM4_

EVENTOUT

SPI2_

MISO

QUADSPI_

BK1_NCS

CM4_

EVENTOUT

SPI2_SCK

PD3

SPI2_

MOSI

TSC_

G5_IO1

QUADSPI_

BK1_IO0

CM4_

EVENTOUT

PD4

TSC_

G5_IO2

QUADSPI_

BK1_IO1

SAI1_

MCLK_B

CM4_

EVENTOUT

PD5

SAI1_

PDM_DI1

TSC_

G5_IO3

QUADSPI_

BK1_IO2

SAI1_

SD_A

CM4_

EVENTOUT

PD6

TSC_

G5_IO4

QUADSPI_

BK1_IO3

CM4_

EVENTOUT

LCD_SEG39

LCD_SEG28

LCD_SEG29

LCD_SEG30

LCD_SEG31

LCD_SEG32

LCD_SEG33

LCD_SEG34

LCD_SEG35

PD7

TIM1

_BKIN2

CM4_

EVENTOUT

PD8

TRACE

CM4_

EVENTOUT

PD9

TRIG

_INOUT

TSC_

G6_IO1

CM4_

EVENTOUT

PD10

PD11

PD12

PD13

PD14

PD15

TSC_

G6_IO2

LPTIM2_

ETR

CM4_

EVENTOUT

TSC_

G6_IO3

LPTIM2_

IN1

CM4_

EVENTOUT

TSC_

G6_IO4

LPTIM2_

OUT

CM4_

EVENTOUT

TIM1_

CH1

CM4_

EVENTOUT

TIM1_

CH2

CM4_

EVENTOUT

Table 17. Alternate functions (continued)

AF0

AF1

AF2

AF3

AF4

AF5 AF6

AF7

AF8

AF9

AF10

AF11

AF12

AF13

AF14

AF15

TIM2/

TIM16/

TIM17/

LPTIM2

Port

TIM1/

TIM2/

LPTIM1

SPI2/

SAI1/

TIM1

COMP1/

COMP2/

TIM1

TIM1/

TIM2

I2C1/

I2C3

SPI1/

USB/

QUADSPI

SYS_AF

USART1 LPUART1

TSC

LCD

SAI1

EVENTOUT

SPI2

TIM1_

ETR

TSC_

G7_IO3

TIM16_

CH1

CM4_

EVENTOUT

LCD_SEG36

PE0

TSC_

G7_IO2

TIM17_

CH1

CM4_

EVENTOUT

LCD_SEG37

PE1

PE2

PE3

PE4

PH0

PH1

PH3

SAI1_

PDM_CK1

TSC_

G7_IO1

SAI1_

MCLK_A

CM4_

EVENTOUT

TRACECK

LCD_SEG38

CM4_

EVENTOUT

CM4_

EVENTOUT

CM4_

EVENTOUT

CM4_

EVENTOUT

CM4_

EVENTOUT

LSCO

STM32WB55xx

Memory mapping

The STM32WB55xx devices feature a single physical address space that can be accessed

by the application processor and by the RF subsystem.

A part of the Flash memory and of the SRAM2a and SRAM2b memories are made secure,

exclusively accessible by the CPU2, protected against execution, read and write from CPU1

and DMA.

In case of shared resources the SW should implement arbitration mechanism to avoid

access conflicts. This happens for peripherals Reset and Clock Controller (RCC), Power

Controller (PWC), EXTI and Flash interface, and can be implemented using the built-in

semaphore block (HSEM).

By default the RF subsystem and CPU2 operate in secure mode. This implies that part of

the Flash and of the SRAM2 memories can only be accessed by the RF subsystem and by

the CPU2. In this case the Host processor (CPU1) has no access to these resources.

The detailed memory map and the peripheral mapping of the STM32WB55xx devices can

be found in the reference manual RM0434.

DS11929 Rev 3

69/165

Electrical characteristics

STM32WB55xx

Electrical characteristics

6.1

Parameter conditions

Unless otherwise specified, all voltages are referenced to V

TBD indicates a value to be defined.

6.1.1

Minimum and maximum values

Unless otherwise specified, the minimum and maximum values are guaranteed in the worst

conditions of ambient temperature, supply voltage and frequencies by tests in production on

100% of the devices with an ambient temperature at T = 25 °C and T = T max (given by

the selected temperature range).

Data based on characterization results, design simulation and/or technology characteristics

are indicated in the table footnotes and are not tested in production. Based on

characterization, the minimum and maximum values refer to sample tests and represent the

mean value plus or minus three times the standard deviation (mean ±3σ).

6.1.2

6.1.3

Typical values

Unless otherwise specified, typical data are based on T = 25 °C, V = V = 3 V. They

DDA

are given only as design guidelines and are not tested.

Typical ADC accuracy values are determined by characterization of a batch of samples from

a standard diffusion lot over the full temperature range, where 95% of the devices have an

error less than or equal to the value indicated (mean ± 2σ).

Typical curves

Unless otherwise specified, all typical curves are given only as design guidelines and are

not tested.

6.1.4

6.1.5

Loading capacitor

The loading conditions used for pin parameter measurement are shown in Figure 11.

Pin input voltage

The input voltage measurement on a pin of the device is described in Figure 12.

Figure 11. Pin loading conditions

Figure 12. Pin input voltage

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70/165

DS11929 Rev 3

STM32WB55xx

Electrical characteristics

6.1.6

Power supply scheme

Figure 13. Power supply scheme

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1. The value of L1 depends upon the frequency, as indicated in Table 6.

DS11929 Rev 3

71/165

152

Electrical characteristics

STM32WB55xx

Caution:

Each power supply pair (V / V , V

/ V

etc.) must be decoupled with filtering

SSA

DDA

ceramic capacitors as shown in Figure 13. These capacitors must be placed as close as

possible to (or below) the appropriate pins on the underside of the PCB to ensure the good

functionality of the device.

6.1.7

Current consumption measurement

Figure 14. Current consumption measurement scheme

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6.2

Absolute maximum ratings

Stresses above the absolute maximum ratings listed in Table 18, Table 19 and Table 20

may cause permanent damage to the device. These are stress ratings only and functional

operation of the device at these conditions is not implied. Exposure to maximum rating

conditions for extended periods may affect device reliability.

(1)

Table 18. Voltage characteristics

Symbol

Ratings

Min

Max

Unit

External main supply voltage

V_DDX- V_SS(including V_DD, V_DDA, V_DDUSB, V_LCD

-0.3

4.0

_DDRF, V_DDSMPS, V_BAT

)

min (V_DD, V_DDA, V_DDUSB, V_LCD, V_DDRF

Input voltage on FT_xxx pins

V_DDSMPS) + 4.0⁽³⁾⁽⁴⁾

(2)

V_SS-0.3

V_IN

Input voltage on TT_xx pins

Input voltage on any other pin

4.0

72/165

DS11929 Rev 3

STM32WB55xx

Symbol

Electrical characteristics

(1)

Table 18. Voltage characteristics (continued)

Ratings

Min

Max

Unit

Variations between different V_DDX

power pins of the same domain

|∆V_DDx

Variations between all the different

ground pins⁽⁵⁾

|V_SSx-V_SS

1. All main power (V_DD, V_DDRF, V_DDA, V_DDUSB, V_LCD, V_BAT) and ground (V_SS, V_SSA) pins must always be connected to the

external power supply, in the permitted range.

2. V_INmaximum must always be respected. Refer to Table 19 for the maximum allowed injected current values.

3. This formula has to be applied only on the power supplies related to the IO structure described in the pin definition table.

4. To sustain a voltage higher than 4 V the internal pull-up/pull-down resistors must be disabled.

5. Include VREF- pin.

Table 19. Current characteristics

Symbol

Ratings

Max

Unit

∑IV_DD

∑IV_SS

Total current into sum of all V_DDpower lines (source)⁽¹⁾

Total current out of sum of all V_SSground lines (sink)⁽¹⁾

Maximum current into each V_DDpower pin (source)⁽¹⁾

Maximum current out of each V_SSground pin (sink)⁽¹⁾

Output current sunk by any I/O and control pin except FT_f

Output current sunk by any FT_f pin

130

100

IV_DD(PIN)

IV_SS(PIN)

I_IO(PIN)

Output current sourced by any I/O and control pin

Total output current sunk by sum of all I/Os and control pins⁽²⁾

Total output current sourced by sum of all I/Os and control pins⁽²⁾

Injected current on FT_xxx, TT_xx, RST and B pins, except PB0 and PB1

Injected current on PB0 and PB1

100

-5 / +0⁽⁴⁾

-5/0

∑I_IO(PIN)

(3)

I_INJ(PIN)

∑|I_INJ(PIN)

Total injected current (sum of all I/Os and control pins)⁽⁵⁾

1. All main power (V_DD, V_DDRF, V_DDA, V_DDUSB, V_BAT) and ground (V_SS, V_SSA) pins must always be connected to the external

power supplies, in the permitted range.

2. This current consumption must be correctly distributed over all I/Os and control pins. The total output current must not be

sunk/sourced between two consecutive power supply pins referring to high pin count packages.

3. Positive injection (when V_IN> V_DD) is not possible on these I/Os and does not occur for input voltages lower than the

specified maximum value.

4. A negative injection is induced by V_IN< V_SS. I_INJ(PIN)must never be exceeded. Refer also to Table 18: Voltage

characteristics for the maximum allowed input voltage values.

5. When several inputs are submitted to a current injection, the maximum ∑|I_INJ(PIN)| is the absolute sum of the negative

injected currents (instantaneous values).

Table 20. Thermal characteristics

Symbol

Ratings

Storage temperature range

Maximum junction temperature

Value

Unit

T_STG

T_J

–65 to +150

130

°C

DS11929 Rev 3

73/165

152

Electrical characteristics

STM32WB55xx

6.3

Operating conditions

6.3.1

Summary of main performance

Table 21. Main performance at V = 3.3 V

Parameter

Test conditions

Typ

Unit

VBAT (V_BAT= 1.8 V, V_DD= 0 V)

Shutdown (V_DD= 1.8 V)

0.002

0.013

Standby (V_DD= 1.8 V,

32 KB RAM retention)

0.320

Stop2

Sleep (16 MHz)

LP run (2 MHz)

1.85

740

I_CORECore current consumption

320

Run (64 MHz)

5000

TBD

Radio RX

µA

Radio TX 0 dBm output power

Advertising

(Tx = 0 dBm; Period 1.28 s;

31 Bytes, 3 channels)

TBD

BLE

Advertising

Connected mode (Tx = 0 dBm, 6 Bytes;

period 300 ms, 3 channels)

Peripheral

I_PERIcurrent

consumption

LP timers

I2C3

TBD

0.450

LPUART

RTC

6.3.2

General operating conditions

Table 22. General operating conditions

Symbol

Parameter

Conditions

Min

Max

Unit

f_HCLKInternal AHB clock frequency

f_PCLK1Internal APB1 clock frequency

f_PCLK2Internal APB2 clock frequency

3.6

MHz

V_DD

Standard operating voltage

1.71⁽¹⁾

1.62

2.4

ADC or COMP used

VREFBUF used

V_DDAAnalog supply voltage

3.6

ADC, COMP, VREFBUF

not used

V_BAT

Backup operating voltage

1.55

74/165

DS11929 Rev 3

STM32WB55xx

Symbol

Electrical characteristics

Table 22. General operating conditions (continued)

Parameter

Conditions

Min

Max

Unit

V_FBSMPSSMPS Feedback voltage

V_DDRFMinimum RF voltage

1.4

1.71

3.0

3.6

USB used

3.6

V_DDUSBUSB supply voltage

USB not used

TT_xx I/O

3.6

–0.3

_DD+ 0.3

min (min (V_DD, V_DDA

V_IN

I/O input voltage

All I/O except TT_xx

–0.3

V_DDUSB, V_LCD) + 3.6 V,

5.5 V)⁽²⁾⁽³⁾

UFQFPN48

392

425

454

Power dissipation at

T_A= 85 °C for suffix 6

P_D

VFQFPN68

T_A= 105 °C for suffix 7⁽⁴⁾

WLCSP100

Maximum power dissipation

Low-power dissipation⁽⁵⁾

Maximum power dissipation

Low-power dissipation⁽⁵⁾

Suffix 6 version

Ambient temperature for the

suffix 6 version

–40

105

125

105

125

T_J

Ambient temperature for the

suffix 7 version

°C

Junction temperature range

Suffix 7 version

1. When RESET is released functionality is guaranteed down to V_BOR0Min.

2. This formula has to be applied only on the power supplies related to the IO structure described by the pin definition table.

Maximum I/O input voltage is the smallest value between min (V_DD, V_DDA, V_DDUSB, V_LCD) + 3.6 V and 5.5V.

3. For operation with voltage higher than min (V_DD, V_DDA, V_DDUSB, V_LCD) + 0.3 V, the internal pull-up and pull-down resistors

must be disabled.

4. If T_Ais lower, higher P_Dvalues are allowed as long as T_Jdoes not exceed T_Jmax (see Section 7.4: Thermal

characteristics).

5. In low-power dissipation state, T_Acan be extended to this range as long as T_Jdoes not exceed T_Jmax (see Section 7.4:

Thermal characteristics).

6.3.3

RF BLE characteristics

RF characteristics are given at 1 Mbps, unless otherwise specified.

Table 23. RF transmitter BLE characteristics

Symbol

Parameter

Test conditions

Min

Typ

Max

Unit

F_op

Frequency operating range

2405

2480

MHz

250

F_xtal

Crystal frequency

Delta frequency

On Air data rate

RF channel spacing

∆F

KHz

Mbps

MHz

Rgfsk

PLLres

DS11929 Rev 3

75/165

152

Electrical characteristics

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(1)

Table 24. RF transmitter BLE characteristics (1 Mbps)

Symbol

Parameter

Test conditions

Min Typ Max Unit

SMPS Bypass (or ON

(V_FBSMPS= 1.7 V) and

V_DD> 1.95 V)

6.0

3.7

Maximum output power

SMPS Bypass (or ON

(V_FBSMPS= 1.4 V) and

V_DD> 1.71 V), Code 29

dBm

P_rf

-20

0 dBm output power

Minimum output power

Tx = 0 dBm - Typical

-0.5

0.4

P_band

Output power variation over the band

670

-58

-61

KHz

BW20dB 20 dB signal bandwidth

2 MHz

Bluetooth^®Low Energy:-20 dBm

IBSE

In band spurious emission

dBm

≥ 3 MHz Bluetooth^®Low Energy: -30 dBm

Bluetooth^®Low Energy: ±50 kHz

-12

KHz

f_d

Frequency drift

Bluetooth^®Low Energy:

±20 KHz / 50 µs

KHz/

50 µs

maxdr

Maximum drift rate

Bluetooth^®Low Energy:

±150 kHz

Frequency offset

Bluetooth^®Low Energy:

between 225 and 275 kHz

246

Frequency deviation average

∆f1

KHz

∆f2

Bluetooth^®Low Energy:> 185 kHz

Bluetooth^®Low Energy:> 0.80

203

Frequency deviation

99.9%

Frequency deviation

0.90

∆fa

∆f2 (average) / ∆f1 (average)

< 1 GHz

≥ 1 GHz

-61

-46

Out of band

spurious emission

OBSE⁽²⁾

dBm

1. :Measured in conducted mode, based on reference design (see AN5165), using output power specific external RF filter and

impedance matching networks to interface with a 50 ꢀ antenna.

2. Suitable for systems targeting compliance with worldwide radio-frequency regulations ETSI EN 300 328 and EN 300 440

Class 2 (Europe), FCC CFR47 Part 15 (US), and ARIB STD-T66 (Japan).

76/165

DS11929 Rev 3

STM32WB55xx

Symbol

Electrical characteristics

(1)

Table 25. RF transmitter BLE characteristics (2 Mbps)

Parameter

Test conditions

Min Typ Max Unit

SMPS Bypass (or ON

(V_FBSMPS= 1.7 V) and

V_DD> 1.95 V)

6.0

3.7

Maximum output power

SMPS Bypass (or ON

(V_FBSMPS= 1.4 V) and

V_DD> 1.71 V), Code 29

dBm

P_rf

-20

0 dBm output power

Minimum output power

Tx = 0 dBm - Typical

-0.5

0.4

P_band

Output power variation over the band

670

-62

-63

-64

KHz

BW20dB 20 dB signal bandwidth

4 MHz

5 MHz

Bluetooth^®Low Energy:-20 dBm

Bluetooth^®Low Energy: -20 dBm

IBSE

f_d

In band spurious emission

dBm

KHz

≥ 6 MHz Bluetooth^®Low Energy: -30 dBm

Bluetooth^®Low Energy: ±50 kHz

-12

Frequency drift

Bluetooth^®Low Energy:

±20 KHz / 50 µs

KHz/

50 µs

maxdr

Maximum drift rate

Frequency offset

Bluetooth^®Low Energy: ±150 kHz

Bluetooth^®Low Energy:

between 450 and 550 kHz

468

Frequency deviation average

∆f1

KHz

∆f2

Bluetooth^®Low Energy:> 370 kHz

Bluetooth^®Low Energy:> 0.80

438

Frequency deviation

99.9%

Frequency deviation

0.97

∆fa

∆f2 (average) / ∆f1 (average)

< 1 GHz

≥ 1 GHz

-61

-46

Out of band

spurious emission

OBSE⁽²⁾

dBm

1. :Measured in conducted mode, based on reference design (see AN5165), using output power specific external RF filter and

impedance matching networks to interface with a 50 ꢀ antenna.

2. Suitable for systems targeting compliance with worldwide radio-frequency regulations ETSI EN 300 328 and EN 300 440

Class 2 (Europe), FCC CFR47 Part 15 (US), and ARIB STD-T66 (Japan).

DS11929 Rev 3

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152

Electrical characteristics

STM32WB55xx

Table 26. RF receiver BLE characteristics (1 Mbps)

Parameter Test conditions

Symbol

Typ

Unit

PER <30.8%

Prx_max

Maximum input signal

Bluetooth^®Low Energy: min -10 dBm

High sensitivity mode (SMPS Bypass)

High sensitivity mode (SMPS ON)

-96

PER <30.8%

Bluetooth^®Low Energy: max -70 dBm

Psens⁽¹⁾

dBm

RSSI maximum value

RSSI minimum value

RSSI accuracy

-7

-94

Rssi_maxrange

Rssi_minrange

Rssi_accu

Co-channel rejection

Bluetooth^®Low Energy: 21 dB

C/Ico

Adj ≥ 5 MHz

-55

-54

-50

-33

-47

-37

-34

Bluetooth^®Low Energy: -27 dB

Adj ≤ -5 MHz

Bluetooth^®Low Energy:-27 dB

Adj = 4 MHz

Bluetooth^®Low Energy:-27 dB

Adj = -4 MHz

Bluetooth^®Low Energy:-15 dB

Adj = 3 MHz

Adjacent channel interference

C/I

Bluetooth^®Low Energy:-27 dB

Adj = 2 MHz

Bluetooth^®Low Energy:-17 dB

Adj = -2 MHz

Bluetooth^®Low Energy:-15 dB

Adj = 1 MHz

Bluetooth^®Low Energy: 15 dB

Adj = -1 MHz

-1

Bluetooth^®Low Energy: 15 dB

C/Image

P_IMD

Image rejection (F_image= -3 MHz)

Intermodulation

Bluetooth^®Low Energy: -9 dB

-26

-35

|f2-f1| = 3 MHz

Bluetooth^®Low Energy: -50 dBm

|f2-f1| = 4 MHz

-30

-35

dBm

Bluetooth^®Low Energy: -50 dBm

|f2-f1| = 5 MHz

Bluetooth^®Low Energy:-50 dBm

78/165

DS11929 Rev 3

STM32WB55xx

Symbol

Electrical characteristics

Table 26. RF receiver BLE characteristics (1 Mbps) (continued)

Parameter Test conditions

Typ

Unit

30 to 2000 MHz

-3

Bluetooth^®Low Energy: -30 dBm

2003 to 2399 MHz

-3

-2

Bluetooth^®Low Energy: -35 dBm

P_OBB

Out of band blocking

dBm

2484 to 2997 MHz

Bluetooth^®Low Energy: -35 dBm

3 to 12.75 GHz

Bluetooth^®Low Energy: -30 dBm

1. With ideal TX.

Table 27. RF receiver BLE characteristics (2 Mbps)

Parameter Test conditions

Symbol

Typ

Unit

PER <30.8%

Prx_max

Maximum input signal

Bluetooth^®Low Energy: min -10 dBm

High sensitivity mode (SMPS Bypass)

High sensitivity mode (SMPS ON)

-92.5

PER <30.8%

Bluetooth^®Low Energy: max -70 dBm

Psens⁽¹⁾

dBm

RSSI maximum value

RSSI minimum value

RSSI accuracy

-7

-94

Rssi_maxrange

Rssi_minrange

Rssi_accu

Co-channel rejection

Bluetooth^®Low Energy spec: 21 dB

C/Ico

Adj ≥ 8MHz

-54

-51

-49

-46

-40

-2

Bluetooth^®Low Energy: -27 dB

Adj ≤ -8 MHz

Bluetooth^®Low Energy:-27 dB

Adj = 6 MHz

Bluetooth^®Low Energy:-27 dB

Adj = -6 MHz

Adjacent channel interference

C/I

Bluetooth^®Low Energy:-15 dB

Adj = 4 MHz

Bluetooth^®Low Energy:-17 dB

Adj = 2 MHz

Bluetooth^®Low Energy:15 dB

Adj = -2 MHz

-4

Bluetooth^®Low Energy:15 dB

C/Image

Image rejection (F_image= -4 MHz)

Bluetooth^®Low Energy: -9 dB

-24

DS11929 Rev 3

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152

Electrical characteristics

STM32WB55xx

Table 27. RF receiver BLE characteristics (2 Mbps) (continued)

Parameter Test conditions

Symbol

Typ

Unit

|f2-f1| = 6 MHz

-27

Bluetooth^®Low Energy: -50 dBm

|f2-f1| = 8 MHz

P_IMD

Intermodulation

-29

-27

-6

Bluetooth^®Low Energy: -50 dBm

|f2-f1| = 10 MHz

Bluetooth^®Low Energy:-50 dBm

30 to 2000 MHz

dBm

Bluetooth^®Low Energy: -30 dBm

2003 to 2399 MHz

-6

Bluetooth^®Low Energy: -35 dBm

P_OBB

Out of band blocking

2484 to 2997 MHz

-2

Bluetooth^®Low Energy: -35 dBm

3 to 12.75 GHz

Bluetooth^®Low Energy: -30 dBm

1. With ideal TX.

Table 28. RF BLE power consumption for V = 3.3 V

Symbol

Parameter

Typ Unit

TX maximum output power consumption (SMPS Bypass)

TX maximum output power consumption (SMPS On, V_FBSMPS= 1.7 V)

TX 0 dBm output power consumption (SMPS Bypass)

TX 0 dBm output power consumption (SMPS On, V_FBSMPS= 1.4 V)

Rx consumption (SMPS Bypass)

13.1

8.1

I_txmax

9.5

5.5

I_tx0dbm

7.0

3.8

I_rxlo

Rx consumption (SMPS On, V_FBSMPS= 1.4 V)

6.3.4

RF 802.15.4 characteristics

Table 29. RF transmitter 802.15.4 characteristics

Symbol

Parameter

Conditions

Min Typ Max Unit

F_op

F_xtal

∆F

Frequency operating range

Crystal frequency

2405

2480

MHz

Delta frequency

Roqpsk On Air data rate

250

Kbps

MHz

PLLres RF channel spacing

80/165

DS11929 Rev 3

STM32WB55xx

Electrical characteristics

Table 29. RF transmitter 802.15.4 characteristics (continued)

Symbol

Parameter

Conditions

Min Typ Max Unit

SMPS Bypass (or ON

(V_FBSMPS= 1.7 V) and

V_DD> 1.95 V)

5.7

3.7

Maximum output power⁽¹⁾

SMPS Bypass (or ON

(V_FBSMPS= 1.4 V) and

V_DD> 1.71 V), Code 29

Prf

dBm

0 dBm output power

-20

Minimum output power

-0.5

Pband Output power variation over the band Tx = 0 dBm - Typical

0.4

EVMrms EVM rms

Txpd Transmit power density

Pmax

|f - fc| > 3.5 MHz

-35

1. Measured in conducted mode, based on reference design (see AN5165), using output power specific

external RF filter and impedance matching networks to interface with a 50 ꢀ antenna.

Table 30. RF receiver 802.15.4 characteristics

Symbol

Parameter

Conditions

Typ

Unit

Prx_max

Maximum input signal

-100

-98

Sensitivity (SMPS Bypass)

Sensitivity (SMPS On)

PER < 1%

dBm

Rsens

Adjacent channel rejection

Alternate channel rejection

C/adj

C/alt

Figure 15. Typical link quality indicator code vs. Rx level

240

220

200

180

160

140

120

100

TEST_NAME

TP/154/PHY24/RECEIVERͲ06/Ch11(2405MHz)

TP/154/PHY24/RECEIVERͲ06/Ch19(2445MHz)

TP/154/PHY24/RECEIVERͲ06/Ch26(2480MHz)

-120-115-110-105-100 -95 -90 -85 -80 -75 -70 -65 -60 -55 -50 -45 -40 -35 -30 -25 -20

P_in(dBm)

DS11929 Rev 3

81/165

152

Electrical characteristics

STM32WB55xx

Figure 16. Typical energy detection (T = 27°C, V = 3.3 V)

240

224

208

192

176

160

144

128

112

Input power

Table 31. RF 802.15.4 power consumption for V = 3.3 V

Symbol

Parameter

Typ

Unit

TX maximum output power consumption (SMPS Bypass)

TX maximum output power consumption (SMPS On, V_FBSMPS= 1.7 V)

TX 0 dBm output power consumption (SMPS Bypass)

TX 0 dBm output power consumption (SMPS On, V_FBSMPS= 1.4 V)

Rx consumption (SMPS Bypass)

TBD

I_txmax

I_tx0dbm

I_rxlo

Rx consumption (SMPS On)

82/165

DS11929 Rev 3

STM32WB55xx

Electrical characteristics

6.3.5

Operating conditions at power-up / power-down

The parameters given in Table 32 are derived from tests performed under the ambient

temperature condition summarized in Table 22.

Table 32. Operating conditions at power-up / power-down

Symbol

Parameter

Conditions

Min

Max

Unit

V_DDrise time rate

∞

t_VDD

V_DDfall time rate

V_DDArise time rate

V_DDAfall time rate

V_DDUSBrise time rate

V_DDUSBfall time rate

V_DDRFrise time rate

t_VDDA

t_VDDUSB

t_VDDRF

µs/V

V_DDRFfall time rate

6.3.6

Embedded reset and power control block characteristics

The parameters given in Table 33 are derived from tests performed under the ambient

temperature conditions summarized in Table 22: General operating conditions.

Table 33. Embedded reset and power control block characteristics

Symbol

Parameter

Conditions⁽¹⁾

Min

Typ

Max Unit

(2)

t_RSTTEMPO

Reset temporization after BOR0 is detected V_DDrising

250

400

μs

Rising edge

Brown-out reset threshold 0

1.62 1.66 1.70

1.60 1.64 1.69

2.06 2.10 2.14

1.96 2.00 2.04

2.26 2.31 2.35

2.16 2.20 2.24

2.56 2.61 2.66

2.47 2.52 2.57

2.85 2.90 2.95

2.76 2.81 2.86

2.10 2.15 2.19

2.00 2.05 2.10

2.26 2.31 2.36

2.15 2.20 2.25

2.41 2.46 2.51

2.31 2.36 2.41

(2)

V_BOR0

Falling edge

Rising edge

Brown-out reset threshold 1

V_BOR1

V_BOR2

V_BOR3

V_BOR4

V_PVD0

V_PVD1

V_PVD2

Falling edge

Rising edge

Brown-out reset threshold 2

Falling edge

Rising edge

Brown-out reset threshold 3

Falling edge

Rising edge

Brown-out reset threshold 4

Falling edge

Rising edge

Programmable voltage detector threshold 0

Falling edge

Rising edge

PVD threshold 1

Falling edge

Rising edge

PVD threshold 2

Falling edge

DS11929 Rev 3

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152

Electrical characteristics

STM32WB55xx

Table 33. Embedded reset and power control block characteristics (continued)

Symbol

Parameter

Conditions⁽¹⁾

Min

Typ

Max Unit

Rising edge

Falling edge

Rising edge

Falling edge

Rising edge

Falling edge

Rising edge

Falling edge

2.56 2.61 2.66

2.47 2.52 2.57

2.69 2.74 2.79

2.59 2.64 2.69

2.85 2.91 2.96

2.75 2.81 2.86

2.92 2.98 3.04

2.84 2.90 2.96

V_PVD3

PVD threshold 3

PVD threshold 4

PVD threshold 5

PVD threshold 6

V_PVD4

V_PVD5

V_PVD6

Hysteresis in

continuous mode

V_{hyst_BORH0}

Hysteresis voltage of BORH0

Hysteresis in

other mode

Hysteresis voltage of BORH (except

BORH0) and PVD

V_{hyst_BOR_PVD}

100

1.1

BOR⁽³⁾(except BOR0) and PVD

consumption from V_DD

I_DD(BOR_PVD)⁽²⁾

V_PVM1

1.6

µA

V_DDUSBperipheral voltage monitoring

1.18 1.22 1.26

1.61 1.65 1.69

Rising edge

V_PVM3

V_DDAperipheral voltage monitoring

Falling edge

1.6

1.64 1.68

V_{hyst_PVM3}

V_{hyst_PVM4}

_DD(PVM1)⁽²⁾

I_DD(PVM3)⁽²⁾

PVM3 hysteresis

0.2

µA

PVM4 hysteresis

PVM1 consumption from V_DD

PVM3 and PVM4 consumption from V_DD

1. Continuous mode means Run/Sleep modes, or temperature sensor enable in Low-power run/Low-power sleep modes.

2. Guaranteed by design.

3. BOR0 is enabled in all modes (except shutdown) and its consumption is therefore included in the supply current

characteristics tables.

84/165

DS11929 Rev 3

STM32WB55xx

Electrical characteristics

6.3.7

Embedded voltage reference

The parameters given in Table 34 are derived from tests performed under the ambient

temperature and supply voltage conditions summarized in Table 22: General operating

conditions.

Table 34. Embedded internal voltage reference

Symbol

V_REFINT

Parameter

Conditions

Min

Typ

Max

Unit

Internal reference voltage

–40 °C < T_A< +125 °C 1.182 1.212 1.232

ADC sampling time when reading

the internal reference voltage

(1)

t_{S_vrefint}

t_{start_vrefint}

I_DD(V_REFINTBUF

ꢁV_REFINT

4⁽²⁾

µs

Start time of reference voltage

buffer when ADC is enable

12⁽²⁾

20⁽²⁾

V_REFINTbuffer consumption from

V_DDwhen converted by ADC

)

12.5

µA

Internal reference voltage spread

over the temperature range

_DD= 3 V

7.5⁽²⁾

50⁽²⁾

T_Coeff

A_Coeff

Temperature coefficient

Long term stability

Voltage coefficient

–40 °C < T_A< +125 °C

1000 hours, T = 25 °C

3.0 V < V_DD< 3.6 V

ppm/°C

ppm

300 1000⁽²⁾

V_DDCoeff

250 1200⁽²⁾ppm/V

V_{REFINT_DIV1}1/4 reference voltage

V_{REFINT_DIV2}1/2 reference voltage

V_{REFINT_DIV3}3/4 reference voltage

V_REFINT

1. The shortest sampling time can be determined in the application by multiple iterations.

2. Guaranteed by design.

Figure 17. V

vs. temperature

REFINT

ꢁꢐꢆꢊꢄ

ꢁꢐꢆꢊ

ꢁꢐꢆꢆꢄ

ꢁꢐꢆꢆ

ꢁꢐꢆꢁꢄ

ꢁꢐꢆꢁ

ꢁꢐꢆꢂꢄ

ꢁꢐꢆ

ꢁꢐꢁꢈꢄ

ꢁꢐꢁꢈ

ꢁꢐꢁꢋꢄ

ꢉꢀꢂ

ꢉꢆꢂ

ꢂ

ꢆꢂ

ꢀꢂ

ꢍꢂ

ꢋꢂ

ꢁꢂꢂ

ꢁꢆꢂ

0HDQ

0LQ

0D[

06Yꢀꢂꢁꢍꢈ9ꢁ

DS11929 Rev 3

85/165

152

Electrical characteristics

STM32WB55xx

6.3.8

Supply current characteristics

The current consumption is a function of several parameters and factors such as the

operating voltage, ambient temperature, I/O pin loading, device software configuration,

operating frequencies, I/O pin switching rate, program location in memory and executed

binary code.

The current consumption is measured as described in Figure 14: Current consumption

measurement scheme.

Typical and maximum current consumption

The MCU is put under the following conditions:

•

All I/O pins are in analog input mode

All peripherals are disabled except when explicitly mentioned

The Flash memory access time is adjusted with the minimum wait states number,

depending on the f

frequency (refer to the table “Number of wait states according

HCLK

to CPU clock (HCLK) frequency” available in the RM0434 reference manual).

•

When the peripherals are enabled f

= f

PCLK

HCLK

PCLK

For Flash memory and shared peripherals f

= f

HCLK HCLKS

The parameters given in Table 35 to Table 46 are derived from tests performed under

ambient temperature and supply voltage conditions summarized in Table 22: General

operating conditions.

86/165

DS11929 Rev 3

Table 35. Current consumption in Run and Low-power run modes, code with data processing

running from Flash, ART enable (Cache ON Prefetch OFF), V = 3.3 V

Conditions

Typ

Max⁽¹⁾

Symbol

Parameter

Unit

Voltage

scaling

f_HCLK

25 °C 55 °C 85 °C 105 °C 125 °C 25 °C 55 °C 85 °C 105 °C 125 °C

16 MHz

2 MHz

1.90

2.00

2.20

1.25

8.60

4.65

2.65

5.20

3.35

2.45

2.55

1.60

9.00

5.05

3.00

5.35

3.50

2.60

1.05

TBD TBD TBD

TBD

Range 2

0.960 0.985 1.10

_HCLK= f_HSI16up to

64 MHz

8.15

4.20

2.25

5.00

3.15

2.30

8.25

4.25

2.30

5.00

3.15

2.30

8.40

4.40

2.40

5.10

3.25

2.35

16 MHz included,

f_HCLK= f_HSE= 32 MHz

Supply

Range 1 32 MHz

16 MHz

I_DD(Run)

current in f_HSI16+ PLL ON

Run mode above 32 MHz

All peripherals

64 MHz

SMPS

32 MHz

Range 1

disabled

16 MHz

2 MHz

1 MHz

0.335 0.360 0.470 0.670

Supply

0.170 0.210 0.325 0.520 0.890 TBD TBD TBD

current in f_HCLK= f_MSI

Low-power All peripherals disabled

run mode

I_DD(LPRun)

400 kHz 0.0815 0.120 0.230 0.425 0.795 TBD TBD TBD

100 kHz 0.0415 0.076 0.190 0.385 0.755 TBD TBD TBD

1. Guaranteed by characterization results, unless otherwise specified.

Table 36. Current consumption in Run and Low-power run modes, code with data processing

running from SRAM1, V = 3.3 V

Conditions

Typ

Max⁽¹⁾

Symbol

Parameter

Unit

Voltage

scaling

f_HCLK25 °C 55 °C 85 °C 105 °C 125 °C 25 °C 55 °C 85 °C 105 °C 125 °C

16 MHz 2.00

2.05

2.15

1.10

9.00

4.70

2.55

5.35

3.35

2.40

2.30

1.25

9.20

4.90

2.70

5.45

3.45

2.45

2.60

1.50

9.55

5.25

3.00

5.60

3.60

2.60

TBD TBD TBD

TBD

Range 2

2 MHz 0.970 1.00

f_HCLK= f_HSI16up to

16 MHz included,

64 MHz 8.80

8.90

4.55

2.40

5.30

3.25

2.35

Supply

f_HCLK= f_HSE= 32 MHz

Range 1 32 MHz 4.50

16 MHz 2.40

I_DD(Run)

current in

f_HSI16+ PLL ON

Run mode above 32 MHz

All peripherals

64 MHz 5.25

disabled

SMPS

Range 1

32 MHz 3.25

16 MHz 2.35

2 MHz 0.265 0.285 0.385 0.550 0.865 TBD TBD TBD

1 MHz 0.135 0.170 0.270 0.430 0.745 TBD TBD TBD

400 kHz 0.066 0.097 0.195 0.360 0.675 TBD TBD TBD

100 kHz 0.031 0.0625 0.160 0.325 0.640 TBD TBD TBD

Supply

current in f_HCLK= f_MSI

Low-power All peripherals disabled

run mode

I_DD(LPRun)

1. Guaranteed by characterization results, unless otherwise specified.

STM32WB55xx

Electrical characteristics

Table 37. Typical current consumption in Run and Low-power run modes, with different codes

running from Flash, ART enable (Cache ON Prefetch OFF), V = 3.3 V

Conditions

TYP

Symbol

Parameter

Unit

Voltage

scaling

Code

25 °C

Reduced code⁽¹⁾

Coremark

1.90

1.85

1.75

1.60

8.15

8.00

8.10

7.60

6.85

5.00

4.95

4.75

4.40

TBD

320

119

116

109

100

127

125

127

119

107

Dhrystone 2.1

µA/MHz

Fibonacci

While⁽¹⁾

Reduced code⁽¹⁾

Coremark

Dhrystone 2.1

Fibonacci

µA

µA/MHz

While⁽¹⁾

Supply current in

Run mode

I_DD(Run)

Reduced code⁽¹⁾

Coremark

Dhrystone 2.1

Fibonacci

While⁽¹⁾

Reduced code⁽¹⁾

TBD

160

175

195

113

Coremark

Dhrystone 2.1

Fibonacci

While⁽¹⁾

Reduced code⁽¹⁾

Coremark

350

Supply current in f_HCLK= f_MSI= 2 MHz

Low-power run All peripherals disable

I_DD(LPRun)

Dhrystone 2.1

350

Fibonacci

390

While⁽¹⁾

225

1. Reduced code used for characterization results provided in Table 35 and Table 36.

DS11929 Rev 3

89/165

152

Electrical characteristics

STM32WB55xx

Table 38. Typical current consumption in Run and Low-power run modes,

with different codes running from SRAM1, V = 3.3 V

Conditions

TYP

Symbol

Parameter

Unit

Voltage

scaling

Code

25 °C

Reduced code⁽¹⁾

Coremark

2.00

1.75

1.95

1.85

8.80

7.50

8.60

7.90

8.00

5.25

4.65

5.15

4.85

4.90

TBD

255

125

109

122

116

138

117

134

123

125

Dhrystone 2.1

µA/MHz

Fibonacci

While⁽¹⁾

Reduced code⁽¹⁾

Coremark

Dhrystone 2.1

Fibonacci

µA

µA/MHz

While⁽¹⁾

Supply current in

Run mode

I_DD(Run)

Reduced code⁽¹⁾

Coremark

Dhrystone 2.1

Fibonacci

While⁽¹⁾

Reduced code⁽¹⁾

TBD

128

103

125

115

110

Coremark

Dhrystone 2.1

Fibonacci

While⁽¹⁾

Reduced code⁽¹⁾

Coremark

205

Supply current in f_HCLK= f_MSI= 2 MHz

Low-power run All peripherals disable

I_DD(LPRun)

Dhrystone 2.1

Fibonacci

250

230

While⁽¹⁾

220

1. Reduced code used for characterization results provided in Table 35 and Table 36.

90/165

DS11929 Rev 3

Table 39. Current consumption in Sleep and Low-power sleep modes, Flash memory ON

Conditions TYP

MAX⁽¹⁾

Symbol

Parameter

Unit

Voltage

scaling

f_HCLK

25 °C 55 °C 85 °C 105 °C 125 °C 25 °C 55 °C 85 °C 105 °C 125 °C

f_HCLK= f_HSI16up Range 2 16 MHz 0.740 0.765 0.865 1.05

to 16 MHz

included,

1.40

3.40

2.20

1.55

2.90

2.25

1.95

805

TBD TBD TBD

TBD

64 MHz 2.65 2.70 2.80

32 MHz 1.40 1.45 1.60

3.00

1.80

Range 1

f_HCLK= f_HSEup

to 32 MHz

Supply

current in

sleep mode,

I_DD(Sleep)

16 MHz 0.845 0.875 0.990 1.20

f_HSI16+ PLL ON

above 32 MHz

64 MHz 2.60 2.60 2.65

32 MHz 1.90 1.95 2.00

16 MHz 1.70 1.70 1.75

2.75

2.10

1.80

430

400

380

370

SMPS

Range 1

All peripherals

disabled

2 MHz

1 MHz

125

235

205

185

175

Supply

775

current in f_HCLK= f_MSI

low-power All peripherals disabled

sleep mode

I_DD(LPSleep)

µA

400 kHz

72.5

755

100 kHz 31.5 63.5

745

1. Guaranteed by characterization results, unless otherwise specified.

Table 40. Current consumption in Low-power sleep modes, Flash memory in Power down

Conditions TYP

MAX⁽¹⁾

Symbol

Parameter

Unit

f_HCLK

25 °C 55 °C 85 °C 105 °C 125 °C 25 °C 55 °C 85 °C 105 °C 125 °C

2 MHz

1 MHz

94.0

56.5

40.5

27.5

115

86.0

66.5

57.5

200

170

150

140

335

305

285

275

575

550

530

520

TBD

Supply

current in

low-power All peripherals

sleep mode disabled

f_HCLK= f_MSI

_DD(LPSleep)

µA

400 kHz

100 kHz

1. Guaranteed by characterization results, unless otherwise specified.

Table 41. Current consumption in Stop 2 mode

TYP

Conditions

MAX⁽¹⁾

Symbol

Parameter

Unit

V_DD0 °C 25 °C 40 °C 55 °C 85 °C 105 °C 125 °C 0 °C 25 °C 40 °C 55 °C 85 °C 105 °C 125 °C

1.8 V 1.60 2.45 3.80 6.60 22.5

2.4 V 1.75 2.50 3.85 6.70 22.5

3.0 V 1.70 2.55 3.95 6.80 23.0

3.6 V 1.85 2.65 4.10 7.00 23.5

1.8 V 1.00 1.85 3.15 5.95 21.5

2.4 V 1.10 1.85 3.20 6.00 22.0

3.0 V 1.10 1.85 3.25 6.10 22.0

3.6 V 1.15 1.95 3.35 6.25 23.0

1.8 V 1.20 2.00 3.35 6.10 22.0

2.4 V 1.20 2.00 3.40 6.20 22.0

3.0 V 1.25 2.10 3.45 6.30 22.5

3.6 V 1.30 2.15 3.60 6.55 23.0

1.8 V 1.30 2.10 3.45 6.25 22.0

2.4 V 1.45 2.25 3.55 6.40 22.5

3.0 V 1.50 2.30 3.70 6.55 22.5

3.6 V 1.75 2.50 3.95 6.85 23.5

1.8 V 1.35 2.20 3.55 6.30 22.0

2.4 V 1.50 2.35 3.65 6.50 22.5

3.0 V 1.70 2.45 3.85 6.65 23.0

3.6 V 1.80 2.60 4.05 6.95 23.5

1.8 V 1.35 2.20 3.50 6.25 22.0

2.4 V 1.45 2.25 3.65 6.40 22.5

3.0 V 1.55 2.45 3.80 6.65 23.0

3.6 V 1.70 2.55 4.05 6.95 23.5

51.0

52.0

52.5

54.0

50.0

51.0

52.0

53.0

50.5

51.0

52.0

53.5

50.5

51.5

52.5

53.5

50.5

51.5

52.5

54.0

50.5

51.5

52.5

54.0

110 TBD TBD TBD TBD TBD TBD

115 TBD TBD TBD TBD TBD TBD

110 TBD TBD TBD TBD TBD TBD

115 TBD TBD TBD TBD TBD TBD

110 TBD TBD TBD TBD TBD TBD

115 TBD TBD TBD TBD TBD TBD

110 TBD TBD TBD TBD TBD TBD

115 TBD TBD TBD TBD TBD TBD

110 TBD TBD TBD TBD TBD TBD

115 TBD TBD TBD TBD TBD TBD

TBD

BLE enabled

LCD disabled

Supply current

in Stop 2

(Stop 2) mode, RTC

disabled

I_DD

LCD disabled

BLE disabled

LCD enabled⁽²⁾

and clocked

by LSI

BLE disabled

µA

RTC clocked

by LSI,

LCD disabled

Supply current

I_DD

in Stop 2

(Stop 2

mode, RTC

with

RTC clocked

by LSI,

enabled, BLE LCD enabled⁽²⁾

disabled

RTC)

TBD TBD TBD TBD TBD TBD

RTC clocked by

LSE quartz⁽³⁾

in low drive

mode

Table 41. Current consumption in Stop 2 mode (continued)

TYP

Conditions

MAX⁽¹⁾

Symbol

Parameter

Unit

V_DD0 °C 25 °C 40 °C 55 °C 85 °C 105 °C 125 °C 0 °C 25 °C 40 °C 55 °C 85 °C 105 °C 125 °C

Wakeup clock is

HSI16, voltage 3.0 V

TBD

Range 2. See⁽⁴⁾

Supply current Wakeup clock is

during

MSI = 32 MHz,

voltage

3.0 V

wakeup from

Stop 2 mode

bypass mode

Range 1. See⁽⁴⁾

I_DD

Wakeup clock is

MSI = 4 MHz,

voltage

(wakeup

from

TBD

µA

Stop 2)

Range 2. See⁽⁴⁾

Wakeup clock is

HSI16, voltage 3.0 V

Range 1. See⁽⁴⁾

Supply current

during

wakeup from

Stop 2 mode

SMPS mode

Wakeup clock is

MSI = 32 MHz,

voltage

3.0 V

Range 1. See⁽⁴⁾

1. Guaranteed based on test during characterization, unless otherwise specified.

2. LCD enabled with external voltage source. Consumption from VLCD excluded. Refer to LCD controller characteristics for I_VLCD

3. Based on characterization done with a 32.768 kHz crystal (MC306-G-06Q-32.768, manufacturer JFVNY) with two 6.8 pF loading capacitors.

4. Wakeup with code execution from Flash memory. Average value given for a typical wakeup time as specified in Table 49: Low-power mode wakeup timings.

Table 42. Current consumption in Stop 1 mode

TYP

Conditions

MAX⁽¹⁾

Symbol Parameter

Unit

V_DD0 °C 25 °C 40 °C 55 °C 85 °C 105 °C 125 °C 0 °C 25 °C 40 °C 55 °C 85 °C 105 °C 125 °C

1.8 V 5.55 9.85 16.0 29.0 97.0

2.4 V 5.80 9.90 16.5 29.0 97.5

3.0 V 5.90 9.90 16.5 29.0 98.0

3.6 V 6.00 10.0 16.5 29.5 99.0

1.8 V 5.05 9.20 15.5 28.0 96.0

2.4 V 5.10 9.25 15.5 28.5 96.5

3.0 V 5.15 9.30 15.5 28.5 97.0

3.6 V 5.25 9.45 16.0 29.0 97.5

1.8 V 5.05 9.30 15.5 28.5 96.0

2.4 V 5.10 9.35 16.0 28.5 96.5

3.0 V 5.20 9.65 16.0 28.5 97.0

3.6 V 5.55 9.85 16.0 29.0 98.5

1.8 V 5.30 9.35 16.0 28.5 96.5

2.4 V 5.40 9.45 16.0 28.5 97.0

3.0 V 5.70 9.55 16.5 29.0 98.5

3.6 V 5.85 10.0 16.5 29.5 96.5

1.8 V 5.25 9.60 16.0 28.5 96.5

2.4 V 5.30 9.80 16.0 29.0 97.0

3.0 V 5.85 9.75 16.5 29.0 97.5

3.6 V 5.90 10.5 16.5 29.0 98.5

1.8 V 5.35 9.55 16.0 28.5 96.5

2.4 V 5.40 9.70 16.0 29.0 96.5

3.0 V 5.75 9.70 16.0 29.0 97.5

3.6 V 5.90 10.0 16.5 29.5 99.0

215

220

210

215

210

215

220

215

220

215

220

435 TBD TBD TBD TBD TBD TBD

440 TBD TBD TBD TBD TBD TBD

445 TBD TBD TBD TBD TBD TBD

450 TBD TBD TBD TBD TBD TBD

435 TBD TBD TBD TBD TBD TBD

440 TBD TBD TBD TBD TBD TBD

445 TBD TBD TBD TBD TBD TBD

435 TBD TBD TBD TBD TBD TBD

440 TBD TBD TBD TBD TBD TBD

445 TBD TBD TBD TBD TBD TBD

440 TBD TBD TBD TBD TBD TBD

445 TBD TBD TBD TBD TBD TBD

435 TBD TBD TBD TBD TBD TBD

440 TBD TBD TBD TBD TBD TBD

445 TBD TBD TBD TBD TBD TBD

TBD

BLE enabled

LCD disabled

Supply

current in

I_DD

BLE disabled

LCD disabled

Stop 1 mode,

(Stop 1)

RTC

disabled

BLE disabled

LCD enabled⁽²⁾

clocked by LSI

µA

RTC clocked by LSI

LCD disabled

Supply

current in

I_DD

(Stop 1 Stop 1 mode, RTC clocked by LSI

with

RTC) enabled,

BLE disabled

RTC

LCD enabled⁽²⁾

TBD TBD TBD TBD TBD TBD

RTC clocked by

LSE quartz⁽³⁾in

Low drive mode

Table 42. Current consumption in Stop 1 mode (continued)

TYP

Conditions

MAX⁽¹⁾

Symbol Parameter

Unit

V_DD0 °C 25 °C 40 °C 55 °C 85 °C 105 °C 125 °C 0 °C 25 °C 40 °C 55 °C 85 °C 105 °C 125 °C

Wakeup clock

HSI16,

3.0 V

TBD

voltage Range 2.

See ⁽⁴⁾

Supply

current

during

Wakeup clock

MSI = 32 MHz,

wakeup from voltage Range 1.

Stop 1

bypass mode

See ⁽⁴⁾

I_DD

(wakeup

from

Wakeup clock

MSI = 4 MHz,

voltage Range 2.

Stop1)

See ⁽⁴⁾

Wakeup clock

HSI16,

Supply

current

during

wakeup from

Stop 1

voltage Range 2.

See ⁽⁴⁾

Wakeup clock

MSI = 32 MHz,

voltage Range 1.

SMPS mode

See ⁽⁴⁾

1. Guaranteed based on test during characterization, unless otherwise specified.

2. LCD enabled with external voltage source. Consumption from VLCD excluded. Refer to LCD controller characteristics for I_VLCD

3. Based on characterization done with a 32.768 kHz crystal (MC306-G-06Q-32.768, manufacturer JFVNY) with two 6.8 pF loading capacitors.

4. Wakeup with code execution from Flash. Average value given for a typical wakeup time as specified in Table 49: Low-power mode wakeup timings.

Table 43. Current consumption in Stop 0 mode

TYP

Conditions

MAX⁽¹⁾

Symbol

Parameter

Unit

V_DD0 °C 25 °C 40 °C 55 °C 85 °C 105 °C 125 °C 0 °C 25 °C 40 °C 55 °C 85 °C 105 °C 125 °C

1.8 V 95.5 100

2.4 V 97.5 105

3.0 V 98.5 105

3.6 V 100 105

110

115

120 195

125 195

125 200

315

320

550

555

560

TBD TBD TBD TBD TBD

TBD

Supply current

in Stop 0 mode,

RTC disabled,

BLE disabled,

LCD disabled

µA

Wakeup clock

HSI16,

3.0 V

TBD

I_DD

(Stop 0)

voltage Range 2.

(2)

See

Supply current Wakeup clock is

during wakeup MSI = 32 MHz,

from Stop 0

Bypass mode

voltage Range 1.

See ⁽²⁾

Wakeup clock is

MSI = 4 MHz,

voltage Range 2.

See ⁽²⁾

1. Guaranteed by characterization results, unless otherwise specified.

2. Wakeup with code execution from Flash memory. Average value given for a typical wakeup time as specified in Table 49: Low-power mode wakeup timings.

Table 44. Current consumption in Standby mode

TYP

Conditions

MAX⁽¹⁾

Symbol

Parameter

Unit

V_DD0 °C 25 °C 40 °C 55 °C 85 °C 105 °C 125 °C 0 °C 25 °C 40 °C 55 °C 85 °C 105 °C 125 °C

1.8 V 0.850 0.925 1.150 1.55 4.00

2.4 V 0.910 0.985 1.200 1.65 4.10

9.00

9.60

19.50 TBD TBD TBD TBD TBD

TBD

BLE enabled

No independent

watchdog

21.0

23.0

25.0

18.5

20.0

22.0

24.0

18.5

20.0

22.0

24.0

18.5

20.0

22.0

24.5

19.0

20.5

22.5

24.5

TBD

TBD TBD TBD TBD TBD

3.0 V 0.940 1.050 1.250 1.75 4.60 10.50

3.6 V 1.050 1.150 1.400 1.90 5.10

1.8 V 0.270 0.320 0.515 0.920 3.45

2.4 V 0.270 0.350 0.540 0.955 3.50

3.0 V 0.270 0.370 0.575 1.00 3.85

11.50

8.20

8.80

9.50

Supplycurrent

in Standby

mode (backup BLE disabled

registers and No independent

(Standby)

SRAM2a

retained),

RTC disabled

watchdog

3.6 V 0.300 0.410 0.645 1.15 4.20 10.50

1.8 V 0.265 0.525 0.710 1.10 3.90

2.4 V 0.280 0.595 0.790 1.20 4.00

3.0 V 0.290 0.670 0.855 1.35 4.15

3.6 V 0.295 0.770 0.990 1.50 4.60

1.8 V 0.500 0.600 0.780 1.20 3.70

2.4 V 0.630 0.705 0.910 1.30 3.80

3.0 V 0.725 0.825 1.050 1.50 3.95

3.6 V 0.860 0.970 1.200 1.70 4.25

1.8 V 0.565 0.655 0.830 1.25 3.75

2.4 V 0.635 0.790 0.975 1.40 4.10

8.40

9.05

9.80

11.00

8.45

9.10

9.90

11.00

8.55

9.20

BLE disabled

With

independent

watchdog

µA

RTC clocked by

LSI, no

independent

watchdog

Supplycurrent

in Standby

mode (backup RTC clocked by

registers and LSI, with

(Standby

with RTC)

SRAM2a

retained),

RTC enabled

BLE disabled

independent

watchdog

3.0 V 0.725 0.915 1.100 1.55 4.50 10.00

3.6 V 0.870 1.050 1.300 1.80 4.90

1.8 V 0.525 0.625 0.840 1.25 3.75

2.4 V 0.665 0.755 0.960 1.35 4.05

11.00

8.60

9.25

RTC clocked by

(2)

LSE quartz in

3.0 V 0.775 0.880 1.100 1.55 4.40 10.00

3.6 V 0.935 1.050 1.300 1.80 5.00 11.00

low drive mode

Table 44. Current consumption in Standby mode (continued)

TYP

Conditions

MAX⁽¹⁾

Symbol

Parameter

Unit

V_DD0 °C 25 °C 40 °C 55 °C 85 °C 105 °C 125 °C 0 °C 25 °C 40 °C 55 °C 85 °C 105 °C 125 °C

1.8 V 0.160 0.210 0.380 0.660 2.30

2.4 V 0.165 0.245 0.375 0.650 2.15

3.0 V 0.155 0.250 0.385 0.630 2.25

3.6 V 0.155 0.235 0.375 0.670 2.20

5.15

5.20

10.9

11.0

TBD TBD TBD TBD TBD TBD

TBD

Supply

current to be

subtracted in

I_DD

(SRAM2a) Standby

µA

(3)

mode when

SRAM2a is

not retained

Wakeup clock is

(4)

HSI16. See

SMPS ON

3.0 V

TBD

Supplycurrent

(wakeup during

from

Standby) Standbymode

wakeup from

Wakeup clock is

(4)

HSI16. See

SMPS OFF

1. Guaranteed by characterization results, unless otherwise specified.

2. Based on characterization done with a 32.768 kHz crystal (MC306-G-06Q-32.768, manufacturer JFVNY) with two 6.8 pF loading capacitors.

3. The supply current in Standby with SRAM2a mode is: I_DD(Standby) + I_DD(SRAM2a). The supply current in Standby with RTC with SRAM2a mode is:

I_DD(Standby + RTC) + I_DD(SRAM2a).

4. Wakeup with code execution from Flash memory. Average value given for a typical wakeup time as specified in Table 49: Low-power mode wakeup timings.

Table 45. Current consumption in Shutdown mode

TYP

Conditions

MAX⁽¹⁾

Symbol

Parameter

Unit

V_DD0 °C 25 °C 40 °C 55 °C 85 °C 105 °C 125 °C 0 °C 25 °C 40 °C 55 °C 85 °C 105 °C 125 °C

1.8 V 0.039 0.013 0.030 0.100 0.635 1.950

5.45

TBD TBD TBD TBD TBD

TBD

0.059

TBD

Supply current

in Shutdown

mode (backup

2.4 V 0.059 0.014 0.055 0.120 0.785 2.350

3.0 V 0.064 0.037 0.070 0.180 1.000 2.900

3.6 V 0.071 0.093 0.140 0.280 1.300 3.700

1.8 V 0.320 0.315 0.355 0.420 0.985 2.300

2.4 V 0.425 0.405 0.460 0.540 1.200 2.800

3.0 V 0.535 0.535 0.595 0.700 1.500 3.450

3.6 V 0.695 0.720 0.790 0.940 2.000 4.350

6.50

(Shutdown) registers

retained) RTC

8.00

disabled

9.75

µA

Supply current

in Shutdown

mode (backup

registers

retained) RTC

enabled

RTC clocked

by LSE

(2)

(Shutdown

with RTC)

quartz

low drive

mode

Supply current

during wakeup

from Shutdown

Wakeup clock

MSI = 4 MHz. 3.0 V

(wakeup

from

TBD

(3)

See

Shutdown) mode

1. Guaranteed by characterization results, unless otherwise specified.

2. Based on characterization done with a 32.768 kHz crystal (MC306-G-06Q-32.768, manufacturer JFVNY) with two 6.8 pF loading capacitors.

3. Wakeup with code execution from Flash memory. Average value given for a typical wakeup time as specified in Table 49: Low-power mode wakeup timings.

Table 46. Current consumption in VBAT mode

TYP

Conditions

MAX⁽¹⁾

Symbol Parameter

Unit

V_BAT0 °C 25 °C 40 °C 55 °C 85 °C 105 °C 125 °C 0 °C 25 °C 40 °C 55 °C 85 °C 105 °C 125 °C

1.8 V 1.00 2.00 4.00 10.0 52.0

2.4 V 1.00 2.00 5.00 12.0 60.0

3.0 V 2.00 4.00 7.00 16.0 75.0

3.6 V 7.00 15.0 23.0 42.0 170

1.8 V 295 305 315 325 380

2.4 V 385 395 400 415 475

3.0 V 495 505 515 530 600

3.6 V 630 645 660 685 830

145

165

225

450

480

595

765

1150

370

425

RTC disabled

725

Backup

domain

supply

current

1150

720

I_DD(VBAT)

RTC enabled

and clocked

by LSE

870

1300

1850

quartz⁽²⁾

1. Guaranteed by characterization results, unless otherwise specified.

2. Based on characterization done with a 32.768 kHz crystal (MC306-G-06Q-32.768, manufacturer JFVNY) with two 6.8 pF loading capacitors.

Table 47. Current under Reset condition

TYP

MAX⁽¹⁾

Symbol Conditions

Unit

0 °C

25 °C 40 °C 55 °C 85 °C 105 °C 125 °C 0 °C

25 °C 40 °C 55 °C 85 °C 105 °C 125 °C

1.8 V

TBD

2.4 V

I_DD(RST)

3.0 V

3.6 V

1. Guaranteed by characterization results, unless otherwise specified.

STM32WB55xx

Electrical characteristics

I/O system current consumption

The current consumption of the I/O system has two components: static and dynamic.

I/O static current consumption

All the I/Os used as inputs with pull-up generate current consumption when the pin is

externally held low. The value of this current consumption can be simply computed by using

the pull-up/pull-down resistors values given in Table 68: I/O static characteristics.

For the output pins, any external pull-down or external load must also be considered to

estimate the current consumption.

Additional I/O current consumption is due to I/Os configured as inputs if an intermediate

voltage level is externally applied. This current consumption is caused by the input Schmitt

trigger circuits used to discriminate the input value. Unless this specific configuration is

required by the application, this supply current consumption can be avoided by configuring

these I/Os in analog mode. This is notably the case of ADC input pins which should be

configured as analog inputs.

Caution:

Any floating input pin can also settle to an intermediate voltage level or switch inadvertently,

as a result of external electromagnetic noise. To avoid current consumption related to

floating pins, they must either be configured in analog mode, or forced internally to a definite

digital value. This can be done either by using pull-up/down resistors or by configuring the

pins in output mode.

I/O dynamic current consumption

In addition to the internal peripheral current consumption measured previously (see

Table 48: Peripheral current consumption, the I/Os used by an application also contribute to

the current consumption. When an I/O pin switches, it uses the current from the I/O supply

voltage to supply the I/O pin circuitry and to charge/discharge the capacitive load (internal or

external) connected to the pin:

I_SW= V_DD× f_SW× C

where

is the current sunk by a switching I/O to charge/discharge the capacitive load

is the I/O supply voltage

is the I/O switching frequency

C is the total capacitance seen by the I/O pin: C = C + C

+ C

INT

EXT

C is the PCB board capacitance including the pad pin.

The test pin is configured in push-pull output mode and is toggled by software at a fixed

frequency.

DS11929 Rev 3

101/165

152

Electrical characteristics

STM32WB55xx

On-chip peripheral current consumption

The current consumption of the on-chip peripherals is given in Table 48. The MCU is placed

under the following conditions:

•

All I/O pins are in Analog mode

The given value is calculated by measuring the difference of the current consumptions:

–

when the peripheral is clocked on

when the peripheral is clocked off

•

Ambient operating temperature and supply voltage conditions summarized in Table 18:

Voltage characteristics

The power consumption of the digital part of the on-chip peripherals is given in

Table 48. The power consumption of the analog part of the peripherals (where

applicable) is indicated in each related section of the datasheet.

Table 48. Peripheral current consumption

Low-power

Peripheral

Bus Matrix⁽¹⁾

Range 1

Range 2

Unit

run and sleep

2.40

1.25

0.465

1.90

2.00

4.15

12.0

4.05

TBD

7.60

2.00

1.05

0.375

1.55

1.65

3.40

10.0

3.35

TBD

6.25

1.80

1.05

0.380

1.80

4.45

11.5

3.90

TBD

7.10

TSC

CRC

AHB1

DMA1

µA/MHz

DMA2

DMAMUX

All AHB1 Peripherals

AES1

ADC independent clock domain

ADC clock domain

GPIOA⁽²⁾

GPIOB⁽²⁾

)

AHB2

µA/MHz

GPIOC⁽²⁾

GPIOD⁽²⁾

GPIOE⁽²⁾

GPIOH⁽²⁾

All AHB2 Peripherals

QSPI

AHB3

µA/MHz

102/165

DS11929 Rev 3

STM32WB55xx

Electrical characteristics

Table 48. Peripheral current consumption (continued)

Low-power

run and sleep

Peripheral

Range 1

Range 2

Unit

RNG independent clock domain

RNG clock domain

TBD

6.95

4.40

TBD

1.10

TBD

1.35

1.65

TBD

5.65

TBD

0.335

TBD

N/A

SRAM2a and SRAM2b

TBD

5.75

3.65

TBD

0.88

TBD

N/A

TBD

0.125

7.00

4.25

TBD

1.25

TBD

N/A

AHB Shared FLASH

µA/MHz

AES2

PKA

All AHB Shared Peripherals

AHB to APB1 bridge⁽³⁾

RTCA

CRS

USB FS independent clock domain

USB FS clock domain

I2C1 independent clock domain

I2C1 clock domain

I2C3 independent clock domain

I2C3 clock domain

LCD

N/A

TBD

1.10

1.40

TBD

4.70

TBD

0.285

TBD

2.10

2.25

TBD

4.90

TBD

0.965

TBD

APB1

µA/MHz

SPI2

LPTIM1 independent clock domain

LPTIM1 clock domain

TIM2

LPUART1 independent clock domain

LPUART1 clock domain

LPTIM2 clock domain

LPTIM2 independent clock domain

WWDG

All APB1 Peripherals

DS11929 Rev 3

103/165

152

Electrical characteristics

STM32WB55xx

Table 48. Peripheral current consumption (continued)

Low-power

run and sleep

Peripheral

Range 1

Range 2

Unit

AHB to APB2⁽⁴⁾

1.10

8.20

TBD

2.75

TBD

0.885

6.80

TBD

2.30

TBD

1.35

7.25

TBD

2.55

TBD

TIM1

TIM17

TIM16

USART1 independent clock domain

USART1 clock domain

SPI1

APB2

µA/MHz

SAI1 independent clock domain

SAI1 clock domain

All APB2 on

ALL

µA/MHz

1. The BusMatrix is automatically active when at least one master is ON (CPU, DMA).

2. The GPIOx (x= A…H) dynamic current consumption is approximately divided by a factor two vs. the values of this table

when the GPIO port is locked through the LCKK and LCKy bits in the GPIOx_LCKR register. To save the full GPIOx current

consumption, the GPIOx clock needs to be disabled in the RCC when all port I/Os are used in alternate function or analog

mode (clock is only required to read or write into GPIO registers, and is not used in AF or analog modes).

3. The AHB to APB1 bridge is automatically active when at least one peripheral is ON on the APB1.

4. The AHB to APB2 bridge is automatically active when at least one peripheral is ON on the APB2.

6.3.9

Wakeup time from Low-power modes and voltage scaling

transition times

The wakeup times given in Table 49 are the latency between the event and the execution of

the first user instruction.

The device goes in Low-power mode after the WFE (Wait For Event) instruction.

(1)

Table 49. Low-power mode wakeup timings

Symbol

Parameter

Conditions

Typ Max

Unit

Wakeup time from

t_WUSLEEPSleep mode

to Run mode

No. of

CPU

cycles

Wakeup time from

Wakeup in Flash with memory in power-down

t_WULPSLEEPLow-power sleep mode during low-power sleep mode (FPDS = 1 in

to Low-power run mode PWR_CR1) and with clock MSI = 2 MHz

104/165

DS11929 Rev 3

STM32WB55xx

Symbol

Electrical characteristics

(1)

Table 49. Low-power mode wakeup timings (continued)

Parameter

Conditions

Typ Max

2.38 2.6

1.69 1.76

Unit

Wakeup clock MSI = 32 MHz

Wakeup clock HSI16 = 16 MHz

Wakeup clock MSI = 4 MHz

Wakeup clock MSI = 32 MHz

Wakeup clock HSI16 = 16 MHz

Wakeup clock MSI = 4 MHz

Wakeup clock MSI = 32 MHz

Wakeup clock HSI16 = 16 MHz

Wakeup clock MSI = 4 MHz

Wakeup clock MSI = 32 MHz

Wakeup clock HSI16 = 16 MHz

Wakeup clock MSI = 32 MHz

Wakeup clock HSI16 = 16 MHz

Wakeup clock MSI = 4 MHz

Wakeup clock MSI = 32 MHz

Wakeup clock HSI16 = 16 MHz

Range 1

Range 2

Range 1

Range 2

Range 1

Range 2

Wake up time from

Stop 0 mode

to Run mode in Flash

memory

1.7

1.78

7.9

7.43

t_WUSTOP0

µs

TBD TBD

4.67 4.94

5.09 5.34

5.08 5.36

8.36 8.76

TBD TBD

Wake up time from

Stop 0 mode

to Run mode in SRAM1

Wake up time from

Stop 1 mode

to Run in Flash memory

SMPS bypassed

Wake up time from

Stop 1 mode

to Run in Flash memory

SMPS ON

Range 1

Range 2

Range 1

Wake up time from

Stop 1 mode

to Run in SRAM1

SMPS bypassed

t_WUSTOP1

µs

Range 2

Wake up time from

Stop 1 mode to Run

in SRAM1

Range 1

Range 2

SMPS ON

Wake up time from

Stop 1 mode to

Low-power run mode

in Flash memory

7.76 8.38

TBD TBD

Regulator in

Low-power

mode (LPR=1 in

PWR_CR1)

Wakeup clock MSI = 4 MHz

Wake up time from

Stop 1 mode to

Low-power run mode

in SRAM1

DS11929 Rev 3

105/165

152

Electrical characteristics

STM32WB55xx

(1)

Table 49. Low-power mode wakeup timings (continued)

Symbol

Parameter

Conditions

Typ Max

Unit

Wakeup clock MSI = 32 MHz

Wakeup clock HSI16 = 16 MHz

Wakeup clock MSI = 4 MHz

Wakeup clock MSI = 48 MHz

Wakeup clock HSI16 = 16 MHz

5.12 5.42

5.55 5.88

5.56 5.88

Wake up time from

Stop 2 mode

to Run mode in Flash

memory

Range 1

Range 2

SMPS bypassed

9.0

9.4

Wake up time from

Stop 2 mode

to Run mode in Flash

memory

TBD TBD

Range 1

Range 2

Range 1

Wakeup clock HSI16 = 16 MHz

TBD TBD

SMPS ON

t_WUSTOP2

µs

Wakeup clock MSI = 32 MHz

Wakeup clock HSI16 = 16 MHz

Wakeup clock MSI = 4 MHz

Wakeup clock MSI = 48 MHz

Wakeup clock HSI16 = 16 MHz

TBD TBD

Wake up time from

Stop 2 mode to Run

mode in SRAM1

SMPS bypassed

Range 2

Wake up time from

Stop 2 mode to Run

mode in SRAM1

SMPS ON

Range 1

Range 2

Wakeup time from

Standby mode

to Run mode

TBD TBD

SMPS Bypassed

t_WUSTBY

Range 1

Wakeup clock HSI16 = 16 MHz

µs

Wakeup time from

Standby mode to Run

mode

TBD TBD

49.75 52.32

SMPS ON

Wakeup time from

t_WUSHDNShutdown mode

to Run mode

Wakeup clock MSI = 4 MHz

1. Guaranteed by characterization results (V_DD= 3 V, .T = 25 °C.

(1)

Table 50. Regulator modes transition times

Symbol

Parameter

Conditions

Typ

Max

Unit

Wakeup time from Low-power run mode to

Run mode⁽²⁾

t_WULPRUN

Code run with MSI 2 MHz

15.33

20.67

15.66

µs

Regulator transition time from Range 2 to

Range 1 or Range 1 to Range 2⁽³⁾

t_VOST

Code run with HSI16

25.64

1. Guaranteed by characterization results.

2. Time until REGLPF flag is cleared in PWR_SR2.

3. Time until VOSF flag is cleared in PWR_SR2.

106/165

DS11929 Rev 3

STM32WB55xx

Symbol

Electrical characteristics

(1)

Table 51. Wakeup time using LPUART

Parameter Conditions

Typ

Max

1.7

Unit

Stop mode 0

Wakeup time needed to calculate the maximum

t_WULPUARTLPUART baud rate allowing to wakeup up from Stop

mode when LPUART clock source is HSI16

µs

Stop mode 1/2

8.5

1. Guaranteed by design.

6.3.10

External clock source characteristics

High-speed external user clock generated from an external source

The high-speed external (HSE) clock must be supplied with a 32 MHz crystal oscillator.

The STM32WB55xx include internal programmable capacitances that can be used to tune

the crystal frequency in order to compensate the PCB parasitic one.

The characteristics in Table 52 and Table 53 are measured over recommended operating

conditions, unless otherwise specified. Typical values are referred to T = 25 °C and

= 3.0 V.

(1)

Table 52. HSE crystal requirements

Conditions

Symbol

Parameter

Min

Typ

Max Unit

f_NOM

Oscillator frequency

Frequency tolerance

MHz

ppm

Includes initial accuracy, stability over

temperature, aging and frequency pulling

due to incorrect load capacitance.

f_TOL

C_L

ESR

P_D

Load capacitance

Equivalent series resistance

Drive level

ꢀ

100

µW

1. 32 MHz XTAL is specified for two specific references: NX2016SA and NX1612SA.

Table 53. HSE oscillator characteristics

Symbol

Parameter

Conditions

Min

Typ

Max Unit

Startup time

for 80% amplitude stabilization

V_DDRFstabilized, XOTUNE=000000,

-40 to +125 °C range

t_SUA(HSE)

1000

µs

Startup time

for XOREADY signal

V_DDRFstabilized, XOTUNE=000000,

-40 to +125 °C range

t_SUR(HSE)

250

I_DDRF(HSE)HSE current consumption

XOT_g(HSE)XOTUNE granularity

HSEGMC=000, XOTUNE=000000

µA

ppm

XOT_fp(HSE)XOTUNE frequency pulling

XOT_nb(HSE)XOTUNE number of tuning bits

XOT_st(HSE)XOTUNE setting time

±20

±40

Capacitor bank

bit

0.1

DS11929 Rev 3

107/165

152

Electrical characteristics

STM32WB55xx

Note:

For information about the trimming of the oscillator, refer to application note AN5042 “HSE

trimming for RF applications using the STM32WB Series”.

Low-speed external user clock generated from an external source

The low-speed external (LSE) clock can be supplied with a 32.768 kHz crystal resonator

oscillator. The information provided in this section is based on design simulation results

obtained with typical external components specified in Table 54. In the application, the

resonator and the load capacitors have to be placed as close as possible to the oscillator

pins to minimize output distortion and startup stabilization time.

Refer to the crystal resonator manufacturer for more details on the resonator characteristics

(frequency, package, accuracy).

(1)

Table 54. Low-speed external user clock characteristics

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

LSEDRV[1:0] = 00

Low drive capability

250

LSEDRV[1:0] = 01

Medium low drive capability

315

I_DD(LSE)

LSE current consumption

LSEDRV[1:0] = 10

Medium high drive capability

500

LSEDRV[1:0] = 11

High drive capability

630

LSEDRV[1:0] = 00

Low drive capability

0.50

0.75

1.70

LSEDRV[1:0] = 01

Medium low drive capability

G_mcritmaxMaximum critical crystal g_m

µA/V

LSEDRV[1:0] = 10

Medium high drive capability

LSEDRV[1:0] = 11

High drive capability

2.70

(2)

t_SU(LSE)

Startup time

V_DDstabilized

1. Guaranteed by design.

2. t_SU(LSE)is the startup time measured from the moment it is enabled (by software) until a stable 32 MHz oscillation is

reached. This value is measured for a standard crystal and it can vary significantly with the crystal manufacturer.

Note:

For information on selecting the crystal, refer to the application note AN2867 “Oscillator

design guide for STM8S, STM8A and STM32 microcontrollers” available from www.st.com.

108/165

DS11929 Rev 3

STM32WB55xx

Electrical characteristics

Figure 18. Typical application with a 32.768 kHz crystal

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An external resistor is not required between OSC32_IN and OSC32_OUT, and it is

forbidden to add one.

6.3.11

Internal clock source characteristics

The parameters given in Table 55 are derived from tests performed under ambient

temperature and supply voltage conditions summarized in Table 22: General operating

conditions. The provided curves are characterization results, not tested in production.

High-speed internal (HSI16) RC oscillator

(1)

Table 55. HSI16 oscillator characteristics

Symbol

Parameter

HSI16 Frequency

Conditions

Min

Typ

Max

Unit

f_HSI16

V_DD=3.0 V, T_A=30 °C

15.88

16.08

MHz

Trimming code is not a

multiple of 64

0.2

-4

0.3

-6

0.4

-8

TRIM

HSI16 user trimming step

Trimming code is a

multiple of 64

DuCy(HSI16)⁽²⁾Duty Cycle

-1

-2

T_A= 0 to 85 °C

T_A= -40 to 125 °C

HSI16 oscillator frequency drift over

temperature

ꢁ

_Temp(HSI16)

1.5

HSI16 oscillator frequency drift over

V_DD

ꢁ_VDD(HSI16)

V_DD=1.62 V to 3.6 V

-0.1

0.05

t_su(HSI16)⁽²⁾

HSI16 oscillator start-up time

0.8

1.2

μs

t_stab(HSI16)⁽²⁾HSI16 oscillator stabilization time

_DD(HSI16)⁽²⁾HSI16 oscillator power consumption

155

190

μA

1. Guaranteed by characterization results.

2. Guaranteed by design.

DS11929 Rev 3

109/165

152

Electrical characteristics

STM32WB55xx

Figure 19. HSI16 frequency vs. temperature

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110/165

DS11929 Rev 3

STM32WB55xx

Electrical characteristics

Multi-speed internal (MSI) RC oscillator

(1)

Table 56. MSI oscillator characteristics

Parameter Conditions

Symbol

Min

Typ

Max Unit

Range 0

Range 1

Range 2

Range 3

Range 4

Range 5

Range 6

Range 7

Range 8

Range 9

Range 10

Range 11

Range 0

Range 1

Range 2

Range 3

Range 4

Range 5

Range 6

Range 7

Range 8

Range 9

Range 10

Range 11

T_A= -0 to 85 °C

98.7

100

200

101.3

197.4

202.6

kHz

405.2

394.8

400

789.6

800

810.4

1.013

2.026

4.052

0.987

1.974

MSI mode

3.948

7.896

8.104

MHz

16.21

15.79

23.69

24.31

32.42

48.62

31.58

MSI frequency

after factory

calibration, done

at V_DD=3 V and

T_A=30 °C

47.38

f_MSI

98.304

196.608

393.216

786.432

1.016

1.999

3.998

7.995

15.991

23.986

32.014

48.005

kHz

PLL mode

XTAL=

32.768 kHz

MHz

MSI oscillator

-3.5

ꢁ_TEMP(MSI)⁽²⁾frequency drift

MSI mode

T_A= -40 to 125 °C

-8

over temperature

DS11929 Rev 3

111/165

152

Electrical characteristics

STM32WB55xx

(1)

Table 56. MSI oscillator characteristics (continued)

Symbol

Parameter

Conditions

Min

Typ

Max Unit

V_DD

1.62 to 3.6 V

-1.2

Range 0 to 3

0.5

V_DD

2.4 to 3.6 V

-0.5

-2.5

-0.8

-5

V_DD

1.62 to 3.6 V

MSI oscillator

frequency drift

over V_DD

ꢁ_VDD(MSI)⁽²⁾

MSI mode Range 4 to 7

0.7

V_DD

2.4 to 3.6 V

(reference is 3 V)

V_DD

1.62 to 3.6 V

Range 8 to 11

V_DD

2.4 to 3.6 V

-1.6

Frequency

T_A= -40 to 85 °C

T_A= -40 to 125 °C

ꢁF_SAMPLING

variation in

MSI mode

(MSI)⁽²⁾⁽⁶⁾

sampling mode⁽³⁾

For next

transition

3.458

P_USB

Period jitter for

USB clock⁽⁴⁾

PLL mode

Range 11

Jitter(MSI)⁽⁶⁾

For paired

transition

3.916

For next

transition

MT_USB

Medium term jitter PLL mode

Jitter(MSI)⁽⁶⁾

for USB clock⁽⁵⁾

Range 11

For paired

transition

RMS cycle-to-

cycle jitter

CC jitter(MSI)⁽⁶⁾

PLL mode Range 11

P jitter(MSI)⁽⁶⁾RMS period jitter PLL mode Range 11

Range 0

Range 1

Range 2

MSI oscillator

start-up time

_SU(MSI)⁽⁶⁾

μs

Range 3

Range 4 to 7

Range 8 to 11

2.5

10 % of final

frequency

0.25

0.5

MSI oscillator

stabilization time Range 11

PLL mode 5 % of final

t_STAB(MSI)⁽⁶⁾

1.25 ms

2.5

frequency

1 % of final

frequency

112/165

DS11929 Rev 3

STM32WB55xx

Symbol

Electrical characteristics

(1)

Table 56. MSI oscillator characteristics (continued)

Parameter

Conditions

Range 0

Min

Typ

Max Unit

0.6

0.8

1.2

1.9

4.7

6.5

Range 1

Range 2

Range 3

Range 4

Range 5

Range 6

Range 7

Range 8

Range 9

Range 10

Range 11

1.2

1.7

2.5

MSI oscillator

power

consumption

MSI and

PLL mode

I_DD(MSI)⁽⁶⁾

µA

18.5

110

130

190

110

155

1. Guaranteed by characterization results.

2. This is a deviation for an individual part once the initial frequency has been measured.

3. Sampling mode means Low-power run/Low-power sleep modes with Temperature sensor disable.

4. Average period of MSI at 48 MHz is compared to a real 48 MHz clock over 28 cycles. It includes frequency tolerance + jitter

of MSI at 48 MHz clock.

5. Only accumulated jitter of MSI at 48 MHz is extracted over 28 cycles.

For next transition: min. and max. jitter of 2 consecutive frame of 28 cycles of the MSI at 48 MHz, for 1000 captures over

28 cycles.

For paired transitions: min. and max. jitter of 2 consecutive frame of 56 cycles of the MSI at 48 MHz, for 1000 captures over

56 cycles.

6. Guaranteed by design.

DS11929 Rev 3

113/165

152

Electrical characteristics

STM32WB55xx

Figure 20. Typical current consumption vs. MSI frequency

High-speed internal 48 MHz (HSI48) RC oscillator

(1)

Table 57. HSI48 oscillator characteristics

Symbol

Parameter

HSI48 frequency

Conditions

Min

Typ

Max

Unit

f_HSI48

TRIM

V_DD= 3.0 V, T_A= 30 °C

MHz

HSI48 user trimming step

0.11⁽²⁾

0.18⁽²⁾

USER TRIM

COVERAGE

HSI48 user trimming coverage

±32 steps

±3⁽³⁾

45⁽²⁾

±3.5⁽³⁾

DuCy(HSI48) Duty cycle

55⁽²⁾

±3⁽³⁾

V_DD= 3.0 V to 3.6 V,

T_A= –15 to 85 °C

Accuracy of the HSI48 oscillator

ACC_{HSI48_REL}over temperature

(factory calibrated)

V_DD= 1.65 V to 3.6 V,

T_A= –40 to 125 °C

±4.5⁽³⁾

V_DD= 3 V to 3.6 V

0.025⁽³⁾0.05⁽³⁾

HSI48 oscillator frequency drift

with V_DD

D_VDD(HSI48)

t_su(HSI48)

V_DD= 1.65 V to 3.6 V

0.05⁽³⁾

2.5⁽²⁾

0.1⁽³⁾

6⁽²⁾

HSI48 oscillator start-up time

μs

_DD(HSI48) HSI48 oscillator power consumption

340⁽²⁾

380⁽²⁾

μA

114/165

DS11929 Rev 3

STM32WB55xx

Symbol

Electrical characteristics

(1)

Table 57. HSI48 oscillator characteristics (continued)

Parameter

Conditions

Min

Typ

Max

Unit

Next transition jitter

N_Tjitter

P_Tjitter

±0.15⁽²⁾

Accumulated jitter on 28 cycles⁽⁴⁾

Paired transition jitter

±0.25⁽²⁾

Accumulated jitter on 56 cycles⁽⁴⁾

1. V_DD= 3 V, T_A= –40 to 125 °C unless otherwise specified.

2. Guaranteed by design.

3. Guaranteed by characterization results.

4. Jitter measurement are performed without clock source activated in parallel.

Figure 21. HSI48 frequency vs. temperature

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Low-speed internal (LSI) RC oscillator

(1)

Table 58. LSI1 oscillator characteristics

Symbol

Parameter

Conditions

Min Typ Max Unit

_DD= 3.0 V, T_A= 30 °C

31.04

32.96

f_LSI

LSI1 frequency

kHz

V_DD= 1.62 to 3.6 V, T_A= -40 to 125 °C 29.5

_SU(LSI1)⁽²⁾LSI1 oscillator start-up time

130

μs

t_STAB(LSI1)⁽²⁾LSI1 oscillator stabilization time 5% of final frequency

125 180

110 180

LSI1 oscillator power

consumption

I_DD(LSI1)⁽²⁾

1. Guaranteed by characterization results.

2. Guaranteed by design.

DS11929 Rev 3

115/165

152

Electrical characteristics

STM32WB55xx

(1)

Table 59. LSI2 oscillator characteristics

Conditions

Symbol

Parameter

LSI2 frequency

Min Typ Max Unit

V_DD= 3.0 V, T_A= 30 °C

21.6

44.2

44.4

3.5

f_LSI2

kHz

V_DD= 1.62 to 3.6 V, T_A= -40 to 125 °C 21.2

t_SU(LSI2)⁽²⁾LSI2 oscillator start-up time

0.7

LSI2 oscillator power

I_DD(LSI2)⁽²⁾

500 1180 nA

1.5 0.4 °C

consumption

Allowed temperature change

∆T_max(LSI2)

during sleep duration⁽³⁾

1. Guaranteed by characterization results.

2. Guaranteed by design.

3. Includes accuracy of 32 Mhz crystal.

6.3.12

PLL characteristics

The parameters given in Table 60 are derived from tests performed under temperature and

supply voltage conditions summarized in Table 22: General operating conditions.

(1)

Table 60. PLL, PLLSAI1 characteristics

Symbol

f_{PLL_IN}

Parameter

Conditions

Min

Typ Max Unit

PLL input clock⁽²⁾

344

128

MHz

PLL input clock duty cycle

Voltage scaling Range 1

Voltage scaling Range 2

Voltage scaling Range 1

Voltage scaling Range 2

Voltage scaling Range 1

Voltage scaling Range 2

Voltage scaling Range 1

Voltage scaling Range 2

f_{PLL_P_OUT}PLL multiplier output clock P

f_{PLL_Q_OUT}PLL multiplier output clock Q

f_{PLL_R_OUT}PLL multiplier output clock R

f_{VCO_OUT}PLL VCO output

MHz

t_LOCK

Jitter

PLL lock time

μs

RMS cycle-to-cycle jitter

RMS period jitter

System clock 64 MHz

VCO freq = 96 MHz

VCO freq = 192 MHz

VCO freq = 344 MHz

200 260

300 380

520 650

PLL power consumption

on V_DD

_DD(PLL)

μA

(1)

1. Guaranteed by design.

2. Take care of using the appropriate division factor M to obtain the specified PLL input clock values. The M factor is shared

between the two PLLs.

116/165

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Electrical characteristics

6.3.13

Flash memory characteristics

(1)

Table 61. Flash memory characteristics

Symbol

Parameter

Conditions

Typ

Max Unit

t_prog

64-bit programming time

Normal programming

Fast programming

Normal programming

Fast programming

81.7

5.2

90.8

5.5

4.0

43.0

31.0

24.5

25.0

µs

One row (64 double word)

programming time

t_{prog_row}

3.8

41.8

One page (4 KByte)

programming time

t_{prog_page}

30.4

t_ERASE

t_ME

Page (4 KByte) erase time

Mass erase time

22.0

22.1

Write mode

3.4

Average consumption from V_DD

Maximum current (peak)

Erase mode

Write mode

3.4

I_DD

7 (for 6 µs)

7 (for 67 µs)

Erase mode

1. Guaranteed by design.

Table 62. Flash memory endurance and data retention

Symbol

Parameter

Endurance

Conditions

Min⁽¹⁾

Unit

N_END

T_A= –40 to +105 °C

kcycles

1 kcycle⁽²⁾at T_A= 85 °C

1 kcycle⁽²⁾at T_A= 105 °C

1 kcycle⁽²⁾at T_A= 125 °C

10 kcycles⁽²⁾at T_A= 55 °C

10 kcycles⁽²⁾at T_A= 85 °C

10 kcycles⁽²⁾at T_A= 105 °C

t_RET

Data retention

Years

1. Guaranteed by characterization results.

2. Cycling performed over the whole temperature range.

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STM32WB55xx

6.3.14

EMC characteristics

Susceptibility tests are performed on a sample basis during device characterization.

Functional EMS (electromagnetic susceptibility)

While a simple application is executed on the device (toggling 2 LEDs through I/O ports).

the device is stressed by two electromagnetic events until a failure occurs. The failure is

indicated by the LEDs:

•

Electrostatic discharge (ESD) (positive and negative) is applied to all device pins until

a functional disturbance occurs. This test is compliant with the IEC 61000-4-2 standard.

•

FTB: A Burst of Fast Transient voltage (positive and negative) is applied to V and

through a 100 pF capacitor, until a functional disturbance occurs. This test is

compliant with the IEC 61000-4-4 standard.

A device reset allows normal operations to be resumed.

The test results are given in Table 63. They are based on the EMS levels and classes

defined in application note AN1709 “EMC design guide for STM8, STM32 and Legacy

MCUs”, available on www.st.com.

Table 63. EMS characteristics

Level/

Class

Symbol

Parameter

Conditions

V_DD= 3.3 V, T_A= +25 °C,

f_HCLK= 64 MHz,

conforming to IEC 61000-4-2

Voltage limits to be applied on any I/O pin

to induce a functional disturbance

V_FESD

TBD

Fast transient voltage burst limits to be

V_EFTBapplied through 100 pF on V_DDand V_SS

pins to induce a functional disturbance

V_DD= 3.3 V, T_A= +25 °C,

f_HCLK= 64 MHz,

conforming to IEC 61000-4-4

Designing hardened software to avoid noise problems

EMC characterization and optimization are performed at component level with a typical

application environment and simplified MCU software. It should be noted that good EMC

performance is highly dependent on the user application and the software in particular.

Therefore it is recommended that the user applies EMC software optimization and

prequalification tests in relation with the EMC level requested for his application.

Software recommendations

The software flow must include the management of runaway conditions such as:

•

corrupted program counter

unexpected reset

critical data corruption (e.g. control registers)

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Electrical characteristics

Prequalification trials

Most of the common failures (unexpected reset and program counter corruption) can be

reproduced by manually forcing a low state on the NRST pin or the Oscillator pins for

1 second.

To complete these trials, ESD stress can be applied directly on the device, over the range of

specification values. When unexpected behavior is detected, the software can be hardened

to prevent unrecoverable errors occurring (see application note AN1015).

Electromagnetic Interference (EMI)

The electromagnetic field emitted by the device are monitored while a simple application is

executed (toggling two LEDs through the I/O ports). This emission test is compliant with

IEC 61967-2 standard which specifies the test board and the pin loading.

Table 64. EMI characteristics

Max vs.

[f_HSE/f_HCLK

]

Monitored

frequency band

Symbol Parameter

Conditions

Unit

8 MHz / 64 MHz

0.1 MHz to 30 MHz

30 MHz to 130 MHz

130 MHz to 1 GHz

1 GHz to 2 GHz

EMI level

TBD

V_DD= 3.6 V, T_A= 25 °C,

Peak level TBD package

dBµV

S_EMI

compliant with IEC 61967-2

6.3.15

Electrical sensitivity characteristics

Based on three different tests (ESD, LU) using specific measurement methods, the device is

stressed in order to determine its performance in terms of electrical sensitivity.

Electrostatic discharge (ESD)

Electrostatic discharges (a positive then a negative pulse separated by 1 second) are

applied to the pins of each sample according to each pin combination. The sample size

depends on the number of supply pins in the device (3 parts × (n+1) supply pins). This test

conforms to the ANSI/JEDEC standard.

Table 65. ESD absolute maximum ratings

Maximum

Symbol

Ratings

Conditions

Class

Unit

value⁽¹⁾

T_A= +25 °C, conforming

to ANSI/ESDA/JEDEC

JS-001

Electrostatic discharge

voltage (human body model)

V_ESD(HBM)

2000

Electrostatic discharge

T_A= +25 °C,

V_ESD(CDM)voltage (charge device

model)

conforming to ANSI/ESD

STM5.3.1 JS-002

500

1. Guaranteed by characterization results.

DS11929 Rev 3

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152

Electrical characteristics

Static latch-up

STM32WB55xx

Two complementary static tests are required on six parts to assess the latch-up

performance:

•

a supply overvoltage is applied to each power supply pin

acurrent injection is applied to each input, output and configurable I/O pin.

These tests are compliant with EIA/JESD 78A IC latch-up standard.

Table 66. Electrical sensitivities

Symbol

Parameter

Conditions

Class

Static latch-up class

T_A= +105 °C conforming to JESD78A

6.3.16

I/O current injection characteristics

As a general rule, current injection to the I/O pins, due to external voltage below V or

above V (for standard, 3.3 V-capable I/O pins) should be avoided during normal product

operation. However, in order to give an indication of the robustness of the microcontroller in

cases when abnormal injection accidentally happens, susceptibility tests are performed on a

sample basis during device characterization.

Functional susceptibility to I/O current injection

While a simple application is executed on the device, the device is stressed by injecting

current into the I/O pins programmed in floating input mode. While current is injected into

the I/O pin, one at a time, the device is checked for functional failures.

The failure is indicated by an out of range parameter: ADC error above a certain limit (higher

than 5 LSB TUE), out of conventional limits of induced leakage current on adjacent pins (out

of the -5 µA / +0 µA range) or other functional failure (for example reset occurrence or

oscillator frequency deviation).

The characterization results are given in Table 67.

Negative induced leakage current is caused by negative injection and positive induced

leakage current is caused by positive injection.

(1)

Table 67. I/O current injection susceptibility

Functional susceptibility

Symbol

Description

Unit

Negative

injection

Positive

injection

Injected current on all pins except PB0, PB1

Injected current on PB0, PB1 pins

TBD

N/A⁽²⁾

TBD

I_INJ

1. Guaranteed by characterization results.

2. Injection not possible.

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Electrical characteristics

6.3.17

I/O port characteristics

General input/output characteristics

Unless otherwise specified, the parameters given in Table 68 are derived from tests

performed under the conditions summarized in Table 22: General operating conditions. All

I/Os are designed as CMOS- and TTL-compliant.

Table 68. I/O static characteristics

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

I/O input

0.3 x V_DD

low level voltage⁽¹⁾

V_IL

I/O input

0.39 x V_DD- 0.06

low level voltage⁽²⁾

I/O input

0.7 x V_DD

high level voltage⁽¹⁾1.62 V < V_DD< 3.6 V

V_IH

I/O input

0.49 x V_DD+ 0.26

high level voltage⁽²⁾

TT_xx, FT_xxx

and NRST I/O

input hysteresis

V_hys

200

(3)

0 ≤ V_IN≤ Max(V_DDXXX

)

±100

650

Max(V_DDXXX) ≤ V_IN

≤

FT_xx

input leakage current

Max(V_DDXXX) +1 V^(2)(3)(4)

Max(V_DDXXX) +1 V < V_IN

5.5 V^{(2)(3)(4)(5)(6)}

≤

200⁽⁷⁾

±150

2500

(3)

0 ≤ V_IN≤ Max(V_DDXXX

)

I_lkg

FT_lu, FT_u and

PC3 IO

Max(V_DDXXX) ≤ V_IN≤

Max(V_DDXXX) +1 V⁽²⁾⁽³⁾

input leakage current

Max(V_DDXXX) +1 V < V_IN

5.5 V^(1)(3)(4)(8)

≤

250

±150

2000

(3)

V_IN≤ Max(V_DDXXX

)

TT_xx

input leakage current

Max(V_DDXXX) ≤ V_IN

3.6 V⁽³⁾

Weak pull-up

R_PU

V_IN= V_SS

equivalent resistor⁽¹⁾

kꢀ

Weak pull-down

R_PD

C_IO

V_IN= V_DD

equivalent resistor⁽¹⁾

I/O pin capacitance

1. Tested in production.

2. Guaranteed by design, not tested in production.

3. Represents the pad leakage of the I/O itself. The total product pad leakage is given by

I_{Total_Ileak_max}= 10 μA + number of I/Os where V_INis applied on the pad x I_lkg(Max)

4. Max(V_DDXXX) is the maximum value among all the I/O supplies.

5. V_INmust be lower than [Max(V_DDXXX) + 3.6 V].

6. Refer to Figure 22: I/O input characteristics.

DS11929 Rev 3

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152

Electrical characteristics

STM32WB55xx

7. To sustain a voltage higher than Min(V_DD, V_DDA, V_DDUSB, V_LCD) + 0.3 V, the internal pull-up and pull-down resistors must

be disabled. All FT_xx IO except FT_lu, FT_u and PC3.

8. Pull-up and pull-down resistors are designed with a true resistance in series with a switchable PMOS/NMOS, whose

contribution to the series resistance is minimal (~10%).

All I/Os are CMOS- and TTL-compliant (no software configuration required). Their

characteristics cover more than the strict CMOS-technology or TTL parameters, as shown

in Figure 22 .

Figure 22. I/O input characteristics

Vil-Vih (all IO except BOOT0)

2.5

TTL requirement Vih min = 2V

cmos vil spec 30%

cmos vih spec 70%

ttl vil spec ttl

1.5

ttl vih spec ttl

datasheet Vil_rule

datasheet Vih_rule

TTL requirement Vil min = 0.8V

0.5

1.5

2.5

3.5

Output driving current

The GPIOs (general purpose input/outputs) can sink or source up to ±8 mA, and sink or

source up to ± 20 mA (with a relaxed V / V ).

In the user application, the number of I/O pins that can drive current must be limited to

respect the absolute maximum rating specified in Section 6.2.

•

The sum of the currents sourced by all the I/Os on V , plus the maximum

consumption of the MCU sourced on V

cannot exceed the absolute maximum rating

DD,

ΣI

(see Table 18: Voltage characteristics).

VDD

•

The sum of the currents sunk by all the I/Os on V , plus the maximum consumption of

the MCU sunk on V , cannot exceed the absolute maximum rating ΣI

(see

VSS

Table 18: Voltage characteristics).

Output voltage levels

Unless otherwise specified, the parameters given in the table below are derived from tests

performed under the ambient temperature and supply voltage conditions summarized in

Table 22: General operating conditions. All I/Os are CMOS- and TTL-compliant (FT or TT

unless otherwise specified).

122/165

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Electrical characteristics

(1)

Table 69. Output voltage characteristics

Parameter Conditions

Symbol

Min

Max Unit

(2)

V_OL

Output low level voltage for an I/O pin CMOS port⁽³⁾

|I_IO| = 8 mA

0.4

(2)

V_OH

Output high level voltage for an I/O pin

V_DD- 0.4

V_DD≥ 2.7 V

(2)

V_OL

Output low level voltage for an I/O pin TTL port⁽³⁾

|I_IO| = 8 mA

0.4

(2)

V_OH

Output high level voltage for an I/O pin

2.4

V_DD≥ 2.7 V

(2)

V_OL

Output low level voltage for an I/O pin

Output high level voltage for an I/O pin

Output low level voltage for an I/O pin

Output high level voltage for an I/O pin

1.3

|I_IO| = 20 mA

V_DD≥ 2.7 V

V_OH

V_DD- 1.3

(2)

V_OL

V_OH

0.4

|I_IO| = 4 mA

V_DD≥ 1.62 V

(2)

V_DD- 0.45

|I_IO| = 20 mA

V_DD≥ 2.7 V

0.4

Output low level voltage for an FT I/O

|I_IO| = 10 mA

(2)

V_OLFM+

0.4

pin in FM+ mode (FT I/O with “f” option) V_DD≥ 1.62 V

|I_IO| = 2 mA

1.62 V ≥ V_DD≥ 1.08 V

1. The I_IOcurrent sourced or sunk by the device must always respect the absolute maximum rating specified

in Table 18: Voltage characteristics, and the sum of the currents sourced or sunk by all the I/Os (I/O ports

and control pins) must always respect the absolute maximum ratings Σ I_IO

2. Guaranteed by design.

3. TTL and CMOS outputs are compatible with JEDEC standards JESD36 and JESD52.

Input/output AC characteristics

The definition and values of input/output AC characteristics are given in Table 70.

Unless otherwise specified, the parameters given are derived from tests performed under

the ambient temperature and supply voltage conditions summarized in Table 22: General

operating conditions.

(1)(2)

Table 70. I/O AC characteristics

Speed Symbol

Parameter

Conditions

Min

Max

Unit

C=50 pF, 2.7 V ≤ V_DD≤ 3.6 V

C=50 pF, 1.62 V ≤ V_DD≤ 2.7 V

C=10 pF, 2.7 V ≤ V_DD≤ 3.6 V

C=10 pF, 1.62 V ≤ V_DD≤ 2.7 V

C=50 pF, 2.7 V ≤ V_DD≤ 3.6 V

C=50 pF, 1.62 V ≤ V_DD≤ 2.7 V

C=10 pF, 2.7 V ≤ V_DD≤ 3.6 V

C=10 pF, 1.62 V ≤ V_DD≤ ≤2.7 V

Fmax Maximum frequency

MHz

1.5

Tr/Tf Output rise and fall time

DS11929 Rev 3

123/165

152

Electrical characteristics

Speed Symbol

STM32WB55xx

(1)(2)

Table 70. I/O AC characteristics

(continued)

Parameter

Conditions

Min

Max

Unit

C=50 pF, 2.7 V ≤ V_DD≤ 3.6 V

C=50 pF, 1.62 V ≤ V_DD≤ ≤2.7 V

C=10 pF, 2.7 V ≤ V_DD≤ 3.6 V

C=10 pF, 1.62 V ≤ V_DD≤ 2.7 V

C=50 pF, 2.7 V ≤ V_DD≤ 3.6 V

C=50 pF, 1.62 V ≤ V_DD≤ 2.7 V

C=10 pF, 2.7 V ≤ V_DD≤ 3.6 V

C=10 pF, 1.62 V ≤ V_DD≤ 2.7 V

C=50 pF, 2.7 V ≤ V_DD≤ 3.6 V

C=50 pF, 1.62 V ≤ V_DD≤ 2.7 V

C=10 pF, 2.7 V ≤ V_DD≤ 3.6 V

C=10 pF, 1.62 V ≤ V_DD≤ 2.7 V

C=50 pF, 2.7 V ≤ V_DD≤ 3.6 V

C=50 pF, 1.62 V ≤ V_DD≤ 2.7 V

C=10 pF, 2.7 V ≤ V_DD≤ 3.6 V

C=10 pF, 1.62 V ≤ V_DD≤ 2.7 V

C=30 pF, 2.7 V ≤ V_DD≤ 3.6 V

C=30 pF, 1.62 V ≤ V_DD≤ 2.7 V

C=10 pF, 2.7 V ≤ V_DD≤ 3.6 V

C=10 pF, 1.62 V ≤ V_DD≤ 2.7 V

C=30 pF, 2.7 V ≤ V_DD≤ 3.6 V

C=30 pF, 1.62 V ≤ V_DD≤ 2.7 V

C=10 pF, 2.7 V ≤ V_DD≤ 3.6 V

C=10 pF, 1.62 V ≤ V_DD≤ 2.7 V

Fmax Maximum frequency

Tr/Tf Output rise and fall time

Fmax Maximum frequency

Tr/Tf Output rise and fall time

Fmax Maximum frequency

Tr/Tf Output rise and fall time

MHz

4.5

100⁽³⁾

37.5

5.8

2.5

120⁽³⁾

MHz

180⁽³⁾

75⁽³⁾

3.3

1.7

3.3

1. The maximum frequency is defined with (T_r+ T_f) ≤ 2/3 T, and Duty cycle comprised between 45 and 55%.

2. The fall and rise time are defined, respectively, between 90 and 10%, and between 10 and 90% of the

output waveform.

3. This value represents the I/O capability but the maximum system frequency is limited to 64 MHz.

6.3.18

NRST pin characteristics

The NRST pin input driver uses the CMOS technology. It is connected to a permanent

pull-up resistor, R

Unless otherwise specified, the parameters given in the table below are derived from tests

performed under the ambient temperature and supply voltage conditions summarized in

Table 22: General operating conditions.

124/165

DS11929 Rev 3

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Electrical characteristics

(1)

Table 71. NRST pin characteristics

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

NRST input

low level voltage

V_IL(NRST)

V_IH(NRST)

V_hys(NRST)

R_PU

0.3 x V_DD

NRST input

high level voltage

0.7 x V_DD

200

NRST Schmitt trigger

voltage hysteresis

Weak pull-up

V_IN= V_SS

kꢀ

equivalent resistor⁽²⁾

NRST input

filtered pulse

V_F(NRST)

V_NF(NRST)

NRST input

not filtered pulse

1.71 V ≤ V_DD≤ 3.6 V

350

1. Guaranteed by design.

2. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution to

^{the series resistance is minimal (~10% order)}.

Figure 23. Recommended NRST pin protection

([WHUQDO

UHVHWꢅFLUFXLW^ꢒꢁꢓ

9_''

5₃₈

1567^ꢒꢆꢓ

,QWHUQDOꢅUHVHW

)LOWHU

ꢂꢐꢁꢅ)

06ꢁꢈꢋꢃꢋ9ꢊ

1. The reset network protects the device against parasitic resets.

2. The user must ensure that the level on the NRST pin can go below the V_IL(NRST)max level specified in

Table 71: NRST pin characteristics. Otherwise the reset will not be taken into account by the device.

3. The external capacitor on NRST must be placed as close as possible to the device.

DS11929 Rev 3

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152

Electrical characteristics

STM32WB55xx

6.3.19

Analog switches booster

(1)

Table 72. Analog switches booster characteristics

Symbol

Parameter

Supply voltage

Min

Typ

Max

Unit

V_DD

1.62

3.6

t_SU(BOOST)

Booster startup time

240

µs

Booster consumption for

1.62 V ≤ V_DD≤ 2.0 V

250

500

900

Booster consumption for

2.0 V ≤ V_DD≤ 2.7 V

I_DD(BOOST)

µA

Booster consumption for

2.7 V ≤ V_DD≤ 3.6 V

1. Guaranteed by design.

126/165

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Electrical characteristics

6.3.20

Analog-to-Digital converter characteristics

Unless otherwise specified, the parameters given in Table 73 are preliminary values derived

from tests performed under ambient temperature, f

frequency and V

supply voltage

PCLK

DDA

conditions summarized in Table 22: General operating conditions.

Note:

It is recommended to perform a calibration after each power-up.

(1) (2) (3)

Table 73. ADC characteristics

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

V_DDA

Analog supply voltage

1.62

3.6

V_DDA≥ 2 V

V_DDA< 2 V

V_DDA

Positive reference

voltage

V_REF+

V_DDA

Negative reference

voltage

V_REF-

V_SSA

Range 1

f_ADC

ADC clock frequency

MHz

Range 2

Resolution = 12 bits

Resolution = 10 bits

Resolution = 8 bits

Resolution = 6 bits

Resolution = 12 bits

Resolution = 10 bits

Resolution = 8 bits

Resolution = 6 bits

4.26

4.92

5.81

7.11

TBD

Sampling rate

for FAST channels

f_s

Msps

Sampling rate

for SLOW channels

f_ADC= 64 MHz

Resolution = 12 bits

4.26

MHz

External trigger

frequency

f_TRIG

Resolution = 12 bits

Differential mode

1/f_ADC

(V_REF+

_REF-) / 2

- 0.18

(V_REF++

_REF-) / 2

+ 0.18

(V_REF+

V_REF-) / 2

Input common mode

CMIN

Conversion voltage

range(2)

(4)

V_AIN

V_REF+

External input

impedance

R_AIN

C_ADC

t_STAB

kꢀ

Internal sample and hold

capacitor

Conversion

cycle

Power-up time

Calibration time

_ADC= 64 MHz

1.8125

116

µs

t_CAL

1 / f_ADC

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152

Electrical characteristics

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(1) (2) (3)

Table 73. ADC characteristics

Conditions

(continued)

Symbol

Parameter

Min

1.5

Typ

Max

Unit

CKMODE = 00

2.5

2.0

Trigger conversion

CKMODE = 01

CKMODE = 10

CKMODE = 11

CKMODE = 00

CKMODE = 01

CKMODE = 10

CKMODE = 11

latency Regular and

injected channels

without conversion abort

t_LATR

1/f_ADC

2.25

2.125

3.5

2.5

Trigger conversion

latency Injected

channels aborting a

regular conversion

3.0

t_LATRINJ

1/f_ADC

3.25

3.125

10.0

640.5

_ADC= 64 MHz

0.039

2.5

µs

t_s

Sampling time

1/f_ADC

ADC voltage regulator

start-up time

µs

ADCVREG_STUP

f_ADC= 64 MHz

Resolution = 12 bits

0.234

1.019

Total conversion time

(including sampling time)

t_CONV

t_s+ 12.5 cycles for successive

approximations = 15 to 653

Resolution = 12 bits

1/f_ADC

fs = 4.26 Msps

fs = 1 Msps

TBD

160

TBD

220

ADC consumption from

the V_DDAsupply

I_DDA(ADC)

µA

fs = 10 ksps

fs = 4.26 Msps

TBD

ADC consumption from

_{DDV_S}(ADC) the V_REF+single ended fs = 1 Msps

µA

mode

fs = 10 ksps

fs = 4.26 Msps

fs = 1 Msps

fs = 10 ksps

0.6

TBD

ADC consumption from

I_{DDV_D}(ADC) the V_REF+differential

mode

1.3

1. Guaranteed by design

2. The I/O analog switch voltage booster is enabled when V_DDA< 2.4 V (BOOSTEN = 1 in the SYSCFG_CFGR1 when

_DDA< 2.4V). It is disable when V_DDA≥ 2.4 V.

3. SMPS in bypass mode.

4. V_REF+can be internally connected to V_DDAand V_REF-can be internally connected to V_SSA, depending on the package.

Refer to Section 4: Pinouts and pin description for further details.

128/165

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Electrical characteristics

(1)(2)

Table 74. Maximum ADC RAIN

RAIN max (Ω)

Resolution Sampling cycle at 64 MHz Sampling time [ns] at 64 MHz

Fast channels⁽³⁾Slow channels⁽⁴⁾

2.5

6.5

39.06

101.56

195.31

382.81

742.19

1445.31

3867.19

10007.81

39.06

TBD

12.5

24.5

47.5

92.5

247.5

640.5

2.5

12 bits

10 bits

8 bits

6.5

101.56

195.31

382.81

742.19

1445.31

3867.19

10007.81

39.06

12.5

24.5

47.5

92.5

247.5

640.5

2.5

6.5

101.56

195.31

382.81

742.19

1445.31

3867.19

10007.81

39.06

12.5

24.5

47.5

92.5

247.5

640.5

2.5

6.5

101.56

195.31

382.81

742.19

1445.31

3867.19

10007.81

12.5

24.5

47.5

92.5

247.5

640.5

6 bits

1. Guaranteed by design.

DS11929 Rev 3

129/165

152

Electrical characteristics

STM32WB55xx

2. The I/O analog switch voltage booster is enabled when V_DDA< 2.4 V (BOOSTEN = 1 in the SYSCFG_CFGR1 when

V_DDA< 2.4V). It is disabled when V_DDA≥ 2.4 V.

3. Fast channels are PC0, PC1, PC2, PC3, PA0, PA1.

4. Slow channels are all ADC inputs except the fast channels.

(1)(2)(3)

Table 75. ADC accuracy - Limited test conditions 1

Symbol Parameter

Conditions⁽⁴⁾

Min Typ Max Unit

Fast channel (max speed)

TBD TBD TBD

Single

ended

Total

Slow channel (max speed)

Fast channel (max speed)

Slow channel (max speed)

Fast channel (max speed)

Slow channel (max speed)

Fast channel (max speed)

Slow channel (max speed)

Fast channel (max speed)

Slow channel (max speed)

Fast channel (max speed)

Slow channel (max speed)

Fast channel (max speed)

Slow channel (max speed)

Fast channel (max speed)

Slow channel (max speed)

unadjusted

error

Differential

Single

ended

Offset error

Gain error

Differential

TBD TBD TBD

LSB

TBD TBD TBD

Single

ended

TBD TBD TBD

Differential

Single

ended

Differential

linearity

error

Differential

130/165

DS11929 Rev 3

STM32WB55xx

Electrical characteristics

(1)(2)(3)

Table 75. ADC accuracy - Limited test conditions 1

(continued)

Symbol Parameter

Conditions⁽⁴⁾

Min Typ Max Unit

Fast channel (max speed)

Slow channel (max speed)

Fast channel (max speed)

Slow channel (max speed)

Fast channel (max speed)

Slow channel (max speed)

Fast channel (max speed)

Slow channel (max speed)

Fast channel (max speed)

Slow channel (max speed)

Fast channel (max speed)

Slow channel (max speed)

Fast channel (max speed)

Slow channel (max speed)

Fast channel (max speed)

Slow channel (max speed)

Fast channel (max speed)

Slow channel (max speed)

Fast channel (max speed)

Slow channel (max speed)

TBD TBD TBD

Single

ended

Integral

linearity

error

TBD TBD TBD

LSB

TBD TBD TBD

Differential

TBD TBD TBD

Single

ended

Effective

number of

bits

TBD TBD TBD

bits

TBD TBD TBD

ENOB

SINAD

SNR

Differential

TBD TBD TBD

Single

ended

Signal-to-

noise and

distortion

ratio

Differential

Single

ended

TBD TBD TBD

Signal-to-

noise ratio

Differential

TBD TBD TBD

Single

ended

Total

harmonic

distortion

THD

Differential

1. Guaranteed by design.

2. ADC DC accuracy values are measured after internal calibration.

3. Injecting negative current on any analog input pin should be avoided as this significantly reduces the accuracy of the

conversion being performed on another analog input. It is recommended to add a Schottky diode (pin to ground) to analog

pins that may potentially inject negative current.

4. The I/O analog switch voltage booster is enabled when V_DDA< 2.4 V (BOOSTEN = 1 in the SYSCFG_CFGR1 when

_DDA< 2.4 V). It is disabled when V_DDA≥ 2.4 V. No oversampling.

DS11929 Rev 3

131/165

152

Electrical characteristics

STM32WB55xx

(1)(2)(3)

Table 76. ADC accuracy - Limited test conditions 2

Conditions⁽⁴⁾

Fast channel (max speed)

Symbol Parameter

Min Typ Max Unit

TBD TBD TBD

Single

ended

Total

Slow channel (max speed)

Fast channel (max speed)

Slow channel (max speed)

Fast channel (max speed)

Slow channel (max speed)

Fast channel (max speed)

Slow channel (max speed)

Fast channel (max speed)

Slow channel (max speed)

Fast channel (max speed)

Slow channel (max speed)

Fast channel (max speed)

Slow channel (max speed)

Fast channel (max speed)

Slow channel (max speed)

Fast channel (max speed)

Slow channel (max speed)

Fast channel (max speed)

Slow channel (max speed)

Fast channel (max speed)

Slow channel (max speed)

Fast channel (max speed)

Slow channel (max speed)

unadjusted

error

Differential

Single

ended

Offset error

Gain error

Differential

Single

ended

TBD TBD TBD

LSB

TBD TBD TBD

Differential

TBD TBD TBD

Single

ended

Differential

linearity

error

Differential

Single

ended

Integral

linearity

error

Differential

Single

ended

Effective

number of

bits

TBD TBD TBD

bits

TBD TBD TBD

ENOB

Differential

TBD TBD TBD

132/165

DS11929 Rev 3

STM32WB55xx

Electrical characteristics

(1)(2)(3)

Table 76. ADC accuracy - Limited test conditions 2

(continued)

Symbol Parameter

Conditions⁽⁴⁾

Min Typ Max Unit

Fast channel (max speed)

Slow channel (max speed)

Fast channel (max speed)

Slow channel (max speed)

Fast channel (max speed)

Slow channel (max speed)

Fast channel (max speed)

Slow channel (max speed)

Fast channel (max speed)

Slow channel (max speed)

Fast channel (max speed)

Slow channel (max speed)

TBD TBD TBD

Single

ended

Signal-to-

noise and

distortion

ratio

SINAD

Differential

Single

ended

TBD TBD TBD

Signal-to-

SNR

noise ratio

Differential

TBD TBD TBD

Single

ended

Total

harmonic

distortion

THD

Differential

1. Guaranteed by design.

2. ADC DC accuracy values are measured after internal calibration.

3. Injecting negative current on any analog input pin should be avoided as this significantly reduces the accuracy of the

conversion being performed on another analog input. It is recommended to add a Schottky diode (pin to ground) to analog

pins that may potentially inject negative current.

4. The I/O analog switch voltage booster is enabled when V_DDA< 2.4 V (BOOSTEN = 1 in the SYSCFG_CFGR1 when

V_DDA< 2.4 V). It is disabled when V_DDA≥ 2.4 V. No oversampling.

(1)(2)(3)

Table 77. ADC accuracy - Limited test conditions 3

Symbol Parameter

Conditions⁽⁴⁾

Min Typ Max Unit

Fast channel (max speed)

TBD TBD TBD

Single

ended

Total

Slow channel (max speed)

Fast channel (max speed)

Slow channel (max speed)

Fast channel (max speed)

Slow channel (max speed)

Fast channel (max speed)

Slow channel (max speed)

Fast channel (max speed)

Slow channel (max speed)

Fast channel (max speed)

Slow channel (max speed)

unadjusted

error

Differential

Single

ended

TBD TBD TBD

LSB

TBD TBD TBD

Offset error

Gain error

Differential

TBD TBD TBD

Single

ended

Differential

DS11929 Rev 3

133/165

152

Electrical characteristics

STM32WB55xx

(1)(2)(3)

Table 77. ADC accuracy - Limited test conditions 3

(continued)

Symbol Parameter

Conditions⁽⁴⁾

Min Typ Max Unit

Fast channel (max speed)

Slow channel (max speed)

Fast channel (max speed)

Slow channel (max speed)

Fast channel (max speed)

Slow channel (max speed)

Fast channel (max speed)

Slow channel (max speed)

Fast channel (max speed)

Slow channel (max speed)

Fast channel (max speed)

Slow channel (max speed)

Fast channel (max speed)

Slow channel (max speed)

Fast channel (max speed)

Slow channel (max speed)

Fast channel (max speed)

Slow channel (max speed)

Fast channel (max speed)

Slow channel (max speed)

Fast channel (max speed)

Slow channel (max speed)

Fast channel (max speed)

Slow channel (max speed)

TBD TBD TBD

Single

ended

Differential

linearity

error

Differential

TBD TBD TBD

LSB

TBD TBD TBD

Single

ended

Integral

linearity

error

TBD TBD TBD

Differential

Single

ended

Effective

ENOB number of

bits

TBD TBD TBD

bits

TBD TBD TBD

Differential

TBD TBD TBD

Single

ended

Signal-to-

noise and

distortion

ratio

SINAD

Differential

TBD TBD TBD

Single

ended

TBD TBD TBD

Signal-to-

SNR

noise ratio

Differential

Single

ended

Total

THD harmonic

distortion

TBD TBD TBD

Differential

TBD TBD TBD

1. Guaranteed by design.

2. ADC DC accuracy values are measured after internal calibration.

3. Injecting negative current on any analog input pin should be avoided as this significantly reduces the accuracy of the

conversion being performed on another analog input. It is recommended to add a Schottky diode (pin to ground) to analog

pins that may potentially inject negative current.

4. The I/O analog switch voltage booster is enabled when V_DDA< 2.4 V (BOOSTEN = 1 in the SYSCFG_CFGR1 when

V_DDA< 2.4 V). It is disabled when V_DDA≥ 2.4 V. No oversampling.

134/165

DS11929 Rev 3

STM32WB55xx

Electrical characteristics

(1)(2)(3)

Table 78. ADC accuracy - Limited test conditions 4

Conditions⁽⁴⁾

Symbol Parameter

Min Typ Max Unit

Fast channel (max speed)

Single

TBD TBD TBD

ended

Total

unadjusted

error

Slow channel (max speed) TBD TBD TBD

Fast channel (max speed)

TBD TBD TBD

Differential

Slow channel (max speed) TBD TBD TBD

Fast channel (max speed) TBD TBD TBD

Slow channel (max speed) TBD TBD TBD

Fast channel (max speed) TBD TBD TBD

Slow channel (max speed) TBD TBD TBD

Fast channel (max speed) TBD TBD TBD

Slow channel (max speed) TBD TBD TBD

Fast channel (max speed) TBD TBD TBD

Slow channel (max speed) TBD TBD TBD

Fast channel (max speed) TBD TBD TBD

Slow channel (max speed) TBD TBD TBD

Fast channel (max speed) TBD TBD TBD

Slow channel (max speed) TBD TBD TBD

Fast channel (max speed) TBD TBD TBD

Slow channel (max speed) TBD TBD TBD

Fast channel (max speed) TBD TBD TBD

Slow channel (max speed) TBD TBD TBD

Fast channel (max speed) TBD TBD TBD

Slow channel (max speed) TBD TBD TBD

Fast channel (max speed) TBD TBD TBD

Slow channel (max speed) TBD TBD TBD

Fast channel (max speed) TBD TBD TBD

Slow channel (max speed) TBD TBD TBD

Fast channel (max speed) TBD TBD TBD

Slow channel (max speed) TBD TBD TBD

Fast channel (max speed) TBD TBD TBD

Slow channel (max speed) TBD TBD TBD

Fast channel (max speed) TBD TBD TBD

Slow channel (max speed) TBD TBD TBD

Single

ended

Offset error

Gain error

Differential

Single

ended

LSB

Differential

Single

ended

Differential

linearity

error

Differential

Single

ended

Integral

linearity

error

Differential

Single

ended

Effective

ENOB number of

bits

Differential

Single

ended

Signal-to-

noise and

distortion

ratio

SINAD

Differential

Single

ended

Signal-to-

SNR

noise ratio

Differential

DS11929 Rev 3

135/165

152

Electrical characteristics

STM32WB55xx

(1)(2)(3)

Table 78. ADC accuracy - Limited test conditions 4

(continued)

Symbol Parameter

Conditions⁽⁴⁾

Min Typ Max Unit

Fast channel (max speed)

TBD TBD TBD

Single

ended

Slow channel (max speed) TBD TBD TBD

Total

THD

harmonic

distortion

Fast channel (max speed)

TBD TBD TBD

Differential

Slow channel (max speed) TBD TBD TBD

1. Guaranteed by design.

2. ADC DC accuracy values are measured after internal calibration.

3. ADC accuracy vs. negative Injection Current: Injecting negative current on any analog input pins should be avoided as this

significantly reduces the accuracy of the conversion being performed on another analog input. It is recommended to add a

Schottky diode (pin to ground) to analog pins which may potentially inject negative current.

4. The I/O analog switch voltage booster is enable when V_DDA< 2.4 V (BOOSTEN = 1 in the SYSCFG_CFGR1 when

_DDA< 2.4 V). It is disable when V_DDA≥ 2.4 V. No oversampling.

Figure 24. ADC accuracy characteristics

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136/165

DS11929 Rev 3

STM32WB55xx

Electrical characteristics

Figure 25. Typical connection diagram using the ADC

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1. Refer to Table 73: ADC characteristics for the values of R_AIN, R_ADCand C_ADC

2. C_parasiticrepresents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the

pad capacitance (refer to Table 68: I/O static characteristics for the value of the pad capacitance). A high

_parasiticvalue will downgrade conversion accuracy. To remedy this, f_ADCshould be reduced.

3. Refer to Table 68: I/O static characteristics for the values of Ilkg.

General PCB design guidelines

Power supply decoupling should be performed as shown in Figure 13: Power supply

scheme. The 10 nF capacitor should be ceramic (good quality) and it should be placed as

close as possible to the chip.

6.3.21

Voltage reference buffer characteristics

(1)

Table 79. VREFBUF characteristics

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

_RS= 0

2.4

2.8

3.6

2.4

2.8

Normal mode

V_RS= 1

Analog supply

voltage

V_DDA

V_RS= 0

V_RS= 1

V_RS= 0

V_RS= 1

V_RS= 0

V_RS= 1

1.65

Degraded mode⁽²⁾

Normal mode

1.65

2.046⁽³⁾

2.498⁽³⁾

V_DDA-150 mV

2.048 2.049⁽³⁾

2.5

2.502⁽³⁾

V_{REFBUF_}Voltage

reference output

OUT

V_DDA

Degraded mode⁽²⁾

V_DDA

Trim step

resolution

TRIM

±0.05

±0.1

1.5

Load capacitor

0.5

µF

Equivalent

series resistor

of C_load

esr

ꢀ

Static load

current

I_load

DS11929 Rev 3

137/165

152

Electrical characteristics

STM32WB55xx

(1)

Table 79. VREFBUF characteristics (continued)

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

_load= 500 µA

200

100

1000

500

I_{line_reg}

I_{load_reg}

Line regulation 2.8 V ≤ V_DDA≤ 3.6 V

ppm/V

I_load= 4 mA

Load regulation 500 μA ≤ I_load≤4 mA Normal mode

500

ppm/mA

T_{coeff_}

-40 °C < T_J< +125 °C

vrefint

Temperature

coefficient

T_Coeff

ppm/ °C

T_{coeff_}

0 °C < T_J< +50 °C

vrefint

Power supply

rejection

PSRR

t_START

µs

100 kHz

CL = 0.5 µF⁽⁴⁾

300

500

650

350

650

800

Start-up time

CL = 1.1 µF⁽⁴⁾

CL = 1.5 µF⁽⁴⁾

Control of

maximum DC

current drive on

VREFBUF_OUT

during start-up

phase ⁽⁵⁾

I_INRUSH

µA

I_load= 0 µA

VREFBUF

consumption

from V_DDA

I_DDA

(VREFBUF)

_load= 500 µA

I_load= 4 mA

1. Guaranteed by design, unless otherwise specified.

2. In degraded mode, the voltage reference buffer cannot maintain accurately the output voltage that will follow (V_DDA- drop

voltage).

3. Guaranteed by test in production.

4. The capacitive load must include a 100 nF capacitor in order to cut-off the high frequency noise.

5. To correctly control the VREFBUF in-rush current during start-up phase and scaling change, the V_DDAvoltage must be in

the range [2.4 V to 3.6 V] and [2.8 V to 3.6 V] respectively for V_RS= 0 and V_RS= 1.

138/165

DS11929 Rev 3

STM32WB55xx

Electrical characteristics

6.3.22

Comparator characteristics

(1)

Table 80. COMP characteristics

Conditions

Symbol

V_DDA

Parameter

Min

Typ

Max Unit

Analog supply voltage

1.62

3.6

Comparator

input voltage range

V_IN

V_DDA

(2)

V_BG

Scaler input voltage

Scaler offset voltage

V_REFINT

V_SC

BRG_EN=0 (bridge disable)

BRG_EN=1 (bridge enable)

±5

200

0.8

100

±10

300

µA

µs

Scaler static consumption

from V_DDA

_DDA(SCALER)

t_{START_SCALER}Scaler startup time

200

V_DDA≥ 2.7 V

High-speed

mode

_DDA< 2.7 V

_DDA≥ 2.7 V

_DDA< 2.7 V

Comparator startup time

to reach propagation

delay specification

t_START

100

0.9

µs

Medium mode

Ultra-low-power mode

V_DDA≥ 2.7 V

V_DDA< 2.7 V

0.55

High-speed

mode

Propagation delay with

100 mV overdrive

(3)

t_D

Medium mode

µs

Ultra-low-power mode

Full common mode range

No hysteresis

V_offset

Comparator offset error

Comparator hysteresis

±5

±20

Low hysteresis

V_hys

Medium hysteresis

High hysteresis

400

Static

600

Ultra-low-

power mode

With 50 kHz ±100 mV

overdrive square signal

1200

Static

Comparator consumption Medium

from V_DDA

I_DDA(COMP)

With 50 kHz ±100 mV

overdrive square signal

mode

100

µA

Static

High-speed

mode

With 50 kHz ±100 mV

overdrive square signal

1. Guaranteed by design, unless otherwise specified.

2. Refer to Table 34: Embedded internal voltage reference.

3. Guaranteed by characterization results.

DS11929 Rev 3

139/165

152

Electrical characteristics

STM32WB55xx

6.3.23

Temperature sensor characteristics

Table 81. TS characteristics

Parameter

Symbol

Min

Typ

Max

Unit

(1)

T_L

V_TSlinearity with temperature

±1

2.5

±2

2.7

°C

mV / °C

Avg_Slope⁽²⁾Average slope

2.3

V₃₀

Voltage at 30 °C (±5 °C)⁽³⁾

0.742

0.76

0.785

t_START

Sensor buffer start-up time in continuous mode⁽⁴⁾

µs

(TS_BUF)⁽¹⁾

Start-up time when entering in continuous mode⁽⁴⁾

ADC sampling time when reading the temperature

120

µs

(1)

t_START

(1)

t_{S_temp}

Temperature sensor consumption from V_DD, when

selected by ADC

_DD(TS)⁽¹⁾

4.7

µA

1. Guaranteed by design.

2. Guaranteed by characterization results.

3. Measured at V_DDA= 3.0 V ±10 mV. The V₃₀ADC conversion result is stored in the TS_CAL1 byte. Refer to Table 11:

Temperature sensor calibration values.

4. Continuous mode means Run/Sleep modes, or temperature sensor enable in Low-power run/Low-power sleep modes.

6.3.24

monitoring characteristics

BAT

Table 82. V

monitoring characteristics

BAT

Symbol

Parameter

Resistor bridge for V_BAT

Min

Typ

Max

Unit

kꢀ

Ratio on V_BATmeasurement

Error on Q

Er⁽¹⁾

-10

µs

(1)

t_{S_vbat}

ADC sampling time when reading the VBAT

1. Guaranteed by design.

Table 83. V

charging characteristics

BAT

Symbol

Parameter Conditions

Min

Typ

Max

Unit

Battery

charging

resistor

VBRS = 0

VBRS = 1

R_BC

kꢀ

1.5

140/165

DS11929 Rev 3

STM32WB55xx

Electrical characteristics

6.3.25

SMPS step-down converter characteristics

The SMPS step-down converter characteristic are given at 4 MHz clock, with a load of

20 mA (unless otherwise specified), using a 10 µH inductor and a 4.7 µF capacitor.

Table 84. SMPS step-down converter characteristics

Symbol

Parameter

Conditions

Min

Typ

Max⁽¹⁾

Unit

_ddsmps= 3.6 V, V_fbsmps= 1.4 V

TBD

T_{smps_start}Startup time from bypass mode

T_{smps_trans}Transition time

μs

V_ddsmps= 2.0 V, V_fbsmps= 1.4 V

_fbsmpsfrom 1.4 to 1.7 V

V_fbsmpsfrom 1.7 to 1.4 V

mV / μs

1. Maximum values are provided over the -40 °C to 90 °C temperature range.

6.3.26

LCD controller characteristics

The devices embed a built-in step-up converter to provide a constant LCD reference voltage

independently from the V voltage. An external capacitor C must be connected to the

ext

VLCD pin to decouple this converter.

(1)

Table 85. LCD controller characteristics

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

V_LCD

V_LCD0

V_LCD1

V_LCD2

V_LCD3

V_LCD4

V_LCD5

V_LCD6

V_LCD7

LCD external voltage

3.6

LCD internal reference voltage 0

LCD internal reference voltage 1

LCD internal reference voltage 2

LCD internal reference voltage 3

LCD internal reference voltage 4

LCD internal reference voltage 5

LCD internal reference voltage 6

LCD internal reference voltage 7

2.62

2.76

2.89

3.04

3.19

3.32

3.46

3.62

Buffer OFF

(BUFEN=0 is LCD_CR register)

0.2

C_ext

V_LCDexternal capacitance

μF

μA

Buffer ON

(BUFEN=1 is LCD_CR register)

Supply current from V_DDat Buffer OFF

V_DD= 2.2 V

(BUFEN=0 is LCD_CR register)

(2)

I_LCD

Supply current from V_DDat Buffer OFF

1.5

V_DD= 3.0 V

(BUFEN=0 is LCD_CR register)

DS11929 Rev 3

141/165

152

Electrical characteristics

STM32WB55xx

(1)

Table 85. LCD controller characteristics (continued)

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

Buffer OFF

(BUFFEN = 0, PON = 0)

0.5

Buffer ON

(BUFFEN = 1, 1/2 Bias)

0.6

0.8

Supply current from V_LCD

(V_LCD= 3 V)

I_VLCD

μA

Buffer ON

(BUFFEN = 1, 1/3 Bias)

Buffer ON

(BUFFEN = 1, 1/4 Bias)

R_HN

R_LN

V₄₄

V₃₄

V₂₃

V₁₂

V₁₃

V₁₄

V₀

Total High resistor value for Low drive resistive network

Total Low resistor value for High drive resistive network

Segment/Common highest level voltage

Segment/Common 3/4 level voltage

5.5

Mꢀ

kꢀ

240

V_LCD

3/4 V_LCD

2/3 V_LCD

1/2 V_LCD

1/3 V_LCD

1/4 V_LCD

Segment/Common 2/3 level voltage

Segment/Common 1/2 level voltage

Segment/Common 1/3 level voltage

Segment/Common 1/4 level voltage

Segment/Common lowest level voltage

1. Guaranteed by design.

2. LCD enabled with 3 V internal step-up active, 1/8 duty, 1/4 bias, division ratio = 64, all pixels active, no LCD connected.

6.3.27

Timer characteristics

The parameters given in the following tables are guaranteed by design. Refer to

Section 6.3.17: I/O port characteristics for details on the input/output alternate function

characteristics (output compare, input capture, external clock, PWM output).

(1)

Table 86. TIMx characteristics

Symbol

t_res(TIM)

Parameter

Conditions

Min

Max

Unit

t_TIMxCLK

Timer resolution time

f_TIMxCLK= 64 MHz

15.625

f_TIMxCLK/2

Timer external clock frequency

on CH1 to CH4

f_EXT

MHz

bit

f_TIMxCLK= 64 MHz

TIM1, TIM16, TIM17

Res_TIM

Timer resolution

TIM2

f_TIMxCLK= 64 MHz

65536

1024

t_TIMxCLK

µs

t_TIMxCLK

t_COUNTER

16-bit counter clock period

0.015625

65536 × 65536

67.10

Maximum possible count with

32-bit counter

t_{MAX_COUNT}

f_TIMxCLK= 64 MHz

1. TIMx_,is used as a general term in which x stands for 1, 2, 16 or 17.

142/165

DS11929 Rev 3

STM32WB55xx

Prescaler divider

Electrical characteristics

(1)

Table 87. IWDG min/max timeout period at 32 kHz (LSI1)

PR[2:0] bits

Min timeout RL[11:0] = 0x000

Max timeout RL[11:0] = 0xFFF Unit

0.125

0.250

0.500

1.0

512

1024

2048

/16

/32

/64

/128

/256

4096

8192

2.0

4.0

16384

32768

6 or 7

8.0

1. The exact timings still depend on the phasing of the APB interface clock vs. the LSI clock, hence there is always a full RC

period of uncertainty.

6.3.28

Communication interfaces characteristics

I²C interface characteristics

The I2C interface meets the timings requirements of the I C-bus specification and user

manual rev. 03 for:

•

Standard-mode (Sm): with a bit rate up to 100 kbit/s

Fast-mode (Fm): with a bit rate up to 400 kbit/s

Fast-mode Plus (Fm+): with a bit rate up to 1 Mbit/s.

Table 88. Minimum I2CCLK frequency in all I C modes

Symbol

Parameter

Condition

Min

Unit

Standard-mode

Fast-mode

Analog filter ON, DNF = 0

Analog filter OFF, DNF = 1

Analog filter ON, DNF = 0

Analog filter OFF, DNF = 1

I2CCLK

frequency

f_(I2CCLK)

MHz

Fast-mode Plus

The I2C timings requirements are guaranteed by design when the I2C peripheral is properly

configured (refer to the reference manual RM0434).

The SDA and SCL I/O requirements are met with the following restriction: the SDA and SCL

I/O pins are not “true” open-drain. When configured as open-drain, the PMOS connected

between the I/O pin and V is disabled, but is still present. The 20 mA output drive

requirement in Fast-mode Plus is supported partially.

This limits the maximum load C

supported in Fast-mode Plus, given by these formulas:

load

•

t (SDA/SCL) = 0.8473 x R x C

r p load

R (min) = [V - V (max)] / I (max)

where R is the I2C lines pull-up. Refer to Section 6.3.17: I/O port characteristics for the I2C

I/Os characteristics.

DS11929 Rev 3

143/165

152

Electrical characteristics

STM32WB55xx

All I2C SDA and SCL I/Os embed an analog filter. Refer to Table 89 for the analog filter

characteristics:

(1)

Table 89. I2C analog filter characteristics

Symbol

Parameter

Min

Max

110⁽³⁾

Unit

Maximum pulse width of spikes that

are suppressed by the analog filter

t_AF

50⁽²⁾

1. Guaranteed by design.

2. Spikes with widths below t_AF(min)are filtered.

3. Spikes with widths above t_AF(max)are not filtered

SPI characteristics

Unless otherwise specified, the parameters given in Table 90 for SPI are derived from tests

performed under the ambient temperature, f frequency and supply voltage conditions

PCLKx

summarized in Table 22: General operating conditions.

•

Output speed is set to OSPEEDRy[1:0] = 11

Capacitive load C = 30 pF

Measurement points are done at CMOS levels: 0.5 ₓ V

Refer to Section 6.3.17: I/O port characteristics for more details on the input/output alternate

function characteristics (NSS, SCK, MOSI, MISO for SPI).

(1)

Table 90. SPI characteristics

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

Master mode

1.65 < V_DD< 3.6 V

Voltage Range 1

Master transmitter mode

1.65 < V_DD< 3.6 V

Voltage Range 1

Slave receiver mode

1.65 < V_DD< 3.6 V

Voltage Range 1

f_SCK

1/t_c(SCK)

SPI clock frequency

MHz

Slave mode transmitter/full duplex

2.7 < V_DD< 3.6 V

32⁽²⁾

Voltage Range 1

Slave mode transmitter/full duplex

1.65 < V_DD< 3.6 V

20.5⁽²⁾

Voltage Range 1

Voltage Range 2

t_su(NSS)NSS setup time

t_h(NSS)NSS hold time

t_w(SCKH)

Slave mode, SPI prescaler = 2

4xT_PCLK

2xT_PCLK

SCK high and low time

Master mode

T_PCLK- 1.5

T_PCLK

T_PCLK+ 1

t_w(SCKL)

144/165

DS11929 Rev 3

STM32WB55xx

Electrical characteristics

(1)

Table 90. SPI characteristics (continued)

Symbol

Parameter

Conditions

Master mode

Min

Typ

Max

Unit

t_su(MI)

1.5

Data input setup time

Data input hold time

t_su(SI)

t_h(MI)

t_h(SI)

Slave mode

Master mode

Slave mode

t_a(SO)Data output access time

t_dis(SO)Data output disable time

Slave mode

Slave mode 2.7 < V_DD< 3.6 V

Voltage Range 1

14.5

15.5

19.5

15.5

Slave mode 1.65 < V_DD< 3.6 V

Voltage Range 1

t_v(SO)

Data output valid time

Slave mode 1.65 < V_DD< 3.6 V

Voltage Range 2

t_v(MO)

Master mode (after enable edge)

Slave mode (after enable edge)

Master mode (after enable edge)

2.5

t_h(SO)

Data output hold time

t_h(MO)

1. Guaranteed by characterization results.

2. Maximum frequency in Slave transmitter mode is determined by the sum of t_v(SO)and t_su(MI), which has to fit into SCK low

or high phase preceding the SCK sampling edge. This value can be achieved when the SPI communicates with a master

having t_su(MI)= 0 while Duty(SCK) = 50 %.

Figure 26. SPI timing diagram - slave mode and CPHA = 0

DS11929 Rev 3

145/165

152

Electrical characteristics

STM32WB55xx

Figure 27. SPI timing diagram - slave mode and CPHA = 1

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1. Measurement points are set at CMOS levels: 0.3 V_DDand 0.7 V_DD

Figure 28. SPI timing diagram - master mode

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1. Measurement points are set at CMOS levels: 0.3 V_DDand 0.7 V_DD

146/165

DS11929 Rev 3

STM32WB55xx

Electrical characteristics

Quad-SPI characteristics

Unless otherwise specified, the parameters given in Table 91 and Table 92 for Quad-SPI

are derived from tests performed under the ambient temperature, f frequency and V

AHB

supply voltage conditions summarized in Table 22: General operating conditions, with the

following configuration:

•

Output speed is set to OSPEEDRy[1:0] = 11

Capacitive load C = 15 or 20 pF

Measurement points are set at CMOS levels: 0.5 ₓ V

Refer to Section 6.3.17: I/O port characteristics for more details on the input/output alternate

function characteristics.

(1)

Table 91. Quad-SPI characteristics in SDR mode

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

1.65 < V_DD< 3.6 V, C_LOAD= 20 pF

Voltage Range 1

1.65 < V_DD< 3.6 V, C_LOAD= 15 pF

Voltage Range 1

F_CK

Quad-SPI clock

frequency

MHz

1/t_(CK)

2.7 < V_DD< 3.6 V, C_LOAD= 15 pF

Voltage Range 1

1.65 < V_DD< 3.6 V C_LOAD= 20 pF

Voltage Range 2

t_w(CKH)

t_w(CKL)

_(CK)/2 - 0.5

t_(CK)/2 + 1

Quad-SPI clock

high and low time

_AHBCLK= 48 MHz, presc=1

t_(CK)/2 - 1

t_(CK)/2 + 0.5

Voltage Range 1

Voltage Range 2

Voltage Range 1

Voltage Range 2

Voltage Range 1

Voltage Range 2

Voltage Range 1

Voltage Range 2

3.5

4.5

t_s(IN)

Data input setup time

Data input hold time

t_h(IN)

1.5

t_v(OUT)Data output valid time

t_h(OUT)Data output hold time

1. Guaranteed by characterization results.

DS11929 Rev 3

147/165

152

Electrical characteristics

STM32WB55xx

(1)

Table 92. Quad-SPI characteristics in DDR mode

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

1.65 < V_DD< 3.6 V, C_LOAD= 20 pF

Voltage Range 1

2.0 < V_DD< 3.6 V, C_LOAD= 20 pF

Voltage Range 1

F_CK

Quad-SPI clock

frequency

MHz

1/t_(CK)

1.65 < V_DD< 3.6 V, C_LOAD= 15 pF

Voltage Range 1

1.65 < V_DD< 3.6 V C_LOAD= 20 pF

Voltage Range 2

t_w(CKH)

_(CK)/2

t_(CK)/2 + 1

t_(CK)/2

Quad-SPI clock

high and low time

f_AHBCLK= 48 MHz, presc=0

t_w(CKL)

t_(CK)/2 - 1

Voltage Range 1

Voltage Range 2

Voltage Range 1

Voltage Range 2

Voltage Range 1

Voltage Range 2

Voltage Range 1

Voltage Range 2

2.5

3.5

2.5

1.5

5.5

6.5

Data input setup

time on rising edge

t_sr(IN)

t_sf(IN)

t_hr(IN)

t_hf(IN)

Data input setup

time on falling edge

Data input hold

time on rising edge

Data input hold

time on falling edge

DHHC=0

Voltage Range 1

5.5

Data output valid

time on rising edge

t_vr(OUT)

t_vf(OUT)

t_hr(OUT)

t_hf(OUT)

DHHC=1

t_(CK)/2 + 1 t_(CK)/2 + 1.5

Voltage Range 2

4.5

DHHC=0

Voltage Range 1

Data output valid

time on falling edge

DHHC=1

t_(CK)/2 + 1 t_(CK)/2 + 2

Voltage Range 2

7.5

DHHC=0

Voltage Range 1

Data output hold

time on rising edge

DHHC=1 t_(CK)/2 + 0.5

3.5

Voltage Range 2

Voltage Range 1

Voltage Range 2

DHHC=0

Data output hold

time on falling edge

DHHC=1 t_(CK)/2 + 0.5

1. Guaranteed by characterization results.

148/165

DS11929 Rev 3

STM32WB55xx

Electrical characteristics

Figure 29. Quad-SPI timing diagram - SDR mode

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SAI characteristics

Unless otherwise specified, the parameters given in Table 93 for SAI are derived

from tests performed under the ambient temperature, f_PCLKxfrequency and V_DD

supply voltage conditions summarized inTable 22: General operating conditions, with

the following configuration:

•

Output speed is set to OSPEEDRy[1:0] = 10

Capacitive load C = 30 pF

Measurement points are done at CMOS levels: 0.5 ₓ V

Refer to Section 6.3.17: I/O port characteristics for more details on the input/output

alternate function characteristics (CK,SD,FS).

DS11929 Rev 3

149/165

152

Electrical characteristics

STM32WB55xx

(1)

Table 93. SAI characteristics

Conditions

Symbol

Parameter

Min

Max Unit

f_MCLK

SAI main clock output

Master transmitter

2.7 V ≤ V_DD≤ 3.6 V

23.5

Voltage Range 1

Master transmitter

1.65 V ≤ V_DD≤ 3.6 V

Voltage Range 1

Master receiver

Voltage Range 1

MHz

f_CK

SAI clock frequency⁽²⁾Slave transmitter

2.7 V ≤ V_DD≤ 3.6 V

Voltage Range 1

Slave transmitter

1.65 V ≤ V_DD≤ 3.6 V

Voltage Range 1

Slave receiver

Voltage Range 1

Voltage Range 2

Master mode

2.7 V ≤ V_DD≤ 3.6 V

FS valid time

t_v(FS)

Master mode

1.65 V ≤ V_DD≤ 3.6 V

t_h(FS)

t_su(FS)

FS hold time

FS setup time

FS hold time

Master mode

Slave mode

1.5

2.5

t_h(FS)

Slave mode

t_{su(SD_A_MR)}

t_{su(SD_B_SR)}

t_{h(SD_A_MR)}

t_{h(SD_B_SR)}

Master receiver

Slave receiver

Master receiver

Slave receiver

Data input setup time

Data input hold time

1.5

6.5

2.5

Slave transmitter (after enable edge)

2.7 V ≤ V_DD≤ 3.6 V

t_{v(SD_B_ST)}Data output valid time

Slave transmitter (after enable edge)

1.65 V ≤ V_DD≤ 3.6 V

t_{h(SD_B_ST)}Data output hold time Slave transmitter (after enable edge)

Master transmitter (after enable edge)

18.5

2.7 V ≤ V_DD≤ 3.6 V

t_{v(SD_A_MT)}Data output valid time

Master transmitter (after enable edge)

1.65 V ≤ V_DD≤ 3.6 V

t_{h(SD_A_MT)}Data output hold time Master transmitter (after enable edge)

1. Guaranteed by characterization results.

2. APB clock frequency must be at least twice SAI clock frequency.

150/165

DS11929 Rev 3

STM32WB55xx

Electrical characteristics

Figure 31. SAI master timing waveforms

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Figure 32. SAI slave timing waveforms

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3!)?3#+?8

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DS11929 Rev 3

151/165

152

Electrical characteristics

STM32WB55xx

USB characteristics

The STM32WB55xx USB interface is fully compliant with the USB specification version 2.0,

and is USB-IF certified (for Full-speed device operation).

(1)

Table 94. USB electrical characteristics

Symbol

Parameter

Conditions

Min

Typ

Max Unit

V_DDUSBUSB transceiver operating voltage

3.0⁽²⁾

3.6

USB crystal-less

T_{crystal_less}

-15

°C

operation temperature

Embedded USB_DP pull-up value

during idle

R_PUI

900

1250 1600

Embedded USB_DP pull-up value

during reception

ꢀ

R_PUR

1400 2300 3200

28 36 44

(3)

Z_DRV

Output driver impedance⁽⁴⁾

Driving high and low

1. T_A= -40 to 125 °C unless otherwise specified.

2. The STM32WB55xx USB functionality is ensured down to 2.7 V, but the full USB electrical characteristics

are degraded in the 2.7 to 3.0 V voltage range.

3. Guaranteed by design.

4. No external termination series resistors are required on USB_DP (D+) and USB_DM (D-); the matching

impedance is already included in the embedded driver.

152/165

DS11929 Rev 3

STM32WB55xx

Package information

In order to meet environmental requirements, ST offers these devices in different grades of

ECOPACK packages, depending on their level of environmental compliance. ECOPACK

specifications, grade definitions and product status are available at: www.st.com.

ECOPACK is an ST trademark.

7.1

7.2

WLCSP100 package information

For information on WLCSP100 package contact your local STMicroelectronics sales office.

VFQFPN68 package information

Figure 33. VFQFPN68, 8 x 8 mm, 0.4 mm pitch, very thin fine pitch quad flat

package outline

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1. VFQFPN stands for Thermally Enhanced Very thin Fine pitch Quad Flat Packages No lead. Sawed

version. Very thin profile: 0.80 < A ≤ 1.00 mm.

2. The pin #1 identifier must be existed on the top surface of the package by using indentation mark or other

feature of package body. Exact shape and size of this feature is optional.

DS11929 Rev 3

153/165

160

Package information

STM32WB55xx

Table 95. VFQFPN68, 8 x 8 mm, 0.4 mm pitch, very thin fine pitch quad flat

mechanical data

millimeters

inches⁽¹⁾

Symbol

Min

Typ

Max

Min

Typ

Max

0.80

0.90

0.02

0.20

8.00

6.40

8.00

6.40

0.40

0.50

1.00

0.05

0.0315

0.0354

0.0008

0.0079

0.3150

0.2520

0.3150

0.2520

0.0157

0.0197

0.0394

0.0020

0.15

7.85

6.30

7.85

6.30

0.25

8.15

6.50

8.15

6.50

0.0059

0.3091

0.2480

0.3091

0.2480

0.0098

0.3209

0.2559

0.3209

0.2559

0.40

0.60

0.08

0.0157

0.0236

0.0031

ddd

1. Values in inches are converted from mm and rounded to 4 decimal digits.

Figure 34. VFQFPN68, 8 x 8 mm, 0.4 mm pitch, very thin fine pitch quad flat

recommended footprint

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1. Dimensions are expressed in millimeters.

154/165

DS11929 Rev 3

STM32WB55xx

Package information

7.3

UFQFPN48 package information

Figure 35. UFQFPN48 - 48-lead, 7 x 7 mm, 0.5 mm pitch, ultra thin fine pitch quad flat

package outline

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1. Drawing is not to scale.

2. All leads/pads should also be soldered to the PCB to improve the lead/pad solder joint life.

3. There is an exposed die pad on the underside of the UFQFPN package, it must be electrically connected to

the PCB ground.

DS11929 Rev 3

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160

Package information

STM32WB55xx

Table 96. UFQFPN48 - 48-lead, 7 x 7 mm, 0.5 mm pitch, ultra thin fine pitch quad flat

package mechanical data

millimeters

Typ

inches⁽¹⁾

Symbol

Min

Max

Min

Typ

Max

0.500

0.000

6.900

5.500

0.300

0.550

0.020

7.000

5.600

0.400

0.152

0.250

0.500

0.600

0.050

7.100

5.700

0.500

0.0197

0.0000

0.2717

0.2165

0.0118

0.0217

0.0008

0.2756

0.2205

0.0157

0.0060

0.0098

0.0197

0.0236

0.0020

0.2795

0.2244

0.0197

0.200

0.300

0.0079

0.0118

ddd

0.080

0.0031

1. Values in inches are converted from mm and rounded to 4 decimal digits.

Figure 36. UFQFPN48 - 48-lead, 7 x 7 mm, 0.5 mm pitch, ultra thin fine pitch quad flat

package recommended footprint

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1. Dimensions are expressed in millimeters.

156/165

DS11929 Rev 3

STM32WB55xx

Package information

Device marking for UFQFPN48

The following figure gives an example of topside marking orientation versus pin 1 identifier

location.

The printed markings may differ depending on the supply chain.

Other optional marking or inset/upset marks, which identify the parts throughout supply

chain operations, are not indicated below.

Figure 37. UFQFPN48 marking example (package top view)

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1. Parts marked as “ES”, “E” or accompanied by an Engineering Sample notification letter, are not yet

qualified and therefore not yet ready to be used in production and any consequences deriving from such

usage will not be at ST charge. In no event, ST will be liable for any customer usage of these engineering

samples in production. ST Quality has to be contacted prior to any decision to use these Engineering

samples to run qualification activity.

DS11929 Rev 3

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Package information

STM32WB55xx

7.4

Thermal characteristics

The maximum chip junction temperature (T max) must never exceed the values given in

Table 22: General operating conditions.

The maximum chip-junction temperature, T max, in degrees Celsius, can be calculated

using the equation:

T max = T max + (P max x Θ )

where:

•

T max is the maximum ambient temperature in °C,

is the package junction-to-ambient thermal resistance, in °C/W,

P max is the sum of P

max and P max (P max = P

max + P max),

INT I/O

INT

I/O

max is the product of I and V , expressed in Watt. This is the maximum chip

DD DD

INT

internal power.

max represents the maximum power dissipation on output pins:

I/O

•

max = Σ (V × I ) + Σ ((V – V ) × I

)

I/O

taking into account the actual V / I and V / I of the I/Os at low and high level in the

OL OL

OH OH

application.

Note:

When the SMPS is used, a portion of the power consumption is dissipated into the external

inductor, therefore reducing the chip power dissipation. This portion depends mainly on the

inductor ESR characteristics.

Note:

As the radiated RF power is quite low (< 4 mW), it is not necessary to remove it from the

chip power consumption.

RF characteristics (such as sensitivity, Tx power, consumption) are provided up to 85 °C.

Table 97. Package thermal characteristics

Symbol

Parameter

Value

Unit

Thermal resistance junction-ambient

UFQFPN48 - 7 mm x 7 mm

Thermal resistance junction-ambient

Θ_JA

°C/W

VFQFPN68 - 8 mm x 8 mm

Thermal resistance junction-ambient

WLCSP100 - 0.4 mm pitch

7.4.1

7.4.2

Reference document

JESD51-2 Integrated Circuits Thermal Test Method Environment Conditions - Natural

Convection (Still Air). Available from www.jedec.org

Selecting the product temperature range

When ordering the microcontroller, the temperature range is specified in the ordering

information scheme shown in Section 8.

Each temperature range suffix corresponds to a specific guaranteed ambient temperature at

maximum dissipation and, to a specific maximum junction temperature.

158/165

DS11929 Rev 3

STM32WB55xx

Package information

As applications do not commonly use the STM32WB55xx at maximum dissipation, it is

useful to calculate the exact power consumption and junction temperature to determine

which temperature range will be best suited to the application.

The following examples show how to calculate the temperature range needed for a given

application.

Example 1: High-performance application

Assuming the following application conditions:

Maximum ambient temperature T

= 82 °C (measured according to JESD51-2),

Amax

= 50 mA, V = 3.5 V, maximum 20 I/Os used at the same time in output at low

DDmax

level with I = 8 mA, V = 0.4 V and maximum 8 I/Os used at the same time in output

at low level with I = 20 mA, V = 1.3 V

= 50 mA × 3.5 V= 175 mW

INTmax

= 20 × 8 mA × 0.4 V + 8 × 20 mA × 1.3 V = 272 mW

IOmax

This gives: P

= 175 mW and P

= 272 mW:

IOmax

INTmax

= 175 + 272 = 447 mW

Dmax

Using the values obtained in Table 97 T

is calculated as follows:

Jmax

–

For VFQFPN68, 47 °C/W

= 82 °C + (47 °C/W × 447 mW) = 82 °C + 21 °C = 103 °C

Jmax

This is within the range of the suffix 6 version parts (–40 < T < 105 °C), see Section 8.

In this case, parts must be ordered at least with the temperature range suffix 6 (see

Section 8).

Note:

With this given P

user can find the T

allowed for a given device temperature range

Dmax

Amax

(order code suffix 7).

Suffix 7: T = T

- (47°C/W × 447 mW) = 125°C -21°C = 104 °C

Jmax

Amax

Example 2: High-temperature application

Using the same rules, it is possible to address applications that run at high ambient

temperatures with a low dissipation, as long as junction temperature T remains within the

specified range.

Assuming the following application conditions:

Maximum ambient temperature T

= 100 °C (measured according to JESD51-2),

Amax

= 20 mA, V = 3.5 V, maximum 20 I/Os used at the same time in output at low

DDmax

level with I = 8 mA, V = 0.4 V

= 20 mA × 3.5 V= 70 mW

INTmax

= 20 × 8 mA × 0.4 V = 64 mW

IOmax

This gives: P

= 70 mW and P

= 64 mW:

IOmax

INTmax

= 70 + 64 = 134 mW

Dmax

Thus: P

= 134 mW

Dmax

Using the values obtained in Table 97 T

is calculated as follows:

Jmax

–

For UFQFPN48, 51°C/W

= 100 °C + (51 °C/W × 134 mW) = 100 °C + 7 °C = 107 °C

Jmax

This is above the range of the suffix 6 version parts (–40 < T < 105 °C).

DS11929 Rev 3

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Package information

STM32WB55xx

In this case, parts must be ordered at least with the temperature range suffix 7 (see

Section 8), unless user reduces the power dissipation to be able to use suffix 6 parts.

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Ordering information

Table 98. STM32WB55xx ordering information scheme

STM32 WB 55

Example:

Device family

STM32 = Arm based 32-bit microcontroller

Product type

WB = Wireless Bluetooth

Device subfamily

55 = Die 5, full set of features

Pin count

C = 48 pins

R = 68 pins

V = 100 pins

Flash memory size

C = 256 KB

E = 512 KB

G = 1 MB

Package

U = UFQFPN48 7 mm x 7 mm

V = VFQFPN68 8 mm x 8 mm

Y = WLCSP100 0.4 mm pitch

Temperature range

6 = Industrial temperature range, -40 to 85 °C (105 °C junction)

7 = Industrial temperature range, -40 to 105 °C (125 °C junction)

Packing

TR = tape and reel

xxx = programmed parts

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Revision history

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Revision history

Table 99. Document revision history

Changes

Date

Revision

25-Jul-2017

Initial release.

Updated document title, Features, Section 1: Introduction, Section 2:

Description, Section 3.1: Architecture, Section 3.3.2: Memory protection

unit, Section 3.3.3: Embedded Flash memory, Section 3.4: Security and

safety, Section 3.6: RF subsystem, Section 3.6.1: RF front-end block

diagram, Section 3.6.2: BLE general description, Section 3.7.1: Power

supply distribution, Section 3.7.2: Power supply schemes, Section 3.7.4:

Power supply supervisor, Section 3.10: Clocks and startup, Section 3.14:

Analog to digital converter (ADC), Section 3.19: True random number

generator (RNG), Section 5: Memory mapping, Section 6.3.25: SMPS

step-down converter characteristics and Section 7.4.2: Selecting the

product temperature range.

Updated Table 2: STM32WB55xx family device features and peripheral

counts, Table 6: Power supply typical components, Table 7: Features over

all modes, Table 8: STM32WB55xx modes overview, Table 13: Timer

features, Table 15: Legend/abbreviations used in the pinout table,

Table 16: STM32WB55xx pin and ball definitions, Table 17: Alternate

functions, Table 23: RF transmitter BLE characteristics, Table 26: RF

receiver BLE characteristics (1 Mbps) and added footnote to it, Table 28:

RF BLE power consumption for VDD = 3.3 V, Table 31: RF 802.15.4

power consumption for VDD = 3.3 V, Table 37: Typical current

04-Apr-2018

consumption in Run and Low-power run modes, with different codes

running from Flash, ART enable (Cache ON Prefetch OFF), VDD= 3.3 V,

Table 38: Typical current consumption in Run and Low-power run modes,

with different codes running from SRAM1, VDD = 3.3 V, Table 40: Current

consumption in Low-power sleep modes, Flash memory in Power down,

Table 41: Current consumption in Stop 2 mode, Table 42: Current

consumption in Stop 1 mode, Table 43: Current consumption in Stop 0

mode, Table 44: Current consumption in Standby mode, Table 45: Current

consumption in Shutdown mode, Table 48: Peripheral current

consumption, Table 97: Package thermal characteristics and Table 98:

STM32WB55xx ordering information scheme.

Added Table 47: Current under Reset condition.

Updated Figure 1: STM32WB55xx block diagram, Figure 2:

STM32WB55xx RF front-end block diagram, Figure 4: Power distribution,

Figure 6: Power supply overview, Figure 7: Clock tree, Figure 8:

STM32WB55xxCx UFQFPN48 pinout(1)(2), Figure 9: STM32WB55xxRx

VFQFPN68 pinout(1)(2), Figure 10: STM32WB55xxVx WLCSP100

ballout(1) and Figure 13: Power supply scheme.

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Revision history

Table 99. Document revision history (continued)

Date

Revision

Changes

Changed document classification to Public.

Updated Features, Section 3.6.2: BLE general description, Section 3.7.2:

Power supply schemes, Section 3.7.3: Linear voltage regulator,

Section 3.10: Clocks and startup, Section 6.3.10: External clock source

characteristics, Section 6.3.20: Analog-to-Digital converter

characteristics, Section 6.3.28: Communication interfaces characteristics,

Section 7.1: WLCSP100 package information and Section 7.4: Thermal

characteristics.

Replaced V_DDIOxwith V_DDthroughout the whole document.

Updated Table 5: Typical external components, footnote 2 of Table 7:

Features over all modes, Table 8: STM32WB55xx modes overview and its

footnote 5, Table 12: Internal voltage reference calibration values,

Table 16: STM32WB55xx pin and ball definitions and its footnote 5,

Table 17: Alternate functions, Table 20: Thermal characteristics, Table 21:

Main performance at VDD = 3.3 V, Table 21: Main performance at VDD =

3.3 V, Table 22: General operating conditions, Table 23: RF transmitter

BLE characteristics and its footnote, Table 26: RF receiver BLE

characteristics (1 Mbps), Table 28: RF BLE power consumption for VDD =

3.3 V, Table 29: RF transmitter 802.15.4 characteristics and its footnote 1,

Table 30: RF receiver 802.15.4 characteristics, Table 31: RF 802.15.4

power consumption for VDD = 3.3 V, Table 34: Embedded internal

voltage reference, Table 35: Current consumption in Run and Low-power

run modes, code with data processing running from Flash, ART enable

(Cache ON Prefetch OFF), VDD = 3.3 V, Table 36: Current consumption

in Run and Low-power run modes, code with data processing running

from SRAM1, VDD = 3.3 V, Table 37: Typical current consumption in Run

and Low-power run modes, with different codes running from Flash, ART

enable (Cache ON Prefetch OFF), VDD= 3.3 V, Table 38: Typical current

consumption in Run and Low-power run modes, with different codes

running from SRAM1, VDD = 3.3 V, Table 39: Current consumption in

Sleep and Low-power sleep modes, Flash memory ON, Table 40: Current

consumption in Low-power sleep modes, Flash memory in Power down,

Table 41: Current consumption in Stop 2 mode, Table 42: Current

consumption in Stop 1 mode, Table 43: Current consumption in Stop 0

mode, Table 44: Current consumption in Standby mode, Table 45: Current

consumption in Shutdown mode, Table 46: Current consumption in VBAT

mode, Table 47: Current under Reset condition, Table 48: Peripheral

current consumption, Table 49: Low-power mode wakeup timings,

Table 50: Regulator modes transition times, Table 51: Wakeup time using

LPUART, Table 53: HSE oscillator characteristics and added footnote to

it, Table 59: LSI2 oscillator characteristics, Table 61: Flash memory

characteristics, Table 63: EMS characteristics, Table 65: ESD absolute

maximum ratings, Table 67: I/O current injection susceptibility, Table 68:

I/O static characteristics and its footnotes, Table 69: Output voltage

characteristics, Table 70: I/O AC characteristics and its footnotes 1 and 2,

Table 71: NRST pin characteristics, Table 75: ADC accuracy - Limited test

conditions 1, Table 76: ADC accuracy - Limited test conditions 2,

Table 76: ADC accuracy - Limited test conditions 2, Table 77: ADC

accuracy - Limited test conditions 3, Table 80: COMP characteristics,

Table 89: I2C analog filter characteristics, Table 90: SPI characteristics,

Table 91: Quad-SPI characteristics in SDR mode, Table 92: Quad-SPI

characteristics in DDR mode and Table 93: SAI characteristics.

08-Oct-2018

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Revision history

STM32WB55xx

Table 99. Document revision history (continued)

Revision Changes

Date

Updated Figure 2: STM32WB55xx RF front-end block diagram, Figure 13:

Power supply scheme, Figure 16: Typical energy detection (T = 27°C,

VDD = 3.3 V) and Figure 22: I/O input characteristics.

Added Figure 5: Power-up/down sequence, Figure 15: Typical link quality

indicator code vs. Rx level and Figure 16: Typical energy detection (T =

27°C, VDD = 3.3 V).

08-Oct-2018

Added Table 24: RF transmitter BLE characteristics (1 Mbps), Table 25:

RF transmitter BLE characteristics (2 Mbps), Table 27: RF receiver BLE

characteristics (2 Mbps), Table 52: HSE crystal requirements and

Table 88: Minimum I2CCLK frequency in all I2C modes.

(cont’d)

Added Device marking for UFQFPN48.

Removed former Figure 22: I/O AC characteristics definition⁽¹⁾and

Figure 27: SMPS efficiency - VDDSMPS = 3.6 V.

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STM32WB55xx

IMPORTANT NOTICE – PLEASE READ CAREFULLY

STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and

improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on

ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order

acknowledgement.

Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or

the design of Purchasers’ products.

No license, express or implied, to any intellectual property right is granted by ST herein.

Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product.

ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners.

Information in this document supersedes and replaces information previously supplied in any prior versions of this document.

DS11929 Rev 3

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165

STM32WB35CC [STMICROELECTRONICS]

相关型号：

STM32WB35CCQ6ATR

STM32WB35CCQ6AXXX

STM32WB35CCQ6TR

STM32WB35CCQ6XXX

STM32WB35CCQ7ATR

STM32WB35CCQ7AXXX

STM32WB35CCQ7TR

STM32WB35CCQ7XXX

STM32WB35CCU6ATR

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