STM32WB55RGV7XXX [STMICROELECTRONICS]

Multiprotocol wireless 32-bit MCU Arm®-based Cortex®-M4 with FPU, Bluetooth® 5 and 802.15.4 radio solution;
STM32WB55RGV7XXX
型号: STM32WB55RGV7XXX
厂家: ST    ST
描述:

Multiprotocol wireless 32-bit MCU Arm®-based Cortex®-M4 with FPU, Bluetooth® 5 and 802.15.4 radio solution

文件: 总193页 (文件大小:3079K)
中文:  中文翻译
下载:  下载PDF数据表文档文件
STM32WB55xx  
STM32WB35xx  
Multiprotocol wireless 32-bit MCU Arm®-based Cortex®-M4  
with FPU, Bluetooth® 5 and 802.15.4 radio solution  
Datasheet - production data  
Features  
.
Includes ST state-of-the-art patented  
technology  
Radio  
UFQFPN48  
7 x 7 mm solder pad  
VFQFPN68  
8 x 8 mm solder pad  
– 2.4 GHz  
®
– RF transceiver supporting Bluetooth 5  
specification, IEEE 802.15.4-2011 PHY  
and MAC, supporting Thread and   
FBGA  
®
Zigbee 3.0  
®
– RX sensitivity: -96 dBm (Bluetooth Low  
WLCSP100  
0.4 mm pitch  
UFBGA129  
0.5 mm pitch  
Energy at 1 Mbps), -100 dBm (802.15.4)  
– Programmable output power up to +6 dBm  
with 1 dB steps  
®
®
Core: Arm 32-bit Cortex -M4 CPU with FPU,  
adaptive real-time accelerator (ART  
– Integrated balun to reduce BOM  
– Support for 2 Mbps  
Accelerator) allowing 0-wait-state execution  
from Flash memory, frequency up to 64 MHz,  
MPU, 80 DMIPS and DSP instructions  
®
®
– Dedicated Arm 32-bit Cortex M0+ CPU  
for real-time Radio layer  
Performance benchmark  
– Accurate RSSI to enable power control  
– 1.25 DMIPS/MHz (Drystone 2.1)  
– Suitable for systems requiring compliance  
with radio frequency regulations ETSI EN  
300 328, EN 300 440, FCC CFR47 Part 15  
and ARIB STD-T66  
®
– 219.48 CoreMark (3.43 CoreMark/MHz at  
64 MHz)  
Energy benckmark  
– 303 ULPMark™ CP score  
– Support for external PA  
– Available integrated passive device (IPD)  
companion chip for optimized matching  
solution (MLPF-WB55-01E3 or   
MLPF-WB55-02E3)  
Supply and reset management  
– High efficiency embedded SMPS   
step-down converter with intelligent bypass  
mode  
Ultra-low-power platform  
– Ultra-safe, low-power BOR (brownout  
reset) with five selectable thresholds  
– 1.71 to 3.6 V power supply  
– – 40 °C to 85 / 105 °C temperature ranges  
– 13 nA shutdown mode  
– Ultra-low-power POR/PDR  
– Programmable voltage detector (PVD)  
– V  
mode with RTC and backup registers  
– 600 nA Standby mode + RTC + 32 KB  
RAM  
BAT  
Clock sources  
– 2.1 µA Stop mode + RTC + 256 KB RAM  
– 32 MHz crystal oscillator with integrated  
trimming capacitors (Radio and CPU clock)  
– Active-mode MCU: < 53 µA / MHz when RF  
and SMPS on  
– 32 kHz crystal oscillator for RTC (LSE)  
– Radio: Rx 4.5 mA / Tx at 0 dBm 5.2 mA  
– Internal low-power 32 kHz (±5%) RC (LSI1)  
– Internal low-power 32 kHz (stability  
±500 ppm) RC (LSI2)  
November 2020  
DS11929 Rev 10  
1/193  
This is information on a product in full production.  
www.st.com  
 
STM32WB55xx STM32WB35xx  
– Internal multispeed 100 kHz to 48 MHz  
oscillator, auto-trimmed by LSE (better than  
±0.25% accuracy)  
– 1x USB 2.0 FS device, crystal-less, BCD  
and LPM  
Touch sensing controller, up to 18 sensors  
– LCD 8x40 with step-up converter  
– 1x 16-bit, four channels advanced timer  
– 2x 16-bit, two channels timer  
– 1x 32-bit, four channels timer  
– 2x 16-bit ultra-low-power timer  
– 1x independent Systick  
– High speed internal 16 MHz factory  
trimmed RC (±1%)  
– 2x PLL for system clock, USB, SAI and  
ADC  
Memories  
– Up to 1 MB Flash memory with sector  
protection (PCROP) against R/W  
– 1x independent watchdog  
®
operations, enabling authentic Bluetooth  
– 1x window watchdog  
Low Energy and 802.15.4 SW stack  
Security and ID  
– Up to 256 KB SRAM, including 64 KB with  
hardware parity check  
– Secure firmware installation (SFI) for  
®
Bluetooth Low Energy and 802.15.4 SW  
– 20x32-bit backup register  
stack  
– Boot loader supporting USART, SPI, I2C  
and USB interfaces  
– 3x hardware encryption AES maximum  
®
®
256-bit for the application, the Bluetooth  
Low Energy and IEEE802.15.4  
– OTA (over the air) Bluetooth Low Energy  
and 802.15.4 update  
– Customer key storage / key manager  
services  
– Quad SPI memory interface with XIP  
– 1 Kbyte (128 double words) OTP  
– HW public key authority (PKA)  
Rich analog peripherals (down to 1.62 V)  
– Cryptographic algorithms: RSA,   
– 12-bit ADC 4.26 Msps, up to 16-bit with  
hardware oversampling, 200 µA/Msps  
Diffie-Helman, ECC over GF(p)  
– True random number generator (RNG)  
– 2x ultra-low-power comparator  
– Sector protection against R/W operation  
(PCROP)  
– Accurate 2.5 V or 2.048 V reference  
voltage buffered output  
– CRC calculation unit  
System peripherals  
– Die information: 96-bit unique ID  
– IEEE 64-bit unique ID. Possibility to derive  
– Inter processor communication controller  
®
(IPCC) for communication with Bluetooth  
Low Energy and 802.15.4  
®
802.15.4 64-bit and Bluetooth Low Energy  
48-bit EUI  
– HW semaphores for resources sharing  
between CPUs  
Up to 72 fast I/Os, 70 of them 5 V-tolerant  
Development support  
– 2x DMA controllers (7x channels each)  
supporting ADC, SPI, I2C, USART, QSPI,  
SAI, AES, timers  
– Serial wire debug (SWD), JTAG for the  
application processor  
– Application cross trigger with input / output  
– 1x USART (ISO 7816, IrDA, SPI Master,  
Modbus and Smartcard mode)  
– Embedded Trace Macrocell™ for  
application  
– 1x LPUART (low power)  
– 2x SPI 32 Mbit/s  
All packages are ECOPACK2 compliant  
– 2x I2C (SMBus/PMBus)  
– 1x SAI (dual channel high quality audio)  
Table 1. Device summary  
Part numbers  
Reference  
STM32WB55CC, STM32WB55CE, STM32WB55CG, STM32WB55RC, STM32WB55RE, STM32WB55RG,  
STM32WB55VC, STM32WB55VE, STM32WB55VG, STM32WB55VY  
STM32WB55xx  
STM32WB35xx  
STM32WB35CC, STM32WB35CE  
2/193  
DS11929 Rev 10  
 
 
STM32WB55xx STM32WB35xx  
Contents  
Contents  
1
2
3
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12  
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13  
Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18  
3.1  
3.2  
3.3  
Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18  
Arm® Cortex®-M4 core with FPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18  
Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19  
3.3.1  
3.3.2  
3.3.3  
3.3.4  
Adaptive real-time memory accelerator (ART Accelerator) . . . . . . . . . . 19  
Memory protection unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19  
Embedded Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19  
Embedded SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21  
3.4  
3.5  
3.6  
Security and safety . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21  
Boot modes and FW update . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22  
RF subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22  
3.6.1  
3.6.2  
3.6.3  
3.6.4  
3.6.5  
RF front-end block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22  
BLE general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23  
802.15.4 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25  
RF pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25  
Typical RF application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25  
3.7  
Power supply management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26  
3.7.1  
3.7.2  
3.7.3  
3.7.4  
3.7.5  
3.7.6  
Power supply distribution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26  
Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27  
Linear voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31  
Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31  
Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31  
Reset mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39  
3.8  
3.9  
VBAT operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39  
Interconnect matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39  
3.10 Clocks and startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41  
3.11 General-purpose inputs/outputs (GPIOs) . . . . . . . . . . . . . . . . . . . . . . . . . 43  
3.12 Direct memory access controller (DMA) . . . . . . . . . . . . . . . . . . . . . . . . . . 44  
3.13 Interrupts and events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44  
DS11929 Rev 10  
3/193  
6
Contents  
STM32WB55xx STM32WB35xx  
3.13.1 Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . 44  
3.13.2 Extended interrupts and events controller (EXTI) . . . . . . . . . . . . . . . . . 45  
3.14 Analog to digital converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45  
3.14.1 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46  
3.14.2 Internal voltage reference (VREFINT) . . . . . . . . . . . . . . . . . . . . . . . . . . 46  
3.15 Voltage reference buffer (VREFBUF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47  
3.16 Comparators (COMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47  
3.17 Touch sensing controller (TSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47  
3.18 Liquid crystal display controller (LCD) . . . . . . . . . . . . . . . . . . . . . . . . . . . 49  
3.19 True random number generator (RNG) . . . . . . . . . . . . . . . . . . . . . . . . . . 49  
3.20 Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50  
3.20.1 Advanced-control timer (TIM1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50  
3.20.2 General-purpose timers (TIM2, TIM16, TIM17) . . . . . . . . . . . . . . . . . . . 50  
3.20.3 Low-power timer (LPTIM1 and LPTIM2) . . . . . . . . . . . . . . . . . . . . . . . . 51  
3.20.4 Independent watchdog (IWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51  
3.20.5 System window watchdog (WWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . 52  
3.20.6 SysTick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52  
3.21 Real-time clock (RTC) and backup registers . . . . . . . . . . . . . . . . . . . . . . 52  
3.22 Inter-integrated circuit interface (I2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53  
3.23 Universal synchronous/asynchronous receiver transmitter (USART) . . . 54  
3.24 Low-power universal asynchronous receiver transmitter (LPUART) . . . . 54  
3.25 Serial peripheral interface (SPI1, SPI2) . . . . . . . . . . . . . . . . . . . . . . . . . . 55  
3.26 Serial audio interfaces (SAI1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55  
3.27 Quad-SPI memory interface (QUADSPI) . . . . . . . . . . . . . . . . . . . . . . . . . 56  
3.28 Development support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57  
3.28.1 Serial wire JTAG debug port (SWJ-DP) . . . . . . . . . . . . . . . . . . . . . . . . . 57  
3.28.2 Embedded Trace Macrocell™ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57  
4
5
6
Pinouts and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58  
Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80  
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81  
6.1  
Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81  
6.1.1  
Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81  
4/193  
DS11929 Rev 10  
STM32WB55xx STM32WB35xx  
Contents  
6.1.2  
6.1.3  
6.1.4  
6.1.5  
6.1.6  
6.1.7  
Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81  
Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81  
Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81  
Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81  
Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82  
Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 84  
6.2  
6.3  
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84  
Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87  
6.3.1  
6.3.2  
6.3.3  
6.3.4  
6.3.5  
6.3.6  
6.3.7  
6.3.8  
6.3.9  
Summary of main performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87  
General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87  
RF BLE characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88  
RF 802.15.4 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93  
Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . 96  
Embedded reset and power control block characteristics . . . . . . . . . . . 96  
Embedded voltage reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98  
Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99  
Wakeup time from Low-power modes and voltage scaling  
transition times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117  
6.3.10 External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 119  
6.3.11 Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 122  
6.3.12 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129  
6.3.13 Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130  
6.3.14 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131  
6.3.15 Electrical sensitivity characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 132  
6.3.16 I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 133  
6.3.17 I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134  
6.3.18 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137  
6.3.19 Analog switches booster . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139  
6.3.20 Analog-to-Digital converter characteristics . . . . . . . . . . . . . . . . . . . . . 140  
6.3.21 Voltage reference buffer characteristics . . . . . . . . . . . . . . . . . . . . . . . 152  
6.3.22 Comparator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154  
6.3.23 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 155  
6.3.24  
V
monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155  
BAT  
6.3.25 SMPS step-down converter characteristics . . . . . . . . . . . . . . . . . . . . . 156  
6.3.26 LCD controller characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156  
6.3.27 Timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157  
6.3.28 Clock recovery system (CRS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158  
DS11929 Rev 10  
5/193  
6
Contents  
STM32WB55xx STM32WB35xx  
6.3.29 Communication interfaces characteristics . . . . . . . . . . . . . . . . . . . . . . 158  
Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170  
7
7.1  
7.2  
7.3  
7.4  
7.5  
UFBGA129 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170  
WLCSP100 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173  
VFQFPN68 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177  
UFQFPN48 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180  
Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183  
7.5.1  
7.5.2  
Reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184  
Selecting the product temperature range . . . . . . . . . . . . . . . . . . . . . . 184  
8
9
Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186  
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187  
6/193  
DS11929 Rev 10  
STM32WB55xx STM32WB35xx  
List of tables  
List of tables  
Table 1.  
Table 2.  
Table 3.  
Table 4.  
Table 5.  
Table 6.  
Table 7.  
Table 8.  
Device summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2  
STM32WB55xx and STM32WB35xx devices features and peripheral counts . . . . . . . . . . 14  
Access status vs. readout protection level and execution modes . . . . . . . . . . . . . . . . . . . 20  
RF pin list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25  
Typical external components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26  
Power supply typical components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27  
Features over all modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33  
STM32WB55xx and STM32WB35xx modes overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . 37  
STM32WB55xx and STM32WB35xx CPU1 peripherals interconnect matrix . . . . . . . . . . . 39  
DMA implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44  
Temperature sensor calibration values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46  
Internal voltage reference calibration values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46  
Timer features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50  
I2C implementation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53  
Legend/abbreviations used in the pinout table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60  
STM32WB55xx pin and ball definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61  
STM32WB35xx pin and ball definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70  
Alternate functions (STM32WB55xx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73  
Alternate functions (STM32WB35xx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78  
Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85  
Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85  
Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86  
Main performance at VDD = 3.3 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87  
General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87  
RF transmitter BLE characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88  
RF transmitter BLE characteristics (1 Mbps) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89  
RF transmitter BLE characteristics (2 Mbps) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90  
RF receiver BLE characteristics (1 Mbps) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91  
RF receiver BLE characteristics (2 Mbps) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92  
RF BLE power consumption for VDD = 3.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93  
RF transmitter 802.15.4 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93  
RF receiver 802.15.4 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94  
RF 802.15.4 power consumption for VDD = 3.3 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95  
Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96  
Embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 96  
Embedded internal voltage reference. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98  
Current consumption in Run and Low-power run modes, code with data processing  
running from Flash, ART enable (Cache ON Prefetch OFF), VDD = 3.3 V . . . . . . . . . . . 100  
Current consumption in Run and Low-power run modes, code with data processing  
running from SRAM1, VDD = 3.3 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101  
Typical current consumption in Run and Low-power run modes, with different codes  
running from Flash, ART enable (Cache ON Prefetch OFF), VDD= 3.3 V. . . . . . . . . . . . 102  
Typical current consumption in Run and Low-power run modes,  
Table 9.  
Table 10.  
Table 11.  
Table 12.  
Table 13.  
Table 14.  
Table 15.  
Table 16.  
Table 17.  
Table 18.  
Table 19.  
Table 20.  
Table 21.  
Table 22.  
Table 23.  
Table 24.  
Table 25.  
Table 26.  
Table 27.  
Table 28.  
Table 29.  
Table 30.  
Table 31.  
Table 32.  
Table 33.  
Table 34.  
Table 35.  
Table 36.  
Table 37.  
Table 38.  
Table 39.  
Table 40.  
with different codes running from SRAM1, VDD = 3.3 V . . . . . . . . . . . . . . . . . . . . . . . . . 103  
Current consumption in Sleep and Low-power sleep modes, Flash memory ON . . . . . . 104  
Current consumption in Low-power sleep modes, Flash memory in Power down . . . . . . 104  
Current consumption in Stop 2 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105  
Current consumption in Stop 1 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107  
Table 41.  
Table 42.  
Table 43.  
Table 44.  
DS11929 Rev 10  
7/193  
9
List of tables  
STM32WB55xx STM32WB35xx  
Table 45.  
Table 46.  
Table 47.  
Table 48.  
Table 49.  
Table 50.  
Table 51.  
Table 52.  
Table 53.  
Table 54.  
Table 55.  
Table 56.  
Table 57.  
Table 58.  
Table 59.  
Table 60.  
Table 61.  
Table 62.  
Table 63.  
Table 64.  
Table 65.  
Table 66.  
Table 67.  
Table 68.  
Table 69.  
Table 70.  
Table 71.  
Table 72.  
Table 73.  
Table 74.  
Table 75.  
Table 76.  
Table 77.  
Table 78.  
Table 79.  
Table 80.  
Table 81.  
Table 82.  
Table 83.  
Table 84.  
Table 85.  
Table 86.  
Table 87.  
Table 88.  
Table 89.  
Table 90.  
Table 91.  
Table 92.  
Table 93.  
Table 94.  
Table 95.  
Table 96.  
Current consumption in Stop 0 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109  
Current consumption in Standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110  
Current consumption in Shutdown mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112  
Current consumption in VBAT mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112  
Current under Reset condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113  
Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115  
Low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117  
Regulator modes transition times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118  
Wakeup time using LPUART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118  
HSE crystal requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119  
HSE clock source requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119  
HSE oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120  
Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120  
Low-speed external user clock characteristics – Bypass mode . . . . . . . . . . . . . . . . . . . . 121  
HSI16 oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122  
MSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .124  
HSI48 oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127  
LSI1 oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128  
LSI2 oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129  
PLL, PLLSAI1 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129  
Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130  
Flash memory endurance and data retention. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130  
EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131  
EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132  
ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132  
Electrical sensitivity. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133  
I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133  
I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134  
Output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136  
I/O AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136  
NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138  
Analog switches booster characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139  
ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140  
ADC sampling time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142  
ADC accuracy - Limited test conditions 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144  
ADC accuracy - Limited test conditions 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146  
ADC accuracy - Limited test conditions 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148  
ADC accuracy - Limited test conditions 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150  
VREFBUF characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152  
COMP characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154  
TS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155  
V
V
monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155  
charging characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155  
BAT  
BAT  
LCD controller characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156  
TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157  
IWDG min/max timeout period at 32 kHz (LSI1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158  
Minimum I2CCLK frequency in all I2C modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158  
I2C analog filter characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159  
SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160  
Quad-SPI characteristics in SDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163  
Quad-SPI characteristics in DDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164  
SAI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166  
8/193  
DS11929 Rev 10  
STM32WB55xx STM32WB35xx  
List of tables  
Table 97.  
Table 98.  
Table 99.  
USB electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168  
JTAG characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168  
SWD characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169  
Table 100. UFBGA129 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170  
Table 101. UFBGA129 recommended PCB design rules. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172  
Table 102. WLCSP100 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174  
Table 103. WLCSP100 recommended PCB design rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175  
Table 104. VFQFPN68 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177  
Table 105. UFQFPN48 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181  
Table 106. Package thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183  
Table 107. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187  
DS11929 Rev 10  
9/193  
9
List of figures  
STM32WB55xx STM32WB35xx  
List of figures  
Figure 1.  
Figure 2.  
Figure 3.  
Figure 4.  
Figure 5.  
Figure 6.  
Figure 7.  
Figure 8.  
Figure 9.  
STM32WB55xx block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16  
STM32WB35xx block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17  
STM32WB55xx and STM32WB35xx RF front-end block diagram . . . . . . . . . . . . . . . . . . . 23  
External components for the RF part . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26  
Power distribution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27  
Power-up/down sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28  
STM32WB55xx - Power supply overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29  
STM32WB35xx - Power supply overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30  
Clock tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43  
(1) (2)  
Figure 10. STM32WB55Cx and STM32WB35Cx UFQFPN48 pinout  
Figure 11. STM32WB55Rx VFQFPN68 pinout  
Figure 12. STM32WB55Vx WLCSP100 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59  
Figure 13. STM32WB55Vx UFBGA129 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59  
. . . . . . . . . . . . . . . . . . . . . . 58  
(1) (2)  
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58  
(1)  
(1)  
Figure 14. Pin loading conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81  
Figure 15. Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81  
Figure 16. Power supply scheme (all packages except UFBGA129 and WLCSP100) . . . . . . . . . . . . 82  
Figure 17. Power supply scheme (UFBGA129 and WLCSP100 packages) . . . . . . . . . . . . . . . . . . . . 83  
Figure 18. Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84  
Figure 19. Typical link quality indicator code vs. Rx level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94  
Figure 20. Typical energy detection (T = 27°C, VDD = 3.3 V). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95  
Figure 21. VREFINT vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98  
Figure 22. Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121  
Figure 23. Low-speed external clock source AC timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . 121  
Figure 24. HSI16 frequency vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123  
Figure 25. Typical current consumption vs. MSI frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127  
Figure 26. HSI48 frequency vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128  
Figure 27. I/O input characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135  
Figure 28. Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138  
Figure 29. ADC accuracy characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151  
Figure 30. Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152  
Figure 31. SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161  
Figure 32. SPI timing diagram - slave mode and CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161  
Figure 33. SPI timing diagram - master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162  
Figure 34. Quad-SPI timing diagram - SDR mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165  
Figure 35. Quad-SPI timing diagram - DDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165  
Figure 36. SAI master timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167  
Figure 37. SAI slave timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167  
Figure 38. UFBGA129 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170  
Figure 39. UFBGA129 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171  
Figure 40. UFBGA129 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172  
Figure 41. WLCSP100 outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173  
Figure 42. WLCSP100 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175  
Figure 43. WLCSP100 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176  
Figure 44. VFQFPN68 package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177  
Figure 45. VFQFPN68 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178  
Figure 46. VFQFPN68 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179  
Figure 47. UFQFPN48 outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180  
Figure 48. UFQFPN48 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181  
10/193  
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List of figures  
Figure 49. STM32WB55xx UFQFPN48 marking example (package top view) . . . . . . . . . . . . . . . . . 182  
Figure 50. STM32WB35xx UFQFPN48 marking example (package top view) . . . . . . . . . . . . . . . . . 182  
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11  
Introduction  
STM32WB55xx STM32WB35xx  
1
Introduction  
This document provides the ordering information and mechanical device characteristics of  
®
(a)  
the STM32WB55xx and STM32WB35xx microcontrollers, based on Arm cores  
.
This document must be read in conjunction with the reference manual (RM0434), available  
from the STMicroelectronics website www.st.com.  
®
®
®
For information on the Arm Cortex -M4 and Cortex -M0+ cores, refer, respectively, to the  
®
®
Cortex -M4 Technical Reference Manual and to the Cortex -M0+ Technical Reference  
Manual, both available on the www.arm.com website.  
For information on 802.15.4 refer to the IEEE website (www.ieee.org).  
®
For information on Bluetooth refer to www.bluetooth.com.  
a. Arm is a registered trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere.  
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STM32WB55xx STM32WB35xx  
Description  
2
Description  
The STM32WB55xx and STM32WB35xx multiprotocol wireless and ultra-low-power  
®
devices embed a powerful and ultra-low-power radio compliant with the Bluetooth Low  
®
Energy SIG specification v5.0 and with IEEE 802.15.4-2011. They contain a dedicated Arm  
®
Cortex -M0+ for performing all the real-time low layer operation.  
The devices are designed to be extremely low-power and are based on the high-  
®
®
performance Arm Cortex -M4 32-bit RISC core operating at a frequency of up to 64 MHz.  
®  
This core features a Floating point unit (FPU) single precision that supports all Arm  
single-precision data-processing instructions and data types. It also implements a full set of  
DSP instructions and a memory protection unit (MPU) that enhances application security.  
Enhanced inter-processor communication is provided by the IPCC with six bidirectional  
channels. The HSEM provides hardware semaphores used to share common resources  
between the two processors.  
The devices embed high-speed memories (up to 1 Mbyte of Flash memory for  
STM32WB55xx, up to 512 Kbytes for STM32WB35xx, up to 256 Kbytes of SRAM for  
STM32WB55xx, 96 Kbytes for STM32WB35xx), a Quad-SPI Flash memory interface  
(available on all packages) and an extensive range of enhanced I/Os and peripherals.  
Direct data transfer between memory and peripherals and from memory to memory is  
supported by fourteen DMA channels with a full flexible channel mapping by the DMAMUX  
peripheral.  
The devices feature several mechanisms for embedded Flash memory and SRAM: readout  
protection, write protection and proprietary code readout protection. Portions of the memory  
®
can be secured for Cortex -M0+ exclusive access.  
The two AES encryption engines, PKA and RNG enable lower layer MAC and upper layer  
cryptography. A customer key storage feature may be used to keep the keys hidden.  
The devices offer a fast 12-bit ADC and two ultra-low-power comparators associated with a  
high accuracy reference voltage generator.  
These devices embed a low-power RTC, one advanced 16-bit timer, one general-purpose  
32-bit timer, two general-purpose 16-bit timers, and two 16-bit low-power timers.  
In addition, up to 18 capacitive sensing channels are available for STM32WB55xx (not on  
UFQFPN48 package). The STM32WB55xx also embed an integrated LCD driver up to 8x40  
or 4x44, with internal step-up converter.  
The STM32WB55xx and STM32WB35xx also feature standard and advanced  
communication interfaces, namely one USART (ISO 7816, IrDA, Modbus and Smartcard  
mode), one low- power UART (LPUART), two I2Cs (SMBus/PMBus), two SPIs (one for  
STM32WB35xx) up to 32 MHz, one serial audio interface (SAI) with two channels and three  
PDMs, one USB 2.0 FS device with embedded crystal-less oscillator, supporting BCD and  
LPM and one Quad-SPI with execute-in-place (XIP) capability.  
The STM32WB55xx and STM32WB35xx operate in the -40 to +105 °C (+125 °C junction)  
and -40 to +85 °C (+105 °C junction) temperature ranges from a 1.71 to 3.6 V power supply.  
A comprehensive set of power-saving modes enables the design of low-power applications.  
The devices include independent power supplies for analog input for ADC.  
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Description  
STM32WB55xx STM32WB35xx  
The STM32WB55xx and STM32WB35xx integrate a high efficiency SMPS step-down  
converter with automatic bypass mode capability when the V falls below V  
(x=1, 2, 3,  
DD  
BORx  
4) voltage level (default is 2.0 V). It includes independent power supplies for analog input for  
ADC and comparators, as well as a 3.3 V dedicated supply input for USB.  
A V  
dedicated supply allows the devices to back up the LSE 32.768 kHz oscillator, the  
BAT  
RTC and the backup registers, thus enabling the STM32WB55xx and STM32WB35xx to  
supply these functions even if the main V is not present through a CR2032-like battery, a  
DD  
Supercap or a small rechargeable battery.  
The STM32WB55xx offer four packages, from 48 to 129 pins. The STM32WB35xx offer one  
package, 48 pins.  
Table 2. STM32WB55xx and STM32WB35xx devices features and peripheral counts  
Feature  
STM32WB55Cx  
STM32WB55Rx  
STM32WB55Vx  
STM32WB35Cx  
Flash  
256 K 512 K 1 M 256 K 512 K 1 M 256 K 512 K 1 M 640 K 256 K 512 K  
Memory  
density  
(bytes)  
SRAM  
128 K 256 K 256 K 128 K 256 K 256 K 128 K 256 K  
64 K 192 K 64 K 192 K 64 K  
64 K  
256 K  
192 K  
96 K  
SRAM1  
SRAM2  
32 KB  
BLE  
V5.0 (2 Mbps)  
Yes  
802.15.4  
Advanced  
1 (16 bits)  
General  
purpose  
2 (16 bits) + 1 (32 bits)  
Timers  
Low power  
SysTick  
SPI  
2 (16 bits)  
1
1
2
1
I2C  
2
USART(1)  
LPUART  
SAI  
1
1
2 channels  
USB FS  
QSPI  
Yes  
1
RTC  
1
Tamper pin  
1
2
3
1
Wakeup pin  
5
2
LCD, COMxSEG  
GPIOs  
Yes, 4x13  
Yes, 4x28  
Yes, 8x40 or 4x44  
No  
30  
No  
30  
49  
6
72  
18  
Capacitive sensing  
No  
12-bit ADC  
Number of channels  
13 channels  
(incl. 3 internal)  
19 channels  
(incl. 3 internal)  
13 channels  
(incl. 3 internal)  
Internal Vref  
14/193  
Yes  
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STM32WB55xx STM32WB35xx  
Description  
Table 2. STM32WB55xx and STM32WB35xx devices features and peripheral counts (continued)  
Feature  
STM32WB55Cx  
STM32WB55Rx  
STM32WB55Vx  
STM32WB35Cx  
Analog comparator  
Max CPU frequency  
2
64 MHz  
-40to  
+85  
°C  
-40 to +85 and -  
40 to +105 °C  
Ambient  
-40 to +85 and -40 to +105 °C  
-40 to +105 and -40 to +125 °C  
-40to  
+105  
°C  
-40 to +105 and  
-40 to +125 °C  
Junction  
Operating voltage  
1.71 to 3.6 V  
WLCSP100  
0.4 mm pitch  
UFQFPN48  
7 mm x 7 mm  
0.5 mm pitch,  
solder pad  
VFQFPN68  
8 mm x 8 mm  
0.4 mm pitch,  
solder pad  
UFQFPN48  
7 mm x 7 mm  
0.5 mm pitch,  
solder pad  
Package  
UFBGA129  
0.5 mm pitch  
-
1. USART peripheral can be used as SPI.  
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57  
Description  
STM32WB55xx STM32WB35xx  
Figure 1. STM32WB55xx block diagram  
APB asynchronous  
RCC2  
NVIC  
BLE IP  
802.15.4  
LSI2  
32 kHz  
BLE / 802.15.4  
HSE2  
32 MHz  
Cortex-M0+  
RF IP  
WKUP  
BLE  
32 KB SRAM2a  
Backup  
LSE  
RTC2  
I-WDG  
TAMP  
32 kHz  
32 KB SRAM2b  
LSI1  
32 kHz  
PKA + RAM  
HSEM  
RNG  
PLL1  
ETM  
NVIC  
HSI 1%  
16 MHz  
and  
IPCC  
Cortex-M4  
(DSP)  
MSI up to  
48 MHz  
PLL2  
RCC + CSS  
PWR  
Power supply POR/  
PDR/BOR/PVD/AVD  
FPU  
MPU  
QSPI - XIP  
DMA1 7 channels  
DMA2 7 channels  
DMAMUX  
EXTI  
CRS  
RC48  
AES2  
USB FS + RAM  
WWDG  
Up to 192 KB  
SRAM1  
DBG  
Temp (oC) sensor  
GPIO Ports  
A, B, C, D, E, H  
SPI1  
SPI2  
ADC1 16-bit ULP  
4.26 Msps / 19 ch  
CRC  
TSC  
LCD  
I2C1  
AES1  
LPTIM1  
LPTIM2  
SAI1  
I2C3  
APB  
TIM1  
LPUART1  
TIM2  
USART1  
SYSCFG/COMP/VREF  
TIM16, TIM17  
MS41407V6  
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STM32WB55xx STM32WB35xx  
Description  
Figure 2. STM32WB35xx block diagram  
APB asynchronous  
RCC2  
NVIC  
BLE IP  
802.15.4  
LSI2  
32 kHz  
BLE / 802.15.4  
HSE2  
32 MHz  
Cortex-M0+  
RF IP  
WKUP  
BLE  
32 KB SRAM2a  
Backup  
LSE  
RTC2  
I-WDG  
TAMP  
32 kHz  
32 KB SRAM2b  
LSI1  
32 kHz  
PKA + RAM  
HSEM  
RNG  
PLL1  
HSI 1%  
16 MHz  
NVIC  
And  
IPCC  
PLL2  
MSI up to  
48 MHz  
Cortex-M4  
(DSP)  
RCC + CSS  
PWR  
Power supply POR/  
PDR/BOR/PVD/AVD  
FPU  
MPU  
QSPI - XIP  
DMA1 7 channels  
DMA2 7 channels  
DMAMUX  
EXTI  
CRS  
RC48  
AES2  
USB FS + RAM  
WWDG  
32 KB SRAM1  
DBG  
Temp (oC) sensor  
GPIO Ports  
A, B, C, E, H  
SPI1  
ADC1 16-bit ULP  
4.26 Msps / 19 ch  
CRC  
I2C1  
I2C3  
AES1  
APB  
TIM1  
LPTIM1  
LPTIM2  
SAI1  
LPUART1  
USART1  
TIM2  
TIM16, TIM17  
SYSCFG/COMP  
MS53592V1  
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Functional overview  
STM32WB55xx STM32WB35xx  
3
Functional overview  
3.1  
Architecture  
The STM32WB55xx and STM32WB35xx multiprotocol wireless devices embed a BLE and  
an 802.15.4 RF subsystem that interfaces with a generic microcontroller subsystem using  
®
®
an Arm Cortex -M4 CPU (called CPU1) on which the host application resides.  
The RF subsystem is composed of an RF analog front end, BLE and 802.15.4 digital MAC  
®
®
blocks as well as of a dedicated Arm Cortex -M0+ microcontroller (called CPU2), plus  
proprietary peripherals. The RF subsystem performs all of the BLE and 802.15.4 low layer  
stack, reducing the interaction with the CPU1 to high level exchanges.  
Some functions are shared between the RF subsystem CPU (CPU2) and the Host CPU  
(CPU1):  
Flash memories  
SRAM1, SRAM2a and SRAM2b (SRAM2a can be retained in Standby mode)  
Security peripherals (RNG, AES1, PKA)  
Clock RCC  
Power control (PWR)  
The communication and the sharing of peripherals between the RF subsystem and the  
®
Cortex -M4 CPU is performed through a dedicated inter processor communication  
controller (IPCC) and semaphore mechanism (HSEM).  
3.2  
Arm® Cortex®-M4 core with FPU  
®
®
The Arm Cortex -M4 with FPU is a processor for embedded systems. It has been  
developed to provide a low-cost platform that meets the needs of MCU implementation, with  
a reduced pin count and low-power consumption, while delivering outstanding  
computational performance and an advanced response to interrupts.  
®
®
The Arm Cortex -M4 with FPU 32-bit RISC processor features exceptional   
®
code-efficiency, delivering the high-performance expected from an Arm core in the  
memory size usually associated with 8- and 16-bit devices.  
The processor supports a set of DSP instructions enabling efficient signal processing and  
complex algorithm execution.  
Its single precision FPU speeds up software development by using metalanguage  
development tools, while avoiding saturation.  
®
With its embedded Arm core, the STM32WB55xx and STM32WB35xx are compatible with  
®
all Arm tools and software.  
Figure 1 and Figure 2 show the general block diagram of, respectively, the STM32WB55xx  
and STM32WB35xx devices.  
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STM32WB55xx STM32WB35xx  
Functional overview  
3.3  
Memories  
3.3.1  
Adaptive real-time memory accelerator (ART Accelerator)  
®
The ART Accelerator is a memory accelerator optimized for STM32 industry-standard Arm  
®
®
Cortex -M4 processors. It balances the inherent performance advantage of the Arm  
®
Cortex -M4 over Flash memory technologies, which normally require the processor to wait  
for the Flash memory at higher frequencies.  
To release the processor near 80 DMIPS performance at 64 MHz, the accelerator  
implements an instruction prefetch queue and branch cache, which increases program  
execution speed from the 64-bit Flash memory. Based on CoreMark benchmark, the  
performance achieved thanks to the ART accelerator is equivalent to 0 wait state program  
execution from Flash memory at a CPU frequency up to 64 MHz.  
3.3.2  
Memory protection unit  
The memory protection unit (MPU) is used to manage the CPU1 accesses to memory to  
prevent one task to accidentally corrupt the memory or resources used by any other active  
task. This memory area is organized into up to eight protected areas, which can be divided  
up into eight subareas. The protection area sizes are between 32 bytes and the whole  
4 Gbytes of addressable memory.  
The MPU is especially helpful for applications where some critical or certified code must be  
protected against the misbehavior of other tasks. It is usually managed by an RTOS   
(real-time operating system). If a program accesses a memory location prohibited by the  
MPU, the RTOS detects it and takes action. In an RTOS environment, the kernel can  
dynamically update the MPU area setting, based on the process to be executed.  
The MPU is optional and can be bypassed for applications that do not need it.  
3.3.3  
Embedded Flash memory  
The STM32WB55xx and STM32WB35xx devices feature, respectively, up to 1 Mbyte and  
512 Kbytes of embedded Flash memory available for storing programs and data, as well as  
some customer keys.  
Flexible protections can be configured thanks to option bytes:  
Readout protection (RDP) to protect the whole memory. Three levels are available:  
Level 0: no readout protection  
Level 1: memory readout protection: the Flash memory cannot be read from or  
written to if either debug features are connected, boot in SRAM or bootloader is  
selected  
®
®
Level 2: chip readout protection: debug features (Cortex -M4 and Cortex -M0+  
JTAG and serial wire), boot in SRAM and bootloader selection are disabled (JTAG  
fuse). This selection is irreversible.  
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Functional overview  
STM32WB55xx STM32WB35xx  
Table 3. Access status vs. readout protection level and execution modes  
Debug, boot from SRAM or boot  
User execution  
Protection  
level  
from system memory (loader)  
Area  
Read  
Write  
Erase  
Read  
Write  
Erase  
1
2
1
2
1
2
1
2
1
2
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
No  
Yes  
Yes  
No  
N/A  
Yes  
N/A  
Yes  
N/A  
No  
No  
N/A  
No  
No  
N/A  
No  
Main  
memory  
No  
System  
memory  
No  
No  
N/A  
Yes  
N/A  
No  
N/A  
Yes  
Yes  
No(1)  
Yes  
Yes  
Yes  
Yes  
Yes  
Option  
bytes  
No(1)  
N/A(2)  
N/A  
N/A  
N/A(2)  
N/A  
No(2)  
N/A  
Backup  
registers  
N/A  
No  
N/A  
No  
Yes(2)  
SRAM2a  
SRAM2b  
Yes  
N/A  
N/A  
1. The option byte can be modified by the RF subsystem.  
2. Erased when RDP changes from Level 1 to Level 0.  
Write protection (WRP): the protected area is protected against erasing and  
programming. Two areas can be selected, with 4-Kbyte granularity.  
Proprietary code readout protection (PCROP): two parts of the Flash memory can be  
protected against read and write from third parties. The protected area is execute-only:  
it can only be reached by the STM32 CPU, as an instruction code, while all other  
accesses (DMA, debug and CPU data read, write and erase) are strictly prohibited.  
Two areas can be selected, with 2-Kbyte granularity. An additional option bit  
(PCROP_RDP) makes possible to select if the PCROP area is erased or not when the  
RDP protection is changed from Level 1 to Level 0.  
A section of the Flash memory is secured for the RF subsystem CPU2, and cannot be  
accessed by the host CPU1.  
The whole non-volatile memory embeds the error correction code (ECC) feature supporting:  
single error detection and correction  
double error detection  
the address of the ECC fail can be read in the ECC register  
The embedded Flash memory is shared between CPU1 and CPU2 on a time sharing basis.  
A dedicated HW mechanism allows both CPUs to perform Write/Erase operations.  
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STM32WB55xx STM32WB35xx  
Functional overview  
3.3.4  
Embedded SRAM  
The STM32WB55xx devices feature up to 256 Kbytes of embedded SRAM, split in three  
blocks:  
SRAM1: up to 192 Kbytes mapped at address 0x2000 0000  
SRAM2a: 32 Kbytes located at address 0x2003 0000 (contiguous to SRAM1) also  
mirrored at 0x1000 0000, with hardware parity check (this SRAM can be retained in  
Standby mode)  
SRAM2b: 32 Kbytes located at address 0x2003 8000 (contiguous with SRAM2a) and  
mirrored at 0x1000 8000 with hardware parity check  
The STM32WB35xx devices feature 96 Kbytes of embedded SRAM, split in three blocks:  
SRAM1: 32 Kbytes mapped at address 0x2000 0000  
SRAM2a: 32 Kbytes located at address 0x2003 0000 (contiguous to SRAM1) also  
mirrored at 0x1000 0000, with hardware parity check (this SRAM can be retained in  
Standby mode)  
SRAM2b: 32 Kbytes located at address 0x2003 8000 (contiguous with SRAM2a) and  
mirrored at 0x1000 8000 with hardware parity check  
SRAM2a and SRAM2b can be write-protected, with 1-Kbyte granularity. A section of the  
SRAM2a and SRAM2b is secured for the RF sub-system and cannot be accessed by the  
host CPU1.  
The SRAMs can be accessed in read/write with 0 wait states for all CPU1 and CPU2 clock  
speeds.  
3.4  
Security and safety  
The STM32WB55xx and STM32WB35xx contain many security blocks both for the BLE or  
IEEE 802.15.4 and the Host application.  
It includes:  
Customer storage of the BLE and 802.15.4 keys  
Secure Flash memory partition for RF subsystem-only access  
Secure SRAM partition, that can be accessed only by the RF subsystem  
True random number generator (RNG)  
Advance encryption standard hardware accelerators (AES-128bit and AES-256bit,  
supporting chaining modes ECB, CBC, CTR, GCM, GMAC, CCM)  
Private key acceleration (PKA) including:  
Modular arithmetic including exponentiation with maximum modulo size of 3136  
bits  
Elliptic curves over prime field scalar multiplication, ECDSA signature, ECDSA  
verification with maximum modulo size of 521 bits  
Cyclic redundancy check calculation unit (CRC)  
A specific mechanism is in place to ensure that all the code executed by the RF subsystem  
CPU2 can be secure, whatever the Host application. For the AES1 a customer key can be  
managed by the CPU2 and used by the CPU1 to encrypt/decrypt data.  
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Functional overview  
STM32WB55xx STM32WB35xx  
3.5  
Boot modes and FW update  
At startup, BOOT0 pin and BOOT1 option bit are used to select one of three boot options:  
Boot from user Flash  
Boot from system memory  
Boot from embedded SRAM  
The devices always boot on CPU1 core. The embedded bootloader code makes it possible  
to boot from various peripherals:  
USB  
UART  
I2C  
SPI  
Secure Firmware update (especially BLE and 802.15.4) from system boot and over the air is  
provided.  
3.6  
RF subsystem  
The STM32WB55xx and STM32WB35xx embed an ultra-low power multi-standard radio  
®
®
Bluetooth Low Energy (BLE) and 802.15.4 network processor, compliant with Bluetooth  
®
specification v5.0 and IEEE 802.15.4-2011. The BLE features 1 Mbps and 2 Mbps transfer  
®
rates, supports multiple roles simultaneously acting at the same time as Bluetooth Low  
Energy sensor and hub device, embeds Elliptic Curve Diffie-Hellman (ECDH) key  
agreement protocol, thus ensuring a secure connection.  
®
®
The Bluetooth Low Energy stack and 802.15.4 Low Level layer run on an embedded Arm  
®
Cortex -M0+ core (CPU2). The stack is stored on the embedded Flash memory, which is  
also shared with the Arm Cortex -M4 (CPU1) application, making it possible in-field stack  
update.  
®
®
3.6.1  
RF front-end block diagram  
The RF front-end is based on a direct modulation of the carrier in Tx, and uses a low IF  
architecture in Rx mode.  
Thanks to an internal transformer at RF pins, the circuit directly interfaces the antenna  
(single ended connection, impedance close to 50 ). The natural bandpass behavior of the  
internal transformer, simplifies outside circuitry aimed for harmonic filtering and out of band  
interferer rejection.  
In Transmit mode, the maximum output power is user selectable through the programmable  
LDO voltage of the power amplifier. A linearized, smoothed analog control offers clean  
power ramp-up.  
In receive mode the circuit can be used in standard high performance or in reduced power  
consumption (user programmable). The Automatic gain control (AGC) is able to reduce the  
chain gain at both RF and IF locations, for optimized interference rejection. Thanks to the  
use of complex filtering and highly accurate I/Q architecture, high sensitivity and excellent  
linearity can be achieved.  
The bill of material is reduced thanks to the high degree of integration. The radio frequency  
source is synthesized form an external 32 MHz crystal that does not need any external  
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STM32WB55xx STM32WB35xx  
Functional overview  
trimming capacitor network thanks to a dual network of user programmable integrated  
capacitors.  
Figure 3. STM32WB55xx and STM32WB35xx RF front-end block diagram  
Timer and Power  
AGC  
control  
EXT_  
PA_TX  
RF control  
G
Interrupt  
Wakeup  
BLE  
BP  
filter  
LNA  
modulator  
BLE  
controller  
AHB  
APB  
G
BLE  
demodulator  
RF1  
802.15.4  
modulator  
APB  
802.15.4  
MAC  
Interrupt  
Wakeup  
802.15.4  
demodulator  
PLL  
See  
notes  
Adjust  
Adjust  
HSE  
Trimmed  
bias  
Max PA  
level  
SMPS  
LDO  
LDO  
LDO  
VDDSMPS VSSSMPS VLXSMPS  
OSC_OUT  
VFBSMPS  
VDDRF  
OSC_IN  
32 MHz  
Notes:  
- UFQFPN48 and VFQFPN68: VSS through exposed pad, and VSSRF pin must be connected to ground plane  
- WLCSP100 and UFBGA129: VSSRF pins must be connected to ground plane  
MS45477V6  
3.6.2  
BLE general description  
®
The BLE block is a master/slave processor, compliant with Bluetooth specification 5.0  
standard (2 Mbps).  
DS11929 Rev 10  
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Functional overview  
STM32WB55xx STM32WB35xx  
®
It integrates a 2.4 GHz RF transceiver and a powerful Cortex -M0+ core, on which a  
®
complete power-optimized stack for Bluetooth Low Energy protocol runs, providing  
master / slave role support  
GAP: central, peripheral, observer or broadcaster roles  
ATT/GATT: client and server  
SM: privacy, authentication and authorization  
L2CAP  
Link layer: AES-128 encryption and decryption  
®
In addition, according to Bluetooth specification v5.0, the BLE block provides:  
Multiple roles simultaneous support  
Master/slave and multiple roles simultaneously  
LE data packet length extension (making it possible to reach 800 kbps at application  
level)  
LE privacy 1.2  
LE secure connections  
Flexible Internet connectivity options  
High data rate (2 Mbps)  
The device allows the applications to meet the tight peak current requirements imposed by  
the use of standard coin cell batteries. When the high efficiency embedded SMPS   
step-down converter is used, the RF front end consumption (I  
) is only 8.1 mA at the  
tmax  
highest output power (+6 dBm).  
The power efficiency of the subsystem is optimized: while running with the radio and the  
®
applicative cores simultaneously using the SMPS, the Cortex -M4 core consumption  
reaches 53 µA / MHz in active mode.  
Ultra-low-power sleep modes and very short transition time between operating modes result  
in very low average current consumption during real operating conditions, resulting in longer  
battery life.  
The BLE block integrates a full bandpass balun, thus reducing the need for external  
components.  
®
The link between the Cortex -M4 application processor (CPU1) running the application, and  
®
the BLE stack running on the dedicated Cortex -M0+ (CPU2) is performed through a  
normalized API, using a dedicated IPCC.  
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STM32WB55xx STM32WB35xx  
Functional overview  
3.6.3  
802.15.4 general description  
The STM32WB55xx and STM32WB35xx embed a dedicated 802.15.4 hardware MAC:  
Support for 802.15.4 release 2011  
Advanced MAC frame filtering; hardwired firewall: Programmable filters based on  
source/destination addresses, frame version, security enabled, frame type  
256-byte RX FIFO; Up to 8 frames capacity, additional frame information (timing, mean  
RSSI, LQI)  
128-byte TX FIFO with retention  
Content not lost, retransmissions possible under CPU2 control  
Automatic frame acknowledgment, with programmable delay  
Advanced channel access features  
Full CSMA-CA support  
Superframe timer  
Beaconing support (require LSE)  
Flexible TX control with programmable delay  
Configuration registers with retention available down to Standby mode for  
software/auto-restore  
Autonomous sniffer, Wakeup based on timer or CPU2 request  
Automatic frame transmission/reception/sleep periods, Interrupt to the CPU2 on  
particular events  
3.6.4  
RF pin description  
The RF block contains dedicated pins, listed in Table 4.  
:
Table 4. RF pin list  
Name  
Type  
Description  
RF1  
RF Input/output, must be connected to the antenna through a low-pass matching network  
OSC_OUT  
OSC_IN  
32 MHz main oscillator, also used as HSE source  
External PA transmit control  
I/O  
RF_TX_  
MOD_EXT_PA  
VDDRF  
VDD Dedicated supply, must be connected to VDD  
VSS To be connected to GND  
VSSRF(1)  
1. On packages with exposed pad, this pad must be connected to GND plane for correct RF operation.  
3.6.5  
Typical RF application schematic  
The schematic in Figure 4 and the external components listed in Table 4 are purely  
indicative. For more details refer to the “Reference design” provided in separate documents.  
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Functional overview  
STM32WB55xx STM32WB35xx  
Figure 4. External components for the RF part  
OSC_IN  
OSC_OUT  
VDDRF  
X1  
32 MHz  
VDD  
C1  
(including exposed pad)  
STM32WB  
microcontroller  
Antenna  
Cf2  
VSSRF  
Lf1  
Cf1  
RF1  
Antenna filter  
MS53575V1  
Table 5. Typical external components  
Description  
Component  
Value  
C1  
X1  
Decoupling capacitance for RF  
32 MHz crystal(1)  
100 nF // 100 pF  
32 MHz  
Antenna filter  
Antenna  
Antenna filter and matching network  
2.4 GHz band antenna  
Refer to AN5165, on www.st.com  
-
1. e.g. NDK reference: NX2016SA 32 MHz EXS00A-CS06654.  
Note:  
For more details refer to AN5165 “Development of RF hardware using STM32WB  
microcontrollers” available on www.st.com.  
3.7  
Power supply management  
3.7.1  
Power supply distribution  
The device integrate an SMPS step-down converter to improve low power performance  
when the V voltage is high enough. This converter has an intelligent mode that  
DD  
automatically enters in bypass mode when the V voltage falls below a specific BORx   
DD  
(x = 1, 2, 3 or 4) voltage.  
By default, at Reset the SMPS is in bypass mode.  
The device can be operated without the SMPS by just wiring its output to V . This is the  
DD  
case for applications where the voltage is low, or where the power consumption is not  
critical.  
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STM32WB55xx STM32WB35xx  
Functional overview  
Figure 5. Power distribution  
VDD  
VDD  
VDDSMPS  
VDDSMPS  
SMPS  
SMPS  
(not used)  
SMPS mode or  
BYPASS mode  
VLXSMPS  
VLXSMPS  
L1  
LPR  
LPR  
VFBSMPS  
VFBSMPS  
C2  
RFR  
MR  
RFR  
MR  
SMPS configuration  
LDO configuration  
MS41409V4  
Table 6. Power supply typical components  
Description  
Component  
Value  
C2  
SMPS output capacitor(1)  
4.7 µF  
2.2 µH  
10 µH  
For 8 MHz(3)  
For 4 MHz(4)  
L1(2)  
SMPS inductance  
1. e.g. GRM155R60J475KE19.  
2. An extra 10 nH inductor in series with L1 is needed to improve the receiver performance,   
e.g Murata LQG15WZ10NJ02D  
3. e.g. Wurth 74479774222.  
4. e.g. Murata LQM21FN100M70L.  
The SMPS can also be switched on or set in bypass mode at any time by the application  
software, for example when very accurate ADC measurement are needed.  
3.7.2  
Power supply schemes  
The devices have different voltage supplies (see Figure 7 and Figure 8) and can operate  
within the following voltage ranges:  
V
= 1.71 to 3.6 V: external power supply for I/Os (V  
), the internal regulator and  
DDIO  
DD  
system functions such as RF, SMPS, reset, power management and internal clocks. It  
is provided externally through VDD pins. V  
connected to VDD pins.  
and V  
must be always  
DDRF  
DDSMPS  
V
= 1.62 (ADC/COMPs) to 3.6 V: external analog power supply for ADC,  
DDA  
comparators and voltage reference buffer. The V  
voltage level can be independent  
DDA  
from the V voltage. When not used V  
must be connected to V  
.
DD  
DDA  
DD  
V
= 3.0 to 3.6 V: external independent power supply for USB transceivers. When  
DDUSB  
not used V  
must be connected to V  
.
DDUSB  
DD  
V
= 2.5 to 3.6 V: the LCD controller can be powered either externally through the  
LCD  
VLCD pin, or internally from an internal voltage generated by the embedded step-up  
converter. This converter can generate a V voltage up to 3.6 V if V is higher than  
LCD  
DD  
2.0 V. Note that the LCD is available only on STM32WB55xx devices.  
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Functional overview  
STM32WB55xx STM32WB35xx  
During power up/down, the following power sequence requirements must be respected:  
When V is below 1 V the other power supplies (V  
, V  
, V ), must remain  
LCD  
DD  
DDA  
DDUSB  
below V + 300 mV  
DD  
When V is above 1 V all power supplies are independent.  
DD  
Figure 6. Power-up/down sequence  
V
3.6  
(1)  
VDDX  
VDD  
VBOR0  
1
0.3  
Power-on  
Invalid supply area  
Operating mode  
VDDX < VDD + 300 mV  
Power-down  
time  
VDDX independent from VDD  
MSv47490V1  
1. VDDX refers to any power supply among VDDA, VDDUSB and VLCD  
.
During the power down phase, V can temporarily become lower than other supplies only  
DD  
if the energy provided to the MCU remains below 1 mJ. This allows the external decoupling  
capacitors to be discharged with different time constants during the power down transient  
phase.  
Note:  
V
, V  
and V must be wired together, so they can follow the same voltage  
DDSMPS  
DD  
DDRF  
sequence.  
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STM32WB55xx STM32WB35xx  
Functional overview  
Figure 7. STM32WB55xx - Power supply overview  
Interruptible domain (VDD12I  
)
On domain (VDD12O)  
(CPU1, CPU2,  
peripherals,  
SysConfig, AIEC,  
RCC, PwrCtrl,  
LPTIM, LPUSART  
IO  
logic  
SRAM1,  
IOs  
SRAM2b)  
Power  
switch  
Power  
switch  
VSS  
VSS  
VSS  
VFBSMPS  
VLXSMPS  
MR  
SMPS  
VDDSMPS  
RFR  
VSSSMPS  
LPR  
VDDRF  
RF domain  
Backup domain  
Radio  
VBKP12  
SRAM2a  
Power switch  
VSSRF  
VSS  
VSS  
(including exposed pad)  
Wakeup domain (VDDIO  
)
HSI, HSE1,  
2xPLL,  
LSI1, LSI2,  
IWDG, RF  
VDD  
Power switch  
VSW  
VBAT  
VSS  
Switch domain (VSW  
)
LSE, RTC,  
backup  
registers  
VBAT  
IOs  
IO  
logic  
VSS  
VSS  
VLCD  
VDDA  
LCD  
Analog domain  
REF_BUF  
ADC  
VREF+  
=
=
VREF+  
VREF-  
VSSA  
VDDUSB  
USB  
VUSB  
IOs  
transceiver(1)  
VSS  
USB domain (VUSB  
)
VSS  
MS41410V7  
1. The USB transceiver is powered by VDDUSB, and the GPIOs associated with USB are powered by VDDUSB  
when USB alternate function (PA11 and PA12) is selected. When USB alternate function is not selected  
the GPIOs associated with USB are powered as standard GPIOs.  
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Functional overview  
STM32WB55xx STM32WB35xx  
Figure 8. STM32WB35xx - Power supply overview  
Interruptible domain (VDD12I  
)
On domain (VDD12O)  
(CPU1, CPU2,  
peripherals,  
SysConfig, AIEC,  
RCC, PwrCtrl,  
LPTIM, LPUSART  
IO  
logic  
SRAM1,  
IOs  
SRAM2b)  
Power  
switch  
Power  
switch  
VSS  
VSS  
VSS  
VFBSMPS  
VLXSMPS  
VDDSMPS  
VSSSMPS  
MR  
SMPS  
LPR  
RFR  
VDDRF  
RF domain  
Backup domain  
Radio  
VBKP12  
SRAM2a  
Power switch  
VSSRF  
VSS  
VSS  
(including exposed pad)  
Wakeup domain (VDDIO  
)
HSI, HSE1,  
2xPLL,  
LSI1, LSI2,  
IWDG, RF  
VDD  
Power switch  
VSW  
VBAT  
VSS  
Switch domain (VSW  
)
LSE, RTC,  
backup  
registers  
VBAT  
IOs  
IO  
logic  
VSS  
VSS  
VDDA  
Analog domain  
ADC  
VREF+  
=
=
VREF-  
VSS  
VDDUSB  
USB  
transceiver(1)  
VUSB  
IOs  
VSS  
USB domain (VUSB  
)
VSS  
MS53593V1  
1. The USB transceiver is powered by VDDUSB, and the GPIOs associated with USB are powered by VDDUSB  
when USB alternate function (PA11 and PA12) is selected. When USB alternate function is not selected  
the GPIOs associated with USB are powered as standard GPIOs.  
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STM32WB55xx STM32WB35xx  
Functional overview  
3.7.3  
Linear voltage regulator  
Three embedded linear voltage regulators supply most of the digital and RF circuitries, the  
main regulator (MR), the low-power regulator (LPR) and the RF regulator (RFR).  
The MR is used in the Run and Sleep modes and in the Stop 0 mode.  
The LPR is used in Low-Power Run, Low-Power Sleep, Stop 1 and Stop 2 modes. It is  
also used to supply the SRAM2a in Standby with retention.  
The RFR is used to supply the RF analog part, its activity is automatically managed by  
the RF subsystem.  
All the regulators are in power-down in Standby and Shutdown modes: the regulator output  
is in high impedance, and the kernel circuitry is powered down, inducing zero consumption.  
The ultralow-power STM32WB55xx and STM32WB35xx support dynamic voltage scaling to  
optimize its power consumption in run mode. The voltage from the main regulator that  
supplies the logic (VCORE) can be adjusted according to the system’s maximum operating  
frequency.  
There are two voltage and frequency ranges:  
Range 1, with the CPU running up to 64 MHz  
Range 2, with a maximum CPU frequency of 16 MHz (note that HSE can be active in  
this mode). All peripheral clocks are also limited to 16 MHz.  
VCORE can also be supplied by the low-power regulator, the main regulator being switched  
off. The system is then in Low-power run mode. In this case the CPU is running at up to  
2 MHz, and peripherals with independent clock can be clocked by HSI16 (in this mode the  
RF subsystem is not available).  
3.7.4  
Power supply supervisor  
An integrated ultra-low-power brown-out reset (BOR) is active in all modes except  
Shutdown ensuring proper operation after power-on and during power down. The devices  
remain in reset mode when the monitored supply voltage V is below a specified  
DD  
threshold, without the need for an external reset circuit.  
The lowest BOR level is 1.71 V at power on, and other higher thresholds can be selected  
through option bytes.The device features an embedded programmable voltage detector  
(PVD) that monitors the V power supply and compares it with the V  
threshold. An  
DD  
PVD  
interrupt can be generated when V drops below the V  
threshold and/or when V is  
DD  
PVD  
DD  
higher than the V  
threshold. The interrupt service routine can then generate a warning  
PVD  
message and/or put the MCU into a safe state. The PVD is enabled by software.  
In addition, the devices embed a peripheral voltage monitor (PVM) that compares the  
independent supply voltage V  
functional supply range.  
with a fixed threshold to ensure that the peripheral is in its  
DDA  
Any BOR level can also be used to automatically switch the SMPS step-down converter in  
bypass mode when the V voltage drops below a given voltage level. The mode of  
DD  
operation is selectable by register bit, the BOR level is selectable by option byte.  
3.7.5  
Low-power modes  
These ultra-low-power devices support several low-power modes to achieve the best  
compromise between low-power consumption, short startup time, available peripherals and  
available wakeup sources.  
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Functional overview  
STM32WB55xx STM32WB35xx  
By default, the microcontroller is in Run mode, Range 1, after a system or a power on  
Reset. It is up to the user to select one of the low-power modes described below:  
Sleep  
In Sleep mode, only the CPU1 is stopped. All peripherals, including the RF subsystem,  
continue to operate and can wake up the CPU when an interrupt/event occurs.  
Low-power run  
This mode is achieved with VCORE supplied by the low-power regulator to minimize  
the regulator operating current. The code can be executed from SRAM or from the  
Flash memory, and the CPU1 frequency is limited to 2 MHz. The peripherals with  
independent clock can be clocked by HSI16. The RF subsystem is not available in this  
mode and must be OFF.  
Low-power sleep  
This mode is entered from the low-power run mode. Only the CPU1 clock is stopped.  
When wakeup is triggered by an event or an interrupt, the system reverts to the   
low-power run mode. The RF subsystem is not available in this mode and must be  
OFF.  
Stop 0, Stop 1 and Stop 2  
Stop modes achieve the lowest power consumption while retaining the content of all  
the SRAM and registers. The LSE (or LSI) is still running.  
The RTC can remain active (Stop mode with RTC, Stop mode without RTC).  
Some peripherals with wakeup capability can enable the HSI16 RC during Stop modes  
to detect their wakeup condition.  
Three modes are available: Stop 0, Stop 1 and Stop 2. In Stop 2 mode, most of the  
VCORE domain is put in a lower leakage mode.  
Stop 1 offers the largest number of active peripherals and wakeup sources, a smaller  
wakeup time but a higher consumption than Stop 2. In Stop 0 mode the main regulator  
remains ON, allowing a very fast wakeup time but with higher consumption.  
In these modes the RF subsystem can wait for incoming events in all Stop modes.  
The system clock when exiting from Stop 0, Stop1 or Stop2 modes can be either MSI  
up to 48 MHz or HSI16 if the RF subsystem is disabled. If the RF subsystem or the  
SMPS is used the exits must be set to HSI16 only. If used, the SMPS is restarted  
automatically.  
Standby  
The Standby mode is used to achieve the lowest power consumption with BOR. The  
internal regulator is switched off so that the VCORE domain is powered off.  
The RTC can remain active (Standby mode with RTC).  
The brown-out reset (BOR) always remains active in Standby mode.  
The state of each I/O during standby mode can be selected by software: I/O with  
internal pull-up, internal pull-down or floating.  
After entering Standby mode, SRAM1, SRAM2b and register contents are lost except  
for registers in the Backup domain and Standby circuitry. Optionally, SRAM2a can be  
retained in Standby mode, supplied by the low-power regulator (Standby with 32 KB  
SRAM2a retention mode).  
The device exits Standby mode when an external reset (NRST pin), an IWDG reset,  
WKUP pin event (configurable rising or falling edge), or an RTC event occurs (alarm,  
periodic wakeup, timestamp, tamper) or a failure is detected on LSE (CSS on LSE, or  
from the RF system wakeup).  
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STM32WB55xx STM32WB35xx  
Functional overview  
The system clock after wakeup is 16 MHz, derived from the HSI16. If used, the SMPS  
is restarted automatically.  
In this mode the RF can be used.  
Shutdown  
The Shutdown mode allows to achieve the ultimate lowest power consumption. The  
internal regulator is switched off so that the VCORE domain is powered off.  
The RTC can remain active (Shutdown mode with RTC, Shutdown mode without RTC).  
The BOR is not available in Shutdown mode. No power voltage monitoring is possible  
in this mode, therefore the switch to Backup domain is not supported.  
SRAM1, SRAM2a, SRAM2b and register contents are lost except for registers in the  
Backup domain.  
The device exits Shutdown mode when an external reset (NRST pin), a WKUP pin  
event (configurable rising or falling edge), or an RTC event occurs (alarm, periodic  
wakeup, timestamp, tamper).  
The system clock after wakeup is 4 MHz, derived from the MSI.  
In this mode the RF is no longer operational.  
When the RF subsystem is active, it changes the power state according to its needs (Run,  
Stop, Standby). This operation is transparent for the CPU1 host application and managed by  
a dedicated HW state machine. At any given time the effective power state reached is the  
higher one needed by both the CPU1 and RF sub-system.  
Table 7 summarizes the peripheral features over all available modes. Wakeup capability is  
detailed in gray cells.  
(1)  
Table 7. Features over all modes  
Stop0/Stop1  
Stop 2  
Standby Shutdown  
Peripheral(2)  
-
-
-
-
CPU1  
CPU2  
Y
Y
-
-
Y
Y
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Radio system  
(BLE, 802.15.4)  
Y
Y(3)  
Y
-
-
Y
Y
Y
Y
Y(4) Y(4)  
Flash memory  
SRAM1  
Y (5)  
Y
Y
Y(7)  
Y(7)  
Y(7)  
O
O(6) O(6)  
R
R
R
R
-
-
-
R
R
R
R
-
-
-
R
-
-
-
R
-
-
-
-
-
-
-
-
R
-
Y
Y
Y
O
Y
Y
Y(7)  
Y(7)  
Y(7)  
O
SRAM2a  
Y
-
-
R(8)  
-
-
-
SRAM2b  
Y
-
-
-
-
-
-
Quad-SPI  
O
-
-
-
-
-
-
Backup registers  
Brown-out reset (BOR)  
Y
Y
Y
R
Y
-
R
Y
-
R
Y
-
R
-
R
-
Y
Y
Y
Y
Y
Y
DS11929 Rev 10  
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Functional overview  
STM32WB55xx STM32WB35xx  
(1)  
Table 7. Features over all modes (continued)  
Stop0/Stop1 Stop 2  
Standby Shutdown  
Peripheral(2)  
-
-
-
-
Programmable voltage  
detector (PVD)  
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
-
-
-
-
-
-
-
-
-
-
Peripheral voltage monitor  
PVMx (x=1, 3)  
SMPS  
O
O
O
O
O
O
O
O
O(9)  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
DMAx (x = 1, 2)  
High speed internal  
(HSI16)  
O
O
O
O
O
O
O
-
O
-
O(10)  
-
-
-
O(10)  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Oscillator HSI48  
-
-
-
-
High speed external  
(HSE)(11)  
O
O
Low speed internal  
(LSI1 or LSI2)  
O
O
O
O
O
O
O
O
O
O
O
O
-
-
-
-
O
O
-
-
-
-
O
O
-
-
-
-
-
O
-
-
-
-
-
O
-
Low speed external (LSE)  
Multi-speed internal  
(MSI)(12)  
48  
24  
48  
PLLx VCO maximum  
frequency  
344 128  
O
O
O
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Clock security system  
(CSS)  
O
O
O
O(13)  
O
O(13)  
Clock security system on  
LSE  
O
O
3
O
O
3
O
O
3
O
O
3
O
O
3
O
O
O
O
O
3
O
O
O
O
O
3
O
O
O
-
-
-
RTC / Auto wakeup  
O
3
O
O
O
3
Number of RTC  
tamper pins  
LCD  
O
O
O
O
O
-
O
-
O
-
O
O
O
-
O
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
USB FS  
USART1  
O
-
O
O
O
O
O(14) O(14)  
-
-
Low-power UART  
(LPUART1)  
O
O
O
O(14) O(14) O(14) O(14)  
O(15) O(15)  
O(15) O(15) O(15) O(15)  
-
-
-
-
-
I2C1  
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
I2C3  
SPIx (x=1, 2)  
SAI1  
-
-
-
-
-
-
-
-
34/193  
DS11929 Rev 10  
STM32WB55xx STM32WB35xx  
Functional overview  
Standby Shutdown  
(1)  
Table 7. Features over all modes (continued)  
Stop0/Stop1 Stop 2  
Peripheral(2)  
-
-
-
-
ADC1  
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
VREFBUF  
O
O
-
COMPx (x=1, 2)  
Temperature sensor  
O
-
O
-
O
-
Timers TIMx  
(x=1, 2, 16, 17)  
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Low-power Timer 1  
(LPTIM1)  
O
O
O
O
O
O
O
-
O
-
Low-power Timer 2  
(LPTIM2)  
-
-
Independent watchdog  
(IWDG)  
O
O
O
O
Window watchdog  
(WWDG)  
O
O
O
O
O
O
O
O
O
O
O
O
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
SysTick timer  
Touch sensing controller  
(TSC)  
True random number  
generator (RNG)  
O
-
O
-
-
-
-
-
-
-
-
-
-
-
AES2 hardware accelerator  
O
O
O
O
O
O
O
-
O
O
O
O
O
O
O
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
CRC calculation unit  
IPCC  
HSEM  
PKA  
-
-
O
O
5
pins  
5
pins  
(16)  
(17)  
GPIOs  
O
O
O
O
O
O
O
O
-
1. Legend: Y = Yes (Enabled), O = Optional (Disabled by default, can be enabled by software), R = Data retained,   
- = Not available.  
2. Available peripherals depend upon package, STM32WB35xx features one SPI, no LCD, no TSC and two wakeup pins. See  
Table 2: STM32WB55xx and STM32WB35xx devices features and peripheral counts for more details.  
3. Bluetooth® Low Energy not possible in this mode.  
4. Standby with SRAM2a retention mode only.  
5. Flash memory programming only possible in Range 1 voltage, not in Range 2 and not in Low Power mode.  
6. The Flash memory can be configured in Power-down mode. By default, it is not in Power-down mode.  
7. The SRAM clock can be gated on or off.  
DS11929 Rev 10  
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57  
Functional overview  
STM32WB55xx STM32WB35xx  
8. SRAM2a content is preserved when the bit RRS is set in PWR_CR3 register.  
9. Stop 0 only. SMPS is automatically switched to Bypass or Open mode during Low power operation.  
10. Some peripherals with wakeup from Stop capability can request HSI16 to be enabled. In this case, HSI16 is woken up by  
the peripheral, and only feeds the peripheral which requested it. HSI16 is automatically put off when the peripheral does not  
need it anymore.  
11. The HSE can be used by the RF subsystem according with the need to perform RF operation (Tx or Rx).  
12. MSI maximum frequency.  
13. In case RF will be used and HSE will fail.  
14. UART and LPUART reception is functional in Stop mode, and generates a wakeup interrupt on Start, address match or  
received frame event.  
15. I2C address detection is functional in Stop mode, and generates a wakeup interrupt in case of address match.  
16. I/Os can be configured with internal pull-up, pull-down or floating in Standby mode.  
17. I/Os can be configured with internal pull-up, pull-down or floating in Shutdown mode but the configuration is lost when  
exiting the Shutdown mode.  
36/193  
DS11929 Rev 10  
Table 8. STM32WB55xx and STM32WB35xx modes overview  
Mode  
Regulator CPU1  
Flash  
SRAM  
Clocks  
DMA and peripherals(1)  
Wakeup source  
Consumption(2)  
Wakeup time  
Range 1  
Yes  
Range 2  
All  
107 µA/MHz  
100 µA/MHz  
Run  
ON(3)(4)  
ON  
Any  
Any  
N/A  
N/A  
All except RNG and USB-FS  
LPRun  
Sleep  
LPR  
Yes  
No  
No  
ON(3)  
ON(3)  
ON(3)  
ON  
except All except RF, RNG and USB-FS  
PLL  
N/A  
103 µA/MHz  
15.33 µs  
9 cycles  
9 cycles  
Range 1  
Range 2  
All  
41 µA/MHz  
46 µA/MHz  
Any interrupt  
or event  
ON(5)  
ON(5)  
Any  
All except RNG and USB-FS  
Any  
Any interrupt  
or event  
LPSleep  
LPR  
All except RF, RNG and USB-FS  
except  
PLL  
45 µA/MHz  
Reset pin, all I/Os,  
RF, BOR, PVD, PVM  
RF, BOR, PVD, PVM  
RTC, LCD, IWDG  
Range 1  
RTC, LCD, IWDG  
COMPx (x=1, 2)  
USART1  
COMPx (x=1, 2)  
LSE,  
USART1(8)  
LSI,  
Stop 0  
No  
OFF  
ON  
100 µA  
1.7 µs  
HSE(6)  
,
LPUART1(8)  
I2Cx (x=1, 3)(9)  
LPUART1  
HSI16(7)  
Range 2  
I2Cx (x=1, 3)  
LPTIMx (x=1, 2)  
USB  
LPTIMx (x=1, 2), SMPS  
All other peripherals are frozen.  
Reset pin, all I/Os  
RF, BOR, PVD, PVM  
RTC, LCD, IWDG  
COMPx (x=1, 2)  
USART1  
RF, BOR, PVD, PVM  
RTC, LCD, IWDG  
COMPx (x=1, 2)  
LSE,  
LSI,  
USART1(8)  
LPUART1(8)  
I2Cx (x=1, 3)(9)  
9.2 µA w/o RTC  
9.6 µA w RTC  
Stop 1  
LPR  
No  
OFF  
ON  
4.7 µs  
HSE(6)  
,
HSI16(7)  
LPUART1  
I2Cx (x=1, 3)  
LPTIMx (x=1, 2)  
USB  
LPTIMx (x=1, 2)  
All other peripherals are frozen.  
 
 
Table 8. STM32WB55xx and STM32WB35xx modes overview (continued)  
Mode  
Regulator CPU1  
Flash  
SRAM  
Clocks  
DMA and peripherals(1)  
Wakeup source  
Consumption(2)  
Wakeup time  
RF, BOR, PVD, PVM  
RTC, LCD, IWDG  
COMPx (x=1, 2)  
LPUART1(8)  
Reset pin, all I/Os  
RF, BOR, PVD, PVM  
RTC, LCD, IWDG  
COMPx (x=1, 2)  
LPUART1  
1.85 µA w/o RTC  
2.1 µA w RTC  
LSE,  
LSI  
Stop 2  
LPR  
No  
OFF  
ON  
5.71 µs  
I2C3(9)  
LPTIM1  
I2C3  
All other peripherals are frozen.  
LPTIM1  
RF, BOR, RTC, IWDG  
0.32 µA w/o RTC  
0.60 µA w RTC  
SRAM2a  
ON(10)  
LPR  
OFF  
RF, Reset pin  
5 I/Os (WKUPx)(11)  
BOR, RTC, IWDG  
All other peripherals are  
powered off.  
LSE,  
LSI  
Standby  
No  
No  
OFF  
OFF  
51 µs  
0.11 µA w/o RTC  
0.390 µA w RTC  
I/O configuration can be floating,  
pull-up or pull-down  
OFF  
RTC  
All other peripherals are  
powered off.  
5 I/Os (WKUPx)(11)  
RTC  
,
0.028 µA w/o RTC  
0.315 µA w/ RTC  
Shutdown  
OFF  
OFF  
LSE  
-
I/O configuration can be floating,  
pull-up or pull-down(12)  
1. Available peripherals depend upon package, STM32WB35xx features one SPI, no LCD, no TSC and two wakeup pins. See Table 2: STM32WB55xx and STM32WB35xx  
devices features and peripheral counts for more details.  
2. Typical current at VDD = 1.8 V, 25 °C. for STOPx, SHUTDOWN and Standby, else VDD = 3.3 V, 25 °C.  
3. The Flash memory controller can be placed in power-down mode if the RF subsystem is not in use and all the program is run from the SRAM.  
4. Flash memory programming is only possible in Range 2 voltage.  
5. The SRAM1 and SRAM2 clocks can be gated off independently.  
6. HSE (32 MHz) automatically used when RF activity is needed by the RF subsystem.  
7. HSI16 (16 MHz) automatically used by some peripherals.  
8. U(S)ART and LPUART reception is functional in Stop mode, and generates a wakeup interrupt on Start, Address match or Received frame event.  
9. I2C address detection is functional in Stop mode, and generates a wakeup interrupt in case of address match.  
10. SRAM1 and SRAM2b are OFF.  
11. I/Os with wakeup from Standby/Shutdown capability: PA0, PC13, PC12, PA2, PC5.  
12. I/Os can be configured with internal pull-up, pull-down or floating but the configuration is lost immediately when exiting the Shutdown mode.  
 
STM32WB55xx STM32WB35xx  
Functional overview  
3.7.6  
Reset mode  
To improve the consumption under reset, the I/Os state under and after reset is “analog  
state” (the I/O Schmitt trigger is disabled). In addition, the internal reset pull-up is  
deactivated when the reset source is internal.  
3.8  
VBAT operation  
The VBAT pin allows to power the device VBAT domain (RTC, LSE and Backup registers)  
from an external battery, an external supercapacitor, or from V when no external battery  
DD  
nor an external supercapacitor are present. Three anti-tamper detection pins are available  
in VBAT mode.  
VBAT operation is automatically activated when V is not present.  
DD  
An internal VBAT battery charging circuit is embedded and can be activated when V is  
DD  
present.  
Note:  
When the microcontroller is supplied only from VBAT, external interrupts and RTC  
alarm/events do not exit it from VBAT operation.  
3.9  
Interconnect matrix  
Several peripherals have direct connections between them. This allows autonomous  
communication between peripherals, saving CPU1 resources and, consequently, reducing  
power supply consumption. In addition, these hardware connections result in fast and  
predictable latency.  
Depending on peripherals, these interconnections can operate in Run, Sleep, Low-power  
run and Sleep, Stop 0, Stop 1 and Stop 2 modes.  
Table 9. STM32WB55xx and STM32WB35xx CPU1 peripherals interconnect matrix  
Source  
Destination  
Action  
TIMx  
ADC1  
DMA  
Timers synchronization or chaining  
Conversion triggers  
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
-
-
-
-
-
-
-
-
TIMx  
Memory to memory transfer trigger  
Comparator output blanking  
COMPx  
TIM1  
TIM2  
Timer input channel, trigger, break  
from analog signals comparison  
Y
Y
Y
Y
-
-
COMPx  
ADC1  
Low-power timer triggered by analog  
signals comparison  
LPTIMERx  
TIM1  
Y
Y
Y
Y
Y
Y
Y
Y
Y
-
Y(1)  
-
Timer triggered by analog watchdog  
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Functional overview  
STM32WB55xx STM32WB35xx  
Table 9. STM32WB55xx and STM32WB35xx CPU1 peripherals interconnect matrix (continued)  
Source  
Destination  
Action  
TIM16  
Timer input channel from RTC events  
Y
Y
Y
Y
Y
Y
Y
Y
-
-
RTC  
Low-power timer triggered by RTC  
alarms or tampers  
LPTIMERx  
Y
Y(1)  
All clock sources  
(internal and external)  
TIM2  
TIM16, 17  
Clock source used as input channel  
for RC measurement and trimming  
Y
Y
Y
Y
Y
-
Y
-
-
-
-
-
USB  
TIM2  
Timer triggered by USB SOF  
CSS  
CPU (hard fault)  
SRAM (parity error)  
Flash memory (ECC error)  
COMPx  
TIM1  
TIM16,17  
Timer break  
Y
Y
Y
Y
-
-
PVD  
TIMx  
External trigger  
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
-
Y
-
-
Y(1)  
-
GPIO  
LPTIMERx External trigger  
ADC1 Conversion external trigger  
1. LPTIM1 only.  
40/193  
DS11929 Rev 10  
STM32WB55xx STM32WB35xx  
Functional overview  
3.10  
Clocks and startup  
The STM32WB55xx and STM32WB35xx devices integrate several clock sources:  
LSE: 32.768 kHz external oscillator, for accurate RTC and calibration with other  
embedded RC oscillators  
LSI1: 32 kHz on-chip low-consumption RC oscillator  
LSI2: almost 32 kHz, on-chip high-stability RC oscillator, used by the RF subsystem  
HSE: high quality 32 MHz external oscillator with trimming, needed by the RF  
subsystem  
HSI16: 16 MHz high accuracy on-chip RC oscillator  
MSI: 100 kHz to 48 MHz multiple speed on-chip low power oscillator, can be trimmed  
using the LSE signal  
HSI48: 48 MHz on-chip RC oscillator, for USB crystal-less purpose  
The clock controller (see Figure 9) distributes the clocks coming from the different  
oscillators to the core and the peripherals including the RF subsystem. It also manages  
clock gating for low power modes and ensures clock robustness. It features:  
Clock prescaler: to get the best trade-off between speed and current consumption,  
the clock frequency to the CPU and peripherals can be adjusted by a programmable  
prescaler  
Safe clock switching: clock sources can be changed safely on the fly in run mode  
through a configuration register.  
Clock management: to reduce power consumption, the clock controller can stop the  
clock to the core, individual peripherals or memory.  
System clock source: four different clock sources can be used to drive the master  
clock SYSCLK:  
16 MHz high-speed internal RC oscillator (HSI16), trimmable by software, that can  
supply a PLL  
Multispeed internal RC oscillator (MSI), trimmable by software, able to generate  
12 frequencies from 100 kHz to 48 MHz. When a 32.768 kHz clock source is  
available in the system (LSE), the MSI frequency can be automatically trimmed by  
hardware to reach better than ±0.25% accuracy. The MSI can supply a PLL.  
System PLL that can be fed by HSE, HSI16 or MSI, with a maximum frequency of  
64 MHz.  
Auxiliary clock source: two ultralow-power clock sources that can be used to drive  
the LCD controller and the real-time clock:  
32.768 kHz low-speed external crystal (LSE), supporting four drive capability  
modes. The LSE can also be configured in bypass mode for an external clock.  
32 kHz low-speed internal RC (LSI), also used to drive the independent watchdog.  
The LSI clock accuracy is ±5%. The LSI source can be either the LSI1 or the LSI2  
on-chip oscillator.  
Peripheral clock sources: Several peripherals (RNG, SAI, USARTs, I2Cs, LPTimers,  
ADC) have their own independent clock whatever the system clock. Two PLLs, each  
DS11929 Rev 10  
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57  
 
Functional overview  
STM32WB55xx STM32WB35xx  
having three independent outputs for the highest flexibility, can generate independent  
clocks for the ADC, the RNG and the SAI.  
Startup clock: after reset, the microcontroller restarts by default with an internal 4 MHz  
clock (MSI). The prescaler ratio and clock source can be changed by the application  
program as soon as the code execution starts.  
Clock security system (CSS): this feature can be enabled by software. If an HSE  
clock failure occurs, the master clock is automatically switched to HSI16 and a software  
interrupt is generated if enabled. LSE failure can also be detected and an interrupt  
generated.  
Clock-out capability:  
MCO: microcontroller clock output: it outputs one of the internal clocks for  
external use by the application. Low frequency clocks (LSIx, LSE) are available  
down to Stop 1 low power state.  
LSCO: low speed clock output: it outputs LSI or LSE in all low-power modes  
down to Standby.  
Several prescalers allow the user to configure the AHB frequencies, the high speed APB  
(APB2) and the low speed APB (APB1) domains. The maximum frequency of the AHB and  
the APB domains is 64 MHz.  
42/193  
DS11929 Rev 10  
STM32WB55xx STM32WB35xx  
Functional overview  
Figure 9. Clock tree  
LSI1 RCC 32 kHz  
to IWDG  
LSI  
LSI2 RCC 32 kHz  
LSCO  
LSI  
to RTC and LCD(1)  
to BLE wakeup  
LSE  
LSE OSC  
32.768 kHz  
OSC32_OUT  
LSE  
OSC32_IN  
to 802.15.4 wakeup  
LSE CSS  
LSI1  
/32  
CPU1  
HPRE  
/1,2,...,512  
to CPU1, AHB1, AHB2, AHB3, and SRAM1  
to CPU1 FCLK  
LSI2  
HCLK1  
/32  
LSE  
to CPU1 system timer  
/8  
HSE  
MCO  
SYSCLK  
PLLRCLK  
HSI16  
/1 - 16  
APB1  
PCLK1  
x1 or  
to APB1  
PPRE1  
SYS clock  
/1,2,4,8,16  
to APB1 TIMx  
source control  
x2  
MSI  
PLLRCLK  
APB2  
PPRE2  
/1,2,4,8,16  
PCLK2  
to APB2  
RC48  
HSI16  
HSE  
HSE OSC  
32 MHz  
to APB2 TIMx  
OSC_OUT  
OSC_IN  
x1 or  
x2  
SYSCLK  
HSEPRE/1,2  
CPU2  
C2HPRE  
1,2,...,512  
to CPU2  
MSI  
HCLK2  
HSE CSS  
to CPU2 FCLK  
HSI16 RC  
16 MHz  
to CPU2 system timer  
/8  
MSI RC  
AHB4  
to AHB4, Flash memory, SRAM2  
HCLK4  
HCLK5  
100 kHz - 48 MHz  
SHDHPRE  
/1,2,...,512  
HSI48 RC  
48 MHz  
to APB3  
to AHB5  
MSI  
HSI16  
HSE  
HSI16  
/2  
/M  
to RF  
to  
HSI16  
PLL  
MSI  
SMPS  
PLLPCLK  
SMPSDIV  
xN  
/P  
/Q  
/R  
/2  
MSI  
HSI48  
to USB  
/1,2,3,4,6,8,12  
HSE  
PLLQCLK  
PLLRCLK  
/3  
PCLKn  
SYSCLK  
HSI16  
to RNG  
SMPS clock  
source control  
LSI  
LSE  
to SAI1  
to USART1  
HSI16  
PLLSAI1  
to LPUART1  
PLLSAI1PCLK  
PLLSAI1QCLK  
PLLSAI1RCLK  
LSE  
xN  
/P  
/Q  
/R  
SAI1_EXTCLK  
PCLKn  
HSI16  
LSI  
PCLKn  
SYSCLK  
HSI16  
to LPTIMx  
to ADC1  
to I2Cx  
SYSCLK  
LSE  
MS45402V7  
1. The LCD is not available on STM32WB35xx devices.  
3.11  
General-purpose inputs/outputs (GPIOs)  
Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as  
input (with or without pull-up or pull-down) or as peripheral alternate function. Most of the  
GPIO pins are shared with digital or analog alternate functions. Fast I/O toggling can be  
achieved thanks to their mapping on the AHB2 bus.  
DS11929 Rev 10  
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57  
 
 
 
Functional overview  
STM32WB55xx STM32WB35xx  
The I/Os alternate function configuration can be locked, if needed, following a specific  
sequence in order to avoid spurious writing to the I/Os registers.  
3.12  
Direct memory access controller (DMA)  
The device embeds two DMAs. Refer to Table 10 for the features implementation.  
Direct memory access (DMA) is used to provide high-speed data transfer between  
peripherals and memory as well as between memories. Data can be quickly moved by DMA  
without any CPU action. This keeps CPU resources free for other operations.  
The two DMA controllers have fourteen channels in total, a full cross matrix allows any  
peripheral to be mapped on any of the available DMA channels. Each DMA has an arbiter  
for handling the priority between DMA requests.  
The DMA supports:  
fourteen independently configurable channels (requests)  
A full cross matrix between peripherals and all the DMA channels exist. There is also a  
HW trigger possibility through the DMAMUX.  
Priorities between requests from DMA channels are software programmable (four  
levels consisting in very high, high, medium and low) or hardware in case of equality  
(request 1 has priority over request 2, etc.).  
Independent source and destination transfer size (byte, half word, word), emulating  
packing and unpacking. Source/destination addresses must be aligned on the data  
size.  
Support for circular buffer management.  
Three event flags (DMA half transfer, DMA transfer complete and DMA transfer error)  
logically OR-ed together in a single interrupt request for each channel.  
Memory-to-memory transfer.  
Peripheral-to-memory and memory-to-peripheral, and peripheral-to-peripheral  
transfers.  
Access to Flash memory, SRAM, APB and AHB peripherals as source and destination.  
Programmable number of data to be transferred: up to 65536.  
Table 10. DMA implementation  
DMA features  
DMA1  
7
DMA2  
7
Number of regular channels  
A DMAMUX block makes it possible to route any peripheral source to any DMA channel.  
3.13  
Interrupts and events  
3.13.1  
Nested vectored interrupt controller (NVIC)  
The devices embed a nested vectored interrupt controller able to manage 16 priority levels,  
and handle up to 63 maskable interrupt channels plus the 16 interrupt lines of the   
®
Cortex -M4 with FPU.  
44/193  
DS11929 Rev 10  
 
 
 
 
STM32WB55xx STM32WB35xx  
Functional overview  
The NVIC benefits are the following:  
Closely coupled NVIC gives low latency interrupt processing  
Interrupt entry vector table address passed directly to the core  
Allows early processing of interrupts  
Processing of late arriving higher priority interrupts  
Support for tail chaining  
Processor state automatically saved  
Interrupt entry restored on interrupt exit with no instruction overhead  
The NVIC hardware block provides flexible interrupt management features with minimal  
interrupt latency.  
3.13.2  
Extended interrupts and events controller (EXTI)  
The EXTI manages wakeup through configurable and direct event inputs. It provides   
wake-up requests to the Power control, and generates interrupt requests to the CPUx NVIC  
and events to the CPUx event input.  
Configurable events/interrupts come from peripherals able to generate a pulse, and make it  
possible to select the Event/Interrupt trigger edge and/or a SW trigger.  
Direct events/interrupts are coming from peripherals having their own clearing mechanism.  
3.14  
Analog to digital converter (ADC)  
The device embeds a successive approximation analog-to-digital converter with the  
following features:  
12-bit native resolution, with built-in calibration  
Up to 16-bit resolution with 256 oversampling ratio  
4.26 Msps maximum conversion rate with full resolution  
Down to 39 ns sampling time  
Increased conversion rate for lower resolution (up to 7.11 Msps for 6-bit  
resolution)  
Up to sixteen external channels and three internal channels: internal reference  
voltages, temperature sensor  
Single-ended and differential mode inputs  
Low-power design  
Capable of low-current operation at low conversion rate (consumption decreases  
linearly with speed)  
Dual clock domain architecture: ADC speed independent from CPU frequency  
Highly versatile digital interface  
Single-shot or continuous/discontinuous sequencer-based scan mode: two groups  
of analog signals conversions can be programmed to differentiate background and  
high-priority real-time conversions  
The ADC supports multiple trigger inputs for synchronization with on-chip timers  
and external signals  
Results stored into three data register or in SRAM with DMA controller support  
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STM32WB55xx STM32WB35xx  
Data pre-processing: left/right alignment and per channel offset compensation  
Built-in oversampling unit for enhanced SNR  
Channel-wise programmable sampling time  
Three analog watchdog for automatic voltage monitoring, generating interrupts  
and trigger for selected timers  
Hardware assistant to prepare the context of the injected channels to allow fast  
context switching  
3.14.1  
Temperature sensor  
The temperature sensor (TS) generates a voltage V that varies linearly with temperature.  
TS  
The temperature sensor is internally connected to the ADC1_IN17 input channel, which is  
used to convert the sensor output voltage into a digital value.  
To improve the accuracy of the temperature sensor measurement, each device is  
individually factory-calibrated by ST. The temperature sensor factory calibration data are  
stored in the system memory area, accessible in read-only mode.  
Table 11. Temperature sensor calibration values  
Calibration value name  
Description  
Memory address  
TS ADC raw data acquired at a  
temperature of 30 °C (± 5 °C),  
VDDA = VREF+ = 3.0 V (± 10 mV)  
TS_CAL1  
0x1FFF 75A8 - 0x1FFF 75A9  
TS ADC raw data acquired at a  
temperature of 130 °C (± 5 °C),  
TS_CAL2  
0x1FFF 75CA - 0x1FFF 75CB  
VDDA = VREF+ = 3.0 V (± 10 mV)  
3.14.2  
Internal voltage reference (V  
)
REFINT  
The internal voltage reference (VREFINT) provides a stable (bandgap) voltage output for  
the ADC and the comparators. VREFINT is internally connected to the ADC1_IN0 input  
channel. The precise voltage of VREFINT is individually measured for each part by ST  
during production test and stored in the system memory area. It is accessible in read-only  
mode.  
Table 12. Internal voltage reference calibration values  
Calibration value name  
Description  
Memory address  
Raw data acquired at a  
VREFINT  
temperature of 30 °C (± 5 °C),  
0x1FFF 75AA - 0x1FFF 75AB  
VDDA = VREF+ = 3.6 V (± 10 mV)  
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STM32WB55xx STM32WB35xx  
Functional overview  
3.15  
Voltage reference buffer (VREFBUF)  
The STM32WB55xx devices embed a voltage reference buffer that can be used as voltage  
reference for the ADC and also as voltage reference for external components through the  
VREF+ pin. The internal voltage reference buffer supports two voltages:  
2.048 V  
2.5 V  
An external voltage reference can be provided through the VREF+ pin when the internal  
voltage reference buffer is off. The VREF+ pin is double-bonded with VDDA on UFQFPN48  
package, hence the internal voltage reference buffer is not available on a dedicated pin, but  
user can still use the V  
value.  
DDA  
3.16  
Comparators (COMP)  
The STM32WB55xx and STM32WB35xx devices embed two rail-to-rail comparators with  
programmable reference voltage (internal or external), hysteresis and speed (low speed for  
low-power) and with selectable output polarity.  
The reference voltage can be one of the following:  
External I/O  
Internal reference voltage or submultiple (1/4, 1/2, 3/4).  
All comparators can wake up from Stop mode, generate interrupts and breaks for the timers  
and can be also combined into a window comparator.  
3.17  
Touch sensing controller (TSC)  
The touch sensing controller provides a simple solution for adding capacitive sensing  
functionality to any application. Capacitive sensing technology is able to detect finger  
presence near an electrode which is protected from direct touch by a dielectric such as  
glass or plastic. The capacitive variation introduced by the finger (or any conductive object)  
is measured using a proven implementation based on a surface charge transfer acquisition  
principle.  
The touch sensing controller is fully supported by the STMTouch touch sensing firmware  
library (free to use) and enables reliable touch sensing functionality in the end application.  
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Functional overview  
STM32WB55xx STM32WB35xx  
The main features of the touch sensing controller are the following:  
Proven and robust surface charge transfer acquisition principle  
Supports up to 18 capacitive sensing channels  
Up to six capacitive sensing channels can be acquired in parallel offering a very good  
response time  
Spread spectrum feature to improve system robustness in noisy environments  
Full hardware management of the charge transfer acquisition sequence  
Programmable charge transfer frequency  
Programmable sampling capacitor I/O pin  
Programmable channel I/O pin  
Programmable max count value to avoid long acquisition when a channel is faulty  
Dedicated end of acquisition and max count error flags with interrupt capability  
One sampling capacitor for up to three capacitive sensing channels to reduce the  
system components  
Compatible with proximity, touchkey, linear and rotary touch sensor implementation  
Designed to operate with STMTouch touch sensing firmware library  
Note:  
The number of capacitive sensing channels is dependent upon the package (not available  
on QFPN48) and subject to I/O availability.  
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3.18  
Liquid crystal display controller (LCD)  
The STM32WB55xx devices embed an LCD controller with the following characteristics:  
Highly flexible frame rate control.  
Supports Static, 1/2, 1/3, 1/4 and 1/8 duty.  
Supports Static, 1/2, 1/3 and 1/4 bias.  
Double buffered memory allows data in LCD_RAM registers to be updated at any time  
by the application firmware without affecting the integrity of the data displayed.  
LCD data RAM of up to 16 x 32-bit registers which contain pixel information  
(active/inactive)  
Software selectable LCD output voltage (contrast) from VLCD  
No need for external analog components:  
to VLCD  
.
max  
min  
A step-up converter is embedded to generate an internal VLCD voltage higher  
than V (up to 3.6 V if V > 2.0 V)  
DD  
DD  
Software selection between external and internal VLCD voltage source. In case of  
an external source, the internal boost circuit is disabled to reduce power  
consumption  
A resistive network is embedded to generate intermediate VLCD voltages  
The structure of the resistive network is configurable by software to adapt the  
power consumption to match the capacitive charge required by the LCD panel  
Integrated voltage output buffers for higher LCD driving capability.  
The contrast can be adjusted using two different methods:  
When using the internal step-up converter, the software can adjust VLCD between  
VLCD and VLCD  
min  
max  
Programmable dead time (up to eight phase periods) between frames.  
Full support of low-power modes: the LCD controller can be displayed in Sleep,   
Low-power run, Low-power sleep and Stop modes, or can be fully disabled to reduce  
power consumption.  
Built in phase inversion for reduced power consumption and EMI (electromagnetic  
interference).  
Start of frame interrupt to synchronize the software when updating the LCD data RAM.  
Blink capability:  
1, 2, 3, 4, 8 or all pixels can be programmed to blink at a configurable frequency  
Software adjustable blink frequency to achieve around 0.5 Hz, 1 Hz, 2 Hz or 4 Hz.  
Used LCD segment and common pins should be configured as GPIO alternate functions  
and unused segment and common pins can be used for general purpose I/O or for another  
peripheral alternate function.  
Note:  
When the LCD relies on the internal step-up converter, the VLCD pin should be connected  
to V with a capacitor. Its typical value is 1 μF.  
SS  
3.19  
True random number generator (RNG)  
The devices embed a true RNG that delivers 32-bit random numbers generated by an  
integrated analog circuit.  
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3.20  
Timers and watchdogs  
The STM32WB55xx and STM32WB35xx include one advanced 16-bit timer, one general-  
purpose 32-bit timer, two 16-bit basic timers, two low-power timers, two watchdog timers  
and a SysTick timer. Table 13 compares the features of the advanced control, general  
purpose and basic timers.  
Table 13. Timer features  
DMA  
request  
generation  
Capture/  
compare  
channels  
Timer  
type  
Counter  
resolution  
Counter  
type  
Prescaler  
factor  
Complementary  
outputs  
Timer  
Advanced  
control  
Up, down,  
Up/down  
TIM1  
TIM2  
16-bits  
32-bits  
16-bits  
16-bits  
16-bits  
4
4
2
2
1
3
No  
1
General  
purpose  
Up, down,  
Up/down  
Any integer  
between 1  
and 65536  
General  
purpose  
TIM16  
TIM17  
Up  
Up  
Up  
Yes  
General  
purpose  
1
LPTIM1  
LPTIM2  
Low power  
1
3.20.1  
Advanced-control timer (TIM1)  
The advanced-control timer can be seen as a three-phase PWM multiplexed on six  
channels. They have complementary PWM outputs with programmable inserted   
dead-times. They can also be seen as complete general-purpose timers. The four  
independent channels can be used for:  
Input capture  
Output compare  
PWM generation (edge or center-aligned modes) with full modulation capability (0 to  
100%)  
One-pulse mode output  
In debug mode, the advanced-control timer counter can be frozen and the PWM outputs  
disabled to turn off any power switches driven by these outputs.  
Many features are shared with those of the general-purpose TIMx timers (described in  
Section 3.20.2) using the same architecture, so the advanced-control timers can work  
together with the TIMx timers via the Timer Link feature for synchronization or event  
chaining.  
3.20.2  
General-purpose timers (TIM2, TIM16, TIM17)  
There are up to three synchronizable general-purpose timers embedded in the  
STM32WB55xx and STM32WB35xx (see Table 13 for differences). Each general-purpose  
timer can be used to generate PWM outputs, or act as a simple time base.  
TIM2  
Full-featured general-purpose timer  
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Functional overview  
Features four independent channels for input capture/output compare, PWM or  
one-pulse mode output. Can work together, or with the other general-purpose  
timers via the Timer Link feature for synchronization or event chaining.  
The counter can be frozen in debug mode.  
Independent DMA request generation, support of quadrature encoders.  
TIM16 and TIM17  
General-purpose timers with mid-range features:  
16-bit auto-reload upcounters and 16-bit prescalers.  
1 channel and 1 complementary channel.  
All channels can be used for input capture/output compare, PWM or one-pulse  
mode output.  
The timers can work together via the Timer Link feature for synchronization or  
event chaining. The timers have independent DMA request generation.  
The counters can be frozen in debug mode.  
3.20.3  
Low-power timer (LPTIM1 and LPTIM2)  
The devices embed two low-power timers, having an independent clock running in Stop  
mode if they are clocked by LSE, LSIx or by an external clock. They are able to wakeup the  
system from Stop mode.  
LPTIM1 is active in Stop 0, Stop 1 and Stop 2 modes.  
LPTIM2 is active in Stop 0 and Stop 1 modes.  
The low-power timers support the following features:  
16-bit up counter with 16-bit autoreload register  
16-bit compare register  
Configurable output: pulse, PWM  
Continuous/ one shot mode  
Selectable software/hardware input trigger  
Selectable clock source  
Internal clock sources: LSE, either LSI1 or LSI2, HSI16 or APB clock  
External clock source over LPTIM input (working even with no internal clock  
source running, used by pulse counter application)  
Programmable digital glitch filter  
Encoder mode (LPTIM1 only)  
3.20.4  
Independent watchdog (IWDG)  
The independent watchdog is based on a 12-bit downcounter and an 8-bit prescaler. It is  
clocked from an independent 32 kHz internal RC (LSI) and as it operates independently  
from the main clock, it can operate in Stop and Standby modes. It can be used either as a  
watchdog to reset the device when a problem occurs, or as a free running timer for  
application timeout management. It is hardware or software configurable through the option  
bytes. The counter can be frozen in debug mode.  
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3.20.5  
System window watchdog (WWDG)  
The window watchdog is based on a 7-bit downcounter that can be set as free running. It  
can be used as a watchdog to reset the device when a problem occurs. It is clocked from  
the main clock. It has an early warning interrupt capability and the counter can be frozen in  
debug mode.  
3.20.6  
SysTick timer  
This timer is dedicated to real-time operating systems, but could also be used as a standard  
down counter. It features:  
a 24-bit down counter  
autoreload capability  
a maskable system interrupt generation when the counter reaches 0  
a programmable clock source.  
3.21  
Real-time clock (RTC) and backup registers  
The RTC is an independent BCD timer/counter, supporting the following features:  
Calendar with subsecond, seconds, minutes, hours (12 or 24 format), week day, date,  
month, year, in BCD (binary-coded decimal) format.  
Automatic correction for 28, 29 (leap year), 30, and 31 days of the month.  
Two programmable alarms.  
On-the-fly correction from 1 to 32767 RTC clock pulses. This can be used to  
synchronize it with a master clock.  
Reference clock detection: a more precise second source clock (50 or 60 Hz) can be  
used to enhance the calendar precision.  
Digital calibration circuit with 0.95 ppm resolution, to compensate for quartz crystal  
inaccuracy.  
Three anti-tamper detection pins with programmable filter.  
Timestamp feature, which can be used to save the calendar content. This function can  
be triggered by an event on the timestamp pin, or by a tamper event, or by a switch to  
VBAT mode.  
17-bit auto-reload wakeup timer (WUT) for periodic events with programmable  
resolution and period.  
The RTC and the 20 backup registers are supplied through a switch that takes power either  
from the V supply (when present) or from the VBAT pin.  
DD  
The backup registers are 32-bit registers used to store 80 bytes of user application data  
when V power is not present. They are not reset by a system or power reset, or when the  
DD  
device wakes up from Standby or Shutdown mode.  
The RTC clock sources can be:  
a 32.768 kHz external crystal (LSE)  
an external resonator or oscillator (LSE)  
one of the internal low power RC oscillators (LSI1 or LSI2, with typical frequency of  
32 kHz)  
the high-speed external clock (HSE) divided by 32.  
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Functional overview  
The RTC is functional in VBAT mode and in all low-power modes when it is clocked by the  
LSE. When clocked by one of the LSIs, the RTC is not functional in VBAT mode, but is  
functional in all low-power modes except Shutdown mode.  
All RTC events (Alarm, WakeUp Timer, Timestamp or Tamper) can generate an interrupt  
and wakeup the device from the low-power modes.  
3.22  
Inter-integrated circuit interface (I2C)  
The devices embed two I2Cs. Refer to Table 14 for the features implementation.  
2
The I C bus interface handles communications between the microcontroller and the serial  
2
2
I C bus. It controls all I C bus-specific sequencing, protocol, arbitration and timing.  
The I2C peripheral supports:  
I2C-bus specification and user manual rev. 5 compatibility:  
Slave and master modes, multimaster capability  
Standard-mode (Sm), with a bitrate up to 100 kbit/s  
Fast-mode (Fm), with a bitrate up to 400 kbit/s  
Fast-mode Plus (Fm+), with a bitrate up to 1 Mbit/s and 20 mA output drive I/Os  
7-bit and 10-bit addressing mode, multiple 7-bit slave addresses  
Programmable setup and hold times  
Optional clock stretching  
System Management Bus (SMBus) specification rev 2.0 compatibility:  
Hardware PEC (packet error checking) generation and verification with ACK  
control  
Address resolution protocol (ARP) support  
SMBus alert  
Power System Management Protocol (PMBus ) specification rev 1.1 compatibility  
Independent clock: a choice of independent clock sources allowing the I2C  
communication speed to be independent from the PCLK reprogramming. Refer to  
Figure 9: Clock tree.  
Wakeup from Stop mode on address match  
Programmable analog and digital noise filters  
1-byte buffer with DMA capability  
Table 14. I2C implementation  
I2C features(1)  
I2C1  
I2C3  
Standard-mode (up to 100 kbit/s)  
X
X
X
X
X
X
X
X
X
X
Fast-mode (up to 400 kbit/s)  
Fast-mode Plus with 20 mA output drive I/Os (up to 1 Mbit/s)  
Programmable analog and digital noise filters  
SMBus/PMBus hardware support  
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Table 14. I2C implementation (continued)  
I2C features(1)  
I2C1  
I2C3  
Independent clock  
X
X
-
X
X
X
Wakeup from Stop 0 / Stop 1 mode on address match  
Wakeup from Stop 2 mode on address match  
1. X: supported  
3.23  
Universal synchronous/asynchronous receiver transmitter  
(USART)  
The devices embed one universal synchronous receiver transmitter.  
This interface provides asynchronous communication, IrDA SIR ENDEC support,  
multiprocessor communication mode, single-wire half-duplex communication mode and has  
LIN Master/Slave capability. It provides hardware management of the CTS and RTS signals,  
and RS485 driver enable.  
The USART is able to communicate at speeds of up to 4 Mbit/s, and also provides Smart  
Card mode (ISO 7816 compliant) and SPI-like communication capability.  
The USART supports synchronous operation (SPI mode), and can be used as an SPI  
master.  
The USART has a clock domain independent from the CPU clock, allowing it to wake up the  
MCU from Stop mode using baudrates up to 200 kbaud. The wake up events from Stop  
mode are programmable and can be:  
the start bit detection  
any received data frame  
a specific programmed data frame.  
The USART interface can be served by the DMA controller.  
3.24  
Low-power universal asynchronous receiver transmitter  
(LPUART)  
The device embeds one Low-Power UART, enabling asynchronous serial communication  
with minimum power consumption. The LPUART supports half duplex single wire  
communication and modem operations (CTS/RTS), allowing multiprocessor  
communication.  
The LPUART has a clock domain independent from the CPU clock, and can wakeup the  
system from Stop mode using baudrates up to 220 kbaud. The wake up events from Stop  
mode are programmable and can be:  
the start bit detection  
any received data frame  
a specific programmed data frame.  
Only a 32.768 kHz clock (LSE) is needed for LPUART communication up to 9600 baud.  
Therefore, even in Stop mode, the LPUART can wait for an incoming frame while having an  
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Functional overview  
extremely low energy consumption. Higher speed clock can be used to reach higher  
baudrates.  
The LPUART interfaces can be served by the DMA controller.  
3.25  
3.26  
Serial peripheral interface (SPI1, SPI2)  
Two SPI interfaces enable communication up to 32 Mbit/s in master and up to 24 Mbit/s in  
slave modes, in half-duplex, full-duplex and simplex modes. The 3-bit prescaler gives 8  
master mode frequencies and the frame size is configurable from 4 bits to 16 bits. The SPI  
interfaces support NSS pulse mode, TI mode and Hardware CRC calculation.  
The SPI interfaces can be served by the DMA controller.  
Serial audio interfaces (SAI1)  
The device embeds a dual channel SAI peripheral that supports full duplex audio operation.  
The SAI bus interface handles communications between the microcontroller and the serial  
audio protocol.  
The SAI peripheral supports:  
One independent audio sub-block that can be a transmitter or a receiver, with the  
respective FIFO  
8-word integrated FIFOs  
Synchronous or asynchronous mode  
Master or slave configuration  
Clock generator to target independent audio frequency sampling when audio sub-block  
is configured in master mode  
Data size configurable: 8-, 10-, 16-, 20-, 24-, 32-bit  
Peripheral with large configurability and flexibility allowing to target as example the  
following audio protocol: I2S, LSB or MSB-justified, PCM/DSP, TDM, AC’97 and SPDIF  
out  
Up to 16 slots available with configurable size and with the possibility to select which  
ones are active in the audio frame  
Number of bits by frame may be configurable  
Frame synchronization active level configurable (offset, bit length, level)  
First active bit position in the slot is configurable  
LSB first or MSB first for data transfer  
Mute mode  
Stereo/Mono audio frame capability  
Communication clock strobing edge configurable (SCK)  
Error flags with associated interrupts if enabled respectively  
Overrun and underrun detection  
Anticipated frame synchronization signal detection in slave mode  
Late frame synchronization signal detection in slave mode  
Codec not ready for the AC’97 mode in reception  
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STM32WB55xx STM32WB35xx  
Interruption sources when enabled:  
Errors  
FIFO requests  
DMA interface with two dedicated channels to handle access to the dedicated  
integrated FIFO of the SAI audio sub-block.  
The PDM (Pulse Density Modulation) block allows the user to manage up to three digital  
microphone pairs (with two different clocks). This block performs Right and Left microphone   
de-interleaving and time alignment through programmable delay lines in order to properly  
feed the SAI.  
3.27  
Quad-SPI memory interface (QUADSPI)  
The Quad-SPI is a specialized communication interface targeting single, dual or quad SPI  
Flash memories. It can operate in any of the three following modes:  
Indirect mode: all the operations are performed using the QUADSPI registers  
Status polling mode: the external memory status register is periodically read and an  
interrupt can be generated in case of flag setting  
Memory-mapped mode: the external Flash memory is mapped and is seen by the  
system as if it were an internal memory. This mode can be used for the Execute In  
Place (XIP)  
The Quad-SPI interface supports:  
Three functional modes: indirect, status-polling, and memory-mapped  
SDR and DDR support  
Fully programmable opcode for both indirect and memory mapped mode  
Fully programmable frame format for both indirect and memory mapped mode  
Each of the five following phases can be configured independently (enable, length,  
single/dual/quad communication)  
Instruction phase  
Address phase  
Alternate bytes phase  
Dummy cycles phase  
Data phase  
Integrated FIFO for reception and transmission  
8, 16, and 32-bit data accesses are allowed  
DMA channel for indirect mode operations  
Programmable masking for external Flash memory flag management  
Timeout management  
Interrupt generation on FIFO threshold, timeout, status match, operation complete, and  
access error  
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Functional overview  
3.28  
Development support  
3.28.1  
Serial wire JTAG debug port (SWJ-DP)  
®
The Arm SWJ-DP interface is embedded, and is a combined JTAG and serial wire debug  
port that enables either a serial wire debug or a JTAG probe to be connected to the target.  
Debug is performed using only two pins instead of the five required by the JTAG (JTAG pins  
can then be reused as GPIOs with alternate function): the JTAG TMS and TCK pins are  
shared with SWDIO and SWCLK, respectively, and a specific sequence on the TMS pin is  
used to switch between JTAG-DP and SW-DP.  
3.28.2  
Embedded Trace Macrocell™  
®
The Arm Embedded Trace Macrocell provides a greater visibility of the instruction and data  
flow inside the CPU core by streaming compressed data at a very high rate from the  
STM32WB55xx through a small number of ETM pins to an external hardware trace port  
analyzer (TPA) device. Real-time instruction and data flow activity be recorded and then  
formatted for display on the host computer that runs the debugger software. TPA hardware  
is commercially available from common development tool vendors.  
The Embedded Trace Macrocell operates with third party debugger software tools.  
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Pinouts and pin description  
STM32WB55xx STM32WB35xx  
4
Pinouts and pin description  
(1)(2)  
Figure 10. STM32WB55Cx and STM32WB35Cx UFQFPN48 pinout  
VBAT  
1
36  
35  
34  
33  
32  
31  
30  
29  
28  
27  
26  
25  
PA10  
PC14-OSC32_IN  
2
VDD  
PC15-OSC32_OUT  
3
VDDSMPS  
VLXSMPS  
VSSSMPS  
VFBSMPS  
PE4  
PH3-BOOT0  
PB8  
4
5
PB9  
6
UFQFPN48  
NRST  
VDDA  
PA0  
7
8
PB1  
9
PB0  
PA1  
10  
11  
12  
AT1  
PA2  
AT0  
PA3  
OSC_IN  
MS42406V4  
1. The above figure shows the package top view.  
2. The exposed pad must be connected to ground plane.  
(1)(2)  
Figure 11. STM32WB55Rx VFQFPN68 pinout  
VBAT  
1
51  
50  
49  
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
PA10  
PC13  
2
PC6  
PC14-OSC32_IN  
3
PB15  
PC15-OSC32_OUT  
4
PB14  
PH3-BOOT0  
PB8  
PB13  
5
PB12  
6
PB9  
VDD  
7
NRST  
PC0  
VDDSMPS  
VLXSMPS  
VSSSMPS  
VFBSMPS  
PE4  
8
9
VFQFPN68  
PC1  
10  
11  
12  
13  
14  
15  
16  
17  
PC2  
PC3  
VREF+  
VDDA  
PA0  
PB1  
PB0  
AT1  
PA1  
AT0  
PA2  
OSC_IN  
MS45417V3  
1. The above figure shows the package top view.  
2. The exposed pad must be connected to ground plane.  
58/193  
DS11929 Rev 10  
 
 
 
 
 
 
 
STM32WB55xx STM32WB35xx  
Pinouts and pin description  
(1)  
Figure 12. STM32WB55Vx WLCSP100 ballout  
1
2
3
PA14  
VDDUSB  
PD1  
4
PA15  
PC9  
5
6
7
8
9
10  
VDD  
PE1  
PA11  
PA12  
PA13  
PA10  
PC12  
PD9  
PC10  
PC11  
PD6  
PB5  
PE2  
PD2  
PD5  
PB4  
PB7  
PD15  
PB8  
PA0  
PA6  
PA8  
PB2  
PD7  
PB3  
A
B
C
D
E
F
VDD  
VSS  
PD12  
PE0  
VSS  
PB13  
PD3  
PD0  
PD13  
VBAT  
PC14-  
PC15-  
VDDSMPS  
VLXSMPS  
VSSSMPS  
PE4  
PC6  
PD4  
PD8  
PD14  
PH3-BOOT0  
PC0  
OSC32_OUT OSC32_IN  
PB14  
PC7  
PD10  
PC8  
PD11  
PB6  
PH1  
NRST  
PC2  
PH0  
PB9  
VFBSMPS  
PE3  
PB15  
PB12  
AT0  
PA2  
PC4  
PC13  
PC5  
PA1  
PC1  
PC3  
G
H
J
PB1  
PB0  
AT1  
PA7  
VREF+  
PA3  
VDDA  
VSS  
VSSA  
VDD  
PA4  
OSC_IN  
VSSRF  
OSC_OUT  
VSSRF  
VDDRF  
VSSRF  
VSSRF  
RF1  
VSS  
VDD  
PB11  
PB10  
PA9  
PA5  
K
Radio  
USB  
SMPS  
VDD  
VSS  
MS42407V3  
1. The above figure shows the package top view.  
(1)  
Figure 13. STM32WB55Vx UFBGA129 ballout  
1
2
3
4
5
6
7
8
VDD  
_DCAP4  
9
10  
11  
12  
13  
PE1  
PB6  
PB5  
PD5  
PD10  
PA13  
VDDUSB  
PA12  
A
B
C
D
E
F
VSS  
PE2  
PE0  
PD15  
VBAT  
PB4  
PB7  
PD12  
PB3  
PD11  
PD7  
PD8  
PD4  
PD6  
PD2  
PD1  
PC10  
PA15  
PC12  
PA14  
PC6  
PD0  
VSS  
VSS  
PA11  
PC9  
_DCAP4  
PD13  
PC11  
PD3  
PA10  
PD14  
PD9  
PC8  
PC7  
PC15-  
OSC32_OUT  
PC14-  
OSC32_IN  
VSS  
VSS  
VSS  
VSS  
VDD  
VSS  
VSS  
VSS  
PB14  
PB13  
VDD  
_DCAP1  
VSS  
_DCAP1  
PH0  
PH3-BOOT0  
PC1  
PC13  
PB9  
VDD  
VDD  
VDD  
VDD  
PB15  
PB12  
VLXSMPS  
VLXSMPS  
VFBSMPS  
VSS_DCAP3  
AT0  
VDDSMPS  
VSSSMPS  
PE3  
VDDSMPS  
VSSSMPS  
PE4  
PH1  
NRST  
PC2  
PB8  
PC0  
PC3  
VDDA  
PA4  
G
H
J
VSS  
VDD_DCAP3  
AT1  
VSSA  
PA1  
VSS  
PA9  
PA8  
VSS  
PB10  
PB11  
PB2  
VSSRF  
VSSRF  
VSSRF  
VSSRF  
VSSRF  
VSSRF  
VSSRF  
K
L
VREF+  
PA0  
PC5  
PC4  
VSSRF  
VSSRF  
RF1  
VSSRF  
VSSRF  
VSSRF  
PB1  
PB0  
VSS  
_DCAP2  
PA3  
PA6  
VSSRF  
VDDRF  
OSC_IN  
OSC_OUT  
M
N
VDD  
_DCAP2  
PA2  
PA5  
PA7  
No pin  
Power supply  
SMPS  
USB  
Radio  
MS51777V4  
1. The above figure shows the package top view.  
DS11929 Rev 10  
59/193  
80  
 
 
 
Pinouts and pin description  
STM32WB55xx STM32WB35xx  
Definition  
Table 15. Legend/abbreviations used in the pinout table  
Name  
Abbreviation  
Unless otherwise specified in brackets below the pin name, the pin function during and after  
reset is the same as the actual pin name  
Pin name  
S
I
Supply pin  
Pin type  
Input only pin  
I/O  
FT  
TT  
RF  
RST  
Input / output pin  
5 V tolerant I/O  
3.6 V tolerant I/O  
RF I/O  
Bidirectional reset pin with weak pull-up resistor  
Option for TT or FT I/Os  
I/O, Fm+ capable  
I/O structure  
_f (1)  
_l (2)  
I/O, with LCD function supplied by VLCD  
I/O, with USB function supplied by VDDUSB  
I/O, with Analog switch function supplied by VDDA  
_u(3)  
_a(4) (5)  
Notes  
Alternate  
Unless otherwise specified by a note, all I/Os are set as analog inputs during and after reset.  
Functions selected through GPIOx_AFR registers  
functions  
Pin  
functions  
Additional  
functions  
Functions directly selected/enabled through peripheral registers  
1. The related I/O structures in Table 16 are: FT_f, FT_fa, FT_fl, FT_fla.  
2. The related I/O structures in Table 16 are: FT_l, FT_fl, FT_lu.  
3. The related I/O structures in Table 16 are: FT_u, FT_lu.  
4. The related I/O structures in Table 16 are: FT_a, FT_la, FT_fa, FT_fla, TT_a, TT_la.  
5. Analog switch for the TSC function is supplied by VDD  
.
60/193  
DS11929 Rev 10  
 
 
STM32WB55xx STM32WB35xx  
Pinouts and pin description  
Table 16. STM32WB55xx pin and ball definitions  
Pin number  
Pin name  
(function after  
reset)  
Alternate functions  
Additional functions  
TIM1_ETR, TSC_G7_IO3,  
LCD_SEG36, TIM16_CH1,  
CM4_EVENTOUT  
-
-
-
-
C8 B2  
PE0  
PE1  
I/O FT_l  
I/O FT_l  
-
-
-
TSC_G7_IO2, LCD_SEG37,  
TIM17_CH1,  
CM4_EVENTOUT  
B10 A1  
E6 B1  
-
-
TRACECK, SAI1_PDM_CK1,  
TSC_G7_IO1, LCD_SEG38,  
SAI1_MCLK_A,  
-
-
PE2  
I/O FT_l  
I/O FT_l  
-
CM4_EVENTOUT  
TSC_G6_IO4, LCD_SEG33,  
LPTIM2_OUT,  
CM4_EVENTOUT  
-
-
-
-
C9 C1  
D8 D3  
PD13  
PD14  
-
-
-
-
TIM1_CH1, LCD_SEG34,  
CM4_EVENTOUT  
I/O FT_l  
I/O FT_l  
TIM1_CH2, LCD_SEG35,  
CM4_EVENTOUT  
-
1
-
-
E7 C2  
C10 D2  
G5 F4  
PD15  
VBAT  
PC13  
-
-
-
-
1
2
S
-
-
(1)  
(2)  
RTC_TAMP1/RTC_TS/  
RTC_OUT/WKUP2  
I/O  
FT  
CM4_EVENTOUT  
(1)  
(2)  
PC14-  
OSC32_IN  
2
3
3
4
D10 E3  
D9 E2  
I/O  
I/O  
FT  
FT  
CM4_EVENTOUT  
CM4_EVENTOUT  
OSC32_IN  
(1)  
(2)  
PC15-  
OSC32_OUT  
OSC32_OUT  
-
-
-
-
-
-
E5  
F6  
VSS  
VDD  
S
-
-
-
-
-
-
-
-
-
-
-
-
-
S
-
-
-
E10 F1  
E9 G2  
E8 G1  
PH0  
I/O  
I/O  
I/O  
FT  
FT  
FT  
CM4_EVENTOUT  
CM4_EVENTOUT  
CM4_EVENTOUT, LSCO(3)  
-
-
PH1  
4
5
PH3-BOOT0  
TIM1_CH2N,  
SAI1_PDM_CK1, I2C1_SCL,  
QUADSPI_BK1_IO1,  
LCD_SEG16, SAI1_MCLK_A,  
TIM16_CH1,  
5
6
F7 G3  
PB8  
I/O FT_fl  
-
-
CM4_EVENTOUT  
DS11929 Rev 10  
61/193  
80  
 
 
Pinouts and pin description  
STM32WB55xx STM32WB35xx  
Table 16. STM32WB55xx pin and ball definitions (continued)  
Pin number  
Pin name  
(function after  
reset)  
Alternate functions  
Additional functions  
TIM1_CH3N, SAI1_PDM_DI2,  
I2C1_SDA, SPI2_NSS,  
IR_OUT, TSC_G7_IO4,  
QUADSPI_BK1_IO0,  
LCD_COM3, SAI1_FS_A,  
TIM17_CH1,  
6
7
F10 H4  
PB9  
I/O FT_fla  
-
-
-
CM4_EVENTOUT  
7
-
8
9
F9 H2  
F8 H3  
NRST  
PC0  
I/O RST  
I/O FT_fla  
-
-
-
LPTIM1_IN1, I2C3_SCL,  
LPUART1_RX, LCD_SEG18,  
LPTIM2_IN1,  
ADC1_IN1  
CM4_EVENTOUT  
LPTIM1_OUT, SPI2_MOSI,  
I2C3_SDA, LPUART1_TX,  
LCD_SEG19,  
-
-
10 G8 H1  
11 G9 J2  
PC1  
PC2  
I/O FT_fla  
I/O FT_la  
-
-
ADC1_IN2  
ADC1_IN3  
CM4_EVENTOUT  
LPTIM1_IN2, SPI2_MISO,  
LCD_SEG20,  
CM4_EVENTOUT  
-
-
-
-
-
-
E7  
H6  
VSS  
VDD  
S
S
-
-
-
-
-
-
-
-
LPTIM1_ETR,  
SAI1_PDM_DI1, SPI2_MOSI,  
LCD_VLCD, SAI1_SD_A,  
LPTIM2_ETR,  
-
12 G10 J3  
PC3  
I/O FT_a  
-
-
ADC1_IN4  
CM4_EVENTOUT  
-
-
-
H10 K2  
VSSA  
VREF+  
VDDA  
VSS  
S
S
S
S
S
-
-
-
-
-
-
-
-
-
-
-
13 H8 L1  
14 H9 K3  
-
VREFBUF_OUT  
(4)  
8
-
-
-
-
-
-
J9 E9  
J10 F8  
-
-
-
VDD  
TIM2_CH1, COMP1_OUT,  
SAI1_EXTCLK, TIM2_ETR,  
CM4_EVENTOUT  
COMP1_INM, ADC1_IN5,  
RTC_TAMP2/WKUP1  
9
15 G7 M1  
PA0  
PA1  
I/O FT_a  
I/O FT_la  
-
-
TIM2_CH2, I2C1_SMBA,  
SPI1_SCK, LCD_SEG0,  
CM4_EVENTOUT  
10 16 G6 L2  
COMP1_INP, ADC1_IN6  
62/193  
DS11929 Rev 10  
STM32WB55xx STM32WB35xx  
Pinouts and pin description  
Table 16. STM32WB55xx pin and ball definitions (continued)  
Pin number  
Pin name  
(function after  
reset)  
Alternate functions  
Additional functions  
LSCO(3), TIM2_CH3,  
LPUART1_TX,  
QUADSPI_BK1_NCS,  
LCD_SEG1, COMP2_OUT,  
CM4_EVENTOUT  
COMP2_INM, ADC1_IN7,  
WKUP4  
11 17 F6 N1  
PA2  
PA3  
I/O FT_la  
I/O FT_la  
-
-
TIM2_CH4, SAI1_PDM_CK1,  
LPUART1_RX,  
QUADSPI_CLK, LCD_SEG2, COMP2_INP, ADC1_IN8  
SAI1_MCLK_A,  
12 18 J8 M2  
CM4_EVENTOUT  
SPI1_NSS, SAI1_FS_B,  
COMP1_INM,  
13 19 K10 L3  
14 20 K9 N2  
PA4  
PA5  
I/O FT_a  
I/O FT_a  
-
-
LPTIM2_OUT, LCD_SEG5,  
COMP2_INM, ADC1_IN9  
CM4_EVENTOUT  
TIM2_CH1, TIM2_ETR,  
SPI1_SCK, LPTIM2_ETR,  
SAI1_SD_B,  
COMP1_INM,  
COMP2_INM, ADC1_IN10  
CM4_EVENTOUT  
TIM1_BKIN, SPI1_MISO,  
LPUART1_CTS,  
15 21 H7 M3  
PA6  
PA7  
PA8  
I/O FT_la  
I/O FT_fla  
I/O FT_la  
-
-
-
QUADSPI_BK1_IO3,