STM32WLE4JCI7XXX [STMICROELECTRONICS]
Multiprotocol LPWAN 32-bit Arm® Cortex®-M4 MCUs, LoRa®, (G)FSK, (G)MSK, BPSK, up to 256KB Flash, 64KB SRAM;
| 型号： | STM32WLE4JCI7XXX |
| 厂家： | 
ST |
| 描述： | Multiprotocol LPWAN 32-bit Arm® Cortex®-M4 MCUs, LoRa®, (G)FSK, (G)MSK, BPSK, up to 256KB Flash, 64KB SRAM LPWA 静态存储器 |
| 文件： | 总145页 (文件大小：2974K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
STM32WLE5xx STM32WLE4xx
Multiprotocol LPWAN 32-bit Arm® Cortex®-M4 MCUs, LoRa®,
(G)FSK, (G)MSK, BPSK, up to 256KB Flash, 64KB SRAM
Datasheet - production data
Features
Radio
• Frequency range: 150 MHz to 960 MHz
UFBGA73
(5 x 5 mm)
WLCSP59
®
UFQFPN48
(7 x 7 mm)
• Modulation: LoRa , (G)FSK, (G)MSK and
BPSK
– Adaptive real-time accelerator (ART
Accelerator) allowing 0-wait-state
• RX sensitivity: –123 dBm for 2-FSK
®
(at 1.2 Kbit/s), –148 dBm for LoRa
execution from Flash memory, frequency
up to 48 MHz, MPU and DSP instructions
(at 10.4 kHz, spreading factor 12)
• Transmitter high output power, programmable
– 1.25 DMIPS/MHz (Dhrystone 2.1)
up to +22 dBm
• Transmitter low output power, programmable
Security and identification
up to +15 dBm
• Hardware encryption AES 256-bit
• True random number generator (RNG)
• Compliant with the following radio frequency
regulations such as ETSI EN 300 220,
EN 300 113, EN 301 166, FCC CFR 47
Part 15, 24, 90, 101 and the Japanese ARIB
STD-T30, T-67, T-108
• Sector protection against read/write operations
(PCROP, RDP, WRP)
• CRC calculation unit
• Compatible with standardized or proprietary
• Unique device identifier (64-bit UID compliant
®
protocols such as LoRaWAN , Sigfox™,
with IEEE 802-2001 standard)
W-MBus and more (fully open wireless
system-on-chip)
• 96-bit unique die identifier
• Hardware public key accelerator (PKA)
Ultra-low-power platform
Supply and reset management
• 1.8 V to 3.6 V power supply
• High-efficiency embedded SMPS step-down
•
–40 °C to +105 °C temperature range
converter
• Shutdown mode: 31 nA (V = 3 V)
DD
• SMPS to LDO smart switch
• Standby (+ RTC) mode:
• Ultra-safe, low-power BOR (brownout reset)
360 nA (V = 3 V)
DD
with 5 selectable thresholds
• Stop2 (+ RTC) mode: 1.07 µA (V = 3 V)
DD
• Ultra-low-power POR/PDR
®
• Active-mode MCU: < 72 µA/MHz (CoreMark )
• Active-mode RX: 4.82 mA
• Programmable voltage detector (PVD)
• V
mode with RTC and 20x32-byte backup
registers
BAT
• Active-mode TX: 15 mA at 10 dBm and 87 mA
®
at 20 dBm (LoRa 125 kHz)
Clock sources
Core
• 32 MHz crystal oscillator
®
®
• 32-bit Arm Cortex -M4 CPU
• TCXO support: programmable supply voltage
November 2020
DS13105 Rev 8
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This is information on a product in full production.
www.st.com
STM32WLE5/E4xx
• 32 kHz oscillator for RTC with calibration
Controllers
• High-speed internal 16 MHz factory trimmed
• 2x DMA controller (7 channels each)
supporting ADC, DAC, SPI, I2C, LPUART,
USART, AES and timers
RC (± 1 %)
• Internal low-power 32 kHz RC
• 2x USART (ISO 7816, IrDA, SPI)
• 1x LPUART (low-power)
• Internal multi-speed low-power 100 kHz to
48 MHz RC
• PLL for CPU, ADC and audio clocks
• 2x SPI 16 Mbit/s (1 over 2 supporting I2S)
• 3x I2C (SMBus/PMBus™)
Memories
• 2x 16-bit 1-channel timer
• Up to 256-Kbyte Flash memory
• Up to 64-Kbyte RAM
• 20x32-bit backup register
• 1x 16-bit 4-channel timer (supporting
motor control)
• 1x 32-bit 4-channel timer
• Bootloader supporting USART and SPI
• 3x 16-bit ultra-low-power timer
interfaces
• 1x RTC with 32-bit sub-second wakeup
• OTA (over-the-air) firmware update capable
• Sector protection against read/write operations
counter
• 1x independent SysTick
• 1x independent watchdog
• 1x window watchdog
Rich analog peripherals (down to 1.62 V)
• 12-bit ADC 2.5 Msps, up to 16 bits with
hardware oversampling, conversion range up
to 3.6 V
Up to 43 I/Os, most 5 V-tolerant
• 12-bit DAC, low-power sample-and-hold
• 2x ultra-low-power comparators
Development support
• Serial-wire debug (SWD), JTAG
System peripherals
All packages ECOPACK2 compliant
• Semaphores for processor firmware process
synchronization
Table 1. Device summary
Reference
Part number
STM32WLE5C8, STM32WLE5CB, STM32WLE5CC
STM32WLE5xx microcontrollers STM32WLE5J8, STM32WLE5JB, STM32WLE5JC
STM32WLE5U8, STM32WLE5UB, STM32WLE5UC
STM32WLE4C8, STM32WLE4CB, STM32WLE4CC
STM32WLE4xx microcontrollers STM32WLE4J8, STM32WLE4JB, STM32WLE4JC
STM32WLE4U8, STM32WLE4UB, STM32WLE4UC
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Contents
Contents
1
2
3
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.1
3.2
3.3
3.4
3.5
Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Arm Cortex-M core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Adaptive real-time memory accelerator (ART Accelerator) . . . . . . . . . . . 15
Memory protection unit (MPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.5.1
3.5.2
Embedded Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Embedded SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.6
3.7
3.8
Security management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Sub-GHz radio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.8.1
3.8.2
3.8.3
3.8.4
3.8.5
3.8.6
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
RF-PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Intermediate frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.9
Power supply management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.9.1
3.9.2
3.9.3
3.9.4
Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Linear voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
VBAT operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.10 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.10.1 Reset mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
3.11 Peripheral interconnect matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
3.12 Reset and clock controller (RCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
3.13 Hardware semaphore (HSEM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
3.14 General-purpose inputs/outputs (GPIOs) . . . . . . . . . . . . . . . . . . . . . . . . . 38
3.15 Direct memory access controller (DMA) . . . . . . . . . . . . . . . . . . . . . . . . . . 38
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3.16 Interrupts and events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
3.16.1 Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . 39
3.16.2 Extended interrupt/event controller (EXTI) . . . . . . . . . . . . . . . . . . . . . . 39
3.17 Cyclic redundancy check (CRC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
3.18 Analog-to-digital converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
3.18.1 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
3.18.2 Internal voltage reference (V
) . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
REFINT
3.18.3
V
battery voltage monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
BAT
3.19 Digital-to-analog converter (DAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
3.20 Voltage reference buffer (VREFBUF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
3.21 Comparator (COMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
3.22 True random number generator (RNG) . . . . . . . . . . . . . . . . . . . . . . . . . . 42
3.23 Advanced encryption standard hardware accelerator (AES) . . . . . . . . . . 42
3.24 Public key accelerator (PKA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
3.25 Timer and watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
3.25.1 Advanced-control timer (TIM1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
3.25.2 General-purpose timers (TIM2, TIM16, TIM17) . . . . . . . . . . . . . . . . . . . 43
3.25.3 Low-power timers (LPTIM1, LPTIM2 and LPTIM3) . . . . . . . . . . . . . . . . 44
3.25.4 Independent watchdog (IWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
3.25.5 System window watchdog (WWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
3.25.6 SysTick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
3.26 Real-time clock (RTC), tamper and backup registers . . . . . . . . . . . . . . . 45
3.27 Inter-integrated circuit interface (I2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
3.28 Universal synchronous/asynchronous receiver transmitter
(USART/UART) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
3.29 Low-power universal asynchronous receiver transmitter (LPUART) . . . . 47
3.30 Serial peripheral interface (SPI)/integrated-interchip sound
interface (I2S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
3.31 Development support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Pinouts, pin description and alternate functions . . . . . . . . . . . . . . . . . 49
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
4
5
5.1
Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
5.1.1
5.1.2
Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
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5.1.3
5.1.4
5.1.5
5.1.6
5.1.7
Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
5.2
5.3
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
5.3.1
5.3.2
5.3.3
5.3.4
5.3.5
5.3.6
5.3.7
5.3.8
Main performances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Sub-GHz radio characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Operating conditions at power-up/power-down . . . . . . . . . . . . . . . . . . . 74
Embedded reset and power-control block characteristics . . . . . . . . . . . 75
Embedded voltage reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Wakeup time from low-power modes and voltage scaling
transition times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
5.3.9
External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
5.3.10 Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
5.3.11 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
5.3.12 Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
5.3.13 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
5.3.14 Electrical sensitivity characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
5.3.15 I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
5.3.16 I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
5.3.17 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
5.3.18 Analog switches booster . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
5.3.19 Analog-to-digital converter characteristics . . . . . . . . . . . . . . . . . . . . . . 114
5.3.20 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
5.3.21
V
monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
BAT
5.3.22 Voltage reference buffer characteristics . . . . . . . . . . . . . . . . . . . . . . . 120
5.3.23 Digital-to-analog converter characteristics . . . . . . . . . . . . . . . . . . . . . . 122
5.3.24 Comparator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
5.3.25 Timers characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
5.3.26 Communication interfaces characteristics . . . . . . . . . . . . . . . . . . . . . . 128
6
Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
6.1
UFQFPN48 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
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6.2
6.3
6.4
WLCSP59 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
UFBGA73 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
Package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
7
8
Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
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List of tables
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Device summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Main features and peripheral counts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Access status versus RDP level and execution mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Sub-GHz radio transmit high output power. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
FSK mode intermediate frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
LoRa mode intermediate frequencies. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Functionalities depending on system operating mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Low-power mode summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
MCU and sub-GHz radio operating modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Peripherals interconnect matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
DMA1 and DMA2 implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Temperature sensor calibration values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Internal voltage reference calibration values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Timer features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
I2C implementation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
USART/LPUART features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
SPI and SPI/I2S implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Legend/abbreviations used in the pinout table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
STM32WLE5/E4xx pin definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Main performances at VDD = 3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Operating range of RF pads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Sub-GHz radio power consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Sub-GHz radio power consumption in transmit mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Sub-GHz radio general specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Sub-GHz radio receive mode specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Sub-GHz radio transmit mode specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Sub-GHz radio power management specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Operating conditions at power-up/power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Embedded reset and power-control block characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 75
Embedded internal voltage reference. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Current consumption in Run and LPRun modes, CoreMark code with data
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
Table 26.
Table 27.
Table 28.
Table 29.
Table 30.
Table 31.
Table 32.
Table 33.
Table 34.
Table 35.
Table 36.
running from Flash memory, ART enable (cache ON, prefetch OFF) . . . . . . . . . . . . . . . . 78
Current consumption in Run and LPRun modes, CoreMark code
with data running from SRAM1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Typical current consumption in Run and LPRun modes, with different codes
running from Flash memory, ART enable (cache ON, prefetch OFF) . . . . . . . . . . . . . . . . 80
Typical current consumption in Run and LPRun modes,
Table 37.
Table 38.
Table 39.
with different codes running from SRAM1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Current consumption in Sleep and LPSleep modes, Flash memory ON . . . . . . . . . . . . . . 84
Current consumption in LPSleep mode, Flash memory in power-down. . . . . . . . . . . . . . . 84
Current consumption in Stop 2 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Current consumption during wakeup from Stop 2 mode . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Current consumption in Stop 1 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Table 40.
Table 41.
Table 42.
Table 43.
Table 44.
DS13105 Rev 8
7/145
9
List of tables
STM32WLE5/E4xx
Table 45.
Table 46.
Table 47.
Table 48.
Table 49.
Table 50.
Table 51.
Table 52.
Table 53.
Table 54.
Table 55.
Table 56.
Table 57.
Table 58.
Table 59.
Table 60.
Table 61.
Table 62.
Table 63.
Table 64.
Table 65.
Table 66.
Table 67.
Table 68.
Table 69.
Table 70.
Table 71.
Table 72.
Table 73.
Table 74.
Table 75.
Table 76.
Table 77.
Table 78.
Table 79.
Table 80.
Table 81.
Table 82.
Table 83.
Table 84.
Table 85.
Table 86.
Table 87.
Table 88.
Table 89.
Table 90.
Table 91.
Table 92.
Table 93.
Table 94.
Table 95.
Table 96.
Current consumption during wakeup from Stop 1 mode . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Current consumption in Stop 0 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Current consumption during wakeup from Stop 0 mode . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Current consumption in Standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Current consumption during wakeup from Standby mode . . . . . . . . . . . . . . . . . . . . . . . . . 88
Current consumption in Shutdown mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Current consumption in VBAT mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Current under Reset condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Regulator modes transition times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
HSE32 crystal requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
HSE32 oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
HSE32 TCXO regulator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Low-speed external user clock characteristics – Bypass mode . . . . . . . . . . . . . . . . . . . . . 98
HSI16 oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
MSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100
LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Flash memory endurance and data retention. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
I/O AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Analog switches booster characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Maximum ADC R
values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
AIN
ADC accuracy. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
TS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
V
V
monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
charging characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
BAT
BAT
VREFBUF characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
DAC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
DAC accuracy. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
COMP characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
IWDG min/max timeout period at 32 kHz (LSI). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
Minimum I2CCLK frequency in all I2C modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
I2C analog filter characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
USART characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
Dynamic JTAG characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
Dynamic SWD characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
UFQFPN48 - Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
UFBGA73 - Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
8/145
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List of tables
Table 97.
Table 98.
Table 99.
UFBGA recommended PCB design rules (0.5 mm pitch BGA) . . . . . . . . . . . . . . . . . . . . 139
Package thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
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9
List of figures
STM32WLE5/E4xx
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
STM32WLE5/E4xx block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
sub-GHz radio system block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
High output power PA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Low output power PA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Power-up/power-down sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Power supply overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Supply configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Clock tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
UFQFPN48 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Figure 10. UFBGA73 pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Figure 11. Pin loading conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Figure 12. Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Figure 13. Power supply scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Figure 14. Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Figure 15. VREFINT versus temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Figure 16. Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Figure 17. Low-speed external clock source AC timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Figure 18. HSI16 frequency versus temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Figure 19. Typical current consumption vs. MSI frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Figure 20. I/O input characteristics - V and V on all I/Os . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
IL
IH
Figure 21. Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Figure 22. ADC accuracy characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
Figure 23. Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Figure 24. VREFOUT_TEMP when VRS = 0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
Figure 25. VREFOUT_TEMP when VRS = 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
Figure 26. 12-bit buffered/non-buffered DAC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
Figure 27. SPI timing diagram - Slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
Figure 28. SPI timing diagram - Slave mode and CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
Figure 29. SPI timing diagram - Master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
Figure 30. UFQFPN48 - Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
Figure 31. UFQFPN48 - Recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
Figure 32. UFQFPN48 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
Figure 33. UFBGA73 - Outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
Figure 34. UFBGA73 - Recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
Figure 35. UFBGA73 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
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STM32WLE5/E4xx
Introduction
1
Introduction
This document provides information on the STM32WLE5/E4xx microcontrollers.
®(a)
®
®
For information on the Arm
Cortex -M4 core, refer to the Cortex -M4 Technical
Reference Manual available from the www.arm.com website.
®
For information on LoRa modulation, refer to the Semtech website
(https://www.semtech.com/technology/lora).
2
Description
The STM32WLE5/E4xx long-range wireless and ultra-low-power devices embed a powerful
and ultra-low-power LPWAN-compliant radio solution, enabling the following modulations:
®
LoRa , (G)FSK, (G)MSK, and BPSK.
®
The LoRa modulation is available in STM32WLx5xx only.
These devices are designed to be extremely low-power and are based on the
®
®
high-performance Arm Cortex -M4 32-bit RISC core operating at a frequency of up to
48 MHz. This core implements a full set of DSP instructions and an independent memory
protection unit (MPU) that enhances the application security.
The devices embed high-speed memories (Flash memory up to 256 Kbytes, SRAM up to
64 Kbytes), and an extensive range of enhanced I/Os and peripherals.
The devices also embed several protection mechanisms for embedded Flash memory and
SRAM: readout protection, write protection and proprietary code readout protection.
These devices offer a 12-bit ADC, a 12-bit DAC low-power sample-and-hold, two
ultra-low-power comparators associated with a high-accuracy reference voltage generator.
The devices embed a low-power RTC with a 32-bit sub-second wakeup counter, one 16-bit
single-channel timer, two 16-bit four-channel timers (supporting motor control), one 32-bit
four-channel timer and three 16-bit ultra-low-power timers.
These devices also embed two DMA controllers (7 channels each) allowing any transfer
combination between memory (Flash memory, SRAM1 and SRAM2) and peripheral, using
the DMAMUX1 for flexible DMA channel mapping.
a. Arm is a registered trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere.
DS13105 Rev 8
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14
Description
STM32WLE5/E4xx
The devices also feature the standard and advanced communication interfaces listed below:
•
•
•
•
•
two USART (supporting LIN, smartcard, IrDA, modem control and ISO7816)
one low-power UART (LPUART)
three I2C (SMBus/PMBus)
2
two SPIs (up to 16 MHz, one supporting I S)
semaphores for processor firmware process synchronization
(a)
The operating temperature/voltage ranges are –40 °C to +105 °C (+85 °C with radio) from
a 1.8 V to 3.6 V power supply. A comprehensive set of power-saving modes allows the
design of low-power applications.
The devices integrate a high-efficiency SMPS step-down converter and independent power
supplies for ADC, DAC and comparator analog inputs.
A V
dedicated supply allows the LSE 32.768 kHz oscillator, the RTC and the backup
BAT
registers to be backed up. The devices can maintain these functions even if the main V is
DD
not present, through a CR2032-like battery, a supercap or a small rechargeable battery.
Table 2. Main features and peripheral counts
STM32WLE5Cx
STM32WLE4Cx
STM32WLE5Jx
STM32WLE4Jx
STM32WLE5Ux
STM32WLE4Ux
Feature
CPU
Arm Cortex-M4
48
Maximum CPU frequency (MHz)
Flash memory density (Kbytes)
256/128/64
32/16/0
SRAM1
SRAM density (Kbytes)
SRAM2
32/32/20
Available on STM32WLE5xx devices.
Not available on STM32WLE4xx devices
LoRa
(G)FSK
Radio
(G)MSK
BPSK
Yes
Yes
Low output power (up to
15 dBm)
Radio power amplifier
High output power (up to
22 dBm)
General purpose
Low-power
SysTick
4
3
1
Timer
a. Devices with suffix 6 operate up to 85 °C. Devices with suffix 7 can operate up to 105 °C except radio.
12/145
DS13105 Rev 8
STM32WLE5/E4xx
Description
Table 2. Main features and peripheral counts (continued)
STM32WLE5Cx
STM32WLE4Cx
STM32WLE5Jx
STM32WLE4Jx
STM32WLE5Ux
STM32WLE4Ux
Feature
SPI/I2S
2 (1 supporting I2S)
I2C
3
2
1
1
1
1
2
1
1
1
1
1
1
Communication
interface
USART
LPUART
Independent
Window
Watchdog
RTC (with wakeup counter)
DMA (7 channels)
Semaphores
AES 256 bits
RNG
PKA
PCROP, RDP, WRP
CRC
Security
64-bit UID compliant with
IEEE 802-2001 standard
1
96-bit die ID
1
Tamper pins
Wakeup pins
GPIOs
3
3
3
2
2
3
43
29
22
ADC (number of channels, ext + int)
DAC (number of channels)
Internal VREFBUF
1 (9 + 4)
1 (12 + 4)
1 (1)
1 (8 + 4)
No
Yes
No
Analog comparator
2
Operating voltage
1.8 to 3.6 V
Ambient operating temperature
Junction temperature
–40 °C to +105 °C / –40 °C to +85 °C (with radio)
–40 °C to +125 °C / –40 °C to +105 °C
UFQFPN48
(7 x 7 mm)
UFBGA73
(5 x 5 mm)
Package
WLCSP59
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14
Description
STM32WLE5/E4xx
Figure 1. STM32WLE5/E4xx block diagram
LDO/SMPS
Sub-GHz
radio
HSE32
32 MHz
SRAM2
LSE
32 kHz
RTC
TAMP
backup memory
LSI
32 kHz
Backup
domain
IWDG
HSI 1 %
16 MHz
PLL
MSI 5 %
0.1-48MHz
NVIC
SRAM1
RCC
Cortex-M4
(DSP)
Power supply
POR/PDR/BOR/PVD/PVM
≤ 48 MHz
SYSCFG/
COMP/VREF
MPU
DMA1 (7 channels)
DMA2 (7 channels)
DMAMUX
PWR
EXTI
HSEM
RNG
AES
WWDG
SPI1
SPI2S2
I2C1
GPIO ports A,B,C,H
CRC
I2C2
PKA
DAC (12 bits)
LPUART1
I2C3
Temperature sensor
TIM1
ADC (12 bits ULP,
2 Msps, 12 channels)
APB1 and APB 2
USART1
LPTIM1
TIM2
LPTIM2
TIM16
TIM17
LPTIM3
USART2
MSv64324V1
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Functional overview
3
Functional overview
3.1
Architecture
The devices embed a sub-GHz RF subsystem that interfaces with a generic microcontroller
subsystem using an Arm Cortex-M4 (called CPU).
An RF low-layer stack is needed and is to be run on CPU with the host application code.
The RF subsystem communication is done through an internal SPI interface.
3.2
Arm Cortex-M core
With its embedded Arm core, the STM32WLE5/E4xx devices are compatible with all
Arm tools and software.
Figure 1 shows the general block diagram of the STM32WLE5/E4xx devices.
Arm Cortex-M4
The Arm Cortex-M4 is a processor for embedded systems. It has been developed to provide
a low-cost platform that meets the needs of MCU implementation, with a reduced pin count
and low-power consumption, while delivering outstanding computational performance and
an advanced response to interrupts.
The Arm Cortex-M4 32-bit RISC processor features exceptional code-efficiency, delivering
the high-performance expected from an Arm core in the memory size usually associated
with 8- and 16-bit devices.
This processor supports a set of DSP instructions that allow efficient signal processing and
complex algorithm execution.
3.3
Adaptive real-time memory accelerator (ART Accelerator)
The ART Accelerator is a memory accelerator that is optimized for STM32 industry-standard
Arm Cortex-M4 processor. The ART Accelerator balances the inherent performance
advantage of the Arm Cortex-M4 over Flash memory technologies, that normally require the
processor to wait for the Flash memory at higher frequencies.
To release the processor near 60 DMIPS performance at 48 MHz, the ART Accelerator
implements an instruction prefetch queue and branch cache, that increases the program
execution speed from the 64-bit Flash memory. Based on CoreMark benchmark, the
performance achieved thanks to the ART Accelerator is equivalent to 0 wait state program
execution from Flash memory at a CPU frequency up to 48 MHz.
3.4
Memory protection unit (MPU)
The memory protection unit (MPU) is used to manage the CPU accesses to memory, to
prevent one task to accidentally corrupt the memory or resources used by any other active
task. This memory area is organized into up to eight protected areas that can in turn be
divided up into eight subareas. The protection area sizes are between 32 bytes and the
whole 4 Gbytes of addressable memory.
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The MPU is especially helpful for applications where some critical or certified code must be
protected against the misbehavior of other tasks. It is usually managed by an RTOS (real-
time operating system). If a program accesses a memory location that is prohibited by the
MPU, the RTOS can detect it and take action. In an RTOS environment, the kernel can
dynamically update the MPU area setting, based on the process to be executed.
The MPU is optional and can be bypassed for applications that do not need it.
3.5
Memories
3.5.1
Embedded Flash memory
The Flash memory interface manages the accesses from CPU AHB ICode/DCode to the
Flash memory. It implements the access, the erase and program Flash memory operations,
and the read and write protection.
The main features of the Flash memory are listed below:
•
Memory organization: 1 bank
–
–
main memory: up to 256 Kbytes
page size: 2 Kbytes
•
•
•
72-bit wide data read (64 bits plus 8 ECC bits)
72-bit wide data write (64 bits plus 8 ECC bits)
Page erase and mass erase
Flexible protections can be configured thanks to option bytes:
Readout protection (RDP) to protect the whole memory. Three levels are available:
•
–
–
Level 0: no readout protection
Level 1: memory readout protection. The Flash memory cannot be read from or
written to if either debug features are connected, boot in SRAM or bootloader is
selected.
–
Level 2: chip readout protection. Debug features (JTAG and serial wire), boot in
SRAM and bootloader selection are disabled (JTAG fuse). This selection is
irreversible.
Table 3. Access status versus RDP level and execution mode
Debug, boot from SRAM or boot from
User execution
RDP
level
system memory (loader)
Area
Read
Write
Erase
Read
Write
Erase
1
2
1
2
1
2
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
Yes
Yes
No
No
NA
Yes
NA
Yes
NA
No
NA
No
No
NA
No
Main memory
System memory
Option bytes
No
No
NA
Yes
NA
NA
Yes
NA
Yes
No(1)
Yes
No(1)
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Functional overview
Table 3. Access status versus RDP level and execution mode (continued)
Debug, boot from SRAM or boot from
system memory (loader)
User execution
Write
RDP
level
Area
Read
Erase
Read
Write
Erase
1
2
1
2
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
NA(2)
No
NA
No
NA
No
NA
No
NA
NA(2)
Backup registers
SRAM2
NA
NA
Yes(2)
Yes
No(2)
NA
1. The option byte can be modified by the sub-GHz radio.
2. Erased when RDP changes from Level 1 to Level 0.
•
•
Write protection (WRP): the protected area is protected against erasing and
programming. Two areas can be selected, with 4-Kbyte granularity.
Proprietary code readout protection (PCROP): two parts of the Flash memory can be
protected against read and write from third parties. The protected area is execute-only:
it can only be reached by the STM32 CPU, as an instruction code, while all other
accesses (DMA, debug and CPU data read, write and erase) are strictly prohibited.
Two areas can be selected, with 2-Kbyte granularity. An additional option bit
(PCROP_RDP) is used to select if the PCROP area is erased or not when the RDP
protection is changed from Level 1 to Level 0.
The whole non-volatile memory embeds the error correction code (ECC) feature supporting:
•
•
•
single error detection and correction
double error detection
address of the ECC fail can be read in the FLASH_ECCR register
3.5.2
Embedded SRAM
The devices feature up to 64 Kbytes of embedded SRAM, split in two blocks:
•
•
SRAM1: up to 32 Kbytes mapped at address 0x2000 0000
SRAM2: up to 32 Kbytes located at address 0x2000 8000 (contiguous to SRAM1), also
mirrored at 0x1000 0000, with hardware parity check (this SRAM can be retained in
Standby mode)
The SRAMs can be accessed in read/write with 0 wait states for all CPU clock speeds.
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STM32WLE5/E4xx
3.6
Security management
The devices contain many security blocks, such as:
•
•
RNG
AES: 128-and 256-bit AES, supporting ECB, CBC, CTR, GCM, GMAC and CCM
chaining modes
•
•
PKA:
–
modular arithmetic including exponentiation with maximum modulo size of
3136 bits
–
elliptic curves over prime field scalar multiplication, ECDSA signature, ECDSA
verification with maximum modulo size of 521 bits
cyclic redundancy check calculation unit (CRC)
3.7
Boot modes
At startup, BOOT0 pin and BOOT1 option bit are used to select one of the following boot
options:
•
•
•
Boot from user Flash memory
Boot from boot system memory (where embedded bootloader is located)
Boot from embedded SRAM
The bootloader makes possible to download code from USART or SPI.
3.8
Sub-GHz radio
3.8.1
Introduction
The sub-GHz radio is an ultra-low-power sub-GHz radio operating in the 150 - 960 MHz ISM
band. LoRa, (G)FSK/(G)MSK modulation in transmit and receive, and (D)BPSK in transmit
only, allow an optimal trade-off between range, data rate and power consumption. This sub-
®
GHz radio is compliant with the LoRaWAN specification v1.0 and radio regulations such as
ETSI EN 300 220, EN 300 113, EN 301 166, FCC CFR 47 part 15, 24, 90, 101 and the ARIB
STD-T30, T-67, T-108.
The sub-GHz radio consists of:
•
an analog front-end transceiver, capable of outputting up to + 15 dBm maximum power
on its RFO_LP pin and up to + 22 dBm maximum power on RFO_HP pin
•
a digital modem bank providing the following modulation schemes:
–
LoRa Rx/Tx with bandwidth (BW) from 7.8 - 500 kHz, spreading factor (SF)
5 - 12, bit rate (BR) from 0.013 to 17.4 Kbit/s (real bitrate)
–
–
–
FSK and GFSK Rx/Tx with BR from 0.6 to 300 Kbit/s
(G)MSK Tx with BR from 0 to 10 Kbit/s
BPSK and DBPSK TX only with bitrate for 100 and 600 bit/s
•
•
a digital control including all data processing and sub-GHz radio configuration control
a high-speed clock generation
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Functional overview
3.8.2
General description
The sub-GHz radio provides an internal processing unit to handle communication with the
system CPU. Communication is handled by commands sent over the SPI interface, and a
set of interrupts is used to signal events. BUSY information signals operation activity and is
used to indicate when the sub-GHz radio commands cannot be received.
The block diagram of the sub-GHz radio system is shown in the figure below.
Figure 2. sub-GHz radio system block diagram
VDDPA
VR_PA
Sub-GHz radio
SUBGHZSPI
BUSY
FSK
RFO_HP
RFO_LP
RFI_P
modem
Interrups
Radio
control
Data
and
control
Sub-GHz
HSEON
RF frontend
RFI_N
LoRa
HSEBYPPWR
modem
PB0_VDDTCXO
OSC_IN
(note)
HSERDY
hse32
HSE32
OSC_OUT
MSv62615V1
Note: LoRa modem is only available on STM32WLE5xx devices.
3.8.3
Transmitter
The transmit chain comprises the modulated output from the modem, that directly
modulates the RF-PLL. An optional pre-filtering of the bit stream can be enabled to reduce
the power in the adjacent channel also dependent on the selected modulation scheme. The
modulated signal from the RF-PLL directly drives the high output power PA (HP PA) or low
output power PA (LP PA).
Transmitter high output power
Transmit high output power up to + 22 dBm, is supported through the RFO_HP RF pin.
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For this, the REG PA must be supplied directly from V on VDDSMPS pin, as shown in the
DD
figure below.
The output power range is programmable in 32 steps of ~ 1 dB. The power amplifier
ramping timing is also programmable.This allows adaptation to meet radio regulation
requirements.
Figure 3. High output power PA
SMPS mode
LDO mode
VDD
VDD
VDDSMPS (1.8 to 3.6V)
VDDSMPS (1.8 to 3.6V)
VLXSMPS
VLXSMPS
LDO/SMPS
LDO/SMPS
VFBSMPS (1.55V)
VFBSMPS (1.55V)
VDDPA
VDD
VDD
VDDPA
VR_PA (up to 3.1V)
RFO_HP
VR_PA (up to 3.1V)
RFO_HP
REG
PA
REG
PA
HP PA
HP PA
Note: Use of the SMPS is optional. When SMPS is not used, the BOM can be reduced by removing the coil
between VLXSMPS and VFBSMPS pins.
MSv62616V2
The table below gives the maximum transmit output power versus the V
supply level.
DDPA
Table 4. Sub-GHz radio transmit high output power
VDDPA supply (V)
Transmit output power (dBm)
3.3
2.7
2.4
1.8
+ 22
+ 20
+ 19
+ 16
Transmitter low output power
The transmit low output power up to + 15 dBm on full V range (1.8 to 3.6 V), is supported
DD
through the RFO_LP RF pin. For this, the REG PA must be supplied from the regulated
V
supply at 1.55 V, as shown in the figure below.
FBSMPS
The output power range is programmable in 32 steps of ~1 dB. The power amplifier ramping
timing is also programmable.This allows adaptation to meet radio regulation requirements.
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Functional overview
Figure 4. Low output power PA
LDO mode
SMPS mode
VDD
VDD
VDDSMPS (1.8 to 3.6V)
VDDSMPS (1.8 to 3.6V)
VLXSMPS
VLXSMPS
LDO/SMPS
LDO/SMPS
VFBSMPS (1.55V)
VDDPA
VFBSMPS (1.55V)
VDDPA
VR_PA (up to 1.35V)
VR_PA (up to 1.35V)
REG
PA
REG
PA
RFO_LP
RFO_LP
LP PA
LP PA
Note: Use of the SMPS is optional. When SMPS is not used, the BOM can be reduced by removing the coil
between VLXSMPS and VFBSMPS pins.
MSv62617V2
3.8.4
Receiver
The receive chain comprises a differential low-noise amplifier (LNA), a down-converter to
low-IF by mixer operation in quadrature configuration. The I and Q signals are low pass
filtered and a Ʃ∆ ADC converts them into the digital domain. In the digital modem, the
signals are decimated, further down converted and channel filtered. The demodulation is
done according to the selected modulation scheme.
The down mixing to low-IF is done by mixing the receive signal with the local RF-PLL
located in the negative frequency, where -f = -f + -f . (where f is the local RF-PLL
lo
rf
if
lo
frequency, f is the received signal and f is the intermediate frequency). The wanted signal
rf
if
is located at f = f + f .
rf
lo
if
The receiver features automatic I and Q calibration, that improves image rejection. The
calibration is done automatically at startup before using the receiver, and can be requested
by command.
The receiver supports LoRa, (G)MSK and (G)FSK modulations.
3.8.5
RF-PLL
The RF-PLL is used as the frequency synthesizer for the generation of the local oscillator
frequency (f ) for both transmit and receive chains. The RF-PLL uses auto calibration and
lo
uses the 32 MHz HSE32 reference. The sub-GHz radio covers all continuous frequencies in
the range between 150 to 960 MHz.
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3.8.6
Intermediate frequencies
The sub-GHz radio receiver operates mostly in low-IF configuration, except for specific high-
bandwidth settings.
Table 5. FSK mode intermediate frequencies
Setting name
Bandwidth (kHz)
fif (kHz)
RX_BW_467
RX_BW_234
RX_BW_117
RX_BW_58
RX_BW_29
RX_BW_14
RX_BW_7
467.0
234.3
117.3
58.6
29.3
14.6
7.3
250
RX_BW_373
RX_BW_187
RX_BW_93
RX_BW_46
RX_BW_23
RX_BW_11
RX_BW_5
373.6
187.2
93.8
46.9
23.4
11.7
5.8
200
RX_BW_312
RX_BW_156
RX_BW_78
RX_BW_39
RX_BW_19
RX_BW_9
312.0
156.2
78.2
39.0
19.5
9.7
167
RX_BW_4
4.8
Table 6. LoRa mode intermediate frequencies
Setting name
Bandwidth (kHz)
fif (kHz)
LORA_BW_500
LORA_BW_250
LORA_BW_125
LORA_BW_62
LORA_BW_41
LORA_BW_31
LORA_BW_20
500
250
0
125
250
62.5
41.67
31.25
20.83
167
250
167
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Functional overview
Table 6. LoRa mode intermediate frequencies (continued)
Setting name
Bandwidth (kHz)
fif (kHz)
LORA_BW_15
LORA_BW_10
LORA_BW_7
15.63
10.42
7.81
250
167
250
3.9
Power supply management
The devices embed two different regulators: one LDO and one DC/DC (SMPS). The SMPS
can be optionally switched-on by software to improve the power efficiency. As LDO and
SMPS operate in parallel, the SMPS switch-on is transparent to the user and only the power
efficiency is affected.
3.9.1
Power supply schemes
The devices require a V operating voltage supply between 1.8 V and 3.6 V. Several
DD
independent supplies (V
peripherals:
, V
, V
, V
) can be provided for specific
DDSMPS
FBSMPS
DDA
DDRF
•
•
•
•
V
= 1.8 V to 3.6 V
DD
V
is the external power supply for the I/Os, the system analog blocks such as reset,
DD
power management, internal clocks and low-power regulator. It is provided externally
through VDD pins.
V
= 1.8 V to 3.6 V
DDSMPS
V
is the external power supply for the SMPS step-down converter. It is provided
DDSMPS
externally through VDDSMPS supply pin and must be connected to the same supply as
V
V
V
.
DD
= 1.45 V to 1.62 V (1.55 V typical)
FBSMPS
is the external power supply for the main system regulator. It is provided
FBSMPS
externally through VFBSMPS pin and is supplied through the SMPS step-down
converter.
V
= 0 V to 3.6 V (DAC minimum voltage is 1.71 V without buffer and 1.8 V with
DDA
buffer. COMP and ADC minimum voltage is 1.62 V. VREFBUF minimum voltage is
2.4 V)
V
is the external analog power supply for A/D converters, D/A converters, voltage
DDA
reference buffer, and comparators. The V
voltage level is independent from the V
DDA
DD
voltage (see power-up and power-down limitations below) and must preferably be
connected to V when these peripherals are not used.
DD
•
•
•
V
= 1.8 V to 3.6 V
DDRF
V
is an external power supply for the radio. It is provided externally through the
DDRF
VDDRF pin and must be connected to the same supply as V
.
DD
V
= 1.45 V to 1.62 V
DDRF1V5
V
is an external power supply for the radio. It is provided externally through the
DDRF1V5
VDDRF1V5 pin and must be connected externally to VFBSMPS.
V
= 1.55 V to 3.6 V
BAT
V
is the power supply for RTC, TAMP, external clock 32 kHz oscillator and backup
BAT
registers (through power switch) when V is not present.
DD
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Functional overview
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•
VREF-, VREF+
is the input reference voltage for ADC and DAC. It is also the output of the
V
REF+
internal voltage reference buffer when enabled.
–
–
V
When V
When V
< 2 V, V
must be equal to V
.
DDA
DDA
DDA
REF+
REF+
≥ 2 V, V
must be between 2 V and V
.
DDA
can be grounded when ADC/DAC is not active. The internal voltage reference
REF+
buffer supports the following output voltages, configured with VRS bit in the
VREFBUF_CSR register:
–
–
V
V
around 2.048 V: this requires V
≥ 2.4 V.
REF+
REF+
DDA
around 2.5 V: this requires V
≥ 2.8 V.
DDA
During power up and power down, the following power sequence is required:
1. When V < 1 V other power supplies (V ) must remain below V + 300 mV.
DD
DDA
DD
During power down, V can temporarily become lower then other supplies only if the
DD
energy provided to the device remains below 1 mJ. This allows external decoupling
capacitors to be discharged with different time constants during this transient phase.
2. When V > 1 V, all other power supplies (V
) become independent.
DDA
DD
An embedded linear voltage regulator is used to supply the internal digital power V
.
CORE
V
is the power supply for digital peripherals, SRAM1 and SRAM2. The Flash memory
CORE
is supplied by V
and V . V
is split in two parts: V
part and an interruptible
CORE
DD
CORE
DDO
part V
.
DDI
Figure 5. Power-up/power-down sequence
V
3.6
VDDA
VDD
VBOR0
1
0.3
Power-on
Operating mode
Power-down
VDDA independent from VDD
time
Invalid supply area
VDDA < VDD + 300 mV
MSv68044V1
Note:
V
, V
and V must be wired together, so they can follow the same voltage
DDSMPS
DD
DDRF
sequence.
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Functional overview
Figure 6. Power supply overview
VSW
VBAT
VDD
en
VDDSMPS
VLXSMPS
POR
LDO/SMPS
FW mode
mode
VFBSMPS
VDDRF1V5
LPR
MR
RFLDO
VLP
VMAIN
VBKP
VRF
VDDO
VDDI
MSv50973V1
The different supply configurations are shown in the figure below.
Figure 7. Supply configurations
VDD
VDD
VDDSMPS
VLXSMPS
VDDSMPS
VLXSMPS
LDO/SMPS
MR
LDO/SMPS
MR
VFBSMPS
VDDRF1V5
VFBSMPS
VDDRF1V5
LPR
LPR
RF
LDO
RF
LDO
LDO/SMPS supply
LDO supply
MSv50974V1
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The LDO or SMPS step-down converter operating mode can be configured by one of the
following:
•
by the MCU using the SMPSEN setting in PWR control register 5 (PWR_CR5), that
depends upon the MCU system operating mode (Run, Stop, Standby or Shutdown).
•
by the sub-GHz radio using SetRegulatorMode() command and the sub-GHz radio
operating mode (Sleep, Calibrate, Standby, Standby with HSE32 or Active).
After any POR and NRST reset, the LDO mode is selected. The SMPS selection has priority
over LDO selection.
While the sub-GHz radio is in Standby with HSE32 or in Active mode, the supply mode is
not altered until the sub-GHz radio enters Standby or Sleep mode. The sub-GHz radio
activity may add a delay for entering the MCU software requested supply mode.
The LDO or SMPS supply mode can be checked with the SMPSRDY flag in power status
register 2 (PWR_SR2).
Note:
When the radio is active, the supply mode is not changed until after the radio activity is
finished.
During Stop 1, Stop 2 and Standby modes, when the sub-GHz radio is not active, the LDO
or SMPS step-down converter is switched off. When exiting low-power modes (except
Shutdown), the SMPS step-down converter is set by hardware to the mode selected by the
SMPSEN bit in PWR control register 5 (PWR_CR5). SMPSEN is retained in Stop and
Standby modes.
Independently from the MCU software selected supply operating mode, the sub-GHz radio
allows the supply mode selection while the sub-GHz radio is active (thanks to the sub-GHz
radio SetRegulatorMode()command).
The maximum load current delivered by the SMPS can be selected by the sub- GHz radio
SUBGHZ_SMPSC2R register.
The inrush current of the LDO and SMPS step-down converter can be controlled via the
sub- GHz radio SUBGHZ_PCR register. This information is retained in all but the sub-GHz
radio Deep-sleep mode.
The SMPS needs a clock to be functional. If for any reason this clock stops, the device may
be destroyed. To avoid this situation, a clock detection is used to, in case of a clock failure,
switch off the SMPS and enable the LDO. The SMPS clock detection is enabled by the sub-
GHz radio SUBGHZ_SMPSC0R.CLKDE. By default, the SMPS clock detection is disabled
and must be enabled before enabling the SMPS.
Danger:
Before enabling the SMPS, the SMPS clock detection must be
enabled in the sub-GHz radio SUBGHZ_SMPSC0R.CLKDE.
3.9.2
Power supply supervisor
The devices integrate a power-on reset/power-down reset, coupled with a Brownout reset
(BOR) circuitry.
BOR0 level cannot be disabled. Other BOR levels can be enabled by user option. When
enabled, BOR is active in all power modes except in Shutdown
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Functional overview
Five BOR thresholds can be selected through option bytes.
During power-on, BOR keeps the device under reset until the supply voltage V reaches
DD
the specified V
threshold:
BORx
•
•
When V drops below the selected threshold, a device reset is generated.
DD
When V is above the V
upper limit, the device reset is released and the system
BORx
DD
can start.
The devices feature an embedded PVD (programmable voltage detector) that monitors the
power supply and compares it with the V threshold. An interrupt can be generated
V
DD
PVD
when V drops below the V
threshold and/or when V is higher than the V
DD
PVD
DD PVD
threshold. The interrupt service routine can then generate a warning message and/or put
the MCU into a safe state.
The PVD is enabled by software and can be configured to monitor the V supply level
DD
needed for the sub-GHz radio operation. For this, the PVD must select its lowest threshold,
and the PVD and the wakeup must be enabled by the EWPVD bit in PWR_CR3 register.
Only a voltage drop below the PVD level generates a wakeup event.
In addition, the devices embed a PVM (peripheral voltage monitor) that compares the
independent supply voltage V
functional supply range.
with a fixed threshold to ensure that the peripheral is in its
DDA
Finally, a radio end-of-life monitor provides information on the V supply when V is too
DD
DD
low to operate the sub-GHz radio. When reaching the EOL level, the software must stop all
radio activity in a safe way.
3.9.3
Linear voltage regulator
Two embedded linear voltage regulators supply all the digital circuitries, except for the
Standby circuitry and the Backup domain. The main regulator (MR) output voltage (V
)
CORE
can be programmed by software to two different power ranges (range 1 and range 2), to
optimize the consumption depending on the system maximum operating frequency.
The voltage regulators are always enabled after a reset. Depending on the application
modes, the V
supply is provided either by the main regulator or by the low-power
CORE
regulator (LPR).
When MR is used, a dynamic voltage scaling is proposed to optimize power as follows:
•
•
range 1: high-performance range
The system clock frequency can be up to 48 MHz. The Flash memory access time for
read access is minimum. Write and erase operations are possible.
range 2: low-power range
The system clock frequency can be up to 16 MHz.The Flash memory access time for a
read access is increased as compared to range 1. Write and erase operations are
possible.
Note:
MR is supplied by V during power-on or at wakeup from Stop1, Stop2, Standby or
DD
Shutdown mode. MR is powered by LDO/SMPS after these transition phases.
3.9.4
VBAT operation
The VBAT pin is used to power the device V
domain (RTC, LSE and backup registers)
BAT
from an external battery, an external super-capacitor, or from V when no external battery
DD
DS13105 Rev 8
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48
Functional overview
STM32WLE5/E4xx
nor an external super-capacitor are present. Three anti-tamper detection pins are available
in VBAT mode.
VBAT operation is automatically activated when V is not present.
DD
An internal V
present.
battery charging circuit is embedded and can be activated when V is
DD
BAT
Note:
When the microcontroller is supplied only from V
alarm/events do not exit it from VBAT operation.
, external interrupts and RTC
BAT
3.10
Low-power modes
The devices support several low-power modes to achieve the best compromise between
low-power consumption, short startup time, available peripherals and available wakeup
sources.
By default, the microcontroller is in Run mode, range 1, after a system or a power-on reset.
It is up to the user to select one of the low-power modes described below:
•
Sleep mode: CPU clock off, all peripherals including CPU core peripherals (among
them NVIC, SysTick) can run and wake up the CPU when an interrupt or an event
occurs.
•
Low-power run mode (LPRun): when the system clock frequency is reduced below
2 MHz. The code is executed from the SRAM or from the Flash memory. The regulator
is in low-power mode to minimize the operating current.
•
•
Low-power sleep mode (LPSleep): entered from the LPRun mode.
Stop 0 and Stop 1 modes: the content of SRAM1, SRAM2 and of all registers is
retained. All clocks in the V
domain are stopped. PLL, MSI, HSI16 and HSE32 are
CORE
disabled. LSI and LSE can be kept running.
RTC can remain active (Stop mode with RTC, Stop mode without RTC). The sub-GHz
radio may remain active independently from the CPU.
Some peripherals with the wakeup capability can enable HSI16 RC during the Stop
mode to detect their wakeup condition.
Stop 1 offers the largest number of active peripherals and wakeup sources, a smaller
wakeup time but a higher consumption compared with Stop 2.
In Stop 0 mode, the main regulator remains on, resulting in the fastest wakeup time but
with much higher consumption. The active peripherals and wakeup sources are the
same as in Stop 1 mode that uses the low-power regulator.
The system clock, when exiting Stop 0 or Stop 1 mode, can be either MSI up to 48 MHz
or HSI16, depending on the software configuration.
•
Stop 2 mode: part of the V
and some peripherals preserve their contents (see Table 7).
domain is powered off. Only SRAM1, SRAM2, CPU
CORE
All clocks in the V domain are stopped. PLL, MSI, HSI16 and HSE32 are disabled.
CORE
LSI and LSE can be kept running.
RTC can remain active (Stop 2 mode with RTC, Stop 2 mode without RTC). The sub-
GHz radio may also remain active independent from the CPU.
Some peripherals with the wakeup capability can enable HSI16 RC during the Stop 2
mode to detect their wakeup condition (see Table 7).
The system clock when exiting from Stop 2 mode, can be either MSI up to 48 MHz or
28/145
DS13105 Rev 8
STM32WLE5/E4xx
Functional overview
HSI16, depending on the software configuration.
•
Standby mode: V
SRAM2 content as detailed below:
domain is powered off. However, it is possible to preserve the
CORE
–
Standby mode with SRAM2 retention when the RRS bit is set in the PWR control
register 3 (PWR_CR3). In this case, SRAM2 is supplied by the low-power
regulator.
–
Standby mode when the RRS bit is cleared in the PWR control register 3
(PWR_CR3). In this case the main regulator and the low-power regulator are
powered off.
All clocks in the V
domain are stopped. PLL, MSI, HSI16 and HSE32 are disabled.
CORE
LSI and LSE can be kept running.
Th RTC can remain active (Standby mode with RTC, Standby mode without RTC). The
sub-GHz radio and the PVD may also remain active when enabled independent from
the CPU. In Standby mode, the PVD selects its lowest level.
The system clock, when exiting Standby modes, is MSI at 4 MHz.
•
Shutdown mode: V
domain is powered off. All clocks in the V
domain are
CORE
CORE
stopped. PLL, MSI, HSI16, LSI and HSE32 are disabled. LSE can be kept running. The
system clock when exiting the Shutdown mode, is MSI at 4 MHz. In this mode, the
supply voltage monitoring is disabled and the product behavior is not guaranteed in
case of a power voltage drop.
The table below summarizes the peripheral features over all available modes. Wakeup
capability is detailed in gray cells.
(1)
Table 7. Functionalities depending on system operating mode
Stop 0
Stop 1
Stop 2 Standby Shutdown
Peripheral
-
-
-
-
-
CPU
Y
R
O
Y
R
O
R
O
-
R
O
-
R
O
-
-
-
-
-
-
-
-
-
Sub-GHz radio system
O
O
O
O
O
O
O
Flash memory
(up to 256 Kbytes)
O(2)
Y
O(2) O(3)
R
-
R
-
R
-
R
-
R
-
R
(3)
Flash memory interface
SRAM1
Y
Y
Y
Y
Y
Y
O(2)
O(2)
Y
Y
Y
Y
Y
Y
Y
O(2)
O(2)
Y
R
R
R
R
Y
-
-
R
R
R
R
Y
-
-
R
R
R
R
Y
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
SRAM2
-
-
-
O(4)
-
-
-
Backup registers
Brownout reset (BOR)
-
-
-
R
-
R
-
R
-
Y
Y
Y
Y
Y
Y
Y
Programmable voltage
detector (PVD)
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O(5) O(5)
-
-
-
-
-
-
Peripheral voltage monitor
(PVM3)
-
-
DS13105 Rev 8
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48
Functional overview
STM32WLE5/E4xx
(1)
Table 7. Functionalities depending on system operating mode (continued)
Stop 0 Stop 1 Stop 2 Standby Shutdown
Peripheral
-
-
-
-
-
DMAx (x = 1, 2)
O
O
O
O
O
O
O
O
O
O
3
O
O
O
O
O
O
O
O
O
O
3
O
O
O
O
O
O
R
R
-
-
R
R
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
DMAMUX1
-
High-speed internal (HSI16)
High-speed external (HSE32)
Low-speed internal (LSI)
Low-speed external (LSE)
Multi-speed internal (MSI)
Clock security system (CSS)
Clock security system on LSE
RTC/auto wakeup
Number of tamper pins
USARTx (x= 1, 2)
Low-power UART (LPUART1)
I2Cx (x = 1, 2)
O(6)
-
O(6)
O(7)
O
-
O(6)
O(7)
O
O
O
-
-
-
-
-
-
-
O(7) O(7) O(7)
-
-
-
O(7)
-
-
-
-
O
O
O
O
O
O
3
O
O
O
O
O
O
3
O
O
O
R
O
O
3
-
-
-
O
O
-
-
-
-
-
-
O
-
-
-
O
-
-
O
-
-
O
-
-
-
-
-
R
-
-
-
-
-
-
-
O
O
O
O
O
O
O
O
O
3
O
O
O
-
O
O
3
-
O
O
O
-
-
-
-
O
O
3
-
O
O
-
O
3
-
3
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O(8) O(8) O(8) O(8)
-
O(8) O(8) O(8) O(8) O(8) O(8)
O(9) O(9) O(9) O(9)
O(9) O(9) O(9) O(9) O(9) O(9)
-
-
-
-
-
-
-
-
-
-
-
-
I2C3
-
-
-
-
-
SPI1
R
R
R
R
R
O
O
R
R
O
O
-
-
R
R
R
R
R
O
O
R
R
O
O
-
-
-
-
-
-
-
-
-
-
-
SUBGHZSPI
-
-
-
-
-
SPI2S2
-
-
-
-
-
-
-
-
-
ADC
-
-
-
-
-
-
-
-
-
DAC
-
-
-
-
-
-
-
-
-
VREFBUF
-
-
R
O
-
-
-
-
-
-
-
COMPx (x = 1, 2)
Temperature sensor
TIMx (x = 1, 2, 16, 17)
LPTIM1
O
-
O
-
O
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
O
O
O
O
O
-
O
-
-
-
-
-
-
LPTIMx (x = 2, 3)
-
-
-
-
-
Independent watchdog
(IWDG)
O
O
O
O
O
O
O
O
O
O
O
O
-
-
-
Window watchdog (WWDG)
SysTick timer
O
O
O
O
O
O
O
O
R
R
-
-
R
R
-
-
R
R
-
-
-
-
-
-
-
-
-
-
-
-
30/145
DS13105 Rev 8
STM32WLE5/E4xx
Functional overview
(1)
Table 7. Functionalities depending on system operating mode (continued)
Stop 0 Stop 1 Stop 2 Standby Shutdown
Peripheral
-
-
-
-
-
True random number
generator (RNG)
O
O(1
R
R
R
-
R
-
-
-
-
-
-
-
-
(10)
0)
AES hardware accelerator
PKA hardware accelerator
CRC calculation unit
HSEM
O
O
O
O
O
O
O
O
R
O
O
O
O
O
O
O
O
O
R
O
R
R
R
R
R
-
-
R
R
R
R
R
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
R
-
-
-
-
-
EXTI
O
O
R
O
3
pin
3
R
(13)
GPIOs
O
O
O
O
O
O
O
O
O
O
pins
-
(11)
s
(12)
(12)
1. Legend: Y = Yes (enabled). O = Optional (disabled by default and can be enabled by software). R = data retained.
- = Not available. Gray cells indicate wakeup capability.
2. The SRAM clock can be gated on or off.
3. Flash memory can be placed in power-down mode.
4. The SRAM2 content can optionally be retained when the PWR_CR3.RRS bit is set.
5. Only when the sub-GHz radio is active.
6. Some peripherals with wakeup from Stop capability can request HSI16 to be enabled. In this case, HSI16 is woken up by
the peripheral, and only feeds the peripheral that requested it. HSI16 is automatically put off when the peripheral does not
need it anymore.
7. HSE32 can be used by sub-GHz radio system.
8. USART reception is functional in Stop 0 and Stop 1 modes. LPUART1 reception is functional is Stop 0, Stop 1, and Stop 2
modes. LPUART1 generates a wakeup interrupt on Start address match or received frame event.
9. I2Cx (x= 1, 2) address detection is functional in Stop 0 and Stop 1 modes. I2C3 address detection is functional in Stop 0,
Stop 1 and Stop 2 modes. I2C3 generates a wakeup interrupt in case of address match.
10. Voltage scaling range 1 only.
11. I/Os can be configured with internal pull-up, pull-down or floating in Standby mode.
12. The I/Os with wakeup from Standby/Shutdown capability are PA0, PC13 and PB3.
13. I/Os can be configured with internal pull-up, pull-down or floating in Shutdown mode, but the configuration is lost when
exiting the Shutdown mode.
DS13105 Rev 8
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48
Functional overview
STM32WLE5/E4xx
Table 8. Low-power mode summary
Voltage
Wakeup
Wakeup
system clock
regulators
Mode name
Entry
Effect on clocks
source(1)
MR LPR
WFI or return
from ISR
CPU clock OFF
Sleep
(Sleep-now or
Sleep-on-exit)
Any interrupt
Wakeup event
Clear LPR bit
Same as before
entering Sleep mode
ON ON
No effect on other clocks
or analog clock sources
WFE
Same as LPRun
clock
LPRun
Set LPR bit
None
OFF ON
OFF ON
OFF ON
Set LPR bit +
WFI or return
from ISR
Any interrupt
CPU clock OFF
Same as before
entering LPSleep
mode
LPSleep
No effect on other clocks
or analog clock sources
Set LPR bit +
WFE
Wakeup event
LPMS = 0b000 +
SLEEPDEEP bit
+ WFI or return
from ISR or WFE
Stop 0
ON
HSI16 when
LPMS = 0b001 + Any EXTI line
STOPWUCK = 1 in
SLEEPDEEP bit (configured in the RCC_CFGR.
Stop 1
Stop 2
All clocks OFF
except HSI16, LSI and
LSE
+ WFI or return
from ISR or WFE
EXTI registers).
MSI with the
ON
Specific
peripherals
events
frequency before
entering the Stop
mode when
OFF
LPMS = 0b010+
SLEEPDEEP bit
+ WFI or return
from ISR or WFE
(with I2C3,
LPUART1,
LPTIM1,
STOPWUCK = 0.
SRAM1,
SRAM2)
LPMS = 0b011+
Set RRS bit +
SLEEPDEEP bit
+ WFI or return
from ISR or WFE
Wakeup PVD,
RFIRQ, wakeup
RFBUSY, WKUP
pin edge, RTC
Standby (with
SRAM2)
OFF ON
OFF OFF
OFF OFF
All clocks OFF
except LSI and LSE
and TAMP event, MSI 4 MHz
LSECSS,
external reset in
NRST pin,
LPMS = 0b011 +
Clear RRS bit +
SLEEPDEEP bit
+ WFI or return
from ISR or WFE
Standby
IWDG reset
WKUP pin edge,
RTC and TAMP
LPMS = 0b1xx +
SLEEPDEEP bit
+ WFI or return
from ISR or WFE
All clocks OFF
except LSE
Shutdown
event, external
reset in NRST
pin
MSI 4 MHz
1. Refer to Table 7: Functionalities depending on system operating mode.
32/145
DS13105 Rev 8
STM32WLE5/E4xx
Functional overview
Relation between MCU and sub-GHz radio operating modes
The CPU and sub-GHz radio have their own operating modes (see the table below).
Table 9. MCU and sub-GHz radio operating modes
CPU operating mode
Sub-GHz radio operating mode
Description
Sleep, Calibration, Standby, Active
(FS, TX, RX)
LDO or SMPS regulator active, MCU running in
main regulator (MR) mode
Run, Sleep
(1)
LDO and SMPS regulator off, MCU running in low
power regulator (LPR) mode
Deep-Sleep
LPRun, LPSleep
Stop 0
Sleep, Calibration, Standby, Active
(FS, TX, RX)
LDO or SMPS regulator active, MCU running in low
power regulator (LPR) mode
Sleep, Calibration, Standby, Active
(FS, TX, RX)(1)
LDO or SMPS regulator active, MCU running in
main regulator (MR) mode
LDO and SMPS regulator off, MCU using low power
regulator (LPR) mode
Deep-Sleep
Stop 1 and Stop 2
Sleep, Calibration, Standby, Active
(FS, TX, RX)
LDO or SMPS regulator active, MCU using low
power regulator (LPR) mode
LDO and SMPS regulator off, MCU regulator off or
Deep-Sleep
on in low power (LPR) mode(2)
.
Standby
Sleep, Calibration, Standby, Active
(FS, TX, RX)
LDO or SMPS regulator active, MCU regulator off or
on in low power (LPR) mode(2)
Shutdown
Deep-Sleep(3)
LDO and SMPS regulator off, MCU regulator off
1. In the MCU Run, Sleep and Stop 0 modes, the sub-GHz radio is prevented from entering Deep-sleep mode.
2. When retaining SRAM2 in Standby mode, the MCU uses the low-power regulator (LPR) mode.
3. When the CPU is in Shutdown mode, the sub-GHz radio cannot be activated and is forced in Deep-sleep mode.
3.10.1
Reset mode
In order to improve the consumption under reset, the I/Os state under and after reset is
"analog state" (the I/O Schmitt trigger is disabled). In addition, the internal reset pull-up is
deactivated when the reset source is internal.
This excludes the five serial-wire JTAG debug ports that are in pull-up/pull-down after reset.
3.11
Peripheral interconnect matrix
Several peripherals have direct connections between them. This allows autonomous
communication between peripherals, saving CPU resources and, consequently, reducing
power-supply consumption. In addition, these hardware connections allow fast and
predictable latency.
Depending on peripherals, these interconnections can operate in Run, Sleep, LPRun,
LPSleep, Stop 0, Stop 1 and Stop 2 modes.
DS13105 Rev 8
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48
Functional overview
STM32WLE5/E4xx
(1) (2)
Table 10. Peripherals interconnect matrix
Destination
Source
TIM1
TIM2
-
X
-
X
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
X
X
-
X
X
-
X
X
-
X
X
-
-
-
-
-
-
-
TIM16
TIM17
LPTIM1
LPTIM2
LPTIM3
ADC
-
-
-
X
X
-
-
X
-
-
-
-
-
-
-
-
-
-
X
X
-
-
X
X
-
-
-
X
X
X
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
X
-
X
-
-
-
-
-
-
Temperature
sensor
-
-
-
-
-
-
-
X
-
-
-
-
-
-
VBAT(3)
VREFINT
HSE32
LSE
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
X
X
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
X
-
-
-
-
-
-
X
-
X
-
-
-
-
-
-
MSI
-
X
-
-
-
-
-
-
LSI
-
-
X
-
-
-
-
-
-
MCO
-
-
X
-
-
-
-
-
-
GPIO EXTI
RTC
-
-
-
-
-
X
-
X
-
X
-
-
-
X
-
-
X
X
X
X
-
X
X
X
X
-
TAMP
-
-
-
-
-
-
COMP1
COMP2
SYST ERR
X
X
X
X
X
-
X
X
X
X
X
X
-
-
-
-
-
-
-
-
-
1. For more details, refer to section “Interconnection details” of the reference manual.
2. The “-” symbol in grayed cells means no interconnect.
3. VDD on STM32WLE5/4UxYx devices.
34/145
DS13105 Rev 8
STM32WLE5/E4xx
Functional overview
3.12
Reset and clock controller (RCC)
The following different clock sources can be used to drive the system clock (SYSCLK):
•
•
•
•
HSI16 (high-speed internal) 16 MHz RC oscillator clock
MSI (multi-speed internal) RC oscillator clock from 100 kHz to 48 MHz
HSE32 (high-speed external) 32 MHz oscillator clock, with trimming capacitors.
PLL clock
The MSI is used as system clock source after startup from reset, configured at 4 MHz.
The devices have the following additional clock sources:
•
LSI: 32 kHz low-speed internal RC that may drive the independent watchdog and
optionally the RTC used for auto-wakeup from Stop and Standby modes.
•
LSE: 32.768 kHz low-speed external crystal that optionally drives the RTC used for
auto-wakeup from Stop, Standby and Shutdown modes, or the real-time clock
(RTCCLK).
Each clock source can be switched on or off independently when it is not used, to optimize
power consumption.
Several prescalers can be used to configure the AHB frequencies (HCLK3/PCLK3, HCLK1),
the high-speed APB2 (PCLK2) and the low-speed APB1 (PCLK1) domains. The maximum
frequency of the AHB (HCLK3, HCLK1), the PCLK1 and the PCLK2 domains is 48 MHz.
Most peripheral clocks are derived from their bus clock (HCLK, PCLK) except the following:
•
The clock used for true RNG, is derived (selected by software) from one of the following
sources:
–
–
–
–
PLL VCO (PLLQCLK) (only available in Run mode)
MSI (only available in Run mode)
LSI clock
LSE clock
•
The ADC clock is derived (selected by software) from one of the following sources:
–
–
–
system clock (SYSCLK) (only available in Run mode)
HSI16 clock (only available in Run mode)
PLL VCO (PLLPCLK) (only available in Run mode)
•
•
The DAC uses the LSI clock in sample and hold mode
The (LP)U(S)ARTs clocks are derived (selected by software) from one of the following
sources:
–
–
–
–
system clock (SYSCLK) (only available in Run mode)
HSI16 clock (available in Run and Stop modes)
LSE clock (available in Run and Stop modes)
APB clock (PCLK depending on which APB the U(S)ART is mapped) (available in
CRun and CSleep when also enabled in (LP)U(S)ARTxSMEN)
The wakeup from Stop mode is supported only when the clock is HSI16 or LSE.
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•
The I2Cs clocks are derived (selected by software) from one of the following sources:
–
–
–
system clock (SYSCLK) (only available in Run mode)
HSI16 clock (available in Run and Stop modes)
APB clock (PCLK depending on which APB the I2C is mapped) (available in CRun
and CSleep when also enabled in I2CxSMEN.)
The wakeup from Stop mode is supported only when the clock is HSI16.
•
•
The SPI2S2 I2S clock is derived (selected by software) from one of the following
sources:
–
–
–
HSI16 clock (only available in Run mode)
PLL VCO (PLLQCLK) (only available in Run mode)
external input I2S_CK (available in Run and Stop modes)
The low-power timers (LPTIMx) clock is derived (selected by software) from one of the
following sources:
–
–
–
–
LSI clock (available in Run and Stop modes)
LSE clock (available in Run and Stop modes)
HSI16 clock (only available in Run mode)
APB clock (PCLK depending on which APB the LPTIMx is mapped) (available in
Run and CStop when enabled in LPTIMxSMEN.)
–
external clock mapped on LPTIMx_IN1 (available in Run and Stop modes)
The functionality in Stop mode (including wakeup) is supported only when the clock is
LSI or LSE, or in external clock mode.
•
•
The RTC clock is derived (selected by software) from one of the following sources:
–
–
–
LSE clock
LSI clock
HSE32 clock divided by 32
The functionality in Stop mode (including wakeup) is supported only when the clock is
LSI or LSE.
The IWDG clock is always the LSI clock.
The RCC feeds the CPU system timer (SysTick) external clock with the AHB clock (HCLK1)
divided by eight. The SysTick can work either with this clock or directly with the CPU clock
(HCLK1), configurable in the SysTick control and status register.
FCLK1 acts as CPU free-running clock. For more details, refer to the programming manual
STM32 Cortex-M4 MCUs and MPUs programming manual (PM0214).
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Figure 8. Clock tree
to IWDG
to RTC
LSI RCC 32 kHz
LSCO
LSI
LSE OSC
OSC32_OUT
OSC32_IN
32.768 kHz
LSE
LSE CSS
LSI
CPU
/32
LSE
HCLK1
to CPU, AHB1, AHB2
to CPU FCLK
HPRE
/1,2,...,512
HSE32
SYSCLK
PLLRCLK
PLLQCLK
PLLPCLK
HSI16
to CPU system timer
/8
MCO
/1 - 16
APB1
PPRE1
/1,2,4,8,16
PCLK1
to APB1
SYS clock
source
x1 or
x2
to APB1 TIMx
control
PLLRCLK
MSI
APB2
PPRE2
/1,2,4,8,16
MSI
PCLK2
to APB2
HSE32 OSC
32 MHz
x1 or
x2
OSC_OUT
OSC_IN
to APB2 TIMx
SYSCLK
HSE CSS
HSEPRE
/1,2
HSE32
HSI16 RC
16 MHz
HSI16
MSI RC
AHB3
SHDHPRE
/1,2,...,512
100 kHz - 48 MHz
HCLK3
to AHB3, Flash, SRAM1, SRAM2
MSI
PCLK3
to APB3
to RF
HSI16
/M
PCLKn
PCLKn
HSI16
LSI
HSI16
SYSCLK
HSI16
LSE
SYSCLK
to ADC
to USART1
to LPTIM1
to LPTIM2
to LPTIM3
PLL
to USART2
x
N
PLLPCLK
to LPUART1
/P
/Q
/R
LSE
PLLQCLK
PLLRCLK
LSI
LSE
MSI
PCLKn
SYSCLK
HSI16
to SPI2S2
HSI16
to RNG
LSI
to I2C1
to I2C2
to I2C3
I2S_CKIN
DAC
MSv62605V2
1. For full details about the internal and external clock source characteristics, refer to the electrical characteristics section in
the device datasheet.
2. The ADC clock can additionally be derived from the AHB clock of the ADC bus interface, divided by a programmable factor
(1, 2 or 4). When the programmable factor is 1, the AHB prescaler must be equal to 1.
3.13
Hardware semaphore (HSEM)
The HSEM provides a 16- (32-bit) register based semaphores. The semaphores can be
used to ensure synchronization between different processes running on the core. The
HSEM provides a non blocking mechanism to lock semaphores in an atomic way. The
following functions are provided:
•
Locking a semaphore can be done in two ways:
–
2-step lock: by writing COREID and PROCID to the semaphore, followed by a
read check
–
1-step lock: by reading the COREID from the semaphore
•
•
•
Interrupt generation when a semaphore is unlocked: Each semaphore may generate
an interrupt on one of the interrupt lines.
Semaphore clear protection: A semaphore is only unlocked when COREID and
PROCID match.
Global semaphore clear per COREID
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3.14
General-purpose inputs/outputs (GPIOs)
Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as
input (with or without pull-up or pull-down) or as peripheral alternate function. Most of the
GPIO pins are shared with digital or analog alternate functions. Fast I/O toggling can be
achieved thanks to their mapping on the AHB2 bus.
The I/Os alternate function configuration can be locked if needed following a specific
sequence in order to avoid spurious writing to the I/Os registers.
3.15
Direct memory access controller (DMA)
The DMA (direct memory access) is used to provide high-speed data transfer between
peripherals and memory, as well as memory to memory. Data can be quickly moved by
DMA without any CPU actions. This keeps CPU resources free for other operations.
The DMA controller has 14 channels in total. A full cross matrix allows the peripherals, with
DMA support, to be mapped on any of the available DMA channels. Each DMA channel has
an arbiter for handling the priority between DMA requests.
The DMA main features are listed below:
•
•
14 independently configurable channels (requests)
a full cross matrix between peripherals and all 14 channels and an hardware trigger
possibility through the DMAMUX1
•
•
software programmable priorities between requests from channels of one DMA (four
levels: very-high, high, medium, low), plus hardware priorities management in case of
equality (example: request 1 has priority over request 2)
independent source and destination transfer size (byte, half-word, word), emulating
packing and unpacking. Source/destination addresses must be aligned on the data
size.
•
•
support for circular buffer management
three event flags (DMA half-transfer, DMA transfer complete and DMA transfer error),
logically ORed together in a single interrupt request for each channel
•
•
•
•
memory-to-memory transfer
peripheral-to-memory, memory-to-peripheral, and peripheral-to-peripheral transfers
access to Flash memory, SRAM, APB and AHB peripherals, as source and destination
programmable number of data to be transferred (up to 65536)
Table 11. DMA1 and DMA2 implementation
Feature
Number of channels
DMA1
DMA2
7
7
DMAMUX1 is used to route the peripherals with DMA source support, to any DMA channel.
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3.16
Interrupts and events
3.16.1
Nested vectored interrupt controller (NVIC)
The devices embed an NIVC able to manage 16 priority levels, and to handle up to
62 maskable interrupt channels plus the 16 interrupt lines of the Cortex-M4.
The NVIC benefits are the following:
•
•
•
•
•
•
•
low-latency interrupt processing
interrupt entry vector table address passed directly to the core
early processing of interrupts
processing of late-arriving higher-priority interrupts
support for tail chaining
processor state automatically saved
interrupt entry restored on interrupt exit, with no instruction overhead
The NVIC hardware block provides flexible interrupt management features with minimal
interrupt latency.
3.16.2
Extended interrupt/event controller (EXTI)
The EXTI manages wakeup through configurable and direct event inputs. It provides wake-
up requests to the power control, and generates interrupt requests to the CPU NVIC and
events to the CPU event input.
Configurable events/interrupts come from peripherals that are able to generate a pulse and
allow the selection between the event/interrupt trigger edge and a software trigger.
Direct events/interrupts come from peripherals having their own clearing mechanism.
3.17
Cyclic redundancy check (CRC)
The CRC calculation unit is used to get a CRC code from 8-, 16- or 32-bit data word and a
generator polynomial.
Among other applications, CRC-based techniques are used to verify data transmission or
storage integrity. In the scope of the functional safety standards, they offer a means of
verifying the Flash memory integrity. The CRC calculation unit helps to compute a signature
of he software during runtime, to be compared with a reference signature generated at link
time and stored at a given memory location.
3.18
Analog-to-digital converter (ADC)
A native 12-bit ADC is embedded into the devices. It can be extended to 16-bit resolution
through hardware oversampling. The ADC has up to 12 external channels and four internal
(a)
channels (temperature sensor, voltage reference, V
monitoring, DAC output). The
BAT
ADC performs conversions in single-shot or scan mode. In scan mode, automatic
conversion is performed on a selected group of analog inputs.
a. VDD on STM32WLE5/E4UxYx devices.
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The ADC frequency is independent from the CPU frequency, allowing maximum sampling
rate of ~2 Msps even with a low CPU speed. An auto-shutdown function guarantees that the
ADC is powered off except during the active conversion phase.
The ADC can be served by the DMA controller. It can operate in the whole V supply
DD
range.
The ADC features a hardware oversampler up to 256 samples, improving the resolution to
16 bits. Refer to the application note Improving STM32F1 Series, STM32F3 Series and
STM32Lx Series ADC resolution by oversampling (AN2668).
An analog watchdog feature allows very precise monitoring of the converted voltage of one,
some or all scanned channels. An interrupt is generated when the converted voltage is
outside the programmed thresholds.
The events generated by the general-purpose timers (TIMx) can be internally connected to
the ADC start triggers, to allow the application to synchronize A/D conversions with timers.
3.18.1
Temperature sensor
The temperature sensor (TS) generates a V voltage that varies linearly with temperature.
TS
The temperature sensor is internally connected to the ADC VIN[12] input channel, to
convert the sensor output voltage into a digital value.
The sensor provides good linearity but it has to be calibrated to obtain good overall
accuracy of the temperature measurement. As the offset of the temperature sensor may
vary from part to part due to process variation, the uncalibrated internal temperature sensor
is suitable only for relative temperature measurements.
To improve the accuracy of the temperature sensor, each part is individually factory-
calibrated by ST. The resulting calibration data is stored in the device engineering bytes,
accessible in read-only mode.
Table 12. Temperature sensor calibration values
Calibration value
Description
Memory address
name
TS ADC raw data acquired at 30 °C (± 5 °C),
VDDA = VREF+ = 3.3 V (± 10 mV)
TS_CAL1
0x1FFF 75A8 - 0x1FFF 75A9
0x1FFF 75C8 - 0x1FFF 75C9
TS ADC raw data acquired at 130 °C (± 5 °C),
VDDA = VREF+ = 3.3 V (± 10 mV)
TS_CAL2
3.18.2
Internal voltage reference (V
)
REFINT
V
provides a stable (bandgap) voltage output for the ADC and comparators. V
REFINT
REFINT
is internally connected to the ADC VIN[13] input channel.
V
is individually and precisely measured, for each part, by ST, during production test
REFINT
and stored in the device engineering bytes. It is accessible in read-only mode.
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Table 13. Internal voltage reference calibration values
Calibration value name
Description
Memory address
Raw data acquired at 30 °C (± 5 °C),
VREFINT_CAL
0x1FFF 75AA - 0x1FFF 75AB
VDDA = VREF+ = 3.3 V (± 10 mV)
3.18.3
V
battery voltage monitoring
BAT
(a)
This embedded hardware feature allows the application to measure the V
battery
, and thus
BAT
voltage using the ADC VIN[14] input channel. As V
may be higher than V
BAT
DDA
outside the ADC input range, the VBAT pin is internally connected to a bridge divider by
three. As a consequence, the converted digital value is one third the V
voltage.
BAT
3.19
Digital-to-analog converter (DAC)
The 1-channel 12-bit buffered DAC converts a digital value into an analog voltage available
on the channel output. The architecture of each channel is based on an integrated resistor
string and an inverting amplifier. The digital circuitry is common for both channels.
DAC main features:
•
•
•
•
•
•
•
•
•
•
•
1 DAC output channel
8-bit or 12-bit output mode
buffer offset calibration (factory and user trimming)
left or right data alignment in 12-bit mode
synchronized update capability
noise-wave generation
triangular-wave generation
independent or simultaneous conversion for DAC channels
DMA capability for either DAC channel
triggering with timer events, synchronized with DMA
triggering with external events
Sample-and-hold low-power mode, with internal or external capacitor
3.20
Voltage reference buffer (VREFBUF)
The devices embed a voltage reference buffer that can be used as voltage reference for
ADC, and also as voltage reference for external components through the VREF+ pin.
VREFBUF supports two voltages: 2.048 V and 2.5 V.
An external voltage reference can be provided through the VREF+ pin when VREFBUF
is off.
a. VDD on STM32WLE5/E4UxYx devices.
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3.21
Comparator (COMP)
The devices embed two rail-to-rail comparators with programmable reference voltage
(internal or external), hysteresis and speed (low speed for low-power) and with selectable
output polarity.
The reference voltage can be one of the following:
•
•
external I/O
internal reference voltage or submultiple (1/4, 1/2, 3/4)
All comparators can wake up from Stop mode, generate interrupts and breaks for the timers,
and can be also combined into a window comparator.
3.22
3.23
True random number generator (RNG)
The devices embed a true RNG that delivers 32-bit random numbers generated by an
integrated analog circuitry.
Advanced encryption standard hardware accelerator (AES)
The AES encrypts or decrypts data, using an algorithm and implementation fully compliant
with the advanced encryption standard (AES) defined in FIPS (federal information
processing standards) publication 197.
Multiple chaining modes are supported (ECB, CBC, CTR, GCM, GMAC, CCM), for key
sizes of 128 or 256 bits. The AES supports DMA single transfers for incoming and outgoing
data (two DMA channels required).
3.24
3.25
Public key accelerator (PKA)
The PKA is used to compute cryptographic public key primitives, specifically those related to
RSA (Rivest, Shamir and Adleman), Diffie-Hellmann or ECC (elliptic curve cryptography)
over GF(p) (Galois fields). These operations are executed in the Montgomery domain.
Timer and watchdog
The devices include one advanced 16-bit timer, one general-purpose 32-bit timer, two 16-bit
basic timers, three low-power timers, two watchdog timers and a SysTick timer.
The table below compares the features of the advanced control, general purpose and basic
timers.
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Table 14. Timer features
Counter
resolution
(bits)
DMA
request
generation
Capture/
compare
channels
Timer
Timer type
Counter
type
Prescaler
factor
Complementary
outputs
name
Advanced
TIM1
Up, down
and
up/down
16
32
3
control
4
2
1
TIM2
NA
General
purpose
Any integer
between
1 and 65536
TIM16
Yes
TIM17
16
Up
1
LPTIM1
Low power LPTIM2
LPTIM3
3.25.1
Advanced-control timer (TIM1)
The advanced-control timer TIM1 can be seen as a three-phase PWM multiplexed on six
channels. Each channel has complementary PWM outputs with programmable inserted
dead-times. Each channel can also be seen as complete general-purpose timers.
The four independent channels can be used for:
•
•
•
input capture
output compare
PWM generation (edge or center-aligned modes) with full modulation capability
(0 - 100 %)
•
one-pulse mode output
In debug mode, the TIM1 counter can be frozen and the PWM outputs disabled to turn off
any power switches driven by these outputs.
Many features are shared with those of the general-purpose timers (described in the next
section) using the same architecture. TIM1 can then work together with TIM2 via the
peripheral interconnect matrix, for synchronization or event chaining.
3.25.2
General-purpose timers (TIM2, TIM16, TIM17)
Each general-purpose timer can be used to generate PWM outputs, or act as a simple time
base.
TIM2 main features:
•
•
full-featured general-purpose timer
four independent channels for input capture/output compare, PWM or one-pulse mode
output
•
•
counter that can be frozen in debug mode
independent DMA request generation, support of quadrature encoders
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TIM16 and TIM17 main features:
•
•
•
•
general-purpose timers with mid-range features
16-bit auto-reload upcounters and 16-bit prescalers
1 channel and 1 complementary channel
channels that can all be used for input capture/output compare, PWM or one-pulse
mode output
•
•
counter that can be frozen in debug mode
independent DMA request generation
3.25.3
Low-power timers (LPTIM1, LPTIM2 and LPTIM3)
These low-power timers have an independent clock and run in Stop mode if they are
clocked by LSE, LSI, or by an external clock. They are able to wake up the system from
Stop mode.
LPTIM1 is active in Stop 0, Stop 1 and Stop 2 modes.
LPTIM2 and LPTIM3 are active in Stop 0 and Stop 1 modes.
LPTIM1/2/3 main features:
•
•
•
•
•
•
•
•
16-bit up counter with 16-bit autoreload register
16-bit compare register
configurable output: pulse, PWM
continuous/one-shot mode
selectable software/hardware input trigger
selectable clock source
internal clock sources: LSE, either LSI, HSI16 or APB clock
external clock source over LPTIM input (works even with no internal clock source
running, used by pulse counter application)
•
•
programmable digital glitch filter
encoder mode (LPTIM1 only)
3.25.4
3.25.5
Independent watchdog (IWDG)
The independent watchdog is based on a 12-bit downcounter and a 8-bit prescaler. The
IWDG is clocked from an independent 32 kHz internal RC (LSI). As the IWDG operates
independently from the main clock, it can operate in Stop and Standby modes.
The IWDG can be used either as a watchdog to reset the device when a problem occurs, or
as a free running timer for application timeout management. The IWDG is hardware or
software configurable through the option bytes. The counter can be frozen in debug mode.
System window watchdog (WWDG)
The window watchdog is based on a 7-bit downcounter that can be set as free running. The
WWDG can be used as a watchdog to reset the device when a problem occurs.
The WWDG is clocked from the main clock and has an early warning interrupt capability.
The counter can be frozen in debug mode.
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3.25.6
SysTick timer
This timer is dedicated to real-time operating systems, but can also be used as a standard
down counter.
SysTick timer main features:
•
•
•
•
24-bit down counter
autoreload capability
maskable system interrupt generation when the counter reaches 0
programmable clock source
3.26
Real-time clock (RTC), tamper and backup registers
The RTC is an independent BCD timer/counter. The RTC provides a time-of-day
clock/calendar with programmable alarm interrupts.
As long as the supply voltage remains in the operating range, the RTC never stops,
regardless of the device status (Run mode, low-power mode or under reset).
The RTC provides an automatic wakeup to manage all low-power modes.
The RTC is functional in VBAT mode.
Twenty 32-bit backup registers are retained in all low-power modes and also in VBAT mode.
These registers can be used to store sensitive data as their content is protected by a tamper
detection circuit.
Three tamper pins and four internal tampers are available for anti-tamper detection. The
external tamper pins can be configured for edge or level detection with or without filtering.
3.27
Inter-integrated circuit interface (I2C)
The device embeds three I2Cs, with features implementation listed in the he table below.
2
The I C bus interface handles communications between the microcontroller and the serial
2
2
I C bus. It controls all I C bus-specific sequencing, protocol, arbitration and timing.
The I2C peripheral supports:
2
•
I C bus specification and user manual rev. 5 compatibility:
–
–
–
–
–
–
–
slave and master modes, multimaster capability
Standard-mode (Sm), with a bitrate up to 100 Kbit/s
Fast-mode (Fm), with a bitrate up to 400 Kbit/s
Fast-mode plus (Fm+), with a bitrate up to 1 Mbit/s and 20 mA output drive I/Os
7-bit and 10-bit addressing mode, multiple 7-bit slave addresses
programmable setup and hold times
clock stretching (optional)
•
SMBus (system management bus) specification rev 2.0 compatibility:
–
hardware PEC (packet error checking) generation and verification with ACK
control
–
–
address resolution protocol (ARP) support
SMBus alert
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STM32WLE5/E4xx
•
•
PMBus (power system management protocol) specification rev 1.1 compatibility
2
independent clock: a choice of independent clock sources allowing the I C
communication speed to be independent from the PCLK reprogramming (see Figure 8)
•
•
•
wakeup from Stop mode on address match
programmable analog and digital noise filters
1-byte buffer with DMA capability
Table 15. I2C implementation
I2C features(1)
I2C1(2)
I2C2(2)
I2C3
7-bit addressing mode
10-bit addressing mode
X
X
X
X
X
X
Standard-mode (up to 100 Kbit/s)
Fast-mode (up to 400 Kbit/s)
Fast-mode Plus with 20mA output drive I/Os (up to 1 Mbit/s)
Independent clock
X
X
X
X
X
X
X
X
X
X
X
X
Wakeup from Stop mode
X(3)
X(3)
X(4)
SMBus/PMBus
X
X
X
1. X = supported.
2. The register content is lost in Stop 2 mode.
3. Wakeup supported from Stop 0 and Stop 1 modes.
4. Wakeup supported from Stop 0, Stop 1 and Stop 2 modes.
3.28
Universal synchronous/asynchronous receiver transmitter
(USART/UART)
The devices embed two universal synchronous receiver transmitters, USART1 and
USART2 (see Table 16 for the implementation details).
Each USART provides asynchronous communication, IrDA SIR ENDEC support,
multiprocessor communication mode, single-wire half-duplex communication mode. Each
USART has LIN Master/Slave capability and provides hardware management of the CTS
and RTS signals, and RS485 driver enable.
The USART is able to communicate at speeds of up to 4 Mbit/s, and also provides
Smart Card mode (ISO 7816 compliant) and SPI-like communication capability.
The USART supports synchronous operation (SPI mode), and can be used as an SPI
master.
The USART has a clock domain independent from the CPU clock, allowing the USART to
wake up the MCU from Stop mode, using baudrates up to 200 kbaud.
The wakeup events from Stop mode are programmable and can be one of the following:
•
•
•
start bit detection
any received data frame
a specific programmed data frame
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The USART interface can be served by the DMA controller.
3.29
Low-power universal asynchronous receiver transmitter
(LPUART)
The devices embed one low-power UART (LPUART1) that enables asynchronous serial
communication with minimum power consumption. The LPUART supports half-duplex
single-wire communication and modem operations (CTS/RTS), allowing multiprocessor
communication.
The LPUART has a clock domain independent from the CPU clock, and can wake up the
system from Stop mode using baudrates up to 220 Kbaud. The wakeup events from Stop
mode are programmable and can be one of the following:
•
•
•
start bit detection
any received data frame
a specific programmed data frame
Only a 32.768 kHz clock (LSE) is needed to allow LPUART communication up to
9600 baud. Therefore, even in Stop mode, the LPUART can wait for an incoming frame
while having an extremely low-energy consumption. Higher speed clock can be used to
reach higher baudrates.
The LPUART interface can be served by the DMA controller.
Table 16. USART/LPUART features
USART modes/features(1)
USART1/2
LPUART1
Hardware flow control for modem
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
-
Continuous communication using DMA
Multiprocessor communication
Synchronous mode (Master/Slave)
Smartcard mode
-
Single-wire half-duplex communication
IrDA SIR ENDEC block
LIN mode
X
-
-
Dual clock domain and wakeup from low-power mode
Receiver timeout interrupt
Modbus communication
Auto baud rate detection
Driver enable
X
-
-
-
X
USART data length
7, 8 and 9 bits
Tx/Rx FIFO
X
X
Tx/Rx FIFO size
8
1. X = supported.
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3.30
Serial peripheral interface (SPI)/integrated-interchip sound
interface (I2S)
The SPI/I2S interface can be used to communicate with external devices using the SPI
protocol or the I S audio protocol. SPI or I2S mode is selectable by software. SPI Motorola
2
®
mode is selected by default after a device reset.
The SPI protocol supports half-duplex, full-duplex and simplex synchronous, serial
communication with external devices. The SPI interface can be configured as master and, in
this case, it provides the communication clock (SCK) to the external slave device. The SPI
interface can also operate in multimaster configuration.
2
The I S protocol is also a synchronous serial communication interface. It can operate in
slave or master mode with half-duplex communication. It can address four different audio
2
standards including the Philips I S standard, the MSB- and LSB-justified standards and the
PCM standard.
(1)
Table 17. SPI and SPI/I2S implementation
Features
SPI1
SPI2S2
SUBGHZSPI
Enhanced NSSP and TI modes
Hardware CRC calculation
I2S support
Yes
Yes
Yes
No
No
No
Yes
Data size configurable (bits)
Rx/Tx FIFO size (bits)
from 4 to 16
32
Wakeup capability from LPSleep
Yes
1. The SPI1 and SPI2S2 instances are general purpose type while the SUBGHZSPI instance is dedicated for
Sub-GHz radio control exclusively. Radio is controlled internally through SUBGHZSPI and, for debug
purpose only, from the external.
3.31
Development support
Serial-wire JTAG debug port (SWJ-DP)
The Arm SWJ-DP interface is embedded, and is a combined JTAG and serial-wire debug
port, that enables either a serial-wire debug or a JTAG probe to be connected to the target.
The debug is performed using only two pins instead of the five required by the JTAG (JTAG
pins can then be reused as GPIOs with alternate function). The JTAG TMS and TCK pins
are shared with SWDIO and SWCLK, respectively, and a specific sequence on the TMS pin
is used to switch between JTAG-DP and SW-DP.
48/145
DS13105 Rev 8
STM32WLE5/E4xx
Pinouts, pin description and alternate functions
4
Pinouts, pin description and alternate functions
Figure 9. UFQFPN48 pinout
1
36
35
34
33
32
31
30
29
28
27
26
25
PB3
PB4
PB5
PB6
PB7
PB8
PA0
PA1
PA2
PA3
VDD
PA4
PA13
2
PA12
3
PA11
4
PA10
5
PB12
6
PB2
UFQFPN48
7
PB0-VDD_TCXO
VDDRF1V55
VDDRF
OSC_OUT
OSC_IN
VDDPA
8
9
10
11
12
MSv48144V4
1. The above figure shows the package top view.
2. The exposed pad must be connected to the ground plain.
DS13105 Rev 8
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60
Pinouts, pin description and alternate functions
STM32WLE5/E4xx
Figure 10. UFBGA73 pinout
1
2
3
4
5
6
7
8
9
VSSSMPS
VDDSMPS
PA14
VDDA
VDD
VBAT
PA12
A
B
C
D
E
F
PC14-
VLXSMPS
PB3
VFBSMPS
PB4
PA15
PB7
PB8
PB15
PB9
VREF+
VSS
PC13
PB13
PA13
PA10
PB2
PA11
OSC32_IN
PC15-
OSC32
_OUT
PB14
PA0
PB5
PC2
PC3
VSS
VDD
PB6
PC1
VDD
PC0
VSS
PC4
PC5
PA6
PA9
PB12
PB1
VDDRF
PB0-
VDD_TCXO
VDDRF
1V55
NRST
OSC_OUT
PC6
PA2
PA5
PA1
PA7
PA8
PB11
PB10
VSS
VDD
VSSRF
VSSRF
RFI_P
VSSRF
RFI_N
VSSRF
VDDPA
RFO_LP
OSC_IN
VR_PA
G
H
J
PA3
PA4
PH3-
BOOT0
RFO_HP
MSv48145V4
1. The above figure shows the package top view.
Table 18. Legend/abbreviations used in the pinout table
Abbreviation Definition
Name
Unless otherwise specified in brackets below the pin name, the pin function during and
after reset is the same as the actual pin name
Pin name
S
I
Supply pin
Input only pin
Input / output pin
Output only pin
5 V tolerant I/O
Radio RF pin
3 V tolerant I/O
Pin type
I/O
O
FT
RF
TT
I/O structure
Option for FT I/Os
_f
I/O, Fm+ capable
_a
I/O, with Analog switch function supplied by VDDA
50/145
DS13105 Rev 8
STM32WLE5/E4xx
Pinouts, pin description and alternate functions
Definition
Table 18. Legend/abbreviations used in the pinout table (continued)
Name
Abbreviation
Unless otherwise specified by a note, all I/Os are set as analog inputs during and after
reset.
Notes
Alternate
functions
Functions selected through GPIOx_AFR registers
Pin
functions
Additional
functions
Functions directly selected/enabled through peripheral registers
Table 19. STM32WLE5/E4xx pin definition
Pin name
Pin number
(function after
reset)
Alternate functions
Additional functions
-
E10
-
VSS
PB3
S
-
-
-
-
-
JTDO/TRACESWO,
TIM2_CH2, SPI1_SCK,
RF_IRQ0, USART1_RTS,
DEBUG_RF_DTB1,
COMP1_INM,
COMP2_INM,
ADC_IN2,
1
D11 C1
I/O FT_a
I/O FT_fa
I/O FT_a
TAMP_IN3/WKUP3
CM4_EVENTOUT
NJTRST, I2C3_SDA,
SPI1_MISO, USART1_CTS,
DEBUG_RF_LDORDY,
TIM17_BKIN,
COMP1_INP,
COMP2_INP,
ADC_IN3
2
3
D9
C2
D2
PB4
PB5
-
-
CM4_EVENTOUT
LPTIM1_IN1, I2C1_SMBA,
SPI1_MOSI, RF_IRQ1,
USART1_CK, COMP2_OUT,
TIM16_BKIN,
-
-
CM4_EVENTOUT
-
-
F7
E3
E2
VSS
VDD
S
S
-
-
-
-
-
-
-
-
F11
LPTIM1_ETR, I2C1_SCL,
USART1_TX, TIM16_CH1N,
CM4_EVENTOUT
4
5
6
-
-
-
E1
C3
D3
PB6
PB7
PB8
I/O FT_f
I/O FT_f
I/O FT_f
-
-
-
-
-
-
LPTIM1_IN2, TIM1_BKIN,
I2C1_SDA, USART1_RX,
TIM17_CH1N,
CM4_EVENTOUT
TIM1_CH2N, I2C1_SCL,
RF_IRQ2, TIM16_CH1,
CM4_EVENTOUT
DS13105 Rev 8
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60
Pinouts, pin description and alternate functions
STM32WLE5/E4xx
Additional functions
Table 19. STM32WLE5/E4xx pin definition (continued)
Pin number
Pin name
(function after
reset)
Alternate functions
TIM1_CH3N, I2C1_SDA,
SPI2_NSS/I2S2_WS,
IR_OUT, TIM17_CH1,
CM4_EVENTOUT
-
-
-
-
C4
PB9
PC0
I/O FT_f
I/O FT_f
I/O FT_f
-
-
-
-
LPTIM1_IN1, I2C3_SCL,
LPUART1_RX, LPTIM2_IN1,
CM4_EVENTOUT
F2
LPTIM1_OUT,
SPI2_MOSI/I2S2_SD,
I2C3_SDA, LPUART1_TX,
CM4_EVENTOUT
-
-
-
-
-
-
F1
D4
D5
PC1
PC2
PC3
-
-
-
-
-
-
LPTIM1_IN2, SPI2_MISO,
CM4_EVENTOUT
I/O
I/O
FT
FT
LPTIM1_ETR,
SPI2_MOSI/I2S2_SD,
LPTIM2_ETR,
CM4_EVENTOUT
-
-
-
-
-
-
F3
E4
G2
PC4
PC5
PC6
I/O
I/O
I/O
FT
FT
FT
-
-
-
CM4_EVENTOUT
CM4_EVENTOUT
-
-
-
I2S2_MCK, CM4_EVENTOUT
TIM2_CH1, I2C3_SMBA,
I2S_CKIN, USART2_CTS,
COMP1_OUT,
DEBUG_PWR_REGLP1S,
TIM2_ETR, CM4_EVENTOUT
7
8
9
H11 D6
PA0
PA1
PA2
I/O FT_a
-
-
-
TAMP_IN2/WKUP1
TIM2_CH2, LPTIM3_OUT,
I2C1_SMBA, SPI1_SCK,
USART2_RTS,
LPUART1_RTS,
DEBUG_PWR_REGLP2S,
CM4_EVENTOUT
G10 G3
I/O FT_a
-
LSCO, TIM2_CH3,
USART2_TX, LPUART1_TX,
COMP2_OUT,
DEBUG_PWR_LDORDY,
CM4_EVENTOUT
F9
H2
I/O FT_a
I/O FT_a
LSCO
TIM2_CH4, I2S2_MCK,
USART2_RX, LPUART1_RX,
CM4_EVENTOUT
10
-
C8
E6
H1
G5
PA3
-
-
-
-
VSS
S
-
-
52/145
DS13105 Rev 8
STM32WLE5/E4xx
Pin number
Pinouts, pin description and alternate functions
Table 19. STM32WLE5/E4xx pin definition (continued)
Pin name
(function after
reset)
Alternate functions
Additional functions
11
12
K11
J10
H5
J1
VDD
PA4
S
-
-
-
-
-
-
RTC_OUT2, LPTIM1_OUT,
SPI1_NSS, USART2_CK,
DEBUG_SUBGHZSPI_
NSSOUT, LPTIM2_OUT,
CM4_EVENTOUT
I/O
FT
TIM2_CH1, TIM2_ETR,
SPI2_MISO, SPI1_SCK,
DEBUG_SUBGHZSPI_
SCKOUT, LPTIM2_ETR,
CM4_EVENTOUT
13
14
H9
G8
J2
PA5
PA6
I/O
I/O
FT
FT
-
-
-
-
TIM1_BKIN, I2C2_SMBA,
SPI1_MISO, LPUART1_CTS,
DEBUG_SUBGHZSPI_
MISOOUT, TIM16_CH1,
CM4_EVENTOUT
F4
TIM1_CH1N, I2C3_SCL,
SPI1_MOSI, COMP2_OUT,
DEBUG_SUBGHZSPI_
MOSIOUT, TIM17_CH1,
CM4_EVENTOUT
15
16
E8
H3
J3
PA7
PA8
I/O FT_fa
I/O FT_a
-
-
-
-
MCO, TIM1_CH1,
SPI2_SCK/I2S2_CK,
USART1_CK, LPTIM2_OUT,
CM4_EVENTOUT
L10
TIM1_CH2,
SPI2_NSS/I2S2_WS,
I2C1_SCL,
SPI2_SCK/I2S2_CK,
USART1_TX,
17
K9
E5
PA9
I/O FT_fa
-
-
CM4_EVENTOUT
TIM2_CH3, I2C3_SCL,
SPI2_SCK/I2S2_CK,
LPUART1_RX, COMP1_OUT,
CM4_EVENTOUT
-
-
-
-
H4
G4
PB10
PB11
I/O FT_f
I/O FT_f
-
-
-
-
TIM2_CH4, I2C3_SDA,
LPUART1_TX, COMP2_OUT,
CM4_EVENTOUT
18
19
-
J8
H7
L8
F5
J5
-
NRST
PH3-BOOT0
VDD
I/O
I/O
S
FT
FT
-
-
-
-
-
-
CM4_EVENTOUT
-
BOOT0
-
DS13105 Rev 8
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60
Pinouts, pin description and alternate functions
STM32WLE5/E4xx
Additional functions
Table 19. STM32WLE5/E4xx pin definition (continued)
Pin number
Pin name
(function after
reset)
Alternate functions
-
-
K7
-
VSS
VSSRF
VSSRF
RFI_P
S
S
S
I
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
J6
H5
L6
K5
G4
J4
L4
-
H6
G6
J6
H7
G7
-
-
-
-
20
21
-
RF
RFI_N
I
RF
VSSRF
VSSRF
RFO_LP
VSSRF
RFO_HP
VSSRF
VR_PA
VDDPA
VSSRF
OSC_IN
OSC_OUT
VSSRF
VDDRF
VDDRF1V55
VSS
S
S
O
S
O
S
S
S
S
I
-
-
-
22
-
J8
G8
J9
-
RF
-
23
-
K3
H3
L2
H1
K1
G2
F1
F3
E2
D1
F5
-
RF
-
24
25
-
H9
H8
-
-
-
-
26
27
-
G9
F8
-
RF
O
S
S
S
S
S
RF
-
-
-
-
-
28
29
-
E8
F7
D9
E9
-
VDD
COMP1_OUT,
CM4_EVENTOUT
30
-
B1
-
F6 PB0-VDD_TCXO I/O
TT
-
-
-
LPUART1_RTS_DE,
LPTIM2_IN1,
CM4_EVENTOUT
COMP2_INP,
ADC_IN5
E7
D8
PB1
PB2
I/O FT_a
I/O FT_a
LPTIM1_OUT, I2C3_SMBA,
SPI1_NSS,
DEBUG_RF_SMPSRDY,
CM4_EVENTOUT
COMP1_INP,
COMP2_INM,
ADC_IN4
31
32
-
-
-
-
TIM1_BKIN, I2C3_SMBA,
SPI2_NSS/I2S2_WS,
LPUART1_RTS,
E6
PB12
I/O
FT
-
CM4_EVENTOUT
54/145
DS13105 Rev 8
STM32WLE5/E4xx
Pin number
Pinouts, pin description and alternate functions
Table 19. STM32WLE5/E4xx pin definition (continued)
Pin name
(function after
reset)
Alternate functions
Additional functions
TIM1_CH1N, I2C3_SCL,
SPI2_SCK/I2S2_CK,
LPUART1_CTS,
-
-
-
-
D7
C6
PB13
PB14
I/O FT_fa
I/O FT_fa
-
-
ADC_IN0
ADC_IN1
CM4_EVENTOUT
TIM1_CH2N, I2S2_MCK,
I2C3_SDA, SPI2_MISO,
CM4_EVENTOUT
RTC_REFIN, TIM1_CH3,
I2C1_SDA,
SPI2_MOSI/I2S2_SD,
USART1_RX,
DEBUG_RF_HSE32RDY,
TIM17_BKIN,
COMP1_INM,
COMP2_INM,
DAC_OUT1,
ADC_IN6
33
34
D3
E4
C8
B9
PA10
PA11
I/O FT_fa
-
-
CM4_EVENTOUT
TIM1_CH4, TIM1_BKIN2,
LPTIM3_ETR, I2C2_SDA,
SPI1_MISO, USART1_CTS,
DEBUG_RF_NRESET,
CM4_EVENTOUT
COMP1_INM,
COMP2_INM,
ADC_IN7
I/O FT_fa
TIM1_ETR, LPTIM3_IN1,
I2C2_SCL, SPI1_MOSI,
RF_BUSY, USART1_RTS,
CM4_EVENTOUT
35
36
D5
D7
A9
B8
PA12
PA13
I/O FT_fa
I/O FT_a
-
-
ADC_IN8
ADC_IN9
JTMS-SWDIO, I2C2_SMBA,
IR_OUT, CM4_EVENTOUT
-
-
C2
A2
-
B7
A7
A8
VSS
VDD
VBAT
S
S
S
-
-
-
-
-
-
-
-
-
-
-
-
37
TAMP_IN1/
RTC_OUT1/RTC_TS/
WKUP2
38
-
C7
PC13
I/O
FT
-
CM4_EVENTOUT
39
40
B3
A4
B6 PC14-OSC32_IN I/O
PC15-
FT
FT
-
-
CM4_EVENTOUT
CM4_EVENTOUT
OSC32_IN
C5
I/O
OSC32_OUT
OSC32_OUT
VREF+
VDDA
-
41
-
-
B5
A5
-
S
S
S
-
-
-
-
-
-
-
-
-
-
-
-
B5
C4
VSS
DS13105 Rev 8
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60
Pinouts, pin description and alternate functions
STM32WLE5/E4xx
Table 19. STM32WLE5/E4xx pin definition (continued)
Pin number
Pin name
(function after
reset)
Alternate functions
Additional functions
JTCK-SWCLK, LPTIM1_OUT,
I2C1_SMBA,
42
C6
A8
-
A4
PA14
PA15
PB15
I/O FT_a
I/O FT_fa
I/O FT_f
-
-
ADC_IN10
CM4_EVENTOUT
JTDI, TIM2_CH1, TIM2_ETR,
I2C2_SDA, SPI1_NSS,
CM4_EVENTOUT
COMP1_INM,
COMP2_INP,
ADC_IN11
43
-
B3
B4
TIM1_CH3N, I2C2_SCL,
SPI2_MOSI/I2S2_SD,
CM4_EVENTOUT
-
44
-
A6
B7
-
-
VDD
VSS
S
S
S
S
S
S
S
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
49(1) G6
-
VSS
45
46
47
48
B9
B2
VFBSMPS
VDDSMPS
VLXSMPS
VSSSMPS
A10 A2
B11 B1
C10 A1
1. Pin 49 is an exposed pad that must be connected to VSS
.
56/145
DS13105 Rev 8
Table 20. Alternate functions
AF0
AF1
AF2
AF3
AF4
AF5
AF6
AF7
AF8
AF9 AF10 AF11
AF12
AF13
AF14
AF15
TIM2/
TIM16/
TIM17/
LPTIM2
Port
TIM1/
TIM2/
LPTIM1
SPI2S2/
TIM1/
LPTIM3
I2C1/
I2C2/
I2C3
USART1
/
USART2
COMP1/
COMP2/
TIM1
SYS_
AF
TIM1/
TIM2
SPI1/
SPI2S2
RF
LPUART1
-
-
-
DEBUG
EVENOUT
TIM2_
CH1
I2C3_
SMBA
I2S_
CKIN
USART2_
CTS
COMP1_ DEBUG_PWR
CM4_
EVENTOUT
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
TIM2_ETR
PA0
OUT
_REGLP1S
TIM2_
CH2
LPTIM3_
OUT
I2C1_
SMBA
SPI1_
SCK
USART2_ LPUART1_
RTS RTS
DEBUG_PWR
_REGLP2S
CM4_
EVENTOUT
-
LSCO
-
-
-
-
-
PA1
PA2
PA3
TIM2_
CH3
USART2_ LPUART1_
TX TX
COMP2_ DEBUG_PWR
CM4_
EVENTOUT
-
-
-
-
-
OUT
_LDORDY
TIM2_
CH4
I2S2_
MCK
USART2_ LPUART1_
CM4_
EVENTOUT
-
-
RX
RX
-
DEBUG_
SUBGHZSPI_
NSSOUT
RTC_
OUT2
LPTIM1
_OUT
SPI1_
NSS
USART2_
CK
LPTIM2_
OUT
CM4_
EVENTOUT
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
PA4
PA5
PA6
PA7
PA8
PA9
DEBUG_
SUBGHZSPI_
SCKOUT
TIM2_
CH1
TIM2_
ETR
SPI2_
MISO
SPI1_
SCK
LPTIM2_
ETR
CM4_
EVENTOUT
-
-
-
-
-
DEBUG_
SUBGHZSPI_
MISOOUT
TIM1_
BKIN
I2C2_
SMBA
SPI1_
MISO
LPUART1_
CTS
TIM1_
BKIN
TIM16_
CH1
CM4_
EVENTOUT
-
-
-
-
-
-
-
-
-
DEBUG_
SUBGHZSPI_
MOSIOUT
TIM1_
CH1N
I2C3_
SCL
SPI1_
MOSI
COMP2_
OUT
TIM17_
CH1
CM4_
EVENTOUT
-
MCO
-
-
-
-
SPI2_
SCK/
I2S2_CK
TIM1_
CH1
USART1_
CK
LPTIM2_
OUT
CM4_
EVENTOUT
-
-
-
-
-
-
SPI2_
NSS/
I2S2_WS
SPI2_
SCK/
I2S2_CK
TIM1_
CH2
I2C1_
SCL
USART1_
TX
CM4_
EVENTOUT
-
SPI2_
MOSI/
I2S2_SD
RTC_
REFIN
TIM1_
CH3
I2C1_
SDA
USART1_
RX
DEBUG_RF_
HSE32RDY
TIM17_
BKIN
CM4_
EVENTOUT
-
-
-
-
-
-
-
-
-
-
-
PA10
PA11
TIM1_
CH4
TIM1_
BKIN2
LPTIM3_
ETR
I2C2_
SDA
SPI1_
MISO
USART1_
CTS
TIM1_
BKIN2
DEBUG_RF_
NRESET
CM4_
EVENTOUT
-
-
Table 20. Alternate functions (continued)
AF0
AF1
AF2
AF3
AF4
AF5
AF6
AF7
AF8
AF9 AF10 AF11
AF12
AF13
AF14
AF15
TIM2/
TIM16/
TIM17/
LPTIM2
Port
TIM1/
TIM2/
LPTIM1
SPI2S2/
TIM1/
LPTIM3
I2C1/
I2C2/
I2C3
USART1
/
USART2
COMP1/
COMP2/
TIM1
SYS_
AF
TIM1/
TIM2
SPI1/
SPI2S2
RF
LPUART1
-
-
-
DEBUG
EVENOUT
TIM1_
ETR
LPTIM3_
IN1
I2C2_
SCL
SPI1_
MOSI
USART1_
RTS
CM4_
EVENTOUT
-
-
-
-
RF_BUSY
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
PA12
JTMS-
SWDIO
I2C2_
SMBA
CM4_
EVENTOUT
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
IR_OUT
PA13
PA14
PA15
PB0
JTCK- LPTIM1_
I2C1_
SMBA
CM4_
EVENTOUT
-
-
-
SWCLK
OUT
TIM2_
CH1
TIM2_
ETR
I2C2_
SDA
SPI1_
NSS
CM4_
EVENTOUT
JTDI
COMP1_
OUT
CM4_
EVENTOUT
-
-
-
-
-
-
-
-
-
-
-
-
LPUART1_
RTS_DE
LPTIM2_
IN1
CM4_
EVENTOUT
-
-
PB1
LPTIM1_
OUT
I2C3_
SMBA
SPI1_
NSS
DEBUG_RF_
SMPSRDY
CM4_
EVENTOUT
-
-
-
-
PB2
JTDO/
TRACE
SWO
TIM2_
CH2
SPI1_
SCK
USART1_
RTS
DEBUG_RF_
DTB1
CM4_
EVENTOUT
-
-
-
RF_IRQ0
-
-
-
-
-
PB3
I2C3_
SDA
SPI1_
MISO
USART1_
CTS
DEBUG_RF_
LDORDY
TIM17_
BKIN
CM4_
EVENTOUT
NJTRST
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
PB4
PB5
PB6
PB7
PB8
LPTIM1_
IN1
I2C1_
SMBA
SPI1_
MOSI
USART1_
CK
COMP2_
OUT
TIM16_
BKIN
CM4_
EVENTOUT
-
-
-
-
RF_IRQ1
-
-
-
-
LPTIM1_
ETR
I2C1_
SCL
USART1_
TX
TIM16_
CH1N
CM4_
EVENTOUT
-
-
-
-
-
-
-
LPTIM1_
IN2
TIM1_
BKIN
I2C1_
SDA
USART1_
RX
TIM17_
CH1N
CM4_
EVENTOUT
-
TIM1_
CH2N
I2C1_
SCL
TIM16_
CH1
CM4_
EVENTOUT
-
-
RF_IRQ2
-
-
SPI2_
NSS/
I2S2_WS
TIM1_
CH3N
I2C1_
SDA
TIM17_
CH1
CM4_
EVENTOUT
PB9
-
-
-
-
-
-
IR_OUT
-
-
-
-
-
-
-
-
-
SPI2_
SCK/
I2S2_CK
TIM2_
CH3
I2C3_
SCL
LPUART1_
RX
COMP1_
OUT
CM4_
EVENTOUT
-
-
-
PB10
Table 20. Alternate functions (continued)
AF0
AF1
AF2
AF3
AF4
AF5
AF6
AF7
AF8
AF9 AF10 AF11
AF12
AF13
AF14
AF15
TIM2/
TIM16/
TIM17/
LPTIM2
Port
TIM1/
TIM2/
LPTIM1
SPI2S2/
TIM1/
LPTIM3
I2C1/
I2C2/
I2C3
USART1
/
USART2
COMP1/
COMP2/
TIM1
SYS_
AF
TIM1/
TIM2
SPI1/
SPI2S2
RF
LPUART1
-
-
-
DEBUG
EVENOUT
TIM2_
CH4
I2C3_
SDA
LPUART1_
TX
COMP2_
OUT
CM4_
EVENTOUT
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
PB11
SPI2_
NSS/
I2S2_WS
TIM1_
BKIN
TIM1_
BKIN
I2C3_
SMBA
LPUART1_
RTS
CM4_
EVENTOUT
-
PB12
SPI2_
SCK/
I2S2_CK
TIM1_
CH1N
I2C3_
SCL
LPUART1_
CTS
CM4_
EVENTOUT
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
PB13
PB14
PB15
TIM1_
CH2N
I2C3_
SDA
SPI2_
MISO
CM4_
EVENTOUT
I2S2_MCK
-
-
-
SPI2_
MOSI/
I2S2_SD
TIM1_
CH3N
I2C2_
SCL
CM4_
EVENTOUT
Table 20. Alternate functions (continued)
AF0
AF1
AF2
AF3
AF4
AF5
AF6
AF7
AF8
AF9 AF10 AF11
AF12
AF13
AF14
AF15
TIM2/
TIM16/
TIM17/
LPTIM2
Port
TIM1/
TIM2/
LPTIM1
SPI2S2/
TIM1/
LPTIM3
I2C1/
I2C2/
I2C3
USART1
/
USART2
COMP1/
COMP2/
TIM1
SYS_
AF
TIM1/
TIM2
SPI1/
SPI2S2
RF
LPUART1
-
-
-
DEBUG
EVENOUT
LPTIM1_
IN1
I2C3_
SCL
LPUART1_
RX
LPTIM2_
IN1
CM4_
EVENTOUT
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
PC0
SPI2_
MOSI/
I2S2_SD
LPTIM1_
OUT
I2C3_
SDA
LPUART1_
TX
CM4_
EVENTOUT
-
-
PC1
PC2
PC3
LPTIM1_
IN2
SPI2_
MISO
CM4_
EVENTOUT
-
-
-
-
-
-
SPI2_
MOSI/
I2S2_SD
LPTIM1_
ETR
LPTIM2_
ETR
CM4_
EVENTOUT
CM4_
EVENTOUT
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
PC4
PC5
CM4_
EVENTOUT
I2S2_
MCK
CM4_
EVENTOUT
PC6
CM4_
EVENTOUT
-
-
-
PC13
PC14
PC15
CM4_
EVENTOUT
CM4_
EVENTOUT
CM4_
EVENTOUT
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
PH3
STM32WLE5/E4xx
Electrical characteristics
5
Electrical characteristics
5.1
Parameter conditions
Unless otherwise specified, all voltages are referenced to V and, for parameter values
SS
based on characterization results, measurements are performed on the UFQFPN48
package.
5.1.1
Minimum and maximum values
Unless otherwise specified, the minimum and maximum values are guaranteed in the worst
conditions of ambient temperature, supply voltage and frequencies, by tests in production
on 100 % of the devices, with an ambient temperature at T = 25 °C and T = T max (given
A
A
A
by the selected temperature range).
Data based on characterization results, design simulation and/or technology characteristics
are indicated in the table footnotes and are not tested in production. Based on
characterization, the minimum and maximum values refer to sample tests and represent the
mean value plus or minus three times the standard deviation (mean ±3σ).
5.1.2
5.1.3
Typical values
Unless otherwise specified, typical data are based on T = 25 °C, V = V
Typical values are given only as design guidelines and are not tested.
= V
= 3 V.
BAT
A
DD
DDA
Typical ADC accuracy values are determined by characterization of a batch of samples from
a standard diffusion lot over the full temperature range, where 95 % of the devices have an
error less than or equal to the value indicated (mean ± 2σ).
Typical curves
Unless otherwise specified, all typical curves are given only as design guidelines and are
not tested.
5.1.4
5.1.5
Loading capacitor
The loading conditions used for pin parameter measurement are shown in Figure 11.
Pin input voltage
The input voltage measurement on a pin of the device is described in Figure 12.
Figure 11. Pin loading conditions
Figure 12. Pin input voltage
MCU pin
MCU pin
C = 50 pF
VIN
MSv68046V1
MSv68045V1
DS13105 Rev 8
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133
Electrical characteristics
STM32WLE5/E4xx
5.1.6
Power supply scheme
Figure 13. Power supply scheme
VBAT
VBAT
1.55 to 3.6 V
Backup circuitry
(LSE, RTC and
backup registers)
Power switch
VDD
VCORE
n x VDD
LPR
Kernel logic
OUT
I/O
logic
(CPU, digital
GPIOs
n x 100 nF + 1 x 4.7 μF
IN
and memories
n x VSS
VDDA
VDDA
MR
VREF
ADC
VREF+
DAC
10 nF + 1 μF
COMPs
VREFBUF
100 nF 1 μF
VREF-
VSS
VDDRF
VDD
VDDSMPS
VLXSMPS
LDO/SMPS
4.7 μF
Sub-GHz radio
15 μH
VFBSMPS
VDDRF1V5
470 nF
RFLDO
REG PA
VSSSMPS
VDDPA (= VDDRF1V5 or VDDSMPS)
Exposed pad
To all modules (VSS/VSSRF)
MSv64325V5
Caution:
Each power supply pair (such as V /V
V
/V ) must be decoupled with filtering
DD SS or DDA SS
ceramic capacitors as shown in the above figure. These capacitors must be placed as close
as possible to (or below) the appropriate pins on the underside of the PCB to ensure the
good functionality of the device.
Note:
For the UFQFPN48 and WLCSP59 package, VREF+ is internally connected to VDDA.
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DS13105 Rev 8
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Electrical characteristics
5.1.7
Current consumption measurement
Figure 14. Current consumption measurement scheme
IDDSMPS
VDDSMPS
VDDSMPS
IDDRF
VDDRF
VDDRF
IDDVBAT
VBAT
VDD
VBAT
VDD
IDD
IDDA
VDDA
VDDA
MSv64326V2
5.2
Absolute maximum ratings
Stresses above the absolute maximum ratings listed in the tables below, may cause
permanent damage to the device. These are stress ratings only and functional operation of
the device at these conditions is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.
Device mission profile (application conditions) is compliant with JEDEC JESD47
Qualification Standard, extended mission profiles are available on demand.
(1)
Table 21. Voltage characteristics
Symbol
Ratings
Min
Max
Unit
External main supply voltage
V
DDX - VSS (including VDD, VDDA, VDDRF
,
–0.3
3.9
V
DDSMPS, VBAT, VREF+
)
Input voltage on FT_xx pins
Input voltage on TT pins
min (VDD, VDDA, VDDRF, VDDSMPS) + 3.9(3)(4)
V
(2)
V
SS - 0.3
3.9
3.9
VIN
Input voltage on any other pin
Variations between different VDDX
power pins of the same domain
|∆VDDx
|VSSx-VSS
VREF+ - VDDA
|
-
-
-
50
50
mV
V
Variations between all the different
ground pins(5)
|
Allowed voltage difference for
0.4
V
REF+ > VDDA
1. All main power (VDD, VDDRF, VDDA, VBAT) and ground (VSS) pins must always be connected to the external power
supply, in the permitted range.
DS13105 Rev 8
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133
Electrical characteristics
STM32WLE5/E4xx
2. VIN maximum must always be respected. Refer to the next table for the maximum allowed injected current values.
3. This formula must be applied only on the power supplies related to the I/O structure described in Table 19:
STM32WLE5/E4xx pin definition.
4. To sustain a voltage higher than 4 V, the internal pull-up/pull-down resistors must be disabled.
5. Include VREF- pin.
Table 22. Current characteristics
Symbol
Ratings
Max
Unit
∑IVDD
∑IVSS
Total current into sum of all VDD power lines (source)(1)
Total current out of sum of all VSS ground lines (sink)(1)
Maximum current into each VDD power pin (source)(1)
Maximum current out of each VSS ground pin (sink)(1)
Output current sunk by any I/O and control pin, except FT_f
Output current sunk by any FT_f pin
130
130
130
100
20
IVDD(PIN)
IVSS(PIN)
IIO(PIN)
20
mA
Output current sourced by any I/O and control pin
Total output current sunk by sum of all I/Os and control pins(2)
Total output current sourced by sum of all I/Os and control pins(2)
Injected current on FT_xx, TT and RST pins, except PB0
Injected current on PB0
20
100
100
–5 / +0(4)
-5/0
25
∑IIO(PIN)
(3)
IINJ(PIN)
∑|IINJ(PIN)
|
Total injected current (sum of all I/Os and control pins)(5)
1. All main power (VDD, VDDRF, VDDA, VBAT) and ground (VSS) pins must always be connected to the external power
supplies, in the permitted range.
2. This current consumption must be correctly distributed over all I/Os and control pins.
3. Positive injection (when VIN > VDD) is not possible on these I/Os and does not occur for input voltages lower than the
specified maximum value.
4. A negative injection is induced by VIN < VSS. IINJ(PIN) must never be exceeded. Refer also to the previous table for the
maximum allowed input voltage values.
5. When several inputs are submitted to a current injection, the maximum ∑|IINJ(PIN)| is the absolute sum of the negative
injected currents (instantaneous values).
Table 23. Thermal characteristics
Symbol
Ratings
Storage temperature range
Maximum junction temperature
Value
Unit
°C
TSTG
TJ
-65 to +150
125
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DS13105 Rev 8
STM32WLE5/E4xx
Electrical characteristics
5.3
Operating conditions
5.3.1
Main performances
Table 24. Main performances at V = 3 V
DD
Parameter
Test conditions
Typ
Unit
VBAT (VBAT = 3V, VDD = 0 V)
0.005
0.031
0.360
1
Shutdown
Standby (32-Kbyte RAM retention)
Stop 2, RTC enabled
ICORE Core current consumption
µA
Sleep (16 MHz)
770
220
3450
4.82
21
LPRun (2 MHz)
Run, SMPS ON (48 MHz)
LoRa 125 kHz, SMPS ON
434 to 490 MHz, 14 dBm, 3.3 V
868 to 915 MHz, 14 dBm, 3.3 V
434 to 490 MHz, 22 dBm, 3.3 V
868 to 915 MHz, 22 dBm, 3.3 V
Rx boosted
Tx low power
26
mA
120
107
Tx high power
5.3.2
General operating conditions
Table 25. General operating conditions
Symbol
Parameter
Conditions
Min
Max
Unit
fHCLK
Internal AHB clock frequency
-
fPCLK1 Internal APB1 clock frequency
fPCLK2 Internal APB2 clock frequency
-
0
48
MHz
-
-
VDD
VDDA
VBAT
Standard operating voltage
1.8(1)
1.62
1.71
2.4
3.6
ADC or COMP used
DAC used
Analog supply voltage
3.6
V
VREFBUF used
ADC, DAC, COMP and
VREFBUF not used
0
Backup operating voltage
-
1.55
1.4
3.6
3.6
3.6
VFBSMPS SMPS feedback voltage
VDDRF Minimum RF voltage
-
-
1.8
TT I/O
–0.3
VDD + 0.3
V
min between
min (VDD, VDDA) + 3.6 V
and 5.5 V(2)(3)
VIN
I/O input voltage
All I/O except TT
DS13105 Rev 8
–0.3
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Electrical characteristics
STM32WLE5/E4xx
Table 25. General operating conditions (continued)
Symbol
Parameter
Conditions
Min
Max
Unit
Power dissipation at
TA = 85 °C for suffix 6 version
or TA = 105 °C for suffix 7(4)
PD
UFBGA73
-
392.0
mW
Maximum power
dissipation
85
Ambient temperature for
suffix 6 version
–40
Low-power dissipation(5)
105
105
TA
°C
°C
Maximum power
dissipation
Ambient temperature for the
suffix 7 version
–40
–40
Low-power dissipation(5)
125
105
125
Suffix 6 version
TJ
Junction temperature range
Suffix 7 version
1. When the reset is released, the functionality is guaranteed down to VBOR0 min.
2. This formula has to be applied only on the power supplies related to the I/O structure described in Table 19:
STM32WLE5/E4xx pin definition. Maximum I/O input voltage is the smallest value between min (VDD, VDDA) + 3.6 V and
5.5 V.
3. For operation with voltage higher than min (VDD, VDDA) + 0.3 V, the internal pull-up and pull-down resistors must be
disabled.
4. If TA is lower, higher PD values are allowed as long as TJ does not exceed TJ max (see Table 98: Package thermal
characteristics).
5. In low-power dissipation state, TA can be extended to this range, as long as TJ does not exceed TJ max (see Table 98:
Package thermal characteristics).
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DS13105 Rev 8
STM32WLE5/E4xx
Electrical characteristics
5.3.3
Sub-GHz radio characteristics
Electrical characteristics of the sub-GHz radio are given with the following conditions unless
otherwise specified:
•
V
= 3.3 V. The current consumption is measured as described in Figure 14.
DD
I
includes current consumption of all supplies (V
, V
, V , V
, V
).
BAT
DD
DDRF
DDSMPS
DD
DDA
All peripherals except Sub-GHz radio are disabled and the system is in Standby mode.
•
•
•
•
•
•
•
Temperature = 25 °C
HSE32 = 32 MHz
F
= 434/868/915 MHz
RF
All RF impedances matched using reference design
Reference design implementing a 32 MHz crystal oscillator
Transmit mode output power defined in 50 Ω load
FSK BER (bit error rate) = 0.1 %, 2-level FSK modulation without pre-filtering,
BR = 4.8 Kbit/s, FDA = 5 kHz, BW_F = 20 kHz
•
LoRa PER (packet error rate) = 1 %, packet of 64 bytes, preamble of 8 bytes, error
correction code CR = 4/5, CRC on payload enabled, no reduced encoding, no implicit
header
•
•
•
Sensitivities given using highest LNA gain step
Power consumption measured with -140 dBm signal and AGC ON
Blocking immunity, ACR and co-channel rejection, given for a single tone interferer and
referenced to sensitivity +6 dB, blocking tests performed with unmodulated signal
•
Bandwidth expressed on DSB (double-sided band)
Table 26. Operating range of RF pads
Pad
Description
Max
Unit
RFI_P/RFI_N
RF input power
Voltage Standing Wave Ratio (VSWR)
0
dBm
RFO_LP/RFO_HP/VR_PA
10.1
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Electrical characteristics
STM32WLE5/E4xx
Table 27. Sub-GHz radio power consumption
Conditions
Symbol
Mode
Min
Typ
Max Unit
Deep-Sleep
mode (Sleep
with cold
All blocks off
-
50
-
start)(1)(2)
nA
Sleep mode
(with warm
start)(2)(3)
Configuration retained
-
-
140
810
-
Configuration retained + RC64k
-
HSE32 off
-
-
-
414
564
700
-
-
Sleep, LDO
mode(4)
LDO, band-gap,
RC 13 MHz on
HSE32 on
µA
Band-gap,
RC 13 MHz on,
SMPS 40 mA max
HSE32 off
HSE32 on
-
Sleep, SMPS
mode(4)
-
-
950
0.7
-
Standby mode
(RC 13 MHz on)
RC 13 MHz on, HSE32 off
-
-
IDD
SMPS mode
40 mA max settings
-
-
-
-
-
-
-
-
-
1.05
0.99
2.66
4.05
4.47
4.82
5.12
5.46
8.18
8.90
9.52
10.22
Standby mode
(HSE32)
mA
LDO mode
-
SMPS mode used with 40 mA drive capability
-
-
-
-
-
Synthesizer
mode
LDO mode
FSK 4.8 Kbit/s
Receive mode,
SMPS mode
used
LoRa 125 kHz
SMPS 40 mA max
Rx boosted, FSK 4.8 Kbit/s
RX boosted, LoRa 125 kHz
FSK 4.8 Kbit/s
-
mA
-
LoRa 125 kHz
Receive mode,
LDO mode used
FSK 4.8 Kbit/s
RX boosted
LoRa 125 kHz
1. Cold start is equivalent to device at POR or when the device wakes up from Sleep mode with all blocks off.
2. Only Sub-GHz radio power consumption.
3. Warm start only happens when the device wakes up from Sleep mode with its configuration retained,
4. System in Stop 0 mode range 2.
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DS13105 Rev 8
STM32WLE5/E4xx
Electrical characteristics
Table 28. Sub-GHz radio power consumption in transmit mode
Symbol Frequency band (MHz)
PA match (conditions)
Power output
Typ
Unit
+14 dBm, VDDRF = 3.3 V
+10 dBm, VDDRF = 3.3 V
+14 dBm, VDDRF = 1.8 V
+10 dBm, VDDRF = 1.8 V
+15 dBm, VDDRF = 3.3 V
+10 dBm, VDDRF = 3.3 V
+15 dBm, VDDRF = 1.8 V
+10 dBm, VDDRF = 1.8 V
+14 dBm, VDDRF = 3.3 V
+10 dBm, VDDRF = 3.3 V
+14 dBm, VDDRF = 1.8
+10 dBm, VDDRF = 1.8 V
+15 dBm, VDDRF = 3.3 V
+10 dBm, VDDRF = 3.3 V
+15 dBm, VDDRF = 1.8 V
+10 dBm, VDDRF = 1.8 V
23.5
17.5
41.5
28.5
25.5
15
Low power
(optimized for 14 dBm)
868 to 915
Low power
(optimal settings)(1)
51
25
22.5
13.5
39.5
22.5
24.5
13.5
43
Low power
(optimized for 14 dBm)
434 to 490
Low power (optimal settings)
Low-power PA, SMPS OFF
21.5
45.5
43.5
119
107.5
98
IDD
mA
868 to 915
+14 dBm, VDDRF = 3.3 V
434 to 490
+22 dBm, VDDRF = 3.3 V
+20 dBm, VDDRF = 3.3 V
+17 dBm, VDDRF = 3.3 V
+14 dBm, VDDRF = 3.3 V
+20 dBm, VDDRF = 3.3 V
High power
(optimized for 22 dBm)
868 to 915
92
92.5
58
High power (optimal settings) +17 dBm, VDDRF = 3.3 V
+14 dBm, VDDRF = 3.3 V
45.5
110.5
90
+22 dBm, VDDRF = 3.3 V
+20 dBm, VDDRF = 3.3 V
+17 dBm, VDDRF = 3.3 V
+14 dBm, VDDRF = 3.3 V
+20 dBm, VDDRF = 3.3 V
High power
(optimized for 22 dBm)
71
434 to 490
59
72
High power (optimal settings) +17 dBm, VDDRF = 3.3 V
+14 dBm, VDDRF = 3.3 V
43.5
38
1. Optimal settings can be used to optimize power consumption when the output power is NOT 22 dBm (high power) or
14 dBm (low power). In that case, a dedicated firmware configuration associated to a dedicated board matching network
(see AN5457 for details) corresponding to the custom output power, can be used.
DS13105 Rev 8
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133
Electrical characteristics
STM32WLE5/E4xx
Table 29. Sub-GHz radio general specifications
Description Conditions Min
Frequency synthesizer range Low-power PA
Symbol
Typ
Max
Unit
FR
150
-
960
MHz
Hz
FSTEP Frequency synthesizer step
High-resolution mode HSE / 2(2)(5)
-
-
-
-
-
095
–100
–120
–135
40
-
-
-
-
-
100 kHz offset
PHN(1) Synthesizer phase noise
1 MHz offset
dBc/Hz
(2)
(868 to 915 MHz)
10 MHz offset
TS_FS Synthesizer wakeup time
From Standby, HSE32 mode
TS_HO
Synthesizer hop time
P
10 MHz step
-
-
40
-
-
µs
TS_OS
From Standby, RC(3) normal mode
from HSE32 off
Crystal oscillator wakeup time
C
170
Crystal oscillator trimming range
OSC_
TRM
for crystal frequency error
Min/max XTAL specifications
±15
±30
-
ppm
compensation(4)
Programmable
(min modulation index is 0.5)
BR_F Bitrate, FSK
0.6
0.6
-
-
-
300(5) Kbit/s
200 kHz
62.5(6) Kbit/s
Programmable
(FDA + BR_F/2 ≤ 250 kHz)
FDA
Frequency deviation, FSK
Min for SF12, BW_L = 7.8 kHz
Max for SF7, BW_L = 500 kHz
BR_L Bitrate, LoRa
0.018
BW_L Signal BW, LoRa
Programmable
7.8
5
-
-
500(6)
12
kHz
-
SF
Spreading factor for LoRa
Programmable, chips/symbol = 2SF
1. Phase Noise specifications are given for the recommended PLL bandwidth to be used for the specific modulation/BR,
optimized settings may be used for specific applications.
2. Phase Noise is not constant over frequency, due to the topology of the PLL. For two frequencies close to each other, the
phase noise may change significantly
3. Wakeup time till crystal oscillator frequency is within ±10 ppm.
4. OSC_TRIM is the available trimming range to compensate for crystal initial frequency error and to allow crystal temperature
compensation implementation. The total available trimming range is higher and allows the compensation for all device
process variations
5. Maximum bit rate is assumed to scale with the RF frequency: for example 300 Kbit /s in the 869-to-915 MHz frequency
band and only 50 Kbit/s at 150 MHz.
6. For RF frequencies below 400 MHz, there is a scaling between the frequency and supported bandwidth. Some bandwidths
may not be available below 400 MHz.
70/145
DS13105 Rev 8
STM32WLE5/E4xx
Symbol
Electrical characteristics
Table 30. Sub-GHz radio receive mode specifications
Description
Conditions
Min
Typ
Max
Unit
BR = 0.6 Kbit/s, FDA = 0.8 kHz,
BW = 4 kHz
-
–125
-
BR = 1.2 Kbit/s, FDA = 5 kHz,
BW = 20 kHz
-
-
-
-
–123
–117
–108
–103
-
-
-
-
Sensitivity 2-FSK,
RX boosted gain,
split RF paths for RX and Tx,
RF switch insertion loss excluded
BR = 4.8 Kbit/s, FDA = 5 kHz,
BW = 20 kHz
RXS_2FB
BR = 38.4 Kbit/s, FDA = 40 kHz,
BW = 160 kHz
BR = 250 Kbit/s, FDA = 125 kHz,
BW = 500 kHz
BW = 10.4 kHz, SF = 7
BW = 10.4 kHz, SF = 12
BW = 125 kHz, SF = 7
BW = 125 kHz, SF = 12
BW = 250 kHz, SF = 7
BW = 250 kHz, SF = 12
BW = 500 kHz, SF = 7
BW = 500 kHz, SF = 12
-
-
-
-
-
-
-
-
–135
–148
–125
–138
–122
–135
–118
–130
-
-
-
-
-
-
-
-
dBm
Sensitivity LoRa,
RX boosted gain,
split RF paths for RX and Tx,
RF switch insertion loss excluded
RXS_LB
Sensitivity 2-FSK, RX power
RSX_2F saving gain with direct tie
connection between RX and Tx
BR = 4.8 Kbit/s, FDA = 5 kHz,
BW = 20 kHz
-
-
–115
–135
-
-
Sensitivity LoRa, RX power
RXS_L saving gain with direct tie
connection between RX and Tx
BW = 125 kHz, SF = 12
CCR_F Co-channel rejection, FSK
-
-
-
-
-
–9
7
-
-
-
-
SF = 7
SF = 12
CCR_L Co-channel rejection, LoRa
19
44
ACR_F Adjacent channel rejection, FSK Offset = ±50 kHz
Offset = ±1.5 x BW_L,
-
-
-
-
-
60
71
67
70
76
-
-
-
-
-
BW = 125 kHz, SF = 7
ACR_L Adjacent channel rejection, LoRa
Offset = ±1.5 x BW_L,
dB
BW = 125 kHz, SF = 12
Offset = ±1 MHz, BR = 4.8 Kbit/s,
FDA = 5 kHz, BW = 20 kHz
Offset = ±2 MHz, BR = 4.8 Kbit/s,
FDA = 5 kHz, BW = 20 kHz
BI_F
Blocking immunity, FSK
Offset = ±10 MHz,BR = 4.8 Kbit/s,
FDA = 5 kHz, BW = 20 kHz
DS13105 Rev 8
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Electrical characteristics
STM32WLE5/E4xx
Table 30. Sub-GHz radio receive mode specifications (continued)
Symbol
Description
Conditions
Min
Typ
Max
Unit
Offset = ±1 MHz, BW = 125 kHz,
SF = 12
-
87
-
Offset = ±2 MHz, BW = 125 kHz,
SF = 12
BI_L
Blocking immunity, LoRa
-
-
91
96
-
-
dB
Offset = ±10 MHz, BW = 125 kHz,
SF = 12
Unwanted tones are 1 MHz and
1.96 MHz above LO.
868 to 915 MHz band
-
-
–9
-
-
IIP3
Third order input intercept point
dBm
dB
Unwanted tones are 1 MHz and
1.96 MHz above LO.
433 MHz band
–15
Without IQ calibration
With IQ calibration
-
-
30
54
-
-
IMA
Image attenuation
-
467
-
BW_F
DSB channel filter BW, FSK
Programmable, typical values
FS to RWX
4.8
-
kHz
µs
TS_RX Receiver wakeup time
41
All bandwidths, ±25 % of BW.
Maximum tolerated frequency
offset between transmitter and
receiver, SF7 to SF12
-
±25
-
BW
The tighter limit between this line
and the three lines below applies.
FERR_L
SF12
SF11
SF10
–50
–100
–200
-
-
-
50
Maximum tolerated frequency
offset between transmitter and
receiver, SF10 to SF12
100
200
ppm
Table 31. Sub-GHz radio transmit mode specifications
Symbol
Description
Conditions
Min
Typ
Max Unit
Highest power step setting
for low-power PA (LP PA)
-
+15(1)
+22
-
TXOP
Max RF output power
dBm
-
Highest power step setting
for high-power PA (HP PA)
-
-
LP PA, under SMPS or LDO
VDDop range from 1.8 to 3.7 V
0.5
-
RF output power drop
versus supply voltage
HP PA, +22 dBm, VDD = 2.7 V
HP PA, +22 dBm, VDD = 2.4 V
HP PA, +22 dBm, VDD = 1.8 V
-
-
-
2
3
6
-
-
-
TXDRP
dB
Programmable in 31 steps,
typical value
TXPRNG RF output power range
TXOP-31
-
-
TXOP dBm
dB
RF output power step
TXACC
-
±2
-
accuracy
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DS13105 Rev 8
STM32WLE5/E4xx
Electrical characteristics
Table 31. Sub-GHz radio transmit mode specifications (continued)
Symbol
Description
Conditions
Programmable
Min
Typ
Max Unit
TXRMP PA ramping time
TS_TX TX wakeup time
10
-
3400
µs
Frequency synthesizer
enabled
-
36 + PA ramping
-
1. For low-power PA, +15 dBm maximum RF output power can be reached with optimal settings.
Table 32. Sub-GHz radio power management specifications
Frequency
(MHz)
Symbol
Description
Conditions
Unit
470 490 868
TRPOR
VEOLL
VEOLH
VEOLD
Required POR reset pulse duration
End-of-life low-threshold voltage
End-of-life high-threshold voltage
End-of-life hysteresis voltage
For VDD ≥ 1.8 V
50 100
-
µs
V
-
1.81 1.89 1.96
1.86 1.94 2.1
-
VEOLH - VEOLL
50
53
56
mV
V
LDO or SMPS over process,
voltage and temperature range
VREG
Main regulated supply
1.47 1.55 1.62
Load transient for ILSMPS 100 µA to High BW mode
-
-
25
47
-
-
LDTRSMPS 100 mA in 10 µs
LDO running
mV
Low BW mode
ILSMPS
SMPS load current
-
-
-
-
-
100 mA
SMPS high power, VDD = 3.3 V
SMPS low power, VDD = 3.3 V
538
460
-
IDDSMPS
SMPS quiescent current
µA
-
SMPS 100 mA max VDD = 3.3 V,
ILSMPS = 6 mA
-
-
-
-
-
71
89
88
91
86
-
-
SMPS 100 mA max VDD = 3.3 V,
ILSMPS = 50 mA
SMPS converter average efficiency
SMPS 100 mA max VDD = 1.8 V,
ILSMPS = 6 mA
EFFSMPS EFF = VREG x ILOAD /
VDDSMPS x IDD
-
-
-
%
SMPS 100 mA max VDD = 2.0 V,
ILSMPS = 50 mA
SMPS 100 mA max VDD = 3.3 V,
ILSMPS = 100 mA
Cout
Lout
Shared between LDO and SMPS
SMPS inductor
±20 % tolerance
-
-
-
-
470
15
-
-
-
nF
µH
µs
TSSMPS
Sleep and Sleep, SMPS startup time For ILIM = 50 mA
70
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133
Electrical characteristics
STM32WLE5/E4xx
Table 32. Sub-GHz radio power management specifications (continued)
Frequency
(MHz)
Symbol
Description
Conditions
Unit
470 490 868
VDD = 3.3 V,
ILOAD = 0 to 100 mA,
current limiter off
-
-
95
-
-
IDDLDO
LDO quiescent current
LDO load current
VDD = 3.3 V, ILOAD = 100 mA,
µA
380
current limiter on
VDD = 3.3 V, ILOAD = 50 mA,
current limiter on
-
-
-
-
280
100
25
-
-
-
-
ILDO
-
-
mA
mV
Load transient for ILDO 100 µA to
100 mA in 10 µs
LDTRLDO
TSLDO
VDIG
Sleep and Sleep, LDO startup time
Digital regulator target voltage
Current limiter max value
For ILIM = 50 mA
60
µs
V
-
-
1.14 1.2 1.26
25
ILM(1)
50 200 mA
1. The default current limiter value is set to 50 mA.
5.3.4
Operating conditions at power-up/power-down
Parameters given in the table below are derived from tests performed under the ambient
temperature condition summarized in Table 25: General operating conditions.
Table 33. Operating conditions at power-up/power-down
Symbol
Parameter
VDD rise time rate
Min
Max
Unit
-
10
0
∞
∞
∞
∞
∞
∞
tVDD
tVDDA
tVDDRF
VDD fall time rate
VDDA rise time rate
µs/V
VDDA fall time rate
10
-
VDDRF rise time rate
VDDRF fall time rate
-
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DS13105 Rev 8
STM32WLE5/E4xx
Electrical characteristics
5.3.5
Embedded reset and power-control block characteristics
Parameters given in the table below are derived from tests performed under the ambient
temperature conditions summarized in Table 25: General operating conditions.
Table 34. Embedded reset and power-control block characteristics
Symbol
Parameter
Conditions(1)
Min
Typ
Max Unit
(2)
tRSTTEMPO
Reset temporization after BOR0 is detected VDD rising
-
250
400
μs
Rising edge
Brownout reset threshold 0
1.72 1.76 1.80
1.70 1.74 1.78
2.06 2.10 2.14
1.96 2.00 2.04
2.26 2.31 2.35
2.16 2.20 2.24
2.56 2.61 2.66
2.47 2.52 2.57
2.85 2.90 2.95
2.76 2.81 2.86
1.88 1.95 2.02
1.83 1.90 1.97
2.26 2.31 2.36
2.15 2.20 2.25
2.41 2.46 2.51
2.31 2.36 2.41
2.56 2.61 2.66
2.47 2.52 2.57
2.69 2.74 2.79
2.59 2.64 2.69
2.85 2.91 2.96
2.75 2.81 2.86
2.92 2.98 3.04
2.84 2.90 2.96
(2)
VBOR0
Falling edge
Rising edge
Brownout reset threshold 1
VBOR1
VBOR2
VBOR3
VBOR4
VPVD0
VPVD1
VPVD2
VPVD3
VPVD4
VPVD5
VPVD6
Falling edge
Rising edge
Brownout reset threshold 2
Falling edge
Rising edge
Brownout reset threshold 3
Falling edge
V
Rising edge
Brownout reset threshold 4
Falling edge
Rising edge
Programmable voltage detector threshold 0
Falling edge
Rising edge
PVD threshold 1
Falling edge
Rising edge
PVD threshold 2
Falling edge
Rising edge
PVD threshold 3
Falling edge
Rising edge
PVD threshold 4
Falling edge
V
Rising edge
PVD threshold 5
Falling edge
Rising edge
PVD threshold 6
Falling edge
Hysteresis in
-
-
-
-
20
30
-
-
continuous mode
Hysteresis voltage of BORH0
Vhyst_BORH0
Hysteresis in
other mode
mV
Hysteresis voltage of BORH (except
BORH0) and PVD
Vhyst_BOR_PVD
-
100
1.1
-
BOR(3) (except BOR0) and PVD
consumption from VDD
IDD (BOR_PVD)(2)
-
1.6
µA
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Electrical characteristics
STM32WLE5/E4xx
Table 34. Embedded reset and power-control block characteristics (continued)
Symbol
Parameter
Conditions(1)
Min
Typ
Max Unit
Rising edge
1.61 1.65 1.69
VPVM3
VDDA peripheral voltage monitoring
V
Falling edge
1.6
1.64 1.68
Vhyst_PVM3
PVM3 hysteresis
-
-
-
-
10
2
-
-
mV
µA
IDD (PVM3)(2)
PVM3 consumption from VDD
1. Continuous mode means Run and Sleep modes, or temperature sensor enable in LPRun and LPSleep modes.
2. Guaranteed by design.
3. BOR0 is enabled in all modes (except Shutdown) and its consumption is therefore included in the supply current
characteristics tables.
5.3.6
Embedded voltage reference
Parameters given in the table below are derived from tests performed under the ambient
temperature and supply voltage conditions summarized in Table 25: General operating
conditions.
Table 35. Embedded internal voltage reference
Symbol
VREFINT
Parameter
Conditions
Min
Typ
Max
Unit
Internal reference voltage
–40 °C < TJ < +105 °C
1.182 1.212 1.232
V
ADC sampling time when reading
the internal reference voltage
(1)
tS_vrefint
tstart_vrefint
IDD(VREFINTBUF
ꢀVREFINT
-
4(2)
-
8
-
µs
Start time of reference voltage
buffer when ADC is enable
-
-
-
-
12(2)
20(2)
VREFINT buffer consumption from
VDD when converted by ADC
)
-
12.5
µA
Internal reference voltage spread
over the temperature range
VDD = 3.3 V
5
7.5(2)
50(2)
mV
TCoeff
ACoeff
Temperature coefficient
Long term stability
Voltage coefficient
–40 °C < TJ < +105 °C
1000 hours, T = 25 °C
3.0 V < VDD < 3.6 V
-
-
30
ppm/°C
ppm
300 1000(2)
VDDCoeff
-
250 1200(2) ppm/V
VREFINT_DIV1 1/4 reference voltage
VREFINT_DIV2 1/2 reference voltage
VREFINT_DIV3 3/4 reference voltage
24
49
74
25
50
75
26
51
76
%
-
VREFINT
1. The shortest sampling time can be determined in the application by multiple iterations.
2. Guaranteed by design.
76/145
DS13105 Rev 8
STM32WLE5/E4xx
Electrical characteristics
Figure 15. V
versus temperature
REFINT
V
1.235
1.23
1.225
1.22
1.215
1.21
1.205
1.2
1.195
1.19
1.185
°C
-40
-20
0
20
Mean
40
60
80
100
120
Min
Max
MSv66005V3
5.3.7
Supply current characteristics
The current consumption is a function of several parameters and factors such as operating
voltage, ambient temperature, I/O pin loading, device software configuration, operating
frequencies, I/O pin switching rate, program location in memory and executed binary code.
The current consumption is measured as described in Figure 14.
Typical and maximum current consumption
The device is put under the following conditions:
•
•
•
All I/O pins are in analog input mode.
All peripherals are disabled, except when explicitly mentioned.
The Flash memory access time is adjusted with the minimum wait-states number,
depending on the f
frequency. Refer to the table ‘Number of wait states according
HCLK
to Flash clock (HCLK3) frequency’ in the reference manual (RM0461).
•
•
f
f
= f
= f
when the peripherals are enabled.
PCLK
PCLK
HCLK
HCLK
= f
for the Flash memory and shared peripherals.
HCLKS
Parameters given in the tables below (Table 36 to Table 52) are derived from tests
performed under ambient temperature and supply voltage conditions summarized in
Table 25: General operating conditions.
DS13105 Rev 8
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133
Table 36. Current consumption in Run and LPRun modes, CoreMark code with data
running from Flash memory, ART enable (cache ON, prefetch OFF)
Conditions
Typ
Max(1)
85 °C
Symbol
Parameter
Unit
Voltage
scaling
fHCLK
(MHz)
-
25 °C
55 °C
85 °C
105 °C
25 °C
105 °C
16
8
1.85
1.10
1.90
1.15
1.95
1.20
2.10
1.30
2.20
2.40
2.80
Range 2
1.40
1.60
1.90
2
0.585
1.50
0.610
1.45
0.670
1.65
0.760
1.70
-
-
-
16
8
-
-
-
SMPS
1.00
1.05
1.05
1.10
-
-
-
-
-
-
Range 2
fHCLK = fMSI
2
0.730
5.55
0.750
5.65
0.780
5.80
0.830
5.95
Supply current
in Run mode
IDD (Run)
All peripherals
disabled
48
32
16
48
32
16
2
7.40
5.60
3.70
-
11.0
8.40
6.60
-
14.0
13.0
11.0
-
Range 1
3.85
3.95
4.05
4.20
mA
2.15
2.20
2.30
2.45
3.40
3.45
3.55
3.60
SMPS
Range 1
2.50
2.55
2.60
2.65
-
-
-
1.60
1.60
1.65
1.70
-
-
-
0.220
0.120
0.058
0.235
0.135
0.0715
0.290
0.185
0.120
0.380
0.275
0.210
0.270
0.150
0.084
0.490
0.390
0.330
0.880
0.780
0.710
fHCLK = fMSI
IDD
Supply current
1
(LPRun) in LPRun mode
All peripherals disabled
0.4
1. Guaranteed by characterization results, unless otherwise specified.
Table 37. Current consumption in Run and LPRun modes, CoreMark code
with data running from SRAM1
Conditions
Typ
Max(1)
85 °C
Symbol
Parameter
Unit
Voltage
scaling
fHCLK
(MHz)
-
25 °C
55 °C
85 °C
105 °C
25 °C
105 °C
16
8
1.90
1.10
-
1.90
1.15
-
2.00
1.20
-
2.10
1.30
-
2.20
2.40
2.80
Range 2
1.40
1.60
2.00
2
-
-
-
16
8
1.40
1.00
0.730
5.65
3.90
2.20
3.45
2.50
1.60
0.220
0.120
0.052
1.45
1.05
0.750
5.75
4.00
2.25
3.50
2.55
1.60
0.230
0.130
0.064
1.50
1.05
0.780
5.90
4.10
2.30
3.60
2.60
1.65
0.285
0.180
0.115
1.55
1.10
0.825
6.05
4.25
2.45
3.65
2.70
1.70
0.375
0.270
0.205
-
-
-
SMPS
Range 2
-
-
-
-
-
-
f
HCLK = fMSI
2
IDD
(Run)
Supply current
in Run mode
All peripherals
disabled
48
32
16
48
32
16
2
6.50
4.60
2.50
-
6.70
4.80
2.80
-
7.10
5.20
3.20
-
Range 1
mA
SMPS
Range 1
-
-
-
-
-
-
0.240
0.140
0.077
0.480
0.380
0.320
0.860
0.770
0.710
fHCLK = fMSI
IDD
(LPRun)
Supply current
in LPRun mode
1
All peripherals disabled
0.4
1. Guaranteed by characterization results, unless otherwise specified.
Table 38. Typical current consumption in Run and LPRun modes, with different codes
running from Flash memory, ART enable (cache ON, prefetch OFF)
Conditions
Typ
Typ
Symbol
Parameter
Unit
Unit
-
Voltage scaling
Code
25 °C
25 °C
Reduced code
CoreMark(1)
Dhrystone 2.1
Fibonacci
1.90
1.85
1.85
1.80
1.60
1.45
1.40
1.40
1.40
1.30
5.70
5.55
5.50
5.40
4.65
3.50
3.40
3.40
3.30
2.90
118.75
115.63
115.63
112.50
100.00
90.63
87.50
87.50
87.50
81.25
118.75
115.63
114.58
112.50
96.88
72.92
70.83
70.83
68.75
60.42
Range 2
f
HCLK = 16 MHz
While(1)
Reduced code
CoreMark(1)
Dhrystone 2.1
Fibonacci
SMPS
Range 2
fHCLK = 16 MHz
While(1)
fHCLK = fMSI
Supply current in
Run mode
IDD(Run)
mA
µA/MHz
All peripherals disabled
Reduced code
CoreMark(1)
Dhrystone 2.1
Fibonacci
Range 1
fHCLK = 48 MHz
While(1)
Reduced code
CoreMark(1)
Dhrystone 2.1
Fibonacci
SMPS
Range 1
fHCLK = 48 MHz
While(1)
Table 38. Typical current consumption in Run and LPRun modes, with different codes
running from Flash memory, ART enable (cache ON, prefetch OFF) (continued)
Conditions
Typ
Typ
Symbol
Parameter
Unit
Unit
-
Voltage scaling
Code
25 °C
25 °C
Reduced code
CoreMark(1)
Dhrystone 2.1
Fibonacci
0.225
0.220
0.220
0.240
0.175
112.50
110.00
110.00
120.00
87.50
fHCLK = fMSI = 2 MHz
Supply current in
LPRun mode
IDD(LPRun)
mA
µA/MHz
All peripherals disabled
While(1)
1. CoreMark used for characterization results provided in Table 36 and Table 38.
Table 39. Typical current consumption in Run and LPRun modes,
with different codes running from SRAM1
Conditions
Typ
Typ
Symbol
Parameter
Unit
Unit
-
Voltage scaling
Code
25 °C
25 °C
Reduced code
CoreMark(1)
Dhrystone 2.1
Fibonacci
1.95
1.90
1.90
1.90
1.75
1.45
1.45
1.45
1.45
1.35
5.90
5.65
5.70
5.65
5.10
3.60
3.45
3.50
3.45
3.15
121.88
118.75
118.75
118.75
109.38
90.63
Range 2
f
HCLK = 16 MHz
While(1)
Reduced code
CoreMark(1)
Dhrystone 2.1
Fibonacci
90.63
Range 2
SMPS ON
90.63
fHCLK = 16 MHz
90.63
While(1)
84.38
fHCLK = fMSI
All peripherals disabled
Supply current
in Run mode
IDD(Run)
mA
µA/MHz
Reduced code
CoreMark(1)
Dhrystone 2.1
Fibonacci
122.92
117.71
118.75
117.71
106.25
75.00
Range 1
fHCLK = 48 MHz
While(1)
Reduced code
CoreMark(1)
Dhrystone 2.1
Fibonacci
71.88
Range 1
SMPS ON
72.92
fHCLK = 48 MHz
71.88
While(1)
65.63
Table 39. Typical current consumption in Run and LPRun modes,
with different codes running from SRAM1 (continued)
Conditions
Typ
Typ
Symbol
Parameter
Unit
Unit
-
Voltage scaling
Code
25 °C
25 °C
Reduced code
CoreMark(1)
Dhrystone 2.1
Fibonacci
0.225
0.220
0.225
0.225
0.195
112.50
110.00
112.50
112.50
97.50
fHCLK = fMSI = 2 MHz
Supply current
in LPRun mode
IDD(LPRun)(2)
mA
µA/MHz
All peripherals disabled
While(1)
1. CoreMark used for characterization results provided in Table 36 and Table 38.
2. Flash memory in power-down mode.
Table 40. Current consumption in Sleep and LPSleep modes, Flash memory ON
Conditions Typ
Max(1)
85 °C
Symbol
Parameter
Unit
Voltage
fHCLK
(MHz)
-
25 °C
55 °C
85 °C
105 °C
25 °C
105 °C
scaling
16
8
0.770
0.570
0.445
1.70
0.800
0.600
0.470
1.70
0.860
0.655
0.525
1.80
0.955
0.745
0.615
1.90
1.00
0.780
0.650
2.10
1.60
1.10
-
1.30
0.990
0.860
2.30
1.90
1.40
-
1.60
1.40
1.30
2.70
2.30
1.80
-
Range 2
2
48
32
16
48
32
16
2
fHCLK = fMSI
Supply current
in Sleep mode
IDD(Sleep)
Range 1
1.25
1.30
1.40
1.50
All peripherals disabled
0.845
1.35
0.875
1.40
0.945
1.45
1.05
1.50
mA
SMPS
Range 1
1.15
1.15
1.20
1.25
-
-
-
0.895
0.068
0.044
0.0225
0.018
0.915
0.950
0.130
0.105
0.0885
0.081
1.00
-
-
-
0.0805
0.0565
0.040
0.220
0.195
0.180
0.170
0.095
0.069
0.052
0.045
0.330
0.310
0.290
0.280
0.720
0.700
0.680
0.670
Supply current
in LPSleep
mode
1
fHCLK = fMSI
All peripherals disabled
IDD(LPSleep)
0.4
0.1
0.032
1. Guaranteed by characterization results, unless otherwise specified.
Table 41. Current consumption in LPSleep mode, Flash memory in power-down
Conditions
fHCLK (MHz)
Typ
Max(1)
Symbol
Parameter
Unit
-
25 °C
55 °C
85 °C
105 °C
25 °C
85 °C
105 °C
2
58.0
35.5
18.5
11.0
74.5
50.5
33.5
26.5
125
99.0
81.5
74.5
215
190
170
165
86.0
60.0
41.0
36.0
330
300
280
280
710
690
670
660
fHCLK = fMS
1
IDD
Supply current in
LPSleep mode
µA
All peripherals
disabled
(LPSleep)
0.4
0.1
1. Guaranteed by characterization results, unless otherwise specified.
Table 42. Current consumption in Stop 2 mode
Conditions
VDD (V)
Typ
Max(1)
Symbol
Parameter
Unit
0 °C 25 °C 55 °C 85 °C
105 °C
0 °C 25 °C 85 °C
105 °C
1.8
2.4
3.0
3.6
1.8
2.4
3.0
3.6
0.545 0.830
0.525 0.850
0.605 0.885
0.630 0.935
0.650 0.880
0.630 0.945
0.715 1.00
0.750 1.10
2.45
2.60
2.80
3.10
2.55
2.70
2.90
3.15
8.45
8.80
9.25
9.75
8.25
8.85
9.70
10.5
13.5
14.0
14.5
15.5
13.5
14.0
15.0
15.5
1.20
-
2.20
-
24.0
-
66.0
-
IDD
Supply current in Stop 2 mode
RTC disabled
(Stop 2)
1.10
1.40
1.30
-
2.60
2.80
2.30
-
26.0
26.0
24.0
-
69.0
71.0
66.0
-
µA
IDD
Supply current in Stop 2 mode
RTC enabled, clocked by LSI(2)
(Stop 2 with
RTC)
1.40
1.50
2.80
3.00
26.0
26.0
69.0
71.0
1. Guaranteed based on test during characterization, unless otherwise specified.
2. LSI using LSIPRE = 1 configuration.
Table 43. Current consumption during wakeup from Stop 2 mode
Typ at 25 °C
Conditions
Unit
VDD = 1.8 V
VDD = 2.4 V
VDD = 3.0 V
VDD = 3.6 V
Wakeup clock: MSI 4 MHz, voltage range 2
Wakeup clock: MSI 2 MHz, voltage range 2
Wakeup clock: MSI 4 MHz, voltage range 1
Wakeup clock: MSI 16 MHz, voltage range 1
Wakeup clock: MSI 48 MHz, voltage range 1
2.93
4.44
3.03
1.75
1.75
3.22
5.03
3.14
1.95
1.40
3.45
5.82
3.51
2.00
1.89
4.79
7.36
4.66
3.06
2.80
nAs
Table 44. Current consumption in Stop 1 mode
Conditions
VDD (V)
Typ
Max(1)
Symbol
Parameter
Unit
0 °C 25 °C 55 °C 85 °C
105 °C
0 °C 25 °C 85 °C
105 °C
1.8
2.4
3.0
3.6
1.8
2.4
3.0
3.6
2.05
2.15
2.15
2.25
2.15
2.15
2.25
2.30
4.00
3.95
4.15
4.20
4.10
4.10
4.20
4.15
14.0
14.0
14.0
14.0
14.0
14.0
14.0
14.5
47.0
47.0
47.5
48.0
47.0
47.5
47.5
48.5
74.5
75.0
75.5
76.5
75.0
75.5
76.0
77.0
6.10
-
20.0
-
200
-
480
-
IDD
Supply current in Stop 1 mode
RTC disabled
(Stop 1)
5.90
6.20
6.30
-
20.0
20.0
20.0
-
200
200
200
-
490
490
480
-
µA
IDD
Supply current in Stop 1 mode
RTC enabled, clocked by LSI(2)
(Stop 1with
RTC)
6.40
6.70
21.0
21.0
200
200
490
490
1. Guaranteed based on test during characterization, unless otherwise specified.
2. LSI using LSIPRE = 1 configuration.
Table 45. Current consumption during wakeup from Stop 1 mode
Typ at 25 °C
Conditions
Unit
VDD = 1.8 V
VDD = 2.4 V
VDD = 3.0 V
VDD = 3.6 V
Wakeup clock: MSI 4 MHz, voltage range 2
Wakeup clock: MSI 2 MHz, voltage range 2
Wakeup clock: MSI 4 MHz, voltage range 1
Wakeup clock: MSI 16 MHz, voltage range 1
Wakeup clock: MSI 48 MHz, voltage range 1
1.05
1.81
1.15
1.81
1.09
2.12
1.18
2.40
0.766
0.310
0.0707
1.23
1.34
1.49
nAs
0.169
0.461
0.935
0.533
0.836
0.565
Table 46. Current consumption in Stop 0 mode
Conditions
Typ
Max(1)
25 °C 85 °C 105 °C
Symbol
Parameter
Unit
VDD
(V)
-
0 °C
25 °C
55 °C
85 °C 105 °C
0 °C
1.8
2.4
3.0
3.6
335
360
390
425
345
370
400
435
365
395
425
460
415
445
475
515
455
485
515
550
480
-
500
-
740
-
1200
-
IDD
Supply current in Stop 0 mode
RTC disabled
µA
(Stop 0)
540
580
570
600
800
840
1200
1300
1. Guaranteed based on test during characterization, unless otherwise specified.
Table 47. Current consumption during wakeup from Stop 0 mode
Typ at 25 °C
Conditions
Unit
VDD = 1.8 V
VDD = 2.4 V
VDD = 3.0 V
VDD = 3.6 V
Wakeup clock: MSI 4 MHz, voltage range 2
Wakeup clock: MSI 2 MHz, voltage range 2
Wakeup clock: MSI 4 MHz, voltage range 1
Wakeup clock: MSI 16 MHz, voltage range 1
Wakeup clock: MSI 48 MHz, voltage range 1
3.45
3.05
3.20
1.07
0.867
3.76
3.20
3.66
1.25
1.13
3.45
3.74
3.30
1.71
1.39
4.04
3.35
4.11
nAs
1.80
0.949
Table 48. Current consumption in Standby mode
Conditions
Typ
Max(1)
Symbol
Parameter
Unit
VDD
(V)
-
0 °C
25 °C
55 °C
85 °C
105 °C
0 °C
25 °C
85 °C
105 °C
1.8
2.4
3.0
3.6
1.8
2.4
3.0
3.6
1.8
2.4
3.0
3.6
1.8
2.4
3.0
3.6
0.009
0.022
0.046
0.075
0.130
0.140
0.165
0.190
0.215
0.230
0.260
0.305
0.270
0.295
0.345
0.415
0.027
0.051
0.071
0.125
0.205
0.225
0.255
0.300
0.295
0.325
0.360
0.425
0.350
0.390
0.445
0.535
0.245
0.340
0.470
0.650
0.820
0.915
1.05
1.00
1.35
1.75
2.30
2.90
3.25
3.70
4.25
3.10
3.45
3.95
4.55
3.15
3.50
4.00
4.60
2.40
2.85
3.40
4.05
5.55
6.05
6.60
7.25
5.30
5.95
6.85
7.85
5.80
6.25
6.85
7.55
-
-
-
-
-
-
-
-
No retention
-
-
-
-
Supply current in
Standby mode
RTC disabled
Backup registers
retained
-
-
-
-
IDD
(Standby)
0.200
0.550
8.20
24.0
-
-
-
-
SRAM2 retained
0.280
0.710
9.40
27.0
1.20
0.330
0.770
10.0
28.0
µA
0.895
0.990
1.15
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
RTC clocked by LSI
(PREDIV = 1)
Supply current in
Standby mode
(backup registers
and SRAM2
retained)
RTC enabled
IDD
(Standby
with RTC)
1.30
0.975
1.10
RTC clocked by LSE
quartz(2) in low drive
mode
1.25
1.45
1. Guaranteed by characterization results, unless otherwise specified.
2. Based on characterization done with a 32.768 kHz crystal (MC306-G-06Q-32.768, manufacturer JFVNY) with two 6.8 pF loading capacitors.
Table 49. Current consumption during wakeup from Standby mode
Typ at 25 °C
Symbol
Conditions
Unit
VDD = 1.8 V
VDD = 2.4 V
VDD = 3.0 V
VDD = 3.6 V
Wakeup clock: MSI 4 MHz
Wakeup clock: MSI 8 MHz
23.5
15.2
81.3
15.7
111
114
IDD (wakeup from Standby)
nAs
17.3
19.6
Table 50. Current consumption in Shutdown mode
Conditions
Typ
Max(1)
Symbol
Parameter
Unit
VDD
(V)
-
0 °C
25 °C
55 °C
85 °C
105 °C
0 °C
25 °C
85 °C
105 °C
1.8
2.4
3.0
3.6
1.8
2.4
3.0
3.6
1.8
2.4
3.0
3.6
0.001
0.008
0.018
0.041
0.054
0.090
0.160
0.250
0.140
0.165
0.205
0.265
0.008
0.018
0.031
0.062
0.065
0.105
0.175
0.280
0.155
0.185
0.225
0.295
0.105
0.135
0.180
0.260
0.145
0.200
0.295
0.440
0.270
0.315
0.380
0.500
0.380
0.445
0.545
0.690
0.545
0.665
0.860
1.15
0.995
1.20
1.45
1.80
1.35
1.60
1.95
2.45
1.20
1.40
1.70
2.10
0.001
0.043
1.70
6.40
Supply current in Shutdown mode
RTC disabled
Backup registers retained
-
-
-
-
IDD
(Shutdown)
0.078
0.150
2.40
8.50
0.110
0.190
2.90
9.90
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
RTC clocked by
µA
an external clock
Supply current
in Shutdown
mode (backup
registers
IDD
(Shutdown
with RTC)
0.605
0.705
0.855
1.10
retained)
RTC enabled
RTC clocked by
LSE quartz (2) in
low drive mode
1. Guaranteed by characterization results, unless otherwise specified.
2. Based on characterization done with a 32.768 kHz crystal (MC306-G-06Q-32.768, manufacturer JFVNY) with two 6.8 pF loading capacitors.
Table 51. Current consumption in VBAT mode
Conditions
Typ
Max
Symbol
Parameter
Unit
VBAT
(V)
-
0 °C
25 °C
55 °C
85 °C
105 °C
105 °C
1.8
2.4
3.0
3.6
1.8
2.4
3.0
3.6
1.00
1.00
1.00
3.00
140
155
185
230
3.00
3.00
5.00
11.0
150
170
200
245
19.0
22.0
31.0
50.0
180
200
235
295
95.0
110
150
220
275
310
375
485
180
200
270
380
390
435
545
710
1.00
1.00
1.00
3.00
140
155
185
230
RTC disabled
Backup domain
supply current
IDD(VBAT)
nA
RTC enabled and
clocked by LSE quartz(1)
1. Based on characterization done with a 32.768 kHz crystal (MC306-G-06Q-32.768, manufacturer JFVNY) with two 6.8 pF loading capacitors.
Table 52. Current under Reset condition
Conditions
Typ
Symbol
Unit
VDD (V)
25 °C
1.8 V
2.4 V
3.0 V
3.6 V
600
650
700
780
IDD(RST)
µA
STM32WLE5/E4xx
Electrical characteristics
I/O system current consumption
The current consumption of the I/O system has two components: a static and a dynamic.
I/O static current consumption
All the I/Os used as inputs with pull-up generate current consumption when the pin is
externally held low. The value of this current consumption can be simply computed by using
the pull-up/pull-down resistors values given in Table 72: I/O static characteristics.
For the output pins, any external pull-down or external load must also be considered to
estimate the current consumption.
Additional I/O current consumption is due to I/Os configured as inputs if an intermediate
voltage level is externally applied. This current consumption is caused by the input Schmitt
trigger circuits used to discriminate the input value. Unless this specific configuration is
required by the application, this supply current consumption can be avoided by configuring
these I/Os in analog mode. This is notably the case of ADC input pins which should be
configured as analog inputs.
Caution:
Any floating input pin can also settle to an intermediate voltage level or switch inadvertently,
as a result of external electromagnetic noise. To avoid current consumption related to
floating pins, these pins must either be configured in analog mode, or forced internally to a
definite digital value. This can be done either by using pull-up/down resistors or by
configuring the pins in output mode.
I/O dynamic current consumption
In addition to the internal peripheral current consumption measured previously (see
Table 53: Peripheral current consumption, the I/Os used by an application also contribute to
the current consumption. When an I/O pin switches, it uses the current from the I/O supply
voltage to supply the I/O pin circuitry and to charge/discharge the capacitive load (internal or
external) connected to the pin:
ISW = VDD × fSW × C
where
•
•
•
•
•
I
is the current sunk by a switching I/O to charge/discharge the capacitive load.
is the I/O supply voltage.
SW
V
f
DD
is the I/O switching frequency.
SW
C is the total capacitance seen by the I/O pin: C = C + C
Io
EXT .
C
is the PCB board capacitance plus any connected external device pin
EXT
capacitance.
The test pin is configured in push-pull output mode and is toggled by software at a fixed
frequency.
DS13105 Rev 8
91/145
133
Electrical characteristics
STM32WLE5/E4xx
On-chip peripheral current consumption
The current consumption of the on-chip peripherals is given in the table below. The device is
placed under the following conditions:
•
•
All I/O pins are in analog mode.
The given value is calculated by measuring the difference of the current consumptions:
–
–
when the peripheral is clocked on
when the peripheral is clocked off
•
•
Ambient operating temperature and supply voltage conditions summarized in Table 21:
Voltage characteristics.
The power consumption of the digital part of the on-chip peripherals is given in the table
below. The power consumption of the analog part of the peripherals (where applicable)
is indicated in each related section of the datasheet.
Table 53. Peripheral current consumption
Peripheral
Range 1
Range 2
LPRun and LPSleep
Unit
CRC1
DMA1
0.42
2.29
2.50
3.96
9.17
0.01
0.01
0.01
0.01
0.62
2.50
7.92
3.33
1.04
0.62
0.62
0.42
16.0
0.83
1.67
2.29
1.67
2.50
1.67
0.38
1.88
1.94
3.38
7.50
0.12
0.12
0.12
0.06
0.56
2.13
6.56
2.75
N/A
1.00
1.45
1.50
2.50
9.30
0.20
0.15
0.15
0.10
0.40
1.80
11.3
2.15
N/A
AHB1 DMA2
µA/MHz
DMAMUX1
All AHB1 peripherals
GPIOA
GPIOB
AHB2 GPIOC
µA/MHz
GPIOH
All AHB2 peripherals
AES1
FLASH
PKA
RNG1
AHB3
µA/MHz
RNG1 independent clock domain
N/A
N/A
SRAM1
0.38
0.37
13.4
0.69
1.37
1.94
1.37
2.00
1.37
0.55
0.50
16.0
0.50
1.05
1.40
1.05
1.60
0.90
SRAM2
All AHB3 peripherals(1)
DAC
I2C1
I2C1 independent clock domain
APB1
µA/MHz
I2C2
I2C2 independent clock domain
I2C3
92/145
DS13105 Rev 8
STM32WLE5/E4xx
Electrical characteristics
Table 53. Peripheral current consumption (continued)
Peripheral
Range 1
Range 2
LPRun and LPSleep
Unit
I2C3 independent clock domain
LPTIM1
2.29
1.67
2.50
1.67
2.50
0.83
2.29
2.08
1.87
1.44
2.19
1.37
2.12
0.69
1.94
1.81
1.30
1.50
1.45
0.90
1.55
0.65
0.65
3.55
LPTIM1 independent clock domain
LPTIM2
LPTIM2 independent clock domain
LPTIM3
LPTIM3 independent clock domain
LPUART1
APB1
µA/MHz
LPUART1 independent clock
domain
2.50
2.06
1.35
RTCAPB
2.08
1.46
4.58
1.88
4.58
0.42
19.6
1.25
0.21
1.25
6.25
2.29
2.29
1.67
4.17
15.8
1.46
1.46
62.9
1.81
1.19
3.81
1.56
3.75
0.31
16.1
1.00
0.13
1.06
5.19
1.94
1.87
1.38
3.38
13.0
1.25
1.25
52.3
1.50
0.90
2.95
1.35
3.05
0.05
20.2
0.70
0.30
0.90
8.30
1.35
1.25
1.00
2.90
15.8
1.10
1.10
59.7
SPI2
TIM2
USART2
USART2 independent clock domain
WWDG1
All APB1 peripherals(1)
ADC
ADC independent clock domain
SPI1
TIM1
APB2 TIM16
TIM17
µA/MHz
USART1
USART1 independent clock domain
All APB2 peripherals(1)
SUBGHZSPI
APB3
All APB3 peripherals
µA/MHz
All peripherals(1)
1. Without independent clocks.
5.3.8
Wakeup time from low-power modes and voltage scaling
transition times
The wakeup times given in the table below, are the latency between the event and the
execution of the first user instruction.
The device goes in low-power mode after the WFE (wait for event) instruction.
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(1)
Table 54. Low-power mode wakeup timings
Symbol
Parameter
Conditions
Typ Max
Unit
Wakeup time from
Sleep to Run mode
tWUSLEEP
-
0.188 0.222
µs
Wakeup time from
tWULPSLEEP LPSleep to LPRun
mode
Wakeup in Flash with memory in power-down
during LPSleep mode (FPDS = 1 in PWR_CR1)
and with clock MSI = 2 MHz
3.81 4.38
Wakeup clock MSI = 48 MHz
Wakeup clock MSI = 16 MHz
2.14 2.90
2.78 3.58
Wakeup clock HSI16 = 16 MHz
To Run mode
1.99
-
Wakeup time from
tWUSTOP0 Stop 0 mode in Flash
memory(2)
Wakeup clock HSI16 = 16 MHz
(Range 1)
1.01 1.13
µs
with HSIKERON enabled
Wakeup clock MSI = 4 MHz
6.79 8.21
10.4 12.2
10.5 12.3
5.15 6.55
5.73 7.14
5.71 7.10
Wakeup clock MSI = 2 MHz
To LPRun mode Wakeup clock MSI = 2 MHz
Wakeup clock MSI = 48 MHz
Wakeup clock MSI = 16 MHz
Wakeup clock HSI16 = 16 MHz
To Run mode
Wakeup time from
tWUSTOP1 Stop 1 mode in Flash
memory(2)
Wakeup clock HSI16 = 16 MHz
with HSIKERON enabled
(Range 1)
4.57 6.52
µs
Wakeup clock MSI = 4 MHz
Wakeup clock MSI = 2 MHz
8.43 9.93
11.9 13.7
10.6 13.9
5.56 6.85
6.32 7.59
6.28 7.51
To LPRun mode Wakeup clock MSI = 2 MHz
Wakeup clock MSI = 48 MHz
Wakeup clock MSI = 16 MHz
Wakeup clock HSI16 = 16 MHz
To Run mode
Wakeup clock HSI16 = 16 MHz
(Range 1)
Wakeup time from
tWUSTOP2 Stop 2 mode in Flash
memory(2)
µs
µs
6.26 7.53
with HSIKERON enabled
Wakeup clock MSI = 4 MHz
Wakeup clock MSI = 2 MHz
9.69 10.9
14.0 15.4
34.3 39.2
22.4 25.6
Wakeup clock MSI = 4 MHz
Range 1
Wakeup time from
tWUSTBY
Standby to Run mode
Wakeup clock MSI = 8 MHz
Wakeup time from
tWUSHUTD
Range 1
Wakeup clock MSI = 4 MHz
264
316
Shutdown to Run mode
1. Guaranteed by characterization results (VDD = 3 V, T = 25 °C).
2. Wakeup time is equivalent when code is executed from SRAM1 compared to Flash memory. It is also equivalent when
going to Range 2 rather than Range 1.
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(1)
Table 55. Regulator modes transition times
Parameter Conditions
Typ
Max
Unit
Transition time from LPRun to Run
mode(2)
tWULPRUN
Code run with MSI = 2 MHz
19.6
-
Regulator transition time from Range 2 to
Range 1(3)
21.9
23.1
32.2
33.9
µs
tVOST
Code run with HSI16
Regulator transition time from Range 1 to
Range 2(3)
1. Guaranteed by characterization results (VDD = 3 V, T = 25 °C).
2. Time until REGLPF flag is cleared in PWR_SR2.
3. Time until VOSF flag is cleared in PWR_SR2.
5.3.9
External clock source characteristics
High-speed external user clock generated from an external source
The high-speed external (HSE32) clock can be supplied with a 32 MHz crystal oscillator or
by a TCXO (temperature controlled crystal oscillator).
Crystal oscillator
The devices include internal programmable capacitances that can be used to tune the
crystal frequency in order to compensate the PCB parasitic one.
Characteristics in the tables below, are measured over recommended operating conditions,
unless otherwise specified. Typical values are referred to T = 25 °C and V = 3 V.
A
DD
(1)
Table 56. HSE32 crystal requirements
Conditions
Symbol
Parameter
Min
Typ
Max Unit
fnom
Oscillator frequency
-
-
-
32
-
-
MHz
Initial
±10
fTOL
Frequency accuracy
Over temperature (-20 to 70 °C)
-
-
±10 ppm
±10
Aging over 10 years
-
-
-
CLoad Load capacitance(2)
9.5
0.3
1.3
10
0.6
1.89
10.5
pF
2
CShunt Crystal shunt capacitance
Cmotion Crystal motional capacitance
-
-
2.5
60
fF
Ω
Crystal equivalent series
resistance
ESR
-
-
-
-
30
-
PD
Drive level
100
µW
1. 32 MHz XTAL is specified for two specific references: NX2016SA and NX1612SA.
2. Load capacitance can be managed by internal programmable capacitances at calibration phase. No need to add external
foot capacitances. The values indicated take into account the combination of the two foot capacitances.
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Table 57. HSE32 oscillator characteristics
Conditions
Symbol
Parameter
Min
Typ
Max Unit
VDDRF stabilized,
SUBGHZ_HSEINTRIMR = 0x12,
-40 to +105 °C temperature range
Startup time for 80% amplitude
stabilization
tSUA(HSE)
-
1000
-
µs
VDDRF stabilized,
Startup time
for HSEREADY signal
tSUR(HSE)
SUBGHZ_HSEINTRIMR = 0x12,
-40 to +105 °C temperature range
-
180
-
HSEGMC = 000,
SUBGHZ_HSEINTRIMR = 0x12
IDDRF(HSE) HSE32 current consumption
-
50
1
-
5
µA
SUBGHZ_HSEINTRIMR
XOTg(HSE)
-
granularity
ppm
SUBGHZ_HSEINTRIMR
XOTfp(HSE)
±15
±30
6
-
frequency pulling
Capacitor bank
SUBGHZ_HSEINTRIMR
XOTnb(HSE)
-
-
-
bit
number of tuning bits
SUBGHZ_HSEINTRIMR setting
XOTst(HSE)
time
-
0.1
ms
For more information about the trimming methodology of the oscillator, refer to the
application note HSE trimming for STM32 wireless MCUs (AN5042).
TCXO regulator
Table 58. HSE32 TCXO regulator characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Regulated voltage range for
TCXO voltage supply
VTCXO
VDDOP > VTCXO + 200 mV
1.6
1.7
1.5
-
3.3
4
V
ILTCXO
Load current for TCXO regulator -
-
-
mA
µs
From enable to regulated voltage
within 25 mV from target
TSVTCXO Startup time for TCXO regulator
50
Quiescent current
-
-
-
70
2
µA
%
Current consumption for TCXO
IDDTCXO
regulator
Relative to load current
1.6
Provided through a 220 Ω resistor
in series with a capacitance
(voltage divider)(1)
Amplitude voltage for external
ATCXO
0.4
0.6
1.2
Vpk-pk
TCXO applied to OSC_IN pin
1. In order to minimize spurious injection, the capacitance value must be calculated such that an amplitude of
0.4 to 0.5 Vpk-pk on OSC_IN is obtained. For TCXO output voltage of 0.8 Vpk-pk, 10 pF can be used.
Low-speed external user clock generated from an external source
The low-speed external (LSE) clock can be supplied with a 32.768 kHz crystal resonator
oscillator. The information provided in this section is based on design simulation results
obtained with typical external components specified in the table below. In the application,
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the resonator and the load capacitors have to be placed as close as possible to the
oscillator pins to minimize output distortion and startup stabilization time.
Refer to the crystal resonator manufacturer for more details on the resonator characteristics
(frequency, package, accuracy).
(1)
Table 59. Low-speed external user clock characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
LSEDRV[1:0] = 00 - Low drive capability
LSEDRV[1:0] = 01 - Medium-low drive capability
LSEDRV[1:0] = 10 - Medium-high drive capability
LSEDRV[1:0] = 11 - High drive capability
LSEDRV[1:0] = 00 - Low drive capability
LSEDRV[1:0] = 01 - Medium-low drive capability
LSEDRV[1:0] = 10 - Medium-high drive capability
LSEDRV[1:0] = 11 - High drive capability
VDD stabilized
-
-
-
-
-
-
-
-
-
250
-
315
-
-
LSE current
consumption
IDD(LSE)
nA
500
630
-
-
-
0.50
0.75
1.70
2.70
-
Maximum
Gmcritmax critical crystal
gm
µA/V
s
-
-
(2)
tSU(LSE)
Startup time
2
1. Guaranteed by design.
2. tSU(LSE) is the startup time measured from the moment it is enabled (by software) until a stable 32.768 kHz oscillation is
reached. This value is measured for a standard crystal and it can vary significantly with the crystal manufacturer.
For more information on the crystal selection, refer to application note Oscillator design
guide for STM8AF/AL/S, STM32 MCUs and MPUs (AN2867).
Figure 16. Typical application with a 32.768 kHz crystal
Resonator with integrated
capacitors
CL1
OSC32_IN
fLSE
Drive
32.768 kHz
resonator
programmable
amplifier
OSC32_OUT
CL2
MS30253V2
Note:
No external resistors are required between OSC32_IN and OSC32_OUT, and it is forbidden
to add one.
In bypass mode, the LSE oscillator is switched off and the input pin is a standard GPIO.
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The external clock signal has to respect the I/O characteristics detailed in Section 5.3.16:
I/O port characteristics.The recommend clock input waveform is shown in the figure below.
Figure 17. Low-speed external clock source AC timing diagram
t
w(LSEH)
V
LSEH
90%
10%
V
LSEL
t
t
t
r(LSE)
f(LSE)
t
w(LSEL)
T
LSE
MS19215V2
(1)
Table 60. Low-speed external user clock characteristics – Bypass mode
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
User external clock source
frequency
fLSE_ext
VLSEH
VLSEL
-
21.2
32.768
44.4
kHz
OSC32_IN input pin high-
level voltage
0.7 x
VDDx
-
-
-
-
-
-
VDDx
V
OSC32_IN input pin low-
level voltage
VSS
250
0.3 x VDDx
-
tw(LSEH)
tw(LSEL)
OSC32_IN high or low time
Frequency tolerance
ns
Includes initial accuracy,
stability over temperature,
aging and frequency pulling
ftolLSE
–500
-
+500
ppm
1. Guaranteed by design.
5.3.10
Internal clock source characteristics
Parameters given in the table below are derived from tests performed under ambient
temperature and supply voltage conditions summarized in Table 25: General operating
conditions. The provided curves are characterization results, not tested in production.
High-speed internal (HSI16) RC oscillator
(1)
Table 61. HSI16 oscillator characteristics
Symbol
fHSI16
Parameter
HSI16 frequency
Conditions
Min
Typ
Max
Unit
VDD = 3.0 V, TA = 30 °C 15.88
-
16.08 MHz
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Electrical characteristics
(1)
Table 61. HSI16 oscillator characteristics (continued)
Parameter
Conditions
Min
Typ
Max
Unit
Trimming code is not a
multiple of 48
0.2
0.3
0.4
TRIM
HSI16 user trimming step
Duty cycle
Trimming code is a
multiple of 48
–4
45
–6
-
–8
55
DuCy(HSI16)
%
-
(2)
Tj = 0 to 85 °C
–1
-
-
1
1.5
0.05
1.2
5
ꢀTemp(HSI16) HSI16 oscillator frequency drift
Tj = -40 to 125 °C
–2
ꢀVDD(HSI16) HSI16 oscillator frequency drift over VDD VDD = 1.8 V to 3.6 V
–0.1
-
tsu(HSI16)(2) HSI16 oscillator start-up time
tstab(HSI16)(2) HSI16 oscillator stabilization time
IDD(HSI16)(2) HSI16 oscillator power consumption
-
-
-
-
-
-
0.8
3
μs
155
190
μA
1. Guaranteed by characterization results.
2. Guaranteed by design.
Figure 18. HSI16 frequency versus temperature
MHz
16.4
+2 %
+1.5 %
+1 %
16.3
16.2
16.1
16
15.9
15.8
15.7
15.6
-1 %
-1.5 %
-2 %
-40
-20
0
20
40
60
80
100
120 °C
MSv66006V3
Mean
Min
Max
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Multi-speed internal (MSI) RC oscillator
(1)
Table 62. MSI oscillator characteristics
Parameter Conditions
Symbol
Min
Typ
Max Unit
Range 0
Range 1
Range 2
Range 3
Range 4
Range 5
Range 6
Range 7
Range 8
Range 9
Range 10
Range 11
Range 0
Range 1
Range 2
Range 3
Range 4
Range 5
Range 6
Range 7
Range 8
Range 9
Range 10
Range 11
Tj = 0 to 85 °C
98.7
100
200
101.3
197.4
202.6
kHz
405.2
394.8
400
789.6
800
810.4
1.013
2.026
4.052
0.987
1
1.974
2
MSI mode
3.948
4
7.896
8
8.104
MHz
16.21
15.79
16
23.69
24
24.31
32.42
48.62
-
31.58
32
MSI frequency
after factory
calibration, done
at VDD= 3 V and
TA= 30 °C
47.38
48
fMSI
-
98.304
196.608
393.216
786.432
1.016
1.999
3.998
7.995
15.991
23.986
32.014
48.005
-
-
-
kHz
-
-
-
-
-
-
-
-
PLL mode
XTAL=
32.768 kHz
-
-
-
-
MHz
-
-
-
-
-
-
-
-
MSI oscillator
–3.5
3
ꢀTEMP(MSI)(2) frequency drift
MSI mode
%
6
Tj = -40 to 125 °C
–8
-
over temperature
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Symbol
Electrical characteristics
(1)
Table 62. MSI oscillator characteristics (continued)
Parameter
Conditions
Min
Typ
Max Unit
VDD
1.8 to 3.6 V
=
–1.2
-
Range 0 to 3
0.5
VDD
2.4 to 3.6 V
=
–0.5
–2.5
–0.8
–5
-
-
-
-
-
VDD
1.8 to 3.6 V
=
MSI oscillator
frequency drift
over VDD
ꢀVDD(MSI)(2)
MSI mode Range 4 to 7
0.7
VDD
2.4 to 3.6 V
=
(reference is 3 V)
%
VDD
1.8 to 3.6 V
=
Range 8 to 11
1
VDD
2.4 to 3.6 V
=
–1.6
Frequency
Tj = -40 to 85 °C
Tj = -40 to 125 °C
-
-
1
2
2
4
ꢀFSAMPLING
variation in
MSI mode
(MSI)(2)(4)
sampling mode(3)
RMS cycle-to-
cycle jitter
CC jitter(MSI)(4)
PLL mode Range 11
-
-
60
-
ps
P jitter(MSI)(4) RMS period jitter PLL mode Range 11
-
-
-
-
-
-
-
-
-
-
-
-
-
-
50
10
5
-
Range 0
Range 1
20
10
Range 2
4
8
MSI oscillator
start-up time
t
SU(MSI)(4)
μs
7
Range 3
3
Range 4 to 7
Range 8 to 11
3
6
6
2.5
10 % of final
frequency
-
-
-
-
-
-
0.25
0.5
-
0.5
MSI oscillator
stabilization time Range 11
PLL mode 5 % of final
tSTAB(MSI)(4)
1.25 ms
2.5
frequency
1 % of final
frequency
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(1)
Table 62. MSI oscillator characteristics (continued)
Symbol
Parameter
Conditions
Range 0
Min
Typ
Max Unit
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0.6
0.8
1.2
1.9
4.7
6.5
11
1
Range 1
Range 2
Range 3
Range 4
Range 5
Range 6
Range 7
Range 8
Range 9
Range 10
Range 11
1.2
1.7
2.5
6
MSI oscillator
power
consumption
9
MSI and
PLL mode
IDD(MSI)(4)
µA
15
18.5
62
25
80
85
110
130
190
110
155
1. Guaranteed by characterization results.
2. This is a deviation for an individual part once the initial frequency has been measured.
3. Sampling mode means LPRun and LPSleep modes with temperature sensor disabled.
4. Guaranteed by design.
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Figure 19. Typical current consumption vs. MSI frequency
Low-speed internal (LSI) RC oscillator
(1)
Table 63. LSI oscillator characteristics
Parameter Conditions
VDD = 3 V, TA = 30 °C
Symbol
Min Typ Max Unit
31.04
-
-
32.96
34
fLSI
LSI frequency
kHz
VDD = 1.8 to 3.6 V, Tj = -40 to 125 °C
-
29.5
tSU(LSI)(2) LSI oscillator startup time
-
-
80
130
μs
tSTAB(LSI)(2) LSI oscillator stabilization time 5 % of final frequency
125 180
110 180
LSI oscillator power
consumption
IDD(LSI)(2)
-
-
nA
1. Guaranteed by characterization results.
2. Guaranteed by design.
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5.3.11
PLL characteristics
Parameters given in the table below are derived from tests performed under temperature
and V supply voltage conditions summarized in Table 25: General operating conditions.
DD
(1)
Table 64. PLL characteristics
Symbol
fPLL_IN
Parameter
PLL input clock(2)
PLL input clock duty cycle
Conditions
Min
Typ Max Unit
-
-
2.66
45
3
-
-
16
55
48
16
48
16
48
16
344
128
40
-
MHz
%
Voltage scaling Range 1
Voltage scaling Range 2
Voltage scaling Range 1
Voltage scaling Range 2
Voltage scaling Range 1
Voltage scaling Range 2
Voltage scaling Range 1
Voltage scaling Range 2
-
-
fPLL_P_OUT PLL multiplier output clock P
fPLL_Q_OUT PLL multiplier output clock Q
fPLL_R_OUT PLL multiplier output clock R
fVCO_OUT PLL VCO output
3
-
12
12
12
12
96
96
-
-
-
MHz
-
-
-
-
tLOCK
Jitter
PLL lock time
15
40
30
μs
RMS cycle-to-cycle jitter
RMS period jitter
-
System clock 48 MHz
ps
-
-
VCO freq = 96 MHz
VCO freq = 192 MHz
VCO freq = 344 MHz
-
200 260
300 380
520 650
PLL power consumption on
VDD
I
DD(PLL)
-
μA
(1)
-
1. Guaranteed by design.
2. Take care of using the appropriate division factor M to obtain the specified PLL input clock values. The M factor is shared
between the two PLLs.
5.3.12
Flash memory characteristics
(1)
Table 65. Flash memory characteristics
Symbol
Parameter
64-bit programming time
Conditions
Typ
Max
Unit
tprog
-
81.7
90.8
µs
Normal
programming
One row (64 double-words) programming time
5.2
3.8
5.5
4.0
tprog_row
Fast programming
Normal
programming
41.8
43.0
ms
tprog_page One 2-Kbyte page programming time
Fast programming
30.4
22.0
22.1
31.0
24.5
25.0
tERASE
tME
2-Kbyte page erase time
Mass erase time
-
-
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Electrical characteristics
(1)
Table 65. Flash memory characteristics (continued)
Parameter Conditions
Write mode
Typ
Max
Unit
3.4
-
-
-
-
Average consumption from VDD
Erase mode
Write mode
Erase mode
3.4
IDD
mA
7 (for 6 µs)
7 (for 67 µs)
Maximum current (peak)
1. Guaranteed by design.
Table 66. Flash memory endurance and data retention
Conditions
Symbol
Parameter
Endurance
Min(1)
Unit
NEND
TA = -40 to +105 °C
10
30
15
30
15
10
kcycles
1 kcycle(2) at TA = 85 °C
1 kcycle(2) at TA = 105 °C
tRET
Data retention
10 kcycles(2) at TA = 55 °C
10 kcycles(2) at TA = 85 °C
10 kcycles(2) at TA = 105 °C
Years
1. Guaranteed by characterization results.
2. Cycling performed over the whole temperature range.
5.3.13
EMC characteristics
Susceptibility tests are performed on a sample basis during device characterization.
Functional EMS (electromagnetic susceptibility)
While a simple application is executed on the device (toggling two LEDs through I/O ports).
the device is stressed by the following electromagnetic events until a failure occurs (failure
indicated by the LEDs):
•
ESD (electrostatic discharge, positive and negative) applied to all device pins until a
functional disturbance occurs (test compliant with IEC 61000-4-2 standard)
•
FTB (burst of fast transient voltage, positive and negative) applied to VDD and VSS
pins, through a 100 pF capacitor, until a functional disturbance occurs (test compliant
with IEC 61000-4-4 standard)
A device reset allows normal operations to be resumed.
The test results given in the table below, are based on the EMS levels and classes defined
in application note EMC design guide for STM8, STM32 and Legacy MCUs (AN1709).
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Level/Class
Table 67. EMS characteristics
Conditions
Voltage limits to be applied on any I/O pin to VDD = 3.3 V, TA = +25 °C, fHCLK = 48 MHz,
Symbol
Parameter
VFESD
2B
5A
induce a functional disturbance
conforming to IEC 61000-4-2
Fast transient voltage burst limits to be
VEFTB applied through 100 pF on VDD and VSS
pins to induce a functional disturbance
VDD = 3.3 V, TA = +25 °C, fHCLK = 48 MHz,
conforming to IEC 61000-4-4
Designing hardened software to avoid noise problems
EMC characterization and optimization are performed at component level with a typical
application environment and simplified MCU software.
Note:
Good EMC performance is highly dependent on the user application and the software in
particular.It is then recommended that the user applies EMC software optimization and
prequalification tests in relation with the EMC level requested for the application.
Software recommendations
The software flow must include the management of runaway conditions such as:
•
•
•
corrupted program counter
unexpected reset
critical data corruption (control registers)
Prequalification trials
Most of the common failures (unexpected reset and program counter corruption) can be
reproduced by manually forcing a low state on the NRST pin or the oscillator pins for 1 s.
To complete these trials, ESD stress can be applied directly on the device, over the range of
specification values. When unexpected behavior is detected, the software can be hardened
to prevent unrecoverable errors occurring. For more details, refer to the application note
Software techniques for improving microcontrollers EMC performance (AN1015).
Electromagnetic interference (EMI)
The electromagnetic field emitted by the device is monitored while a simple application is
executed (toggling two LEDs through the I/O ports). This emission test is compliant with the
IEC 61967-2 standard, that specifies the test board and the pin loading.
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Symbol Parameter
Electrical characteristics
Table 68. EMI characteristics
Monitored
Peripheral ON
SMPS OFF
fHSE = /fCPUM4, fCPUM0
]
Conditions
Unit
frequency band
fHSE = 32 MHz
fCPU = 48 MHz
0.1 MHz to 30 MHz
30 MHz to 130 MHz
130 MHz to 1 GHz
1 GHz to 2 GHz
EMI level
1
4
0
7
2
V
DD = 3.6 V, TA = 25 °C,
Peak level UFBGA73 package
compliant with IEC 61967-2
dBµV
-
SEMI
5.3.14
Electrical sensitivity characteristics
Based on three different tests (ESD, LU) using specific measurement methods, the device is
stressed to determine its performance in terms of electrical sensitivity.
Electrostatic discharge (ESD)
Electrostatic discharges (a positive then a negative pulse separated by 1 s) are applied to
the pins of each sample according to each pin combination. The sample size depends on
the number of supply pins in the device (3 parts × (n+1) supply pins). This test conforms to
the ANSI/JEDEC standard.
Table 69. ESD absolute maximum ratings
Symbol
VESD(HBM)
Ratings
Conditions
Class Maximum value(1) Unit
Electrostatic discharge voltage TA = +25 °C, conforming to
(human body model)
2
2000
500
ANSI/ESDA/JEDEC JS-001
V
Electrostatic discharge voltage TA = +25 °C, conforming to
(charge device model)
VESD(CDM)
C2a
ANSI/ESD STM5.3.1 JS-002
1. Guaranteed by characterization results.
Static latch-up
The following complementary static tests are required on three parts to assess the latch-up
performance:
•
•
A supply overvoltage is applied to each power supply pin.
A current injection is applied to each input, output and configurable I/O pin.
These tests are compliant with EIA/JESD 78A IC latch-up standard.
Table 70. Electrical sensitivities
Symbol
Parameter
Conditions
Class
LU
Static latch-up class
TA = +105 °C conforming to JESD78A
Level A
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5.3.15
I/O current injection characteristics
As a general rule, current injection to the I/O pins, due to external voltage below V or
SS
above V (for standard, 3V-capable I/O pins), must be avoided during normal product
DD
operation. However, in order to give an indication of the robustness of the microcontroller in
case abnormal injection accidentally happens, susceptibility tests are performed on a
sample basis during device characterization.
Functional susceptibility to I/O current injection
While a simple application is executed on the device, the device is stressed by injecting
current into the I/O pins programmed in floating-input mode. While current is injected into
the I/O pin, one at a time, the device is checked for functional failures.
The failure is indicated by an out-of-range parameter: ADC error above a certain limit
(higher than 5 LSB TUE), out of conventional limits of induced leakage current on adjacent
pins (out of the -5 µA/0 µA range) or other functional failure (for example reset occurrence
or oscillator frequency deviation).
The characterization results are given in the table below.
Negative induced leakage current is caused by negative injection and positive induced
leakage current is caused by positive injection.
(1)
Table 71. I/O current injection susceptibility
Functional susceptibility
Symbol
Description
Unit
Negative
injection
Positive
injection
Injected current on all pins except PB0
Injected current on PB0 pin
–5
–5
N/A(2)
0
IINJ
mA
1. Guaranteed by characterization results.
2. Injection not possible.
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5.3.16
I/O port characteristics
General input/output characteristics
Unless otherwise specified, the parameters given in the table below are derived from tests
performed under the conditions summarized in Table 25: General operating conditions. All
I/Os are designed as CMOS- and TTL-compliant.
Table 72. I/O static characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
I/O input low-level voltage(1)
-
-
0.3 x VDD
VIL
0.39 x VDD
- 0.06
I/O input low-level voltage(2)
I/O input high-level voltage(1)
I/O input high-level voltage(2)
V
0.7 x VDD
-
-
-
-
1.8 V < VDD < 3.6 V
VIH
0.49 x VDD
+ 0.26
TT, FT_xx and NRST I/O
input hysteresis
Vhys
-
-
-
200
-
mV
nA
(3)(4)
0 ≤ VIN ≤ Max(VDDXXX
)
-
-
±100
650
Max(VDDXXX) ≤ VIN
≤
FT_xx input leakage current Max(VDDXXX) +1 V(2)(3)(4)
Ilkg
Max(VDDXXX) +1 V < VIN
5.5 V(2)(3)(4)(5)(6)
≤
-
-
200(7)
(3)
V
IN ≤ Max(VDDXXX
)
-
-
-
-
±150
2000
TT input leakage current
Max(VDDXXX) ≤ VIN < 3.6 V(3)
Weak pull-up equivalent
resistor(1)
RPU
VIN = VSS
25
40
55
kꢁ
Weak pull-down equivalent
resistor(1)
RPD
CIO
VIN = VDD
25
-
40
5
55
-
I/O pin capacitance
-
pF
1. Tested in production.
2. Guaranteed by design, not tested in production.
3. Represents the pad leakage of the I/O itself. The total product pad leakage is given by
ITotal_Ileak_max = 10 μA + number of I/Os where VIN is applied on the pad x Ilkg(Max)
4. Max(VDDXXX) is the maximum value among all the I/O supplies.
5. VIN must be lower than [Max(VDDXXX) + 3.6 V].
.
6. Refer to the figure below.
7. To sustain a voltage higher than [Min(VDD, VDDA) + 0.3 V], the internal pull-up and pull-down resistors must be disabled on
all FT_xx I/O.
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All I/Os are CMOS- and TTL-compliant (no software configuration required). Their
characteristics cover more than the strict CMOS-technology or TTL parameters, as shown
in the figure below.
Figure 20. I/O input characteristics - V and V on all I/Os
IL
IH
VIH spec 70 %
VIL spec 30 %
VIH rule
VIL rule
VIH spec TTL
VIL spec TTL
MSv64346V1
Output driving current
The GPIOs can sink or source up to ±8 mA, and sink or source up to ± 20 mA (with a
relaxed V /V ).
OL OH
In the user application, the number of I/O pins that can drive current must be limited to
respect the absolute maximum rating specified in Section 5.2: Absolute maximum ratings.
The sum of the currents sourced by all the I/Os on V , plus the maximum consumption of
DD
the MCU sourced on V
cannot exceed the absolute maximum rating ΣI
(see
DD,
VDD
Table 21: Voltage characteristics).
The sum of the currents sunk by all the I/Os on V , plus the maximum consumption of the
SS
MCU sunk on V , cannot exceed the absolute maximum rating ΣI
(see Table 21:
VSS
SS
Voltage characteristics).
Output voltage levels
Unless otherwise specified, the parameters given in the table below are derived from tests
performed under the ambient temperature and supply voltage conditions summarized in
Table 25: General operating conditions. All I/Os are CMOS- and TTL-compliant (FT or TT
unless otherwise specified).
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(1)
Table 73. Output voltage characteristics
Parameter Conditions
Output low-level voltage for an I/O pin
Symbol
Min
Max Unit
(2)
CMOS port(3)
VOL
VOH
-
0.4
-
(2)
|IIO| = 8 mA, VDD ≥ 2.7 V
Output high-level voltage for an I/O pin
Output low-level voltage for an I/O pin
Output high-level voltage for an I/O pin
Output low-level voltage for an I/O pin
Output high-level voltage for an I/O pin
Output low-level voltage for an I/O pin
Output high-level voltage for an I/O pin
VDD - 0.4
(2)
(2)
TTL port(3)
|IIO| = 8 mA, VDD ≥ 2.7 V
VOL
-
0.4
-
VOH
2.4
(2)
VOL
VOH
-
1.3
|IIO| = 20 mA, VDD ≥ 2.7 V
|IIO| = 4 mA, VDD ≥ 1.8 V
V
(2)
VDD - 1.3
-
(2)
VOL
-
0.4
-
(2)
VOH
VDD - 0.45
-
Output low-level voltage for an FT I/O |IIO| = 20 mA, VDD ≥ 2.7 V
0.4
(2)
VOLFM+
pin in FM+ mode
(FT I/O with “f” option)
|IIO| = 10 mA, VDD ≥ 1.8 V
-
0.4
1. The IIO current sourced or sunk by the device must always respect the absolute maximum rating specified in Table 21:
Voltage characteristics. The sum of the currents sourced or sunk by all the I/Os (I/O ports and control pins) must always
respect the absolute maximum ratings Σ IIO
.
2. Guaranteed by design.
3. TTL and CMOS outputs are compatible with JEDEC standards JESD36 and JESD52.
Input/output AC characteristics
Unless otherwise specified, the parameters given in the table below are derived from tests
performed under the ambient temperature and supply voltage conditions summarized in
Table 25: General operating conditions.
(1)(2)
Table 74. I/O AC characteristics
OSPEEDx[1:0](3)
Symbol
Parameter
Conditions
Min
Max
Unit
C = 50 pF, 2.7 V ≤ VDD ≤ 3.6 V
C = 50 pF, 1.8 V ≤ VDD ≤ 2.7 V
C = 10 pF, 2.7 V ≤ VDD ≤ 3.6 V
C = 10 pF, 1.8 V ≤ VDD ≤ 2.7 V
C = 50 pF, 2.7 V ≤ VDD ≤ 3.6 V
C = 50 pF, 1.8 V ≤ VDD ≤ 2.7 V
C = 10 pF, 2.7 V ≤ VDD ≤ 3.6 V
C = 10 pF, 1.8 V ≤ VDD ≤ 2.7 V
-
-
-
-
-
-
-
-
5
1
Maximum
frequency
Fmax
MHz
10
1.5
25
52
17
37
0b00
Output rise and
fall time
Tr/Tf
ns
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STM32WLE5/E4xx
(1)(2)
Table 74. I/O AC characteristics
(continued)
OSPEEDx[1:0](3)
Symbol
Parameter
Conditions
Min
Max
Unit
C = 50 pF, 2.7 V ≤ VDD ≤ 3.6 V
C = 50 pF, 1.8 V ≤ VDD ≤ 2.7 V
C = 10 pF, 2.7 V ≤ VDD ≤ 3.6 V
C = 10 pF, 1.8 V ≤ VDD ≤ 2.7 V
C = 50 pF, 2.7 V ≤ VDD ≤ 3.6 V
C = 50 pF, 1.8 V ≤ VDD ≤ 2.7 V
C = 10 pF, 2.7 V ≤ VDD ≤ 3.6 V
C = 10 pF, 1.8 V ≤ VDD ≤ 2.7 V
C = 50 pF, 2.7 V ≤ VDD ≤ 3.6 V
C = 50 pF, 1.8 V ≤ VDD ≤ 2.7 V
C = 10 pF, 2.7 V ≤ VDD ≤ 3.6 V
C = 10 pF, 1.8 V ≤ VDD ≤ 2.7 V
C = 50 pF, 2.7 V ≤ VDD ≤ 3.6 V
C = 50 pF, 1.8 V ≤ VDD ≤ 2.7 V
C = 10 pF, 2.7 V ≤ VDD ≤ 3.6 V
C = 10 pF, 1.8 V ≤ VDD ≤ 2.7 V
C = 30 pF, 2.7 V ≤ VDD ≤ 3.6 V
C = 30 pF, 1.8 V ≤ VDD ≤ 2.7 V
C = 10 pF, 2.7 V ≤ VDD ≤ 3.6 V
C = 10 pF, 1.8 V ≤ VDD ≤ 2.7 V
C = 30 pF, 2.7 V ≤ VDD ≤ 3.6 V
C = 30 pF, 1.8 V ≤ VDD ≤ 2.7 V
C = 10 pF, 2.7 V ≤ VDD ≤ 3.6 V
C = 10 pF, 1.8 V ≤ VDD ≤ 2.7 V
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
25
10
Maximum
frequency
Fmax
MHz
50
15
0b01
9
16
Output rise and
fall time
Tr/Tf
Fmax
Tr/Tf
Fmax
Tr/Tf
ns
MHz
ns
4.5
9
50
25
Maximum
frequency
100(4)
37.5
5.8
11
0b10
Output rise and
fall time
2.5
5
120(4)
50
Maximum
frequency
MHz
180(4)
75(4)
3.3
6
0b11
Output rise and
fall time
ns
1.7
3.3
1. The maximum frequency is defined with (Tr+ Tf) ≤ 2/3 T, and duty cycle comprised between 45 and 55 %.
2. The fall and rise time are defined, respectively, between 90 and 10 %, and between 10 and 90 % of the output waveform.
3. OSPEED0[1:0] in GPIOA_OSPEEDR, GPIOB_OSPEEDR and GPIOC_OSPEEDR. OSPEED3[1:0] in GPIOH_OSPEEDR
4. This value represents the I/O capability but the maximum system frequency is limited to 48 MHz.
5.3.17
NRST pin characteristics
The NRST pin input driver uses the CMOS technology. It is connected to a permanent
pull-up resistor, R
.
PU
Unless otherwise specified, the parameters given in the table below are derived from tests
performed under the ambient temperature and supply voltage conditions summarized in
Table 25: General operating conditions.
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Symbol
Electrical characteristics
(1)
Table 75. NRST pin characteristics
Parameter
Conditions
Min
Typ
Max
Unit
VIL(NRST) NRST input low level voltage
VIH(NRST) NRST input high level voltage
Vhys(NRST) NRST Schmitt trigger voltage hysteresis
-
-
-
-
0.3 x VDD
V
-
0.7 x VDD
-
-
-
-
25
-
200
40
-
mV
RPU
Weak pull-up equivalent resistor(2)
VIN = VSS
55
70
-
kꢁ
VF(NRST) NRST input, filtered pulse
VNF(NRST) NRST input, not filtered pulse
1. Guaranteed by design.
-
ns
1.8 V ≤ VDD ≤ 3.6 V
350
-
2. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution to the series
resistance is minimal (~10 %).
Figure 21. Recommended NRST pin protection
External
reset circuit(1)
VDD
RPU
NRST(2)
Internal reset
Filter
0.1 μF
MS19878V3
1. The reset network protects the device against parasitic resets.
2. The user must ensure that the level on the NRST pin can go below the VIL(NRST) max level specified in the above table.
Otherwise the reset is not be taken into account by the device.
3. The external capacitor on NRST must be placed as close as possible to the device.
5.3.18
Analog switches booster
(1)
Table 76. Analog switches booster characteristics
Symbol
VDD
tSU(BOOST) Booster startup time
Booster consumption for 1.8 V ≤ VDD ≤ 2.0 V
Parameter
Min
Typ
Max
Unit
Supply voltage
1.8
-
-
-
-
-
3.6
240
250
500
900
V
-
-
-
-
µs
IDD(BOOST) Booster consumption for 2.0 V ≤ VDD ≤ 2.7 V
Booster consumption for 2.7 V ≤ VDD ≤ 3.6 V
1. Guaranteed by design.
µA
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STM32WLE5/E4xx
5.3.19
Analog-to-digital converter characteristics
Unless otherwise specified, the parameters given in the table below are preliminary values
derived from tests performed under ambient temperature, f
frequency and V
supply
PCLK
DDA
voltage conditions summarized in Table 25: General operating conditions.
Note:
It is recommended to perform a calibration after each power-up.
(1)
Table 77. ADC characteristics
Symbol
Parameter
Conditions(2)
Min
Typ
Max
Unit
VDDA
Analog supply voltage
-
1.62
2
-
3.6
V
DDA ≥ 2 V
-
VDDA
V
Positive reference
voltage
VREF+
VDDA < 2 V
VDDA
Range 1
0.14
-
-
-
-
-
-
-
-
-
-
35
fADC
ADC clock frequency
MHz
Range 2
0.14
16
12 bits, VDDA > 2 V
10 bits, VDDA > 2 V
8 bits, VDDA > 2 V
6 bits, VDDA > 2 V
12 bits, VDDA ≤ 2 V
10 bits, VDDA ≤ 2 V
8 bits, VDDA ≤ 2 V
6 bits, VDDA ≤ 2 V
-
-
-
-
-
-
-
-
2.50
2.92
3.50
4.38
2.18
2.50
2.92
3.50
fs
Sampling rate
Msps
f
ADC = 35 MHz,
-
-
-
-
2.35
2.18
12 bits, VDDA > 2 V
fADC = 35 MHz,
External trigger
frequency
fTRIG
MHz
12 bits, VDDA ≤ 2 V
12 bits, VDDA > 2 V
12 bits, VDDA ≤ 2 V
-
-
-
-
fADC/15
fADC/17
Conversion voltage
range
VAIN
RAIN
CADC
tSTAB
-
-
-
-
VSS
-
-
VREF+
V
External input
impedance
-
-
50
-
kꢁ
pF
Internal sample and
hold capacitor
5
2
Conversion
cycle
ADC power-up time
Calibration time
f
ADC = 35 MHz
2.35
82
µs
tCAL
-
1/fADC
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Symbol
Electrical characteristics
(1)
Table 77. ADC characteristics
Parameter
Conditions(2)
CKMODE = 00
(continued)
Min
Typ
Max
Unit
2
-
6.5
12.5
3.5
-
3
1/fADC
CKMODE = 01
CKMODE = 10
CKMODE = 11
Trigger conversion
latency
tLATR
1/fPCLK
fADC = 35 MHz
0.043
1.5
4.59
µs
ts
Sampling time
-
-
160.5
1/fADC
ADC voltage regulator
start-up time
-
-
-
-
20
tADCVREG_STUP
µs
fADC = 35 MHz
Resolution = 12 bits
0.40
4.95
µs
Total conversion time
(including sampling
time)
tCONV
ts + 12.5 cycles for successive
approximation
Resolution = 12 bits
1/fADC
= 14 to 173
Laps of time allowed
between two
conversions without
rearm
tIDLE
-
-
-
µs
100
fs = 2.5 Msps
fs = 1 Msps
fs = 10 ksps
fs = 2.5 Msps
fs = 1 Msps
fs = 10 ksps
-
-
-
-
-
-
410
164
17
-
-
-
-
-
-
ADC consumption
from VDDA
IDDA(ADC)
µA
µA
65
ADC consumption
from VREF+
single ended mode
IDDV(ADC)
26
0.26
1. Guaranteed by design
2. I/O analog switch voltage booster must be enabled (BOOSTEN = 1 in the SYSCFG_CFGR1) when VDDA < 2.4 V and
disabled when VDDA ≥ 2.4 V.
Table 78. Maximum ADC R
values
AIN
Resolution
Sampling cycle at 35 MHz (ns)
Sampling time at 35 MHz (ns)
Max. RAIN(1)(2)(Ω)
1.5(3)
3.5
43
50
100
680
7.5
214
2200
4700
8200
15000
33000
50000
12.5
19.5
39.5
79.5
160.5
357
12 bits
557
1129
2271
4586
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STM32WLE5/E4xx
Table 78. Maximum ADC R
values (continued)
AIN
Resolution
Sampling cycle at 35 MHz (ns)
Sampling time at 35 MHz (ns)
Max. RAIN(1)(2)(Ω)
1.5(3)
3.5
43
100
214
357
557
1129
2271
4586
43
68
820
7.5
3300
5600
10000
22000
39000
50000
82
12.5
19.5
39.5
79.5
160.5
1.5(3)
3.5
10 bits
100
214
357
557
1129
2271
4586
43
1500
3900
6800
12000
27000
50000
50000
390
7.5
12.5
19.5
39.5
79.5
160.5
1.5(3)
3.5
8 bits
100
214
357
557
1129
2271
4586
2200
5600
10000
15000
33000
50000
50000
7.5
12.5
19.5
39.5
79.5
160.5
6 bits
1. Guaranteed by design.
2. I/O analog switch voltage booster must be enabled (BOOSTEN = 1 in the SYSCFG_CFGR1) when VDDA < 2.4 V and
disabled when VDDA ≥ 2.4 V.
3. Only allowed with VDDA > 2 V
(1)(2)(3)
Table 79. ADC accuracy
Symbol Parameter
Conditions(4)
Min Typ Max Unit
V
DDA = VREF+ = 3 V, fADC = 35 MHz, fs ≤ 2.5 Msps, TA = 25 °C
-
-
3
3
4
2 V < VDDA, VREF+ < 3.6 V,
fADC = 35 MHz; fs ≤ 2.5 Msps, TA = entire range
Total
6.5
ET
unadjusted
error
LSB
1.62 V < VDDA = VREF+ < 3.6 V, TA = entire range
Range 1: fADC = 35 MHz, fs ≤ 2.2 Msps
Range 2: fADC = 16 MHz, fs ≤ 1.1 Msps
-
3
7.5
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Symbol Parameter
Electrical characteristics
Min Typ Max Unit
(1)(2)(3)
Table 79. ADC accuracy
Conditions(4)
DDA = VREF+ = 3 V, fADC = 35 MHz, fs ≤ 2.5 Msps, TA = 25 °C
(continued)
V
-
-
1.5
2
2 V < VDDA, VREF+ < 3.6 V,
1.5 4.5
1.5 5.5
fADC = 35 MHz; fs ≤ 2.5 Msps, TA = entire range
EO
EG
Offset error
LSB
LSB
LSB
LSB
bit
1.62 V < VDDA = VREF+ < 3.6 V, TA = entire range
Range 1: fADC = 35 MHz, fs ≤ 2.2 Msps
Range 2: fADC = 16 MHz, fs ≤ 1.1 Msps
-
V
DDA = VREF+ = 3 V, fADC = 35 MHz, fs ≤ 2.5 Msps, TA = 25 °C
-
-
3
3
3.5
5
2 V < VDDA, VREF+ < 3.6 V,
fADC = 35 MHz, fs ≤ 2.5 Msps, TA = entire range
Gain error
1.62 V < VDDA = VREF+ < 3.6 V, TA = entire range
Range 1: fADC = 35 MHz, fs ≤ 2.2 Msps
Range 2: fADC = 16 MHz, fs ≤ 1.1 Msps
-
3
6.5
VDDA = VREF+ = 3 V, fADC = 35 MHz, fs ≤ 2.5 Msps, TA = 25 °C
-
-
1.2 1.5
1.2 1.5
2 V < VDDA, VREF+ < 3.6 V,
Differential fADC = 35 MHz, fs ≤ 2.5 Msps, TA = entire range
linearity error
ED
1.62 V < VDDA = VREF+ < 3.6 V,TA = entire range
Range 1: fADC = 35 MHz, fs ≤ 2.2 Msps
Range 2: fADC = 16 MHz, fs ≤ 1.1 Msps
-
1.2 1.5
VDDA = VREF+ = 3 V, fADC = 35 MHz, fs ≤ 2.5 Msps, TA = 25 °C
-
-
2.5
2.5
3
3
2 V < VDDA, VREF+ < 3.6 V,
Integral
linearity error
fADC = 35 MHz, fs ≤ 2.5 Msps, TA = entire range
EL
1.62 V < VDDA = VREF+ < 3.6 V, TA = entire range
Range 1: fADC = 35 MHz, fs ≤ 2.2 Msps
Range 2: fADC = 16 MHz, fs ≤ 1.1 Msps
-
2.5 3.5
V
DDA = VREF+ = 3 V, fADC = 35 MHz, fs ≤ 2.5 Msps, TA = 25 °C 10.1 10.2
-
-
2 V < VDDA, VREF+ < 3.6 V,
Effective
number of
bits
9.6 10.2
9.5 10.2
fADC = 35 MHz, fs ≤ 2.5 Msps, TA = entire range
ENOB
1.62 V < VDDA = VREF+ < 3.6 V, TA = entire range
Range 1: fADC = 35 MHz, fs ≤ 2.2 Msps
Range 2: fADC = 16 MHz, fs ≤ 1.1 Msps
-
VDDA = VREF+ = 3 V, fADC = 35 MHz, fs ≤ 2.5 Msps, TA = 25 °C 62.5 63
-
-
Signal-to-
noise and
distortion
ratio
2 V < VDDA, VREF+ < 3.6 V,
59.5 63
fADC = 35 MHz, fs ≤ 2.5 Msps, TA = entire range
dB
SINAD
1.62 V < VDDA = VREF+ < 3.6 V, TA = entire range
Range 1: fADC = 35 MHz, fs ≤ 2.2 Msps
Range 2: fADC = 16 MHz, fs ≤ 1.1 Msps
59
63
-
VDDA = VREF+ = 3 V, fADC = 35 MHz, fs ≤ 2.5 Msps, TA = 25 °C
63
60
64
64
-
-
2 V < VDDA, VREF+ < 3.6 V,
fADC = 35 MHz, fs ≤ 2.5 Msps, TA = entire range
Signal-to-
noise ratio
dB
SNR
1.62 V < VDDA = VREF+ < 3.6 V, TA = entire range
Range 1: fADC = 35 MHz, fs ≤ 2.2 Msps
Range 2: fADC = 16 MHz, fs ≤ 1.1 Msps
60
64
-
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133
Electrical characteristics
Symbol Parameter
STM32WLE5/E4xx
Min Typ Max Unit
(1)(2)(3)
Table 79. ADC accuracy
Conditions(4)
DDA = VREF+ = 3 V, fADC = 35 MHz, fs ≤ 2.5 Msps, TA = 25 °C
(continued)
V
-
-
-74 -73
-74 -70
2 V < VDDA, VREF+ < 3.6 V,
fADC = 35 MHz, fs ≤ 2.5 Msps, TA = entire range
Total
harmonic
distortion
dB
THD
1.62 V < VDDA = VREF+ < 3.6 V, TA = entire range
Range 1: fADC = 35 MHz, fs ≤ 2.2 Msps
Range 2: fADC = 16 MHz, fs ≤ 1.1 Msps
-
-74 -70
1. Based on characterization results, not tested in production.
2. ADC DC accuracy values are measured after internal calibration.
3. Injecting negative current on any analog input pin significantly reduces the accuracy of A-to-D conversion of signal on
another analog input. It is recommended to add a Schottky diode (pin to ground) to analog pins susceptible to receive
negative current.
4. I/O analog switch voltage booster enabled (BOOSTEN = 1 in the SYSCFG_CFGR1) when VDDA < 2.4 V and disabled when
DDA ≥ 2.4 V.
V
Figure 22. ADC accuracy characteristics
EG
Code
4095
(1) Example of an actual transfer curve
(2) Ideal transfer curve
4094
(3) End point correlation line
4093
ET
total unadjusted error: maximum deviation
between the actual and ideal transfer curves.
(2)
ET
EO
offset error: maximum deviation between the
first actual transition and the first ideal one.
(3)
7
(1)
6
5
4
3
2
1
EG gain error: deviation between the last ideal
transition and the last actual one.
EL
EO
ED
differential linearity error: maximum deviation
between actual steps and the ideal ones.
ED
EL integral linearity error: maximum deviation between
any actual transition and the end point correlation line.
1 LSB ideal
0
1
2
3
4
5
6
7
4093 4094 4095
(VAIN / VREF+)*4095
MSv19880V3
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DS13105 Rev 8
STM32WLE5/E4xx
Electrical characteristics
Figure 23. Typical connection diagram using the ADC
VDDA
VT
Sample and hold ADC converter
(1)
RAIN
RADC
AINx
12-bit
converter
(2)
(3)
Cparasitic
CADC
VT
Ilkg
VAIN
MS33900V5
1. Refer to Table 79: ADC accuracy for the values of RAIN, RADC and CADC
.
2. Cparasitic represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the pad capacitance
(refer to Table 72: I/O static characteristics for the value of the pad capacitance). A high Cparasitic value downgrades the
conversion accuracy. To remedy this, fADC must be reduced.
3. Refer to Table 72: I/O static characteristics for the values of Ilkg.
General PCB design guidelines
Power supply decoupling must be performed as shown in Figure 13: Power supply scheme.
The 100 nF capacitor must be ceramic (good quality) and must be placed as close as
possible to the chip.
5.3.20
Temperature sensor characteristics
Table 80. TS characteristics
Symbol
Parameter
Min
Typ
Max
Unit
(1)
TL
VTS linearity with temperature
-
±1
2.5
±2
2.7
°C
mV/°C
V
Avg_Slope(2) Average slope
2.3
V30
Voltage at 30 °C (±5 °C)(3)
0.742
0.76
0.785
tSTART
Sensor buffer startup time in continuous mode(4)
-
8
15
µs
(TS_BUF)(1)
Startup time when entering in continuous mode(4)
ADC sampling time when reading the temperature
-
70
-
120
-
µs
µs
(1)
tSTART
(1)
tS_temp
5
Temperature sensor consumption from VDD, when
selected by the ADC
I
DD(TS)(1)
-
4.7
7
µA
1. Guaranteed by design.
2. Guaranteed by characterization results.
3. Measured at VDDA = 3.3 V ±10 mV. The V30 ADC conversion result is stored in the TS_CAL1 byte. Refer to
Table 12: Temperature sensor calibration values.
4. Continuous mode means Run and Sleep modes, or temperature sensor enable in LPRun and LPSleep modes.
DS13105 Rev 8
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Electrical characteristics
STM32WLE5/E4xx
5.3.21
V
monitoring characteristics
BAT
(1)
Table 81. V
monitoring characteristics
BAT
Symbol
Parameter
Min
Typ
Max
Unit
(2)
R
Q
Resistor bridge for VBAT
-
-
3 * 39
-
-
kꢁ
-
Ratio on VBAT measurement
Error on Q
3
-
Er(3)
-10
12
10
-
%
µs
(3)
tS_vbat
ADC sampling time when reading VBAT
-
1. 1.55 V < VBAT < 3.6 V.
2. VDD on STM32WLE5/4UxYx devices.
3. Guaranteed by design.
Table 82. V
charging characteristics
BAT
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
kꢁ
VBRS = 0
VBRS = 1
-
-
5
-
-
RBC
Battery charging resistor
1.5
5.3.22
Voltage reference buffer characteristics
(1)
Table 83. VREFBUF characteristics
Symbol
Parameter
Conditions
VRS = 0
RS = 1
Min
Typ
Max
Unit
2.4
2.8
-
3.6
3.6
Normal mode
V
-
Analog supply
voltage
VDDA
VRS = 0
VRS = 1
1.62
1.62
2.044
-
-
2.4
Degraded mode(2)
2.8
Normal mode
ILOAD=100 μA,
TJ = 30 °C
V
RS = 0
VRS = 1
RS = 0
2.048
2.052
V
2.495
2.030
2.478
2.5
2.505
2.057
2.509
Normal mode
V
2.048
2.500
VREFBUF_ Voltage
ILOAD=100 μA,
-40 °C < TJ < 125 °C
reference output
OUT
VRS = 1
VRS = 0
VRS = 1
VDDA - 250 mV
VDDA - 250 mV
-
-
VDDA
VDDA
Degraded mode(2)
Trim step
resolution
TRIM
CL
-
-
-
-
-
±0.05
1
±0.1
1.5
%
Load capacitor
0.5
µF
Equivalent
series resistor
of Cload
esr
-
-
-
-
-
-
-
-
2
4
ꢁ
Static load
current
Iload
mA
120/145
DS13105 Rev 8
STM32WLE5/E4xx
Electrical characteristics
(1)
Table 83. VREFBUF characteristics (continued)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Normal
mode
ppm
/V
Iline_reg
Line regulation 2.8 V ≤ VDDA ≤ 3.6 V
Load regulation 500 μA ≤ Iload ≤ 4 mA
-
-
2000
Normal
mode
ppm
/mA
Iload_reg
-
-
-
50
-
500
±[Tcoeff _ vrefint
+ 50]
-40 °C < TJ < +105 °C
Temperature
ppm
/°C
Tcoeff
coefficient
±[Tcoeff_vrefint
+ 50]
0 °C < TJ < +50 °C
-
DC
40
25
-
55
40
-
Power supply
rejection
PSRR
tSTART
dB
µs
100 kHz
-
CL = 0.5 µF(3)
300
500
650
350
650
800
Startup time
CL = 1.1 µF(3)
CL = 1.5 µF(3)
-
-
Control of
maximum DC
current drive on
VREFBUF_OUT
during start-up
phase (4)
IINRUSH
-
-
-
8
-
mA
µA
Iload = 0 µA
-
-
-
16
18
35
25
30
50
VREFBUF
consumption
from VDDA
IDDA
(VREFBUF)
Iload = 500 µA
I
load = 4 mA
1. Guaranteed by design or characterization. Not tested in production.
2. In degraded mode, VREFBUF cannot maintain accurately the output voltage that follows (VDDA - drop voltage).
3. The capacitive load must include a 100 nF capacitor in order to cut-off the high-frequency noise.
4. To correctly control the VREFBUF in-rush current during start-up phase and scaling change, the VDDA voltage must be in
the range [2.4 V to 3.6 V] and [2.8 V to 3.6 V] respectively for VRS = 0 and VRS = 1.
Figure 24. VREFOUT_TEMP when VRS = 0
V
2.06
Max
2.055
2.05
2.045
Mean
2.04
2.035
Min
2.03
2.025
-40
-20
0
20
40
60
80
100
120°C
MSv62522V2
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133
Electrical characteristics
STM32WLE5/E4xx
Figure 25. VREFOUT_TEMP when VRS = 1
V
2.51
Max
2.505
2.5
2.495
2.49
2.485
2.48
Mean
Min
2.475
-40
-20
0
20
40
60
80
100
120°C
MSv62523V2
5.3.23
Symbol
VDDA
Digital-to-analog converter characteristics
(1)
Table 84. DAC characteristics
Conditions
Parameter
Min
Typ
Max
Unit
DAC output buffer OFF, DAC_OUT
pin not connected (internal
connection only)
1.71
1.80
1.71
1.80
-
-
-
-
Analog supply voltage for
DAC ON
3.6
V
Other modes
DAC output buffer OFF, DAC_OUT
pin not connected (internal
connection only)
VREF+
Positive reference voltage
VDDA
V
Other modes
Connected to VSS
DAC output
5
25
9.6
-
-
-
-
RL
Resistive load
buffer ON
Connected to VDDA
-
11.7
-
RO
Output impedance
DAC output buffer OFF
13.8
2
Output impedance sample- VDD = 2.7 V
and-hold mode, output
kꢁ
RBON
VDD = 2.0 V
-
-
-
-
-
-
3.5
buffer ON
Output impedance sample VDD = 2.7 V
and hold mode, output
16.5
18.0
RBOFF
VDD = 2.0 V
buffer OFF
CL
DAC output buffer ON
Sample-and-hold mode
-
-
-
50
1
pF
µF
Capacitive load
CSH
0.1
VREF+
- 0.2
DAC output buffer ON
DAC output buffer OFF
0.2
0
-
-
Voltage on DAC_OUT
output
VDAC_OUT
V
VREF+
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DS13105 Rev 8
STM32WLE5/E4xx
Electrical characteristics
(1)
Table 84. DAC characteristics (continued)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
±0.5 LSB
-
-
-
-
-
1.7
1.6
3
Normal mode
Settling time (full scale: for
a 12-bit code transition
between the lowest and the
±1 LSB
±2 LSB
±4 LSB
±8 LSB
2.9
DAC output
buffer ON
CL ≤ 50 pF
RL ≥ 5 kꢁ
1.55
1.48
1.4
2.85
2.8
tSETTLING highest input codes, when
DAC_OUT reaches final
µs
2.75
value ±0.5 LSB, ±1 LSB,
±2 LSB, ±4 LSB, ±8 LSB)
Normal mode DAC output buffer
OFF, ±1LSB, CL = 10 pF
-
-
2
4.2
2
2.5
7.5
5
Normal mode DAC output buffer ON
CL ≤ 50 pF, RL ≥ 5 kꢁ
Wakeup time from off state
tWAKEUP (setting the ENx bit in the
µs
(2)
DAC control register) until
final value ±1 LSB
Normal mode DAC output buffer
OFF, CL ≤ 10 pF
-
Normal mode DAC output buffer ON
CL ≤ 50 pF, RL ≥ 5 kꢁ, DC
PSRR
VDDA supply rejection ratio
-
-80
-
-28
-
dB
Minimum time between two DAC_MCR:MODEx[2:0] = 000 or 001
consecutive writes into the CL ≤ 50 pF, RL ≥ 5 kꢁ
DAC_DORx register to
1
TW_to_W guarantee a correct
DAC_OUT for a small
variation of the input code
(1 LSB)
µs
DAC_MCR:MODEx[2:0] = 010 or 011
CL ≤ 10 pF
1.4
-
-
DAC output buffer
ON, CSH = 100 nF
-
-
0.7
3.5
18
DAC_OUT pin
connected
Sampling time in sample
and hold mode (code
transition between the
ms
DAC output buffer
OFF, CSH = 100 nF
10.5
tSAMP
lowest input code and the
highest input code when
DACOUT reaches final
value ±1LSB)
DAC_OUT pin
not connected
DAC output buffer
(internal
-
2
3.5
µs
OFF
connection
only)
Sample and hold mode,
DAC_OUT pin connected
(3)
Ileak
Output leakage current
-
-
-
nA
Internal sample and hold
capacitor
CIint
-
5.2
7
8.8
pF
µs
tTRIM
Middle code offset trim time DAC output buffer ON
50
-
-
-
-
-
VREF+ = 3.6 V
1500
750
Middle code offset for 1 trim
code step
Voffset
µV
VREF+ = 1.8 V
-
DS13105 Rev 8
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133
Electrical characteristics
STM32WLE5/E4xx
(1)
Table 84. DAC characteristics (continued)
Conditions Min
No load, middle
Symbol
Parameter
Typ
Max
Unit
-
-
-
315
500
code (0x800)
DAC output
buffer ON
No load, worst code
(0xF1C)
450
670
DAC consumption from
VDDA
IDDA(DAC)
µA
DAC output
buffer OFF
No load, middle
code (0x800)
-
0.2
315 x
670 x
Sample and hold mode, CSH
100 nF
=
-
Ton/(Ton Ton/(Ton
+Toff)(4) +Toff
)
(4)
No load, middle
code (0x800)
-
-
-
185
340
240
400
DAC output
buffer ON
No load, worst code
(0xF1C)
DAC output
buffer OFF
No load, middle
code (0x800)
155
205
DAC consumption from
VREF+
IDDV(DAC)
µA
185 x
400 x
Sample and hold mode, buffer ON,
CSH = 100 nF, worst case
-
-
Ton/(Ton Ton/(Ton
+Toff)(4) +Toff
)
(4)
155 x 205 x
Sample and hold mode, buffer OFF,
CSH = 100 nF, worst case
Ton/(Ton Ton/(Ton
+Toff)(4) +Toff
)
(4)
1. Guaranteed by design.
2. In buffered mode, the output can overshoot above the final value for low input code (starting from min value).
3. Refer to Table 72: I/O static characteristics.
4. Ton is the Refresh phase duration. Toff is the Hold phase duration. Refer to the reference manual for more details.
Figure 26. 12-bit buffered/non-buffered DAC
Buffered/non-buffered DAC
Buffer(1)
RLOAD
DAC_OUTx
12-bit
digital-to-analog
converter
CLOAD
(1) The DAC integrates an output buffer that can be used to reduce the output impedance and to drive external loads
directly without the use of an external operational amplifier. The buffer can be bypassed by configuring the BOFFx bit in
the DAC_CR register.
MSv47959V2
124/145
DS13105 Rev 8
STM32WLE5/E4xx
Electrical characteristics
.
(1)
Table 85. DAC accuracy
Conditions
Symbol
Parameter
Min
Typ
Max Unit
DAC output buffer ON
-
-
-
±2
±2
Differential non
linearity (2)
DNL
-
DAC output buffer OFF
10 bits
-
Monotonicity
Guaranteed
DAC output buffer ON, CL ≤ 50 pF, RL ≥ 5 kꢁ
DAC output buffer OFF, CL ≤ 50 pF, no RL
-
-
-
-
-
-
±4
±4
INL
Integral non linearity(3)
VREF+ = 3.6 V
±12
DAC output buffer ON
LSB
Offset error at code
0x800(3)
CL ≤ 50 pF, RL ≥ 5 kꢁ
Offset
VREF+ = 1.8 V
-
-
-
-
-
-
±25
±8
DAC output buffer OFF, CL ≤ 50 pF, no RL
DAC output buffer OFF, CL ≤ 50 pF, no RL
Offset error at code
0x001(4)
Offset1
±5
V
REF+ = 3.6 V
-
-
-
-
±5
±7
Offset Error at code
0x800 after calibration CL ≤ 50 pF, RL ≥ 5 kꢁ
DAC output buffer ON
OffsetCal
VREF+ = 1.8 V
DAC output buffer ON, CL ≤ 50 pF, RL ≥ 5 kꢁ
DAC output buffer OFF, CL ≤ 50 pF, no RL
-
-
-
-
±0.5
%
±0.5
Gain
Gain error(5)
DAC output buffer ON, CL ≤ 50 pF, RL ≥ 5 kꢁ
DAC output buffer OFF, CL ≤ 50 pF no RL
DAC output buffer ON, CL ≤ 50 pF, RL ≥ 5 kꢁ
-
-
-
-
-
-
±30
TUE
Total unadjusted error
LSB
±12
Total unadjusted error
after calibration
TUECal
±23
LSB
dB
DAC output buffer ON, CL ≤ 50 pF, RL ≥ 5 kꢁ,
1 kHz, BW 500 kHz
-
-
-
-
-
-
71.2
71.6
-78
-
-
-
-
-
-
SNR
THD
Signal-to-noise ratio
DAC output buffer OFF, CL ≤ 50 pF, no RL,
1 kHz, BW 500 kHz
DAC output buffer ON, CL ≤ 50 pF, RL ≥ 5 kꢁ,
1 kHz
Total harmonic
distortion
dB
dB
DAC output buffer OFF, CL ≤ 50 pF, no RL,
1 kHz
-79
DAC output buffer ON, CL ≤ 50 pF, RL ≥ 5 kꢁ,
1 kHz
70.4
71
Signal-to-noise and
distortion ratio
SINAD
DAC output buffer OFF, CL ≤ 50 pF, no RL,
1 kHz
DS13105 Rev 8
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133
Electrical characteristics
STM32WLE5/E4xx
(1)
Table 85. DAC accuracy (continued)
Symbol
Parameter
Conditions
Min
Typ
Max Unit
DAC output buffer ON, CL ≤ 50 pF, RL ≥ 5 kꢁ,
1 kHz
-
11.4
-
Effective number of
bits
ENOB
bits
DAC output buffer OFF, CL ≤ 50 pF, no RL,
1 kHz
-
11.5
-
1. Guaranteed by design.
2. Difference between two consecutive codes - 1 LSB.
3. Difference between measured value at code i and the value at code i on a line drawn between code 0 and last code 4095.
4. Difference between the value measured at code (0x001) and the ideal value.
5. Difference between the ideal slope of the transfer function and the measured slope computed from code 0x000 and 0xFFF
when buffer is OFF, and from code giving 0.2 V and (VREF+ – 0.2) V when buffer is ON.
5.3.24
Comparator characteristics
(1)
Table 86. COMP characteristics
Symbol
VDDA
Parameter
Conditions
Min
Typ
Max Unit
Analog supply voltage
-
1.62
-
3.6
Comparator
input voltage range
VIN
-
0
-
VDDA
V
(2)
VBG
Scaler input voltage
Scaler offset voltage
-
-
VREFINT
VSC
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
±5
200
0.8
100
-
±10
300
1
mV
nA
µA
µs
BRG_EN = 0 (bridge disabled)
Scaler static consumption
from VDDA
I
DDA(SCALER)
BRG_EN = 1 (bridge enabled)
-
tSTART_SCALER Scaler startup time
200
5
VDDA ≥ 2.7 V
High-speed
mode
VDDA < 2.7 V
-
7
Comparator startup time
to reach propagation
delay specification
tSTART
V
DDA ≥ 2.7 V
VDDA < 2.7 V
Ultra-low-power mode
-
15
25
40
80
100
0.9
7
µs
Medium mode
-
-
VDDA ≥ 2.7 V
VDDA < 2.7 V
55
55
0.55
4
High-speed
mode
ns
Propagation delay with
100 mV overdrive
(3)
tD
Medium mode
µs
Ultra-low-power mode
Full common mode range
No hysteresis
Voffset
Comparator offset error
Comparator hysteresis
±5
0
±20
-
mV
Low hysteresis
8
-
Vhys
mV
Medium hysteresis
High hysteresis
15
27
-
-
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DS13105 Rev 8
STM32WLE5/E4xx
Symbol
Electrical characteristics
(1)
Table 86. COMP characteristics (continued)
Parameter
Conditions
Min
Typ
Max Unit
Static
-
400
600
Ultra-low-
power mode
nA
-
With 50 kHz ±100 mV
overdrive square signal
-
-
-
-
-
1200
5
Static
7
-
Comparator consumption Medium
IDDA(COMP)
With 50 kHz ±100 mV
overdrive square signal
from VDDA
mode
6
µA
Static
70
75
100
High-speed
mode
With 50 kHz ±100 mV
overdrive square signal
-
1. Guaranteed by design, unless otherwise specified.
2. Refer to Table 35: Embedded internal voltage reference.
3. Guaranteed by characterization results.
5.3.25
Timers characteristics
Parameters given in the following tables are guaranteed by design. Refer to Section 5.3.16:
I/O port characteristics for details on the input/output alternate function characteristics
(output compare, input capture, external clock, PWM output).
(1)
Table 87. TIMx characteristics
Symbol
tres(TIM)
Parameter
Conditions
Min
Max
Unit
-
1
-
tTIMxCLK
ns
Timer resolution time
fTIMxCLK = 48 MHz
15.625
-
fTIMxCLK/2
40
-
0
Timer external clock frequency
on CH1 to CH4
fEXT
MHz
bit
fTIMxCLK = 48 MHz
0
TIM1, TIM16, TIM17
-
16
ResTIM
Timer resolution
TIM2
-
32
-
fTIMxCLK = 48 MHz
-
1
65536
1024
tTIMxCLK
µs
tTIMxCLK
s
tCOUNTER
16-bit counter clock period
0.015625
-
-
65536 × 65536
67.10
Maximum possible count with
32-bit counter
tMAX_COUNT
fTIMxCLK = 48 MHz
1. TIMx, is used as a general term where x stands for 1, 2, 16 or 17.
DS13105 Rev 8
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Electrical characteristics
STM32WLE5/E4xx
(1)
Table 88. IWDG min/max timeout period at 32 kHz (LSI)
PR[2:0] bits Min timeout (RL[11:0] = 0x000) Max timeout (RL[11:0] = 0xFFF) Unit
Prescaler divider
/4
/8
0x0
0x1
0.125
0.250
0.500
1.0
512
1024
2048
4096
8192
16384
32768
/16
/32
/64
/128
/256
0x2
0x3
ms
0x4
2.0
0x5
4.0
0x6 or 0x7
8.0
1. The exact timings still depend on the phasing of the APB interface clock versus the LSI clock, hence there is always a full
RC period of uncertainty.
5.3.26
Communication interfaces characteristics
I2C interface characteristics
2
2
The I C interface meets the timings requirements of the I C-bus specification and user
manual rev. 03 for:
•
•
•
Standard-mode (Sm): bitrate up to 100 Kbit/s
Fast-mode (Fm): bitrate up to 400 Kbit/s
Fast-mode Plus (Fm+): bitrate up to 1 Mbit/s
2
The I C timings requirements are guaranteed by design when the I2C peripheral is properly
configured (refer to the reference manual) and when the II2CCLK frequency is greater than
the minimum shown in the table below.
Table 89. Minimum I2CCLK frequency in all I2C modes
Symbol
Parameter
Conditions
Min
Unit
Standard-mode
Fast-mode
-
2
8
Analog filter ON, DNF = 0
Analog filter OFF, DNF = 1
Analog filter ON, DNF = 0
Analog filter OFF, DNF = 1
f(I2CCLK)
I2CCLK frequency
9
MHz
18
16
Fast-mode Plus
The SDA and SCL I/O requirements are met with the following restrictions:
•
The SDA and SCL I/O pins are not “true” open-drain. When configured as open-drain,
the PMOS connected between the I/O pin and V is disabled, but is still present.
DD
•
The 20 mA output drive requirement in Fast-mode Plus is partially supported. This
limits the maximum load C
supported in Fast-mode Plus, given by these formulas:
load
–
–
t (SDA/SCL) = 0.8473 x R x C
r p load
R (min) = [V - V (max)] / I (max)
p
DD
OL
OL
where R is the I2C lines pull-up. Refer to Section 5.3.16: I/O port characteristics
p
for more details.
128/145
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STM32WLE5/E4xx
Electrical characteristics
All I2C SDA and SCL I/Os embed an analog filter (refer to the table below for its
characteristics).
(1)
Table 90. I2C analog filter characteristics
Parameter
Symbol
Min
Max
Unit
tAF
Maximum pulse width of spikes that are suppressed by the analog filter
50(2)
100(3)
ns
1. Guaranteed by characterization.
2. Spikes with widths below tAF(min) filtered.
3. Spikes with widths above tAF(max) not filtered.
USART characteristics
Unless otherwise specified, the parameters given in the table below are derived from tests
performed under the ambient temperature, f frequency and supply voltage conditions
PCLKx
summarized in Table 25: General operating conditions, with the following configuration:
•
•
•
OSPEEDRy[1:0] set to 10 (output speed)
capacitive load C = 30 pF
measurement points at CMOS levels: 0.5 x V
DD
Refer to Section 5.3.16: I/O port characteristics for more details on the input/output alternate
function characteristics (NSS, CK, TX, and RX for USART).
Table 91. USART characteristics
Symbol
Parameter
Conditions
Master mode
Min
Typ
Max
Unit
-
-
-
-
-
6
16
-
fCK
USART clock frequency
MHz
Slave mode
Slave mode
Slave mode
-
tker + 5
2
tsu(NSS)
th(NSS)
tw(CKH)
tw(CKL)
NSS setup time
NSS hold time
CK high time
CK low time
-
Master mode
1 / fCK / 2 - 1 1 / fCK / 2 1 / fCK / 2 + 1
Master mode
Slave mode
Master mode
Slave mode
Master mode
Slave mode
Master mode
Slave mode
22
3
-
-
-
-
tsu(RX)
th(RX)
tv(TX)
th(TX)
Data input setup time
Data input hold time
Data output valid time
Data output hold time
ns
0
-
-
1
-
-
-
13
0.5
-
22
1
-
-
10
0
-
-
DS13105 Rev 8
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133
Electrical characteristics
STM32WLE5/E4xx
SPI characteristics
Unless otherwise specified, the parameters given in the table below are derived from tests
performed under the ambient temperature, f frequency and supply voltage conditions
PCLKx
summarized in Table 25: General operating conditions, with the following configuration:
•
•
•
output speed set to OSPEEDRy[1:0] = 11
capacitive load C = 30 pF
measurements done at CMOS levels: 0.5 x V
DD
Refer to Section 5.3.16: I/O port characteristics for more details on the input/output alternate
function characteristics (NSS, SCK, MOSI, MISO for SPI).
(1)
Table 92. SPI characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Master mode
1.8 < VDD < 3.6 V, Range 1
24
Master transmitter mode
1.8 < VDD < 3.6 V, Range 1
24
24
fSCK
1/tc(SCK)
Slave receiver mode
1.8 < VDD < 3.6 V, Range 1
SPI clock frequency
-
-
MHz
Slave mode transmitter/full duplex
2.7 < VDD < 3.6 V, Range 1
24(2)
24(2)
Slave mode transmitter/full duplex
1.8 < VDD < 3.6 V, Range 1
tsu(NSS) NSS setup time
th(NSS) NSS hold time
tw(SCKH)
Slave mode, SPI prescaler = 2
Slave mode, SPI prescaler = 2
3 x TPCLK
2 x TPCLK
-
-
-
-
-
SCK high and low time
Master mode
TPCLK - 1
TPCLK
TPCLK + 1
tw(SCKL)
tsu(MI)
tsu(SI)
th(MI)
Master mode
Slave mode
Master mode
Slave mode
1
1
6
2
9
9
-
-
-
-
Data input setup time
Data input hold time
-
-
ns
th(SI)
-
-
ta(SO) Data output access time
tdis(SO) Data output disable time
12
10
34
16
Slave mode
130/145
DS13105 Rev 8
STM32WLE5/E4xx
Electrical characteristics
(1)
Table 92. SPI characteristics (continued)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Slave mode, 2.7 < VDD < 3.6 V
Range 1
-
10
13.5
Slave mode, 2.7 < VDD < 3.6 V
Range 2
-
-
-
17
10
17
18
20
24
tv(SO)
Data output valid time
Slave mode, 1.8 < VDD < 3.6 V
Range 1
ns
Slave mode, 1.8 < VDD < 3.6 V
Range 2
tv(MO)
th(SO)
th(MO)
Master mode (after enable edge)
Slave mode (after enable edge)
Master mode (after enable edge)
-
1
-
1.5
8
0
-
-
Data output hold time
-
1. Guaranteed by characterization results.
2. Maximum frequency in Slave transmitter mode is determined by the sum of tv(SO) and tsu(MI), that has to fit into SCK low or
high phase preceding the SCK sampling edge. This value can be achieved when the SPI communicates with a master
having tsu(MI) = 0 while Duty(SCK) = 50 %.
Figure 27. SPI timing diagram - Slave mode and CPHA = 0
NSS input
MISO
MSB OUT
BIT6 OUT
BIT1 IN
LSB OUT
OUTPUT
(SI)
MOSI
INPUT
LSB IN
MSB IN
(SI)
DS13105 Rev 8
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133
Electrical characteristics
STM32WLE5/E4xx
Figure 28. SPI timing diagram - Slave mode and CPHA = 1
NSS input
tSU(NSS)
th(NSS)
tc(SCK)
CPHA=1
CPOL=0
CPHA=1
CPOL=1
tw(SCKH)
tw(SCKL)
tr(SCK)
tf(SCK)
th(SO)
tdis(SO)
tv(SO)
ta(SO)
MISO
MSB OUT
MSB IN
BIT6 OUT
LSB OUT
OUTPUT
th(SI)
tsu(SI)
MOSI
INPUT
LSB IN
BIT 1 IN
ai14135b
1. Measurement points are set at CMOS levels: 0.3 VDD and 0.7 VDD
.
Figure 29. SPI timing diagram - Master mode
High
NSS input
t
c(SCK)
CPHA=0
CPOL=0
CPHA=0
CPOL=1
CPHA=1
CPOL=0
CPHA=1
CPOL=1
t
t
t
t
w(SCKH)
w(SCKL)
r(SCK)
f(SCK)
t
su(MI)
MISO
INPUT
BIT6 IN
LSB IN
MSB IN
t
h(MI)
MOSI
OUTPUT
BIT1 OUT
LSB OUT
MSB OUT
t
t
h(MO)
v(MO)
ai14136c
1. Measurement points are set at CMOS levels: 0.3 VDD and 0.7 VDD
.
132/145
DS13105 Rev 8
STM32WLE5/E4xx
Electrical characteristics
JTAG/SWD characteristics
Unless otherwise specified, the parameters given in the table below are derived from tests
performed under the ambient temperature, f frequency and supply voltage conditions
PCLKx
summarized in Table 25: General operating conditions, with the following configuration:
•
•
capacitive load C = 30 pF
measurement done at CMOS levels: 0.5 x V
DD.
Refer to Section 5.3.16: I/O port characteristics for more details.
Table 93. Dynamic JTAG characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
2.7 V < VDD < 3.6 V
-
-
-
-
33
25
-
fPP
TCK clock frequency
MHz
1/tc(TCK)
1.8 V < VDD < 3.6 V
tisu(TMS) TMS input setup time
-
0.5
1
-
tih(TMS)
tisu(TDI)
tih(TDI)
TMS input hold time
TDI input setup time
TDI input hold time
-
-
-
-
1
-
-
-
2.5
-
-
-
ns
2.7 V < VDD < 3.6 V
12
12
-
15
20
-
tov(TDO) TDO output valid time
toh(TDO) TDO output hold time
1.8 V< VDD < 3.6 V
-
-
10
Table 94. Dynamic SWD characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
2.7 V < VDD < 3.6 V
-
-
-
-
58
41
-
fPP
SWCLK clock frequency
MHz
1/tc(SWCLK)
1.8 < VDD < 3.6 V
tisu(SWDIO) SWDIO input setup time
tih(SWDIO) SWDIO input hold time
-
1
2
-
-
-
-
-
2.7 V < VDD < 3.6 V
15
15
-
17
24
-
ns
tov(SWDIO) SWDIO output valid time
toh(SWDIO) SWDIO output hold time
1.8 V < VDD < 3.6 V
-
-
9
DS13105 Rev 8
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133
Package information
STM32WLE5/E4xx
6
Package information
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK packages, depending on their level of environmental compliance. ECOPACK
specifications, grade definitions and product status are available at www.st.com. ECOPACK
is an ST trademark.
6.1
UFQFPN48 package information
This UFQFPN is a 48 leads, 7x7 mm, 0.5 mm pitch, ultra thin fine pitch quad flat package.
Figure 30. UFQFPN48 - Outline
Pin 1 identifier
laser marking area
D
A
E
Y
E
Seating
plane
T
ddd
A1
b
e
Detail Y
D
Exposed pad
area
D2
1
L
48
C 0.500x45°
pin1 corner
R 0.125 typ.
Detail Z
E2
1
48
Z
A0B9_ME_V3
1. Drawing is not to scale.
2. All leads/pads should also be soldered to the PCB to improve the lead/pad solder joint life.
3. There is an exposed die pad on the underside of the UFQFPN package. It is recommended to connect and
solder this back-side pad to PCB ground.
134/145
DS13105 Rev 8
STM32WLE5/E4xx
Package information
inches(1)
Table 95. UFQFPN48 - Mechanical data
millimeters
Symbol
Min
Typ
Max
Min
Typ
Max
A
A1
D
0.500
0.000
6.900
6.900
5.500
5.500
0.300
-
0.550
0.020
7.000
7.000
5.600
5.600
0.400
0.152
0.250
0.500
-
0.600
0.050
7.100
7.100
5.700
5.700
0.500
-
0.0197
0.0000
0.2717
0.2717
0.2165
0.2165
0.0118
-
0.0217
0.0008
0.2756
0.2756
0.2205
0.2205
0.0157
0.0060
0.0098
0.0197
-
0.0236
0.0020
0.2795
0.2795
0.2244
0.2244
0.0197
-
E
D2
E2
L
T
b
0.200
-
0.300
-
0.0079
-
0.0118
-
e
ddd
-
0.080
-
0.0031
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Figure 31. UFQFPN48 - Recommended footprint
7.30
6.20
48
37
1
36
5.60
0.20
7.30
5.80
6.20
5.60
0.30
12
25
13
24
0.75
0.50
0.55
5.80
A0B9_FP_V2
1. Dimensions are expressed in millimeters.
DS13105 Rev 8
135/145
140
Package information
STM32WLE5/E4xx
Device marking for UFQFPN48
The following figure gives an example of topside marking versus pin 1 position identifier
location.
The printed markings may differ depending on the supply chain.
Other optional marking or inset/upset marks, which depend on supply chain operations, are
not indicated below.
Figure 32. UFQFPN48 marking example (package top view)
STM32WLE5
Product identification(1)
CCU6
Date code
YWW
Pin 1 identifier
Revision code
R
MSv66046V1
1. Parts marked as “ES”, “E” or accompanied by an Engineering Sample notification letter, are not yet
qualified and therefore not approved for use in production. ST is not responsible for any consequences
resulting from such use. In no event will ST be liable for the customer using any of these engineering
samples in production. ST’s Quality department must be contacted prior to any decision to use these
engineering samples to run a qualification activity.
136/145
DS13105 Rev 8
STM32WLE5/E4xx
Package information
6.2
6.3
WLCSP59 package information
For more information on this package, contact the local STMicroelectronics sales office.
UFBGA73 package information
This UFBGA is a 73 balls, 5 × 5 mm, ultra thin fine pitch ball grid array package.
Figure 33. UFBGA73 - Outline
SEATING PLANE
C
ddd
C
A4 A2
SIDE VIEW
A1
A
E
B
E1
A
F
e
F
J
H
G
F
E
D
C
B
A
D1
D
e
1
2 3 4 5 6 7 8 9
A1 INDEX CORNER AREA
b (73 BALLS)
A
B
eee
C
C
M
M
BOTTOM VIEW
f f f
B08E_UFBGA73_ME_V1
1. Drawing is not to scale.
2. - The terminal A1 corner must be identified on the top surface by using a corner chamfer, ink or metalized
markings, or other feature of package body or integral heat slug.
- A distinguishing feature is allowable on the bottom surface of the package to identify the terminal A1
corner. Exact shape of each corner is optional.
Table 96. UFBGA73 - Mechanical data
millimeters
Typ
inches(1)
Typ
Symbol
Min
Max
Min
Max
A(2)
A1
-
-
-
-
0.60
0.11
-
-
-
-
0.236
0.0043
DS13105 Rev 8
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140
Package information
STM32WLE5/E4xx
Table 96. UFBGA73 - Mechanical data (continued)
millimeters
Typ
inches(1)
Symbol
Min
Max
Min
Typ
Max
A2
A4
b(3)
D
-
0.13
0.32
0.29
5.00
4.00
5.00
4.00
0.50
0.50
-
-
-
-
0.0051
0.0126
0.0114
0.1969
0.1575
0.1969
0.1575
0.0197
0.0197
-
-
-
-
-
0.24
0.34
5.15
-
0.0094
0.0134
4.85
0.1909
0.2028
D1
E
-
-
-
4.85
5.15
-
0.1909
0.2028
E1
e
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
F
-
-
ddd
eee(4)
fff(5)
0.08
0.15
0.05
0.0031
0.0059
0.0020
-
-
-
-
1. Values in inches are converted from mm and rounded to 4 decimal digits.
2. - UFBGA stands for Ultra-Thin Profile Fine Pitch Ball Grid Array.
- Ultra Thin profile: 0.50 < A ≤ 0.65mm / Fine pitch: e < 1.00mm pitch.
- The total profile height (Dim A) is measured from the seating plane to the top of the component
- The maximum total package height is calculated by the following methodology:
A Max = A1 Typ + A2 Typ + A4 Typ + √ (A1²+A2²+A4² tolerance values)
3. The typical balls diameters before mounting is 0.20 mm.
4. The tolerance of position that controls the location of the pattern of balls with respect to datum A and B. For
each ball there is a cylindrical tolerance zone eee perpendicular to datum C and located on true position
with respect to datum A and B as defined by e. The axis perpendicular to datum C of each ball must lie
within this tolerance zone.
5. The tolerance of position that controls the location of the balls within the matrix with respect to each other.
For each ball there is a cylindrical tolerance zone fff perpendicular to datum C and located on true position
as defined by e. The axis perpendicular to datum C of each ball must lie within this tolerance zone. Each
tolerance zone fff in the array is contained entirely in the respective zone eee above. The axis of each ball
must lie simultaneously in both tolerance zones.
Figure 34. UFBGA73 - Recommended footprint
Dpad
Dsm
MSv62396V1
138/145
DS13105 Rev 8
STM32WLE5/E4xx
Package information
Table 97. UFBGA recommended PCB design rules (0.5 mm pitch BGA)
Dimension Recommended values
Pitch
Dpad
0.5 mm
0.230 mm
0.330 mm typ. (depends on the soldermask
registration tolerance)
Dsm
Stencil opening
0.280 mm
Stencil thickness
Pad trace width
Ball diameter
Between 0.100 mm and 0.125 mm
0.100 mm
0.280 mm
Device marking for UFBGA73
The following figure gives an example of topside marking versus pin 1 position identifier
location.
The printed markings may differ depending on the supply chain.
Other optional marking or inset/upset marks, which depend on supply chain operations, are
not indicated below.
Figure 35. UFBGA73 marking example (package top view)
Product identification(1)
WLE5J8I6
Y WW R
Date code
Revision code
Pin 1 identifier
MSv64357V1
1. Parts marked as “ES”, “E” or accompanied by an Engineering Sample notification letter, are not yet
qualified and therefore not approved for use in production. ST is not responsible for any consequences
resulting from such use. In no event will ST be liable for the customer using any of these engineering
samples in production. ST’s Quality department must be contacted prior to any decision to use these
engineering samples to run a qualification activity.
DS13105 Rev 8
139/145
140
Package information
STM32WLE5/E4xx
6.4
Package thermal characteristics
The maximum chip junction temperature (T max) must never exceed the values given in
J
Table 25: General operating conditions.
The maximum chip-junction temperature, T max (in °C), can be calculated using the
J
equation:
T max = T max + (P max x Θ )
J
A
D
JA
where:
•
•
•
•
T max is the maximum ambient temperature in °C.
A
Θ
is the package junction-to-ambient thermal resistance, in °C/W.
JA
P max is the sum of P
max and P max (P max = P
max + P max).
INT I/O
D
INT
I/O
D
P
max is the product of I and V , expressed in Watt. This is the maximum chip
DD DD
INT
internal power.
P
max represents the maximum power dissipation on output pins:
I/O
P
max = Σ (V × I ) + Σ ((V – V ) × I
)
OH
I/O
OL
OL
DD
OH
taking into account the actual V / I and V / I of the I/Os at low and high level in the
OL OL
OH OH
application.
When the SMPS is used, a portion of the power consumption is dissipated into the external
inductor, therefore reducing the device power dissipation. This portion depends mainly on
the inductor ESR characteristics.
As the radiated RF power is quite low (< 4 mW), it is not necessary to remove it from the
device power consumption.
RF characteristics (such as sensitivity, Tx power consumption) are provided up to 85 °C.
Table 98. Package thermal characteristics
Symbol
Parameter
Value
Unit
Thermal resistance junction-ambient
UFBGA73 - 5 x 5 mm
UFQFPN48 - 7 x 7 mm
WLCSP59
20.1
27.4
TBD
ΘJA
Thermal resistance junction-board
UFBGA73 - 5 x 5 mm
UFQFPN48 - 7 x 7 mm
WLCSP59
20.2
11.7
TBD
ΘJB
°C/W
Thermal resistance junction-top case
UFBGA73 - 5 x 5 mm
UFQFPN48 - 7 x 7 mm
WLCSP59
31.1
8.5
ΘJC
TBD
140/145
DS13105 Rev 8
STM32WLE5/E4xx
Ordering information
7
Ordering information
Example:
STM32
WL
E5
J
C
I
6 TR
Device family
STM32 = Arm based 32-bit microcontroller
Product type
WL = wireless long range
Device subfamily
E5 = Cortex-M4, full set of modulations
E4 = Cortex-M4, full set of modulations except LoRa
Pin/ball count
C = 48
U= 59
J = 73
Flash memory size
8 = 64 Kbytes
B = 128 Kbytes
C = 256 Kbytes
Package
I = UFBGA
U= UFQFPN
Y= WLCSP
Temperature range
6 = -40 to 85 °C (105 °C junction)
7 = -40 to 105 °C (125 °C junction)
Packing
TR = tape and reel
xxx = programmed parts
For a list of available options (such as speed or package) or for further information on any
aspect of this device, contact the nearest ST sales office.
DS13105 Rev 8
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141
Revision history
STM32WLE5/E4xx
8
Revision history
Table 99. Document revision history
Changes
Date
Revision
20-Dec-2019
8-Jan-2020
1
2
Initial release.
Updated Ultra-low-power platform features.
Updated:
– TJ in Table 2: Main features and peripheral counts and in the whole doc
– Section 3.9.1: Power supply schemes
– Table 12: Temperature sensor calibration values
– Table 13: Internal voltage reference calibration values
– Ff renamed RF in Table 18: Legend/abbreviations used in the pinout table and
Table 19: STM32WLE5J8/JB/JC pin definition
– new RF AF in Table 20: Alternate functions
– Section 5.1.2: Typical values
– Figure 12: Current consumption measurement scheme
– Table 21: Voltage characteristics
– Table 23: Thermal characteristics
25-Feb-2020
3
– Table 25: General operating conditions
– Section 5.3.3: Sub-GHz radio characteristics
– Table 34: Embedded internal voltage reference
– Table 57: MSI oscillator characteristics
– Table 58: LSI oscillator characteristics
– Table 67: I/O static characteristics
– Table 68: Output voltage characteristics
– Table 69: I/O AC characteristics
– Table 72: ADC characteristics
– Table 75: TS characteristics
– Table 76: VBAT monitoring characteristics
Removed table LSI2 oscillator.
Updated:
27-Feb-2020
4
– Features
– Table 24: Main performances at VDD = 3 V
142/145
DS13105 Rev 8
STM32WLE5/E4xx
Revision history
Table 99. Document revision history (continued)
Revision Changes
Date
Updated:
– Radio in Features
– Section 3.8.3: Transmitter
– Table 13: Internal voltage reference calibration values
– F6 I/O structure and footnotes in Table 19: STM32WLE5xx pin definition
– Figure 11: Power supply scheme
– IVDD(PIN) in Table 22: Current characteristics
– New Table 26: Operating range of RF pads
– PA match in Table 27: Sub-GHz radio power consumption
– EFFSMPS in Table 32: Sub-GHz radio power management specifications
– IDD(Run) in Table 36
29-Jun-2020
5
– New Table 43, Table 45, Table 47 and Table 49
– New footnote in Table 56: HSE32 crystal requirements
– Note 2 in Table 59: Low-speed external user clock characteristics
– ꢀTemp(HSI16) in Table 61: HSI16 oscillator characteristics
– Tj replacing TA in Table 62 and Table 63
– Ilkg in Table 72: I/O static characteristics
– Table 73: Output voltage characteristics
– Table 77: ADC characteristics
– Table 79: ADC accuracy
Updated:
– Package list in the cover page
– Table 1: Device summary
– Table 2: Main features and peripheral counts
– New Figure 8: UFQFPN48 pinout and Figure 9: WLCSP59 pinout
– Figure 10: UFBGA73 pinout
8-Jul-2020
6
– Figure 13: Power supply scheme
– Table 19: STM32WLE5/E4xx pin definition
– Table 20: Alternate functions
– Table 70: ESD absolute maximum ratings
– Table 82: VBAT monitoring characteristics
– Table 93: SPI characteristics
– Section 7: Ordering information
DS13105 Rev 8
143/145
144
Revision history
STM32WLE5/E4xx
Table 99. Document revision history (continued)
Revision Changes
Date
Updated:
– Table 1 with STM32WLE4xx products (without LoRa) and -40/+105 °C
– Table 2: Main features and peripheral counts
– Figure 9: UFBGA73 pinout (formatting only)
– Table 19: STM32WLE5/E4xx pin definition and Table 20: Alternate functions
– TJ in Table 23: Thermal characteristics
– IINJ(PIN) in Table 22: Current characteristics
– Table 25: General operating conditions
– Table 27: Sub-GHz radio power consumption
– Table 28: Sub-GHz radio power consumption in transmit mode
– Figure 14: VREFINT versus temperature
5-Oct-2020
7
– all TBD and values at 105 °C in Table 36 to Table 55
– Table 56: HSE32 crystal requirements
– Figure 17: HSI16 frequency versus temperature
– Table 71: I/O current injection susceptibility
– Footnote of Table 72: I/O static characteristics
– Table 83: VREFBUF characteristics
– new Figure 23 and Figure 24
– Table 98: Package thermal characteristics
– Section 7: Ordering information
Updated:
– Features
– New logos in Section 1: Introduction
– Section 3.6: Security management
– New Figure 5: Power-up/power-down sequence
– New Section 3.13: Hardware semaphore (HSEM)
– New Section 3.17: Cyclic redundancy check (CRC)
– Table 9: MCU and sub-GHz radio operating modes
– Section 3.18.3: VBAT battery voltage monitoring
– Figure 13: Power supply scheme
9-Nov-2020
8
– Table 28: Sub-GHz radio power consumption in transmit mode
– Table 44: Current consumption in Stop 1 mode
– Table 53: Peripheral current consumption
– tWUSTOP1 in Table 54: Low-power mode wakeup timings
– Table 81: VBAT monitoring characteristics
144/145
DS13105 Rev 8
STM32WLE5/E4xx
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ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order
acknowledgment.
Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or
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© 2020 STMicroelectronics – All rights reserved
DS13105 Rev 8
145/145
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