STM6321_08 [STMICROELECTRONICS]
5-pin supervisor with watchdog timer and push-button reset; 5针主管与看门狗定时器和按钮复位
| 型号： | STM6321_08 |
| 厂家： | 
ST |
| 描述： | 5-pin supervisor with watchdog timer and push-button reset |
| 文件： | 总28页 (文件大小：260K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
STM6321/6322
STM6821/6822/6823/6824/6825
5-pin supervisor with watchdog timer and push-button reset
Features
■ Precision V monitoring of 5, 3.3, 3, or 2.5 V
CC
power supplies
■ RST outputs (active-low, push-pull or open
drain)
■ RST outputs (active-high, push-pull)
■ Reset pulse width of 1.4 ms, 200 ms and
(a)
240 ms (typ)
(a)
■ Watchdog timeout period of 1.6 s (typ)
■ Manual reset input (MR)
■ Low supply current - 3 µA (typ)
■ Guaranteed RST (RST) assertion down to
V
= 1.0 V
CC
SOT23-5 (WY)
■ Operating temperature: –40 to +85°C
(industrial grade)
■ RoHS compliance
Lead-free components are compliant with the
RoHS directive
a. Other t and watchdog timings are
rec
offered. Minimum order quantities may
apply. Contact local sales office for
availability.
Table 1.
Device summary
Reset output
Manual reset
input
Part number
Watchdog input
Active-low
(push-pull)
Active-high
(push-pull)
Active-low
(open drain)
STM6321
✔
✔
✔
✔
✔
✔
STM6322
STM6821
STM6822
STM6823
STM6824
STM6825
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
June 2008
Rev 8
1/28
www.st.com
1
Contents
STM6321/6322STM6821/6822/6823/6824/6825
Contents
1
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.1
Pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.1.1
1.1.2
1.1.3
1.1.4
1.1.5
Active-low, push-pull reset output (RST) - STM6822/6823/6824/6825 . . 7
Active-low, open drain reset output (RST) - STM6321/6322/6822 . . . . . 7
Push-button reset input (MR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Watchdog input (WDI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Active-high reset output (RST) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.1
2.2
2.3
2.4
2.5
Reset output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Open drain RST output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Push-button reset input (STM6322/6821/6822/6823/6825) . . . . . . . . . . . 11
Watchdog input (STM6321/6821/6822/6823/6824) . . . . . . . . . . . . . . . . . 11
Applications information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.5.1
2.5.2
Watchdog input current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Ensuring a valid reset output down to V = 0 V . . . . . . . . . . . . . . . . . . 11
CC
2.6
Interfacing to microprocessors with bidirectional reset pins . . . . . . . . . . . 12
3
4
5
6
7
8
Typical operating characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
2/28
STM6321/6322STM6821/6822/6823/6824/6825
List of tables
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Device summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Operating and AC measurement conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
DC and AC characteristic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
SOT23-5 – 5-lead small outline transistor package mechanical data. . . . . . . . . . . . . . . . . 24
Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Marking description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3/28
List of figures
STM6321/6322STM6821/6822/6823/6824/6825
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Logic diagram (STM6821/6822/6823) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Logic diagram (STM6321/6322/6824/6825) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
STM6822/6823 SOT23-5 connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
STM6821 SOT23-5 connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
STM6322/6825 SOT23-5 connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
STM6321/6824 SOT23-5 connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Block diagram (STM6821/6822/6823) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Block diagram (STM6321/6824) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Block diagram (STM6322/6825) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 10. Hardware hookup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 11. STM6321/6322/6822 open drain RST output with multiple supplies . . . . . . . . . . . . . . . . . 10
Figure 12. Ensuring RST valid to V = 0, (active-low push-pull outputs). . . . . . . . . . . . . . . . . . . . . . 12
CC
Figure 13. Ensuring RST valid to V = 0, (active-high, push-pull outputs) . . . . . . . . . . . . . . . . . . . . 12
CC
Figure 14. Interfacing to microprocessors with bidirectional reset I/O . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 15.
V
-to-reset output delay vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
CC
Figure 16. Supply current vs. temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 17. MR-to-reset output delay vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 18. Normalized power-up t vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
rec
Figure 19. Normalized reset threshold voltage vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 20. Normalized power-up watchdog time-out period . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 21. Voltage output low vs. I
Figure 22. Voltage output high vs. I
SINK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
SOURCE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Figure 23. Maximum transient duration vs. reset threshold overdrive . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 24. AC testing input/output waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 25. MR timing waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 26. Watchdog timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 27. SOT23-5 – 5-lead small outline transistor package mechanical drawing . . . . . . . . . . . . . . 23
4/28
STM6321/6322STM6821/6822/6823/6824/6825
Description
1
Description
The STM6xxx supervisors are self-contained devices which provide microprocessor
supervisory functions. A precision voltage reference and comparator monitors the V input
CC
for an out-of-tolerance condition. When an invalid V condition occurs, the reset output
CC
(RST) is forced low (or high in the case of RST). These devices also offer a watchdog timer
(except for STM6322/6825) and/or a push-button (MR) reset input.
These devices are available in a standard 5-pin SOT23 package.
Figure 1.
Logic diagram (STM6821/6822/6823)
V
CC
WDI
MR
(1)
STM6XXX
RST (RST)
V
SS
AI09128
1. For STM6821 only.
Figure 2.
Logic diagram (STM6321/6322/6824/6825)
V
CC
RST
RST
(1)
STM6XXX
(WDI) MR
V
SS
AI09129
1. For STM6321/6824.
Table 2.
MR
Signal names
Push-button reset input
Watchdog input
WDI
RST
RST
VCC
VSS
Active-low reset output
Active-high reset output
Supply voltage
Ground
5/28
Description
STM6321/6322STM6821/6822/6823/6824/6825
STM6822/6823 SOT23-5 connections
Figure 3.
SOT23-5
(1)
V
5
1
2
3
CC
RST
V
SS
WDI
MR
4
AI09130a
1. Open drain for STM6822.
Figure 4.
STM6821 SOT23-5 connections
SOT23-5
(1)
V
5
1
2
3
CC
RST
V
SS
WDI
MR
4
AI12285
1. Push-pull only.
Figure 5.
STM6322/6825 SOT23-5 connections
SOT23-5
(1)
5
V
1
2
3
RST
CC
V
SS
(2)
4
MR
RST
AI09131a
1. Open drain for STM6322.
2. Push-pull only.
Figure 6.
STM6321/6824 SOT23-5 connections
SOT23-5
(1)
5
V
1
2
3
RST
CC
V
SS
(2)
4
WDI
RST
AI12286
1. Open drain for STM6321.
2. Push-pull only.
6/28
STM6321/6322STM6821/6822/6823/6824/6825
Description
1.1
Pin descriptions
1.1.1
Active-low, push-pull reset output (RST) - STM6822/6823/6824/6825
Pulses low when triggered, and stays low whenever V is below the reset threshold or
CC
when MR is a logic low. It remains low for t after either V rises above the reset
rec
CC
threshold, the watchdog triggers a reset, or MR goes from low to high.
1.1.2
1.1.3
1.1.4
1.1.5
Active-low, open drain reset output (RST) - STM6321/6322/6822
Pulses low when triggered, and stays low whenever V is below the reset threshold or
CC
when MR is a logic low. It remains low for t after either V rises above the reset
rec
CC
threshold, the watchdog triggers a reset, or MR goes from low to high. Connect a pull-up
resistor to supply voltage.
Push-button reset input (MR)
A logic low on MR asserts the reset output. Reset remains asserted as long as MR is low
and for t after MR returns high. This active-low input has an internal 52 kΩ pull-up. It can
rec
be driven from a TTL or CMOS logic line, or shorted to ground with a switch. Leave open if
unused.
Watchdog input (WDI)
If WDI remains high or low for at least 1.6s, the internal watchdog timer expires and reset is
asserted. The internal watchdog timer clears while reset is asserted or when WDI sees a
rising or falling edge. The watchdog function CAN be disabled if WDI is left unconnected or
is connected to a tri-state buffer output.
Active-high reset output (RST)
Active-high, push-pull reset output; inverse of RST.
Table 3.
Pin functions
Pin
Name
Function
STM6822
STM6823
STM6321
STM6322
STM6825
STM6821
STM6824
1
3
—
3
1
—
4
1
4
RST
MR
Active-low reset output
Push-button reset input
Watchdog Input
4
4
—
3
WDI
RST
VCC
VSS
—
5
1
3
Active-high reset output
Supply voltage
5
5
5
2
2
2
2
Ground
7/28
Description
STM6321/6322STM6821/6822/6823/6824/6825
Figure 7.
Block diagram (STM6821/6822/6823)
WDI
Transitional
Detector
WATCHDOG
TIMER
WDI
V
CC
t
(1,2)
rec
RST (RST)
COMPARE
V
V
RST
Generator
CC
MR
AI09132a
1. Push-pull for STM6823, open drain for STM6822.
2. Active-high (push-pull) for STM6821.
Figure 8.
Block diagram (STM6321/6824)
WDI
Transitional
Detector
WATCHDOG
TIMER
WDI
(1)
RST
V
CC
t
rec
COMPARE
V
RST
Generator
(2)
RST
A12287
3. Active-low (open drain) for STM6321, active-low (push-pull) for STM6824.
4. Push-pull only.
Figure 9.
Block diagram (STM6322/6825)
(1)
RST
V
CC
t
rec
COMPARE
V
V
RST
Generator
CC
(2)
RST
MR
AI12288
1. Active-low (open drain) for STM6322, active-low (push-pull) for STM6825.
2. Push-pull only.
8/28
STM6321/6322STM6821/6822/6823/6824/6825
Description
Figure 10. Hardware hookup
VCC
VCC
0.1μF
STM6XXX
WDI(1)
MR(2)
From Microprocessor
Push-button
RST (RST)(3)
To Microprocessor Reset
To Microprocessor Reset
RST(4)
AI09133
1. For STM6321/6821/6822/6823/6824
2. For STM6322/6821/6822/6823/6825
3. For STM6821/ (RST output only)
4. For STM6321/6322/6824/6825 (both RST and RST outputs)
9/28
Operation
STM6321/6322STM6821/6822/6823/6824/6825
2
Operation
2.1
Reset output
The STM6xxx Supervisor asserts a reset signal to the MCU whenever V goes below the
CC
reset threshold (V
), a watchdog time-out occurs, or when the Push-button Reset Input
RST
(MR) is taken low. Reset is guaranteed valid for V < V
down to V =1 V for T = 0°C
CC
RST
CC A
to 85°C.
During power-up, once V exceeds the reset threshold an internal timer keeps reset low
CC
for the reset time-out period, t . After this interval reset is de-asserted.
rec
Each time RST is asserted, it stays low for at least the reset time-out period (t ). Any time
rec
V
V
goes below the reset threshold the internal timer clears. The reset timer starts when
returns above the reset threshold.
CC
CC
2.2
Open drain RST output
The STM6321/6322/6822 have an active-low, open drain reset output. This output structure
will sink current when RST is asserted. Connect a pull-up resistor from RST to any supply
voltage up to 6 V (see Figure 11). Select a resistor value large enough to register a logic
low, and small enough to register a logic high while supplying all input current and leakage
paths connected to the reset output line. A 10 kΩ pull-up resistor is sufficient in most
applications.
Figure 11. STM6321/6322/6822 open drain RST output with multiple supplies
3.3V
5.0V
V
CC
STM6XXX
5V System
10k
(1)
MR
(2)
(3)
WDI
RST
RST
GND
AI09137
1. STM6322/6822
2. STM6321/6822
3. STM6321/6322
10/28
STM6321/6322STM6821/6822/6823/6824/6825
Operation
2.3
Push-button reset input (STM6322/6821/6822/6823/6825)
A logic low on MR asserts reset. Reset remains asserted while MR is low, and for t (see
rec
Figure 25 on page 19) after it returns high. The MR input has an internal 52 kΩ pull-up
resistor, allowing it to be left open if not used. This input can be driven with TTL/CMOS-logic
levels or with open-drain/collector outputs. Connect a normally open momentary switch from
MR to GND to create a manual reset function; external debounce circuitry is not required. If
MR is driven from long cables or the device is used in a noisy environment, connect a 0.1 µF
capacitor from MR to GND to provide additional noise immunity. MR may float, or be tied to
V
when not used.
CC
2.4
Watchdog input (STM6321/6821/6822/6823/6824)
The watchdog timer can be used to detect an out-of-control MCU. If the MCU does not
toggle the Watchdog Input (WDI) within t
watchdog timer is cleared by either:
(1.6 sec), the reset is asserted. The internal
WD
1. a reset pulse, or
2. by toggling WDI (high-to-low or low-to-high), which can detect pulses as short as 50 ns.
The timer remains cleared and does not count for as long as reset is asserted. As soon as
reset is released, the timer starts counting.
Note:
The watchdog function may be disabled by floating WDI or tri-stating the driver connected to
WDI. When tri-stated or disconnected, the maximum allowable leakage current is 10 µA and
the maximum allowable load capacitance is 200 pF.
2.5
Applications information
2.5.1
Watchdog input current
The WDI input is internally driven through a buffer and series resistor from the watchdog
counter. For minimum watchdog input current (minimum overall power consumption), leave
WDI low for the majority of the watchdog time-out period. When high, WDI can draw as
much as 160µA. Pulsing WDI high at a low duty cycle will reduce the effect of the large input
current. When WDI is left unconnected, the watchdog timer is serviced within the watchdog
time-out period by a low-high-low pulse from the counter chain.
2.5.2
Ensuring a valid reset output down to V = 0 V
CC
The STM6xxx supervisors are guaranteed to operate properly down to V = 1 V. In
CC
applications that require valid reset levels down to V = 0, a pull-down resistor to active-
CC
low outputs (push/pull only, see Figure 12 on page 12) and a pull-up resistor to active-high
outputs (push/pull only, see Figure 13 on page 12) will ensure that the reset line is valid
while the reset output can no longer sink or source current. This scheme does not work with
the open drain outputs of the STM6321/6322/6822.
The resistor value used is not critical, but it must be large enough not to load the reset
output when V is above the reset threshold. For most applications, 100 kΩ is adequate.
CC
11/28
Operation
STM6321/6322STM6821/6822/6823/6824/6825
Figure 12. Ensuring RST valid to V = 0, (active-low push-pull outputs)
CC
STM6XXX
V
CC
V
CC
GND
RST
R1
AI09138
Figure 13. Ensuring RST valid to V = 0, (active-high, push-pull outputs)
CC
V
CC
STM6XXX
R1
V
CC
GND
RST
AI09139
1. This configuration does not work on open drain outputs of the STM6321/6322/6822.
2.6
Interfacing to microprocessors with bidirectional reset pins
Microprocessors with bidirectional reset pins can contend with the STM6321/6322/6821/
6822/6823/6824/6825 reset output. For example, if the reset output is driven high and the
microprocessor wants to pull it low, signal contention will result. To prevent this from
occurring, connect a 4.7 kΩ resistor between the reset output and the microprocessor’s
reset I/O as in Figure 14.
Figure 14. Interfacing to microprocessors with bidirectional reset I/O
Buffered Reset to other
System Components
V
V
CC
CC
STM6XXX
RST
Microprocessor
4.7k
RST
GND
GND
AI09135
12/28
STM6321/6322STM6821/6822/6823/6824/6825
Typical operating characteristics
3
Typical operating characteristics
Figure 15. V -to-reset output delay vs. temperature
CC
35
30
25
20
15
10
5
0
–40
–20
0
20
40
60
80
Temperature (˚C)
AI09627a
Figure 16. Supply current vs. temperature
7
6
5
4
3
2
1
0
V
V
= 3V
= 5V
CC
CC
–40
–20
0
20
40
60
80
Temperature (˚C)
AI09628a
13/28
Typical operating characteristics
STM6321/6322STM6821/6822/6823/6824/6825
Figure 17. MR-to-reset output delay vs. temperature
600
500
400
300
200
100
0
–40
–20
0
20
40
60
80
Temperature (˚C)
AI09669
Figure 18. Normalized power-up t vs. temperature
rec
1.05
1.04
1.03
1.02
1.01
1.00
0.99
–40
–20
0
20
40
60
80
Temperature (˚C)
AI09670
14/28
STM6321/6322STM6821/6822/6823/6824/6825
Typical operating characteristics
Figure 19. Normalized reset threshold voltage vs. temperature
1.05
1.04
1.03
1.02
1.01
1.00
0.99
0.98
0.97
0.96
0.95
–40
–20
0
20
40
60
80
Temperature (˚C)
AI09631a
Figure 20. Normalized power-up watchdog time-out period
1.05
1.04
1.03
1.02
1.01
1.00
0.99
–40
–20
0
20
40
60
80
Temperature (˚C)
AI09671
15/28
Typical operating characteristics
Figure 21. Voltage output low vs. I
STM6321/6322STM6821/6822/6823/6824/6825
SINK
0.35
0.30
0.25
0.20
0.15
0.10
0.05
0.00
V
= 2.9V
CC
0
1
2
3
4
5
6
I
(mA)
SINK
AI09634a
Figure 22. Voltage output high vs. I
SOURCE
2.92
2.90
2.88
2.86
2.84
V
= 2.9V
CC
2.82
2.80
2.78
2.76
2.74
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
I
(mA)
SOURCE
AI09635a
16/28
STM6321/6322STM6821/6822/6823/6824/6825
Typical operating characteristics
Figure 23. Maximum transient duration vs. reset threshold overdrive
35
30
25
20
15
10
5
S
Z
L
0
0
20
40
60
80
100
120
140
160
180
200
Reset Threshold Overdrive (mV)
AI09637a
17/28
Maximum ratings
STM6321/6322STM6821/6822/6823/6824/6825
4
Maximum ratings
Stressing the device above the rating listed in Table 4 may cause permanent damage to the
device. These are stress ratings only and operation of the device at these or any other
conditions above those indicated in the operating sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect device
reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality
documents.
Table 4.
Symbol
TSTG
Absolute maximum ratings
Parameter
Value
Unit
Storage temperature (VCC off)
Lead solder temperature for 10 seconds
Input or output voltage
Supply voltage
–55 to 150
°C
°C
V
(1)
TSLD
VIO
VCC
IO
260
–0.3 to VCC + 0.3
–0.3 to 7.0
20
V
Output current
mA
mW
PD
Power dissipation
320
1. Reflow at peak temperature of 260°C (total thermal budget not to exceed 245°C for greater than 30 seconds).
18/28
STM6321/6322STM6821/6822/6823/6824/6825
DC and AC parameters
5
DC and AC parameters
This section summarizes the operating measurement conditions, and the DC and AC
characteristics of the device. The parameters in the DC and AC characteristics tables that
follow, are derived from tests performed under the measurement conditions summarized in
Table 5. Designers should check that the operating conditions in their circuit match the
operating conditions when relying on the quoted parameters.
Table 5.
Operating and AC measurement conditions
Parameter
STM6xxx
Unit
VCC supply voltage
1.0 to 5.5
–40 to 85
≤ 5
V
°C
ns
V
Ambient operating temperature (TA)
Input rise and fall times
Input pulse voltages
0.2 to 0.8VCC
0.3 to 0.7VCC
Input and output timing ref. voltages
V
Figure 24. AC testing input/output waveforms
0.8V
CC
0.7V
CC
CC
0.3V
0.2V
CC
AI02568
Figure 25. MR timing waveform
MR
tMLRL
RST (1)
trec
tMLMH
AI07837a
1. RST for STM6322/6821/6825.
Figure 26. Watchdog timing
VCC
trec
RST
tWD
WDI
AI09136
19/28
DC and AC parameters
STM6321/6322STM6821/6822/6823/6824/6825
Table 6.
Sym
DC and AC characteristic
Alter-
Description
Test condition (1)
Min
Typ
Max
Unit
native
VCC
Operating voltage
1.2 (2)
5.5
12
17
8
V
T/S/R/Z/Y (VCC < 3.6 V)
L/M (VCC < 5.5 V)
4
6
3
µA
µA
µA
VCC supply current
(MR and WDI unconnected)
ICC
VCC supply current
T/S/R/Z/Y (VCC < 3.6 V)
(MR unconnected;
STM6322/6825)
L/M (VCC < 5.5 V)
3
12
µA
Input leakage current
0V = VIN = VCC
–1
+1
µA
µA
µA
ILI
WDI = VCC, time average
WDI = GND, time average
120
–15
160
Input leakage current
(WDI)(3)
–20
–1
VCC > VRST
,
Open drain reset output
leakage current
ILO
+1
µA
Reset not asserted
VRST > 4.0 V
2.0
V
V
V
V
V
V
VIH
VIH
VIL
VIL
Input high voltage (MR)
Input high voltage (WDI) (4)
Input low voltage (MR)
VRST < 4.0 V
0.7VCC
0.7VCC
VRST (max) < VCC < 5.5 V
VRST > 4.0 V
0.8
VRST < 4.0 V
0.3VCC
0.3VCC
Input low voltage (WDI) (4)
VRST (max) < VCC < 5.5 V
VCC ≥ 1.0 V, ISINK = 50 µA,
0.3
0.3
0.3
0.4
0.3
0.4
V
V
V
V
V
V
Reset asserted
VCC ≥ 1.2 V, ISINK = 100 µA,
Reset asserted
Output low voltage (RST;
push-pull or open drain)
VCC ≥ 2.7 V, ISINK = 1.2 mA,
Reset asserted
VOL
VCC ≥ 4.5 V, ISINK = 3.2 mA,
Reset asserted
VCC ≥ 2.7 V, ISINK = 1.2 mA,
Reset not asserted
Output low voltage (RST;
push-pull only)
VCC ≥ 4.5 V, ISINK = 3.2 mA,
Reset not asserted
20/28
STM6321/6322STM6821/6822/6823/6824/6825
DC and AC parameters
Table 6.
Sym
DC and AC characteristic (continued)
Alter-
native
Description
Test condition (1)
Min
Typ
Max
Unit
V
VCC ≥ 2.7 V, ISOURCE = 500 µA,
0.8VCC
0.8VCC
0.8VCC
Reset not asserted
Output high voltage (RST)
VCC ≥ 4.5 V, ISOURCE = 800 µA
V
, Reset not asserted
VCC ≥ 1.0 V, ISOURCE = 1 µA,
Reset asserted (0°C to 85°C)
V
VOH
VCC ≥ 1.5 V, ISOURCE = 100 µA,
0.8VCC
0.8VCC
0.8VCC
V
V
V
Reset asserted
Output high voltage (RST)
VCC ≥ 2.55 V, ISOURCE = 500 µA,
Reset asserted
VCC ≥ 4.25 V, ISOURCE = 800 µA,
Reset asserted
Reset Thresholds
25°C
4.561 4.630 4.699
V
V
STM6xxxL
–40 to 85°C 4.514
4.746
25°C
4.314 4.390 4.446
V
STM6xxxM
–40 to 85°C 4.270
4.490
V
25°C
3.040 3.080 3.110
V
STM6xxxT
–40 to 85°C 3.000
3.150
V
25°C
2.890 2.930 2.960
V
(5)
VRST
Reset threshold
STM6xxxS
–40 to 85°C 2.857
3.000
V
25°C
2.590 2.630 2.660
V
STM6xxxR
–40 to 85°C 2.564
2.696
V
25°C
2.266 2.300 2.335
V
STM6xxxZ
–40 to 85°C 2.243
2.358
V
25°C
1.970 2.000 2.030
V
STM6xxxY
–40 to 85°C 1.950
2.050
V
L/M versions
10
5
mV
mV
Reset threshold hysteresis
T/S/R/Z/Y versions
VCC to RST delay
20
µs
(VRST – VCC = 100 mV, VCC
falling at 1 mV/µs)
A
Blank
J
1
1.4
200
360
2
ms
ms
ms
(6)
trec
Reset pulse width
140
240
280
480
21/28
DC and AC parameters
STM6321/6322STM6821/6822/6823/6824/6825
Table 6.
Sym
DC and AC characteristic (continued)
Alter-
Description
Test condition (1)
Min
Typ
Max
Unit
native
Reset threshold
temperature coefficient
40
ppm/C
Push-button Reset Input
tMLMH
tMLRL
tMR
MR pulse width
MR to RST output delay
MR glitch immunity
MR pull-up resistor
1
µs
ns
ns
kΩ
tMRD
500
100
52
35
75
Watchdog Timer
(6)
tWD
Watchdog timeout period
WDI pulse width(7)
1.12
50
1.60
2.24
s
VCC ≥ 3.0 V
ns
1. Valid for ambient operating temperature: TA = –40 to 85°C; VCC = 4.5 to 5.5 V for “L/M” versions; VCC = 2.7 to 3.6 V for
“T/S/R” versions; and VCC = 1.2 to 2.75 V for “Z/Y” version (except where noted).
2. VCC (min) = 1.0 V for TA = 0 to +85°C.
3. WDI input is designed to be driven by a three-state output device. To float WDI, the “high-impedance mode” of the output
device must have a maximum leakage current of 10 µA and a maximum output capacitance of 200 pF. The output device
must also be able to source and sink at least 200 µA when active.
4. WDI is internally serviced within the watchdog period if WDI is left unconnected.
5. The leakage current measured on the RST pin is tested with the reset asserted (output high impedance).
6. Other trec and watchdog timings are offered. Minimum order quantities may apply. Contact local sales office for availability.
7. For VCC < 3.0 V, tWD(min) = 100 ns.
22/28
STM6321/6322STM6821/6822/6823/6824/6825
Package mechanical data
6
Package mechanical data
®
In order to meet environmental requirements, ST offers these devices in ECOPACK
packages. These packages have a Lead-free second level interconnect. The category of
second Level Interconnect is marked on the package and on the inner box label, in
compliance with JEDEC Standard JESD97. The maximum ratings related to soldering
conditions are also marked on the inner box label. ECOPACK is an ST trademark.
ECOPACK specifications are available at: www.st.com.
Figure 27. SOT23-5 – 5-lead small outline transistor package mechanical drawing
SOT23-5L
1. Drawing is not to scale.
23/28
Package mechanical data
STM6321/6322STM6821/6822/6823/6824/6825
Table 7.
Symb
SOT23-5 – 5-lead small outline transistor package mechanical data
mm
inches
Typ
Min
Max
Typ
Min
Max
A
A1
A2
B
1.20
0.90
1.45
0.15
1.30
0.50
0.20
3.00
0.047
0.035
0.057
0.006
0.051
0.020
0.008
0.118
1.05
0.40
0.15
2.90
1.90
2.80
0.95
1.60
0.90
0.35
0.09
2.80
0.041
0.016
0.006
0.114
0.075
0.110
0.037
0.063
0.035
0.014
0.004
0.110
C
D
D1
E
2.60
3.00
0.102
0.118
e
F
1.50
0°
1.75
10°
0.059
0°
0.069
10°
K
L
0.35
0.10
0.60
0.014
0.004
0.024
24/28
STM6321/6322STM6821/6822/6823/6824/6825
Part numbering
7
Part numbering
Table 8.
Example:
Ordering information scheme
STM6xxx
L
WY
6
E
Device type
STM6xxx
Reset threshold voltage
L: VRST = 4.514 to 4.746 V
M: VRST = 4.270 to 4.490 V
T: VRST = 3.000 to 3.150 V
S: VRST = 2.850 to 3.000 V
R: VRST = 2.564 to 2.696 V
Z: VRST = 2.243 to 2.358 V
Y: VRST = 1.950 to 2.050 V
Reset pulse width (1)
A: trec = 1 to 2 ms
Blank: trec = 140 to 280 ms
J: trec = 240 to 480 ms
Package
WY = SOT23-5
Temperature range
6 = –40 to 85°C
Shipping method
E = ECOPACK® package, tubes
F = ECOPACK® package, tape & reel
1. Contact local sales office for availability. Other trec and watchdog timings are offered. Minimum order
quantities may apply. Contact local sales office for availability.
For other options, or for more information on any aspect of this device, please contact the
ST sales office nearest you.
25/28
Part numbering
STM6321/6322STM6821/6822/6823/6824/6825
Table 9.
Part number
STM6321LWY6F
Marking description
Reset threshold (V)
Reset pulse width (ms)
Topside marking
4.630
4.390
4.390
3.080
2.930
2.630
4.630
4.390
3.080
2.930
2.630
4.630
4.390
3.080
2.930
2.630
4.630
4.390
3.080
2.930
2.630
2.300
2.000
4.630
4.390
3.080
3.080
2.930
2.930
2.630
2.630
4.630
4.390
3.080
2.930
2.630
4.630
4.390
3.080
2.930
2.630
200
1.4
5AUx
5CRx
5AVx
5AWx
5AXx
5AYx
5BAx
5BBx
5BCx
5BDx
5BEx
5BGx
5BHx
5BJx
5BKx
5BLx
5BNx
5BPx
5BQx
5BRx
5BSx
5BTx
5CTx
5BUx
5BVx
5CMx
5BWx
5CNx
5BXx
5CPx
5BYx
5CAx
5CBx
5CCx
5CDx
5CEx
5CGx
5CHx
5CJx
5CKx
5CLx
STM6321MAWY6F
STM6321MWY6F
STM6321TWY6F
STM6321SWY6F
STM6321RWY6F
STM6322LWY6F
STM6322MWY6F
STM6322TWY6F
STM6322SWY6F
STM6322RWY6F
STM6821LWY6F
STM6821MWY6F
STM6821TWY6F
STM6821SWY6F
STM6821RWY6F
STM6822LWY6F
STM6822MWY6F
STM6822TWY6F
STM6822SWY6F
STM6822RWY6F
STM6822ZWY6F
STM6822YWY6F
STM6823LWY6F
STM6823MWY6F
STM6823TJWY6F
STM6823TWY6F
STM6823SJWY6F
STM6823SWY6F
STM6823RJWY6F
STM6823RWY6F
STM6824LWY6F
STM6824MWY6F
STM6824TWY6F
STM6824SWY6F
STM6824RWY6F
STM6825LWY6F
STM6825MWY6F
STM6825TWY6F
STM6825SWY6F
STM6825RWY6F
200
200
200
200
200
200
200
200
200
200
200
200
200
200
200
200
200
200
200
200
200
200
200
280
200
280
200
280
200
200
200
200
200
200
200
200
200
200
200
Note:
Where “x” = assembly work week (A to Z), such that “A” = WW01-02, “B” = WW03-04, and
so forth.
26/28
STM6321/6322STM6821/6822/6823/6824/6825
Revision history
8
Revision history
Table 10. Document revision history
Date
Revision
Changes
25-Aug-2004
15-Dec-2004
10-Mar-2005
17-Jun-2005
1
2
3
4
First draft
Update characteristics (Figure 15, 16, 17; Table 6, and 8)
Document promoted to Datasheet status
Package marking update (Table 9)
Update characteristics, Lead-free text, availability (Figure 3, 4, 5, 6,
7, 8, and 9; Table 1, 6, 8, and 9)
11-Apr-2006
5
11-Aug-2006
25-May-2007
6
7
Update Description, Table 8, and 9.
Formatting changes, updated Table 9.
Updated cover page; updated reset threshold values in Table 6, 8,
and 9; addition of text to Section 6; updated Figure 27 and Table 6
and 7; minor text changes.
03-Jun-2008
8
27/28
STM6321/6322STM6821/6822/6823/6824/6825
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