STM6502WEABDG6F [STMICROELECTRONICS]
Dual push-button Smart ResetTM with user-adjustable setup delays; 与用户可调的建立延迟的双按钮式智能ResetTM
| 型号： | STM6502WEABDG6F |
| 厂家： | 
ST |
| 描述： | Dual push-button Smart ResetTM with user-adjustable setup delays |
| 文件： | 总29页 (文件大小：450K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
STM6502, STM6503
STM6504, STM6505
Dual push-button Smart ResetTM with user-adjustable setup delays
Features
■ Dual Smart Reset push-button inputs with
extended reset setup delay
■ Adjustable Smart Reset setup delay (t
):
SRC
by external capacitor or three-state logic
(product options): t
= 2, 6, 10 s (min.)
SRC
■ Power-on reset
TDFN8 (DG)
2 mm x 2 mm
■ Single RST output, active-low, open-drain
■ Factory-programmable thresholds to monitor
in the range of 1.575 to 4.625 V typ.
V
CC
Applications
■ Operating voltage 1.0 V (active-low output
■ Mobile phones, smartphones
■ e-books
valid) to 5.5 V
■ Low supply current
■ MP3 players
■ Operating temperature:
industrial grade –40 °C to +85 °C
■ Games
■ Portable navigation devices
■ TDFN8 package: 2 mm x 2 mm x 0.75 mm
■ RoHS compliant
■ Any application that requires delayed reset
push-button(s) response for improved system
stability
Table 1.
Device summary
Voltage inputs
t
Reset or Power
Good outputs
SRC
Smart Reset inputs
programming
Three-
state
Part
number
Package
SRE
immediate,
independent
Ext.
SRC pin
input
V
V
SR0
SR1
RST
BLD
CC
BAT
TSR
(1)
STM6502
STM6503
STM6504
STM6505
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
TDFN-8L
TDFN-8L
TDFN-8L
TDFN-8L
(1)
✓
✓
✓
✓
1. Contact local ST sales office for availability.
June 2010
Doc ID 16101 Rev 5
1/29
www.st.com
1
Contents
STM6502, STM6503, STM6504, STM6505
Contents
1
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.1
1.2
Smart Reset devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
1.2.1
1.2.2
1.2.3
1.2.4
1.2.5
1.2.6
Power supply (V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
CC
Ground (V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
SS
Primary Smart Reset input (SR0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Secondary Smart Reset input (SR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Edge-triggered Smart Reset input (SRE pin) – STM6504 only . . . . . . . 11
Adjustable delay of Smart Reset input (SRC pin) – STM6502
and STM6505 only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
1.2.7
Programmable Smart Reset input delay (TSR pin) – STM6503
and STM6504 only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
1.2.8
1.2.9
Reset output (RST) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Battery monitoring input (V
) – STM6505 only . . . . . . . . . . . . . . . . . 12
BAT
1.2.10 Battery low detect output (BLD) – STM6505 only . . . . . . . . . . . . . . . . . 12
2
3
4
5
6
7
8
Typical operating characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Package marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
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STM6502, STM6503, STM6504, STM6505
List of tables
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Device summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
t
programmed by an ideal external capacitor – STM6502 and STM6505 . . . . . . . . . . 11
SRC
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Operating and measurement conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
DC and AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
V
voltage thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
CC
TDFN – 8-lead 2 x 2 x 0.75 mm, 0.5 mm pitch package mechanical data . . . . . . . . . . . . . 21
Parameter for landing pattern - TDFN – 8-lead 2 x 2 mm package . . . . . . . . . . . . . . . . . . 22
Carrier tape dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Reel dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Package marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
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STM6502, STM6503, STM6504, STM6505
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Logic diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Pin connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Block diagram - STM6502, STM6503, STM6504 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Block diagram - STM6505 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Single-button Smart Reset typical hookup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Dual-button Smart Reset typical hookup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
STM6502, STM6503 timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
STM6504 timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
STM6505 timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 10. Supply current (I ) vs. temperature (STM6505) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
CC
Figure 11. Smart Reset delay (t
) vs. temperature, C
= 0.62 µF (STM6505) . . . . . . . . . . . . . . 13
SRC
SRC
Figure 12. Reset threshold (V
) vs. temperature, “S” threshold option, V falling (STM6505) . . . 14
RST
CC
Figure 13.
V
monitoring threshold (V
) vs. temperature, falling (STM6505) . . . . . . . . . . . . . . 14
BATTH
BAT
Figure 14. AC testing input/output waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 15. TDFN – 8-lead 2 x 2 x 0.75 mm, 0.5 mm pitch package outline. . . . . . . . . . . . . . . . . . . . . 21
Figure 16. Landing pattern - TDFN – 8-lead 2 x 2 mm without thermal pad . . . . . . . . . . . . . . . . . . . . 22
Figure 17. Carrier tape . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 18. Reel dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 19. Tape trailer/leader. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 20. Pin 1 orientation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 21. Package marking, top view. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
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STM6502, STM6503, STM6504, STM6505
Description
1
Description
STM6502 has two combined Smart Reset inputs (SR0 and SR1) with delayed Smart Reset
setup time (t ) programmed by an external capacitor on the SRC pin.
SRC
STM6503 is similar to STM6502, has two combined delayed Smart Reset inputs (SR0, SR1)
and three user-selectable delayed Smart Reset setup time (t ) options of 2 s, 6 s and
SRC
10 s through a three-state TSR input pin: when connected to ground, t
= 2 s; when left
SRC
open, t
= 6 s; when connected to V , t
= 10 s (all the times are minimum).
SRC
CC SRC
STM6504 has two independent Smart Reset inputs. SR0 provides the delayed Smart Reset
setup time (t ) function with three user-selectable t options through a three-state TSR
SRC
SRC
input pin: when connected to ground, t
= 2 s; when left open, t
= 6 s; when
SRC
SRC
connected to V , t
= 10 s (all the times are minimum). SRE provides instant reset. SRE
CC SRC
is edge-triggered with a special debounce time (t
edge after a valid reset period.
= 240 ms min.) at the falling
DEBOUNCE
STM6505 has two combined delayed Smart Reset inputs (SR0, SR1) and provides an
adjustable reset delay setup time via an external capacitor connected to the SRC pin.
The RST output depends also on the V monitoring threshold. STM6505 also provides
CC
independent low battery detect (BLD) output controlled by the secondary external input
voltage V . V
is monitored for low voltage and provides an indication on the battery low
BAT BAT
detect output pin (BLD). V
threshold is 1.25 V, fixed, and an external resistor divider is to
BAT
be used to set the actual battery voltage threshold. V
threshold hysteresis is 8 mV typ.
BAT
(16 mV max.). V
is voltage monitoring input only, the device is powered only from the
BAT
V
pin; V must be ≥ 1.575 V for proper operation of the V
comparator.
CC
CC
BAT
1.1
Smart Reset devices
The Smart Reset device family STM65xx provides a useful feature that ensures inadvertent
short reset push-button closures do not cause system resets. This is done by implementing
extended Smart Reset input delay (t
). Once the valid Smart Reset input levels and setup
SRC
delay are met, the device generates an output reset pulse with user-programmable timeout
period (t ).
REC
The Smart Reset inputs can be also connected to the applications interrupt to allow the
control of both the interrupt pin and the hard reset functions. If the push-buttons are closed
for a short time, the processor is only interrupted. If the system still does not respond
properly, holding the push-buttons for the extended setup time (t
) causes hard reset of
SRC
the processor through the reset outputs. The Smart Reset feature helps significantly
increase system stability.
The STM65xx family of Smart Reset devices consists of low current microprocessor reset
circuits targeted at applications such as MP3 players, navigation, smartphones or mobile
phones; generally any application that requires delayed reset push-button(s) response for
improved system stability. The STM65xx devices feature single or dual Smart Reset inputs
(SR). The delayed Smart Reset setup time (t
) options of 2 s, 6 s and 10 s
SRC
(all min.) are adjustable by an external capacitor on the SRC pin or selectable by three-state
logic. The delayed setup period ignores switch closures shorter than t
unwanted resets.
, thus preventing
SRC
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Description
STM6502, STM6503, STM6504, STM6505
The STM65xx devices have active-low (optionally active-high) open-drain reset (RST)
output(s) with or without internal pull-up resistor or push-pull as output options, with factory-
programmed or capacitor-adjustable or push-buttons defined output reset pulse duration,
with or without power-on reset function.
Some devices also have an undervoltage monitoring feature: the reset output is also
asserted when the monitored supply voltage V drops below the specified threshold. The
CC
reset output remains asserted for the reset timeout period (t
voltage goes above the specified threshold.
) after the monitored supply
REC
Figure 1.
Logic diagrams
V
V
CC
CC
SR0
SR0
STM6502
SR1
SRC
SR1
TSR
RST
STM6503
RST
V
V
V
SS
SS
V
CC
CC
SR0
SR1
SRC
SR0
SRE
TSR
RST
BLD
RST
STM6504
STM6505
V
BAT
V
V
SS
SS
AM00378
Figure 2.
Pin connections
RST
1
2
8
V
CC
RST
1
2
8
7
V
CC
V
7
SR0
TSR
NC
V
SR0
SS
SS
STM
6502
STM
6503
SR1
NC
3
4
6
SR1
NC
3
4
6
5
SRC
NC
5
8
RST
1
2
8
7
V
RST
1
2
V
CC
CC
V
SR0
TSR
NC
V
7
SR0
SS
SS
STM
6505
STM
6504
SRE
NC
3
4
6
5
SR1
BLD
3
4
6
SRC
V
5
BAT
AM00379
6/29
Doc ID 16101 Rev 5
STM6502, STM6503, STM6504, STM6505
Description
Table 2.
Symbol
Signal names
Input/
Description
output
RST
BLD
Output Open-drain reset output, active-low.
Output Battery low detect output, active-low, open-drain. STM6505 only.
Primary push-button Smart Reset input. Active-low, with or without internal
SR0
SR1
Input
Input
65 kΩ pull-up to V (product options).
CC
Secondary push-button Smart Reset input - combines with the primary push-
button reset to provide setup delay time before reset. Active-low, with or without
internal 65 kΩ pull-up to V (product options).
CC
Secondary push-button Smart Reset input - provides instant Smart Reset. SRE
is edge-triggered with a special debounce time (t
the falling edge after a valid reset period. Active-high, no internal pull-up to V
STM6504 only.
= 240 ms min.) at
DEBOUNCE
SRE
SRC
Input
Input
.
CC
Smart Reset input delay setup control: connect to an external capacitor to adjust
the delay setup time (t ). STM6502 and STM6505 only.
SRC
A three-state Smart Reset input delay setup control. When connected to
ground, t = 2 s; when left open, t = 6 s; when connected to V
,
CC
SRC
SRC
t
= 10 s (all times are minimum). TSR is a DC-type input, intended to be
SRC
TSR
Input
either permanently grounded, permanently connected to V or permanently
CC
left open. If left open, for improved system glitch immunity it is strongly
recommended to connect a 0.1 µF decoupling ceramic capacitor between the
TSR and V pins. STM6503 and STM6504 only.
SS
Supply voltage input. Power supply for the device and an input for the monitored
V
Supply supply voltage. A 0.1 µF decoupling ceramic capacitor is recommended to be
connected between the V and V pins.
CC
CC
SS
V
Input
Supply Ground
No connect (not bonded); should be connected to V
Battery voltage monitoring input. STM6505 only.
BAT
V
SS
NC
.
SS
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Description
STM6502, STM6503, STM6504, STM6505
Figure 3.
Block diagram - STM6502, STM6503, STM6504
V
CC
V
COMPARE
RST
SR1
(SRE
Logic
Logic
STM6504
t
(1)
REC
generator
only)
RST
SR0
SRC (STM6502)
TSR (STM6503,
STM6504)
AM00352a
1. STM6504 only: SR0 and SRE are working independently. SRE is edge-triggered and has a special
debounce time (tDEBOUNCE = 240 ms min.) at the falling edge after a valid reset period.
Figure 4.
Block diagram - STM6505
6
"!4
6
#/-0!2%
#/-0!2%
"!44(
",$
6
##
6
234
T
2%#
6
##
234
GENERATOR
32ꢀ
32ꢂ
,OGIC
32#
!-ꢀꢀꢁꢂꢃB
8/29
Doc ID 16101 Rev 5
STM6502, STM6503, STM6504, STM6505
Description
Figure 5.
Single-button Smart Reset typical hookup
6
##
##
6
6
##
234
432
2%3%4
34-ꢇꢈꢀꢁ
-#5
32ꢂ
32ꢀ
).4ꢅ
.-)
6
6
33
33
053(ꢆ"544/.
37)4#(
!-ꢀꢀꢁꢄꢀB
Figure 6.
Dual-button Smart Reset typical hookup
6
##
6
6
##
##
234
432
2%3%4
34-ꢇꢈꢀꢁ
-#5
32ꢂ
32ꢀ
).4ꢅ
.-)
6
6
33
33
053(ꢆ"544/.
37)4#(
053(ꢆ"544/.
37)4#(
!-ꢀꢀꢁꢄꢂ6ꢉ
Doc ID 16101 Rev 5
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Description
STM6502, STM6503, STM6504, STM6505
1.2
Pin descriptions
1.2.1
Power supply (V
)
CC
This pin is used to provide the power to the device and to monitor the power supply.
A 0.1 µF decoupling ceramic capacitor is recommended to be connected between the V
CC
and V pins.
SS
1.2.2
1.2.3
Ground (V )
SS
This is the supply ground for the device.
Primary Smart Reset input (SR0)
The primary push-button Smart Reset input, active-low pin is connected to the first push-
button switch.
1.2.4
Secondary Smart Reset input (SR1)
The secondary push-button Smart Reset input, active-low pin is connected to the second
push-button switch. Keeping both Smart Reset inputs SR0 and SR1 active for longer than
t
activates the reset output pulse.
SRC
Figure 7.
STM6502, STM6503 timing
t
t
REC
SRC
SR0
SR1
RST
AM00327
Reset is asserted “low” right after the Smart Reset setup delay (t
) has been met and
SRC
returns to high after the t
period.
REC
10/29
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STM6502, STM6503, STM6504, STM6505
Description
1.2.5
Edge-triggered Smart Reset input (SRE pin) – STM6504 only
The SRE pin is active-high, immediate and independent reset input that includes an edge
trigger with debounce delay t
on the falling edge.
DEBOUNCE
Note:
The triggering edge must be a high-to-low or low-to-high transition with a slew-rate faster
than 1 V/µs typ.
Figure 8.
STM6504 timing
t < t
t < t
SRC
=> no output response
DEBOUNCE
t
=> t
timer reset
SRC
REC
SR0
Independent
SRE
RST
No debounce
t
REC
t
t
t
REC
REC
DEBOUNCE
(rising edges within
are ignored)
t
DEBOUNCE
AM00328V2
1.2.6
Adjustable delay of Smart Reset input (SRC pin) – STM6502 and
STM6505 only
This pin controls the setup time before the push-button action is validated by the reset
output. It is connected to an external capacitor (C ), which is tied to ground to provide the
SRC
desired value of the setup time (t
).
SRC
Calculated t
and C
examples are given in Table 3. Refer also to Table 6.
SRC
SRC
Table 3.
t
programmed by an ideal external capacitor – STM6502 and STM6505
SRC
(1)(2)
Setup delay t
[s]
SRC
Calculated C
Closest common
SRC
value [µF]
C
value [µF]
SRC
Min.
Typ.
Max.
0.2
0.3
0.6
1
2
3
2.5
3.75
7.5
3.0
4.5
9
0.22
0.33
0.56
1
6
10
12.5
15
1. At 25 °C. Example calculations based on an ideal capacitor. During application design and component
selection it should be considered that the current flowing into the external tSRC programming capacitor
(CSRC) is on the order of 100 nA, therefore a low-leakage capacitor (ceramic or film capacitor) should be
used and placed as close as possible to the SRC pin. Also an adequate low-leakage PCB environment
should be ensured to prevent tSRC accuracy from being affected. A recommended minimum value of CSRC
is 0.01 µF.
2. In case of repeated activations of the tSRC timer, an interval of 10 ms min. is needed between the
activations to fully discharge CSRC, so that the next tSRC is as specified.
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Description
STM6502, STM6503, STM6504, STM6505
1.2.7
Programmable Smart Reset input delay (TSR pin) – STM6503 and
STM6504 only
The TSR pin allows the user to program the setup time before the push-button action is
validated by the reset output. It is controlled by different voltage levels on the three-state
TSR input pin: when connected to ground, t
= 2 s; when left open, t
= 6 s; when
SRC
SRC
connected to V , t
= 10 s (all times are minimum). TSR is a DC-type input, intended to
CC SRC
be either permanently grounded, permanently connected to V or permanently left open.
CC
If it is left open, for improved system glitch immunity it is strongly recommended to connect
a 0.1 µF decoupling ceramic capacitor between the TSR and V pins.
SS
1.2.8
1.2.9
Reset output (RST)
RST is the active-low, open-drain reset output in the Smart Reset family.
Battery monitoring input (V
) – STM6505 only
BAT
V
is an input for monitoring the battery voltage. V
threshold is 1.25 V, fixed, and an
BAT
BAT
external resistor divider is to be used to set the actual battery voltage threshold.
1.2.10
Battery low detect output (BLD) – STM6505 only
The battery low detect output is controlled by the V
active-low, open-drain, with no pull-up.
voltage monitoring input and is
BAT
Figure 9.
STM6505 timing
t
t
REC
SRC
SR0
SR1
RST
V
BAT
V
BATTH
BLD
AM00329
12/29
Doc ID 16101 Rev 5
STM6502, STM6503, STM6504, STM6505
Typical operating characteristics
2
Typical operating characteristics
Figure 10. Supply current (I ) vs. temperature (STM6505)
CC
3
2.5
2
1.5
1
0.5
0
-60
-40
-20
0
20
40
60
80
100
120
140
Temperature [°C]
5.5 V
2 V
5 V
3 V
AM04886v1
Figure 11. Smart Reset delay (t
) vs. temperature, C
= 0.62 µF (STM6505)
SRC
SRC
9.2
8.7
8.2
7.7
7.2
6.7
6.2
-60
-40
-20
0
20
40
60
80
100
120
140
Temperature [°C]
5.75 V
5.5 V
3.3 V
AM04887v1
Doc ID 16101 Rev 5
13/29
Typical operating characteristics
STM6502, STM6503, STM6504, STM6505
Figure 12. Reset threshold (V
) vs. temperature, “S” threshold option, V falling (STM6505)
CC
RST
2.99
2.97
2.95
2.93
2.91
2.89
2.87
2.85
-60
-40
-20
0
20
40
60
80
100
120
140
Temperature [°C]
AM04888v1
Figure 13.
V
monitoring threshold (V
) vs. temperature, falling (STM6505)
BATTH
BAT
1.275
1.27
1.265
1.26
1.255
1.25
1.245
1.24
1.235
1.23
1.225
-60
-40
-20
0
20
40
Temperature [°C]
60
80
100
120
140
5.75 V
5.5 V 3.3 V
2 V
1.58 V
AM04889v1
14/29
Doc ID 16101 Rev 5
STM6502, STM6503, STM6504, STM6505
Maximum ratings
3
Maximum ratings
Stressing the device above the rating listed in Table 4: Absolute maximum ratings may
cause permanent damage to the device. These are stress ratings only and operation of the
device at these or any other conditions above those indicated in the operating sections of
this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability. Refer also to the STMicroelectronics SURE
Program and other relevant quality documents.
Table 4.
Symbol
Absolute maximum ratings
Parameter
Value
Unit
T
Storage temperature (V off)
–55 to +150
260
°C
°C
STG
(1)
CC
T
Lead solder temperature for 10 seconds
Thermal resistance (junction to ambient)
Input or output voltage
SLD
TDFN8
149.0
°C/W
V
θ
JA
(2)
V
–0.3 to 5.5
IO
V
Supply voltage
–0.3 to 7
V
CC
1. Reflow at peak temperature of 260 °C. The time above 255 °C must not exceed 30 seconds.
2. For inputs or outputs with internal pull-up resistors and push-pull type outputs –0.3 to VCC+0.3 V only.
Doc ID 16101 Rev 5
15/29
DC and AC parameters
STM6502, STM6503, STM6504, STM6505
4
DC and AC parameters
This section summarizes the operating measurement conditions, and the DC and AC
characteristics of the device. The parameters in the DC and AC characteristics tables that
follow, are derived from tests performed under the measurement conditions summarized in
Table 5: Operating and measurement conditions. Designers should check that the operating
conditions in their circuit match the operating conditions when relying on the quoted
parameters.
Table 5.
Operating and measurement conditions
Parameter
Value
Unit
V
supply voltage
1.0 to 5.5
–40 to +85
≤ 5
V
°C
ns
V
CC
Ambient operating temperature (T )
A
Input rise and fall times
Input pulse voltages
0.2 to 0.8 V
0.3 to 0.7 V
CC
CC
Input and output timing ref. voltages
V
Figure 14. AC testing input/output waveforms
0.8 V
CC
0.7 V
CC
0.2 V
0.3 V
CC
CC
AM00478
16/29
Doc ID 16101 Rev 5
STM6502, STM6503, STM6504, STM6505
DC and AC parameters
Table 6.
Symbol
DC and AC characteristics
Parameter
(1)
(2)
Test conditions
Min. Typ.
Max. Unit
V
Supply voltage range
Reset output valid - active-low
1.0
1.2
1.1
4
5.5
V
CC
V
V
V
V
V
V
V
V
= 5.0 V
= 3.0 V
µA
µA
µA
µA
µA
µA
µA
µA
CC
CC
CC
CC
CC
CC
CC
CC
STM6502
STM6503
STM6504
STM6505
(3)
= 5.0 V, TSR left open
= 3.0 V, TSR left open
= 5.0 V, TSR left open
= 3.0 V, TSR left open
= 5.0 V
5.8
5.8
3.3
(3)
(3)
3
Supply current (inputs in
their inactive state)
I
CC
4
3
2.3
2.2
(3)
= 3.0 V
Output characteristics
V
V
V
≥ 4.5 V, sinking 3.2 mA
≥ 3.3 V, sinking 2.5 mA
≥ 1.0 V, sinking 0.1 mA
0.3
0.3
V
V
CC
CC
CC
Reset output voltage low
(reset asserted: RST, BLD)
V
OL
0.3
V
Option A
Option B
140
240
210
360
280
480
ms
ms
Reset timeout delay,
factory-programmed
t
REC
V
monitoring reset thresholds
CC
V
V
RST
RST
–40 to +85 °C
25 °C
V
V
V
RST
RST
Fixed voltage trip point for
+2.5%
–2.5%
V
V
monitoring (refer to
RST
CC
V
V
Table 7)
RST
RST
V
–2.0%
+2.0%
L, M
0.5%
1%
V
Hysteresis of V
HYST
RST
T, S, R, Z, Y, W, V
V
falling from
CC
V
to reset delay
(V
+ 100 mV) to (V - 100 mV) at
20
µs
V
CC
RST
RST
(4)
10 mV/µs
V
V
V
monitoring
BAT
Fixed V
threshold
monitoring
BAT
STM6505 only
STM6505 only
1.225 1.25
8
1.275
BATTH
V
V
hysteresis
BATTH
16
mV
nA
BATHYST
LI(VBAT)
I
input leakage current STM6505 only
–100
10
100
BAT
Doc ID 16101 Rev 5
17/29
DC and AC parameters
STM6502, STM6503, STM6504, STM6505
Table 6.
Symbol
DC and AC characteristics (continued)
Parameter Test conditions
(1)
(2)
Min. Typ.
Max. Unit
Smart Reset inputs
SR0, SR1, SRE input
voltage low
V
–0.3
0.3
V
SS
V
IL
V
CC
SR0, SR1, SRE input
voltage high
0.7
V
5.5
+1
+7
V
IH
V
CC
Input leakage current, SR
and SRE inputs
I
Option without internal pull-up resistor
STM6503 and STM6504 only
–1
µA
µA
LI(SR)
Input leakage current, TSR
input
I
–5
LI(TSR)
Internal pull-up resistor,
input (optional - refer to
Table 12)
R
65
kΩ
PUI
SRE input falling edge
debounce time
t
STM6504 only
240
360
480
ms
DEBOUNCE
Smart Reset delay
Capacitor-programmable
10 x 12.5 x
15 x
Smart Reset setup time,
STM6502 and STM6505.
Refer to Table 3.
(5)
(5)
t
T = 25 °C
C
C
C
s
SRC
A
SRC
SRC
SRC
(µF)
(µF)
(µF)
TSR = V
2
6
2.5
7.5
3
9
s
s
s
SS
TSR pin-programmable
Smart Reset setup time,
STM6503 and STM6504.
(6)
t
TSR = floating
TSR = V
SRC
10
12.5
15
CC
1. Valid for ambient operating temperature: TA = –40 to +85 °C; VCC = 1.0 to 5.5 V (except where noted).
2. Typical value is at 25 °C and VCC = 3.3 V unless otherwise noted.
3. For devices with VRST < 3.0 V.
4. Guaranteed by design.
5. Input glitch immunity is equal to tSRC (when both SR inputs are low, otherwise infinite). STM6502, STM6503, STM6505
only.
6. If left open, for improved system glitch immunity it is strongly recommended to connect a 0.1 µF decoupling ceramic
capacitor between the TSR and VSS pins.
18/29
Doc ID 16101 Rev 5
STM6502, STM6503, STM6504, STM6505
DC and AC parameters
.
Table 7.
V
voltage thresholds
CC
2.5% (–40 °C to +85 °C)
2.0% (25 °C)
Unit
V
monitoring threshold
CC
Typ.
V
RST
Min.
Max.
Min.
Max.
L (falling)
M (falling)
T (falling)
S (falling)
R (falling)
Z (falling)
Y (falling)
W (falling)
V (falling)
4.625
4.375
3.075
2.925
2.625
2.313
2.188
1.665
1.575
4.509
4.266
2.998
2.852
2.559
2.255
2.133
1.623
1.536
4.741
4.484
3.152
2.998
2.691
2.371
2.243
1.707
1.614
4.533
4.288
3.014
2.867
2.573
2.267
2.144
1.632
1.544
4.718
4.463
3.137
2.984
2.678
2.359
2.232
1.698
1.607
V
V
V
V
V
V
V
V
V
Doc ID 16101 Rev 5
19/29
Package mechanical data
STM6502, STM6503, STM6504, STM6505
5
Package mechanical data
In order to meet environmental requirements, ST offers these devices in different grades of
®
®
ECOPACK packages, depending on their level of environmental compliance. ECOPACK
specifications, grade definitions and product status are available at: www.st.com.
®
ECOPACK is an ST trademark.
20/29
Doc ID 16101 Rev 5
STM6502, STM6503, STM6504, STM6505
Package mechanical data
Figure 15. TDFN – 8-lead 2 x 2 x 0.75 mm, 0.5 mm pitch package outline
D
A
B
PIN 1 INDEX AREA
E
2x
C
0.10
0.10 C 2x
TOP VIEW
0.10
C
A
C
A1
SEATING
PLANE
SIDE VIEW
e
0.08
C
b
PIN 1 INDEX AREA
0.10
C A B
1
4
Pin#1 ID
L
5
8
BOTTOM VIEW
8070540_A
Table 8.
Symbol
TDFN – 8-lead 2 x 2 x 0.75 mm, 0.5 mm pitch package mechanical data
Dimension (mm)
Dimension (inches)
Min.
Nom.
Max.
Min.
Nom.
Max.
A
A1
b
0.70
0.00
0.15
0.75
0.02
0.20
0.80
0.05
0.25
0.028
0.000
0.006
0.030
0.001
0.008
0.031
0.002
0.010
D
1.9
1.9
2.00
2.00
2.1
2.1
0.075
0.075
0.079
0.079
0.083
0.083
BSC
E
BSC
e
L
0.50
0.55
0.020
0.022
0.45
0.65
0.018
0.026
Doc ID 16101 Rev 5
21/29
Package mechanical data
STM6502, STM6503, STM6504, STM6505
Figure 16. Landing pattern - TDFN – 8-lead 2 x 2 mm without thermal pad
D
P
E
E1
L
b
AM00441
Table 9.
Parameter for landing pattern - TDFN – 8-lead 2 x 2 mm package
Dimension (mm)
Description
Parameter
Min.
Nom.
Max.
L
b
Contact length
1.05
0.25
—
1.15
0.30
—
—
—
Contact width
E
Max. land pattern Y-direction
Contact gap spacing
Max. land pattern X-direction
Contact pitch
2.85
0.65
1.75
0.5
E1
D
P
—
—
—
—
—
—
22/29
Doc ID 16101 Rev 5
STM6502, STM6503, STM6504, STM6505
Figure 17. Carrier tape
Package mechanical data
P
0
D
P
2
T
E
A
0
F
Top cover
tape
W
B
0
Center lines
of cavity
K
0
P
1
User direction of feed
AM03073v2
Table 10.
Package
Carrier tape dimensions
Bulk
qty.
W
D
E
P
P
F
A
B
K
P
1
T
Unit
0
2
0
0
0
8.00
+0.30 +0.10/
–0.10 –0.00
1.50
1.75
0.10
4.00
0.10
2.00
0.10
3.50
0.05
2.30
0.05
2.30
0.05
1.00
0.05
4.00 0.250
0.10 0.05
TDFN8
mm 3000
Doc ID 16101 Rev 5
23/29
Package mechanical data
STM6502, STM6503, STM6504, STM6505
Figure 18. Reel dimensions
T
40 mm min.
acces hole
at slot location
B
D
C
N
A
Full radius
Tape slot
in core for
tape start
25 mm min width
G measured
at hub
AM00443
Table 11.
Tape sizes
Reel dimensions
A max.
B min.
C
D min.
N min.
G
T max.
8 mm
180 (7 inches)
1.50
13.0 +/– 0.20
20.20
60
8.4 +2/–0 14.40
24/29
Doc ID 16101 Rev 5
STM6502, STM6503, STM6504, STM6505
Package mechanical data
Figure 19. Tape trailer/leader
End
Start
Top
cover
tape
No components
Components
100 mm min. No components
T RA IL ER
L EA D ER
400 mm min.
160 mm min.
Sealed with cover tape
User direction of feed
AM00444
Figure 20. Pin 1 orientation
User direction of feed
AM00442
Note:
1
2
Drawings are not to scale.
All dimensions are in mm, unless otherwise noted.
Doc ID 16101 Rev 5
25/29
Part numbering
STM6502, STM6503, STM6504, STM6505
6
Part numbering
Table 12.
Example:
Ordering information scheme
STM6505
W
C
A
B
DG
6
F
Device type
(1)
STM6502
STM6503
(1)
STM6504
STM6505
Reset (V monitoring) threshold voltage
CC
(V
), typ., falling
RST
L = 4.625 V
S = 2.925 V
R = 2.625 V
Z = 2.313 V
W = 1.665 V
V = 1.575 V
Smart Reset setup delay (t
); presence of internal input
SRC
pull-up on all Smart Reset inputs (SRx, SRE)
A = user-programmable (external capacitor); no input pull-up
C = user-programmable (external capacitor); 65 kΩ input pull-up
E = 2 or 6 or 10 s min., user-programmable (three-state); no input pull-up
F = 2 or 6 or 10 s min., user-programmable (three-state); 65 kΩ input pull-up
Output type
A = open-drain, no pull-up, active-low
Reset timeout period (t
A = 140 ms min.
B = 240 ms min.
Package
)
REC
DG = TDFN8 2 x 2 x 0.75 mm, 0.5 mm pitch
Temperature range
6 = –40 °C to +85 °C
Shipping method
®
F = ECOPACK package, tape and reel
1. Contact local ST sales office for availability.
For device options currently available refer to Table 13. For other options, voltage threshold values etc. or
for more information on any aspect of this device, please contact the ST sales office nearest you.
26/29
Doc ID 16101 Rev 5
STM6502, STM6503, STM6504, STM6505
Package marking
7
Package marking
Table 13.
Package marking
t
Smart
Reset
SRC
RST
output
t
BLD
REC
Part number
delay
control inputs
V
Topmark
(1)
(1)
RST
option output
(1)
STM6503VEAADG6F
TSR
TSR
AL
V
S
AL, OD
AL, OD
AL, OD
AL, OD
AL, OD
A
B
B
B
B
—
—
3VG
4SG
5SK
5RK
5WK
(2)
STM6504SEABDG6F
STM6505SCABDG6F
STM6505RCABDG6F
STM6505WCABDG6F
AL
C
AL, PU
AL, PU
AL, PU
S
AL, OD
AL, OD
AL, OD
SRC
SRC
SRC
C
C
R
W
1. AL = active-low, AH = active-high, PU = with internal pull-up resistor, OD = open-drain.
2. Contact local ST sales office for availability.
Figure 21. Package marking, top view
A
B
E
C
D
Topmark
A = dot (pin 1 reference)
B = assembly plant (P)
C = assembly year (Y, 0-9): 9 = 2009 etc.
D = assembly work week (WW, 01 to 52): 20 = WW20 etc.
E = marking area (topmark)
AM00479
Doc ID 16101 Rev 5
27/29
Revision history
STM6502, STM6503, STM6504, STM6505
8
Revision history
Table 14.
Date
Document revision history
Revision
Changes
31-Aug-2009
1
Initial release.
Updated Applications, Section 1, Section , Figure 3 to Figure 6
updated and moved to Section , updated Table 1, Table 2, Table 3,
Table 4, Table 6, Table 12, Section 1.2.3, Section 1.2.7,
Section 1.2.9, Section 5, added package footprint, tape and reel
information, and Section 7.
06-Nov-2009
2
Updated Features, Section 1, Section 1.2.6, Table 1, Table 2,
Figure 5, Figure 6, Table 3, Table 6, Table 12, Table 13, removed
Table 4.
15-Jan-2010
01-Mar-2010
3
4
Updated title of datasheet, Features, Applications, Table 1, 2, 6, 12,
footnote 5 of Table 6; updated Figure 3, 4; added Section 2: Typical
operating characteristics; minor textual and formatting changes.
Updated Features, Section 1, Figure 8, footnote 1 and 2 of Table 3,
updated Table 4, added footnote 2 to Table 4, Table 6, added
footnote 6 to Table 6, updated Table 6 to Table 9, and added footnote
2 of Table 13.
21-Jun-2010
5
28/29
Doc ID 16101 Rev 5
STM6502, STM6503, STM6504, STM6505
Please Read Carefully:
Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the
right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any
time, without notice.
All ST products are sold pursuant to ST’s terms and conditions of sale.
Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no
liability whatsoever relating to the choice, selection or use of the ST products and services described herein.
No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. If any part of this
document refers to any third party products or services it shall not be deemed a license grant by ST for the use of such third party products
or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoever of such
third party products or services or any intellectual property contained therein.
UNLESS OTHERWISE SET FORTH IN ST’S TERMS AND CONDITIONS OF SALE ST DISCLAIMS ANY EXPRESS OR IMPLIED
WARRANTY WITH RESPECT TO THE USE AND/OR SALE OF ST PRODUCTS INCLUDING WITHOUT LIMITATION IMPLIED
WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE (AND THEIR EQUIVALENTS UNDER THE LAWS
OF ANY JURISDICTION), OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT.
UNLESS EXPRESSLY APPROVED IN WRITING BY AN AUTHORIZED ST REPRESENTATIVE, ST PRODUCTS ARE NOT
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Resale of ST products with provisions different from the statements and/or technical features set forth in this document shall immediately void
any warranty granted by ST for the ST product or service described herein and shall not create or extend in any manner whatsoever, any
liability of ST.
ST and the ST logo are trademarks or registered trademarks of ST in various countries.
Information in this document supersedes and replaces all information previously supplied.
The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners.
© 2010 STMicroelectronics - All rights reserved
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Doc ID 16101 Rev 5
29/29
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