STM6519ACAFUB6F [STMICROELECTRONICS]
POWER SUPPLY SUPPORT CKT;
| 型号： | STM6519ACAFUB6F |
| 厂家： | 
ST |
| 描述： | POWER SUPPLY SUPPORT CKT |
| 文件： | 总25页 (文件大小：391K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
STM6519
4-pin Smart Reset™
Datasheet - production data
Features
■ Operating voltage range 2 V to 5.5 V
■ Low supply current 1 μA
■ Integrated test mode
■ Single Smart Reset™ push-button input with
fixed extended reset setup delay (t
) from
SRC
0.5 s to 10 s in 0.5 s steps (typ.), option with
internal input pull-up resistor
UDFN4 1.00 mm x 1.45 mm
■ Push-button controlled reset pulse duration
– Option 1: fully push-button controlled, no
fixed or minimum pulse width guaranteed
– Option 2: defined output reset pulse
duration (t
), factory-programmed
REC
■ Single reset output
– Active-low or active-high
UDFN6 1.00 mm x 1.45 mm
– Push-pull or open drain with optional
pull-up resistor
■ Fixed Smart Reset input logic voltage levels
■ Operating temperature: -40 °C to +85 °C
■ UDFN4 package 1.00 mm x 1.45 mm and
UDFN6 package 1.00 mm x 1.45 mm
®
■ ECOPACK 2 (RoHS compliant, Halogen-
Free)
Applications
■ Mobile phones, smartphones, PDAs
■ e-books
■ MP3 players
■ Games
■ Portable navigation devices
■ Any application that requires delayed reset
push-button response for improved system
stability
January 2013
Doc ID 022111 Rev 6
1/25
This is information on a product in full production.
www.st.com
1
Contents
STM6519
Contents
1
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.1
1.2
1.3
Test mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Pin connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2
3
Device overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.1
3.2
3.3
3.4
3.5
3.6
Power supply (V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
CC
Power-up sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Ground (V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
SS
Smart Reset input (SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Reset output (RST) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
RST output undervoltage behavior (for open-drain option) . . . . . . . . . . . . 8
4
Typical application diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Typical operating characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Tape and reel information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Package marking information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
5
6
7
8
9
10
11
12
13
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STM6519
List of tables
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Operating and measurement conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
DC and AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
UDFN4, 1.00 mm x 1.45 mm x 0.50 mm, 0.65 mm pitch package mechanical data . . . . . 18
UDFN6, 1.00 mm x 1.45 mm x 0.50 mm, 0.50 mm pitch package mechanical data . . . . . 19
Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Package marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
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List of figures
STM6519
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
STM6519 logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
UDFN4 pin connections (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
UDFN6 pin connections (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
STM6519 block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Typical application diagram - input, output and STM6519 device in one voltage
domain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Typical application diagram - STM6519 device in a different voltage domain than
input and output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 6.
Figure 7.
Typical application diagram in different voltage domains - SR input in V
domain
BAT
like V totally disables the test mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
CC
Figure 8.
Figure 9.
RST output without t
option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
REC
RST output with t
REC
Figure 10. Supply current (I ) vs. temperature (T ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
CC
A
Figure 11. Smart Reset delay (t
) vs. temperature (T ), t
= 4.0 s (typ.) . . . . . . . . . . . . . . . . . . 12
SRC
A
SRC
Figure 12. Test mode entry voltage (V
) vs. temperature (T ). . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
TEST
A
Figure 13. Initial test mode time (t
) vs. temperature (T ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
SRC-INI
A
Figure 14. UDFN4, 1.00 mm x 1.45 mm x 0.50 mm, 0.65 mm pitch package outline . . . . . . . . . . . . . 17
Figure 15. Footprint recommendation for UDFN4, 1.00 mm x 1.45 mm x 0.50 mm, 0.65 mm pitch . . 18
Figure 16. UDFN6, 1.00 mm x 1.45 mm x 0.50 mm, 0.50 mm pitch package outline . . . . . . . . . . . . . 19
Figure 17. Footprint recommendation for UDFN6 1.00 mm x 1.45 mm x 0.50 mm, 0.50 mm pitch. . . 20
Figure 18. Carrier tape. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 19. Pin 1 orientation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 20. Package marking (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
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STM6519
Description
1
Description
TM
The Smart Reset devices provide a useful feature which ensures that inadvertent short
reset push-button closures do not cause system resets. This is done by implementing an
extended Smart Reset input delay time (t
), which ensures a safe reset and eliminates
SRC
the need for a specific dedicated reset button.
This reset configuration provides versatility and allows the application to distinguish between
a software generated interrupt and a hard system reset. When the input push-button is
connected to the microcontroller interrupt input, and is closed for a short time, the processor
can only be interrupted. If the system still does not respond properly, continuing to keep the
push-buttons closed for the extended setup time t
through the reset output.
causes a hard reset of the processor
SRC
The STM6519 has one Smart Reset input (SR) with preset delayed Smart Reset setup time
(t ). The reset output (RST) is asserted after the Smart Reset input is held active for the
SRC
selected t
delay time. The RST output remains asserted either until the SR input goes to
SRC
inactive logic level (i.e. neither fixed nor minimum reset pulse width is set) or the output reset
pulse duration is fixed for t (i.e. factory-programmed). The device fully operates over
REC
a broad V range from 2.0 V to 5.5 V.
CC
1.1
Test mode
After pulling SR up to V
(V + 1.4 V) or above, the counter starts to count the initial
CC
TEST
shortened t
(42 ms, typ.). After t
expires, the RST output either goes down for
SRC-INI
SRC-INI
t
(if t
option is used) or stays low as long as overvoltage on SR is detected (if t
REC
REC REC
option is not used). This is feedback, and the user only knows that the device is locked in
test mode. Each time the SR input is connected to ground in test mode, a shortened
t
(t
/128) is used instead of regular t
(0.5 s - 10 s). In this way the device
SRC-SHORT SRC
SRC
can be quickly tested without repeating test mode triggering. Return to normal mode is
possible by performing a new startup of the device (i.e. V goes to 0 V and back to its
CC
original state).
The advantages of this solution are its high glitch immunity, user feedback regarding entry
into test mode, and testability within the full V range.
CC
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Description
STM6519
1.2
Logic diagram
Figure 1.
STM6519 logic diagram
6
##
32
234
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!-ꢄꢅꢆꢀꢇ
1.3
Pin connections
Figure 2.
UDFN4 pin connections (top view)
6
ꢂ
ꢇ
ꢆ
ꢈ
234
33
34-
ꢀꢁꢂꢃ
6
32
##
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Figure 3.
UDFN6 pin connections (top view)
ꢉꢂꢊ
234
.#
ꢂ
ꢇ
ꢈ
ꢀ
ꢁ
ꢆ
34-
ꢀꢁꢂꢃ
ꢉꢂꢊ
6
.#
6
33
32
##
5$&.ꢀ
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1. Not connected (not bonded); should be connected to VSS
.
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STM6519
Device overview
2
Device overview
Table 1.
Signal names
Pin number
Name
Type
Description
UDFN6
UDFN4
1
2
3
4
1
2
RST
Output
Reset output, active-low, open drain.
V
Supply ground Ground
Input Smart Reset input, active-low.
Positive supply voltage for the device. A 0.1 µF decoupling
SS
SR
4
3
V
Supply voltage ceramic capacitor is recommended to be connected between
and V pins.
CC
V
CC
SS
5
6
-
-
NC
NC
-
-
Not connected (not bonded); should be connected to V
Not connected (not bonded); should be connected to V
.
SS
.
SS
Figure 4.
STM6519 block diagram
T
2%#
T
32#
GENERATOR
ꢉOPTIONALꢊ
32
234
GENERATOR
/VERVOLTAGE DETECT
ꢋ TEST MODE TRIGGER
!-ꢄꢅꢆꢀꢁ6ꢂ
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Pin descriptions
STM6519
3
Pin descriptions
3.1
Power supply (VCC)
This pin is used to provide power to the Smart Reset device. A 0.1 µF ceramic decoupling
capacitor is recommended to be connected between the V and V pins, as close to the
CC
SS
STM6519 device as possible.
3.2
Power-up sequence
In normal mode, if different input side (SR) and V voltage domains are used, power-on
CC
sequence must avoid meeting the test mode entry condition to avoid inadvertent test mode
entry: there should not be logic high present on the SR input before the V power-up.
CC
However V and V(SR) rising at the same time is OK (e.g. if both are in the same voltage
CC
domain), the device will then safely start into normal operating mode, with RST output
inactive (in High-Z mode for open-drain option).
3.3
3.4
Ground (VSS)
This is the ground pin for the device.
Smart Reset input (SR)
Push-button Smart Reset input, active-low with optional pull-up resistor. SR input needs to
be asserted for at least t
to assert the reset output (RST).
SRC
By connecting a voltage higher than V + 1.4 V to the SR input the device enters test mode
CC
(see Section 1: Description on page 5 for more information).
3.5
Reset output (RST)
RST is active-low or active-high, open drain or push-pull reset output with optional internal
pull-up resistor.
Output reset pulse width is optional as follows:
●
●
Neither fixed nor minimum output reset pulse duration (releasing the push-button while
reset output is active, causes the output to de-assert)
Fixed, factory-programmed output reset pulse duration for t
Reset input state.
independent on Smart
REC
3.6
RST output undervoltage behavior (for open-drain option)
High-Z on RST output below the specified operating voltage range is guaranteed at V
CC
power-on or in case that valid V dropped while the device was idle, i.e. while both output
CC
and input were inactive.
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STM6519
Typical application diagrams
4
Typical application diagrams
Figure 5.
Typical application diagram - input, output and STM6519 device in one
voltage domain
Figure 6.
Typical application diagram - STM6519 device in a different voltage
domain than input and output
1. Open-drain RST output type and fixed SR input logic threshold allows to use the device in different voltage
domains. To prevent entering test mode by creating a condition V(SR) > VCC + 1.1 V typ., VCC should be
powered up before or together with voltage on the SR input.
Doc ID 022111 Rev 6
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Typical application diagrams
STM6519
Figure 7.
Typical application diagram in different voltage domains - SR input in
V
domain like V totally disables the test mode
BAT
CC
10/25
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STM6519
5
Timing diagrams
Timing diagrams
Figure 8.
RST output without t
option
REC
1. VCC should be powered up before or together with voltage on the SR input to prevent entering test mode by creating
a condition V(SR) > VCC +1.1 V typ.
Figure 9.
RST output with t
option
REC
1. VCC should be powered up before or together with voltage on the SR input to prevent entering test mode by creating
a condition V(SR) > VCC +1.1 V typ.
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Typical operating characteristics
STM6519
6
Typical operating characteristics
Figure 10. Supply current (I ) vs. temperature (T )
CC
A
ꢄꢌꢀ
ꢄꢌꢁ
ꢄꢌꢆ
ꢄꢌꢈ
ꢄꢌꢇ
ꢄꢌꢂ
ꢄ
6
6
ꢐ ꢁꢌꢁ 6
##
ꢐ ꢈꢌꢀ 6
ꢐ ꢇꢌꢄ 6
##
##
6
ꢍꢆꢄ
ꢍꢇꢄ
ꢄ
ꢇꢄ
ꢆꢄ
ꢀꢄ
ꢎꢄ
4EMPERATUREꢏ 4 ꢉ #ꢊ
!
!-ꢄꢅꢁꢈꢂ
Figure 11. Smart Reset delay (t
) vs. temperature (T ), t
= 4.0 s (typ.)
SRC
SRC
A
ꢆꢌꢎ
ꢆꢌꢀ
ꢆꢌꢆ
ꢆꢌꢇ
ꢆꢌꢄ
ꢈꢌꢎ
ꢈꢌꢀ
ꢈꢌꢆ
ꢈꢌꢇ
6
ꢐ ꢁꢌꢁ 6
##
6
6
ꢐ ꢈꢌꢀ 6
##
##
ꢐ ꢇꢌꢄ 6
ꢍꢆꢄ
ꢍꢇꢄ
ꢄ
ꢇꢄ
ꢆꢄ
ꢀꢄ
ꢎꢄ
4EMPERATUREꢏ 4 ꢉ #ꢊ
!
!-ꢄꢅꢁꢈꢇ
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STM6519
Typical operating characteristics
Figure 12. Test mode entry voltage (V
) vs. temperature (T )
A
TEST
ꢂꢌꢈꢄ
6
6
ꢐ ꢁꢌꢄ 6
##
ꢐ ꢈꢌꢀ 6
ꢐ ꢇꢌꢄ 6
ꢂꢌꢇꢁ
ꢂꢌꢇꢄ
ꢂꢌꢂꢁ
ꢂꢌꢂꢄ
ꢂꢌꢄꢁ
ꢂꢌꢄꢄ
##
6
##
ꢍꢆꢄ
ꢍꢇꢄ
ꢄ
ꢇꢄ
ꢆꢄ
ꢀꢄ
ꢎꢄ
4EMPERATUREꢏ 4 ꢉ #ꢊ
!
!-ꢄꢅꢁꢈꢈ
Figure 13. Initial test mode time (t
) vs. temperature (T )
A
SRC-INI
ꢁꢁ
6
ꢐ ꢁꢌꢄ 6
ꢐ ꢈꢌꢀ 6
##
6
##
ꢁꢄ
ꢆꢁ
ꢆꢄ
ꢈꢁ
ꢈꢄ
6
ꢐ ꢇꢌꢄ 6
##
ꢍꢆꢄ
ꢍꢇꢄ
ꢄ
ꢇꢄ
ꢆꢄ
ꢀꢄ
ꢎꢄ
4EMPERATUREꢏ 4 ꢉ #ꢊ
!
!-ꢄꢅꢁꢈꢆ
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Maximum ratings
STM6519
7
Maximum ratings
Stressing the device above the rating listed in Table 2: Absolute maximum ratings may
cause permanent damage to the device. These are stress ratings only and operation of the
device at these or any other conditions above those indicated in Table 3: Operating and
measurement conditions of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability. Refer also to the
STMicroelectronics™ SURE program and other relevant quality documents.
Table 2.
Symbol
Absolute maximum ratings
Parameter
Value
Unit
T
Storage temperature (V off)
-55 to +150
260
°C
°C
V
STG
(1)
CC
T
Lead solder temperature for 10 seconds
Input or output voltage
SLD
V
-0.3 to 5.5
-0.3 to 7
IO
V
Supply voltage
V
CC
ESD
Electrostatic discharge protection, human body model (JESD22-
A114-B level 2)
V
2
kV
kV
V
HBM
V
Electrostatic discharge protection, charged device model, all pins
1
RCDM
Electrostatic discharge protection, machine model, all pins
(JESD22-A115-A level A)
V
200
MM
Latch-up (V pin, SR reset input pin)
EIA/JESD78
CC
1. Reflow at peak temperature of 260 °C. The time above 255 °C must not exceed 30 seconds.
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STM6519
DC and AC parameters
8
DC and AC parameters
This section summarizes the operating measurement conditions, and the DC and AC
characteristics of the device. The parameters in Table 4: DC and AC characteristics are
derived from tests performed under the measurement conditions summarized in Table 3:
Operating and measurement conditions. Designers should check that the operating
conditions in their circuit match the operating conditions when relying on the quoted
parameters.
Table 3.
Symbol
Operating and measurement conditions
Parameter
Value
Unit
V
Supply voltage
2.0 to 5.5
-40 to +85
≤ 5
V
°C
ns
V
CC
T
Ambient operating temperature
Input rise and fall times
A
t , t
R
F
Input pulse voltages
0.2 to 0.8 V
0.3 to 0.7 V
CC
CC
Input and output timing reference voltages
V
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DC and AC parameters
STM6519
Table 4.
Symbol
DC and AC characteristics
Parameter
Supply voltage
(1)
(2)
Test conditions
Min.
Typ.
Max.
Unit
V
2.0
5.5
1.0
V
CC
SR = V , t
and t
SRC
CC REC
I
Supply current
0.4
µA
CC
counter is not running
V
V
V
≥ 4.5 V, sinking 3.2 mA
≥ 3.3 V, sinking 2.5 mA
≥ 2.0 V, sinking 1 mA
0.3
0.3
V
CC
CC
CC
V
Reset output voltage low
V
OL
0.3
V
0.85
66
1.28
100
210
360
1.71
134
280
480
ms
ms
ms
ms
Reset timeout delay,
factory-programmed
t
(device option)
REC
140
240
Internal output pull-up
resistor on RST
R
(device option)
65
kΩ
PUO
V
= 5.5 V, open drain
RST
I
Output leakage current
device option without output
pull-up resistor
-0.1
0.1
µA
LO
Smart Reset
T = -40 to +85 °C
0.8 x t
0.9 x t
1.2 x t
1.1 x t
A
SRC
SRC
SRC
(3)
t
Smart Reset delay
t
s
SRC
SRC
T = 25 °C
A
SRC
V
SR input voltage low
SR input voltage high
V
-0.3
SS
0.3
5.5
V
V
IL
V
0.85
IH
Internal input pull-up
resistor on SR
R
(device option)
65
kΩ
PUI
device option without input
pull-up resistor
I
SR input leakage current
Input glitch immunity
-0.1
0.1
µA
s
LEAK
t
SRC
Test mode
V
Test mode entry voltage
Initial test mode time
V
+0.9
V
+1.1
V +1.4
CC
V
TEST
CC
CC
t
28
42
/ 128
56
ms
SRC-INI
Shortened Smart Reset
delay
t
t
ms
SRC-SHORT
SRC
1. Valid for ambient operating temperature TA = -40 to +85 °C, VCC = 2.0 to 5.5 V.
2. Typical values are at 25 °C and VCC = 3.3 V unless otherwise noted.
3. Factory-programmable in the range of 0.5 s to 10 s typ. in 0.5 s steps.
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Package information
9
Package information
In order to meet environmental requirements, ST offers these devices in different grades of
®
ECOPACK packages, depending on their level of environmental compliance. ECOPACK
specifications, grade definitions and product status are available at: www.st.com. ECOPACK
is an ST trademark.
Figure 14. UDFN4, 1.00 mm x 1.45 mm x 0.50 mm, 0.65 mm pitch package outline
5$&.ꢍꢆ
Doc ID 022111 Rev 6
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Package information
Table 5.
STM6519
UDFN4, 1.00 mm x 1.45 mm x 0.50 mm, 0.65 mm pitch package
mechanical data
Dimensions
(1)
Symbol
(mm)
Typ.
(inches)
Typ.
Note
Min.
Max.
Min.
Max.
A
A1
A3
b
0.50
0.00
0.55
0.02
0.127
0.25
1.45
1.0
0.60
0.05
0.020
0.000
0.022
0.001
0.005
0.010
0.057
0.039
0.026
0.014
4
0.024
0.002
0.20
1.40
0.95
0.30
1.50
1.05
0.008
0.055
0.037
0.012
0.059
0.041
D
E
e
0.65
0.35
4
L
0.30
0.40
0.012
0.016
N
1. Controlling dimension: millimeters.
Figure 15. Footprint recommendation for UDFN4, 1.00 mm x 1.45 mm x 0.50 mm,
0.65 mm pitch
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ꢄꢌꢈꢄꢄꢄ
!-ꢄꢅꢆꢃꢀ
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Package information
Figure 16. UDFN6, 1.00 mm x 1.45 mm x 0.50 mm, 0.50 mm pitch package outline
$
.
%
ꢂ
ꢂ
ꢇ
ꢇ
!
!ꢂ
,
K
E
B
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Table 6.
Symbol
UDFN6, 1.00 mm x 1.45 mm x 0.50 mm, 0.50 mm pitch package
mechanical data
Dimensions
(1)
(mm)
Typ.
(inches)
Typ.
Note
Min.
Max.
Min.
Max.
A
A1
b
0.50
0.00
0.18
1.40
0.95
0.45
0.20
0.30
0.55
0.02
0.25
1.45
1.00
0.50
0.60
0.05
0.30
1.50
1.05
0.55
0.0197
0.000
0.0217
0.0008
0.0098
0.0571
0.0394
0.0197
0.0236
0.0020
0.0118
0.0591
0.0413
0.0217
0.0071
0.0551
0.0374
0.0177
0.0079
0.0118
D
E
e
k
L
0.35
0.40
0.0138
0.0157
1. Package outline exclusive of any mold flashes dimensions and metal burrs.
Doc ID 022111 Rev 6
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Package information
STM6519
Figure 17. Footprint recommendation for UDFN6 1.00 mm x 1.45 mm x 0.50 mm,
0.50 mm pitch
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ꢄꢌꢈꢄ
ꢂꢌꢀꢄ
!-ꢄꢅꢆꢃꢅ
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Tape and reel information
10
Tape and reel information
Figure 18. Carrier tape
!-ꢄꢅꢆꢃꢂ
1. 10-sprocket hole pitch cumulative tolerance 0.20.
Figure 19. Pin 1 orientation
5SER DIRECTION OF FEED
!-ꢄꢄꢆꢆꢇ6ꢂ
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Part numbering
STM6519
11
Part numbering
Table 7.
Ordering information scheme
STM6519
Example:
A
H
A
R
UB
6
F
Device type
STM6519
Reset (V monitoring threshold) voltage V
CC
RST
A = no V monitoring feature
CC
(1)
Smart Reset setup delay (t
)
SRC
C = factory programmable t
H = factory programmable t
= 1.5 s (typ.)
= 4.0 s (typ.)
= 6.0 s (typ.)
= 7.5 s (typ.)
= 10.0 s (typ.)
SRC
SRC
SRC
L = factory programmable t
P = factory programmable t
SRC
SRC
U = factory programmable t
(2)
Inputs, outputs type
A = active-low SR input with no pull-up,
active-low open drain RST output with no pull-up
B = active-low SR input with pull-up,
active-low open drain RST output with no pull-up
Reset timeout period (t
)
REC
A = factory programmable t
B = factory programmable t
E = factory programmable t
F = factory programmable t
= 210 ms (typ.)
= 360 ms (typ.)
= 1.28 ms (typ.)
= 100 ms (typ.)
REC
REC
REC
REC
R = push-button controlled (no defined t
)
REC
Package
UC = UDFN-4L
UB = UDFN-6L
Temperature range
6 = -40 °C to +85 °C
Shipping method
F = tape and reel
1. Smart Reset delay (tSRC) is available from 0.5 s to 10 s in 0.5 s steps (typ.). Minimum order quantities may apply. Contact
local sales office for availability.
2. Push-pull reset output type also available (active-low or active-high). SR input and open drain reset output available with
optional pull-up resistor. Minimum order quantities may apply. Contact local sales office for availability.
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Package marking information
12
Package marking information
Table 8.
Package marking
t
SmartReset
inputs
Output
type
t
REC
option
SRC
(s)
Part number
Package Topmark
(1)
(2)
(3)
STM6519AHARUC6F
STM6519ALARUC6F
STM6519APARUC6F
STM6519AUARUC6F
STM6519ACARUB6F
STM6519AHARUB6F
STM6519ALARUB6F
STM6519APAAUB6F
STM6519APARUB6F
STM6519APBBUB6F
STM6519AUARUB6F
1. AL = active-low.
4.0
6.0
7.5
10.0
1.5
4.0
6.0
7.5
7.5
7.5
10.0
AL
OD, AL
OD, AL
OD, AL
OD, AL
OD, AL
OD, AL
OD, AL
OD, AL
OD, AL
OD, AL
OD, AL
No t
No t
No t
No t
No t
No t
No t
UDFN4
UDFN4
UDFN4
UDFN4
UDFN6
UDFN6
UDFN6
UDFN6
UDFN6
UDFN6
UDFN6
HA
LA
PA
UA
CA
HA
LA
PB
PA
PC
UA
REC
AL
REC
REC
REC
REC
REC
REC
AL
AL
AL
AL
AL
AL
AL
210 ms
No t
REC
AL + pull-up
AL
360 ms
No t
REC
2. OD = open drain, AL = active-low.
3. No tREC = push-button controlled reset pulse width, any other value represents typical value of tREC
.
Figure 20. Package marking (top view)
!
"
! ꢐ DOT ꢉPIN ꢂ REFERENCEꢊ
" ꢐ MARKING AREA ꢉTOPMARKꢊ
'!0-3-$ꢄꢄꢄꢈꢅ
Doc ID 022111 Rev 6
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Revision history
STM6519
13
Revision history
Table 9.
Date
Document revision history
Revision
Changes
12-Aug-2011
22-Sep-2011
07-Oct-2011
27-Oct-2011
13-Jun-2012
1
2
3
4
5
Initial release.
Updated Figure 5, Table 4, Table 7 and Table 8.
Removed label “Preliminary data”.
Updated Figure 3 and Table 1.
Updated Features, Table 4, title of Section 9.
Moved Figure 4 below Table 1.
Added Section 3.2, Section 3.6, Figure 6 and Figure 7.
Updated title of Figure 5.
17-Jan-2013
6
Updated Figure 8 and Figure 9 (added notes and minor
modifications).
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