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STM660OAQ54DM6E [STMICROELECTRONICS]

Smart push-button on/off controller with Smart ResetTM and power-on lockout; 开/关控制器与智能ResetTM和上电智能锁定按钮
STM660OAQ54DM6E
型号： STM660OAQ54DM6E
厂家： ST    ST
描述：

Smart push-button on/off controller with Smart ResetTM and power-on lockout
开/关控制器与智能ResetTM和上电智能锁定按钮

控制器
文件： 总51页 (文件大小：1291K)
中文：  中文翻译
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STM6600  
STM6601  
Smart push-button on/off controller with  
Smart ResetTM and power-on lockout  
Features  
■ Operating voltage 1.6 V to 5.5 V  
■ Low standby current of 1 µA  
■ Adjustable Smart Reset™ assertion delay time  
driven by external C  
SRD  
■ Power-up duration determined primarily by  
push-button press (STM6600) or by fixed time  
period, t  
(STM6601)  
ON_BLANK  
■ Debounced PB and SR inputs  
■ PB and SR ESD inputs withstand voltage up to  
15 kV (air discharge) 8 kV (contact  
discharge)  
TDFN12  
■ Active high or active low enable output option  
(EN or EN) provides control of MOSFET,  
DC-DC converter, regulator, etc.  
Applications  
■ Secure startup, interrupt, Smart Reset™ or  
power down driven by push-button  
■ Portable devices  
■ Terminals  
■ Precise 1.5 V voltage reference with 1%  
accuracy  
■
Audio and video players  
■ Industrial operating temperature –40 to +85 °C  
■ Available in TDFN12 2 x 3 mm package  
■ Cell phones and smart phones  
■ PDAs, palmtops, organizers  
Table 1.  
Device  
Device summary  
RST  
C
PB / SR  
EN or EN  
INT  
Startup process  
PB must be held low until the  
SRD  
(1)  
(1)  
(1)  
(1)  
STM6600 open drain  
STM6601 open drain  
✓
✓
push-pull  
push-pull  
open drain  
(2)  
PS  
confirmation  
HOLD  
PB can be released before the  
✓
✓
open drain  
(2)  
PS  
confirmation  
HOLD  
1. External pull-up resistor needs to be connected to open drain outputs.  
2. For a successful startup, the PSHOLD (Power Supply Hold) needs to be pulled high within specific time, tON_BLANK  
.
June 2010  
Doc ID 15453 Rev 7  
1/51  
www.st.com  
1
Contents  
STM6600 - STM6601  
Contents  
1
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5  
Pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9  
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12  
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14  
Typical operating characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28  
Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38  
DC and AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39  
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42  
Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46  
Product selector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48  
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50  
2
3
4
5
6
7
8
9
10  
11  
2/51  
Doc ID 15453 Rev 7  
STM6600 - STM6601  
List of tables  
List of tables  
Table 1.  
Table 2.  
Table 3.  
Table 4.  
Table 5.  
Table 6.  
Table 7.  
Table 8.  
Table 9.  
Table 10.  
Table 11.  
Table 12.  
Device summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1  
Pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7  
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38  
Operating and AC measurement conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39  
DC and AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39  
TDFN12 (2 x 3 mm) package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43  
Carrier tape dimensions for TDFN12 (2 mm x 3 mm) package . . . . . . . . . . . . . . . . . . . . . 45  
STM6600 ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46  
STM6601 ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47  
STM6600 product selector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48  
STM6601 product selector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49  
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50  
Doc ID 15453 Rev 7  
3/51  
List of figures  
STM6600 - STM6601  
List of figures  
Figure 1.  
Figure 2.  
Figure 3.  
Figure 4.  
Figure 5.  
Figure 6.  
Figure 7.  
Application hookup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5  
Basic functionality (option with enable deassertion after long push) . . . . . . . . . . . . . . . . . . 6  
Basic functionality (option with RST assertion after long push) . . . . . . . . . . . . . . . . . . . . . . 6  
Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6  
TDFN12 pin connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7  
Block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8  
Successful power-up on STM6600  
(PB released prior to t  
expiration) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14  
ON_BLANK  
Figure 8.  
Figure 9.  
Successful power-up on STM6600  
(t expires prior to PB release) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15  
ON_BLANK  
Unsuccessful power-up on STM6600  
(PB released prior to t ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16  
ON_BLANK  
Figure 10. Unsuccessful power-up on STM6600  
(t expires prior to PB release) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17  
ON_BLANK  
Figure 11. Successful power-up on STM6601. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18  
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19  
Figure 12. Unsuccessful power-up on STM6601  
Figure 13. Power-up on STM660x with voltage dropout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20  
Figure 14. PB interrupt. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21  
Figure 15. Long push, PB pressed first . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22  
Figure 16. Long push, SR pressed first . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22  
Figure 17. Invalid long push . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23  
Figure 18. Long push (option with RST assertion). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24  
Figure 19. Long push (option with enable deassertion) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25  
Figure 20. Undervoltage detected for <t  
Figure 21. Undervoltage detected for >t  
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26  
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26  
SRD  
SRD  
Figure 22. PB  
output waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27  
OUT  
Figure 23. Supply current vs. temperature, normal state. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28  
Figure 24. Supply current vs. temperature, standby state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28  
Figure 25. Supply current vs. supply voltage, normal state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29  
Figure 26. Supply current vs. supply voltage, standby state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29  
Figure 27. Threshold vs. temperature, V  
= 3.4 V (typ.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30  
TH+  
Figure 28. Threshold hysteresis vs. temperature, V  
= 200 mV (typ.). . . . . . . . . . . . . . . . . . . . . . 30  
HYST  
Figure 29. Debounce period vs. supply voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31  
Figure 30. charging current vs. temperature, V = 3.6 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31  
Figure 31. Output low voltage vs. output low current, T = 25°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32  
C
SRD  
CC  
A
Figure 32. Output high voltage vs. output high current, T = 25°C . . . . . . . . . . . . . . . . . . . . . . . . . . . 32  
A
Figure 33. Output voltage vs. supply voltage, I  
= 1 mA, T = 25 °C . . . . . . . . . . . . . . . . . . . . . . . 33  
OUT  
A
Figure 34. Input voltage vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33  
Figure 35. Reference output voltage vs. temperature, V = 2.0 V. . . . . . . . . . . . . . . . . . . . . . . . . . . 34  
CC  
Figure 36. Reference output voltage vs. load current, V = 2.0 V, T = 25 °C . . . . . . . . . . . . . . . . . 34  
CC  
A
Figure 37. Reference output voltage vs. supply voltage, T = 25 °C. . . . . . . . . . . . . . . . . . . . . . . . . . 35  
A
Figure 38. Reference startup, I  
= 15 µF, T = 25 °C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35  
REF  
A
Figure 39. Reference response to steps on supply voltage, I  
= 15 µA, T = 25 °C . . . . . . . . . . . . 36  
A
REF  
Figure 40. Reference response to steps in load current, V = 3.6 V, T = 25 °C . . . . . . . . . . . . . . . 37  
CC  
A
Figure 41. TDFN12 (2 x 3 mm) package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43  
Figure 42. TDFN12 (2 x 3 mm) recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44  
Figure 43. Carrier tape for TDFN12 (2 mm x 3 mm) package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45  
4/51  
Doc ID 15453 Rev 7  
STM6600 - STM6601  
Description  
1
Description  
The STM6600-01 devices monitor the state of connected push-button(s) as well as sufficient  
supply voltage. An enable output controls power for the application through the MOSFET  
transistor, DC-DC converter, regulator, etc. If the supply voltage is above a precise voltage  
threshold, the enable output can be asserted by a simple press of the button. Factory-  
selectable supply voltage thresholds are determined by highly accurate and temperature-  
compensated references. An interrupt is asserted by pressing the push-button during  
normal operation and can be used to request a system power-down. The interrupt is also  
asserted if undervoltage is detected. By a long push of one button (PB) or two buttons (PB  
and SR) either a reset is asserted or power for the application is disabled depending on the  
option used.  
The device also offers additional features such as precise 1.5 V voltage reference with very  
tight accuracy of 1%, separate output indicating undervoltage detection and separate output  
for distinguishing between interrupt by push-button or undervoltage.  
The device consumes very low current of 6 µA during normal operation and only 1 µA  
current during standby.  
The STM6600-01 is available in the TDFN12 package and is offered in several options  
among features such as selectable threshold, hysteresis, timeouts, output types, etc. (see  
Table 8 and Table 9 for more information).  
Figure 1.  
Application hookup  
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REGULATORꢇ ETCꢈ  
2
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ꢃꢂꢅ  
6
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%. ꢃ%.ꢅ  
6
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2
##  
2
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234  
234  
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03  
(/,$  
0"  
.-) OR ).4  
34-ꢀꢀꢁꢁ  
34-ꢀꢀꢁꢂ  
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ꢃꢄꢅ  
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)ꢋ/  
/54  
6
2%&  
-#5  
32  
#05  
ꢃꢉꢅ  
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!-ꢁꢁꢉꢊꢀVꢊ  
1. A resistor is required for open drain output type only. A 10 kΩ pull-up is sufficient in most applications.  
2. Capacitor CREF is mandatory on VREF output (even if VREF is not used). Capacitor value of 1 µF is recommended.  
3. For the STM6601 the processor has to confirm the proper power-on during the fixed time period, tON_BLANK. This failsafe  
feature prevents the user from turning on the system when there is a faulty power switch or an unresponsive  
microprocessor.  
Doc ID 15453 Rev 7  
5/51  
Description  
STM6600 - STM6601  
Figure 2.  
Basic functionality (option with enable deassertion after long push)  
INTERRUPT  
(short push)  
POWER DOWN  
(long push)  
POWER-UP(1)  
PB  
SR  
EN  
INT  
interrupt  
interrupt  
AM00243v1  
1. For power-up the battery voltage has to be above VTH+ threshold.  
Figure 3.  
Basic functionality (option with RST assertion after long push)  
INTERRUPT  
(short push)  
POWER DOWN  
(long push)  
POWER-UP(1)  
PB  
SR  
RST  
INT  
interrupt  
interrupt  
AM00243bv1  
1. For power-up the battery voltage has to be above VTH+ threshold.  
Figure 4.  
Logic diagram  
V
CC  
EN (EN)  
RST  
PB  
SR  
INT  
STM6600  
STM6601  
PB  
PS  
OUT  
HOLD  
VCC  
LO  
C
SRD  
V
REF  
GND  
AM00236v1  
6/51  
Doc ID 15453 Rev 7  
STM6600 - STM6601  
Table 2.  
Description  
Pin descriptions  
Symbol  
Pin number  
Function  
1
2
V
Power supply input  
CC  
™
SR  
Smart Reset button input  
3
V
Precise 1.5 V voltage reference  
PS input  
REF  
4
PS  
C
HOLD  
SRD  
HOLD  
™
5
Adjustable Smart Reset delay time input  
Push-button input  
6
PB  
7
VCC  
Output for high threshold comparator output (V  
Status of PB push-button input  
Enable output  
)
TH+  
LO  
8
PB  
OUT  
9
EN or EN  
RST  
10  
11  
12  
Reset output  
INT  
Interrupt output  
GND  
Ground  
Figure 5.  
TDFN12 pin connections  
V
1
12 GND  
CC  
11  
2
3
SR  
INT  
V
10  
RST  
REF  
EN (EN)  
PBOUT  
VCCLO  
9
8
7
4
5
6
PSHOLD  
CSRD  
PB  
AM00245v1  
Doc ID 15453 Rev 7  
7/51  
Description  
Figure 6.  
STM6600 - STM6601  
Block diagram  
VCC  
V
EN (EN)  
LO  
CC  
+
–
+
–
RST  
t
REC  
generator  
V
V
CC  
CC  
PS  
HOLD  
(2)  
(1)  
PB  
V
V
TH–  
TH+  
R
R
SR  
Smart  
logic  
PB  
(3)  
PSHOLD  
Glitch immunity  
Edge detector debounce  
R
INT  
SR  
Glitch immunity  
Edge detector debounce  
V
REF  
GND  
1.5 V  
SRD logic  
C
PB  
SRD  
OUT  
AM00237v3  
1. Internal pull-up resistor connected to PB input (see Table 5 for precise specifications).  
2. Optional internal pull-up resistor connected to SR input (see Table 5 for precise specifications and Table 10 for detailed  
device options).  
3. Internal pull-down resistor is connected to PSHOLD input only during startup (see Figure 7, 8, 9, 10, 11, 12, 13, and 18).  
8/51  
Doc ID 15453 Rev 7  
STM6600 - STM6601  
Pin descriptions  
2
Pin descriptions  
V
- power supply input  
CC  
V
is monitored during startup and normal operation for sufficient voltage level. Decouple  
CC  
the V pin from ground by placing a 0.1 µF capacitor as close to the device as possible.  
CC  
™
SR - Smart Reset button input  
This input is equipped with voltage detector with a factory-trimmed threshold and has 8 kV  
HBM ESD protection.  
Both PB and SR buttons have to be pressed and held for t  
period so the long push is  
SRD  
recognized and the reset is asserted (or the enable output is deasserted depending on the  
option) - see Figure 15, 16, and 17.  
Active low SR input is usually connected to GND through the momentary push-button (see  
Figure 1) and it has an optional 100 kΩ pull-up resistor. It is also possible to drive this input  
using an external device with either open drain (recommended) or push-pull output. Open  
drain output can be connected in parallel with push-button or other open drain outputs,  
which is not possible with push-pull output.  
V
- external precise 1.5 V voltage reference  
REF  
This 1.5 V voltage reference is specified with very tight accuracy of 1% (see Table 5). It has  
proper output voltage as soon as the reset output is deasserted (i.e. after t expires) and  
REC  
it is disabled when the device enters standby mode. A mandatory capacitor needs to be  
connected to V  
recommended.  
output (even if V  
is not used). Capacitor value of 1 µF is  
REF  
REF  
PS  
input  
HOLD  
This input is equipped with a voltage detector with a factory-trimmed threshold. It is used to  
confirm correct power-up of the device (if EN or EN is not asserted) or to initiate a shutdown  
(if EN or EN is asserted).  
Forcing PS  
high during power-up confirms the proper start of the application and keeps  
HOLD  
enable output asserted. Because most processors have outputs in high-Z state before  
initialization, an internal pull-down resistor is connected to PS  
input during startup (see  
HOLD  
Figure 7, 8, 9, 10, 11, 12, 13, and 18).  
Forcing the PS  
signal low during normal operation deasserts the enable output (see  
HOLD  
Figure 14). Input voltage on this pin is compared to an accurate voltage reference.  
™
C
- Smart Reset delay time input  
SRD  
A capacitor to ground determines the additional time (t  
) that PB with SR must be  
SRD  
pressed and held before a long push is recognized. The connected C  
capacitor is  
SRD  
™
charged with I  
current. Additional Smart Reset delay time t  
ends when voltage on  
SRD  
SRD  
the C  
capacitor reaches the V  
voltage threshold. It is recommended to use a low  
SRD  
SRD  
ESR capacitor (e.g. ceramic). If the capacitor is not used, leave the C  
pin open. If no  
SRD  
capacitor is connected, there is no t  
and a long push is recognized right after t  
SRD  
INT_Min  
expires (see Figure 18 and 19).  
Doc ID 15453 Rev 7  
9/51  
Pin descriptions  
STM6600 - STM6601  
PB - power ON switch  
This input is equipped with a voltage detector with a factory-trimmed threshold and has  
8 kV HBM ESD protection.  
When the PB button is pressed and held, the battery voltage is detected and EN (or EN) is  
asserted if the battery voltage is above the threshold V  
during the whole t  
TH+  
DEBOUNCE  
period (see Figure 13).  
A short push of the push-button during normal operation can initiate an interrupt through  
debounced INT output (see Figure 14) and a long push of PB and SR simultaneously can  
either assert reset output RST (see Figure 18) or deassert the EN or EN output (see  
Figure 19) based on the option used.  
Note:  
A switch to GND must be connected to this input (e.g. mechanical push-button, open drain  
output of external circuitry, etc.), see Figure 1. This ensures a proper startup signal on PB  
(i.e. a transition from full V below specified V ). PB input has an internal 100 kΩ pull-up  
CC  
IL  
resistor connected.  
VCC - high threshold detection output  
LO  
During power-up, VCC is low when V supply voltage is below the V threshold. After  
TH+  
LO  
CC  
successful power-up (i.e. during normal operation) VCC is low anytime undervoltage is  
LO  
detected (see Figure 13).  
Output type is active low and open drain by default. Open drain output type requires a pull-  
up resistor. A 10 kΩ is sufficient in most applications.  
VCC is floating when STM660x is in standby mode.  
LO  
PB  
- PB input state  
OUT  
If the push-button PB is pressed, the pin stays low during the t  
time period.  
DEBOUNCE  
If PB is asserted for the entire t  
period, PB  
will then stay low for at least  
DEBOUNCE  
OUT  
t
. If PB is asserted after t  
expires, PB  
will return high as soon as PB is  
INT_Min  
INT_Min  
OUT  
deasserted (see Figure 22). PB  
ignores PB assertion during an undervoltage condition.  
will respond only to the first PB assertion and any other  
OUT  
At startup on the STM6601 PB  
OUT  
assertion will be ignored until t  
expires. This output is active low and open drain by  
ON_BLANK  
default. Open drain output type requires a pull-up resistor. A 10 kΩ is sufficient in most  
applications.  
10/51  
Doc ID 15453 Rev 7  
STM6600 - STM6601  
Pin descriptions  
EN or EN - enable output  
This output is intended to enable system power (see Figure 1). EN is asserted high after  
a valid turn-on event has been detected and confirmed (i.e. push-button has been pressed  
and held for t  
or more and V > V  
voltage level has been detected - see  
DEBOUNCE  
CC  
TH+  
Figure 13). EN is released low if any of the conditions below occur:  
a) the push-button is released before PS is driven high (valid for STM6600, see  
HOLD  
Figure 9) or t  
expires before PS  
is driven high during startup (valid  
ON_BLANK  
HOLD  
for both STM6600 and STM6601, see Figure 10 and 12).  
b) PS is driven low during normal operation (see Figure 14).  
HOLD  
c) an undervoltage condition is detected for more than t  
+ t  
+ t  
SRD  
INT_Min DEBOUNCE  
(see Figure 21).  
d) a long push of the buttons is detected (only for the device with option “EN  
deasserted by long push” - see Figure 19) or PS is not driven high during  
HOLD  
t
after a long push of the buttons (only for the device with option “RST  
ON_BLANK  
asserted by long push” - see Figure 18).  
Described logic levels are inverted in case of EN output. Output type is push-pull by default.  
RST - reset output  
This output pulls low for t  
:
REC  
a) during startup. PB has been pressed (falling edge on the PB detected) and held  
for at least t and V > V (see Figure 7, 8, 9, 10, 11, 12 and 13 for  
DEBOUNCE  
CC  
TH+  
more details).  
b) after long push detection (valid only for the device with option “RST asserted by  
long push”). PB has been pressed (falling edge on the PB detected) and held for  
™
more than t  
+ t  
(additional Smart Reset delay time can be adjusted  
DEBOUNCE  
SRD  
by the external capacitor C  
) - see Figure 18.  
SRD  
Output type is active low and open drain by default. Open drain output type requires a pull-  
up resistor. A 10 kΩ is sufficient in most applications.  
INT - interrupt output  
While the system is under normal operation (PS  
is driven high, power for application is  
HOLD  
asserted), the INT is driven low if:  
a)  
V
falls below V  
threshold (i.e. undervoltage is detected - see Figure 20 and  
TH-  
CC  
21).  
b) the falling edge on the PB is detected and the push-button is held for t  
or  
DEBOUNCE  
more. INT is driven low after t  
and stays low as long as PB is held. The  
DEBOUNCE  
INT signal is held high during power-up.  
The state of the PB output can be used to determine if the interrupt was caused by  
OUT  
either the assertion of the PB input, or was due to the detection of an undervoltage condition  
on V  
.
CC  
INT output is asserted low for at least t  
.
INT_Min  
Output type is active low and open drain by default. Open drain output type requires a pull-  
up resistor. A 10 kΩ is sufficient in most applications.  
GND - ground  
Doc ID 15453 Rev 7  
11/51  
Operation  
STM6600 - STM6601  
3
Operation  
™
The STM6600-STM6601 simplified smart push-button on/off controller with Smart Reset  
and power-on lockout enables and disables power for the application depending on push-  
button states, signals from the processor, and battery voltage.  
Power-on  
Because most of the processors have outputs in high-Z state before initialization, an internal  
pull-down resistor is connected to PS  
input during startup (see Figure 7, 8, 9, 10, 11,  
HOLD  
12, 13, and 18).  
To power up the device the push-button PB has to be pressed for at least t  
and  
DEBOUNCE  
V
has to be above V  
for the whole t  
period. If the battery voltage drops  
CC  
TH+  
DEBOUNCE  
below V  
during the t  
, the counter is reset and starts to count again when V  
>
TH+  
DEBOUNCE  
CC  
V
(see Figure 13). After t  
the enable signal is asserted (EN goes high, EN  
TH+  
DEBOUNCE  
goes low), reset output RST is asserted for t  
and then the startup routine is performed  
REC  
by the processor. During initialization, the processor sets the PS  
signal high.  
HOLD  
On the STM6600 the PS  
signal has to be set high prior to push-button release and  
HOLD  
t
expiration, otherwise the enable signal is deasserted (EN goes low, EN goes  
ON_BLANK  
high) - see Figure 7, 8, 9, and 10. The time up to push-button release represents the  
maximum time allowed for the system to power up and initialize the circuits driving the  
PS  
input. If the PS  
signal is low at push-button release, the enable output is  
HOLD  
HOLD  
deasserted immediately, thus turning off the system power. If t  
expires prior to  
ON_BLANK  
push-button release, the PS  
state is checked at its expiration. This safety feature  
HOLD  
disables the power and prevents discharging the battery if the push-button is stuck or it is  
held for an unreasonable period of time and the application is not responding (see Figure 8  
and 10). PB status, INT status and V undervoltage detection are not monitored until  
CC  
power-up is completed.  
On the STM6601 the PS  
signal has to be set high before t  
expires, otherwise  
ON_BLANK  
HOLD  
the enable signal is deasserted - see Figure 11 and 12. In this case the t  
period is  
ON_BLANK  
the maximum time allowed for the power switch and processor to perform the proper power-  
on. If the PS signal is low at the end of the blanking period, the enable output is  
HOLD  
released immediately, thus turning off the system power. PB status, INT status and V  
CC  
undervoltage detection are not monitored during the entire t  
period. This failsafe  
ON_BLANK  
feature prevents the user from turning on the system when there is a faulty power switch or  
an unresponsive microprocessor.  
Push-button interrupt  
If the device works under normal operation (i.e. PS  
is high) and the push-button PB is  
HOLD  
pressed for more than t  
, a negative pulse with minimum t  
_
width is  
DEBOUNCE  
INT Min  
generated on the INT output. By connecting INT to the processor interrupt input (INT or  
NMI) a safeguard routine can be performed and the power can be shut down by setting  
PS  
low - see Figure 14.  
HOLD  
Forced power-down mode  
The PS output can be forced low anytime during normal operation by the processor  
HOLD  
and can deassert the enable signal - see Figure 14.  
12/51  
Doc ID 15453 Rev 7  
STM6600 - STM6601  
Operation  
Undervoltage detection  
If V voltage drops below V  
voltage threshold during normal operation, the INT output is  
TH-  
CC  
driven low (see Figure 20 and Figure 21).  
If an undervoltage condition is detected for t  
+ t  
+ t  
, the enable output is  
DEBOUNCE  
INT_Min  
SRD  
deasserted (see Figure 21).  
Hardware reset or power-down while system not responding  
If the system is not responding and the system hangs, the PB and SR push-buttons can be  
pressed simultaneously longer than t + t + t , and then  
DEBOUNCE  
INT_Min  
SRD  
a) either the reset output RST is asserted for t  
and the processor is reset (valid  
REC  
only for the device with option “RST asserted by long push”) – see Figure 18  
b) or the power is disabled by EN or EN signal (valid only for the device with option  
“EN deasserted by long push”) – see Figure 19  
The t  
is set by the external capacitor connected to the C  
pin.  
SRD  
SRD  
Standby  
If the enable output is deasserted (i.e. EN is low or EN is high), the STM660x device enters  
standby mode with low current consumption (see Table 5). In standby mode PB input is only  
monitored for the falling edge. The external 1.5 V voltage reference is also disabled in  
standby mode.  
Doc ID 15453 Rev 7  
13/51  
Waveforms  
4
STM6600 - STM6601  
Waveforms  
Figure 7.  
Successful power-up on STM6600 (PB released prior to t  
expiration)  
ON_BLANK  
PB released prior to t ON_BLANK  
expiration  
PSHOLD state detected as high  
EN remains asserted  
Push-button pressed and  
PB connected to GND  
processor  
sets PSHOLD  
VCC undervoltage detection  
ignored  
PB(1)  
PSHOLD  
ignored  
internal pull-down resistor  
connected to PSHOLD input  
(2)  
PSHOLD  
EN(3)  
RST  
tDEBOUNCE  
tREC  
tON_BLANK  
Note:  
INT signal is held high during power-up (i.e. until PB release in this case).  
CC is considered VCC > VTH+  
V
.
AM00247v3  
1. PB detection on falling and rising edges.  
2. Internal pull-down resistor 300 kΩis connected to PSHOLD input during power-up.  
3. EN signal is high even after PB release, because processor sets PSHOLD signal high before PB is released.  
14/51  
Doc ID 15453 Rev 7  
STM6600 - STM6601  
Waveforms  
Figure 8.  
Successful power-up on STM6600 (t  
expires prior to PB release)  
ON_BLANK  
tON_BLANK expired prior to PB  
release  
PSHOLD state detected as high  
EN remains asserted  
Push-button pressed and  
PB connected to GND  
processor  
sets PSHOLD  
PB released  
VCC undervoltage detection  
ignored  
PB(1)  
PSHOLD  
ignored  
internal pull-down resistor  
connected to PSHOLD input  
(2)  
PSHOLD  
EN(3)  
RST  
tDEBOUNCE  
tREC  
tON_BLANK  
Note:  
INT signal is held high during power-up (i.e. until t  
expires in this case).  
ON_BLANK  
V
CC is considered VCC > VTH+  
.
AM00247bv2  
1. PB detection on falling and rising edges.  
2. Internal pull-down resistor 300 kΩis connected to PSHOLD input during power-up.  
3. tON_BLANK expires prior to PB release so PSHOLD is checked at its expiration.  
Doc ID 15453 Rev 7  
15/51  
Waveforms  
Figure 9.  
STM6600 - STM6601  
Unsuccessful power-up on STM6600 (PB released prior to t  
)
ON_BLANK  
PB released  
PSHOLD state detected as low  
EN deasserted  
Push-button pressed and  
PB connected to GND  
VCC undervoltage detection  
ignored  
PB status  
ignored  
PB(1)  
PSHOLD  
ignored  
internal pull-down resistor  
connected to PSHOLD input  
(2)  
PSHOLD  
EN(3)  
RST  
tEN_OFF  
tDEBOUNCE  
tREC  
tON_BLANK  
Note:  
INT signal is held high during power-up (i.e. until PB release in this case).  
CC is considered VCC > VTH+  
V
.
AM00248v3  
1. PB detection on falling and rising edges.  
2. Internal pull-down resistor 300 kΩis connected to PSHOLD input during power-up.  
3. EN signal goes low with PB release, because processor did not force PSHOLD signal high.  
16/51  
Doc ID 15453 Rev 7  
STM6600 - STM6601  
Waveforms  
Figure 10. Unsuccessful power-up on STM6600 (t  
expires prior to PB release)  
ON_BLANK  
tON_BLANK expired prior to PB release  
PSHOLD state detected as low  
EN is deasserted  
Push-button pressed and  
PB connected to GND  
PB released  
PB status  
ignored  
PB(1)  
VCC undervoltage detection ignored  
PSHOLD  
ignored  
internal pull-down resistor connected to  
PSHOLD input  
(2)  
PSHOLD  
EN(3)  
RST  
tEN_OFF  
tDEBOUNCE  
tREC  
tON_BLANK  
Note:  
INT signal is held high during power-up (i.e. until t  
expires in this case).  
ON_BLANK  
V
CC is considered VCC > VTH+  
.
AM00248bv2  
1. PB detection on falling and rising edges.  
2. Internal pull-down resistor 300 kΩis connected to PSHOLD input during power-up.  
3. tON_BLANK expires prior to PB release so PSHOLD is checked at its expiration.  
Doc ID 15453 Rev 7  
17/51  
Waveforms  
STM6600 - STM6601  
Figure 11. Successful power-up on STM6601  
t
expires  
ON_BLANK  
PS state detected as high  
Push-button pressed and  
PB connected to GND  
processor  
sets PS  
HOLD  
EN remains asserted  
HOLD  
PB status and V  
undervoltage  
(1)  
CC  
detection ignored  
PB  
PS  
ignored  
HOLD  
(2)  
HOLD  
internal pull-down resistor  
connected to PS input  
PS  
HOLD  
(3)  
EN  
RST  
t
DEBOUNCE  
t
REC  
t
ON_BLANK  
Note:  
INT signal is held high during power-up (i.e. until t  
expires in the case of the STM6601).  
ON_BLANK  
V
CC is considered VCC > VTH+.  
AM00250v2  
1. PB detection on falling edge.  
2. Internal pull-down resistor 300 kΩis connected to PSHOLD input during power-up.  
3. PSHOLD signal is ignored during tON_BLANK. When tON_BLANK expires, the level of the PSHOLD signal is high therefore the  
EN signal remains asserted.  
18/51  
Doc ID 15453 Rev 7  
STM6600 - STM6601  
Waveforms  
Figure 12. Unsuccessful power-up on STM6601  
t
expires  
ON_BLANK  
Push-button pressed and  
PB connected to GND  
Push-button pressed and  
PB connected to GND  
PSHOLD state detected as low  
EN deasserted  
(1)  
PB  
PSHOLD ignored  
(2)  
intenal pull-down resistor  
connected to PS input  
PSHOLD  
HOLD  
(3)  
EN  
RST  
t
t
DEBOUNCE  
REC  
Note:  
INT signal is held high during power-up (i.e. until t  
expires in the case of the STM6601).  
ON_BLANK  
V
CC is considered VCC > VTH+.  
AM00238v2  
1. PB detection on falling edge.  
2. Internal pull-down resistor 300 kΩis connected to PSHOLD input during power-up.  
3. PSHOLD signal is ignored during tON_BLANK. When tON_BLANK expires, the level of the PSHOLD signal is not high therefore  
the EN signal goes low. Even releasing the PB button after the tON_BLANK will not prevent this.  
Doc ID 15453 Rev 7  
19/51  
Waveforms  
STM6600 - STM6601  
Figure 13. Power-up on STM660x with voltage dropout  
Push-button pressed and  
PB connected to GND  
V
t
goes above V  
and  
is counted again  
TH+  
CC  
DEBOUNCE  
V
TH+  
V
TH–  
V
V
CC  
CC–Min  
V
CC  
under-  
voltage  
detected  
V
drop  
CC  
VCC  
LO  
(1)  
PB  
(2)  
HOLD  
internal pull-down resistor  
PS  
connected to PS  
input  
HOLD  
(3)  
INT signal is held high during power-up  
INT  
EN  
RST  
< tDEBOUNCE  
t
tREC  
DEBOUNCE  
< tON_BLANK  
AM00249v2  
1. PB detection on falling and rising edges.  
2. Internal pull-down resistor 300 kΩis connected to PSHOLD input during power-up.  
3. INT signal is held high during power-up.  
20/51  
Doc ID 15453 Rev 7  
STM6600 - STM6601  
Waveforms  
Figure 14. PB interrupt  
processor interrupt starts power-down sequence  
processor sets PS  
HOLD  
low  
Push-button pressed and  
PB connected to GND  
and EN is deasserted  
accordingly  
PB status  
ignored  
(1,2)  
PB  
PSHOLD  
PB status  
ignored  
VCC undervoltage  
detection ignored  
t
t
t
DEBOUNCE  
EN_OFF  
INT_Min  
Note: VCC is considered VCC > VTH+  
.
AM00251v2  
1. PB detection on falling edge.  
2. PB is released within tSRD and that is why NO reset is asserted and EN is NOT deasserted immediately.  
Doc ID 15453 Rev 7  
21/51  
Waveforms  
STM6600 - STM6601  
Figure 15. Long push, PB pressed first  
Push-button  
PB is pressed  
t
starts to  
Push-button  
SR is pressed  
SRD  
be counted  
t
t
SRD  
DEBOUNCE  
PB  
SR  
set by C  
SRD  
t
DEBOUNCE  
INT  
PB status  
ignored  
t
INT_Min  
AM00257v1  
Figure 16. Long push, SR pressed first  
t
starts to  
Push-button  
SR is pressed  
Push-button  
PB is pressed  
SRD  
be counted  
t
DEBOUNCE  
PB  
t
SRD  
SR  
set by C  
SRD  
INT  
PB status  
ignored  
t
INT_Min  
AM00258v1  
22/51  
Doc ID 15453 Rev 7  
STM6600 - STM6601  
Waveforms  
Figure 17. Invalid long push  
Push-button  
PB is pressed  
Any rising edge will stop  
to count regardless  
Push-button  
SR is pressed  
t
starts to  
SRD  
be counted  
t
SRD  
of glitch immunity  
t
DEBOUNCE  
PB  
SR  
INT  
< t  
SRD  
set by C  
SRD  
PB status  
ignored  
t
INT_Min  
AM00259v1  
Doc ID 15453 Rev 7  
23/51  
Waveforms  
STM6600 - STM6601  
Figure 18. Long push (option with RST assertion)  
tON_BLANK expires  
PSHOLD state detected as high  
therefore EN remains high  
Push-button pressed  
and PB connected to  
GND  
Push-button held even  
after tSRD expires  
therefore RST is asserted  
After tON_BLANK  
PB is monitored  
for falling edge  
(1)  
tON_BLANK  
tSRD  
PB  
SR  
set by CSRD  
(valid for STM6600 and STM6601)  
INT can go high, if PB goes high,  
but system freezes and processor  
won’t respond  
PB status  
ignored  
INT(2)  
VCC undervoltage detection status ignored  
RST  
PSHOLD ignored  
internal pull-down resistor  
connected to PSHOLD input  
if system freezes, processor won’t  
respond to any INT status change  
(3, 4)  
PSHOLD  
tDEBOUNCE  
tINT  
tREC  
tDEBOUNCE  
_
Min  
Note: EN is high.  
AM00252v2  
1. tSRD period is set by external capacitor CSRD  
2. PB ignored during tINT_Min  
.
.
3. PSHOLD signal is ignored during tON_BLANK. Its level is checked after tON_BLANK expires and if it is high the EN signal  
remains asserted, otherwise EN goes low.  
4. Internal pull-down resistor 300 kΩis connected to PSHOLD input during startup when device is reset.  
24/51  
Doc ID 15453 Rev 7  
STM6600 - STM6601  
Waveforms  
Figure 19. Long push (option with enable deassertion)  
Push-button  
pressed and PB  
connected to GND  
Push-button held even  
after tSRD expires and  
EN is deasserted  
After tEN_OFF expires  
PB is monitored for  
falling edge  
(1)  
PB status  
tSRD  
PB  
SR  
set by CSRD  
ignored  
INT can go high, if PB goes high,  
but system freezes and processor  
won’t respond  
PB status  
ignored  
INT(2)  
EN(3)  
VCC undervoltage detection status ignored  
if system freezes, processor won’t  
respond to any INT status change  
PSHOLD  
tDEBOUNCE  
t INT  
tEN  
tDEBOUNCE  
_
_
OFF  
Min  
AM00253v2  
1. tSRD period is set by external capacitor CSRD  
2. PB ignored during tINT_Min  
3. After tSRD expires EN is forced low.  
.
.
Doc ID 15453 Rev 7  
25/51  
Waveforms  
STM6600 - STM6601  
Figure 20. Undervoltage detected for <t  
SRD  
processor interrupt starts power-down sequence  
VCC  
undervoltage  
detected  
processor sets PSHOLD low  
and EN is deasserted  
(1)  
CC  
VTH+  
V
(2)  
accordingly  
tSRD  
PB status  
ignored  
VTH  
–
set by CSRD  
V
CC-Min  
VCCLO  
V
PSHOLD  
CC  
under-  
voltage  
detection  
ignored  
INT  
EN  
PB status ignored  
tINT_Min  
tDEBOUNCE  
tEN_OFF  
AM00254v1  
1.  
VCC goes above VTH+ within tSRD thus power is not disabled after tSRD expires.  
2. tSRD period is set by external capacitor CSRD  
.
Figure 21. Undervoltage detected for >t  
SRD  
V
V
is below V  
even after t expires  
SRD  
CC  
CC  
TH+  
thus power is disabled (EN goes low) and  
PB is monitored for regular startup  
undervoltage  
detected  
V
V
TH+  
(2)  
t
SRD  
(1)  
CC  
–
TH  
V
set by C  
SRD  
V
CC-Min  
VCC  
LO  
PS  
HOLD  
INT  
V
CC  
under-  
voltage  
detection  
ignored  
PB status ignored  
PB status  
ignored  
EN  
t
t
t
DEBOUNCE  
INT_Min  
EN_OFF  
AM00255v1  
1. After tSRD expires VCC is still insufficient (below VTH+) thus power is disabled (EN goes low or EN goes high).  
2. tSRD period is set by external capacitor CSRD  
.
26/51  
Doc ID 15453 Rev 7  
STM6600 - STM6601  
Waveforms  
Figure 22. PB  
output waveform  
OUT  
<glitch immunity  
(1,2,3,4)  
PB  
PBOUT  
t
t
INT_min  
DEBOUNCE  
AM00256v1  
1. Pulses on PB shorter than glitch immunity are ignored.  
2. Pulses on PB shorter than tDEBOUNCE are not recognized by PBOUT  
3. Minimum pulse width on PBOUT is tINT_Min  
4. If push-button is held longer than tDEBOUNCE + tINT_Min, PBOUT goes high when the push-button is released.  
.
.
Doc ID 15453 Rev 7  
27/51  
Typical operating characteristics  
STM6600 - STM6601  
5
Typical operating characteristics  
Figure 23. Supply current vs. temperature, normal state  
7.0  
6.5  
6.0  
5.5  
5.0  
4.5  
4.0  
3.5  
3.0  
V
V
= 5.5 V  
CC  
= 3.6 V  
CC  
V
= 2.0 V  
CC  
-40  
-20  
0
20  
40  
60  
80  
Temperature, TA (°C)  
AM04701v1  
Figure 24. Supply current vs. temperature, standby state  
2.0  
V
= 5.5 V  
CC  
V
= 3.6 V  
CC  
1.5  
1.0  
0.5  
0.0  
V
= 2.0 V  
CC  
-40  
-20  
0
20  
40  
60  
80  
Temperature, TA (°C)  
AM04702v1  
28/51  
Doc ID 15453 Rev 7  
STM6600 - STM6601  
Typical operating characteristics  
Figure 25. Supply current vs. supply voltage, normal state  
7
6
5
4
3
2
1
0
T
T
T
T
= 85 °C  
= 25 °C  
= 0 °C  
A
A
A
A
= –40 °C  
2.0  
2.5  
3.0  
3.5  
4.0  
CC  
4.5  
5.0  
5.5  
Supply voltage, V  
(V)  
AM04703v1  
Figure 26. Supply current vs. supply voltage, standby state  
1.5  
T
T
T
T
= 85 °C  
= 25 °C  
= 0 °C  
A
A
A
A
1.0  
0.5  
0.0  
= –40 °C  
2.0  
2.5  
3.0  
3.5  
4.0  
CC  
4.5  
5.0  
5.5  
Supply voltage, V  
(V)  
AM04704v1  
Doc ID 15453 Rev 7  
29/51  
Typical operating characteristics  
STM6600 - STM6601  
Figure 27. Threshold vs. temperature, V  
= 3.4 V (typ.)  
TH+  
3.50  
3.45  
3.40  
3.35  
3.30  
3.25  
3.20  
-40  
-20  
0
20  
40  
60  
80  
Temperature, TA (°C)  
AM04705v1  
Figure 28. Threshold hysteresis vs. temperature, V  
= 200 mV (typ.)  
HYST  
230  
220  
210  
200  
190  
180  
170  
-40  
-20  
0
20  
40  
60  
80  
Temperature, T (°C)  
A
AM04706v1  
30/51  
Doc ID 15453 Rev 7  
STM6600 - STM6601  
Typical operating characteristics  
Figure 29. Debounce period vs. supply voltage  
45  
40  
35  
30  
25  
20  
15  
T
T
T
T
= 85 °C  
= 25 °C  
= 0 °C  
A
A
A
A
= –40 °C  
3.5  
4
4.5  
5
5.5  
Supply voltage, V  
(V)  
CC  
AM04707v1  
Figure 30.  
C
charging current vs. temperature, V = 3.6 V  
SRD  
CC  
200  
190  
180  
170  
160  
150  
140  
130  
120  
110  
100  
VCC = 5.5 V  
VCC = 3.6 V  
VCC = 2 V  
-40  
-20  
0
20  
40  
60  
80  
Temperature, TA (°C)  
AM04708v1  
Doc ID 15453 Rev 7  
31/51  
Typical operating characteristics  
STM6600 - STM6601  
Figure 31. Output low voltage vs. output low current, T = 25°C  
A
0.30  
0.25  
0.20  
0.15  
0.10  
0.05  
0.00  
V
V
V
=1.6V  
=3.6V  
=5.5V  
CC  
CC  
CC  
0
1
2
3
4
5
Output low current, I (mA)  
OL  
AM04709v1  
Note:  
Characteristics valid for all the outputs (EN, EN, RST, INT, PB  
and VCC ).  
OUT LO  
Figure 32. Output high voltage vs. output high current, T = 25°C  
A
0.8  
V
=1.6V  
=3.6V  
=5.5V  
CC  
V
CC  
0.6  
0.4  
0.2  
0
V
CC  
0
0.5  
1
1.5  
2
Output high current, I  
(mA)  
OH  
AM04710v1  
Note:  
Characteristics valid for EN and EN outputs.  
32/51  
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STM6600 - STM6601  
Typical operating characteristics  
Figure 33. Output voltage vs. supply voltage, I  
= 1 mA, T = 25 °C  
A
OUT  
1
0.8  
0.6  
0.4  
0.2  
0
0
1
2
3
4
5
Supply voltage, V  
(V)  
CC  
AM04711v1  
Note:  
Characteristics valid for all the outputs (EN, EN, RST, INT, PB  
and VCC ).  
OUT  
LO  
Figure 34. Input voltage vs. temperature  
1.05  
V
V
= 3.6 V  
CC  
1.04  
1.03  
1.02  
1.01  
1.00  
0.99  
= 5.5 V  
CC  
-40  
-20  
0
20  
40  
60  
80  
Temperature, T (°C)  
A
AM04712v1  
Note:  
Characteristics valid for PB, SR and PS  
inputs.  
HOLD  
Doc ID 15453 Rev 7  
33/51  
Typical operating characteristics  
STM6600 - STM6601  
Figure 35. Reference output voltage vs. temperature, V = 2.0 V  
CC  
1.520  
1.515  
1.510  
1.505  
1.500  
1.495  
1.490  
1.485  
1.480  
I
= 0 mA  
REF  
I
= 15 µA  
REF  
-40  
-20  
0
20  
40  
60  
80  
Temperature, TA (°C)  
AM04713v1  
Note:  
1 µF capacitor is connected to the V  
pin.  
REF  
Figure 36. Reference output voltage vs. load current, V = 2.0 V, T = 25 °C  
CC  
A
1.6  
1.5  
1.4  
1.3  
1.2  
1.1  
1
0
50  
100  
150  
200  
250  
300  
Load current, I  
(µA)  
REF  
AM04714v1  
Note:  
1 µF capacitor is connected to the V  
pin.  
REF  
34/51  
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STM6600 - STM6601  
Typical operating characteristics  
Figure 37. Reference output voltage vs. supply voltage, T = 25 °C  
A
1.520  
1.515  
1.510  
1.505  
1.500  
1.495  
1.490  
1.485  
1.480  
I
= 0 µA  
REF  
IREF = 15 µA  
2
2.5  
3
3.5  
4
4.5  
5
5.5  
Supply voltage, V  
(V)  
CC  
AM04715v1  
Note:  
1 µF capacitor is connected to the V  
pin.  
REF  
Figure 38. Reference startup, I  
= 15 µF, T = 25 °C  
A
REF  
Note:  
1 µF capacitor is connected to the V  
pin.  
REF  
Doc ID 15453 Rev 7  
35/51  
Typical operating characteristics  
STM6600 - STM6601  
Figure 39. Reference response to steps on supply voltage, I  
= 15 µA, T = 25 °C  
A
REF  
Note:  
1
2
Supply voltage goes from 3.6 V to 5.5 V and back to 3.6 V, ramp 1 V / 100 ns.  
1 µF capacitor is connected to the V pin.  
REF  
36/51  
Doc ID 15453 Rev 7  
STM6600 - STM6601  
Typical operating characteristics  
Figure 40. Reference response to steps in load current, V = 3.6 V, T = 25 °C  
CC  
A
Note:  
1
2
Supply voltage goes from 0 µA to 15 µA and back to 0 µA, ramp 1 µA / 100 ns.  
1 µF capacitor is connected to the V pin.  
REF  
Doc ID 15453 Rev 7  
37/51  
Maximum ratings  
STM6600 - STM6601  
6
Maximum ratings  
Stressing the device above the rating listed in the absolute maximum ratings table may  
cause permanent damage to the device. These are stress ratings only and operation of the  
device at these or any other conditions above those indicated in the operating sections of  
this specification is not implied. Exposure to absolute maximum rating conditions for  
extended periods may affect device reliability. Refer also to the STMicroelectronics SURE  
Program and other relevant quality documents.  
Table 3.  
Symbol  
Absolute maximum ratings  
Parameter  
Input supply voltage  
Input voltages on PB, SR, PS  
Min.  
Max.  
Unit  
Remarks  
V
–0.3  
+7.0  
V
CC  
and  
HOLD  
–0.3  
–0.3  
V
V
+ 0.3  
V
V
CC  
CC  
C
SRD  
Output voltages on EN (EN), RST and  
INT  
+ 0.3  
–2  
–8  
+2  
kV Human body model (all pins)  
V
Electrostatic protection  
ESD  
+8  
+1000  
+200  
+8  
kV Human body model (PB and SR)  
V
V
V
V
Electrostatic protection  
–1000  
–200  
–8  
V
V
Charged device model  
Machine model  
ESD  
ESD  
ESD  
ESD  
Electrostatic protection  
Point discharge on PB and SR inputs  
Air discharge on PB and SR inputs  
Operating ambient temperature  
Storage temperature  
kV IEC61000-4-2  
–15  
–40  
–45  
+15  
kV IEC61000-4-2  
T
+85  
°C  
°C  
°C  
A
T
+150  
+260  
STG  
(1)  
T
Lead solder temperature for 10 seconds  
Thermal resistance (junction to ambient)  
SLD  
+132.4 °C/W  
θJA  
1. Reflow at peak temperature of 260°C. The time above 255°C must not exceed 30 seconds.  
38/51  
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STM6600 - STM6601  
DC and AC characteristics  
7
DC and AC characteristics  
This section summarizes the operating measurement conditions and the DC and AC  
characteristics of the device. The parameters in the DC and AC characteristics tables that  
follow are derived from tests performed under the measurement conditions summarized in  
Table 4. Designers should check that the operating conditions in their circuit match the  
operating conditions when relying on the quoted parameters.  
Table 4.  
Operating and AC measurement conditions  
Parameter  
Condition  
Unit  
V
supply voltage  
1.6 to 5.5  
–40 to 85  
V
CC  
Ambient operating temperature (T )  
°C  
ns  
A
Input rise and fall times  
≤_  
5
Table 5.  
Symbol  
DC and AC characteristics  
Parameter  
(1)  
(2)  
Test condition  
Min.  
Typ.  
Max. Unit  
V
Supply voltage  
1.6  
5.5  
8
V
CC  
V
= 3.6 V, no load  
6
µA  
CC  
I
Supply current  
CC  
Standby mode, enable  
deasserted, V = 3.6 V  
1
µA  
CC  
2.40  
3.00  
3.20  
3.29  
3.39  
2.50  
3.10  
3.30  
3.40  
3.50  
200  
2.60  
3.20  
3.40  
3.51  
3.61  
Power-on lockout voltage  
(see Table 10 for detailed  
listing)  
V
V
TH+  
Threshold hysteresis (see  
Table 10 for detailed listing)  
V
mV  
HYST  
500  
Forced power-off voltage  
(see Table 10 for detailed  
listing)  
V
V
– V  
32  
V
TH–  
TH+  
HYST  
Undervoltage detection to  
INT delay  
t
V
≥ 2.0 V  
20  
44  
ms  
TH–  
CC  
1.4  
5.6  
2.2  
8.8  
3.0  
Blanking period (see  
t
Table 10 for detailed  
12.0  
24.0  
s
ON_BLANK  
(3)  
listing)  
11.2  
17.6  
RST assertion to EN (EN)  
assertion delay during  
power-up  
V
= 3.6 V  
100  
ns  
CC  
Doc ID 15453 Rev 7  
39/51  
DC and AC characteristics  
STM6600 - STM6601  
Table 5.  
Symbol  
DC and AC characteristics (continued)  
Parameter Test condition  
(1)  
(2)  
Min.  
Typ.  
Max. Unit  
PB  
V
Input low voltage  
V
V
V
V
≥ 2.0 V, enable asserted  
≥ 2.0 V, enable asserted  
≥ 2.0 V  
0.99  
V
V
IL  
CC  
CC  
CC  
CC  
V
Input high voltage  
Debounce period  
1.05  
20  
IH  
t
32  
44  
ms  
kΩ  
DEBOUNCE  
R
Internal pull-up resistor  
= 5.5 V, input asserted  
65  
100  
135  
PB  
SR  
V
Input low voltage  
0.99  
V
V
IL  
V
Input high voltage  
Debounce period  
Internal pull-up resistor  
1.05  
20  
IH  
t
32  
44  
ms  
kΩ  
DEBOUNCE  
(4)  
R
V
V
= 5.5 V, input asserted  
65  
100  
135  
SR  
CC  
CC  
PB  
OUT  
= 2 V, I  
= 1 mA,  
SINK  
V
Output low voltage  
0.3  
V
OL  
PB  
asserted  
OUT  
V
drain  
= 3 V, PB  
open  
OUT  
PBOUT  
PB  
leakage current  
–0.1  
–0.1  
+0.1  
µA  
OUT  
VCC  
LO  
V
= 2 V, I  
= 1 mA,  
CC  
SINK  
V
Output low voltage  
0.3  
V
OL  
VCC asserted  
LO  
V
drain  
= 3 V, VCC open  
LO  
VCCLO  
VCC leakage current  
+0.1  
µA  
LO  
PS  
HOLD  
V
Input low voltage  
Input high voltage  
Glitch immunity  
V
V
≥ 2.0 V  
0.99  
V
V
IL  
CC  
CC  
V
≥ 2.0 V  
1.05  
1
IH  
80  
µs  
µA  
PS  
leakage current  
to enable  
V
V
= 0.6 V  
= 5.5 V  
–0.1  
0.1  
30  
HOLD  
PSHOLD  
PSHOLD  
PS  
HOLD  
µs  
propagation delay  
Pull-down resistor  
connected internally during  
power-up  
R
195  
300  
405  
kΩ  
PSHOLD  
40/51  
Doc ID 15453 Rev 7  
STM6600 - STM6601  
DC and AC characteristics  
Table 5.  
Symbol  
DC and AC characteristics (continued)  
(1)  
(2)  
Parameter  
Test condition  
Min.  
Typ.  
Max. Unit  
C
SRD  
I
C
C
charging current  
voltage threshold  
100  
150  
1.5  
200  
nA  
V
SRD  
SRD  
SRD  
V
= 3.6 V, load on V  
pin  
REF  
CC  
V
100 kΩ and mandatory 1 µF  
capacitor, T = 25 °C  
SRD  
A
™
Additional Smart Reset  
delay time  
t
External C  
connected  
10  
s/µF  
SRD  
SRD  
EN, EN  
V
= 2 V, I  
= 1 mA,  
CC  
SINK  
V
Output low voltage  
0.3  
V
V
OL  
enable asserted  
V
= 2 V, I = 1 mA,  
SOURCE  
(5)  
OH  
CC  
V
Output high voltage  
V
– 0.3  
CC  
enable asserted  
(6)  
t
enable off to enable on  
V
V
≥ 2.0 V  
40  
64  
88  
ms  
µA  
EN_OFF  
CC  
EN  
EN, EN leakage current  
= 2 V, enable open drain  
–0.1  
+0.1  
RST  
V
= 2 V, I  
= 1 mA,  
CC  
SINK  
V
Output low voltage  
0.3  
V
OL  
RST asserted  
t
RST pulse width  
V
V
≥ 2.0 V  
240  
360  
480  
ms  
µA  
REC  
CC  
RST leakage current  
= 3V  
–0.1  
+0.1  
RST  
INT  
V
= 2 V, I  
= 1 mA,  
CC  
SINK  
V
Output low voltage  
0.3  
V
OL  
INT asserted  
t
Minimum INT pulse width  
INT leakage current  
V
V
≥ 2.0 V  
20  
32  
44  
ms  
µA  
INT_Min  
CC  
= 3 V  
–0.1  
+0.1  
INT  
V
REF  
V
= 3.6 V, load on V  
pin  
REF  
CC  
1.485  
–1%  
1.515  
+1%  
V
1.5 V voltage reference  
100 kΩ and mandatory 1 µF  
capacitor, T = 25 °C  
1.5  
V
REF  
A
1. Valid for ambient operating temperature: TA = –40 to 85 °C; VCC = 1.6 V to 5.5 V (except where noted).  
2. Typical values are at TA = +25 °C.  
3. This blanking time allows the processor to start up correctly (see Figure 7, 8, 9, 10, 11, 12).  
4. The internal pull-up resistor connected to the SR input is optional (see Table 10 for detailed device options).  
5. Valid for push-pull only.  
6. Minimal delay between enable off and enable on allows the application to power down properly. PB is ignored during this  
period.  
Doc ID 15453 Rev 7  
41/51  
Package mechanical data  
STM6600 - STM6601  
8
Package mechanical data  
In order to meet environmental requirements, ST offers these devices in different grades of  
®
®
ECOPACK packages, depending on their level of environmental compliance. ECOPACK  
specifications, grade definitions and product status are available at: www.st.com.  
®
ECOPACK is an ST trademark.  
42/51  
Doc ID 15453 Rev 7  
STM6600 - STM6601  
Package mechanical data  
Figure 41. TDFN12 (2 x 3 mm) package outline  
D
B
INDEX AREA  
(D/2xE/2)  
0.10  
C
TOP VIEW  
0.10  
C
C
SEATING  
PLANE  
SIDE VIEW  
e
0.08  
C
b
0.10  
C A B  
6
1
PIN#1 ID  
INDEX AREA  
(D/2xE/2)  
12  
7
BOTTOM VIEW  
8070542_A  
Table 6.  
Symbol  
TDFN12 (2 x 3 mm) package mechanical data  
mm  
inches  
Typ.  
Min.  
Typ.  
Max.  
Min.  
Max.  
A
A1  
b
0.70  
0.00  
0.15  
0.75  
0.02  
0.80  
0.05  
0.25  
0.028  
0.000  
0.006  
0.030  
0.001  
0.008  
0.118  
0.079  
0.020  
0.022  
0.031  
0.002  
0.010  
0.20  
D
E
3.00 BSC  
2.00 BSC  
0.50  
e
L
0.45  
0.55  
0.65  
0.018  
0.026  
Doc ID 15453 Rev 7  
43/51  
Package mechanical data  
STM6600 - STM6601  
Figure 42. TDFN12 (2 x 3 mm) recommended footprint  
ꢉꢈꢌꢁ  
ꢃꢁꢈꢂꢁꢁꢅ  
ꢂꢁ X ꢁꢈꢌꢁ  
ꢃꢂꢁ X ꢁꢈꢁꢉꢁꢅ  
ꢁꢈꢐꢁ  
ꢃꢁꢈꢁꢄꢌꢅ  
ꢂꢈꢀꢁ  
ꢃꢁꢈꢁꢀꢄꢅ ꢃꢁꢈꢁꢐꢂꢅ  
ꢉꢈꢄꢁ  
ꢂꢉ X ꢁꢍꢈꢁ  
ꢃꢂꢉ X ꢁꢈꢁꢉꢎꢅ  
ꢂꢉ X ꢁꢈꢉꢌ  
ꢃꢂꢉ X ꢁꢈꢁꢂꢁꢅ  
ꢂꢁ X ꢁꢈꢉꢌ  
ꢃꢂꢁ X ꢁꢈꢁꢂꢁꢅ  
MM  
ꢃINCHES ꢅ  
$IMENSIONSꢏ  
!-ꢁꢍꢄꢄꢉ  
Note:  
Drawing not to scale.  
44/51  
Doc ID 15453 Rev 7  
STM6600 - STM6601  
Package mechanical data  
Figure 43. Carrier tape for TDFN12 (2 mm x 3 mm) package  
P
0
E
P
D
2
T
A
0
F
TOP COVER  
TAPE  
W
B
0
P
1
CENTER LINES  
OF CAVITY  
K
0
USER DIRECTION OF FEED  
AM03073v1  
Table 7.  
Carrier tape dimensions for TDFN12 (2 mm x 3 mm) package  
Bulk  
Qty.  
Package  
W
D
E
P
P
F
A
B
K
P
1
T
Unit  
0
2
0
0
0
1.50  
+0.10/  
–0.00  
12.00  
0.30  
1.75  
0.10  
4.00  
0.10  
2.00  
0.10  
5.50  
0.05  
2.30  
0.10  
3.20  
0.10  
1.10  
0.01  
4.00  
0.10  
0.30  
0.05  
TDFN12  
mm 3000  
Doc ID 15453 Rev 7  
45/51  
Part numbering  
STM6600 - STM6601  
9
Part numbering  
Table 8.  
STM6600 ordering information scheme  
Example:  
STM660  
0
F
Q
2
4
DM  
6
F
Device type  
STM660  
Startup process  
0: PB must be held low until the PS  
confirmation  
HOLD  
(1)  
Input and output types  
A: active high EN output, long push asserts RST, pull-up on SR  
E: active high EN output, long push asserts RST, no resistor on SR  
F: active low EN output, long push asserts RST, no resistor on SR  
G: active high EN output, long push deasserts EN, no resistor on SR  
H: active low EN output, long push deasserts EN, no resistor on SR  
(1)  
V
threshold voltage  
TH+  
A: 2.50 V  
Q: 3.30 V  
S: 3.40 V  
U: 3.50 V  
(1)  
V
voltage hysteresis  
HYST  
2: 200 mV  
5: 500 mV  
(1)  
t
blanking period  
ON_BLANK  
2: 1.4 s (min.)  
4: 5.6 s (min.)  
5: 11.2 s (min.)  
Package  
DM: TDFN12  
Temperature range  
6: –40 °C to +85 °C  
Shipping method  
®
E: ECOPACK package, tubes  
®
F: ECOPACK package, tape and reel  
1. Other options are offered. Minimum order quantities may apply. Please contact local ST sales office for availability.  
46/51  
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STM6600 - STM6601  
Part numbering  
Table 9.  
STM6601 ordering information scheme  
Example:  
STM660  
1
G
U
2
B
DM  
6
F
Device type  
STM660  
Startup process  
1: PB can be released before the PS  
confirmation  
HOLD  
(1)  
Input and output types  
A: active high EN output, long push asserts RST, pull-up on SR  
B: active low EN output, long push asserts RST, pull-up on SR  
C: active high EN output, long push deasserts EN, pull-up on SR  
D: active low EN output, long push deasserts EN, pull-up on SR  
G: active high EN output, long push deasserts EN, no resistor on SR  
(1)  
V
threshold voltage  
TH+  
M: 3.10 V  
Q: 3.30 V  
S: 3.40 V  
U: 3.50 V  
(1)  
V
voltage hysteresis  
HYST  
2: 200 mV  
(1)  
t
blanking period  
ON_BLANK  
B: 1.4 s (min.)  
D: 5.6 s (min.)  
Package  
DM: TDFN12  
Temperature range  
6: –40 °C to +85 °C  
Shipping method  
®
E: ECOPACK package, tubes  
®
F: ECOPACK package, tape and reel  
1. Other options are offered. Minimum order quantities may apply. Please contact local ST sales office for availability.  
Doc ID 15453 Rev 7  
47/51  
Product selector  
STM6600 - STM6601  
10  
Product selector  
Table 10.  
STM6600 product selector  
t
t
Internal Power-on Forced  
resistor lockout power-off  
ON_BLANK ON_BLANK  
After  
EN or  
EN  
Top  
marking  
(s)  
(s)  
Full part number  
long  
(1)  
(3)  
on SR  
voltage  
voltage  
V (V)  
TH-  
at startup  
(min.)  
at reset  
(min.)  
(2)  
push  
input  
V
(V)  
TH+  
pyww  
AS24  
STM6600AS24DM6F  
STM6600ES24DM6F  
STM6600FQ24DM6F  
EN  
RST  
RST  
RST  
EN  
pull-up  
—
3.40  
3.40  
3.30  
3.40  
3.40  
3.50  
2.50  
3.30  
3.50  
3.20  
3.20  
3.10  
3.20  
3.20  
3.30  
2.00  
3.10  
3.30  
5.6  
5.6  
5.6  
5.6  
5.6  
—
pyww  
ES24  
(4)  
(4)  
(4)  
EN  
EN  
EN  
EN  
EN  
EN  
EN  
EN  
pyww  
FQ24  
—
5.6  
pyww  
GS22  
STM6600GS22DM6F  
STM6600GS25DM6F  
STM6600GU22DM6F  
—
1.4  
pyww  
GS25  
(4)  
(4)  
EN  
—
11.2  
1.4  
—
pyww  
GU22  
EN  
—
—
pyww  
HA55  
(4)  
(4)  
STM6600HA55DM6F  
EN  
—
11.2  
11.2  
11.2  
—
pyww  
HQ25  
STM6600HQ25DM6F  
EN  
—
—
pyww  
HU25  
(4)  
STM6600HU25DM6F  
EN  
—
—
1. EN (or EN) output is push-pull. RST, INT, PBOUT and VCCLO outputs are open drain.  
2. After tSRD expires through long push, either device reset (RST) will be activated for tREC (240 ms min.) or the EN (or EN)  
pin will be deasserted. The additional Smart Reset™ delay time, tSRD, can be adjusted by the user at 10 s/µF (typ.) by  
connecting the external capacitor to the CSRD pin.  
3. Where “p” = assembly plant, “y” = assembly year (0 to 9) and “ww” = assembly work week (01 to 52).  
4. Please contact local ST sales office for availability.  
48/51  
Doc ID 15453 Rev 7  
STM6600 - STM6601  
Product selector  
Table 11.  
STM6601 product selector  
t
t
Internal Power-on  
resistor lockout power-off  
Forced  
ON_BLANK ON_BLANK  
After  
long  
push  
EN or  
EN  
Top  
marking  
(s)  
(s)  
Full part number  
(1)  
(3)  
on SR  
input  
voltage  
(V)  
voltage  
V (V)  
TH-  
at startup  
(min.)  
at reset  
(min.)  
(2)  
V
TH+  
pyww  
AQ2B  
STM6601AQ2BDM6F  
STM6601AU2DDM6F  
STM6601BM2DDM6F  
STM6601BS2BDM6F  
STM6601CM2DDM6F  
STM6601CQ2BDM6F  
STM6601DS2BDM6F  
EN  
EN  
EN  
EN  
EN  
EN  
EN  
EN  
RST  
RST  
RST  
RST  
EN  
pull-up  
pull-up  
pull-up  
pull-up  
pull-up  
pull-up  
pull-up  
—
3.30  
3.50  
3.10  
3.40  
3.10  
3.30  
3.40  
3.50  
3.10  
3.30  
2.90  
3.20  
2.90  
3.10  
3.20  
3.30  
1.4  
5.6  
5.6  
1.4  
5.6  
1.4  
1.4  
5.6  
1.4  
5.6  
5.6  
1.4  
—
pyww  
AU2D  
pyww  
BM2D  
pyww  
BS2B  
pyww  
CM2D  
pyww  
CQ2B  
EN  
—
pyww  
DS2B  
EN  
—
pyww  
GU2B  
(4)  
STM6601GU2BDM6F  
RST  
5.6  
1. EN (or EN) output is push-pull. RST, INT, PBOUT and VCCLO outputs are open drain.  
2. After tSRD expires through long push, either device reset (RST) will be activated for tREC (240 ms min.) or the EN (or EN) pin  
will be deasserted. The additional Smart Reset™ delay time, tSRD, can be adjusted by the user at 10 s/µF (typ.) by  
connecting the external capacitor to the CSRD pin.  
3. Where “p” = assembly plant, “y” = assembly year (0 to 9) and “ww” = assembly work week (01 to 52).  
4. Please contact local ST sales office for availability.  
Doc ID 15453 Rev 7  
49/51  
Revision history  
STM6600 - STM6601  
11  
Revision history  
Table 12.  
Date  
Document revision history  
Revision  
Changes  
04-Mar-2009  
05-Jun-2009  
23-Jul-2009  
22-Oct-2009  
1
2
3
4
Initial release.  
Updated text in Section 2, Section 3, Figure 11, 12; updated Figure 1, 7, 9,  
14, 18, 19, 43, Table 3, 5, 8, 9, 10; added Figure 8, 10, Table 7;  
reformatted document.  
Updated text in Features, Table 1, 8, 9, and 10; reformatted document.  
Updated Section 2, Table 5, Table 10, Figure 1, 7, 8, 9, 10, 11, 12, 14, 18,  
title of Section 10; added Section 5: Typical operating characteristics  
(Figure 23 through 40); document status upgraded to full datasheet.  
25-Jan-2010  
13-Apr-2010  
5
6
Updated Figure 6, Section 2, Table 5; textual update to “Smart Reset™”.  
Updated Figure 1, 6, 7, 8, 9, 10, 11, 12, 13, Section 2, Section 3, Table 3,  
5, 8, 9, 10.  
Reformatted Figure 1 and Figure 42, corrected typo in Section 3, added  
option A to Table 8, updated Table 10 and separated Table 10 to Table 10  
and Table 11.  
07-Jun-2010  
7
50/51  
Doc ID 15453 Rev 7  
STM6600 - STM6601  
Please Read Carefully:  
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All ST products are sold pursuant to ST’s terms and conditions of sale.  
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