STM6717LTGWB6E [STMICROELECTRONICS]
Dual/triple ultra-low voltage supervisors with push-button reset (with delay option); 双/三超低电压监控器与按钮复位（与延迟选项）
| 型号： | STM6717LTGWB6E |
| 厂家： | 
ST |
| 描述： | Dual/triple ultra-low voltage supervisors with push-button reset (with delay option) |
| 文件： | 总29页 (文件大小：253K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
STM6717/6718/6719/6720
STM6777/6778/6779/6780
Dual/triple ultra-low voltage supervisors
with push-button reset (with delay option)
Features
■ Primary supply (V
) monitor. Fixed (factory-
CC1
programmed) reset thresholds: 4.63V to 1.58V
■ Secondary supply (V ) monitor
CC2
(STM6717/18/19/20/77/78).
■ Fixed (factory-programmed) reset thresholds:
3.08V to 0.79V
■ Tertiary supply monitor (using externally
adjustable rstin):
SOT23-5 (WY)
■ 0.626V internal reference
■ RST outputs (push-pull or open drain); state
guaranteed IF V
OR V
≥ 0.8V
CC1
CC2
■ Reset delay time (t ) on power-up: 210ms,
rec
900ms (typ)
■ Manual reset input (MR)
■ Optional delayed manual reset input (MRC)
with external capacitor (STM6777/78/79/80)
SOT23-6 (WB)
■ Low supply current - 11µA (typ),
V
= V
= 3.6V
CC1
CC2
■ Operating temperature: –40°C to 85°C
(industrial grade)
Table 1.
Device summary
Monitored voltages
Reset output (RST)
Delayed
MR pin
(MRC)
Part
number
Manual reset
input (MR)
Package
Active-low
Active-low
VCC1
VCC2
RSTIN
(push-pull) (open drain)
STM6717
STM6718
STM6719
STM6720
STM6777
STM6778
STM6779
STM6780
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
WY
WY
WB
WB
WB
WB
WB
WB
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
December 2007
Rev 6
1/29
www.st.com
1
Contents
STM6717/6718/6719/6720/STM6777/6778/6779/6780
Contents
1
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.1
Pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.1.1
1.1.2
1.1.3
1.1.4
1.1.5
1.1.6
1.1.7
Active-low, push-pull reset output (RST) - STM6718/20/78/80 . . . . . . . . 7
Active-low, open drain reset output (RST) - STM6717/19/77/79 . . . . . . . 7
Push-button reset input (MR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Manual reset delay input (MRC) - STM6777/78/79/80) . . . . . . . . . . . . . . 8
Primary supply voltage monitoring input (V
) . . . . . . . . . . . . . . . . . . . 8
CC1
Secondary supply voltage monitoring input (V
) . . . . . . . . . . . . . . . . . 8
CC2
Adjustable reset comparator input (RSTIN; STM6719/20/79/80) . . . . . . 8
2
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.1
Applications information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3
4
5
6
7
8
Typical operating characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
2/29
STM6717/6718/6719/6720/STM6777/6778/6779/6780
List of tables
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Device summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Operating and AC measurement conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
DC and AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
t
minimum pulse width . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
MLMH
SOT23-5 – 5-lead small outline transistor package mechanical data. . . . . . . . . . . . . . . . . 23
SOT23-6 – 6-lead small outline transistor package mechanical data. . . . . . . . . . . . . . . . . 24
Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Marking description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3/29
List of figures
STM6717/6718/6719/6720/STM6777/6778/6779/6780
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Logic diagram (STM6717/18) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Logic diagram (STM6777/78) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Logic diagram (STM6719/20) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Logic diagram (STM6779/80) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
STM6717/18 SOT23-5 connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
STM6777/78 SOT23-6 connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
STM6719/20 SOT23-6 connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
STM6779/80 SOT23-6 connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 10. Hardware hookup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 11. STM67xx interface to processor with bi-directional reset pins . . . . . . . . . . . . . . . . . . . . . . 10
Figure 12. Ensuring RST valid to V = 0 (active-low, push-pull outputs). . . . . . . . . . . . . . . . . . . . . . 10
CC
Figure 13. Supply current vs. temperature (V
Figure 14. Supply current vs. temperature (V
Figure 15. Supply current vs. temperature (V
Figure 16. Supply current vs. temperature (V
= 5.5V; V
= 3.6V; V
= 3.0V; V
= 2.0V; V
= 3.6V) . . . . . . . . . . . . . . . . . . . . . . . 11
= 2.75V) . . . . . . . . . . . . . . . . . . . . . . 11
= 2.0V) . . . . . . . . . . . . . . . . . . . . . . . 12
= 1.0V) . . . . . . . . . . . . . . . . . . . . . . . 12
CC1
CC1
CC1
CC1
CC2
CC2
CC2
CC2
Figure 17. Normalized V reset time-out period vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
CC
Figure 18. Maximum V transient duration vs. reset threshold overdrive . . . . . . . . . . . . . . . . . . . . . 13
CC
Figure 19. Normalized V
Figure 20. Normalized V
threshold vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
threshold vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
RST1
RST2
Figure 21. Reset input threshold vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 22. -to-reset delay vs. temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 23. Reset input-to-reset output delay vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 24. MR-to-reset output delay vs. temperature (V = 3.6V) . . . . . . . . . . . . . . . . . . . . . . . . . . 16
V
CC1
CC1
Figure 25. AC testing input/output waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 26. MR timing waveform (STM6717/18/19/20) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 27. MR timing waveform (STM6777/78/79/80) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 28. SOT23-5 – 5-lead small outline transistor package mechanical drawing . . . . . . . . . . . . . . 22
Figure 29. SOT23-6 – 6-lead small outline transistor package mechanical drawing . . . . . . . . . . . . . . 23
4/29
STM6717/6718/6719/6720/STM6777/6778/6779/6780
Description
1
Description
The STM6717/18/19/20 and STM6777/78/79/80 supervisors are a family of low voltage/low
supply current processor (Micro or DSP) supervisors, designed to monitor two (or three)
system power supply voltages. They are targeted at applications such as Set-Top Boxes
(STBs), portable, battery-powered systems, networking, and communication systems.
All device options have a push-button-type manual reset input (MR). The
STM6777/78/79/80 also includes an option which enables the user to delay the start of the
Manual Reset process from 6µs (MRC pin left open) or more with external capacitor. The
delay is implemented by connecting the appropriately sized capacitor between the MRC pin
and V (typical 4s delay with a 3.3µF capacitor, see Table 7 on page 21).
SS
Two of the three supplies monitored (V
and V
) have fixed (customer-selectable,
CC2
CC1
factory-trimmed) thresholds (V
and V
). The third voltage is monitored using an
RST1
RST2
externally adjustable RSTIN threshold (0.626V internal reference).
If any of the three monitored voltages drop below its factory-trimmed or adjustable
thresholds, or if MR is asserted to logic low, a RST is asserted (driven low). Once asserted,
RST is maintained at Low for a minimum delay period (t ) after ALL supplies rise above
rec
their respective thresholds and MR returns to High. These devices are guaranteed to be in
the correct reset output logic state when V
and/or V
is greater than 0.8V.
CC1
CC2
These devices are available in a standard 5-pin or 6-pin SOT23 packages (see Table 1 on
page 1).
5/29
Description
Figure 1.
STM6717/6718/6719/6720/STM6777/6778/6779/6780
Logic diagram (STM6717/18)
Figure 2.
Logic diagram (STM6777/78)
V
V
V
V
CC2
CC1
CC2 CC1
MRC
MR
STM6717
STM6718
STM6777
STM6778
MR
RST
RST
V
V
SS
SS
AI10413
AI10415
Figure 3.
Logic diagram (STM6719/20)
Figure 4.
Logic diagram (STM6779/80)
V
V
V
CC
CC2
CC1
RSTIN
RSTIN
MR
STM6719
STM6720
STM6779
STM6780
MRC
MR
RST
RST
V
V
SS
SS
AI10414
AI10416
Table 2.
Signal names
MR
Push-button reset input
Manual reset delay input
Active-low reset output
Primary supply voltage input
Secondary supply voltage input
Adjustable reset comparator input
Ground
MRC
RST
VCC1
VCC2
RSTIN
VSS
6/29
STM6717/6718/6719/6720/STM6777/6778/6779/6780
Description
Figure 5.
STM6717/18 SOT23-5 connections Figure 6.
STM6777/78 SOT23-6 connections
V
V
V
CC1
5
4
6
5
4
1
2
3
CC1
CC2
1
2
3
RST
RST
V
V
SS
SS
MRC
V
MR
MR
CC2
AI10417
AI10418
Figure 7.
STM6719/20 SOT23-6 connections Figure 8.
STM6779/80 SOT23-6 connections
V
V
CC1
6
5
4
6
5
4
1
2
3
CC1
1
2
3
RST
RST
V
V
SS
RSTIN
SS
RSTIN
V
MRC
MR
MR
CC2
AI10419
AI10420
1.1
Pin descriptions
1.1.1
Active-low, push-pull reset output (RST) - STM6718/20/78/80
The RST pin is driven low and stays low whenever V
or V
or RSTIN falls below its
CC2
CC1
factory-trimmed or adjustable reset threshold or when MR goes to logic low. It remains low
for t after ALL supply voltages being monitored rise above their reset thresholds and MR
rec
goes from low to high. (Push-pull outputs are referenced to V
.)
CC1
1.1.2
1.1.3
Active-low, open drain reset output (RST) - STM6717/19/77/79
The RST pin is driven low and stays low whenever V
or V
or RSTIN falls below its
CC2
CC1
factory-trimmed or adjustable reset threshold or when MR goes to logic low. It remains low
for t after ALL supply voltages being monitored rise above their reset thresholds and MR
rec
goes from low to high. Connect an external pull-up resistor to V
should be sufficient for most applications.
. A 10kΩ pull-up resistor
CC1
Push-button reset input (MR)
When MR goes low the RST output is driven low. RST remains low as long as MR is low and
for t after MR returns to high. This active-low input has an internal 50kΩ pull-up resistor to
rec
7/29
Description
STM6717/6718/6719/6720/STM6777/6778/6779/6780
V
. It can be driven from a TTL or CMOS logic line, or with open drain/collector outputs,
CC1
or connected to V through a switch. If unused, leave this pin open or connect it to V
.
SS
CC1
Connect a normally open momentary switch from MR to V ; external debounce circuitry is
SS
not required. (If MR is driven from long cables or if the device is used in noisy environments,
connecting a 0.1µF capacitor from MR to V provides additional noise immunity.
SS
1.1.4
Manual reset delay input (MRC) - STM6777/78/79/80)
This pin is either left open or connected to V via a capacitor. By selecting the appropriate
SS
capacitor, the manual reset process, initiated by pressing the push-button Manual Reset
Input, can be delayed by any value from 6µs or more (see Table 7 on page 21).
1.1.5
1.1.6
1.1.7
Primary supply voltage monitoring input (V
)
CC1
It also is the input for the primary reset threshold monitor. Available fixed (customer-
selectable, factory-programmed) reset thresholds include 4.63V to 1.58V.
Secondary supply voltage monitoring input (V
)
CC2
This function is available on the STM6717/18/19/20/77/78. Fixed (customer-selectable,
factory-programmed) reset thresholds include 3.08V to 0.79V.
Adjustable reset comparator input (RSTIN; STM6719/20/79/80)
This is a high impedance input. RST is driven low when the voltage at the RSTIN pin falls
below 0.626V (internal reference voltage at this comparator). The monitored voltage reset
threshold is set with an external resistor-divider network.
Table 3.
Pin functions
Pin
Name
Function
STM6717 STM6719 STM6777 STM6779
STM6718 STM6720 STM6778 STM6780
1
3
–
5
4
–
2
1
3
–
6
4
5
2
1
3
5
6
4
–
2
1
3
4
6
–
5
2
RST Active-low reset output
MR Push-button reset input
MRC Manual reset delay input
VCC1 Primary supply voltage input
VCC2 Secondary supply voltage input
RSTIN Adjustable reset comparator input
VSS Ground
8/29
STM6717/6718/6719/6720/STM6777/6778/6779/6780
Description
Figure 9.
Block diagram
V
CC1
COMPARE
COMPARE
COMPARE
V
V
RST1
RST2
(1)
V
CC2
(2)
RSTIN
t
rec
Generator
RST
V
= 0.626
REF/2
V
CC1
MR
Logic
(3)
MRC
AI10421
1. VCC2 input is available on STM6717/18/19/20/77/78.
2. RSTIN available only on STM6719/20/79/80.
3. MRC available only on STM6777/78/79/80.
Figure 10. Hardware hookup
From DC/DC Converter
(1)
V
V
CC2
CC1
V
V
CC1
R1 + R2
R2
V
=
(626.5mV)
CC3
(
)
0.1μF
STM67xx
CC2
V
CC3
0.1μF
R1
(2)
RSTIN
MR
RST
RST (To Processor Reset)
R2
(3)
MRC
Push-button
Switch
V
SS
C
AI10422
1. VCC2 is available only on STM6717/18/19/20/77/78.
2. RSTIN available only on STM6719/20/79/80.
3. MRC available only on STM6777/78/79/80.
9/29
Operation
STM6717/6718/6719/6720/STM6777/6778/6779/6780
2
Operation
2.1
Applications information
1. Interfacing to processors with bi-directional reset pins
Most processors with bi-directional reset pins can interface directly to the open drain
RST outputs (STM6717/19/77/79). Systems simultaneously requiring a push-pull RST
output and a bi-directional reset interface can be in logic contention. To prevent this
contention, connect a 4.7kΩ resistor between RST and the processor’s reset I/O as
shown in Figure 11.
2. Ensuring a Valid RST Output Down to V = 0V
CC
The STM67xx Supervisors are guaranteed to be in the correct RST output logic state
when V
and/or V
is greater than 0.8V. In applications which require valid reset
CC1
CC2
levels down to V = 0, a pull-down resistor to active-low outputs (push-pull only, see
CC
Figure 12) will ensure that the reset line is valid while the reset output can no longer
sink or source current. This scheme does NOT work with the open drain outputs of the
STM6717/19/77/79.
The resistor value used is not critical, but it must be large enough not to load the reset
output when V is above the reset threshold. For most applications, 100kΩ is
CC
adequate.
Figure 11. STM67xx interface to processor with bi-directional reset pins
V
V
CC2
CC1
STM67xx
Processor
To other
system
components
V
V
CC1
CC2
RST
RESET
4.7kΩ
V
V
SS
SS
AI10425
Figure 12. Ensuring RST valid to V = 0 (active-low, push-pull outputs)
CC
STM67xx
V
CC1
V
CC1
RST
V
SS
R1
AI10426
10/29
STM6717/6718/6719/6720/STM6777/6778/6779/6780
Typical operating characteristics
3
Typical operating characteristics
Note:
Typical values are at T = 25°C unless otherwise noted.
A
Figure 13. Supply current vs. temperature (V
= 5.5V; V
= 3.6V)
CC2
CC1
18
16
14
12
I
TOTAL
10
I
CC1
8
6
4
2
0
I
CC2
–40
–20
0
20
40
60
80
Temperature (°C)
AI11843
Figure 14. Supply current vs. temperature (V
= 3.6V; V
= 2.75V)
CC2
CC1
18
16
14
12
10
8
I
TOTAL
I
CC1
6
4
I
CC2
2
0
–40
–20
0
20
40
60
80
Temperature (°C)
AI11844
11/29
Typical operating characteristics
STM6717/6718/6719/6720/STM6777/6778/6779/6780
Figure 15. Supply current vs. temperature (V
= 3.0V; V
= 2.0V)
CC2
CC1
18
16
14
12
10
8
I
TOTAL
6
I
CC1
4
2
I
CC2
20
0
–40
–20
0
40
60
80
Temperature (°C)
AI11845
Figure 16. Supply current vs. temperature (V
= 2.0V; V
= 1.0V)
CC2
CC1
18
16
14
12
10
8
I
TOTAL
6
I
CC1
4
2
0
I
CC2
20
–40
–20
0
40
60
80
Temperature (°C)
AI11846
12/29
STM6717/6718/6719/6720/STM6777/6778/6779/6780
Typical operating characteristics
Figure 17. Normalized V reset time-out period vs. temperature
CC
1.07
1.05
1.03
1.01
0.99
0.97
–40
–20
0
20
40
60
80
Temperature (°C)
AI11847
Figure 18. Maximum V transient duration vs. reset threshold overdrive
CC
1000
100
10
1
1
10
100
1000
Reset Threshold Overdrive (mV)
AI11848
13/29
Typical operating characteristics
STM6717/6718/6719/6720/STM6777/6778/6779/6780
threshold vs. temperature
Figure 19. Normalized V
RST1
1.004
1.002
1.000
0.998
0.996
–40
–20
0
20
40
60
80
Temperature (°C)
AI11849
Figure 20. Normalized V
threshold vs. temperature
RST2
1.004
1.002
1.000
0.998
0.996
–40
–20
0
20
40
60
80
Temperature (°C)
AI11850
14/29
STM6717/6718/6719/6720/STM6777/6778/6779/6780
Typical operating characteristics
Figure 21. Reset input threshold vs. temperature
630
629
628
627
626
625
624
–40
–20
0
20
40
60
80
Temperature (°C)
AI11851
Figure 22. V
-to-reset delay vs. temperature
CC1
48
44
40
36
32
28
–40
–20
0
20
40
60
80
Temperature (°C)
AI11852
15/29
Typical operating characteristics
STM6717/6718/6719/6720/STM6777/6778/6779/6780
Figure 23. Reset input-to-reset output delay vs. temperature
29.0
28.5
28.0
27.5
27.0
26.5
26.0
25.5
25.0
–40
–20
0
20
40
60
80
Temperature (°C)
AI11853
Figure 24. MR-to-reset output delay vs. temperature (V
= 3.6V)
CC1
500
480
460
440
420
400
–40
–20
0
20
40
60
80
Temperature (°C)
AI11854
16/29
STM6717/6718/6719/6720/STM6777/6778/6779/6780
Maximum rating
4
Maximum rating
Stressing the device above the rating listed in the Absolute Maximum Ratings” table may
cause permanent damage to the device. These are stress ratings only and operation of the
device at these or any other conditions above those indicated in the Operating sections of
this specification is not implied. Exposure to Absolute Maximum Rating conditions for
extended periods may affect device reliability. Refer also to the STMicroelectronics SURE
Program and other relevant quality documents.
Table 4.
Symbol
TSTG
Absolute maximum ratings
Parameter
Value
Unit
Storage temperature (VCC Off)
–55 to 150
°C
°C
V
(1)
TSLD
Lead solder temperature for 10 seconds
260
–0.3 to VCC1 + 0.3
–0.3 to VCC2 + 0.3
–0.3 to 7.0
20
VIO
Input or output voltage
V
VCC1, VCC2 Supply voltage
V
IIO
Input or output current (all pins)
mA
mW
mW
SOT23-5
SOT23-6
654
PD
Power dissipation
675
Note:
Reflow at peak temperature of 255°C to 260°C for < 30 seconds (total thermal budget not to
exceed 180°C for between 90 to 150 seconds).
17/29
DC and AC parameters
STM6717/6718/6719/6720/STM6777/6778/6779/6780
5
DC and AC parameters
This section summarizes the operating measurement conditions, and the DC and AC
characteristics of the device. The parameters in the DC and AC characteristics Tables that
follow, are derived from tests performed under the Measurement Conditions summarized in
Table 5: Operating and AC measurement conditions. Designers should check that the
operating conditions in their circuit match the operating conditions when relying on the
quoted parameters.
Table 5.
Operating and AC measurement conditions
Parameter
STM67xx
Unit
V
CC supply voltage
0.8 to 5.5
–40 to 85
≤ 5
V
°C
ns
V
Ambient operating temperature (TA)
Input rise and fall times
Input pulse voltages
0.2 to 0.8VCC
0.3 to 0.7VCC
Input and output timing ref. voltages
V
Figure 25. AC testing input/output waveforms
0.8V
CC
0.7V
CC
0.3V
CC
0.2V
CC
AI02568
Figure 26. MR timing waveform (STM6717/18/19/20)
tMLMH
MR
tMLRL
RST
trec
AI10423a
Figure 27. MR timing waveform (STM6777/78/79/80)
tMLMH(1)
MR
tMLRL
RST
trec
AI10424c
1. By connecting a certain capacitor between the MRC pin and VSS, the RST can be delayed from 6µs or
more (tMLMH, see Table 7 on page 21).
18/29
STM6717/6718/6719/6720/STM6777/6778/6779/6780
DC and AC parameters
Table 6.
Sym
DC and AC characteristics
Alter-
native
Description
Test condition(1)
Min
Typ
Max
Unit
VCC
ICC1
Operating voltage
VCC1 supply current
0.8
5.5
35
23
9
V
V
CC1 < 5.5V, all I/O pins open
12
8
µA
µA
µA
µA
µA
VCC1 < 3.6V, all I/O pins open
CC2 < 3.6V, all I/O pins open
V
3
ICC2
VCC2 supply current
Input leakage current
VCC2 < 2.75V, all I/O pins open
0V = VIN = VCC
2.5
7
(2)
ILI
–1
+1
VCC1 > VRST1, VCC2 > VRST2
RST not asserted
;
Open drain RST output
leakage current
ILO
0.5
0.3
0.3
0.3
0.3
0.4
µA
V
VCC1 or VCC2 ≥ 0.8V,
ISINK = 1µA, RST asserted
V
CC1 or VCC2 ≥ 1.0V,
ISINK = 50µA, RST asserted
CC1 or VCC2 ≥ 1.2V,
ISINK = 100µA, RST asserted
CC1 or VCC2 ≥ 2.7V,
ISINK = 1.2mA, RST asserted
CC1 or VCC2 ≥ 4.5V,
V
V
Output low voltage (RST;
push-pull or open drain)
VOL
V
V
V
V
V
V
V
V
ISINK = 3.2mA, RST asserted
VCC1 ≥ 1.8V, ISOURCE = 200µA,
0.8VCC1
0.8VCC1
0.8VCC1
RST not asserted
Output high voltage (RST;
push-pull only)
VCC1 ≥ 2.7V, ISOURCE = 500µA,
VOH
RST not asserted
VCC1 ≥ 4.5V, ISOURCE = 800µA,
RST not asserted
Rise time measured from 10% to
Push-pull RST rise time
(STM6718/20/78/80)
(3)
90% of VCC
;
tR
5
25
ns
CL = 5pF, VCC = 3.3V
Reset thresholds
L (falling)
M (falling)
T (falling)
S (falling)
R (falling)
Z (falling)
Y (falling)
W (falling)
V (falling)
4.500 4.625 4.750
4.250 4.375 4.500
3.000 3.075 3.150
2.850 2.925 3.000
2.550 2.625 2.700
2.250 2.313 2.375
2.125 2.188 2.250
1.620 1.665 1.710
1.530 1.575 1.620
V
V
V
V
V
V
V
V
V
(4)
VRST
VTH1
VCC1 reset threshold
19/29
DC and AC parameters
STM6717/6718/6719/6720/STM6777/6778/6779/6780
Table 6.
Sym
DC and AC characteristics (continued)
Alter-
Description
Test condition(1)
Min
Typ
Max
Unit
native
T (falling)
S (falling)
3.000 3.075 3.150
2.850 2.925 3.000
2.550 2.625 2.700
2.250 2.313 2.375
2.125 2.188 2.250
1.620 1.665 1.710
1.530 1.575 1.620
1.350 1.388 1.425
1.275 1.313 1.350
1.080 1.110 1.140
1.020 1.050 1.080
0.895 0.925 0.955
0.845 0.875 0.905
0.810 0.833 0.855
0.765 0.788 0.810
0.5
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
%
R (falling)
Z (falling)
Y (falling)
W (falling)
V (falling)
(4)
VRST2
VTH2
VCC2 reset threshold
I (falling)
H (falling)
G (falling)
F (falling)
K (falling)
J (falling)
E (falling)
D (falling)
VHYST
Reset threshold hysteresis
VCC to RST delay
Referenced to VRST typical
V
CC1 = (VRST1 + 100mV) to
20
20
µs
µs
(VRST – 100mV)
tRD
V
CC2 = (VRST2 + 75mV) to
(VRST2 – 75mV)
blank
G
140
600
210
900
280
trec
tRP
RST pulse width
ms
1200
Adjustable reset comparator input (STM6719/20/79/80)
VRSTIN
IRSTIN
RSTIN input threshold
RSTIN input current
RSTIN hysteresis
611
–25
626.5 642
mV
nA
+25
3
mV
RSTIN to RST
output delay
tRSTIND
VRSTIN to (VRSTIN – 30mV)
22
µs
20/29
STM6717/6718/6719/6720/STM6777/6778/6779/6780
DC and AC parameters
Table 6.
Sym
DC and AC characteristics (continued)
Alter-
native
Description
Test condition(1)
Min
Typ
Max
Unit
Manual (push-button) reset input
0.3VC
VIL
V
V
C1
MR input voltage
VIH
0.7VCC1
1
MR minimum pulse width
(STM6717/18/19/20)
µs
tMLMH
tMR
MRC connected via
MR minimum pulse width
(STM6777/78/79/80)
6
µs
ns
ns
kΩ
(5)
capacitor to VSS
tMLRL
tMRD
MR to RST output delay
200
100
50
MR glitch immunity
(STM6717/18/19/20)
MR pull-up resistance
25
80
1. Valid for ambient operating temperature: TA = –40 to 85°C; VCC1 = 0.8 to 5.5V and VCC2 = 0.8 to 3.6V (except where noted).
2. Input leakage for the MRC pin is not tested.
3. Guaranteed by design.
4. The leakage current measured on the RST pin is tested with the reset de-asserted (output high impedance).
5. Selecting the appropriate external capacitor (preferably less than 100pF) allows systems designers to vary the minimum
delay from 6µs (MRC pin left open) or more (see Table 7).
Table 7.
VCC1
t
minimum pulse width
MLMH
Capacitor value(1)
100pF
0.1µF
2.2µF
2.6s
3.3µF
4.0s
4.7µF
6.8µF
1.6V
2.0V
3.0V
4.0V
5.0V
120µs
122µs
125µs
128µs
130µs
120ms
122ms
125ms
129ms
130ms
5.6s
5.8s
5.9s
6.0s
6.1s
8.2s
8.3s
8.5s
8.7s
8.8s
2.7s
2.7s
2.8s
2.8s
4.0s
4.1s
4.2s
4.3s
1. At 25°C (typical)
21/29
Package mechanical data
STM6717/6718/6719/6720/STM6777/6778/6779/6780
6
Package mechanical data
®
In order to meet environmental requirements, ST offers these devices in ECOPACK
packages. These packages have a lead-free second level interconnect. The category of
second Level Interconnect is marked on the package and on the inner box label, in
compliance with JEDEC Standard JESD97.
The maximum ratings related to soldering conditions are also marked on the inner box label.
ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com.
Figure 28. SOT23-5 – 5-lead small outline transistor package mechanical drawing
E
A1
1
e
e1
D
5x b
5x
M
0.20
C A B
A2
A
C 0.10
A
C
Datum A
0.20
C
θ
B
L
E1
SOT23-5b
Note:
Drawing is not to scale.
22/29
STM6717/6718/6719/6720/STM6777/6778/6779/6780
Package mechanical data
Table 8.
Symb
SOT23-5 – 5-lead small outline transistor package mechanical data
mm
Min
inches
Min
Typ
Max
Typ
Max
A
A1
A2
b
–
–
–
1.45
0.15
1.30
0.50
0.22
–
–
–
0.057
0.006
0.051
0.020
0.009
–
–
–
–
1.15
–
0.90
0.30
0.08
–
0.045
–
0.035
0.012
C
–
–
0.003
D
2.90
2.80
1.60
0.95
1.90
0.45
4°
0.114
0.110
0.063
0.037
0.075
0.018
4°
–
E
–
–
–
–
E1
e
–
–
–
–
–
–
–
–
e1
L
–
–
–
–
0.30
0°
0.60
8°
0.012
0°
0.024
8°
Q
N
5
5
Note:
Dimensions per JEDEC SOT/SOP Product Outline MO-178C, variation AA
Figure 29. SOT23-6 – 6-lead small outline transistor package mechanical drawing
E
A1
1
e
e1
D
6x b
0.10
6x
M
C A B
C 0.10
A2
A
C
A
Datum A
0.20
C
θ
B
L
E1
SOT23-6
Note:
Drawing is not to scale.
23/29
Package mechanical data
STM6717/6718/6719/6720/STM6777/6778/6779/6780
Table 9.
Symb
SOT23-6 – 6-lead small outline transistor package mechanical data
mm
Min
inches
Min
Typ
Max
Typ
Max
A
A1
A2
b
–
–
–
1.45
0.15
1.30
0.50
0.22
–
–
–
0.057
0.006
0.051
0.020
0.009
–
–
–
–
1.15
–
0.90
0.30
0.08
–
0.045
–
0.035
0.012
C
–
–
0.003
D
2.90
2.80
1.60
0.95
1.90
0.45
4°
0.114
0.110
0.063
0.037
0.075
0.018
4°
–
E
–
–
–
–
E1
e
–
–
–
–
–
–
–
–
e1
L
–
–
–
–
0.30
0°
0.60
8°
0.012
0°
0.024
8°
Q
N
6
6
Note:
Dimensions per JEDEC SOT/SOP product outline MO-178C variation AA
24/29
STM6717/6718/6719/6720/STM6777/6778/6779/6780
Part numbering
7
Part numbering
Table 10. Ordering information scheme
Example:
STM67xx
LT
WY
6
E
Device type
STM67xx
Reset thresholds (VRST1 and VRST2) for VCC1 and VCC2
STM6717/18/19/20/77/78 (VRST1 and VRST2
)
STM6779/80 (VRST1 only)
Suffix
LT
MS
VRST1
4.625
4.375
4.375
3.075
3.075
3.075
3.075
3.075
3.075
2.925
2.925
2.925
2.925
2.925
2.925
2.188
2.188
2.188
2.188
2.188
1.575
1.575
1.575
1.575
VRST2
3.075
2.925
2.625
2.313
1.665
1.388
1.110
0.925
0.833
2.188
1.575
1.313
1.050
0.875
0.788
1.575
1.313
1.050
0.875
0.788
1.313
1.050
0.875
0.788
Suffix VRST1
L–(1)
T–(1)
S–(1)
Y–(1)
V–(1)
R–
4.625
3.075
2.925
2.188
1.575
2.625
2.313
MR
TZ(1)
TW(1)
TI
TG(1)
TK
Z–
TE
SY(1)
SV(1)
SH(2)
SF(1)
SJ(3)
SD(3)
YV
YH
YF
YJ
YD
VH
VF
VJ
VD
Reset pulse width
blank: trec = 140ms to 280ms
G: trec = 600ms to 1200ms
Package
WY = SOT23-5
WB = SOT23-6
Temperature range
6 = –40 to 85°C
Shipping method
E = ECOPACK® package, tubes
F = ECOPACK® package, tape & reel
1. These are standard versions and are typically held in stock. A non-standard version may require a higher minimum
volumes, and/or longer delivery times. For other options, or for more information on any aspect of this device, please
contact the ST Sales Office nearest you
2. Available in STM6719 version only.
3. Available in STM6717 version only.
25/29
Part numbering
STM6717/6718/6719/6720/STM6777/6778/6779/6780
Table 11. Marking description
Part number
VRST1 threshold (V) VRST1 threshold (V)
Topside marking
Bottomside marking
STM6717SD
STM6717SJ
STM6717SF
STM6717TG
STM6717TGG
STM6717TW
STM6717SV
STM6717SY
STM6717TZ
STM6718SF
STM6718TG
STM6718TW
STM6718SV
STM6718SY
STM6718TZ
STM6719SF
STM6719TG
STM6719SH
STM6719TW
STM6719SV
STM6719SY
STM6719TZ
STM6720SF
STM6720TG
STM6720TW
STM6720SV
STM6720SY
STM6720TZ
STM6777SF
STM6777TG
STM6777TW
STM6777SV
STM6777SY
STM6777TZ
STM6778SF
2.925
2.925
2.925
3.075
3.075
3.075
2.925
2.925
3.075
2.925
3.075
3.075
2.925
2.925
3.075
2.925
3.075
2.925
3.075
2.925
2.925
3.075
2.925
3.075
3.075
2.925
2.925
3.075
2.925
3.075
3.075
2.925
2.925
3.075
2.925
0.788
0.875
1.050
1.110
1.110
1.665
1.575
2.188
2.313
1.050
1.110
1.665
1.575
2.188
2.313
1.050
1.110
1.313
1.665
1.575
2.188
2.313
1.050
1.110
1.665
1.575
2.188
2.313
1.050
1.110
1.665
1.575
2.188
2.313
1.050
7SD1
7SJ1
7SF1
7TG1
7TG9
7TW1
7SV1
7SY1
7TZ1
7SF2
7TG2
7TW2
7SV2
7SY2
7TZ2
7SF3
7TG3
7SH3
7TW3
7SV3
7SY3
7TZ3
7SF4
7TG4
7TW4
7SV4
7SY4
7TZ4
7SF5
7TG5
7TW5
7SV5
7SY5
7TZ5
7SF6
PYWW
PYWW
PYWW
PYWW
PYWW
PYWW
PYWW
PYWW
PYWW
PYWW
PYWW
PYWW
PYWW
PYWW
PYWW
PYWW
PYWW
PYWW
PYWW
PYWW
PYWW
PYWW
PYWW
PYWW
PYWW
PYWW
PYWW
PYWW
PYWW
PYWW
PYWW
PYWW
PYWW
PYWW
PYWW
26/29
STM6717/6718/6719/6720/STM6777/6778/6779/6780
Table 11. Marking description (continued)
Part numbering
Part number
VRST1 threshold (V) VRST1 threshold (V)
Topside marking
Bottomside marking
STM6778TG
STM6778TW
STM6778SV
STM6778SY
STM6778TZ
STM6779L
STM6779T
STM6779S
STM6779Y
STM6779V
STM6780L
STM6780T
STM6780S
STM6780Y
STM6780V
3.075
3.075
2.925
2.925
3.075
4.625
3.075
2.925
2.188
1.575
4.625
3.075
2.925
2.188
1.575
1.110
7TG6
7TW6
7SV6
7SY6
7TZ6
7Lx7
7Tx7
7Sx7
7Yx7
7Vx7
7Lx8
7Tx8
7Sx8
7Yx8
7Vx8
PYWW
PYWW
PYWW
PYWW
PYWW
PYWW
PYWW
PYWW
PYWW
PYWW
PYWW
PYWW
PYWW
PYWW
PYWW
1.665
1.575
2.188
2.313
-
-
-
-
-
-
-
-
-
-
Note:
For Topside marking, “7” is the family number, followed by the V
threshold, V
RST1 RST2
threshold and device number (1,9 = STM6717, 2 = 6718, 3 = 6719, 4 = 6720, 5 = 6777, 6 =
6778, 7 = 6779, 8 = 6780).
For Bottomside marking, “P” = assembly site, “Y” = 1-digit year, and “WW” = 2-digit work
week.
27/29
Revision history
STM6717/6718/6719/6720/STM6777/6778/6779/6780
8
Revision history
Table 12. Document revision history
Date
Version
Revision details
18-Oct-2004
25-Oct-2004
14-Jan-2005
09-Feb-2005
1.0
1.1
1.2
1.3
First draft
Descriptive text, sales types (Table 10)
Update characteristics, pin functions (Table 2)
Update characteristics (Figure 9; Table 3)
Update characteristics and mechanical dimensions; add table
(Figure 9, 10, 27, 28, 29; Table 4, 6, 10, 8, 9)
08-Apr-2005
28-Jul-2005
1.4
1.5
Update characteristics, reset delay (Figure 10, 27; Table 4, 6, 7, 10)
Add operating characteristics; update timings, document status, Lead-
free text (Figure Figure 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24,
26, 27; Table 10)
13-Sep-2005
2.0
07-Oct-2005
07-Feb-2007
12-Jun-2007
05-Dec-2007
3.0
4.0
5.0
6.0
Marked STM6779/6780 as availability request parts (Table 1, 10)
Updated STM6779/6780 availability (cover page, Table 1, 10)
Updated Table 10, added Table 11: Marking description.
Updated cover page, Table 6, 10, and 11.
28/29
STM6717/6718/6719/6720/STM6777/6778/6779/6780
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