STM704MM6F [STMICROELECTRONICS]
IC,POWER SUPPLY SUPERVISOR,SOP,8PIN,PLASTIC;
| 型号： | STM704MM6F |
| 厂家： | 
ST |
| 描述： | IC,POWER SUPPLY SUPERVISOR,SOP,8PIN,PLASTIC 光电二极管 |
| 文件： | 总33页 (文件大小：214K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
STM69XA, STM70X, STM80X, STM81X
5V Supervisor with Battery Switchover
FEATURES SUMMARY
■
5V OPERATING VOLTAGE
Figure 1. Packages
■
NVRAM SUPERVISOR FOR EXTERNAL
LPSRAM
■
CHIP-ENABLE GATING (STM818 only) FOR
EXTERNAL LPSRAM (7ns max PROP
DELAY)
8
■
■
■
■
■
RST AND RST OUTPUTS
1
200ms (TYP) t
rec
SO8 (M)
WATCHDOG TIMER - 1.6sec (TYP)
AUTOMATIC BATTERY SWITCHOVER
LOW BATTERY SUPPLY CURRENT - 0.4µA
(TYP)
■
■
■
POWER-FAIL COMPARATOR (PFI/PFO)
LOW SUPPLY CURRENT - 40µA (TYP)
GUARANTEED RST (RST) ASSERTION
TSSOP8 3x3 (DS)*
DOWN TO V = 1.0V
CC
■
OPERATING TEMPERATURE:
–40°C to 85°C (Industrial Grade)
Table 1. Device Options
Active-
Low
Active-
High
Manual
Reset
Input
Battery
Switch-
over
Power-fail
Compar-
ator
Chip-
Enable
Gating
Battery
Freshness
Seal
Watchdog
Input
(1)
(1)
RST
RST
STM690A
STM692A
STM703
■
■
■
■
■
■
■
■
■
■
■
■
■
■
■
■
■
■
■
■
■
■
■
■
■
STM704
STM802L/M
STM805L
■
■
■
■
■
STM817L/M
STM818L/M
STM819L/M
■
■
■
■
■
■
■
■
■
Note: 1. All RST and RST outputs are push-pull.
* Contact local ST sales office for availability.
July 2004
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STM690A/692A/703/704/802/805/817/818/819
TABLE OF CONTENTS
FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Figure 1. Packages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Table 1. Device Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
SUMMARY DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Figure 2. Logic Diagram (STM690A/692A/802/805/817) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Figure 3. Logic Diagram (STM703/704/819). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Figure 4. Logic Diagram (STM818). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Table 2. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Figure 5. STM690A/692A/802/805/817 Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 6. STM703/704/819 Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 7. STM818 Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Table 3. Pin Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 8. Block Diagram (STM690A/692A/802/805/817) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 9. Block Diagram (STM703/704/819) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 10.Block Diagram (STM818) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 11.Hardware Hookup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Reset Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Push-button Reset Input (STM703/704/819) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Watchdog Input (NOT available on STM703/704/819) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Back-up Battery Switchover. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 4. I/O Status in Battery Back-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Chip-Enable Gating (STM818 only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Chip Enable Input (STM818 only). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Chip Enable Output (STM818 only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 12.Chip-Enable Gating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 13.Chip Enable Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Power-fail Input/Output (NOT available on STM818) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Applications Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 14.Power-fail Comparator Waveform (STM817/818/819) . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 15.Power-fail Comparator Waveform (STM690A/692A/703/704/802/805) . . . . . . . . . . . . . 13
Using a SuperCap™ as a Backup Power Source. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 16.Using a SuperCap™ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Negative-Going V Transients . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
CC
Battery Freshness Seal (STM817/818/819) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 17.Freshness Seal Enable Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
TYPICAL OPERATING CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 18.V
-to-V
On-Resistance vs. Temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
OUT
BAT
Figure 19.Supply Current vs. Temperature (no load) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 20.V Threshold vs. Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
PFI
2/33
STM690A/692A/703/704/802/805/817/818/819
Figure 21.Reset Comparator Propagation Delay vs. Temperature . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 22.Power-up t vs. Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
rec
Figure 23.Normalized Reset Threshold vs. Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 24.Watchdog Time-out Period vs. Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 25.E to E
On-Resistance vs. Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
CON
Figure 26.PFI to PFO Propagation Delay vs. Temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 27.RST Output Voltage vs. Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 28.RST Output Voltage vs. Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 29.RST Response Time (Assertion). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 30.RST Response Time (Assertion). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 31.Power-fail Comparator Response Time (Assertion) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 32.Power-fail Comparator Response Time (De-Assertion) . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 33.V to Reset Propagation Delay vs. Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
CC
Figure 34.Maximum Transient Duration vs. Reset Threshold Overdrive. . . . . . . . . . . . . . . . . . . . . 22
Figure 35.E to E
Propagation Delay vs. Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
CON
MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 5. Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
DC and AC PARAMETERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 6. Operating and AC Measurement Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 36.E to ECON Propagation Delay Test Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 37.AC Testing Input/Output Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 38.MR Timing Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 39.Watchdog Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 7. DC and AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 40.SO8 – 8-lead Plastic Small Outline, 150 mils body width, Package Mech. Drawing. . . . 28
Table 8. SO8 – 8-lead Plastic Small Outline, 150 mils body width, Package Mechanical Data . . 28
Figure 41.TSSOP8 – 8-lead, Thin Shrink Small Outline, 3x3mm body size, Outline . . . . . . . . . . . 29
Table 9. TSSOP8 – 8-lead, Thin Shrink Small Outline, 3x3mm body size, Mechanical Data . . . . 29
PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 10. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 11. Marking Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 12. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
3/33
STM690A/692A/703/704/802/805/817/818/819
SUMMARY DESCRIPTION
The STMXXX SUPERVISORs are self-contained
devices which provide microprocessor superviso-
ry functions with the ability to non-volatize and
write-protect external LPSRAM. A precision volt-
These devices also offer a watchdog timer (except
for STM703/704/819) as well as a power-fail com-
parator (except for STM818) to provide the system
with an early warning of impending power failure.
age reference and comparator monitors the V
CC
These devices are available in a standard 8-pin
SOIC package or a space-saving 8-pin TSSOP
package.
input for an out-of-tolerance condition. When an
invalid V condition occurs, the reset output
CC
(RST) is forced low (or high in the case of RST).
Figure 2. Logic Diagram (STM690A/692A/802/
805/817)
Figure 4. Logic Diagram (STM818)
V
V
BAT
CC
V
V
BAT
CC
V
OUT
WDI
E
V
OUT
RST
STM818
WDI
PFI
STM690A/
692A/802/
805/817
(1)
RST(RST)
E
CON
PFO
V
SS
AI07896
V
SS
AI07894
Note: 1. For STM805, reset output is active-high.
Table 2. Signal Names
MR
WDI
RST
RST
Push-button Reset Input
Watchdog Input
Figure 3. Logic Diagram (STM703/704/819)
V
V
BAT
Active-Low Reset Output
Active-High Reset Output
Chip Enable Input
CC
(1)
E
V
OUT
MR
PFI
STM703
/704/819
(1)
Conditioned Chip Enable Output
E
CON
RST
PFO
V
Supply Voltage Output
Supply Voltage
OUT
V
CC
V
Back-up Supply Voltage
Power-fail Input
Power-fail Output
Ground
BAT
V
SS
AI07895
PFI
PFO
V
SS
Note: 1. STM818
4/33
STM690A/692A/703/704/802/805/817/818/819
Figure 5. STM690A/692A/802/805/817
Connections
Figure 6. STM703/704/819 Connections
SO8/TSSOP8
SO8/TSSOP8
V
V
BAT
OUT
1
2
3
4
8
7
6
5
V
V
BAT
V
OUT
1
2
3
4
8
7
6
5
RST
MR
CC
(1)
V
RST(RST)
WDI
V
CC
SS
V
SS
PFI
PFO
PFI
PFO
AI07890
AI07889
Note: 1. For STM805, reset output is active-high.
Figure 7. STM818 Connections
SO8/TSSOP8
V
V
BAT
OUT
1
2
3
4
8
7
6
5
V
CC
RST
WDI
E
V
SS
E
CON
AI07892
Table 3. Pin Description
Pin
Name
Function
STM690A
STM692A
STM802
STM817
STM703
STM704
STM819
STM818
STM805
Push-button Reset Input.
A logic low on /MR asserts the reset output. Reset
remains asserted as long as MR is low and for t
rec
–
–
6
6
–
–
MR
after MR returns high. This active-low input has an
internal pull-up. It can be driven from a TTL or
CMOS logic line, or shorted to ground with a switch.
Leave open if unused.
Watchdog Input.
If WDI remains high or low for 1.6sec, the internal
watchdog timer runs out and reset is triggered. The
6
6
WDI internal watchdog timer clears while reset is
asserted or when WDI sees a rising or falling edge.
The watchdog function can be disabled by allowing
the WDI pin to float.
Active-Low Reset Output.
Pulses low for t when triggered, and stays low
rec
whenever V is below the reset threshold or when
CC
7
–
7
–
7
–
–
7
RST
RST
MR is a logic low. It remains low for t after either
rec
V
CC
rises above the reset threshold, the watchdog
triggers a reset, or MR goes from low to high.
Active-High Reset Output.
Inverse of RST.
Supply Output for External LPSRAM. When V
CC
is above the switchover voltage (V ), V
is
SO
OUT
V
connected to V through a P-channel MOSFET
CC
1
2
1
2
1
2
1
2
OUT
switch. When V falls below V , V
connects
CC
SO BAT
to V . Connect to V if no battery is used.
OUT CC
V
Supply Voltage.
CC
5/33
STM690A/692A/703/704/802/805/817/818/819
Pin
Name
Function
STM690A
STM692A
STM802
STM817
STM703
STM704
STM819
STM818
STM805
Backup-Battery Input.
When V falls below V , V
switches from
SO OUT
CC
V
to V . When V rises above V
+
may
V
8
4
8
–
8
–
8
–
CC
BAT
CC
SO
BAT
hysteresis, V
exceed V . Connect to V if no battery is used.
reconnects to V . V
OUT
CC BAT
CC
CC
Chip Enable Input.
The input to the chip-enable gating circuit. Connect
to ground if unused.
E
Conditioned Chip Enable Output.
E
CON
goes low only when E is low and reset is not
asserted. If E
is low when reset is asserted,
CON
E
5
–
–
4
–
4
–
4
CON
E
CON
will remain low for 15µs or until E goes high,
whichever occurs first. In the disabled mode, E
is pulled up to V
CON
.
OUT
PFI Power-fail Input.
When PFI is less than V
or when V falls below
CC
PFI
PFI
2.4V (or V ), PFO goes low; otherwise, PFO
SO
remains high. Connect to ground if unused.
PFO Power-fail Output.
When PFI is less than V , or V falls below 2.4V
PFI
CC
–
3
5
3
5
3
5
3
PFO
(or V ), PFO goes low; otherwise, PFO remains
SO
high. Leave open if unused.
V
SS
Ground.
Figure 8. Block Diagram (STM690A/692A/802/805/817)
VCC
VOUT
VBAT
COMPARE
COMPARE
VSO
VRST
trec
Generator
RST(RST)(1)
WATCHDOG
TIMER
WDI
PFI
VPFI
COMPARE
PFO
AI07897
Note: 1. For STM805, reset output is active-high.
6/33
STM690A/692A/703/704/802/805/817/818/819
Figure 9. Block Diagram (STM703/704/819)
VCC
VOUT
VBAT
COMPARE
VSO
COMPARE
VRST
trec
Generator
RST
MR
PFI
VPFI
COMPARE
PFO
AI07898
Figure 10. Block Diagram (STM818)
VCC
VOUT
VBAT
COMPARE
VSO
COMPARE
VRST
trec
Generator
WATCHDOG
TIMER
RST
WDI
ECON OUTPUT
CONTROL
E
ECON
AI07899a
7/33
STM690A/692A/703/704/802/805/817/818/819
Figure 11. Hardware Hookup
Regulator
Unregulated
Voltage
VCC
VCC
LPSRAM
VIN
VCC
VCC
VOUT
0.1µF
E
STMXXX
E
0.1µF
WDI(1)
E(2)
From Microprocessor
(2)
ECON
R1
R2
PFI(3)
MR(4)
VBAT
PFO(3)
RST
To Microprocessor NMI
To Microprocessor Reset
Push-Button
AI07893
Note: 1. For STM690A/692A/802/805/817/818.
2. For STM818 only.
3. Not available on STM818.
4. For STM703/704/819.
8/33
STM690A/692A/703/704/802/805/817/818/819
OPERATION
Reset Output
The STMXXX SUPERVISOR asserts a reset sig-
the device is used in a noisy environment, connect
a 0.1µF capacitor from MR to GND to provide ad-
ditional noise immunity. MR may float, or be tied to
nal to the MCU whenever V goes below the re-
CC
set threshold (V
), a watchdog time-out occurs,
RST
or when the Push-button Reset Input (MR) is taken
V
when not used.
CC
low. RST is guaranteed to be a logic low (logic
Watchdog Input (NOT available on STM703/
704/819)
The watchdog timer can be used to detect an out-
of-control MCU. If the MCU does not toggle the
high for STM805) for 0V < V
< V
if V
is
BAT
CC
RST
greater than 1V. Without a back-up battery, RST is
guaranteed valid down to V =1V.
CC
During power-up, once V
exceeds the reset
CC
Watchdog Input (WDI) within t
(1.6sec typ), the
WD
threshold an internal timer keeps RST low for the
reset is asserted. The internal watchdog timer is
cleared by either:
1. a reset pulse, or
2. by toggling WDI (high-to-low or low-to-high),
which can detect pulses as short as 50ns. If
WDI is tied high or low, a reset pulse is
reset time-out period, t . After this interval RST
rec
returns high.
If V drops below the reset threshold, RST goes
CC
low. Each time RST is asserted, it stays low for at
least the reset time-out period (t ). Any time V
rec
CC
goes below the reset threshold the internal timer
triggered every 1.8sec (t
+ t ).
WD
rec
clears. The reset timer starts when V
above the reset threshold.
returns
CC
The timer remains cleared and does not count for
as long as reset is asserted. As soon as reset is re-
leased, the timer starts counting (see Figure
39., page 24).
Push-button Reset Input (STM703/704/819)
A logic low on MR asserts reset. Reset remains
asserted while MR is low, and for t (see Figure
rec
Note: The watchdog function may be disabled by
floating WDI or tri-stating the driver connected to
WDI. When tri-stated or disconnected, the maxi-
mum allowable leakage current is 10uA and the
maximum allowable load capacitance is 200pF.
Note: Input frequency greater than 20ns (50MHz)
will be filtered.
38., page 24) after it returns high. The MR input
has an internal 40kΩ pull-up resistor, allowing it to
be left open if not used. This input can be driven
with TTL/CMOS-logic levels or with open-drain/
collector outputs. Connect a normally open mo-
mentary switch from MR to GND to create a man-
ual reset function; external debounce circuitry is
not required. If MR is driven from long cables or
9/33
STM690A/692A/703/704/802/805/817/818/819
Back-up Battery Switchover
Chip-Enable Gating (STM818 only)
In the event of a power failure, it may be necessary
to preserve the contents of external SRAM
Internal gating of the chip enable (E) signal pre-
vents erroneous data from corrupting the external
CMOS RAM in the event of an undervoltage con-
dition. The STM818 uses a series transmission
through V
. With a backup battery installed with
, the devices automatically switch the
OUT
voltage V
BAT
SRAM to the back-up supply when V falls.
Note: If back-up battery is not used, connect both
gate from E to E
(see Figure 12., page 11).
CC
CON
During normal operation (reset not asserted), the
E transmission gate is enabled and passes all E
transitions. When reset is asserted, this path be-
comes disabled, preventing erroneous data from
corrupting the CMOS RAM. The short E propaga-
V
and V
to V
.
BAT
OUT
CC
This family of Supervisors does not always con-
nect V to V when V is greater than V
.
CC
BAT
OUT
BAT
V
connects to V
CC
(through a 100Ω switch)
BAT
OUT
RST
tion delay from E to E
enables the STM818 to
CON
when V is below V
and V
. This is done to
BAT
be used with most µPs. If E is low when reset as-
serts, E remains low for typically 15µs to per-
allow the back-up battery (e.g., a 3.6V lithium cell)
to have a higher voltage than V
CON
.
CC
mit the current WRITE cycle to complete. Connect
Assuming V
> 2.0V, switchover at V ensures
SO
BAT
E to V if unused.
SS
that battery back-up mode is entered before V
gets too close to the 2.0V minimum required to re-
liably retain data in most external SRAMs. When
OUT
Chip Enable Input (STM818 only)
The chip-enable transmission gate is disabled and
E is high impedance (disabled mode) while reset
is asserted. During a power-down sequence when
V
recovers, hysteresis is used to avoid oscilla-
CC
tion around the V
point. V
is connected to
SO
OUT
V
passes the reset threshold, the chip-enable
CC
V
through a 3Ω PMOS power switch.
CC
transmission gate disables and E immediately be-
comes high impedance if the voltage at E is high.
If E is low when reset asserts, the chip-enable
transmission gate will disable 15µs after reset as-
serts (see Figure 13., page 11). This permits the
current WRITE cycle to complete during power-
down.
Note: The back-up battery may be removed while
is valid, assuming V is adequately decou-
pled (0.1µF typ), without danger of triggering a re-
set.
V
CC
BAT
Table 4. I/O Status in Battery Back-up
Any time a reset is generated, the chip-enable
transmission gate remains disabled and E remains
high impedance (regardless of E activity) for the
reset time-out period. When the chip enable trans-
mission gate is enabled, the impedance of E ap-
pears as a 40Ω resistor in series with the load at
Pin
Status
V
OUT
Connected to V
through internal switch
BAT
V
Disconnected from V
Disabled
CC
PFI
PFO
E
OUT
E
. The propagation delay through the chip-en-
CON
Logic low
able transmission gate depends on V , the
CC
source impedance of the drive connected to E,
High impedance
Logic high
and the loading on E
(see “Typical Operating
CON
E
CON
Characteristics”). The chip enable propagation de-
lay is production tested from the 50% point on E to
WDI
Watchdog timer is disabled
the 50% point on E
using a 50Ω driver and a
CON
50pF load capacitance (see Figure 37., page 24).
For minimum propagation delay, minimize the ca-
WDO Logic low
MR
RST
RST
Disabled
pacitive load at E
pedance driver.
and use a low-output im-
CON
Logic low
Chip Enable Output (STM818 only)
When the chip-enable transmission gate is en-
Logic high
Connected to V
V
BAT
OUT
abled, the impedance of E
is equivalent to a
CON
40Ω resistor in series with the source driving E. In
the disabled mode, the transmission gate is off
and an active pull-up connects E
to V
(see
CON
OUT
Figure 12., page 11). This pull-up turns off when
the transmission gate is enabled.
10/33
STM690A/692A/703/704/802/805/817/818/819
Figure 12. Chip-Enable Gating
VCC
trec
Generator
RST
COMPARE
VRST
VOUT
ECON OUTPUT
CONTROL
E
ECON
AI08802
Figure 13. Chip Enable Waveform
VCC
VRST
VBAT
ECON
½ trec
½ trec
trec
15µs
trec
RST
E
AI08803b
11/33
STM690A/692A/703/704/802/805/817/818/819
Power-fail Input/Output (NOT available on STM818)
The Power-fail Input (PFI) is compared to an inter-
nal reference voltage (independent from the V
comparator). If PFI is less than the power-fail
V
drops below 2.4V (or V ). When power re-
CC SO
turns, PFO is forced high (STM817/819 only), irre-
spective of V for the WRITE protect time (t ).
RST
PFI
rec
threshold (V ), the Power-Fail Output (PFO) will
At the end of this time, the power-fail comparator
is enabled and PFO follows PFI. If the comparator
PFI
go low. This function is intended for use as an un-
dervoltage detector to signal a failing power sup-
ply. Typically PFI is connected through an external
voltage divider (see Figure 11., page 8) to either
the unregulated DC input (if it is available) or the
is unused, PFI should be connected to V
and
SS
PFO left unconnected. PFO may be connected to
MR on the STM703/704/818 so that a low voltage
on PFI will generate a reset output.
regulated output of the V regulator. The voltage
divider can be set up such that the voltage at PFI
CC
Applications Information
These Supervisor circuits are not short-circuit pro-
falls below V
several milliseconds before the
PFI
tected. Shorting V
to ground - excluding pow-
OUT
regulated V input to the STMXXX or the micro-
CC
er-up transients such as charging a decoupling
capacitor - destroys the device. Decouple both
processor drops below the minimum operating
voltage.
During battery back-up, the power-fail comparator
turns off and PFO goes (or remains) low (see Fig-
ure 14 and Figure 15., page 13). This occurs after
V
and V
pins to ground by placing 0.1µF ca-
BAT
CC
pacitors as close to the device as possible.
Figure 14. Power-fail Comparator Waveform (STM817/818/819)
VCC
VRST
VSO (or 2.4V)
trec
PFO
(STM817/819)
PFO follows PFI
PFO follows PFI
RST to ECON Delay (STM818)
RST
ECON (STM818)
AI08804a
12/33
STM690A/692A/703/704/802/805/817/818/819
Figure 15. Power-fail Comparator Waveform (STM690A/692A/703/704/802/805)
VCC
VRST
2.4V (or VSO
)
trec
PFO
PFO follows PFI
PFO follows PFI
RST
AI08832a
Using a SuperCap™ as a Backup Power
Source
Figure 16. Using a SuperCap™
5V
SuperCaps™ are capacitors with extremely high
capacitance values (e.g., order of 0.47F) for their
size. Figure 16 shows how to use a SuperCap as
a back-up power source. The SuperCap may be
connected through a diode to the 5V input. Since
VCC
VOUT
To external SRAM
STMXXX
VBAT
V
can exceed V while V is above the reset
BAT
CC CC
threshold, there are no special precautions when
using these supervisors with a SuperCap.
RST
To µP
GND
AI08805
Negative-Going V Transients
CC
The STMXXXs are relatively immune to negative-
going V transients (glitches). This graph shows
CC
typical transient duration versus reset comparator
overdrive (for which the STMXXX will NOT gener-
ate a reset pulse). The graph was generated using
a negative pulse applied to V , starting at V
+
CC
RST
0.3V and ending below the reset threshold by the
13/33
STM690A/692A/703/704/802/805/817/818/819
Battery Freshness Seal (STM817/818/819)
Figure 17. Freshness Seal Enable Waveform
The battery freshness seal disconnects the back-
VRST
up battery from internal circuitry and V
until it is
OUT
needed. This allows an OEM to ensure that the
back-up battery connected to V will be fresh
when the final product is put to use. To enable the
freshness seal:
VCC
BAT
trec
RST
1. Connect a battery to V
2. Ground PFO;
;
BAT
ECON out state latched
at 1/2 trec
,
Freshness
3. Bring V above the reset threshold and hold
(Externally held at 0V)
Seal enabled
CC
ECON
it there until reset is deasserted following the
reset timeout period; and
(STM818)
PFO out state latched
at 1/2 trec
,
Freshness
Seal Enabled
(Externally held at 0V)
4. Bring V down again (Figure 17).
CC
PFO
(STM817/819)
Use the same procedure for the STM818, but
AI08806
ground E
instead of PFO. Once the battery
CON
freshness seal is enabled (disconnecting the
back-up battery from internal circuitry and any-
thing connected to V
), it remains enabled until
OUT
V
is brought above V
.
CC
RST
14/33
STM690A/692A/703/704/802/805/817/818/819
TYPICAL OPERATING CHARACTERISTICS
Note: Typical values are at T = 25°C
A
Figure 18. V
-to-V
BAT
On-Resistance vs. Temperature
OUT
220
200
180
160
140
120
100
V
= 0V
CC
V
= 2V
BAT
V
= 3V
BAT
V
= 3.3V
BAT
V
= 5V
BAT
–60
–40
–20
0
20
40
60
80
100
120
140
TEMPERATURE [°C]
AI09140
Figure 19. Supply Current vs. Temperature (no load)
30
25
20
15
10
5
2.5V
3.3V
3.6V
5.0V
5.5V
0
–50 –40 –30 –20 –10
0
10
20
30
40
50
60
70
80
90
100
TEMPERATURE [°C]
AI09141
15/33
STM690A/692A/703/704/802/805/817/818/819
Figure 20. V
Threshold vs. Temperature
PFI
1.255
1.250
1.245
1.240
1.235
1.230
V
= 5V
CC
V
= 3.3V
CC
V
= 2.5V
CC
V
= 3.0V
BAT
1.225
–50
–30
–10
10
30
50
70
90
110
130
TEMPERATURE [°C]
AI09142
Figure 21. Reset Comparator Propagation Delay vs. Temperature
24
22
V
= 3.0V
BAT
20
18
16
14
12
10
100mV OVERDRIVE
–60
–40
–20
0
20
40
60
80
100
TEMPERATURE [°C]
AI09143
Figure 22. Power-up t
vs. Temperature
rec
215
210
205
200
195
–50
–30
–10
10
30
50
70
90
110
130
TEMPERATURE [°C]
AI09144
16/33
STM690A/692A/703/704/802/805/817/818/819
Figure 23. Normalized Reset Threshold vs. Temperature
1.002
1.000
0.998
0.996
0.994
V
= 3.0V
BAT
–60
–40
–20
0
20
40
60
80
100
120
140
TEMPERATURE [°C]
AI09145
Figure 24. Watchdog Time-out Period vs. Temperature
1.74
1.72
1.70
1.68
1.66
1.64
1.62
1.60
1.58
1.56
–50
–30
–10
10
30
50
70
90
110
130
TEMPERATURE [°C]
AI09146
Figure 25. E to E
On-Resistance vs. Temperature
CON
90
80
70
60
50
40
V
= 3V
CC
30
–60
–40
–20
0
20
40
60
80
100
120
140
TEMPERATURE [°C]
AI09147
17/33
STM690A/692A/703/704/802/805/817/818/819
Figure 26. PFI to PFO Propagation Delay vs. Temperature
9
8
7
6
5
4
3
2
1
0
–60
–40
–20
0
20
40
60
80
100
120
140
TEMPERATURE [°C]
AI09148
Figure 27. RST Output Voltage vs. Supply Voltage
6
5
4
V
CC
3
2
1
0
V
RST
500 ms/div
AI09149
18/33
STM690A/692A/703/704/802/805/817/818/819
Figure 28. RST Output Voltage vs. Supply Voltage
6
5
V
CC
4
3
2
1
0
V
RST
500 ms/div
AI09150
Figure 29. RST Response Time (Assertion)
6
5
4
3
2
1
0
V
CC
V
RST
2 µs/div
AI09151
19/33
STM690A/692A/703/704/802/805/817/818/819
Figure 30. RST Response Time (Assertion)
6
V
CC
5
4
3
2
1
0
V
RST
2µs/div
AI09152
Figure 31. Power-fail Comparator Response Time (Assertion)
6
1.45
1.40
1.35
1.30
1.25
1.20
1.15
5
4
PFO
3
PFI
2
1
0
2µs/div
AI09153
20/33
STM690A/692A/703/704/802/805/817/818/819
Figure 32. Power-fail Comparator Response Time (De-Assertion)
6
5
4
3
2
1
0
1.45
1.40
1.35
1.30
1.25
1.20
PFO
PFI
1.15
2 µs/div
AI09154
Figure 33. V to Reset Propagation Delay vs. Temperature
CC
60
50
40
30
20
10
0
10V/ms
1V/ms
0.25V/ms
–60
–40
–20
0
20
40
60
80
100
TEMPERATURE [°C]
AI09155
21/33
STM690A/692A/703/704/802/805/817/818/819
Figure 34. Maximum Transient Duration vs. Reset Threshold Overdrive
250
200
150
100
50
0
1
10
100
1000
10000
RESET COMPARATOR OVERDRIVE, V
– V [mV]
CC
RST
AI09156
Figure 35. E to E
Propagation Delay vs. Temperature
CON
3.5
E Rising
3.0
2.5
2.0
1.5
1.0
0.5
E Falling
0
140
–60
–40
–20
0
20
40
60
80
100
120
TEMPERATURE [°C]
AI09157
22/33
STM690A/692A/703/704/802/805/817/818/819
MAXIMUM RATING
Stressing the device above the rating listed in the
Absolute Maximum Ratings” table may cause per-
manent damage to the device. These are stress
ratings only and operation of the device at these or
any other conditions above those indicated in the
Operating sections of this specification is not im-
plied. Exposure to Absolute Maximum Rating con-
ditions for extended periods may affect device
reliability. Refer also to the STMicroelectronics
SURE Program and other relevant quality docu-
ments.
Table 5. Absolute Maximum Ratings
Symbol
Parameter
Value
Unit
T
Storage Temperature (V Off)
–55 to 150
°C
STG
CC
Lead Solder Temperature for 10 seconds
Input or Output Voltage
Supply Voltage
(1)
260
°C
V
T
SLD
V
–0.3 to V +0.3
IO
CC
V
/V
–0.3 to 6.0
20
V
CC BAT
I
O
Output Current
mA
mW
P
Power Dissipation
320
D
Note: 1. Reflow at peak temperature of 255°C to 260°C for < 30 seconds (total thermal budget not to exceed 180°C for between 90 to 150
seconds).
DC AND AC PARAMETERS
This section summarizes the operating measure-
ment conditions, and the DC and AC characteris-
tics of the device. The parameters in the DC and
AC characteristics Tables that follow, are derived
from tests performed under the Measurement
Conditions summarized in Table 6, Operating and
AC Measurement Conditions. Designers should
check that the operating conditions in their circuit
match the operating conditions when relying on
the quoted parameters.
Table 6. Operating and AC Measurement Conditions
Parameter
STM690A/692A/703/704/802/
Unit
805/817/818/819
V
/V
Supply Voltage
1.0 to 5.5
–40 to 85
≤ 5
V
°C
ns
V
CC BAT
Ambient Operating Temperature (T )
A
Input Rise and Fall Times
0.2 to 0.8V
Input Pulse Voltages
CC
0.3 to 0.7V
Input and Output Timing Ref. Voltages
V
CC
23/33
STM690A/692A/703/704/802/805/817/818/819
Figure 36. E to ECON Propagation Delay Test Circuit
VCC
VCC
VBAT
3.6V
STMXXX
50Ω Equivalent
Source Impedance
E
ECON
50Ω
50Ω Cable
(1)
50pF CL
50Ω
GND
AI08854
Note: 1. C includes load capacitance and scope probe capacitance.
L
Figure 37. AC Testing Input/Output Waveforms
0.8V
CC
0.7V
0.3V
CC
CC
0.2V
CC
AI02568
Figure 38. MR Timing Waveform
MR
tMLRL
RST (1)
trec
tMLMH
AI07837a
Note: 1. RST for STM805.
Figure 39. Watchdog Timing
VCC
trec
RST
tWD
WDI
AI07891
24/33
STM690A/692A/703/704/802/805/817/818/819
Table 7. DC and AC Characteristics
Alter-
(1)
Sym
Description
Min
Typ
Max
Unit
Test Condition
native
V
,
CC
(2)
(3)
T = –40 to +85°C
Operating Voltage
5.5
60
35
V
A
1.2
V
BAT
V
V
Supply Current
Excluding I
Excluding I
(V < 5.5V)
CC
25
25
µA
µA
CC
OUT
I
CC
(V
BAT
= 2.3V,
Supply Current in
OUT
CC
V
= 2.0V, MR = V
)
Battery Back-up Mode
CC
CC
V
Supply Current in
BAT
(4)
Excluding I
(V
= 3.6V)
0.4
1.0
µA
V
I
OUT
BAT
BAT
Battery Back-up Mode
V
0.03
–
V
CC
–
CC
(5)
I
= 5mA
OUT1
0.015
V
0.3
–
V
0.15
–
CC
CC
V
V
V
Voltage (Active)
Voltage (Battery
I
= 75mA
V
OUT1
OUT
OUT1
V
CC
–
V
CC
–
(5)
V
I
= 250µA, V > 2.5V
CC
OUT1
0.0015 0.0006
V
BAT
–
V
BAT
–
I
= 250µA, V
= 1mA, V
= 2.3V
BAT
V
OUT2
0.1
0.034
OUT
V
OUT2
Back-up)
V
BAT
–
I
= 2.3V
BAT
V
OUT2
0.14
V
V
to V
On-resistance
3
4
Ω
Ω
CC
OUT
to V
On-resistance
100
125
2
BAT
OUT
4.5V < V < 5.5V
Input Leakage Current (MR)
Input Leakage Current (PFI)
75
300
+25
160
µA
nA
µA
µA
V
CC
0V = V = V
–25
IN
CC
I
LI
WDI = V , time average
120
–15
CC
Input Leakage Current
(6)
(WDI)
WDI = GND, time average
–20
2.0
V
V
4.5V < V < 5.5V
Input High Voltage (MR)
Input High Voltage (WDI)
Input Low Voltage (MR)
Input Low Voltage (WDI)
IH
CC
V
(max) < V < 5.5V
0.7V
CC
V
IH
RST
CC
V
4.5V < V < 5.5V
0.8
V
IL
IL
CC
V
V
(max) < V < 5.5V
0.3V
CC
V
RST
CC
V
= V
(max), I
3.2mA
=
Output Low Voltage (PFO,
RST, RST)
CC
RST
SINK
0.3
V
V
V
V
V
OL
V
CC
= V (max),
RST
Output Low Voltage (E
)
0.2V
CON
CC
I
= 1.6mA, E = 0V
OUT
I
= 50µA; V = 1.0V;
CC
= 0V; T = 0°C to 85°C
A
SINK
0.3
0.3
V
BAT
V
OL
Output Low Voltage (RST)
I
= 100µA; V = 1.2V;
CC
SINK
V
= 0V
BAT
25/33
STM690A/692A/703/704/802/805/817/818/819
Alter-
native
(1)
Sym
Description
Min
2.4
Typ
Max
Unit
V
Test Condition
I
= 1mA,
(max)
Output High Voltage (RST,
RST)
SOURCE
V
CC
= V
RST
V
= V
(max),
CC
RST
V
OH
Output High Voltage (E
)
0.8V
CC
V
CON
I
= 1.6mA, E = V
CC
OUT
I
V
= 75µA,
SOURCE
0.8V
Output High Voltage (PFO)
Output High Voltage
V
CC
= V
(max)
CC
RST
I
V
= 4µA; V = 1.1V;
CC
SOURCE
0.8
0.9
V
= 0V; T = 0°C to 85°C
A
BAT
V
OH
I
= 4µA; V = 1.2V;
CC
SOURCE
V
V
BAT
= 0V
V
Battery Back-up (E
,
CON
OH
V
OHB
I
= 100µA,
0.8V
BAT
V
SOURCE
RST, RST)
Power-fail Comparator (NOT available on STM818)
All other
versions
1.20
1.25
1.250
2
1.30
V
V
PFI Falling
(V = 5V)
CC
V
PFI
PFI Input Threshold
STM802
1.225
1.275
PFI to PFO Propagation
Delay
t
µs
PFD
PFO Output Short to
GND Current
I
V
CC
= 5V, V = 0V
PFO
0.1
0.75
2.0
mA
SC
Battery Switchover
V
RST
V
RST
V
RST
V
RST
> V
< V
> V
< V
V
V
V
BAT
BAT
BAT
BAT
BAT
Power-down
Power-up
Battery Back-up
V
RST
(7,8)
Switchover Voltage
V
SO
V
BAT
V
(V < V
& V < V
)
CC
BAT
CC
RST
V
V
RST
Hysteresis
40
mV
Reset Thresholds
STM690A/703, STM8XXL
STM692A/704, STM8XXM
4.50
4.25
4.65
4.40
25
4.75
4.50
V
V
Reset Threshold
V
RST
Reset Threshold Hysteresis
to RST Delay (from
mV
V
CC
STM817/818/819
100
200
µs
V
, V falling at 10V/ms)
RST CC
t
RST Pulse Width
140
280
ms
rec
26/33
STM690A/692A/703/704/802/805/817/818/819
Alter-
native
(1)
Sym
Description
Min
Typ
Max
Unit
Test Condition
Push-button Reset Input (STM703/704/819)
STM703/704
STM819
150
1
ns
µs
ns
ns
ns
kΩ
t
t
MR
MR Pulse Width
MLMH
STM703/704
STM819
250
t
t
MRD
MR to RST Output Delay
MLRL
120
100
63
MR Glitch Immunity
MR Pull-up Resistor
STM819
MR = 0V; V = 5V
45
85
CC
Watchdog Timer (NOT available on STM703/704/819)
t
V
(max) < V < 5.5V
Watchdog Timeout Period
WDI Pulse Width
1.12
50
1.60
2.24
s
WD
RST
CC
V
RST
(max) < V < 5.5V
ns
CC
Chip-Enable Gating (STM818 only)
E-to-E Resistance
V
= V
(max)
40
2
150
7
Ω
CON
CC
RST
E-to-E
Propagation Delay
4.5V < V < 5.5V
ns
µs
CON
CC
Reset-to-E
High Delay
(Power-down)
15
CON
V
= 5V, Disable Mode,
CC
E
CON
Short Circuit Current
0.1
0.75
2.0
mA
E = Logic high, E
= 0V
CON
Note: 1. Valid for Ambient Operating Temperature: T = –40 to 85°C; V = 4.75V to 5.5V for “L” versions; V = 4.5V to 5.5V for “M” ver-
A
CC
CC
sions; and V
= 2.8V (except where noted).
BAT
2. V supply current, logic input leakage, Watchdog functionality, Push-button Reset functionality, PFI functionality, state of RST and
CC
RST tested at V
= 3.6V, and V = 5.5V. The state of RST or RST and PFO is tested at V = V (min). Either V or V
BAT
CC CC CC CC BAT
can go to 0V if the other is greater than 2.0V.
3. V (min) = 1.0V for T = 0°C to +85°C.
CC
A
4. Tested at V
= 3.6V, V = 3.5V and 0V.
BAT
CC
5. Guaranteed by design.
6. WDI input is designed to be driven by a three-state output device. To float WDI, the “high impedance mode” of the output device
must have a maximum leakage current of 10µA and a maximum output capacitance of 200pF. The output device must also be able
to source and sink at least 200µA when active.
7. When V
8. When V
> V > V
, V
remains connected to V until V drops below V
.
BAT
RST
CC
RST
OUT
CC
CC
RST
> V > V
, V
remains connected to V until V drops below the battery voltage (V
) – 75mV.
BAT
CC
BAT OUT
CC
CC
27/33
STM690A/692A/703/704/802/805/817/818/819
PACKAGE MECHANICAL
Figure 40. SO8 – 8-lead Plastic Small Outline, 150 mils body width, Package Mech. Drawing
h x 45˚
A2
A
C
B
ddd
e
D
8
1
E
H
A1
α
L
SO-A
Note: Drawing is not to scale.
Table 8. SO8 – 8-lead Plastic Small Outline, 150 mils body width, Package Mechanical Data
mm
Min
1.35
0.10
0.33
0.19
4.80
–
inches
Min
Symb
Typ
–
Max
1.75
0.25
0.51
0.25
5.00
0.10
4.00
–
Typ
Max
0.069
0.010
0.020
0.010
0.197
0.004
0.157
–
A
A1
B
–
0.053
0.004
0.013
0.007
0.189
–
–
–
–
–
C
–
–
D
–
–
ddd
E
–
–
–
3.80
–
–
0.150
–
e
1.27
–
0.050
H
5.80
0.25
0.40
0°
6.20
0.50
0.90
8°
–
–
–
–
0.228
0.010
0.016
0°
0.244
0.020
0.035
8°
h
–
L
–
α
–
N
8
8
28/33
STM690A/692A/703/704/802/805/817/818/819
Figure 41. TSSOP8 – 8-lead, Thin Shrink Small Outline, 3x3mm body size, Outline
D
8
1
5
4
c
E1
E
α
A1
L
A
A2
L1
CP
b
e
TSSOP8BM
Note: Drawing is not to scale.
Table 9. TSSOP8 – 8-lead, Thin Shrink Small Outline, 3x3mm body size, Mechanical Data
mm
Min
–
inches
Min
–
Symb
Typ
–
Max
1.10
0.15
0.95
0.40
0.23
0.10
3.10
–
Typ
–
Max
0.043
0.006
0.037
0.016
0.009
0.004
0.122
–
A
A1
A2
b
–
0.05
0.75
0.25
0.13
–
–
0.002
0.030
0.010
0.005
–
0.85
–
0.034
–
c
–
–
CP
D
–
–
3.00
0.65
4.90
3.00
0.55
0.95
–
2.90
–
0.118
0.026
0.193
0.118
0.022
0.037
–
0.114
–
e
E
4.65
2.90
0.40
–
5.15
3.10
0.70
–
0.183
0.114
0.016
–
0.203
0.122
0.030
–
E1
L
L1
α
0°
6°
0°
6°
N
8
8
29/33
STM690A/692A/703/704/802/805/817/818/819
PART NUMBERING
Table 10. Ordering Information Scheme
Example:
STMXXX
L
M
6
E
Device Type
STMXXX
Reset Threshold Voltage
L = STM690A/703, STM8XXL = V
= 4.50V to 4.75V
RST
M = STM692A/704, STM8XXM = V
= 4.25V to 4.50V
RST
Package
M = SO8
(1)
DS = TSSOP8
Temperature Range
6 = –40 to 85°C
Shipping Method
®
E = Tubes (Pb-Free - ECO PACK )
®
F = Tape & Reel (Pb-Free - ECO PACK )
Note: 1. Contact local ST sales office for availability.
For other options, or for more information on any aspect of this device, please contact the ST Sales Office
nearest you.
30/33
STM690A/692A/703/704/802/805/817/818/819
Table 11. Marking Description
Part Number
STM690A
STM692A
STM703
Reset Threshold
Package
SO8
Topside Marking
4.65V
4.65V
4.65V
4.40V
4.65V
4.40V
4.65V
690A
692A
703
SO8
SO8
STM704
SO8
704
STM802L
STM802M
STM805L
SO8
802L
802M
805L
SO8
SO8
SO8
STM817L
STM817M
STM818L
STM818M
STM819L
STM819M
4.65V
4.40V
4.65V
4.40V
4.65V
4.40V
817L
817M
818L
818M
819L
819M
TSSOP8
SO8
TSSOP8
SO8
TSSOP8
SO8
TSSOP8
SO8
TSSOP8
SO8
TSSOP8
31/33
STM690A/692A/703/704/802/805/817/818/819
REVISION HISTORY
Table 12. Document Revision History
Date
Version
1.0
Revision Details
October 2003
31-Oct-03
First Issue
1.1
Update DC Characteristics (Table 7)
Reformatted; updated characteristics (Figure 1, 3, 4, 7, 8, 9, 10, 11, 12, 13, 14, 15,
17; Table 3, 4, 7, 9, 11)
22-Dec-03
2.0
Add Typical Characteristics (Figure 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29,
30, 31, 32, 33, 34, 35)
16-Jan-04
08-Apr-04
25-May-04
2.1
2.2
3.0
Update characteristics (Figure 13, 21, 26, 28, 29, 30, 33, 34; Table 1,7)
Remove references to ‘Open Drain’ (Figure 2, 5, 8; Table 2); update characteristics
(Table 3, 7)
Update package availability, pin description; promote document (Figure 1, 14, 15;
Table 3. 7, 10)
05-Jul-04
4.0
32/33
STM690A/692A/703/704/802/805/817/818/819
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
The ST logo is a registered trademark of STMicroelectronics.
All other names are the property of their respective owners.
© 2004 STMicroelectronics - All rights reserved
STMicroelectronics GROUP OF COMPANIES
Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany -
Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Singapore -
Spain - Sweden - Switzerland - United Kingdom - United States
www.st.com
33/33
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