STM708T/S/R [STMICROELECTRONICS]
3V监控器;
| 型号： | STM708T/S/R |
| 厂家： | 
ST |
| 描述： | 3V监控器 监控 |
| 文件： | 总26页 (文件大小：470K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
STM706T/S/R, STM706P, STM708T/S/R
3V Supervisor
FEATURES SUMMARY
■
PRECISION V MONITOR
Figure 1. Packages
CC
–
STM706/708
T: 3.00V ≤ V
S: 2.88V ≤ V
≤ 3.15V
≤ 3.00V
RST
RST
8
R; STM706P: 2.59V ≤ V
≤ 2.70V
RST
1
■
■
■
■
■
■
■
RST AND RST OUTPUTS
200ms (TYP) t
rec
SO8 (M)
WATCHDOG TIMER - 1.6sec (TYP)
MANUAL RESET INPUT (MR)
POWER-FAIL COMPARATOR (PFI/PFO)
LOW SUPPLY CURRENT - 40µA (TYP)
GUARANTEED RST (RST) ASSERTION
DOWN TO V = 1.0V
CC
TSSOP8 3x3 (DS)
■
OPERATING TEMPERATURE:
–40°C to 85°C (Industrial Grade)
Table 1. Device Options
Active-Low
Active-High
Watchdog
Watchdog
Output
Manual
Reset Input
Power-fail
Comparator
(1)
(1)
Input
RST
RST
STM706T/S/R
■
■
■
■
■
■
■
■
■
■
■
(2)
■
■
■
STM706P
STM708T/S/R
Note: 1. Push-Pull Output
2. The STM706P is identical to the STM706R, except its reset output is active-high.
February 2005
1/26
STM706T/S/R; STM706P; STM708T/S/R
TABLE OF CONTENTS
FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Figure 1. Packages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Table 1. Device Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
SUMMARY DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Figure 2. Logic Diagram (STM706T/S/R and STM706P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Figure 3. Logic Diagram (STM708T/S/R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Table 2. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Figure 4. STM706T/S/R and STM706P SO8 Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 5. STM706T/S/R and STM706P TSSOP8 Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 6. STM708T/S/R SO8 Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 7. STM708T/S/R TSSOP8 Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Table 3. Pin Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 8. Block Diagram (STM706T/S/R and STM706P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 9. Block Diagram (STM708T/S/R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 10.Hardware Hookup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Reset Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Push-button Reset Input. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Watchdog Input (STM706T/S/R and STM706P). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Watchdog Output (STM706T/S/R and STM706P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Power-fail Input/Output. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Ensuring a Valid Reset Output Down to V = 0V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
CC
Figure 11.Reset Output Valid to Ground Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Interfacing to Microprocessors with Bi-directional Reset Pins . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 12.Interfacing to Microprocessors with Bi-directional Reset I/O. . . . . . . . . . . . . . . . . . . . . . 10
TYPICAL OPERATING CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 13.Supply Current vs. Temperature (no load) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 14.V
Threshold vs. Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
PFI
Figure 15.Reset Comparator Propagation Delay vs. Temperature . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 16.Power-up t vs. Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
rec
Figure 17.Normalized Reset Threshold vs. Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 18.Watchdog Time-out Period vs. Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 19.PFI to PFO Propagation Delay vs. Temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 20.Output Voltage vs. Load Current (V = 5V; V
= 2.8V; T = 25°C). . . . . . . . . . . . . . 14
A
CC
BAT
BAT
Figure 21.Output Voltage vs. Load Current (V = 0V; V
= 2.8V; T = 25°C). . . . . . . . . . . . . . 14
A
CC
Figure 22.RST Output Voltage vs. Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 23.RST Output Voltage vs. Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 24.Power-fail Comparator Response Time (Assertion) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 25.Power-fail Comparator Response Time (De-Assertion) . . . . . . . . . . . . . . . . . . . . . . . . . 16
2/26
STM706T/S/R; STM706P; STM708T/S/R
Figure 26.Maximum Transient Duration vs. Reset Threshold Overdrive. . . . . . . . . . . . . . . . . . . . . 17
MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 4. Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
DC and AC PARAMETERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 5. Operating and AC Measurement Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 27.AC Testing Input/Output Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 28.Power-fail Comparator Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 29.MR Timing Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 30.Watchdog Timing (STM706T/S/R and STM706P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 6. DC and AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 31.SO8 – 8-lead Plastic Small Outline, 150 mils body width, Package Mechanical. . . . . . . 21
Table 7. SO8 – 8-lead Plastic Small Outline, 150 mils body width, Package Mechanical Data . . 21
Figure 32.TSSOP8 – 8-lead, Thin Shrink Small Outline, 3x3mm body size, Outline . . . . . . . . . . . 22
Table 8. TSSOP8 – 8-lead, Thin Shrink Small Outline, 3x3mm body size, Mechanical Data . . . . 22
PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 9. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 10. Marking Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 11. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3/26
STM706T/S/R; STM706P; STM708T/S/R
SUMMARY DESCRIPTION
The STM70x Supervisors are self-contained de-
vices which provide microprocessor supervisory
functions. A precision voltage reference and com-
These devices also offer a watchdog timer (except
for STM708T/S/R) as well as a power-fail compar-
ator to provide the system with an early warning of
impending power failure.
parator monitors the V
input for an out-of-toler-
CC
ance condition. When an invalid V
occurs, the reset output (RST) is forced low (or
high in the case of RST).
condition
CC
The STM706P is identical to the STM706R, except
its reset output is active-high.
These devices are available in a standard 8-pin
SOIC package or a space-saving 8-pin TSSOP
package.
Figure 2. Logic Diagram (STM706T/S/R and
STM706P)
Table 2. Signal Names
MR
WDI
WDO
RST
Push-button Reset Input
Watchdog Input
V
CC
Watchdog Output
Active-Low Reset Output
WDI
MR
PFI
WDO
(1)
Active-High Reset Output
Supply Voltage
Power-fail Input
Power-fail Output
Ground
RST
V
STM706T/S/R,
STM706P
(1)
RST (RST)
PFO
CC
PFI
PFO
V
SS
V
SS
AI08841
NC
No Connect
Note: 1. For STM706P and STM708T/S/R only.
Note: 1. For STM706P only.
Figure 3. Logic Diagram (STM708T/S/R)
V
CC
RST
RST
PFO
MR
PFI
STM708T/S/R
V
SS
AI08842
4/26
STM706T/S/R; STM706P; STM708T/S/R
Figure 6. STM708T/S/R SO8 Connections
Figure 4. STM706T/S/R and STM706P SO8
Connections
SO8
SO8
MR
RST
RST
NC
1
2
3
4
8
7
6
5
MR
1
2
3
4
8
7
6
5
WDO
(1)
V
V
CC
RST(RST)
WDI
CC
V
V
SS
SS
PFI
PFO
PFI
PFO
AI08839
AI08837
Note: 1. For STM706P reset output is active-high.
Figure 7. STM708T/S/R TSSOP8 Connections
Figure 5. STM706T/S/R and STM706P TSSOP8
Connections
TSSOP8
TSSOP8
(1)
RST
RST
MR
NC
1
2
3
4
8
7
6
5
RST(RST)
WDO
MR
WDI
PFO
PFI
1
2
3
4
8
7
6
5
PFO
PFI
V
V
CC
SS
V
V
CC
SS
AI08840
AI08838
Note: 1. For STM706P reset output is active-high.
5/26
STM706T/S/R; STM706P; STM708T/S/R
Pin Descriptions
MR. A logic low on MR asserts the reset output.
Reset remains asserted as long as MR is low and
RST. Pulses low for t when triggered, and stays
rec
low whenever V
is below the reset threshold or
CC
for t after MR returns high. This active-low input
when MR is a logic low. It remains low for t after
rec
rec
has an internal pull-up. It can be driven from a TTL
or CMOS logic line, or shorted to ground with a
switch. Leave open if unused.
either V
rises above the reset threshold, the
CC
watchdog triggers a reset, or MR goes from low to
high.
WDI. If WDI remains high or low for 1.6sec, the in-
ternal watchdog timer runs out and reset (or WDO)
is triggered. The internal watchdog timer clears
while reset is asserted or when WDI sees a rising
or falling edge.
The watchdog function cannot be disabled by al-
lowing the WDI pin to float.
RST. Pulses high for t
stays high whenever V
when triggered, and
is above the reset
rec
CC
threshold or when MR is a logic high. It remains
high for t after either V falls below the reset
rec
CC
threshold, the watchdog triggers a reset, or MR
goes from high to low.
PFI. When PFI is less than V , PFO goes low;
PFI
otherwise, PFO remains high. Connect to ground
if unused.
WDO. WDO goes low when a transition does not
occur on WDI within 1.6sec, and remains low until
a transition occurs on WDI (indicating the watch-
dog interrupt has been serviced). WDO also goes
PFO. When PFI is less than V , PFO goes low;
PFI
otherwise, PFO remains high. Leave open if un-
used.
low when V falls below the reset threshold; how-
CC
ever, unlike the reset output, WDO goes high as
soon as V exceeds the reset threshold.
CC
Note: For those devices with a WDO output, a
watchdog timeout will not trigger reset unless
WDO is connected to MR.
Table 3. Pin Description
Pin
STM706P
STM706T/S/R
STM708T/S/R Name
Function
SO8 TSSOP8 SO8 TSSOP8 SO8 TSSOP8
1
6
8
–
7
2
4
5
3
–
3
8
2
–
1
4
6
7
5
–
1
6
8
7
–
2
4
5
3
–
3
8
2
1
–
4
6
7
5
–
1
–
–
7
8
2
4
5
3
6
3
–
–
1
2
4
6
7
5
8
MR
Push-button Reset Input
WDI Watchdog Input
WDO Watchdog Output
RST Active-Low Reset Output
RST Active-High Reset Output
V
CC
Supply Voltage
PFI
PFI Power-fail Input
PFO PFO Power-fail Output
V
Ground
SS
NC
No Connect
6/26
STM706T/S/R; STM706P; STM708T/S/R
Figure 8. Block Diagram (STM706T/S/R and STM706P)
WDI
Transitional
Detector
WATCHDOG
TIMER
WDI
VCC
WDO
VRST
COMPARE
VCC
trec
Generator
RST(RST)(1)
MR
PFI
VPFI
COMPARE
PFO
AI08829
Note: 1. For STM706P only.
Figure 9. Block Diagram (STM708T/S/R)
VCC
COMPARE
VRST
RST
VCC
trec
Generator
RST
MR
PFI
VPFI
COMPARE
PFO
AI08830
7/26
STM706T/S/R; STM706P; STM708T/S/R
Figure 10. Hardware Hookup
Regulator
Unregulated
Voltage
VIN
VCC
VCC
STM706T/S/R;
STM706P;
0.1µF
STM708T/S/R
WDI(1)
To Microprocessor IRQ
To Microprocessor NMI
WDO(1)
PFO
R1
R2
From Microprocessor
PFI
MR
RST
To Microprocessor Reset
Push-button
RST(2)
AI08843
Note: 1. For STM706T/S/R and STM706P.
2. For STM706P and STM708T/S/R.
8/26
STM706T/S/R; STM706P; STM708T/S/R
OPERATION
Reset Output
The STM70x Supervisor asserts a reset signal to
Watchdog Output (STM706T/S/R and
STM706P)
the MCU whenever V
goes below the reset
When V drops below the reset threshold, WDO
will go low even if the watchdog timer has not yet
timed out. However, unlike the reset output, WDO
CC
CC
threshold (V
), a watchdog time-out occurs (if
RST
WDO is connected to MR), or when the Push-but-
ton Reset Input (MR) is taken low. RST is guaran-
teed to be a logic low (logic high for STM706P and
goes high as soon as V
exceeds the reset
CC
threshold. WDO may be used to generate a reset
pulse by connecting it to the MR input.
STM708T/S/R) for V
< V
down to V
=1V
CC
RST
CC
for T = 0°C to 85°C.
A
Power-fail Input/Output
During power-up, once V
threshold an internal timer keeps RST low for the
exceeds the reset
CC
The Power-fail Input (PFI) is compared to an inter-
nal reference voltage (independent from the V
RST
reset time-out period, t . After this interval RST
rec
comparator). If PFI is less than the power-fail
returns high.
threshold (V ), the Power-Fail Output (PFO) will
PFI
If V drops below the reset threshold, RST goes
low. Each time RST is asserted, it stays low for at
go low. This function is intended for use as an un-
dervoltage detector to signal a failing power sup-
ply. Typically PFI is connected through an external
voltage divider (see Figure 10., page 8) to either
the unregulated DC input (if it is available) or the
CC
least the reset time-out period (t ). Any time V
rec
CC
goes below the reset threshold the internal timer
clears. The reset timer starts when V
above the reset threshold.
returns
CC
regulated output of the V regulator. The voltage
CC
divider can be set up such that the voltage at PFI
Push-button Reset Input
A logic low on MR asserts reset. Reset remains
asserted while MR is low, and for t (see Figure
falls below V
several milliseconds before the
input to the STM70x or the micro-
PFI
regulated V
CC
rec
processor drops below the minimum operating
voltage.
If the comparator is unused, PFI should be con-
29., page 19) after it returns high. The MR input
has an internal 40kΩ pull-up resistor, allowing it to
be left open if not used. This input can be driven
with TTL/CMOS-logic levels or with open-drain/
collector outputs. Connect a normally open mo-
mentary switch from MR to GND to create a man-
ual reset function; external debounce circuitry is
not required. If MR is driven from long cables or
the device is used in a noisy environment, connect
a 0.1µF capacitor from MR to GND to provide ad-
ditional noise immunity. MR may float, or be tied to
nected to V
and PFO left unconnected. PFO
SS
may be connected to MR on the STM70x so that a
low voltage on PFI will generate a reset output.
Ensuring a Valid Reset Output Down to
V
= 0V
CC
When V falls below 1V, the state of the RST out-
CC
put can no longer be guaranteed, and becomes
essentially an open circuit. If a high value pull-
down resistor is added to the RST pin, the output
will be held low during this condition. A resistor val-
ue of approximately 100kΩ will be large enough to
not load the output under operating conditions, but
still sufficient to pull RST to ground during this low
voltage condition (see Figure 11).
V
when not used.
CC
Watchdog Input (STM706T/S/R and STM706P)
The watchdog timer can be used to detect an out-
of-control MCU. If the MCU does not toggle the
Watchdog Input (WDI) within t
Watchdog Output pin (WDO) is asserted. The in-
ternal 1.6sec timer is cleared by either:
(1.6sec), the
WD
Figure 11. Reset Output Valid to Ground
Circuit
1. a reset pulse, or
2. by toggling WDI (high-to-low or low-to-high),
which can detect pulses as short as 50ns.
See Figure 30., page 19 for STM706T/S/R and
STM706P.
The timer remains cleared and does not count for
as long as reset is asserted. As soon as reset is re-
leased, the timer starts counting.
STM70x
RST
R1
AI08844
9/26
STM706T/S/R; STM706P; STM708T/S/R
Interfacing to Microprocessors with Bi-
directional Reset Pins
Figure 12. Interfacing to Microprocessors with
Bi-directional Reset I/O
Microprocessors with bi-directional reset pins can
contend with the STM70x reset output. For exam-
ple, if the reset output is driven high and the micro
wants to pull it low, signal contention will result. To
prevent this from occurring, connect a 4.7kΩ resis-
tor between the reset output and the micro’s reset
I/O as in Figure 12.
Buffered Reset to other
System Components
VCC
VCC
STM70x
Microprocessor
4.7k
RST
RST
GND
GND
AI08845
TYPICAL OPERATING CHARACTERISTICS
Note: Typical values are at T = 25°C.
A
Figure 13. Supply Current vs. Temperature (no load)
30
25
20
15
10
5
V
V
V
V
V
= 2.7V
= 3.0V
= 3.6V
= 4.5V
= 5.5V
CC
CC
CC
CC
CC
0
–40
–20
0
20
40
60
80
100
120
Temperature (°C)
AI09141b
10/26
STM706T/S/R; STM706P; STM708T/S/R
Figure 14. V
Threshold vs. Temperature
PFI
1.270
1.265
1.260
1.255
1.250
1.245
1.240
1.235
1.230
1.225
V
V
V
V
= 2.5V
= 3.0V
= 3.3V
= 3.6V
CC
CC
CC
CC
–40
–20
0
20
40
60
80
100
120
Temperature (°C)
AI09142b
Figure 15. Reset Comparator Propagation Delay vs. Temperature
30
28
26
24
22
20
18
16
14
12
10
–40
–20
0
20
40
60
80
100
120
Temperature (°C)
AI09143b
11/26
STM706T/S/R; STM706P; STM708T/S/R
Figure 16. Power-up t
vs. Temperature
rec
240
235
230
225
220
215
210
V
V
V
= 3.0V
= 4.5V
= 5.5V
CC
CC
CC
–40
–20
0
20
40
60
80
100
120
Temperature (°C)
AI09144b
Figure 17. Normalized Reset Threshold vs. Temperature
1.004
1.002
1.000
0.998
0.996
–40
–20
0
20
40
60
80
100
120
Temperature (°C)
AI09145b
12/26
STM706T/S/R; STM706P; STM708T/S/R
Figure 18. Watchdog Time-out Period vs. Temperature
1.90
1.85
1.80
1.75
1.70
1.65
1.60
V
V
V
= 3.0V
= 4.5V
= 5.5V
CC
CC
CC
–40
–20
0
20
40
60
80
100
120
Temperature (°C)
AI09146b
Figure 19. PFI to PFO Propagation Delay vs. Temperature
4.0
V
V
V
V
= 3.0V
CC
CC
CC
CC
= 3.6V
= 4.5V
= 5.5V
3.0
2.0
1.0
0.0
–40
–20
0
20
40
60
80
100
120
Temperature (°C)
AI09148b
13/26
STM706T/S/R; STM706P; STM708T/S/R
Figure 20. Output Voltage vs. Load Current (V = 5V; V
= 2.8V; T = 25°C)
A
CC
BAT
5.00
4.98
4.96
4.94
0
10
20
30
40
50
I
(mA)
OUT
AI10496
Figure 21. Output Voltage vs. Load Current (V = 0V; V
= 2.8V; T = 25°C)
A
CC
BAT
2.80
2.78
2.76
2.74
2.72
2.70
2.68
2.66
0.0
0.2
0.4
0.6
0.8
1.0
I
(mA)
OUT
AI10497
14/26
STM706T/S/R; STM706P; STM708T/S/R
Figure 22. RST Output Voltage vs. Supply Voltage
5
5
V
V
RST
CC
4
3
2
1
0
4
3
2
1
0
500ms/div
AI09149b
Figure 23. RST Output Voltage vs. Supply Voltage
5
5
V
RST
V
CC
4
3
2
1
4
3
2
1
0
0
500ms/div
AI09150b
15/26
STM706T/S/R; STM706P; STM708T/S/R
Figure 24. Power-fail Comparator Response Time (Assertion)
5V
1V/div
PFO
0V
1.3V
PFI
500mV/div
0V
500ns/div
AI09153b
Figure 25. Power-fail Comparator Response Time (De-Assertion)
5V
1V/div
PFO
0V
1.3V
PFI
500mV/div
0V
500ns/div
AI09154b
16/26
STM706T/S/R; STM706P; STM708T/S/R
Figure 26. Maximum Transient Duration vs. Reset Threshold Overdrive
6000
5000
4000
3000
2000
1000
0
Reset occurs
above the curve.
0.001
0.01
0.1
1
10
Reset Comparator Overdrive, V
– V (V)
CC
RST
AI09156b
MAXIMUM RATING
Stressing the device above the rating listed in the
Absolute Maximum Ratings” table may cause per-
manent damage to the device. These are stress
ratings only and operation of the device at these or
any other conditions above those indicated in the
Operating sections of this specification is not im-
plied. Exposure to Absolute Maximum Rating con-
ditions for extended periods may affect device
reliability. Refer also to the STMicroelectronics
SURE Program and other relevant quality docu-
ments.
Table 4. Absolute Maximum Ratings
Symbol
Parameter
Value
Unit
T
Storage Temperature (V Off)
–55 to 150
°C
STG
CC
Lead Solder Temperature for 10 seconds
Input or Output Voltage
Supply Voltage
(1)
260
°C
V
T
SLD
V
–0.3 to V +0.3
IO
CC
V
–0.3 to 7.0
20
V
CC
I
O
Output Current
mA
mW
P
Power Dissipation
320
D
Note: 1. Reflow at peak temperature of 255°C to 260°C for < 30 seconds (total thermal budget not to exceed 180°C for between 90 to 150
seconds).
17/26
STM706T/S/R; STM706P; STM708T/S/R
DC AND AC PARAMETERS
This section summarizes the operating measure-
ment conditions, and the DC and AC characteris-
tics of the device. The parameters in the DC and
AC characteristics Tables that follow, are derived
from tests performed under the Measurement
Conditions summarized in Table 5, Operating and
AC Measurement Conditions. Designers should
check that the operating conditions in their circuit
match the operating conditions when relying on
the quoted parameters.
Table 5. Operating and AC Measurement Conditions
Parameter
STM70x
1.0 to 5.5
–40 to 85
≤ 5
Unit
V
V
CC
Supply Voltage
Ambient Operating Temperature (T )
°C
ns
V
A
Input Rise and Fall Times
0.2 to 0.8V
Input Pulse Voltages
CC
0.3 to 0.7V
Input and Output Timing Ref. Voltages
V
CC
Figure 27. AC Testing Input/Output Waveforms
0.8V
CC
0.7V
CC
0.3V
CC
0.2V
CC
AI02568
Figure 28. Power-fail Comparator Waveform
VCC
VRST
trec
PFO
RST
AI08860a
18/26
STM706T/S/R; STM706P; STM708T/S/R
Figure 29. MR Timing Waveform
MR
tMLRL
RST (1)
trec
tMLMH
AI07837a
Note: 1. RST for STM706P and STM708T/S/R.
Figure 30. Watchdog Timing (STM706T/S/R and STM706P)
VCC
trec
RST
tWD
WDI
WDO
AI08833
Table 6. DC and AC Characteristics
Alter-
(1)
Sym
Description
Min
Typ
Max
Unit
Test Condition
native
(2)
V
Operating Voltage
V Supply Current
CC
5.5
50
V
µA
µA
µA
nA
µA
µA
V
CC
1.2
V
V
< 3.6V
< 5.5V
35
40
CC
I
CC
60
CC
0V = V = V
Input Leakage Current (WDI)
Input Leakage Current (PFI)
–1
+1
IN
CC
0V = V = V
–25
25
2
+25
250
300
IN
CC
I
LI
V
RST
(max) < V < 3.6V
CC
80
Input Leakage Current (MR)
4.5V < V
< 5.5V
< 5.5V
75
125
CC
CC
4.5V < V
2.0
V
V
Input High Voltage (MR)
Input High Voltage (WDI)
Input Low Voltage (MR)
Input Low Voltage (WDI)
IH
IH
V
V
(max) < V < 3.6V
0.7V
CC
V
RST
CC
(max) < V < 5.5V
0.7V
CC
V
RST
CC
4.5V < V
< 5.5V
0.8
0.6
V
CC
V
IL
IL
V
V
(max) < V < 3.6V
V
RST
CC
V
(max) < V < 5.5V
0.3V
V
RST
CC
CC
19/26
STM706T/S/R; STM706P; STM708T/S/R
Alter-
native
(1)
Sym
Description
Min
Typ
Max
Unit
Test Condition
V
= V
(max),
RST
Output Low Voltage (PFO,
RST, RST, WDO)
CC
I
V
OL
0.3
V
= 3.2mA
SINK
I
= 50µA, V = 1.0V,
CC
T = 0°C to 85°C
A
SINK
0.3
0.3
V
V
V
V
OL
Output Low Voltage (RST)
I
= 100µA, V = 1.2V
SINK
CC
I
V
= 1mA,
Output High Voltage (RST,
RST, WDO)
SOURCE
2.4
= V
(max)
RST
CC
V
OH
I
V
= 75µA,
(max)
RST
SOURCE
0.8V
Output High Voltage (PFO)
V
CC
= V
CC
Power-fail Comparator
PFI Falling
(STM70xP/R, V = 3.0V;
V
PFI Input Threshold
1.20
1.25
2
1.30
V
CC
PFI
STM70xS/T, V = 3.3V)
CC
t
PFI to PFO Propagation Delay
µs
PFD
Reset Thresholds
STM706P/70xR
STM70xS
2.55
2.85
3.00
2.63
2.93
3.08
20
2.70
3.00
3.15
V
V
(3)
V
RST
Reset Threshold
STM70xT
V
Reset Threshold Hysteresis
RST Pulse Width
mV
ms
t
140
200
280
rec
Push-button Reset Input
V
V
(max) < V < 3.6V
CC
500
150
ns
ns
ns
ns
RST
t
t
MR
MR Pulse Width
MLMH
4.5V < V
< 5.5V
CC
(max) < V < 3.6V
750
250
RST
CC
t
t
MRD
MR to RST Output Delay
MLRL
4.5V < V
< 5.5V
CC
Watchdog Timer (STM706T/S/R and STM706P)
STM706P/70xR,
= 3.0V
V
CC
t
Watchdog Timeout Period
WDI Pulse Width
1.12
1.60
2.24
s
WD
STM70xS/70XT,
= 3.3V
V
CC
4.5V < V
< 5.5V
50
ns
ns
CC
V
(max) < V < 3.6V
CC
100
RST
Note: 1. Valid for Ambient Operating Temperature: T = –40 to 85°C; V = V (max) to 5.5V (except where noted).
RST
A
CC
2. V (min) = 1.0V for T = 0°C to +85°C.
CC
A
3. For V falling.
CC
20/26
STM706T/S/R; STM706P; STM708T/S/R
PACKAGE MECHANICAL
Figure 31. SO8 – 8-lead Plastic Small Outline, 150 mils body width, Package Mechanical
h x 45˚
A2
A
C
B
ddd
e
D
8
1
E
H
A1
α
L
SO-A
Note: Drawing is not to scale.
Table 7. SO8 – 8-lead Plastic Small Outline, 150 mils body width, Package Mechanical Data
mm
Min
1.35
0.10
0.33
0.19
4.80
–
inches
Min
Symb
Typ
–
Max
1.75
0.25
0.51
0.25
5.00
0.10
4.00
–
Typ
Max
0.069
0.010
0.020
0.010
0.197
0.004
0.157
–
A
A1
B
–
0.053
0.004
0.013
0.007
0.189
–
–
–
–
–
C
–
–
D
–
–
ddd
E
–
–
–
3.80
–
–
0.150
–
e
1.27
–
0.050
H
5.80
0.25
0.40
0°
6.20
0.50
0.90
8°
–
–
–
–
0.228
0.010
0.016
0°
0.244
0.020
0.035
8°
h
–
L
–
α
–
N
8
8
21/26
STM706T/S/R; STM706P; STM708T/S/R
Figure 32. TSSOP8 – 8-lead, Thin Shrink Small Outline, 3x3mm body size, Outline
D
8
1
5
4
c
E1
E
α
A1
L
A
A2
L1
CP
b
e
TSSOP8BM
Note: Drawing is not to scale.
Table 8. TSSOP8 – 8-lead, Thin Shrink Small Outline, 3x3mm body size, Mechanical Data
mm
Min
–
inches
Min
–
Symb
Typ
–
Max
1.10
0.15
0.95
0.40
0.23
0.10
3.10
–
Typ
–
Max
0.043
0.006
0.037
0.016
0.009
0.004
0.122
–
A
A1
A2
b
–
0.05
0.75
0.25
0.13
–
–
0.002
0.030
0.010
0.005
–
0.85
–
0.034
–
c
–
–
CP
D
–
–
3.00
0.65
4.90
3.00
0.55
0.95
–
2.90
–
0.118
0.026
0.193
0.118
0.022
0.037
–
0.114
–
e
E
4.65
2.90
0.40
–
5.15
3.10
0.70
–
0.183
0.114
0.016
–
0.203
0.122
0.030
–
E1
L
L1
α
0°
6°
0°
6°
N
8
8
22/26
STM706T/S/R; STM706P; STM708T/S/R
PART NUMBERING
Table 9. Ordering Information Scheme
Example:
STM706
T
M
6
E
Device Type
STM706
STM708
Reset Threshold Voltage
T: 3.00V ≤ V
≤ 3.15V
≤ 3.00V
RST
S: 2.88V ≤ V
RST
R, STM706P: 2.59V ≤ V
≤ 2.70V
RST
Package
M = SO8
DS = TSSOP8
Temperature Range
6 = –40 to 85°C
Shipping Method
E = Tubes
F = Tape & Reel
For other options, or for more information on any aspect of this device, please contact the ST Sales Office
nearest you.
23/26
STM706T/S/R; STM706P; STM708T/S/R
Table 10. Marking Description
Part Number
Reset Threshold
Package
SO8
Topside Marking
STM706P
2.63V
706P
TSSOP8
SO8
STM706T
STM706S
STM706R
STM708T
STM708S
STM708R
3.08V
2.93V
2.63V
3.08V
2.93V
2.63V
706T
706S
706R
708T
708S
708R
TSSOP8
SO8
TSSOP8
SO8
TSSOP8
SO8
TSSOP8
SO8
TSSOP8
SO8
TSSOP8
24/26
STM706T/S/R; STM706P; STM708T/S/R
REVISION HISTORY
Table 11. Document Revision History
Date
Version
Revision Details
October 2003
1.0
First Issue
Reformatted; update characteristics (Figure 2, 3, 8, 9, 10, 28, 29, 30; Table 6, 7, 8,
9)
12-Dec-03
16-Jan-04
2.0
2.1
Add Typical Operating Characteristics (Figure 13, 14, 15, 16, 17, 18, 19, 22, 23, 24,
25, 26)
09-Apr-04
25-May-04
02-Jul-04
21-Sep-04
3.0
4.0
5.0
6.0
Reformatted; update characteristics (Figure 15, 19, 22, 23, 26; Table 6)
Update characteristics (Table 3, 6)
Datasheet promoted; waveform corrected (Figure 28)
Clarify root part numbers; (Figure 2, 3, 4, 5, 6, 7, 8, 9, 10, 30; Table 1, 3, 6, 9)
Update Typical Characteristics (Figure 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23,
24, 25, 26)
25-Feb-05
7.0
25/26
STM706T/S/R; STM706P; STM708T/S/R
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
The ST logo is a registered trademark of STMicroelectronics.
All other names are the property of their respective owners
© 2005 STMicroelectronics - All rights reserved
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26/26
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