STM802SM6F [STMICROELECTRONICS]
3V Supervisor with Battery Switchover; 3V监控器，电池切换
| 型号： | STM802SM6F |
| 厂家： | 
ST |
| 描述： | 3V Supervisor with Battery Switchover |
| 文件： | 总31页 (文件大小：447K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
STM690, STM704, STM795
STM802, STM804, STM805, STM806
3V Supervisor with Battery Switchover
FEATURES SUMMARY
■
RST OR RST OUTPUTS
Figure 1. Packages
■
NVRAM SUPERVISOR FOR EXTERNAL
LPSRAM
■
CHIP-ENABLE GATING (STM795 only) FOR
EXTERNAL LPSRAM (7ns max PROP
DELAY)
8
■
■
■
■
■
MANUAL (PUSH-BUTTON) RESET INPUT
1
200ms (TYP) t
rec
WATCHDOG TIMER - 1.6sec (TYP)
AUTOMATIC BATTERY SWITCHOVER
LOW BATTERY SUPPLY CURRENT - 0.4µA
(TYP)
SO8 (M)
■
■
■
POWER-FAIL COMPARATOR (PFI/PFO)
LOW SUPPLY CURRENT - 40µA (TYP)
GUARANTEED RST (RST) ASSERTION
TSSOP8 3x3 (DS)*
DOWN TO V = 1.0V
CC
■
OPERATING TEMPERATURE:
–40°C to 85°C (Industrial Grade)
Table 1. Device Options
Active-
High
RST
Power-fail
Compar-
Chip-
Enable
Gating
Active-
Watchdog
Input
Manual
Reset Input Switch-over
Battery
(1)
Low RST
ator
STM690T/S/R
STM704T/S/R
STM795T/S/R
STM802T/S/R
STM804T/S/R
■
■
■
■
■
■
■
■
■
■
■
■
■
(2)
■
■
■
■
■
■
■
■
■
■
(2)
■
(2)
STM805T/S/R
STM806T/S/R
■
■
■
Note: 1. All RST outputs push-pull (unless otherwise noted)
2. Open drain output.
* Contact local ST sales office for availability.
September 2004
1/31
STM690/704/795/802/804/805/806
TABLE OF CONTENTS
FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Figure 1. Packages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Table 1. Device Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
SUMMARY DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Figure 2. Logic Diagram (STM690/802/804/805) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Figure 3. Logic Diagram (STM704/806) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Figure 4. Logic Diagram (STM795). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Table 2. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Figure 5. STM690/802/804/805 Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 6. STM704/806 Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 7. STM795 Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Table 3. Pin Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 8. Block Diagram (STM690/802/804/805) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 9. Block Diagram (STM704/806) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 10.Block Diagram (STM795) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 11.Hardware Hookup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Reset Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Push-button Reset Input (STM704/806). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Watchdog Input (NOT available on STM704/795/806) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Back-up Battery Switchover. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 4. I/O Status in Battery Back-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Chip-Enable Gating (STM795 only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Chip Enable Input (STM795 only). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Chip Enable Output (STM795 only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 12.Chip-Enable Gating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 13.Chip Enable Waveform (STM795) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Power-fail Input/Output (NOT available on STM795) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Applications Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 14.Power-fail Comparator Waveform (STM690/704/802/804/805/806) . . . . . . . . . . . . . . . . 11
Using a SuperCap™ as a Backup Power Source. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 15.Using a SuperCap™ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Negative-Going V Transients . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
CC
TYPICAL OPERATING CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 16.V
-to-V
On-Resistance vs. Temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
OUT
BAT
Figure 17.Supply Current vs. Temperature (no load) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 18.V Threshold vs. Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
PFI
Figure 19.Reset Comparator Propagation Delay vs. Temperature . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 20.Power-up t vs. Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
rec
2/31
STM690/704/795/802/804/805/806
Figure 21.Normalized Reset Threshold vs. Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 22.Watchdog Time-out Period vs. Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 23.E to E
On-Resistance vs. Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
CON
Figure 24.PFI to PFO Propagation Delay vs. Temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 25.RST Output Voltage vs. Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 26.RST Output Voltage vs. Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 27.RST Response Time (Assertion). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 28.RESET Response Time (Assertion) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 29.Power-fail Comparator Response Time (Assertion) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 30.Power-fail Comparator Response Time (De-Assertion) . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 31.V to Reset Propagation Delay vs. Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
CC
Figure 32.Maximum Transient Duration vs. Reset Threshold Overdrive. . . . . . . . . . . . . . . . . . . . . 20
Figure 33.E to E
Propagation Delay vs. Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
CON
MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 5. Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
DC and AC PARAMETERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 6. Operating and AC Measurement Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 34.E to ECON Propagation Delay Test Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 35.AC Testing Input/Output Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 36.MR Timing Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 37.Watchdog Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 7. DC and AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 38.SO8 – 8-lead Plastic Small Outline, 150 mils body width, Package Mech. Drawing. . . . 26
Table 8. SO8 – 8-lead Plastic Small Outline, 150 mils body width, Package Mechanical Data . . 26
Figure 39.TSSOP8 – 8-lead, Thin Shrink Small Outline, 3x3mm body size, Outline . . . . . . . . . . . 27
Table 9. TSSOP8 – 8-lead, Thin Shrink Small Outline, 3x3mm body size, Mechanical Data . . . . 27
PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 10. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 11. Marking Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 12. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3/31
STM690/704/795/802/804/805/806
SUMMARY DESCRIPTION
The STM690/704/795/802/804/805/806 Supervi-
sors are self-contained devices which provide mi-
croprocessor supervisory functions with the ability
to non-volatize and write-protect external
LPSRAM. A precision voltage reference and com-
a watchdog timer (except for STM704/795/806) as
well as a power-fail comparator (except for
STM795) to provide the system with an early
warning of impending power failure.
These devices are available in a standard 8-pin
SOIC package or a space-saving 8-pin TSSOP
package.
parator monitors the V
input for an out-of-toler-
CC
ance condition. When an invalid V
condition
CC
occurs, the reset output (RST) is forced low (or
high in the case of RST). These devices also offer
Figure 2. Logic Diagram (STM690/802/804/805)
Figure 4. Logic Diagram (STM795)
V
V
BAT
V
V
BAT
CC
CC
V
V
OUT
OUT
V
WDI
PFI
STM690/
802/804/
805
CCSW
(1)
RST
E
RST(RST)
STM795
E
PFO
CON
V
V
SS
SS
AI08848
AI08846
Note: 1. For STM804/805, reset output is active-high and open
drain.
Table 2. Signal Names
MR
WDI
RST
Push-button Reset Input
Figure 3. Logic Diagram (STM704/806)
Watchdog Input
V
V
BAT
CC
Active-Low Reset Output
Active-High Reset Output
(1)
RST
V
OUT
(2)
Chip Enable Input
E
MR
PFI
STM704
STM806
RST
PFO
(2)
Conditioned Chip Enable Output
Switch Output
E
CON
(2)
V
CC
Vccsw
V
Supply Voltage Output
Supply Voltage
OUT
V
SS
V
AI08847
CC
V
Back-up Supply Voltage
Power-fail Input
Power-fail Output
Ground
BAT
PFI
PFO
V
SS
Note: 1. Open drain for STM804/805 only.
2. STM795
4/31
STM690/704/795/802/804/805/806
Figure 5. STM690/802/804/805 Connections
Figure 6. STM704/806 Connections
SO8/TSSOP8
SO8/TSSOP8
V
V
BAT
OUT
1
2
3
4
8
7
6
5
V
V
BAT
(1)
OUT
1
2
3
4
8
7
6
5
V
RST(RST)
WDI
CC
V
RST
MR
CC
V
SS
V
SS
PFI
PFO
PFI
PFO
AI08849
AI08850
Note: 1. For STM804/805, reset output is active-high and open
drain.
Figure 7. STM795 Connections
SO8/TSSOP8
V
V
BAT
OUT
1
2
3
4
8
7
6
5
V
RST
E
CC
V
CCSW
CON
V
E
SS
AI08851
5/31
STM690/704/795/802/804/805/806
Pin Descriptions
MR. A logic low on /MR asserts the reset output.
Reset remains asserted as long as MR is low and
PFI. When PFI is less than V
or when V falls
PFI CC
below V
(2.4V), PFO goes low; otherwise, PFO
SW
for t after MR returns high. This active-low input
remains high. Connect to ground if unused.
rec
has an internal pull-up. It can be driven from a TTL
or CMOS logic line, or shorted to ground with a
switch. Leave open if unused.
PFO. When PFI is less than V , or V falls be-
PFI
CC
low V , PFO goes low; otherwise, PFO remains
SW
high. Leave open if unused.
WDI. If WDI remains high or low for 1.6sec, the in-
ternal watchdog timer runs out and reset is trig-
gered. The internal watchdog timer clears while
reset is asserted or when WDI sees a rising or fall-
ing edge.
V
. When V is above the switchover voltage
CC
OUT
SO
(V ), V
channel MOSFET switch. When V
V
is connected to V
through a P-
OUT
CC
falls below
CC
, V
SO BAT
connects to V
. Connect to V if no
OUT CC
battery is used.
The watchdog function cannot be disabled by al-
lowing the WDI pin to float.
switches to battery, Vccsw is
OUT
switches back to V , Vccsw is
CC
low. It can be used to drive gate of external PMOS
transistor for I requirements exceeding 75mA.
rec
OUT
when MR is a logic low. It remains low for t after
rec
E. The input to the chip-enable gating circuit. Con-
nect to ground if unused.
either V
rises above the reset threshold, the
CC
watchdog triggers a reset, or MR goes from low to
high.
E
. E
goes low only when E is low and re-
CON
CON
set is not asserted. If E
is low when reset is as-
CON
RST (Open Drain). Pulses high for t when trig-
rec
serted, E
will remain low for 15µs or until E
CON
gered, and stays high whenever V is above the
CC
goes high, whichever occurs first. In the disabled
mode, E is pulled up to V
reset threshold or when MR is a logic high. It re-
.
OUT
CON
mains high for t after either V
falls below the
rec
CC
V
. When V
falls below V , V
switches
OUT
BAT
CC
SO
reset threshold, the watchdog triggers a reset, or
MR goes from high to low.
from V
to V
. When V
rises above V
+
CC
BAT
CC
SO
hysteresis, V
reconnects to V . V
may ex-
OUT
CC BAT
ceed V . Connect to V if no battery is used.
CC
CC
Table 3. Pin Description
Pin
Name
Function
STM690
STM802
STM704
STM806
STM804
STM805
STM795
–
–
7
–
–
–
1
2
3
4
5
6
8
–
6
7
–
4
5
1
2
–
3
–
–
8
6
–
7
–
4
5
1
2
–
3
–
–
8
–
6
–
7
4
5
1
2
–
3
–
–
8
MR
Push-button Reset Input
WDI Watchdog Input
RST Active-Low Reset Output
RST Active-High Reset Output
PFI PFI Power-fail Input
PFO PFO Power-fail Output
V
OUT
Supply Output for External LPSRAM
Supply Voltage
V
CC
V
CC
Switch Output
Vccsw
V
SS
Ground
E
Chip Enable Input
E
CON
Conditioned Chip Enable Output
Backup-Battery Input
V
BAT
6/31
STM690/704/795/802/804/805/806
Figure 8. Block Diagram (STM690/802/804/805)
VCC
VOUT
VBAT
COMPARE
COMPARE
VSO
VRST
trec
Generator
RST(RST)(1)
WATCHDOG
TIMER
WDI
PFI
VPFI
COMPARE
PFO
AI07897
Note: 1. For STM804/805, reset output is active-high and open drain.
Figure 9. Block Diagram (STM704/806)
VCC
VOUT
VBAT
COMPARE
COMPARE
VSO
VRST
trec
Generator
RST
MR
PFI
VPFI
COMPARE
PFO
AI07898
7/31
STM690/704/795/802/804/805/806
Figure 10. Block Diagram (STM795)
VCC
VOUT
VBAT
VCCSW
COMPARE
COMPARE
VSO
trec
Generator
RST
VRST
ECON OUTPUT
CONTROL
E
ECON
PFO
PFI
VPFI
COMPARE
AI08852
Figure 11. Hardware Hookup
(2)
VCCSW
Regulator
Unregulated
Voltage
VCC
VCC
LPSRAM
VIN
VCC
VCC
VOUT
STM690/704/
795/802/804/
805/806
0.1µF
E
E
0.1µF
WDI(1)
From Microprocessor
E(2)
(2)
ECON
R1
R2
PFI(3)
MR(4)
VBAT
PFO(3)
RST
To Microprocessor NMI
To Microprocessor Reset
Push-Button
AI08853
Note: 1. For STM690/802/804/805.
2. For STM795 only.
3. Not available on STM795.
4. For STM704/806.
8/31
STM690/704/795/802/804/805/806
OPERATION
Reset Output
The STM690/704/795/802/804/805/806 Supervi-
sor asserts a reset signal to the MCU whenever
Note: Input frequency greater than 20ns (50MHz)
will be filtered.
V
goes below the reset threshold (V
), a
CC
RST
Back-up Battery Switchover
In the event of a power failure, it may be necessary
to preserve the contents of external SRAM
watchdog time-out occurs, or when the Push-but-
ton Reset Input (MR) is taken low. RST is guaran-
teed to be a logic low (logic high for STM804/805)
through V
. With a backup battery installed with
, the devices automatically switch the
OUT
for 0V < V
< V
if V
is greater than 1V.
CC
RST
BAT
voltage V
BAT
Without a back-up battery, RST is guaranteed val-
id down to V =1V.
During power-up, once V
threshold an internal timer keeps RST low for the
reset time-out period, t . After this interval RST
returns high.
If V drops below the reset threshold, RST goes
low. Each time RST is asserted, it stays low for at
least the reset time-out period (t ). Any time V
goes below the reset threshold the internal timer
clears. The reset timer starts when V
above the reset threshold.
Push-button Reset Input (STM704/806)
A logic low on MR asserts reset. Reset remains
SRAM to the back-up supply when V falls.
Note: If back-up battery is not used, connect both
CC
CC
exceeds the reset
CC
V
and V
to V
.
BAT
OUT
CC
This family of Supervisors does not always con-
nect V to V when V is greater than V
rec
.
CC
BAT
OUT
BAT
V
connects to V
CC
(through a 100Ω switch)
(2.4V) or V
BAT
OUT
SW
CC
when V is below V
(whichever
BAT
is lower). This is done to allow the back-up battery
(e.g., a 3.6V lithium cell) to have a higher voltage
rec
CC
than V
.
CC
returns
CC
Assuming that V
> 2.0V, switchover at V en-
SO
BAT
sures that battery back-up mode is entered before
V
gets too close to the 2.0V minimum required
OUT
to reliably retain data in most external SRAMs.
When V recovers, hysteresis is used to avoid
asserted while MR is low, and for t (see Figure
rec
CC
36., page 22) after it returns high. The MR input
has an internal 40kΩ pull-up resistor, allowing it to
be left open if not used. This input can be driven
with TTL/CMOS-logic levels or with open-drain/
collector outputs. Connect a normally open mo-
mentary switch from MR to GND to create a man-
ual reset function; external debounce circuitry is
not required. If MR is driven from long cables or
the device is used in a noisy environment, connect
a 0.1µF capacitor from MR to GND to provide ad-
ditional noise immunity. MR may float, or be tied to
oscillation around the V point. V
is connect-
SO
OUT
ed to V through a 3Ω PMOS power switch.
CC
Note: The back-up battery may be removed while
V
is valid, assuming V
is adequately decou-
CC
BAT
pled (0.1µF typ), without danger of triggering a re-
set.
Table 4. I/O Status in Battery Back-up
Pin
Status
V
when not used.
V
OUT
Connected to V
through internal switch
BAT
CC
Watchdog Input (NOT available on STM704/
795/806)
The watchdog timer can be used to detect an out-
of-control MCU. If the MCU does not toggle the
V
Disconnected from V
Disabled
CC
PFI
PFO
E
OUT
Logic Low
Watchdog Input (WDI) within t
(1.6sec typ), the
WD
High impedance
Logic High
reset is asserted. The internal watchdog timer is
cleared by either:
1. a reset pulse, or
2. by toggling WDI (high-to-low or low-to-high),
which can detect pulses as short as 50ns. If
WDI is tied high or low, a reset pulse is
E
CON
WDI
MR
Watchdog timer is disabled
Disabled
RST
RST
Logic Low
triggered every 1.8sec (t
+ t ).
WD
rec
The timer remains cleared and does not count for
as long as reset is asserted. As soon as reset is re-
leased, the timer starts counting (see Figure
37., page 23).
Logic High
V
BAT
Connected to V
OUT
Vccsw Logic High (STM795)
9/31
STM690/704/795/802/804/805/806
Chip-Enable Gating (STM795 only)
Any time a reset is generated, the chip-enable
transmission gate remains disabled and E remains
high impedance (regardless of E activity) for the
first half of the reset time-out period (t /2). When
rec
the chip enable transmission gate is enabled, the
mal operation (reset not asserted), the E transmis-
sion gate is enabled and passes all E transitions.
When reset is asserted, this path becomes dis-
abled, preventing erroneous data from corrupting
the CMOS RAM. The short E propagation delay
impedance of E appears as a 40Ω resistor in se-
ries with the load at E
. The propagation delay
CON
through the chip-enable transmission gate de-
pends on V , the source impedance of the drive
CC
connected to E, and the loading on E
. The chip
CON
from E to E
enables the STM795 to be used
enable propagation delay is production tested
CON
with most µPs. If E is low when reset asserts,
remains low for typically 10µs to permit the
current WRITE cycle to complete.
from the 50% point on E to the 50% point on E
using a 50Ω driver and a 50pF load capacitance
(see Figure 35., page 22). For minimum propaga-
CON
E
CON
tion delay, minimize the capacitive load at E
and use a low-output impedance driver.
Chip Enable Output (STM795 only)
CON
Chip Enable Input (STM795 only)
The chip-enable transmission gate is disabled and
E is high impedance (disabled mode) while reset
is asserted. During a power-down sequence when
When the chip-enable transmission gate is en-
abled, the impedance of E is equivalent to a
V
passes the reset threshold, the chip-enable
CC
CON
transmission gate disables and E immediately be-
comes high impedance if the voltage at E is high.
If E is low when reset asserts, the chip-enable
transmission gate will disable 10µs after reset as-
serts (see Figure 13). This permits the current
WRITE cycle to complete during power-down.
40Ω resistor in series with the source driving E. In
the disabled mode, the transmission gate is off
and an active pull-up connects E
to V
(see
CON
OUT
Figure 12). This pull-up turns off when the trans-
mission gate is enabled.
Figure 12. Chip-Enable Gating
VCC
trec
Generator
RST
COMPARE
VRST
VOUT
E
CON OUTPUT
CONTROL
E
ECON
AI08802
Figure 13. Chip Enable Waveform (STM795)
VCC
VRST
VBAT
ECON
½ trec
½ trec
trec
10µs
trec
RST
E
AI08855b
10/31
STM690/704/795/802/804/805/806
Power-fail Input/Output (NOT available on STM795)
The Power-fail Input (PFI) is compared to an inter-
drops
CC
nal reference voltage (independent from the V
RST
comparator). If PFI is less than the power-fail
er-fail comparator is enabled and PFO follows PFI.
If the comparator is unused, PFI should be con-
threshold (V ), the Power-Fail Output (PFO) will
PFI
go low. This function is intended for use as an un-
dervoltage detector to signal a failing power sup-
ply. Typically PFI is connected through an external
voltage divider (see Figure 11., page 8) to either
the unregulated DC input (if it is available) or the
nected to V
and PFO left unconnected. PFO
SS
may be connected to MR on the STM704/806 so
that a low voltage on PFI will generate a reset out-
put.
Applications Information
These Supervisor circuits are not short-circuit pro-
tected. Shorting V
er-up transients such as charging a decoupling
capacitor - destroys the device. Decouple both
regulated output of the V regulator. The voltage
CC
divider can be set up such that the voltage at PFI
to ground - excluding pow-
OUT
falls below V
several milliseconds before the
input to the STM690/704/795/802/
PFI
regulated V
CC
804/805/806 or the microprocessor drops below
the minimum operating voltage.
During battery back-up, the power-fail comparator
is turned off and PFO goes (or remains) low (see
V
and V
pins to ground by placing 0.1µF ca-
CC
BAT
pacitors as close to the device as possible.
Figure 14. Power-fail Comparator Waveform (STM690/704/802/804/805/806)
V
CC
V
RST
V
(2.4V)
SW
trec
PFO
PFO follows PFI
PFO follows PFI
RST
AI08861a
11/31
STM690/704/795/802/804/805/806
Using a SuperCap™ as a Backup Power
Source
Negative-Going V Transients
The STM690/704/795/802/804/805/806 Supervi-
CC
SuperCaps™ are capacitors with extremely high
capacitance values (e.g., order of 0.47F) for their
size. Figure 15 shows how to use a SuperCap as
a back-up power source. The SuperCap may be
sors are relatively immune to negative-going V
CC
transients (glitches). Figure 32., page 20 was gen-
erated using a negative pulse applied to V
,
CC
starting at V
+ 0.3V and ending below the reset
RST
connected through a diode to the V
supply.
is above
threshold by the magnitude indicated (comparator
overdrive). The graph indicates the maximum
CC
Since V
can exceed V
while V
BAT
CC
CC
the reset threshold, there are no special precau-
tions when using these supervisors with a Super-
Cap.
pulse width a negative V
transient can have
CC
without causing a reset pulse. As the magnitude of
the transient increases (further below the thresh-
old), the maximum allowable pulse width decreas-
es. Any combination of duration and overdrive
which lies under the curve will NOT generate a re-
Figure 15. Using a SuperCap™
5V
set signal. Typically, a V
transient that goes
CC
100mV below the reset threshold and lasts 40µs or
VCC
VOUT
To external SRAM
STMXXX
VBAT
RST
To µP
GND
AI08805
12/31
STM690/704/795/802/804/805/806
TYPICAL OPERATING CHARACTERISTICS
Note: Typical values are at T = 25°C.
A
Figure 16. V
-to-V
BAT
On-Resistance vs. Temperature
OUT
220
200
180
160
140
120
100
V
= 0V
CC
V
= 2V
BAT
V
= 3V
BAT
V
= 3.3V
BAT
V
= 5V
BAT
–60
–40
–20
0
20
40
60
80
100
120
140
TEMPERATURE [°C]
AI09140
Figure 17. Supply Current vs. Temperature (no load)
30
25
20
15
10
5
2.5V
3.3V
3.6V
5.0V
5.5V
0
–50 –40 –30 –20 –10
0
10
20
30
40
50
60
70
80
90
100
TEMPERATURE [°C]
AI09141
13/31
STM690/704/795/802/804/805/806
Figure 18. V
Threshold vs. Temperature
PFI
1.255
1.250
1.245
1.240
1.235
1.230
V
= 5V
CC
V
= 3.3V
CC
V
= 2.5V
CC
V
= 3.0V
BAT
1.225
–50
–30
–10
10
30
50
70
90
110
130
TEMPERATURE [°C]
AI09142
Figure 19. Reset Comparator Propagation Delay vs. Temperature
24
22
V
= 3.0V
BAT
20
18
16
14
12
10
100mV OVERDRIVE
–60
–40
–20
0
20
40
60
80
100
TEMPERATURE [°C]
AI09143
Figure 20. Power-up t
vs. Temperature
rec
215
210
205
200
195
–50
–30
–10
10
30
50
70
90
110
130
TEMPERATURE [°C]
AI09144
14/31
STM690/704/795/802/804/805/806
Figure 21. Normalized Reset Threshold vs. Temperature
1.002
1.000
0.998
0.996
V
= 3.0V
BAT
0.994
–60
–40
–20
0
20
40
60
80
100
120
140
TEMPERATURE [°C]
AI09145
Figure 22. Watchdog Time-out Period vs. Temperature
1.74
1.72
1.70
1.68
1.66
1.64
1.62
1.60
1.58
1.56
–50
–30
–10
10
30
50
70
90
110
130
TEMPERATURE [°C]
AI09146
Figure 23. E to E
On-Resistance vs. Temperature
CON
90
80
70
60
50
40
V
= 3V
CC
30
–60
–40
–20
0
20
40
60
80
100
120
140
TEMPERATURE [°C]
AI09147
15/31
STM690/704/795/802/804/805/806
Figure 24. PFI to PFO Propagation Delay vs. Temperature
9
8
7
6
5
4
3
2
1
0
–60
–40
–20
0
20
40
60
80
100
120
140
TEMPERATURE [°C]
AI09148
Figure 25. RST Output Voltage vs. Supply Voltage
6
5
4
V
CC
3
2
1
0
V
RST
500 ms/div
AI09149
16/31
STM690/704/795/802/804/805/806
Figure 26. RST Output Voltage vs. Supply Voltage
6
5
V
CC
4
3
2
1
0
V
RST
500 ms/div
AI09150
Figure 27. RST Response Time (Assertion)
6
5
4
3
2
1
0
V
CC
V
RST
2 µs/div
AI09151
17/31
STM690/704/795/802/804/805/806
Figure 28. RESET Response Time (Assertion)
6
V
CC
5
4
3
2
1
0
V
RST
2µs/div
AI09152
Figure 29. Power-fail Comparator Response Time (Assertion)
6
1.45
1.40
1.35
1.30
1.25
1.20
1.15
5
4
PFO
3
PFI
2
1
0
2µs/div
AI09153
18/31
STM690/704/795/802/804/805/806
Figure 30. Power-fail Comparator Response Time (De-Assertion)
6
5
4
3
2
1
0
1.45
1.40
1.35
1.30
1.25
1.20
PFO
PFI
1.15
2 µs/div
AI09154
Figure 31. V to Reset Propagation Delay vs. Temperature
CC
60
50
40
30
20
10
0
10V/ms
1V/ms
0.25V/ms
–60
–40
–20
0
20
40
60
80
100
TEMPERATURE [°C]
AI09155
19/31
STM690/704/795/802/804/805/806
Figure 32. Maximum Transient Duration vs. Reset Threshold Overdrive
250
200
150
100
50
0
1
10
100
1000
10000
RESET COMPARATOR OVERDRIVE, V
– V [mV]
CC
RST
AI09156
Figure 33. E to E
Propagation Delay vs. Temperature
CON
3.5
E Rising
3.0
2.5
2.0
1.5
1.0
0.5
E Falling
0
140
–60
–40
–20
0
20
40
60
80
100
120
TEMPERATURE [°C]
AI09157
20/31
STM690/704/795/802/804/805/806
MAXIMUM RATING
Stressing the device above the rating listed in the
Absolute Maximum Ratings” table may cause per-
manent damage to the device. These are stress
ratings only and operation of the device at these or
any other conditions above those indicated in the
Operating sections of this specification is not im-
plied. Exposure to Absolute Maximum Rating con-
ditions for extended periods may affect device
reliability. Refer also to the STMicroelectronics
SURE Program and other relevant quality docu-
ments.
Table 5. Absolute Maximum Ratings
Symbol
Parameter
Value
Unit
T
Storage Temperature (V Off)
–55 to 150
°C
STG
CC
Lead Solder Temperature for 10 seconds
Input or Output Voltage
Supply Voltage
(1)
260
°C
V
T
SLD
V
–0.3 to V +0.3
IO
CC
V
/V
–0.3 to 6.0
20
V
CC BAT
I
O
Output Current
mA
mW
P
Power Dissipation
320
D
Note: 1. Reflow at peak temperature of 255°C to 260°C for < 30 seconds (total thermal budget not to exceed 180°C for between 90 to 150
seconds).
DC AND AC PARAMETERS
This section summarizes the operating measure-
ment conditions, and the DC and AC characteris-
tics of the device. The parameters in the DC and
AC characteristics Tables that follow, are derived
from tests performed under the Measurement
Conditions summarized in Table 6, Operating and
AC Measurement Conditions. Designers should
check that the operating conditions in their circuit
match the operating conditions when relying on
the quoted parameters.
Table 6. Operating and AC Measurement Conditions
Parameter
STM690/704/795/
Unit
802/804/805/806
V
/V
Supply Voltage
1.0 to 5.5
–40 to 85
≤ 5
V
°C
ns
V
CC BAT
Ambient Operating Temperature (T )
A
Input Rise and Fall Times
0.2 to 0.8V
Input Pulse Voltages
CC
0.3 to 0.7V
Input and Output Timing Ref. Voltages
V
CC
21/31
STM690/704/795/802/804/805/806
Figure 34. E to E
Propagation Delay Test Circuit
CON
VCC
VCC
VBAT
3.6V
STM690/704/
795/802/804/
805/806
25Ω Equivalent
Source Impedance
E
ECON
50Ω
50Ω Cable
50Ω
(1)
50pF CL
GND
AI08854
Note: 1. C includes load capacitance and scope probe capacitance.
L
Figure 35. AC Testing Input/Output Waveforms
0.8V
CC
0.7V
CC
0.3V
CC
0.2V
CC
AI02568
Figure 36. MR Timing Waveform
MR
tMLRL
RST (1)
trec
tMLMH
AI07837a
Note: 1. RST for STM805.
22/31
STM690/704/795/802/804/805/806
Figure 37. Watchdog Timing
VCC
trec
RST
tWD
WDI
AI07891
Table 7. DC and AC Characteristics
Alter-
(1)
Sym
Description
Min
Typ
Max
Unit
Test Condition
native
V
,
CC
(2)
(3)
T = –40 to +85°C
A
Operating Voltage
5.5
V
1.1
V
BAT
Excluding I
Excluding I
(V < 5.5V)
CC
40
35
60
50
µA
µA
OUT
V
V
Supply Current
CC
(V < 3.6V)
CC
OUT
I
CC
Excluding I
OUT
= 2.3V,
Supply Current in
CC
(V
25
35
µA
BAT
Battery Back-up Mode
V
CC
= 2.0V, MR = V
)
CC
Excluding I
V
Supply Current in
OUT
BAT
(4)
0.4
1.0
µA
V
I
BAT
(V
BAT
= 3.6V)
Battery Back-up Mode
V
0.03
–
V
–
CC
CC
(5)
I
= 5mA
OUT1
0.015
V
0.3
–
V
0.15
–
CC
CC
I
= 75mA
V
OUT1
V
V
V
Voltage (Active)
Voltage (Battery
OUT1
OUT
I
= 250µA,
OUT1
V
CC
–
V
–
CC
V
(5)
0.0015
0.0006
V
> 2.5V
CC
V
BAT
–
V
BAT
–
I
= 250µA, V
= 1mA, V
= 2.3V
BAT
V
V
OUT2
0.1
0.034
OUT
V
OUT2
Back-up)
V
BAT
–
I
= 2.3V
BAT
OUT2
0.14
V
to V
On-resistance
3
4
Ω
Ω
CC
OUT
V
to V
On-resistance
100
BAT
OUT
STM704/806 only;
Input Leakage Current (MR)
20
75
2
350
µA
MR = 0V; V = 3V
CC
I
LI
0V = V = V
Input Leakage Current (PFI)
Input Leakage Current (WDI)
–25
–1
+25
+1
nA
µA
IN
CC
CC
0V = V = V
IN
STM804/805/795;
I
LO
Output Leakage Current
–1
+1
µA
(6)
0V = V = V
IN
CC
V
V
RST
V
RST
(max) < V < 5.5V
0.7V
CC
Input High Voltage (MR, WDI)
Input Low Voltage (MR, WDI)
V
V
IH
CC
V
(max) < V < 5.5V
0.3V
CC
IL
CC
23/31
STM690/704/795/802/804/805/806
Alter-
native
(1)
Sym
Description
Min
Typ
Max
Unit
V
Test Condition
V
= V
(max),
= 3.2mA
Output Low Voltage (PFO,
RST, RST, Vccsw)
CC
RST
0.3
I
SINK
V
OL
OL
V
= V
(max),
= 1.6mA, E = 0V
CC
RST
Output Low Voltage (E
)
0.2V
CC
V
CON
I
OUT
I
= 40µA; V = 1.0V;
CC
OL
V
= V
;
CC
0.3
0.3
V
BAT
T = 0°C to 85°C
A
V
Output Low Voltage (RST)
Output High Voltage (RST,
I
OL
= 200µA;
V
V
V
V
V
V
= 1.2V; V
= V
CC
BAT
CC
I
= 1mA,
(max)
SOURCE
2.4
(7)
V
= V
RST)
CC
RST
V
= V
(max),
CC
RST
V
OH
Output High Voltage (E
)
0.8V
CON
CC
I
= 1.6mA, E = V
OUT
CC
I
= 75µA,
SOURCE
0.8V
0.8V
Output High Voltage (PFO)
CC
V
= V
(max)
CC
RST
V
OH
Battery Back-up (E
Vccsw, RST)
,
CON
V
OHB
I
= 100µA,
SOURCE
BAT
Power-fail Comparator (NOT available on STM795)
STM802/
804/806
1.212
1.187
1.237
1.262
V
PFI Falling
(V < 3.6V)
V
PFI
PFI Input Threshold
CC
STM690/
704/805
1.237
10
1.287
20
V
PFI Rising (V < 3.6V)
PFI Hysteresis
mV
µs
CC
PFI to PFO Propagation
Delay
t
2
PFD
PFO Output Short to
GND Current
I
V
= 3.6V, PFO = 0V
CC
0.1
0.75
2.0
mA
SC
Battery Switchover
V
BAT
V
BAT
V
BAT
V
BAT
> V
< V
> V
< V
V
V
V
SW
SW
SW
SW
SW
Power-down
Power-up
V
BAT
Battery Back-up
(8,9)
Switchover Voltage
V
SW
V
V
SO
V
BAT
V
V
2.4
40
V
SW
Hysteresis
mV
24/31
STM690/704/795/802/804/805/806
Alter-
native
(1)
Sym
Description
Min
Typ
Max
Unit
Test Condition
Reset Thresholds
STM690T/
704T/795T/
805T
V
Falling
Rising
Falling
Rising
Falling
Rising
3.00
3.00
3.075
3.085
3.15
3.17
V
V
CC
V
V
CC
3.00
3.00
2.85
3.075
3.085
2.925
3.12
3.14
3.00
V
V
V
CC
STM802T/
804T/806T
V
CC
CC
STM690S/
704S/795S/
805S
V
V
V
2.85
2.88
2.88
2.55
2.55
2.59
2.59
140
2.935
2.925
2.935
2.625
2.635
2.625
2.635
200
3.02
3.00
3.02
2.70
2.72
2.70
2.72
280
V
V
CC
(10)
Reset Threshold
V
RST
Falling
Rising
Falling
CC
STM802S/
804S/806S
V
V
CC
STM690R/
704R/795R/
805R
V
CC
V
V
Rising
V
CC
V
CC
Falling
Rising
V
STM802R/
804R/806R
V
V
CC
t
V
CC
< 3.6V
RST Pulse Width
ms
rec
Push-button Reset Input (STM704/806)
t
t
MR
MR Pulse Width
100
20
60
ns
ns
MLMH
t
t
MRD
MR to RST Output Delay
500
MLRL
Watchdog Timer (NOT available on STM704/795/806)
t
V
(max) < V < 3.6V
Watchdog Timeout Period
WDI Pulse Width
1.12
100
1.60
20
2.24
s
WD
RST
RST
CC
V
(max) < V < 3.6V
ns
CC
Chip-Enable Gating (STM795 only)
E-to-E Resistance
V
V
= V
= V
(max)
(max)
46
2
Ω
CON
CC
CC
RST
E-to-E
Propagation Delay
7
ns
µs
CON
RST
Reset-to-E
High Delay
10
CON
V
CC
= 3.6V, Disable Mode,
I
E
CON
Short Circuit Current
0.1
0.75
2.0
mA
SC
E
CON
= 0V
Note: 1. Valid for Ambient Operating Temperature: T = –40 to 85°C; V = V
(max) to 5.5V; and V
= 2.8V (except where noted).
BAT
A
CC
RST
2. V supply current, logic input leakage, Watchdog functionality, Push-button Reset functionality, PFI functionality, state of RST and
CC
RST tested at V
= 3.6V, and V = 5.5V. The state of RST or RST and PFO is tested at V = V (min). Either V or V
BAT
CC CC CC CC BAT
can go to 0V if the other is greater than 2.0V.
3. V (min) = 1.0V for T = 0°C to +85°C.
CC
A
4. Tested at V
= 3.6V, V = 3.5V and 0V.
BAT
CC
5. Guaranteed by design.
6. The leakage current measured on the RST pin (STM804/805) or RST pin (STM795) is tested with the reset output not asserted
(output high impedance).
7. Not valid for STM795/804/805 (open drain).
8. When V
9. When V
> V > V , V
remains connected to V until V drops below V
.
SW
BAT
CC
SW
OUT
CC
CC
> V > V
, V
BAT
remains connected to V until V drops below the battery voltage (V
) – 75mV.
BAT
SW
CC
OUT
CC
CC
10. The reset threshold tolerance is wider for V rising than for V falling due to the 10mV (typ) hysteresis, which prevents internal
CC
CC
oscillation.
25/31
STM690/704/795/802/804/805/806
PACKAGE MECHANICAL
Figure 38. SO8 – 8-lead Plastic Small Outline, 150 mils body width, Package Mech. Drawing
h x 45˚
A2
A
C
B
ddd
e
D
8
1
E
H
A1
α
L
SO-A
Note: Drawing is not to scale.
Table 8. SO8 – 8-lead Plastic Small Outline, 150 mils body width, Package Mechanical Data
mm
Min
1.35
0.10
0.33
0.19
4.80
–
inches
Min
Symb
Typ
–
Max
1.75
0.25
0.51
0.25
5.00
0.10
4.00
–
Typ
Max
0.069
0.010
0.020
0.010
0.197
0.004
0.157
–
A
A1
B
–
0.053
0.004
0.013
0.007
0.189
–
–
–
–
–
C
–
–
D
–
–
ddd
E
–
–
–
3.80
–
–
0.150
–
e
1.27
–
0.050
H
5.80
0.25
0.40
0°
6.20
0.50
0.90
8°
–
–
–
–
0.228
0.010
0.016
0°
0.244
0.020
0.035
8°
h
–
L
–
α
–
N
8
8
26/31
STM690/704/795/802/804/805/806
Figure 39. TSSOP8 – 8-lead, Thin Shrink Small Outline, 3x3mm body size, Outline
D
8
1
5
4
c
E1
E
α
A1
L
A
A2
L1
CP
b
e
TSSOP8BM
Note: Drawing is not to scale.
Table 9. TSSOP8 – 8-lead, Thin Shrink Small Outline, 3x3mm body size, Mechanical Data
mm
Min
–
inches
Min
–
Symb
Typ
–
Max
1.10
0.15
0.95
0.40
0.23
0.10
3.10
–
Typ
–
Max
0.043
0.006
0.037
0.016
0.009
0.004
0.122
–
A
A1
A2
b
–
0.05
0.75
0.25
0.13
–
–
0.002
0.030
0.010
0.005
–
0.85
–
0.034
–
c
–
–
CP
D
–
–
3.00
0.65
4.90
3.00
0.55
0.95
–
2.90
–
0.118
0.026
0.193
0.118
0.022
0.037
–
0.114
–
e
E
4.65
2.90
0.40
–
5.15
3.10
0.70
–
0.183
0.114
0.016
–
0.203
0.122
0.030
–
E1
L
L1
α
0°
6°
0°
6°
N
8
8
27/31
STM690/704/795/802/804/805/806
PART NUMBERING
Table 10. Ordering Information Scheme
Example:
STM690
T
M
6
E
Device Type
STM690/704/795/802/804/805/806
Reset Threshold Voltage
T = STM690/704/795/805 = V
= 3.00V to 3.15V
RST
STM802/804/806 = V
= 3.00V to 3.12V
RST
S = STM690/704/795/805 = V
= 2.85V to 3.00V
RST
STM802/804/806 = V
= 2.88V to 3.00V
RST
R = STM690/704/795/805 = V
= 2.55V to 2.70V
RST
STM802/804/806 = V
= 2.59V to 2.70V
RST
Package
M = SO8
(1)
DS = TSSOP8
Temperature Range
6 = –40 to 85°C
Shipping Method
®
E = Tubes (Pb-Free - ECO PACK )
®
F = Tape & Reel (Pb-Free - ECO PACK )
Note: 1. Contact local ST sales office for availability.
For other options, or for more information on any aspect of this device, please contact the ST Sales Office
nearest you.
28/31
STM690/704/795/802/804/805/806
Table 11. Marking Description
Part Number
Reset Threshold
Package
Topside Marking
SO8
TSSOP8
SO8
STM690T
3.075
2.925
2.625
3.075
2.925
2.625
3.075
2.925
2.625
3.075
2.925
2.625
3.075
2.925
2.625
3.075
2.925
2.625
3.075
2.925
2.625
690T
STM690S
STM690R
STM704T
STM704S
STM704R
STM795T
STM795S
STM795R
STM802T
STM802S
STM802R
STM804T
STM804S
STM804R
STM805T
STM805S
STM805R
STM806T
STM806S
STM806R
690S
690R
704T
704S
704R
795T
795S
795R
802T
802S
802R
804T
804S
804R
805T
805S
805R
806T
806S
806R
TSSOP8
SO8
TSSOP8
SO8
TSSOP8
SO8
TSSOP8
SO8
TSSOP8
SO8
TSSOP8
SO8
TSSOP8
SO8
TSSOP8
SO8
TSSOP8
SO8
TSSOP8
SO8
TSSOP8
SO8
TSSOP8
SO8
TSSOP8
SO8
TSSOP8
SO8
TSSOP8
SO8
TSSOP8
SO8
TSSOP8
SO8
TSSOP8
SO8
TSSOP8
SO8
TSSOP8
29/31
STM690/704/795/802/804/805/806
REVISION HISTORY
Table 12. Document Revision History
Date
Version
Revision Details
October 31, 2003
1.0
First Issue
Reformatted; update characteristics (Figure 1, 3, 4, 11, 13, 14, 36; Table 1, 3, 4, 7,
9, 11)
22-Dec-03
16-Jan-04
2.0
2.1
Add Typical Operating Characteristics (Figure 16, 17, 18, 19, 20, 21, 22, 23, 24, 25,
26, 27, 28, 29, 30, 31, 32, 33)
07-Apr-04
25-May-04
2.2
3.0
Update characteristics (Figure 13, 25, 26, 27, 28, 31; Table 1, 3, 7)
Update characteristics (Table 3, 7)
Update package availability, pin description; promote document (Figure 1, 14;
Table 3, 10)
02-Jul-04
4.0
5.0
Clarify root part numbers, pin descriptions, update characteristics (Figure 2, 3, 4, 5,
6, 7, 8, 9, 10, 11, 13, 14, 34; Table 1, 3, 6, 7, 10)
29-Sep-04
30/31
STM690/704/795/802/804/805/806
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
The ST logo is a registered trademark of STMicroelectronics.
All other names are the property of their respective owners
© 2004 STMicroelectronics - All rights reserved
STMicroelectronics group of companies
Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan -
Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America
www.st.com
31/31
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