STM819MDS6F [STMICROELECTRONICS]
5 V supervisor with battery switchover; 5 V主管与电池切换
| 型号： | STM819MDS6F |
| 厂家： | 
ST |
| 描述： | 5 V supervisor with battery switchover |
| 文件： | 总43页 (文件大小：1146K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
STM690A, STM692A, STM703
STM704, STM802, STM805, STM817/8/9
5 V supervisor with battery switchover
Features
■ 5 V operating voltage
■ NVRAM supervisor for external LPSRAM
8
■ Chip-enable gating (STM818 only) for external
LPSRAM (7 ns max prop delay)
1
■ RST and RST outputs
■ 200 ms (typ) t
rec
■ Watchdog timer - 1.6 sec (typ)
SO8 (M)
■ Automatic battery switchover
■ Low battery supply current - 0.4 µA (typ)
■ Power-fail comparator (PFI/PFO)
■ Low supply current - 40 µA (typ)
■ Guaranteed RST (RST) assertion down to
V
= 1.0 V
CC
■ Operating temperature:
TSSOP8 3 x 3 (DS)(1)
–40 °C to +85 °C (industrial grade)
■ RoHS compliance
– Lead-free components are compliant with
the RoHS directive
1. Contact local ST sales office for availability.
Table 1.
Device summary
Manual Battery
Chip-
enable
gating
Battery
freshness
seal
Watchdog Active-low Active-
Power-fail
comparator
Part number
reset
switch-
over
input
RST(1)
high RST
input(1)
STM690A
STM692A
STM703
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
STM704
STM802L/M
STM805L
✓
✓
✓
✓
✓
STM817L/M
STM818L/M
STM819L/M
✓
✓
✓
✓
✓
✓
✓
✓
✓
1. All RST and RST outputs are push-pull.
August 2010
Doc ID 10522 Rev 10
1/43
www.st.com
1
Contents
STM690A/692A/703/704/802/805/817/818/819
Contents
1
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.1
Pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
1.1.1
1.1.2
1.1.3
1.1.4
1.1.5
1.1.6
1.1.7
1.1.8
1.1.9
MR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
WDI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
RST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
RST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
V
V
OUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
BAT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
E
CON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
PFI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
1.1.10 PFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
Reset output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Push-button reset input (STM703/704/819) . . . . . . . . . . . . . . . . . . . . . . . 13
Watchdog input (NOT available on STM703/704/819) . . . . . . . . . . . . . . . 13
Backup battery switchover . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Chip-enable gating (STM818 only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Chip-enable input (STM818 only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Chip-enable output (STM818 only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Power-fail input/output (NOT available on STM818) . . . . . . . . . . . . . . . . 16
Applications information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.10 Using a SuperCap™ as a backup power source . . . . . . . . . . . . . . . . . . . 17
2.11 Negative-going VCC transients . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.12 Battery freshness seal (STM817/818/819) . . . . . . . . . . . . . . . . . . . . . . . . 19
3
4
5
Typical operating characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
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Contents
6
7
8
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
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List of tables
STM690A/692A/703/704/802/805/817/818/819
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Device summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
I/O status in battery backup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Operating and AC measurement conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
DC and AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
SO8 - 8-lead plastic small outline, 150 mils body width, package mechanical data. . . . . . 38
TSSOP8 - 8-lead, thin shrink small outline, 3 x 3 mm body size, mechanical data . . . . . . 39
Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Marking description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
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List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Logic diagram (STM690A/692/802/805/817) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Logic diagram (STM703/704/819) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Logic diagram (STM818) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
STM690A/692A/802/805/817 connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
STM703/704/819 connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
STM818 connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Block diagram (STM690A/692A/802/805/817) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Block diagram (STM703/704/819) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Block diagram (STM818) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 10. Hardware hookup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 11. Chip-enable gating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 12. Chip-enable waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 13. Power-fail comparator waveform (STM817/818/819) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 14. Power-fail comparator waveform (STM690A/692A/703/704/802/805) . . . . . . . . . . . . . . . . 17
Figure 15. Using a SuperCap™. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 16. Freshness seal enable waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 17.
Figure 18.
V
V
to V
on-resistance vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
on-resistance vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
OUT
CC
OUT
to V
BAT
Figure 19. Supply current vs. temperature (no load) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 20. Battery current vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 21.
Figure 22. Reset comparator propagation delay vs. temperature (other than STM817/818/819) . . . . 22
Figure 23. Reset comparator propagation delay vs. temperature (V = 3.0 V; STM817/818/819) . 23
V
threshold vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
PFI
BAT
Figure 24. Power-up t
vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
REC
Figure 25. Normalized reset threshold vs. temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 26. Watchdog time-out period vs. temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 27. E to E
on-resistance vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
CON
Figure 28. PFI to PFO propagation delay vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 29. Output voltage vs. load current (V = 5 V; V
= 2.8 V; T = 25 °C) . . . . . . . . . . . . . . . 26
CC
BAT
A
Figure 30. Output voltage vs. load current (V = 0 V; V
= 2.8 V; T = 25 °C) . . . . . . . . . . . . . . . 26
A
CC
BAT
Figure 31. RST output voltage vs. supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 32. RST output voltage vs. supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 33. RST response time (assertion) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 34. RST response time (assertion) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 35. Power-fail comparator response time (assertion) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 36. Power-fail comparator response time (de-assertion) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
Figure 37. Maximum transient duration vs. reset threshold overdrive . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 38. E to E
Figure 39. E to E
propagation delay vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
propagation delay test circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
CON
CON
Figure 40. AC testing input/output waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 41. MR timing waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 42. Watchdog timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 43. SO8 - 8-lead plastic small outline, 150 mils body width, package mechanical drawing . . . 38
Figure 44. TSSOP8 - 8-lead, thin shrink small outline, 3 x 3 mm body size, outline . . . . . . . . . . . . . . 39
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Description
STM690A/692A/703/704/802/805/817/818/819
1
Description
The STM690A/692A/703/704/802/805/817/818/819 supervisors are self-contained devices
which provide microprocessor supervisory functions with the ability to non-volatize and
write-protect external LPSRAM. A precision voltage reference and comparator monitors the
V
CC input for an out-of-tolerance condition. When an invalid V condition occurs, the reset
CC
output (RST) is forced low (or high in the case of RST). These devices also offer a watchdog
timer (except for STM703/704/819) as well as a power-fail comparator (except for STM818)
to provide the system with an early warning of impending power failure.
These devices are available in a standard 8-pin SOIC package or a space-saving 8-pin
TSSOP package.
Figure 1.
Logic diagram (STM690A/692/802/805/817)
V
V
BAT
CC
V
OUT
WDI
PFI
STM690A/
692A/802/
805/817
(1)
RST(RST)
PFO
V
SS
AI07894
1. For STM805, reset output is active-high.
Figure 2. Logic diagram (STM703/704/819)
V
V
BAT
CC
V
OUT
MR
PFI
STM703/
704/819
RST
PFO
V
SS
AI07895
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Description
Figure 3.
Logic diagram (STM818)
V
V
BAT
CC
V
OUT
WDI
E
RST
STM818
E
CON
V
SS
AI07896
Table 2.
Signal names
MR
WDI
RST
RST
E(1)
Push-button reset input
Watchdog input
Active-low reset output
Active-high reset outpu
Chip-enable input
(1)
ECON
VOUT
VCC
Conditioned chip-enable output
Supply voltage output
Supply voltage
VBAT
PFI
Backup supply voltage
Power-fail input
PFO
VSS
Power-fail output
Ground
1. STM818
Figure 4.
STM690A/692A/802/805/817 connections
SO8/TSSOP8
V
V
BAT
OUT
1
2
3
4
8
7
6
5
(1)
V
RST(RST)
WDI
CC
V
SS
PFI
PFO
AI07889
1. For STM805, reset output is active-high.
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Description
STM690A/692A/703/704/802/805/817/818/819
Figure 5.
STM703/704/819 connections
SO8/TSSOP8
V
V
BAT
OUT
1
2
3
4
8
7
6
5
V
RST
MR
CC
V
SS
PFI
PFO
AI07890
Figure 6.
STM818 connections
SO8/TSSOP8
V
V
BAT
OUT
1
2
3
4
8
7
6
5
V
CC
RST
WDI
E
V
SS
E
CON
AI07892
1.1
Pin descriptions
1.1.1
MR
A logic low on MR asserts the reset output. Reset remains asserted as long as MR is low
and for t after MR returns high. This active-low input has an internal pull-up. It can be
rec
driven from a TTL or CMOS logic line, or shorted to ground with a switch. Leave open if
unused.
1.1.2
WDI
If WDI remains high or low for 1.6 sec, the internal watchdog timer runs out and reset is
triggered. The internal watchdog timer clears while reset is asserted or when WDI sees a
rising or falling edge.
The watchdog function can be disabled by allowing the WDI pin to float.
1.1.3
1.1.4
RST
Pulses low for trec when triggered, and stays low whenever V is below the reset threshold
or when MR is a logic low. It remains low for t after either V rises above the reset
threshold, the watchdog triggers a reset, or MR goes from low to high.
CC
rec
CC
RST
Pulses high for t when triggered, and stays high whenever V is above the reset
rec
CC
threshold or when MR is a logic high. It remains high for t after either V falls below the
rec
CC
reset threshold, the watchdog triggers a reset, or MR goes from high to low.
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STM690A/692A/703/704/802/805/817/818/819
Description
1.1.5
V
OUT
When V is above the switchover voltage (V ), V
is connected to V through a P-
CC
SO
OUT
CC
channel MOSFET switch. When V falls below V , V
connects to V
.
CC
SO BAT
OUT
1.1.6
V
BAT
When V falls below V , V
switches from V to V . When V rises above V +
SO
CC
SO OUT
CC
BAT
CC
hysteresis, VOUT reconnects to V . V
may exceed V . Connect to V if no battery is
CC BAT
CC CC
used.
1.1.7
1.1.8
E
The input to the chip-enable gating circuit. Connect to ground if unused.
E
CON
goes low only when E is low and reset is not asserted. If E
E
is low when reset is
CON
CON
asserted, E
will remain low for 15 µs or until E goes high, whichever occurs first. In the
CON
disabled mode, E
is pulled up to V
.
CON
OUT
1.1.9
PFI
When PFI is less than V
or when V falls below 2.4 V (or V ), PFO goes low;
CC SO
PFI
otherwise, PFO remains high. Connect to ground if unused.
1.1.10
PFO
When PFI is less than V , or V falls below 2.4 V (or V ), PFO goes low; otherwise,
PFI
CC
SO
PFO remains high. Leave open if unused. Output type is push-pull.
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Description
Table 3.
STM690A/692A/703/704/802/805/817/818/819
Pin description
Pin
STM690A
STM692A
STM802
STM817
STM703
STM704
STM819
Name
Function
STM818
STM805
-
-
6
7
-
6
-
-
6
-
MR
WDI
RST
RST
Push-button reset input
Watchdog input
6
7
-
7
-
Active-low reset output
Active-high reset output
7
1
2
8
-
1
2
8
4
5
-
1
2
8
-
1
2
8
-
VOUT Supply output for external LPSRAM
VCC
VBAT
E
Supply voltage
Backup battery input
Chip-enable input
-
-
-
ECON Conditioned chip-enable output
4
5
3
4
5
3
4
5
3
PFI
PFO
VSS
Power-fail input
-
Power-fail output (push-pull)
Ground
3
Figure 7.
Block diagram (STM690A/692A/802/805/817)
VCC
VOUT
VBAT
VSO
COMPARE
COMPARE
VRST
trec
Generator
RST(RST)(1)
WATCHDOG
TIMER
WDI
PFI
VPFI
COMPARE
PFO
AI07897
1. For STM805, reset output is active-high.
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STM690A/692A/703/704/802/805/817/818/819
Figure 8. Block diagram (STM703/704/819)
Description
VCC
VOUT
VBAT
VSO
COMPARE
COMPARE
VRST
trec
Generator
RST
MR
PFI
VPFI
COMPARE
PFO
AI07898
Figure 9.
Block diagram (STM818)
VCC
VOUT
VBAT
VSO
COMPARE
COMPARE
VRST
trec
Generator
WATCHDOG
TIMER
RST
WDI
E
CON OUTPUT
CONTROL
E
ECON
AI07899a
Doc ID 10522 Rev 10
11/43
Description
STM690A/692A/703/704/802/805/817/818/819
Figure 10. Hardware hookup
Regulator
VIN VCC
Unregulated
Voltage
VCC
VCC
LPSRAM
VCC
VOUT
STM690A/692A/
703/704/802/805/
817/818/819
0.1 F
E
E
0.1 F
WDI(1)
From Microprocessor
E(2)
(2)
ECON
R1
R2
PFI(3)
MR(4)
VBAT
PFO(3)
RST(5)
To Microprocessor NMI
To Microprocessor Reset
Push-Button
AI07893
1. For STM690A/692A/802/805/817/818.
2. For STM818 only.
3. Not available on STM818.
4. For STM703/704/819.
5. Active high on STM805.
12/43
Doc ID 10522 Rev 10
STM690A/692A/703/704/802/805/817/818/819
Operation
2
Operation
2.1
Reset output
The STM690A/692A/703/704/802/805/817/818/819 Supervisor asserts a reset signal to the
MCU whenever V goes below the reset threshold (V , a watchdog time-out occurs, or
CC
RST)
when the Push-button Reset Input (MR) is taken low. RST is guaranteed to be a logic low
(logic high for STM805) for 0V < V < V if VBAT is greater than 1 V. Without a backup
CC
RST
battery, RST is guaranteed valid down to V =1 V.
CC
During power-up, once V exceeds the reset threshold an internal timer keeps RST low for
CC
the reset time-out period, t . After this interval RST returns high.
rec
If V drops below the reset threshold, RST goes low. Each time RST is asserted, it stays
CC
low for at least the reset time-out period (t ). Any time V goes below the reset threshold
rec
CC
the internal timer clears. The reset timer starts when V returns above the reset threshold.
CC
2.2
Push-button reset input (STM703/704/819)
A logic low on MR asserts reset. Reset remains asserted while MR is low, and for t (see
rec
Figure 41) after it returns high. The MR input has an internal 40 kΩ pull-up resistor, allowing
it to be left open if not used. This input can be driven with TTL/CMOS-logic levels or with
open-drain/collector outputs. Connect a normally open momentary switch from MR to GND
to create a manual reset function; external debounce circuitry is not required. If MR is driven
from long cables or the device is used in a noisy environment, connect a 0.1 µF capacitor
from MR to GND to provide additional noise immunity. MR may float, or be tied to V when
CC
not used.
2.3
Watchdog input (NOT available on STM703/704/819)
The watchdog timer can be used to detect an out-of-control MCU. If the MCU does not
toggle the Watchdog Input (WDI) within t (1.6 sec typ), the reset is asserted. The internal
WD
watchdog timer is cleared by either:
1. a reset pulse, or
2. by toggling WDI (high-to-low or low-to-high), which can detect pulses as short as 50ns.
If WDI is tied high or low, a reset pulse is triggered every 1.8 sec (t
+ t ).
WD
rec
The timer remains cleared and does not count for as long as reset is asserted. As soon as
reset is released, the timer starts counting (see Figure 42).
Note:
1
2
The watchdog function may be disabled by floating WDI or tri-stating the driver connected to
WDI. When tri-stated or disconnected, the maximum allowable leakage current is 10 µA and
the maximum allowable load capacitance is 200 pF.
Input pulses less than 20 ns will be ignored.
Doc ID 10522 Rev 10
13/43
Operation
STM690A/692A/703/704/802/805/817/818/819
2.4
Backup battery switchover
In the event of a power failure, it may be necessary to preserve the contents of external
SRAM through V . With a backup battery installed with voltage V , the devices
OUT
BAT
automatically switch the SRAM to the backup supply when V falls.
CC
Note:
When the battery is first connected without V power applied, the device does not
CC
immediately provide backup battery voltage on V
. Only after V exceeds V
will the
OUT
CC
RST
switchover operate as described below. This mode allows a battery to be attached during
manufacturing but not used until after the system has been activated for the first time. As a
result, no battery power is consumed by the device during storage and shipment. For the
STM81x devices, the battery freshness seal can be initiated again by following the
procedure outlined in Section 2.12. If the backup battery is not used, connect both V
and
BAT
V
to V
.
OUT
CC
Whenever V falls below the switchover voltage, V , V
is connected to V
through a
BAT
CC
SO OUT
100 Ω switch. V is the lesser of V
and V . Choosing the lesser allows the device to
be powered by V for as long as possible before switching over thereby maximizing the
SO
BAT
RST
CC
battery life.
Assuming V
> 2.0 V, switchover at V ensures that battery backup mode is entered
SO
BAT
before V
gets too close to the 2.0 V minimum required to reliably retain data in most
OUT
external SRAMs. When V recovers, hysteresis is used to avoid oscillation around the V
CC
SO
point. V
is connected to V through a 3 Ω PMOS power switch.
OUT
CC
Note:
The backup battery may be removed while V is valid, assuming V
is adequately
BAT
CC
decoupled (0.1 µF typ), without danger of triggering a reset.
Table 4.
I/O status in battery backup
VOUT Connected to VBAT through internal switch
VCC
PFI
Disconnected from VOUT
Disabled
PFO
E
Logic low
High impedance
Logic high
ECON
WDI
MR
Watchdog timer is disabled
Disabled
RST
RST
VBAT
Logic low
Logic high
Connected to VOUT
14/43
Doc ID 10522 Rev 10
STM690A/692A/703/704/802/805/817/818/819
Operation
2.5
Chip-enable gating (STM818 only)
Internal gating of the chip-enable (E) signal prevents erroneous data from corrupting the
external CMOS RAM in the event of an undervoltage condition. The STM818 uses a series
transmission gate from E to E (see Figure 11). During normal operation (reset not
CON
asserted), the E transmission gate is enabled and passes all E transitions. When reset is
asserted, this path becomes disabled, preventing erroneous data from corrupting the CMOS
RAM. The short propagation delay from E to E
enables the STM818 to be used with
CON
most µPs. If E is low when reset asserts, E
remains low for typically 15 µs (or until E
CON
goes high) to permit the current WRITE cycle to complete. Connect E to V if unused.
SS
2.6
Chip-enable input (STM818 only)
The chip-enable transmission gate is disabled and E is high impedance (disabled mode)
while reset is asserted. During a power-down sequence when V passes the reset
CC
threshold, the chip-enable transmission gate disables and E immediately becomes high
impedance if the voltage at E is high. If E is low when reset asserts, the chip-enable
transmission gate will disable 15 µs after reset asserts (see Figure 12). This permits the
current WRITE cycle to complete during power-down.
Any time a reset is generated, the chip-enable transmission gate remains disabled and E
remains high impedance (regardless of E activity) for the reset time-out period. When the
chip-enable transmission gate is enabled, the impedance of E appears as a 40 Ω resistor in
series with the load at E
. The propagation delay through the chip-enable transmission
CON
gate depends on V , the source impedance of the drive connected to E, and the loading
CC
on E
. The chip-enable propagation delay is production tested from the 50% point on E to
CON
the 50% point on E
For minimum propagation delay, minimize the capacitive load at E
impedance driver.
using a 50 Ω driver and a 50 pF load capacitance (see Figure 39).
CON
and use a low-output
CON
2.7
Chip-enable output (STM818 only)
When the chip-enable transmission gate is enabled, the impedance of E
is equivalent to
CON
a 40 Ω resistor in series with the source driving E. In the disabled mode, the transmission
gate is off and an active pull-up connects E
off when the transmission gate is enabled.
to V
(see Figure 11). This pull-up turns
CON
OUT
Figure 11. Chip-enable gating
VCC
trec
Generator
RST
COMPARE
E
VRST
VOUT
CON OUTPUT
CONTROL
E
ECON
AI08802
Doc ID 10522 Rev 10
15/43
Operation
STM690A/692A/703/704/802/805/817/818/819
Figure 12. Chip-enable waveform
VCC
VRST
VBAT
ECON
t
t
rec
rec
15µs
RST
E
X X
XX
AI08803b
2.8
Power-fail input/output (NOT available on STM818)
The Power-fail Input (PFI) is compared to an internal reference voltage (independent from
the V
comparator). If PFI is less than the power-fail threshold (V ), the Power-Fail
RST
PFI
Output (PFO) will go low. This function is intended for use as an undervoltage detector to
signal a failing power supply. Typically PFI is connected through an external voltage divider
(see Figure 12) to either the unregulated DC input (if it is available) or the regulated output
of the V regulator. The voltage divider can be set up such that the voltage at PFI falls
CC
below V several milliseconds before the regulated V input to the
PFI
CC
STM690A/692A/703/704/802/805/817/818/819 Supervisor or before the microprocessor
drops below the minimum operating voltage. This provides several milliseconds of advanced
warning that power is about to fail.
During battery backup, the power-fail comparator turns off and PFO goes (or remains) low
(see Figure 13 below and Figure 14). This occurs after V drops below 2.4 V (or V ).
CC
SO
When power returns, PFO is forced high (STM817/819 only), irrespective of V
for the
PFI
WRITE protect time (t ). At the end of this time, the power-fail comparator is enabled and
rec
PFO follows PFI. If the comparator is unused, PFI should be connected to V and PFO left
SS
unconnected. PFO may be connected to MR on the STM703/704/818 so that a low voltage
on PFI will generate a reset output.
2.9
Applications information
These supervisor circuits are not short-circuit protected. Shorting V
to ground -
OUT
excluding power-up transients such as charging a decoupling capacitor - destroys the
device. Decouple both V and V
pins to ground by placing 0.1 µF capacitors as close to
CC
BAT
the device as possible.
16/43
Doc ID 10522 Rev 10
STM690A/692A/703/704/802/805/817/818/819
Operation
Figure 13. Power-fail comparator waveform (STM817/818/819)
VCC
VRST
VSO (or 2.4V)
t
rec
PFO
(STM817/819)
PFO follows PFI
PFO follows PFI
RST to ECON Delay (STM818)
RST
ECON (STM818)
AI08804a
Figure 14. Power-fail comparator waveform (STM690A/692A/703/704/802/805)
VCC
VRST
2.4V (or VSO
PFO
)
t
rec
PFO follows PFI
PFO follows PFI
RST
AI08832a
2.10
Using a SuperCap™ as a backup power source
SuperCaps™ are capacitors with extremely high capacitance values (e.g., 0.47 F) for their
size. Figure 15 shows how to use a SuperCap as a backup power source. The SuperCap
may be connected through a diode to the 5 V supply. Since V
can exceed V while V
BAT
CC CC
is above the reset threshold, there are no special precautions for using these supervisors
with a SuperCap.
Doc ID 10522 Rev 10
17/43
Operation
STM690A/692A/703/704/802/805/817/818/819
2.11
Negative-going VCC transients
The STM690A/692A/703/704/802/805/817/818/819 Supervisors are relatively immune to
negative-going V transients (glitches). Figure 37 shows typical transient duration versus
CC
reset comparator overdrive (for which the STM690A/692A/703/704/802/805/817/818/819
will NOT generate a reset pulse). The graph was generated using a negative pulse applied
to V , starting at V
+ 0.3 V and ending below the reset threshold by the magnitude
CC
RST
indicated (comparator overdrive). The graph indicates the maximum pulse width a negative
transient can have without causing a reset pulse. As the magnitude of the transient
V
CC
increases (further below the threshold), the maximum allowable pulse width decreases. Any
combination of duration and overdrive which lies under the curve will NOT generate a reset
signal. Typically, a V transient that goes 100 mV below the reset threshold and lasts 40 µs
CC
or less will not cause a reset pulse. A 0.1 µF bypass capacitor mounted as close as possible
to the V pin provides additional transient immunity.
CC
18/43
Doc ID 10522 Rev 10
STM690A/692A/703/704/802/805/817/818/819
Operation
2.12
Battery freshness seal (STM817/818/819)
The battery freshness seal disconnects the backup battery from internal circuitry and V
OUT
until it is needed. This allows an OEM to ensure that the backup battery connected to V
BAT
will be fresh when the final product is put to use. To enable the freshness seal:
1. Connect a battery to V
2. Ground PFO
BAT
3. Bring V above the reset threshold and hold it there until reset is deasserted following
CC
the reset timeout period and
4. Bring V down again (Figure 16)
CC
Use the same procedure for the STM818, but ground E
instead of PFO. Once the
CON
battery freshness seal is enabled (disconnecting the backup battery from internal circuitry
and anything connected to V ), it remains enabled until V is brought above V
.
RST
OUT
CC
Figure 15. Using a SuperCap™
5V
V
V
V
OUT
To external SRAM
CC
STMXXX
RST
To µP
BAT
GND
AI08805
Figure 16. Freshness seal enable waveform
VRST
VCC
t
rec
RST
ECON out state latched
at 1/2 trec
,
Freshness
Seal enabled
(Externally held at 0V)
ECON
(STM818)
PFO out state latched
at 1/2 trec
,
Freshness
Seal Enabled
(Externally held at 0V)
PFO
(STM817/819)
AI08806
Doc ID 10522 Rev 10
19/43
Typical operating characteristics
STM690A/692A/703/704/802/805/817/818/819
3
Typical operating characteristics
Note:
Typical values are at T = 25 °C.
A
Figure 17. V to V
on-resistance vs. temperature
CC
OUT
5.0
4.0
3.0
2.0
1.0
V
V
V
= 3.0V
= 4.5V
= 5.5V
CC
CC
CC
0.0
0
20
40
60
80
100
120
–40
–20
Temperature (°C)
AI10498
Figure 18. V
to V
on-resistance vs. temperature
BAT
OUT
160
140
120
100
80
60
V
V
V
V
= 2.0V
BAT
BAT
BAT
BAT
= 3.0V
= 3.3V
= 3.6V
40
20
0
–40
–20
0
20
40
60
80
100
120
Temperature (°C)
AI09140b
20/43
Doc ID 10522 Rev 10
STM690A/692A/703/704/802/805/817/818/819
Typical operating characteristics
Figure 19. Supply current vs. temperature (no load)
30
25
20
15
10
5
V
V
V
V
V
= 2.7V
= 3.0V
= 3.6V
= 4.5V
= 5.5V
CC
CC
CC
CC
CC
0
–40
–20
0
20
40
60
80
100
120
Temperature (°C)
AI09141b
Figure 20. Battery current vs. temperature
1000
100
10
V
V
V
= 2.0V
= 3.0V
= 3.6V
BAT
BAT
BAT
1
0.1
–40
–20
0
20
40
60
80
100
120
Temperature (°C)
AI10499
Doc ID 10522 Rev 10
21/43
Typical operating characteristics
STM690A/692A/703/704/802/805/817/818/819
Figure 21. V
threshold vs. temperature
PFI
1.270
1.265
1.260
1.255
1.250
1.245
1.240
1.235
1.230
1.225
V
V
V
V
= 3.0V
= 4.5V
= 4.75V
= 5.5V
CC
CC
CC
CC
–40
–20
0
20
40
60
80
100
120
Temperature (°C)
AI09142c
Figure 22. Reset comparator propagation delay vs. temperature (other than STM817/818/819)
30
28
26
24
22
20
18
16
14
12
10
–40
–20
0
20
40
60
80
100
120
Temperature (°C)
AI09143b
22/43
Doc ID 10522 Rev 10
STM690A/692A/703/704/802/805/817/818/819
Typical operating characteristics
= 3.0 V; STM817/818/819)
Figure 23. Reset comparator propagation delay vs. temperature (V
BAT
350
300
250
200
150
100
50
1v/ms
10V/ms
0
–40
–20
0
20
40
60
80
100
120
Temperature (°C)
AI11100
Figure 24. Power-up t
vs. temperature
REC
240
235
230
225
220
215
210
V
V
V
= 3.0V
= 4.5V
= 5.5V
CC
CC
CC
–40
–20
0
20
40
60
80
100
120
Temperature (°C)
AI09144b
Doc ID 10522 Rev 10
23/43
Typical operating characteristics
STM690A/692A/703/704/802/805/817/818/819
Figure 25. Normalized reset threshold vs. temperature
1.004
1.002
1.000
0.998
0.996
–40
–20
0
20
40
60
80
100
120
AI09145b
Temperature (°C)
Figure 26. Watchdog time-out period vs. temperature
1.90
1.85
1.80
1.75
1.70
1.65
1.60
V
V
V
= 3.0V
= 4.5V
= 5.5V
CC
CC
CC
–40
–20
0
20
40
60
80
100
120
Temperature (°C)
AI09146b
24/43
Doc ID 10522 Rev 10
STM690A/692A/703/704/802/805/817/818/819
Typical operating characteristics
Figure 27. E to E
on-resistance vs. temperature
CON
60
50
40
30
20
10
0
V
V
V
= 3.0V
= 4.5V
= 5.5V
CC
CC
CC
–40
–20
0
20
40
60
80
100
120
Temperature (°C)
AI09147b
Figure 28. PFI to PFO propagation delay vs. temperature
4.0
V
V
V
V
= 3.0V
= 3.6V
= 4.5V
= 5.5V
CC
CC
CC
CC
3.0
2.0
1.0
0.0
–40
–20
0
20
40
60
80
100
120
Temperature (°C)
AI09148b
Doc ID 10522 Rev 10
25/43
Typical operating characteristics
STM690A/692A/703/704/802/805/817/818/819
Figure 29. Output voltage vs. load current (V = 5 V; V
= 2.8 V; T = 25 °C)
CC
BAT
A
5.00
4.98
4.96
4.94
0
10
20
30
40
50
I
(mA)
AI10496
OUT
Figure 30. Output voltage vs. load current (V = 0 V; V
= 2.8 V; T = 25 °C)
CC
BAT
A
2.80
2.78
2.76
2.74
2.72
2.70
2.68
2.66
0.0
0.2
0.4
0.6
0.8
1.0
I
(mA)
OUT
AI10497
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Doc ID 10522 Rev 10
STM690A/692A/703/704/802/805/817/818/819
Typical operating characteristics
Figure 31. RST output voltage vs. supply voltage
5
5
4
V
V
RST
CC
4
3
2
3
2
1
0
1
0
500ms/div
AI09149b
Figure 32. RST output voltage vs. supply voltage
5
5
4
3
2
1
0
V
V
RST
CC
4
3
2
1
0
500ms/div
AI09150b
Doc ID 10522 Rev 10
27/43
Typical operating characteristics
STM690A/692A/703/704/802/805/817/818/819
Figure 33. RST response time (assertion)
5V
1V/div
4V
V
CC
5V
4V
RST
1V/div
0V
AI09151b
5µs/div
Figure 34. RST response time (assertion)
5V
4V
V
CC
1V/div
4V
RST
1V/div
0V
5µs/div
AI09152b
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STM690A/692A/703/704/802/805/817/818/819
Typical operating characteristics
Figure 35. Power-fail comparator response time (assertion)
5V
1V/div
PFO
0V
1.3V
PFI
500mV/div
0V
AI09153b
500ns/div
Figure 36. Power-fail comparator response time (de-assertion)
5V
1V/div
PFO
0V
1.3V
PFI
500mV/div
0V
AI09154b
500ns/div
Doc ID 10522 Rev 10
29/43
Typical operating characteristics
STM690A/692A/703/704/802/805/817/818/819
Figure 37. Maximum transient duration vs. reset threshold overdrive
6000
5000
4000
Reset occurs
above the curve.
3000
2000
1000
0
0.001
0.01
0.1
1
10
Reset Comparator Overdrive, V
– V (V)
RST
CC
AI09156b
Figure 38. E to E
propagation delay vs. temperature
CON
4.0
3.0
2.0
1.0
V
V
V
= 3.0V
= 4.5V
= 5.5V
CC
CC
CC
0.0
–40
–20
0
20
40
60
80
100
120
Temperature (°C)
AI09157b
30/43
Doc ID 10522 Rev 10
STM690A/692A/703/704/802/805/817/818/819
Maximum ratings
4
Maximum ratings
Stressing the device above the rating listed in the absolute maximum ratings table may
cause permanent damage to the device. These are stress ratings only and operation of the
device at these or any other conditions above those indicated in the operating sections of
this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
Table 5.
Symbol
TSTG
Absolute maximum ratings
Parameter
Value
Unit
Storage temperature (VCC off)
Lead solder temperature for 10 seconds
Input or output voltage
Supply voltage
–55 to 150
260
°C
°C
V
(1)
TSLD
VIO
–0.3 to VCC +0.3
–0.3 to 6.0
20
VCC/VBAT
V
IO
Output current
mA
mW
PD
Power dissipation
320
1. Reflow at peak temperature of 260 °C. The time above 255 °C must not exceed 30 seconds.
Doc ID 10522 Rev 10
31/43
DC and AC parameters
STM690A/692A/703/704/802/805/817/818/819
5
DC and AC parameters
This section summarizes the operating measurement conditions, and the DC and AC
characteristics of the device. The parameters in the DC and AC characteristics Tables that
follow, are derived from tests performed under the measurement conditions summarized in
Table 6: Operating and AC measurement conditions. Designers should check that the
operating conditions in their circuit match the operating conditions when relying on the
quoted parameters.
Table 6.
Operating and AC measurement conditions
STM690A/692A/703/704/802/805/
Parameter
CC/VBAT supply voltage
Unit
817/818/819
V
1.0 to 5.5
–40 to 85
≤ 5
V
°C
ns
V
Ambient operating temperature (TA)
Input rise and fall times
Input pulse voltages
0.2 to 0.8VCC
0.3 to 0.7VCC
Input and output timing ref. voltages
V
Figure 39. E to E
propagation delay test circuit
CON
VCC
VCC
VBAT
3.6V
STMXXX
25 Equivalent
Source Impedance
E
ECON
50
50 Cable
50
(1)
50pF CL
GND
AI08854
1. CL includes load capacitance and scope probe capacitance.
32/43
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STM690A/692A/703/704/802/805/817/818/819
Figure 40. AC testing input/output waveforms
DC and AC parameters
0.8V
0.2V
CC
0.7V
CC
0.3V
CC
CC
AI02568
Figure 41. MR timing waveform
MR
t
MLRL
RST (1)
t
t
rec
MLMH
AI07837a
1. RST for STM805.
Figure 42. Watchdog timing
VCC
t
rec
RST
WDI
t
WD
AI07891
Doc ID 10522 Rev 10
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DC and AC parameters
STM690A/692A/703/704/802/805/817/818/819
Table 7.
Sym
DC and AC characteristics
Alter-
Description
Test condition(1)
Min
Typ
Max Unit
native
VCC
VBAT
,
Operating voltage
VCC supply current
TA = –40 to +85 °C
1.2(3)
5.5
60
35
V
(2)
Excluding IOUT (VCC < 5.5 V)
Excluding IOUT (VBAT = 2.3 V,
25
25
µA
µA
ICC
VCC supply current in
battery backup mode
VCC = 2.0 V, MR = VCC
)
VBAT supply current in
battery backup mode
Excluding IOUT
(VBAT = 3.6 V)
(4)
IBAT
0.4
1.0
µA
V
VCC
0.03
–
IOUT1 = 5 mA(5)
VCC – 0.015
VCC
0.3
–
IOUT1 = 75 mA
VCC – 0.15
V
VOUT1
VOUT voltage (active)
IOUT1 = 250 µA,
VCC > 2.5 V(5)
VCC
0.0015
–
VCC
0.0006
–
V
VBAT
0.1
–
IOUT2 = 250 µA, VBAT = 2.3 V
IOUT2 = 1 mA, VBAT = 2.3 V
V
BAT – 0.034
V
V
Ω
VOUT voltage (battery
backup)
VOUT2
VBAT – 0.14
3
VCC to VOUT
on-resistance
4
V
BAT to VOUT
100
125
2
Ω
on-resistance
Input leakage current
(MR)
4.5 V < VCC < 5.5 V
0 V < VIN < VCC
75
300
µA
nA
Input leakage current
(PFI)
–25
+25
160
ILI
WDI = VCC , time average
WDI = GND, time average
4.5 V < VCC < 5.5 V
120
–15
µA
µA
V
Input leakage current
(WDI)(6)
–20
2.0
VIH
VIH
VIL
VIL
Input high voltage (MR)
Input high voltage (WDI)
Input low voltage (MR)
Input low voltage (WDI)
VRST (max) < VCC < 5.5 V
4.5 V < VCC < 5.5 V
0.7VCC
V
0.8
V
VRST (max) < VCC < 5.5 V
0.3VCC
V
VCC = VRST (max),
ISINK = 3.2 mA
Output low voltage (PFO,
RST, RST)
0.3
0.2VCC
0.3
V
V
V
V
VOL
VCC = VRST (max),
Output low voltage
(ECON
)
IOUT = 1.6 mA, E = 0 V
I
SINK = 50 µA, VCC = 1.0 V,
VBAT = VCC , TA = 0°C to 85°C
VOL
Output low voltage (RST)
I
SINK = 100 µA, VCC = 1.2 V,
BAT = VCC
0.3
V
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Doc ID 10522 Rev 10
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DC and AC parameters
Table 7.
Sym
DC and AC characteristics (continued)
Alter-
native
Description
Test condition(1)
Min
2.4
Typ
Max Unit
ISOURCE = 1 mA
Output high voltage
(RST, RST)
V
V
V
VCC = VRST (max)
VCC = VRST (max),
Output high voltage
VOH
0.8VCC
0.8VCC
(ECON
)
IOUT = 1.6 mA, E= VCC
ISOURCE = 75 µA,
VCC = VRST (max)
Output high voltage
(PFO)
I
SOURCE = 4 µA, VCC = 1.1 V,
0.8
0.9
V
V
V
V
VBAT = VCC , TA = 0°C to 85°C
VOH
Output high voltage
ISOURCE = 4 µA, VCC = 1.2 V,
VBAT = VCC
ISOURCE = 100 µA,
VOH battery backup
(RST, RST)
0.8VBAT
0.8VBAT
VCC = 0, VBAT = 2.8 V
VOHB
ISOURCE = 75 µA,
VOH battery backup
(ECON
)
VCC = 0, VBAT = 2.8 V
Power-fail comparator (NOT available on STM818)
All other
versions
PFI falling
(VCC = 5 V)
1.20
1.25
1.30
V
VPFI
PFI input threshold
STM802
1.225
1.250
2
1.275
V
PFI to PFO propagation
delay
tPFD
ISC
µs
PFO output short to GND
current
VCC = 5 V, VPFO = 0 V
0.1
0.75
2.0
mA
Battery switchover
VRST > VBAT
VRST < VBAT
RST > VBAT
VRST < VBAT
VBAT
VRST
VBAT
VRST
40
V
V
Battery backup
switchover voltage(7)(8)
(VCC < VBAT
Power-down
Power-up
&
VSO
V
V
VCC < VRST
)
V
Hysteresis
mV
Reset thresholds
STM690A/703, STM8XXL
STM692A/704, STM8XXM
4.50
4.25
4.65
4.40
4.75
4.50
V
V
VRST
Reset threshold(9)
Reset threshold
hysteresis
25
mV
µs
VCC to RST delay (from
VRST, VCC falling at
10 V/ms)
STM817/818/819
100
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DC and AC parameters
STM690A/692A/703/704/802/805/817/818/819
Table 7.
Sym
DC and AC characteristics (continued)
Alter-
Description
Test condition(1)
Min
Typ
Max Unit
native
tREC
RST pulse width
140
200
280
ms
Push-button reset input (STM703/704/819)
tMLMH tMR MR pulse width
STM703/704
STM819
150
1
ns
µs
ns
ns
ns
kΩ
STM703/704
STM819
250
tMLMR tMRD MR to RST output delay
120
100
63
MR glitch immunity
MR pull-up resistor
STM819
MR = 0 V, VCC = 5 V
45
85
Watchdog timer (NOT available on STM703/704/819)
tWD Watchdog timeout period
WDI pulse width
VRST (max) < VCC < 5.5 V
1.12
50
1.60
2.24
s
V
RST (max) < VCC < 5.5 V
ns
Chip-enable gating (STM818 only)
E to ECON resistance
VCC = VRST (max)
4.5 V < VCC < 5.5 V
(Power-down)
40
2
150
7
Ω
ns
E to ECON propagation
delay
Reset to ECON high delay
15
µs
V
CC = 5 V, disable mode,
ECON short circuit current
0.1
0.75
2.0
mA
E = logic high, ECON = 0 V
1. Valid for ambient operating temperature: TA = –40 to 85 °C; VCC = 4.75 V to 5.5 V for “L” versions; VCC = 4.5 V to 5.5 V for
“M” versions; and VBAT = 2.8 V (except where noted).
2. VCC supply current, logic input leakage, watchdog functionality, push-button reset functionality, PFI functionality, state of
RST and RST tested at VBAT = 3.6 V, and VCC = 5.5 V. The state of RST or RST and PFO is tested at VCC = VCC (min).
Either VCC or VBAT can go to 0 V if the other is greater than 2.0 V.
3. VCC (min) = 1.0 V for TA = 0 °C to +85 °C.
4. Tested at VBAT = 3.6 V, VCC = 3.5 V and 0 V.
5. Guaranteed by design.
6. WDI input is designed to be driven by a three-state output device. To float WDI, the “high impedance mode” of the output
device must have a maximum leakage current of 10 µA and a maximum output capacitance of 200 pF. The output device
must also be able to source and sink at least 200 µA when active.
7. When VBAT > VCC > VRST, VOUT remains connected to VCC until VCC drops below VRST
.
8. When VRST > VCC > VBAT, VOUT remains connected to VCC until VCC drops below the battery voltage (VBAT) – 75 mV.
9. For VCC falling.
36/43
Doc ID 10522 Rev 10
STM690A/692A/703/704/802/805/817/818/819
Package mechanical data
6
Package mechanical data
In order to meet environmental requirements, ST offers these devices in different grades of
®
®
ECOPACK packages, depending on their level of environmental compliance. ECOPACK
specifications, grade definitions and product status are available at: www.st.com.
®
ECOPACK is an ST trademark.
Doc ID 10522 Rev 10
37/43
Package mechanical data
STM690A/692A/703/704/802/805/817/818/819
Figure 43. SO8 - 8-lead plastic small outline, 150 mils body width, package
mechanical drawing
A2
A
C
B
ddd
e
D
8
1
E
H
A1
L
SO-A
Note:
Drawing is not to scale.
Table 8.
Symbol
SO8 - 8-lead plastic small outline, 150 mils body width, package
mechanical data
mm
Min
inches
Min
Typ
Max
Typ
Max
A
A1
B
-
1.35
0.10
0.33
0.19
4.80
-
1.75
0.25
0.51
0.25
5.00
0.10
4.00
-
-
0.053
0.004
0.013
0.007
0.189
-
0.069
0.010
0.020
0.010
0.197
0.004
0.157
-
-
-
-
-
C
-
-
D
-
-
ddd
E
-
-
-
3.80
-
-
0.150
-
e
1.27
0.050
H
-
-
-
-
5.80
0.25
0.40
0°
6.20
0.50
0.90
8°
-
-
-
-
0.228
0.010
0.016
0°
0.244
0.020
0.035
8°
h
L
α
N
8
8
38/43
Doc ID 10522 Rev 10
STM690A/692A/703/704/802/805/817/818/819
Package mechanical data
Figure 44. TSSOP8 - 8-lead, thin shrink small outline, 3 x 3 mm body size, outline
D
8
1
5
4
c
E1
E
A1
L
A
A2
L1
CP
b
e
TSSOP8BM
Note:
Drawing is not to scale.
Table 9.
Symbol
TSSOP8 - 8-lead, thin shrink small outline, 3 x 3 mm body size,
mechanical data
mm
Min
inches
Min
Typ
Max
Typ
Max
A
A1
A2
b
-
-
1.10
0.15
0.95
0.40
0.23
0.10
3.10
-
-
-
0.043
0.006
0.037
0.016
0.009
0.004
0.122
-
-
0.05
0.75
0.25
0.13
-
-
0.002
0.030
0.010
0.005
-
0.85
-
0.034
-
c
-
-
CP
D
-
-
3.00
0.65
4.90
3.00
0.55
0.95
-
2.90
-
0.118
0.026
0.193
0.118
0.022
0.037
-
0.114
-
e
E
4.65
2.90
0.40
-
5.15
3.10
0.70
-
0.183
0.114
0.016
-
0.203
0.122
0.030
-
E1
L
L1
α
0°
6°
0°
6°
N
8
8
Doc ID 10522 Rev 10
39/43
Part numbering
STM690A/692A/703/704/802/805/817/818/819
7
Part numbering
Table 10. Ordering information scheme
Example:
STM690A
M
6
E
Device type
STM690A/692A/703/704/802/805/817/818/819
Threshold voltage
STM690A, STM703: blank: VRST = 4.50 V to 4.75 V
STM692A, STM704: blank: VRST = 4.25 V to 4.50 V
STM8xx: L: VRST = 4.50 V to 4.75 V
M: VRST = 4.25 V to 4.50 V
Package
M = SO8
DS(1) = TSSOP8
Temperature range
6: –40 °C to 85 °C
Shipping method
E = ECOPACK® package, tubes
F = ECOPACK® package, tape & reel
1. Contact local ST sales office for availability.
For other options or for more information on any aspect of this device, please contact the ST
sales office nearest you.
40/43
Doc ID 10522 Rev 10
STM690A/692A/703/704/802/805/817/818/819
Table 11. Marking description
Part numbering
Topside marking
Part number
Reset threshold
Package
STM690A
STM692A
STM703
4.65 V
4.40 V
4.65 V
4.40 V
4.65 V
4.40 V
4.65 V
SO8
SO8
690A
692A
703
SO8
STM704
SO8
704
STM802L
STM802M
STM805L
SO8
802L
802M
805L
SO8
SO8
SO8
STM817L
STM817M
STM818L
STM818M
STM819L
STM819M
4.65 V
4.40 V
4.65 V
4.40 V
4.65 V
4.40 V
817L
817M
818L
818M
819L
819M
TSSOP8
SO8
TSSOP8
SO8
TSSOP8
SO8
TSSOP8
SO8
TSSOP8
SO8
TSSOP8
Doc ID 10522 Rev 10
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Revision history
STM690A/692A/703/704/802/805/817/818/819
8
Revision history
Table 12. Document revision history
Date
Revision
Changes
Oct-2003
1
Initial release.
31-Oct-2003
1.1
Update DC characteristics (Table 7).
Reformatted; updated characteristics (cover page, Figure 2, 3, 6, 7, 8, 9,
10, 11, 12, 13, 14, 16, Table 3, 4, 7, 9, 11).
22-Dec-2003
2
Add typical characteristics (Figure 18, 19, 21, 22, 24, 25, 26, 27, 28, 31,
32, 33, 34, 35, 36, 37, 38).
16-Jan-2004
08-Apr-2004
25-May-2004
2.1
2.2
3
Update characteristics (Figure 12, 22, 28, 32, 33, 34, 37; Table 1, 7).
Remove references to “open drain” (cover page, 4, 7; Table 2); update
characteristics (Table 3, 7).
Update package availability, pin description; promote document (cover
page, Figure 13, 14; Table 3, 7, 10).
05-Jul-2004
29-Sep-2004
01-Mar-2005
20-Jan-2006
21-Oct-2008
4
5
6
7
8
Clarify root part numbers, pin descriptions (Figure 10, 12, 39; Table 7, 10).
Update characteristics (Figure 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27,
28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38)
Correct marking, update lead-free text (Table 10, 11)
Reformatted, minor text changes; updated Table 3, 4, 7, 10, Figure 9, 10,
11, 12, 16, 39, Section 6: Package mechanical data.
20-Nov-2009
18-Aug-2010
9
Updated text in Section 6, Table 5.
10
Updated Section 2.4: Backup battery switchover.
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