STM8AF5189TBR_技术文档

STM8AF61xx, STM8AH61xx

STM8AF51xx, STM8AH51xx

Automotive 8-bit MCU, with up to 128 Kbytes Flash, EEPROM,

10-bit ADC, timers, LIN, CAN, USART, SPI, I²C, 3 V to 5.5 V

Features

Core

■ Max f

: 24 MHz

LQFP48 7x7

LQFP32 7x7

CPU

■ Advanced STM8A core with Harvard

architecture and 3-stage pipeline

■ Average 1.6 cycles/instruction resulting in 10

LQFP80 14x14

LQFP64 10x10

MIPS at 16 MHz f

benchmark

for industry standard

CPU

Communication interfaces

Memories

■ High speed 1 Mbit/s active CAN 2.0B interface

■ USART with clock output for synchronous

operation - LIN master mode

■ LINUART LIN 2.1 compliant, master/slave

modes with automatic resynchronization

■ Program memory: 48 to 128 Kbytes Flash; data

retention 20 years at 55 °C after 1 kcycle

■ Data memory: 1.5 to 2 Kbytes true data

EEPROM; endurance 300 kcycles

■ RAM: 3 to 6 Kbytes

■ SPI interface up to 10 Mbit/s or f

■ I C interface up to 400 Kbit/s

/2

CPU

Clock management

■ Low power crystal resonator oscillator with

external clock input

■ Internal, user-trimmable 16 MHz RC and low

power 128 kHz RC oscillators

2

Analog to digital converter (ADC)

■ 10-bit, 3 LSB ADC with up to 16 multiplexed

channels

I/Os

■ Clock security system with clock monitor

■ Up to 70 user pins including 10 high sink I/Os

Reset and supply management

■ Multiple low power modes (wait, slow, auto

wake-up, halt) with user definable clock gating

■ Low consumption power-on and power-down

reset

■ Highly robust I/O design, immune against

current injection

(1)

Table 1.

Device summary

Part numbers: STM8AF61xx/STM8AH61xx

Interrupt management

STM8AF/H61AA, STM8AF/H619A, STM8AF/H61A9,

STM8AF/H6199, STM8AF/H6189, STM8AF/H6179,

STM8AF/H6169, STM8AF/H61A8, STM8AF/H6198,

STM8AF/H6188, STM8AF/H6178, STM8AF/H6186,

STM8AF/H6176

■ Nested interrupt controller with 32 interrupt

vectors

■ Up to 37 external interrupts on 5 vectors

Timers

Part numbers: STM8AF51xx/STM8AH51xx (CAN)

■ Up to 2 auto-reload 16-bit PWM timers with up

to 3 CAPCOM channels each (IC, OC or PWM)

■ Multipurpose timer: 16-bit, 4 CAPCOM

channels, 3 complementary outputs, dead-time

insertion and flexible synchronization

STM8AF/H51AA, STM8AF/H519A, STM8AF/H51A9,

STM8AF/H5199, STM8AF/H5189, STM8AF/H5179,

STM8AF/H5169, STM8AF/H51A8, STM8AF/H5198,

STM8AF/H5188, STM8AF/H5178

1. This datasheet applies to product versions with and

without data EEPROM. The order code identifier is ‘F’

or ‘H’ respectively, only one of which appears in an

order code.

■ 8-bit AR system timer with 8-bit prescaler

■ Auto wake-up timer

■ Two watchdog timers: Window and standard

September 2008

Rev 3

1/100

www.st.com

1

Contents

STM8AF61xx, STM8AF51xx

Contents

1

2

3

4

5

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Product line-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Product overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

5.1

Central processing unit STM8A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

5.1.1

5.1.2

5.1.3

Architecture and registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

5.2

Single wire interface module (SWIM) and debug module . . . . . . . . . . . . 13

5.2.1

5.2.2

SWIM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Debug module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

5.3

5.4

Interrupt controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Non-volatile memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

5.4.1

5.4.2

5.4.3

5.4.4

Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Write protection (WP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Read-out protection (ROP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Speed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

5.5

5.6

Low-power operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Clock and clock controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

5.6.1

5.6.2

5.6.3

5.6.4

5.6.5

5.6.6

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Internal 16 MHz RC oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Internal 128 kHz RC oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Internal high-speed crystal oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

External clock input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Clock security system (CSS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

5.7

Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

5.7.1

5.7.2

5.7.3

Watchdog timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Auto wake-up counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Multipurpose and PWM timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

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STM8AF61xx, STM8AF51xx

Contents

5.7.4

Timer 4: System timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

5.8

5.9

ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Communication interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

5.9.1

5.9.2

5.9.3

5.9.4

5.9.5

USART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

LINUART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

2

I C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

CAN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

5.10 Input/output specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

6

Pinouts and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

6.1

6.2

Package pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

6.2.1

Alternate function remapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

7

Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Interrupt table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Register mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Option bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

8

9

10

11

11.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

11.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

11.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

11.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

11.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

11.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

11.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

11.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

11.3.1 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

11.3.2 External clock sources and timing characteristics . . . . . . . . . . . . . . . . . 67

11.3.3 Internal clock sources and timing characteristics . . . . . . . . . . . . . . . . . 69

11.3.4 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

11.3.5 I/O port pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

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Contents

STM8AF61xx, STM8AF51xx

11.3.6 Reset pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

11.3.7 TIM 1, 2, 3, and 4 timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 78

11.3.8 SPI serial peripheral interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

2

11.3.9 I C interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

11.3.10 10-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

11.3.11 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

11.4 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

11.4.1 Reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

11.4.2 Selecting the product temperature range . . . . . . . . . . . . . . . . . . . . . . . . 89

12

Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

12.1 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

13

14

Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

STM8 development tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

14.1 Emulation and in-circuit debugging tools . . . . . . . . . . . . . . . . . . . . . . . . . 96

14.2 Software tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

14.2.1 STM8 toolset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

14.2.2 C and assembly toolchains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

14.3 Programming tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

15

Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

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STM8AF61xx, STM8AF51xx

List of tables

Table 1.

Table 2.

Table 3.

Table 4.

Table 5.

Table 6.

Table 7.

Table 8.

Table 9.

Table 10.

Table 11.

Table 12.

Table 13.

Table 14.

Table 15.

Table 16.

Table 17.

Table 18.

Table 19.

Table 20.

Device summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

STM8AF/H51xx product line-up with CAN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

STM8AF/H61xx product line-up without CAN. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

STM8A timer configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Legend/abbreviation for Table 6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

STM8A microcontroller family pin description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Stack and RAM partitioning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

STM8A interrupt table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

STM8A I/O port hardware register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

STM8A general hardware register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

CPU/SWIM/debug module/interrupt controller registers. . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Option bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Option byte description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Operating conditions at power-up/power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Total current consumption in run, wait and slow mode at V = 5.0 V. . . . . . . . . . . . . . . . 59

DD

Total current consumption and timing in halt, fast active halt and slow

active halt modes at V = 5.0 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

DD

Table 21.

Table 22.

Total current consumption in run, wait and slow mode at V = 3.3 V. . . . . . . . . . . . . . . . 61

Total current consumption and timing in halt, fast active halt and slow

DD

active halt modes at V = 3.3 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

DD

Table 23.

Table 24.

Table 25.

Table 26.

Table 27.

Table 28.

Table 29.

Table 30.

Table 31.

Table 32.

Table 33.

Table 34.

Table 35.

Table 36.

Table 37.

Table 38.

Table 39.

Table 40.

Table 41.

Table 42.

Table 43.

Table 44.

Table 45.

Table 46.

Typical peripheral current consumption V = 5.0 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

DD

HSE user external clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

HSE oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

HSI oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

RAM and hardware registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

Flash program memory/data EEPROM memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

TIM 1, 2, 3 characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

2

I C characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

ADC accuracy with R

< 10 kΩ R , V

= 3.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

= 5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

AIN

< 10 kΩ , V

DDA

AIN

DDA

EMS data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

EMI data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

80-pin low profile quad flat package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

64-pin low profile quad flat package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

48-pin low profile quad flat package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

32-pin low profile quad flat package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

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List of tables

STM8AF61xx, STM8AF51xx

Table 47. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

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STM8AF61xx, STM8AF51xx

List of figures

Figure 1.

Figure 2.

Figure 3.

Figure 4.

Figure 5.

Figure 6.

Figure 7.

Figure 8.

Figure 9.

Figure 10.

STM8A block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Flash memory organization of STM8A products. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

LQFP 80-pin pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

LQFP 64-pin pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

LQFP 48-pin pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

LQFP 32-pin pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Register and memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Pin loading conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

f

versus V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

CPUmax

DD

Figure 11. Typ. I

Figure 12. Typ. I

Figure 13. Typ. I

Figure 14. Typ. I

Figure 15. Typ. I

Figure 16. Typ. I

vs. V @f

= 16 MHz, periph = on . . . . . . . . . . . . . . . . . . . . . . . . . . 66

DD(RUN)HSE

DD(RUN)HSI

DD(WFI)HSE

DD

CPU

vs. f

@ V = 5.0 V, periph = on . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

CPU

DD

vs. V @ f

= 16 MHz, periph = off . . . . . . . . . . . . . . . . . . . . . . . . . . 66

= 16 MHz, periph = on . . . . . . . . . . . . . . . . . . . . . . . . . . 66

DD

CPU

vs. V @ f

DD

CPU

vs. f

@ V = 5.0 V, periph = on . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

CPU

DD

vs. V @ f = 16 MHz, periph = off . . . . . . . . . . . . . . . . . . . . . . . . . . 66

DD(WFI)HSI

DD

CPU

Figure 17. HSE external clock source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

Figure 18. HSE oscillator circuit diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

Figure 19. Typical HSI frequency vs V @ four temperatures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

DD

Figure 20. Typical LSI frequency vs V @ room temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

DD

Figure 21. Typical V and V vs V @ four temperatures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

IL

IH

DD

Figure 22. Typical pull-up resistance R vs V @ four temperatures . . . . . . . . . . . . . . . . . . . . . . . 73

PU

DD

Figure 23. Typical pull-up current I vs V @ four temperatures . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

pu

DD

Figure 24. Typ. V @ V = 3.3 V (standard ports). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

OL

DD

Figure 25. Typ. V @ V = 5.0 V (standard ports). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

OL

DD

Figure 26. Typ. V @ V = 3.3 V (true open drain ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

OL

DD

Figure 27. Typ. V @ V = 5.0 V (true open drain ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

OL

DD

Figure 28. Typ. V @ V = 3.3 V (high sink ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

OL

DD

Figure 29. Typ. V @ V = 5.0 V (high sink ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

OL

DD

Figure 30. Typ. V - V @ V = 3.3 V (standard ports). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

DD

OH

DD

Figure 31. Typ. V - V @ V = 5.0 V (standard ports). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

DD

OH

DD

Figure 32. Typ. V - V @ V = 3.3 V (high sink ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

DD

OH

DD

Figure 33. Typ. V - V @ V = 5.0 V (high sink ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

DD

OH

DD

Figure 34. Typical NRST V and V vs V @ four temperatures . . . . . . . . . . . . . . . . . . . . . . . . . . 76

IL

IH

DD

Figure 35. Typical NRST pull-up resistance R vs V @ four temperatures. . . . . . . . . . . . . . . . . . 77

PU

DD

Figure 36. Typical NRST pull-up current I vs V @ four temperatures . . . . . . . . . . . . . . . . . . . . . 77

pu

DD

Figure 37. Recommended reset pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

Figure 38. SPI timing diagram where slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

Figure 39. SPI timing diagram where slave mode and CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

Figure 40. SPI timing diagram - master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

Figure 41. ADC accuracy characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

Figure 42. Typical application with ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

Figure 43. 80-pin low profile quad flat package (14 x 14) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

Figure 44. 64-pin low profile quad flat package (10 x 10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

Figure 45. 48-pin low profile quad flat package (7 x 7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

Figure 46. 32-pin low profile quad flat package (7 x 7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

Figure 47. STM8A order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

7/100

Introduction

STM8AF61xx, STM8AF51xx

1

Introduction

This datasheet refers to the STM8AF61xx, STM8AH61xx, STM8AF51xx, STM8AH51xx

products with 48 to 128 Kbytes of program memory. The STM8AF51xx and STM8AH51xx

are hereafter referred to as the STM8AF/H51xx and the STM8AF61xx and STM8AH61xx

are hereafter referred to as the STM8AF/H61xx. ‘F’ refers to product versions with data

EEPROM and ‘H’ refers to product versions without EEPROM. The identifiers ‘F’ and ‘H’ do

not both appear in an order code.

The datasheet contains the description of family features, pinout, electrical characteristics,

mechanical data and ordering information.

●

For complete information on the STM8A microcontroller memory, registers and

peripherals, please refer to STM8A microcontroller family reference manual (RM0009).

●

For information on programming, erasing and protection of the internal Flash memory

please refer to the STM8 Flash programming manual (PM0047).

For information on the debug and SWIM (single wire interface module) refer to the

STM8 SWIM communication protocol and debug module user manual (UM0470).

For information on the STM8 core, please refer to the STM8 CPU programming manual

(PM0044).

8/100

STM8AF61xx, STM8AF51xx

Description

2

Description

The STM8A automotive 8-bit microcontrollers offer from 48 to 128 Kbytes of program

memory and integrated true data EEPROM.

The STM8AF/H51xx series feature a CAN interface.

All devices of the STM8A product line provide the following benefits:

●

Reduced system cost

–

Integrated true data EEPROM for up to 300 k write/erase cycles

High system integration level with internal clock oscillators, watchdog and brown-

out reset

●

Performance and robustness

–

Peak performance 20 MIPS at 24 MHz and average performance 10 MIPS at 16

MHz CPU clock frequency

–

Robust I/O, independent watchdogs with separate clock source

Clock security system

●

Short development cycles

–

Applications scalability across a common family product architecture with

compatible pinout, memory map and and modular peripherals.

–

Full documentation and a wide choice of development tools

Product longevity

–

Advanced core and peripherals made in a state-of-the art technology

Native automotive product family operating both at 3.3 V and 5 V supply

All STM8A and ST7 microcontrollers are supported by the same tools including

STVD/STVP development environment, the STice emulator and a low-cost, third party in-

circuit debugging tool (for more details, see Section 14: STM8 development tools on

page 96).

9/100

Product line-up

STM8AF61xx, STM8AF51xx

3

Product line-up

.

Table 2.

STM8AF/H51xx product line-up with CAN

Prog.

RAM Data EE 10-bit

Timers

Serial

interfaces

I/0 wakeup

pins

Order code

Package

(bytes) (bytes) (bytes) A/D ch. (IC/OC/PWM)

STM8AF/H51AAT

STM8AF/H519AT

STM8AF/H51A9T

STM8AF/H5199T

STM8AF/H5189T

STM8AF/H5179T

STM8AF/H5169T

STM8AF/H51A8T

STM8AF/H5198T

STM8AF/H5188T

STM8AF/H5178T

128 K

96 K

LQFP80

(14x14)

72/37

6 K

2 K

128 K

96 K

64 K

48 K

32 K

128 K

96 K

64 K

48 K

16

10

LQFP64

(10x10)

4 K

3 K

2 K

56/36

1x8-bit: TIM4

3x16-bit: TIM1, LIN(UART),

TIM2, TIM3

(9/9/9)

CAN,

1.5 K

1 K

SPI,USART,

I²C

6 K

2 K

LQFP48

(7x7)⁽¹⁾

40/35

4 K

3 K

1.5 K

1. QFN package planned

²

Table 3.

STM8AF/H61xx product line-up without CAN

I/0

wakeup

pins

Prog.

RAM Data EE 10-bit

Timers

Serial

interfaces

Order code

Package

(bytes) (bytes) (bytes) A/D ch. (IC/OC/PWM)

STM8AF/H61AAT

STM8AF/H619AT

STM8AF/H61A9T

STM8AF/H6199T

STM8AF/H6189T

STM8AF/H6179T

STM8AF/H6169T

STM8AF/H61A8T

STM8AF/H6198T

STM8AF/H6188T

STM8AF/H6178T

STM8AF/H6186T

128 K

96 K

LQFP80

(14x14)

72/37

56/36

6 K

2 K

128 K

96 K

64 K

48 K

32 K

128 K

96 K

64 K

48 K

64 K

16

LQFP64

(10x10)

4 K

3 K

2 K

1x8-bit: TIM4

3x16-bit: TIM1,

TIM2, TIM3

(9/9/9)

LIN(UART),

SPI, USART,

I²C

1.5 K

1 K

6 K

2 K

LQFP48

(7x7)⁽¹⁾

10

7

40/35

25/23

4 K

3 K

4 K

1.5 K

1x8-bit: TIM4

3x16-bit: TIM1, LIN(UART),

TIM2, TIM3

(8/8/8)

LQFP32

(7x7)⁽¹⁾

SPI, I²C

STM8AF/H6176T

48 K

3 K

1. QFN package planned

10/100

STM8AF61xx, STM8AF51xx

Block diagram

4

Block diagram

Figure 1.

STM8A block diagram

Reset block

Reset

XTAL 1-24 MHz

RC int. 16 MHz

RC int. 128 kHz

Clock controller

Detector

Reset

POR

PDR

Clock to peripherals and core

Window WDG

WDG

STM8A CORE

Single wire

debug interf.

Up to 128 Kbyte

program

Debug/SWIM

LINUART

Flash

Master/slave

autosynchro

Up to 2 Kbytes

data EEPROM

400 Kbit/s

10 Mbit/s

2

Up to 6 Kbytes

RAM

I C

Boot ROM

SPI

16-bit multi-purpose

timer (TIM1)

LIN master

SPI emul.

USART

beCAN

Up to

9 CAPCOM

channels

16-bit PWM timers

(TIM2, TIM3)

1 Mbit/s

8-bit AR timer

(TIM4)

16 channels

10-bit ADC

AWU timer

11/100

Product overview

STM8AF61xx, STM8AF51xx

5

Product overview

The following section intends to give an overview of the basic features of the STM8A

functional modules and peripherals.

For more detailed information please refer to the STM8A microcontroller family reference

manual (RM0009).

5.1

Central processing unit STM8A

The 8-bit STM8A core is designed for code efficiency and performance.

It contains 21 internal registers (six directly addressable in each execution context), 20

addressing modes including indexed indirect and relative addressing and 80 instructions.

5.1.1

Architecture and registers

●

Harvard architecture

3-stage pipeline

32-bit wide program memory bus with single cycle fetching for most instructions

X and Y 16-bit index registers, enabling indexed addressing modes with or without

offset and read-modify-write type data manipulations

●

8-bit accumulator

24-bit program counter with 16-Mbyte linear memory space

16-bit stack pointer with access to a 64 Kbyte stack

8-bit condition code register with seven condition flags for the result of the last

instruction

5.1.2

5.1.3

Addressing

●

20 addressing modes

Indexed indirect addressing mode for look-up tables located anywhere in the address

space

●

Stack pointer relative addressing mode for local variables and parameter passing

Instruction set

●

80 instructions with 2-byte average instruction size

Standard data movement and logic/arithmetic functions

8-bit by 8-bit multiplication

16-bit by 8-bit and 16-bit by 16-bit division

Bit manipulation

Data transfer between stack and accumulator (push/pop) with direct stack access

Data transfer using the X and Y registers or direct memory-to-memory transfers

12/100

STM8AF61xx, STM8AF51xx

Product overview

5.2

Single wire interface module (SWIM) and debug module

The single wire interface module, SWIM, together with an integrated debug module, permits

non-intrusive, real-time in-circuit debugging and fast memory programming.

5.2.1

SWIM

Single wire interface for direct access to the debugging module and memory programming.

The interface can be activated in all device operation modes and supports hot-plugging. The

maximum data transmission speed is 145 bytes/ms.

5.2.2

Debug module

The non-intrusive debugging module features a performance close to a full-featured

emulator. Besides memory and peripheral operation, CPU operation can also be monitored

in real-time by means of shadow registers.

●

R/W of RAM and peripheral registers in real-time

R/W for all resources when the application is stopped

Breakpoints on all program-memory instructions (software breakpoints) except the

vector table

●

Two advanced breakpoints and 23 predefined configurations

5.3

Interrupt controller

●

Nested interrupts with three software priority levels

32 interrupt vectors with hardware priority

Up to 37 external interrupts on five vectors

Trap and reset interrupts

5.4

Non-volatile memory

●

Up to 128 Kbytes of program single voltage Flash memory

Up to 2 Kbytes true (not emulated) data EEPROM

Read while write: Writing in the data memory is possible while executing code in the

program memory

●

128 user option bytes permit permanent device set up

5.4.1

Architecture

●

Array: Up to 128 Kbytes of Flash program memory organized in blocks of 128 bytes

each

●

Read granularity: 1 word = 4 bytes

Write/erase granularity: 1 word (4 bytes) or 1 block (128 bytes) in parallel

Writing, erasing, word and block register management is handled automatically by the

memory interface.

13/100

Product overview

STM8AF61xx, STM8AF51xx

5.4.2

Write protection (WP)

Write protection in application mode is intended to avoid unintentional overwriting of the

memory in case of user software malfunction. Code update in user mode is still possible

after execution of a specific MASS key sequence.

The program memory is divided into two areas:

●

Main program memory: Up to 128 Kbytes minus user-specific boot code (UBC)

UBC: Configurable up to 128 Kbytes

●

The UBC area also remains write-protected during in-application programming. It permits

storage of the boot program or specific code libraries.

The boot area is a part of the program memory that contains the reset and interrupt vectors,

the reset routine and usually the IAP and communication routines. The UBC area has a

second level of protection to prevent unintentional erasing or modification during IAP

programming. This means that the MASS keys do not unlock the UBC area.

The size of the UBC is programmable through the UBC option byte, in increments of 512

bytes, by programming the UBC option byte in ICP mode.

Figure 2.

Flash memory organization of STM8A products

Programmable area from 1 Kbyte

(first two pages) up to program memory

end - maximum 128 Kbytes

UBC area

Remains write protected during IAP

Flash

program

memory

Program memory area

Write access possible for IAP

Data memory area (2 Kbytes)

Option bytes

Data

EEPROM

memory

14/100

STM8AF61xx, STM8AF51xx

Product overview

5.4.3

Read-out protection (ROP)

STM8A devices provide a read-out protection of the code and data memory by

programming the lock byte at address 4800h with the value AAh.

Read-out protection prevents reading and writing the program and data memory via the

debug module and SWIM interface. This protection is active in all device operation modes.

Any attempt to remove the protection by overwriting the lock byte triggers a global erase of

the program and data memory.

The ROP circuit may provide a temporary access for debugging or failure analysis. This is a

specific product option and must be specified while ordering STM8A products.

Temporary read access is protected by a user defined, 8-byte keyword that is different from

00h or FFh. The keys are stored in the option byte area.

Temporary read-out can be permanently disabled by means of the option byte TMU_DIS.

For enabling temporary read access the eight access keys have to be written in the TMU

registers. A wrong code does not change the protection status. More than eight

unsuccessful access trials trigger an erase of the program and data memory.

Entering the right key sequence enables a temporary read access to the code and data

memory after a delay of several milliseconds.

The procedure for temporary read access is as follows:

●

Activate SWIM mode under device reset - the CPU is stalled, code and data memory

are not visible by the debug module.

●

Enable the internal 128 KHz LSI oscillator

Write the 8eight key bytes into the TMU registers

Set the bit(0) of the TMU status register to 1. A dedicated state machine on an isolated

bus, compares the TMU register content with the key stored in the TMU option bytes.

During this periode read and write operations have no effect. A reset re-activates the

initial protection status. The comparison can be monitored by means of the TU_CTL_ST

register.

●

In case of a successful key comparison, the SWIM interface enables read access to the

code and data memory and program execution. A comparison error does not change

the protection status but increments the counter MAXATT. If the counter content

exceedes eight unsuccessful trials, a global erase of the data and code memory is

triggered.

The read access is temporary. A device reset restores the initial protection.

5.4.4

Speed

●

Operation at up to 16 MHz CPU clock frequency without wait states. At a higher clock

frequency, a single wait state has to be inserted.

●

Programming time modes (same for word or block)

–

Fast programming: Without erase

Standard programming: Erase and program

15/100

Product overview

STM8AF61xx, STM8AF51xx

5.5

Low-power operating modes

The product features various low-power modes:

●

Slow mode: Prescaled CPU clock, selected peripherals at full clock speed

Active halt mode: CPU and peripheral clocks are stopped

Halt mode: CPU and peripheral clocks are stopped, the device remains powered on.

Wake-up is triggered by an external interrupt.

In all modes the CPU and peripherals remain permanently powered on, the system clock is

applied only to selected modules.

The RAM content is preserved and the brown-out reset circuit remains activated.

5.6

Clock and clock controller

The clock controller distributes the system clock coming from different oscillators to the core

and the peripherals. It also manages clock gating for low power modes and ensures clock

robustness.

5.6.1

Features

●

Clock sources:

–

Internal 16 MHz and 128 kHz RC oscillators

Crystal oscillator

External clock input

●

Reset: After reset the microcontroller restarts by default with an internal 2-MHz clock

(16 MHz/8). The prescaler ratio and clock source can be changed by the application

program as soon as the code execution starts.

Safe clock switching: Clock sources can be changed safely on the fly in run mode

through a configuration register. The clock signal is not switched until the new clock

source is ready. The design guarantees glitch-free switching.

●

Clock management: To reduce power consumption, the clock controller can stop the

clock to the core, individual peripherals or memory.

Wake-up: Recovery from halt and AWU (auto wake-up) low power modes uses the

internal RC oscillator (16 MHz/8) for quick start-up and then switches to the last

selected clock source before halt mode is entered.

●

Clock security system (CSS): The CSS permits monitoring of external clock sources

and automatic switching to the internal RC (16 MHz/8) in case of a clock failure.

Configurable main clock output (CCO): This outputs an external clock for use by the

application.

16/100

STM8AF61xx, STM8AF51xx

Product overview

5.6.2

Internal 16 MHz RC oscillator

●

Default clock after reset 2 MHz (16 MHz/8)

Wake-up time: < 2 µs

User trimming

The register CLK_HSITRIMR with two trimming bits plus one additional bit for the sign permits

frequency tuning to a precision of 1% by the application program. The trimming step

granularity is 1.5 %.

The adjustment range covers all possible frequency variations versus supply voltage and

temperature. This trimming does not change the initial production setting.

5.6.3

5.6.4

Internal 128 kHz RC oscillator

The frequency of this clock is 128 kHz and it is independent from the main clock. It drives

the watchdog or the AWU wake-up timer.

In systems which do not need independent clock sources for the watchdog counters, the

128 kHz signal can be used as the system clock. This configuration has to be enabled by

setting an option byte (OPT3, LSI_EN).

Internal high-speed crystal oscillator

The internal high-speed crystal oscillator delivers the main clock in normal run mode. It

operates with quartz crystals and ceramic resonators.

●

Frequency range: 1 to 24 MHz

Crystal oscillation mode: Preferred fundamental

I/Os: Standard I/O pins multiplexed with OSCIN, OSCOUT

Optionally, an external clock signal can be injected into the OSCIN input pin.

5.6.5

5.6.6

External clock input

The external clock signal is applied to the OSCIN input pin of the crystal oscillator. The

frequency range is 0 to 24 MHz.

Clock security system (CSS)

The clock security system protects against a system stall in case of an external crystal clock

failure.

In case of a clock failure an interrupt is generated and the high speed internal clock (HSI) is

automatically selected with a frequency of 2 MHz (16 MHz/8). This function can be enabled

using the CSS register (CLK_CSSR).

The CSS operates by detecting when the external clock signal (crystal or external clock)

falls below 500 kHz. With active CSS this is the minimum operating frequency.

17/100

Product overview

STM8AF61xx, STM8AF51xx

5.7

Timers

5.7.1

Watchdog timers

The watchdog system is based on two independent timers providing maximum security to

the applications.

The WDG timer activity is controlled by the application program or option bytes. Once the

watchdog is activated, it cannot be disabled by the user program without a reset.

Window watchdog timer

The window watchdog is used to detect the occurrence of a software fault, usually

generated by external interferences or by unexpected logical conditions, which cause the

application program to abandon its normal sequence.

The window function can be used to trim the watchdog behavior to match the application

perfectly.

The application software must refresh the counter before time-out and during a limited time

window.

A reset is generated in two situations:

1. Timeout

2. Refresh out of window: The downcounter is refreshed before its value is lower then the

one stored in the window register.

Independent watchdog timer

The independent watchdog peripheral can be used to resolve processor malfunctions due to

hardware or software failures.

It is clocked by the 128 kHz LSI internal RC clock source, and thus stays active even in case

of a CPU clock failure. If the hardware watchdog feature is enabled through the device

option bits, the watchdog is automatically enabled at power-on, and generates a reset

unless the key register is written by software before the counter reaches the end of count.

The IWDG time base spans from 60 µs to 1 s. It can be adjusted by setting the registers of

the 7-bit prescaler and 8-bit down-counter.

5.7.2

Auto wake-up counter

●

Used for auto wake-up from active halt mode.

Clock source: Internal 128 kHz internal low frequency RC oscillator or external clock.

18/100

STM8AF61xx, STM8AF51xx

Product overview

5.7.3

Multipurpose and PWM timers

STM8A devices described in this datasheet, contain up to three 16-bit multipurpose and

PWM timers providing nine CAPCOM channels in total.

Table 4.

STM8A timer configuration

Complementary Synchronization

Timer Counter

Prescaler

Type

CAPCOM

outputs

module

Timer1

16

Up/down

4

3

2

3

Yes

Timer2

Timer3

16

8

15-bit fixed power

of 2 ratios

Up

0

No

7-bit fixed power

of 2 ratios

Timer4

0

Timer 1: Multipurpose PWM timer

This is a high-end timer designed for a wide range of control applications. With its

complementary outputs, dead-time control and center-aligned PWM capability, the field of

applications is extended to motor control, lighting and half-bridge driver.

●

16-bit up, down and up/down AR (auto-reload) counter with 16-bit prescaler

●

Four independent CAPCOM channels configurable as input capture, output compare,

PWM generation (edge and center aligned mode) and single pulse mode output

●

Trigger module which allows the interaction of timer 1 with other timers or the ADC to

be controlled

●

Break input to force the timer outputs into a defined state

Three complementary outputs with adjustable dead time

Interrupt sources: 4 x input capture/output compare, 1 x overflow/update, 1 x break

Timer 2 and 3: 16-bit PWM timers

●

16-bit auto-reload up-counter

15-bit prescaler adjustable to fixed power of two ratios 1…32768

Timers with three or two individually configurable CAPCOM channels

Interrupt sources: 2 or 3 x input capture/output compare, 1 x overflow/update

5.7.4

Timer 4: System timer

●

8-bit auto-reload, adjustable prescaler ratio to any power of two from 1 to 128

Clock source: master clock

Interrupt source: 1 x overflow/update

19/100

Product overview

STM8AF61xx, STM8AF51xx

5.8

ADC

The STM8A products described in this datasheet, contain a 10-bit successive approximation

ADC with 16 multiplexed input channels.

General features:

●

10-bit ADC with up to 16 channels

Input voltage range: 0 to V

Acqusition modes

DDA

–

Single conversion

Continous acquisition - up to 100 ksamples/s effective sampling rate

Trigger register and external trigger input

●

Interrupts

End of conversion (EOC) - can be masked

–

5.9

Communication interfaces

The following communication interfaces are implemented on STM8A products:

●

USART: Full feature UART, SPI emulation, LIN master capability

LINUART: LIN2.1 master/slave capability, full feature UART

SPI - full and half-duplex, 10 Mbit/s

I²C - up to 400 Kbit/s

CAN (rev. 2.0A,B) - 3 Tx mailboxes - up to 1 Mbit/s

SWIM for debugging and device programming

5.9.1

USART

Main features

●

1 Mbit/s full duplex SCI

LIN master capable

SPI emulation

16-bit baud-rate prescaler

20/100

STM8AF61xx, STM8AF51xx

Product overview

Full duplex, asynchronous communication

●

NRZ standard format (mark/space)

High-precision baud rate generator system

–

Common programmable transmit and receive baud rates up to 2.5 M baud

●

Programmable data word length (8 or 9 bits)

Configurable stop bits providing support for 1 or 2 stop bits

LIN master mode

–

LIN break and delimiter generation

–

LIN break and delimiter detection with separate flag and interrupt source for read-

back checking

●

Transmitter clock output for synchronous communication

Single wire half duplex communication

Separate enable bits for transmitter and receiver

Transfer detection flags

–

Receive buffer full

–

Transmit buffer empty

End of transmission flags

●

Parity control:

–

Transmit parity bit

Check parity of received data byte

Four error detection flags

–

Overrun error

Noise error

Frame error

Parity error

●

Six interrupt sources with flags

–

Transmit data register empty

Transmission complete

Receive data register full

Idle line received

Parity error

LIN break and delimiter detection

●

Two interrupt vectors

–

Transmitter interrupt

Receiver interrupt

●

Reduced power consumption mode

Multi-processor communication, allowing entry into mute mode if address match does

not occur

●

Wakeup from mute mode (by idle line detection or address mark detection)

Two receiver wakeup modes:

–

Address bit (MSB)

Idle line

21/100

Product overview

STM8AF61xx, STM8AF51xx

5.9.2

LINUART

Main features

●

LIN master/slave rev. 2.1 compliant

Auto-synchronization in LIN slave mode

16-bit baud rate prescaler

1 Mbit full duplex SCI

LIN master

●

Autonomous header handling

13-bit LIN synch break generation

LIN slave

●

Autonomous header handling - one single interrupt per valid message header

Automatic baud rate synchronization - maximum tolerated initial clock deviation 15 %

Synch delimiter checking

11-bit LIN synch break detection - break detection always active

Parity check on the LIN identifier field

LIN error management

Hot plugging support

Asynchronous communication (UART)

●

Full duplex, asynchronous communications - NRZ standard format (mark/space)

Independently programmable transmit and receive baud rates up to 500 Kbit/s

Programmable data word length (8 or 9 bits)

Low-power standby mode - two receiver wake-up modes:

–

Address bit (MSB)

Idle line

●

Muting function for multiprocessor configurations

Overrun, noise and frame error detection

Six interrupt sources

Tx, Rx parity control

5.9.3

SPI

●

Maximum speed: 10 Mbit/s or f

/2 both for master and slave

CPU

Full duplex synchronous transfers

Simplex synchronous transfers on two lines with a possible bidirectional data line

Master or slave operation - selectable by hardware or software

CRC calculation

1 byte Tx and Rx buffer

Slave/master selection input pin

22/100

STM8AF61xx, STM8AF51xx

2

Product overview

5.9.4

I C

●

I²C master features:

–

Clock generation

Start and stop generation

●

I²C slave features:

–

Programmable I²C address detection

Stop bit detection

●

Generation and detection of 7-bit/10-bit addressing and general call

Supports different communication speeds:

–

Standard speed (up to 100 kHz),

Fast speed (up to 400 kHz)

●

Interrupt:

–

Successful address/data communication

Error condition

Wake-up from halt

●

Wake-up from halt on address detection in slave mode

5.9.5

CAN

The beCAN3 controller (basic enhanced CAN), interfaces the CAN network and supports

the CAN protocol version 2.0A and B. It has been designed to manage a high number of

incoming messages efficiently with a minimum CPU load.

For safety-critical applications, the CAN controller provides all hardware functions to support

the CAN time triggered communication option (TTCAN).

The maximum transmission speed is 1 Mbit.

Transmission

●

Three transmit mailboxes

Configurable transmit priority by identifier or order request

Time stamp on SOF transmission

Reception

●

11- and 29-bit ID

1 receive FIFO (3 messages deep)

Software-efficient mailbox mapping at a unique address space

FMI (filter match index) stored with message

Configurable FIFO overrun

Time stamp on SOF reception

6 filter banks, 2 x 32 bytes (scalable to 4 x 16-bit) each, enabling various masking

configurations, such as 12 filters for 29-bit ID or 48 filters for 11-bit ID

23/100

Product overview

STM8AF61xx, STM8AF51xx

●

Filtering modes:

–

Mask mode permitting ID range filtering

ID list mode

●

Time triggered communication option

–

Disable automatic retransmission mode

16-bit free running timer

Configurable timer resolution

Time stamp sent in last two data bytes

Interrupt management

●

Maskable interrupt

Software-efficient mailbox mapping at a unique address space

5.10

Input/output specifications

The product features four different I/O types:

●

Standard I/O 2 MHz

Fast I/O 10 MHz

High sink 8 mA, 2 MHz

2

True open drain (I C interface)

To decrease EMI (electromagnetic interference), high sink I/Os have a limited maximum

slew rate. The rise and fall times are similar to those of standard I/Os. Selected I/Os include

a low leakage analog switch.

STM8A I/Os are designed to withstand current injection. For a negative injection current of

4 mA, the resulting leakage current in the adjacent input does not exceed 1 µA. External

protection diodes are no longer required.

24/100

STM8AF61xx, STM8AF51xx

Pinouts and pin description

6

Pinouts and pin description

6.1

Package pinouts

Figure 3.

LQFP 80-pin pinout

60

59

58

57

56

55

54

53

52

51

50

49

48

47

46

45

44

43

42

41

1

2

3

4

5

6

7

8

NRST

OSCIN/PA1

OSCOUT/PA2

PI3

PI2

PI1

PI0

V

SSIO_1

V

PG4

PG3

PG2

PG1/CAN_RX

PG0/CAN_TX

PC7/SPI_MISO

PC6/SPI_MOSI

SS

VCAP

V

DD

(1)

V

DDIO_1

(1)

9

TIM2_CC3/PA3

USART_RX/PA4

USART_TX/PA5

USART_CK/PA6

(HS) PH0

10

11

12

13

14

15

16

17

18

19

20

V

DDIO_2

SSIO_2

(HS) PH1

PC5/SPI_SCK

PH2

PH3

AIN15/PF7

AIN14/PF6

AIN13/PF5

AIN12/PF4

PC4 (HS)/TIM1_CC4

PC3 (HS)/TIM1_CC3

PC2 (HS)/TIM1_CC2

PC1 (HS)/TIM1_CC1

PC0/ADC_ETR

PE5/SPI_NSS

(HS) high sink capability

1. The CAN interface is only available on the STM8AF/H51xx product line

25/100

Pinouts and pin description

Figure 4. LQFP 64-pin pinout

STM8AF61xx, STM8AF51xx

64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49

PI0

48

NRST

OSCIN/PA1

OSCOUT/PA2

1

PG4

PG3

PG2

PG1/CAN_RX

PG0/CAN_TX

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

V

SSIO_1

(1)

V

SS

(1)

VCAP

PC7/SPI_MISO

PC6/SPI_MOSI

V

DD

V

DDIO_1

V

TIM2_CC3/PA3

USART_RX/PA4

USART_TX/PA5

USART_CK/PA6

AIN15/PF7

DDIO_2

V

SSIO_2

PC5/SPI_SCK

PC4 (HS)/TIM1_CC4

PC3 (HS)/TIM1_CC3

PC2 (HS)/TIM1_CC2

PC1 (HS)/TIM1_CC1

PE5/SPI_NSS

AIN14/PF6

AIN13/PF5

AIN12/PF4

17181920 212223242526272829303132

(HS) high sink capability

1. The CAN interface is only available on the STM8AF/H51xx product line

26/100

STM8AF61xx, STM8AF51xx

Figure 5. LQFP 48-pin pinout

Pinouts and pin description

48 47 46 45 4443424140393837

36

NRST

OSCIN/PA1

PG1

35 PG0

1

2

OSCOUT/PA2

3

4

34 PC7/SPI_MISO

33 PC6/SPI_MOSI

V

SSIO_1

V

32

31

30

29

28

27

26

25

5

6

7

8

9

10

11

V

SS

DDIO_2

VCAP

SSIO_2

V

PC5/SPI_SCK

DD

V

PC4 (HS)/TIM1_CC4

PC3 (HS)/TIM1_CC3

PC2 (HS)/TIM1_CC2

PC1 (HS)/TIM1_CC1

PE5/SPI_NSS

DDIO_1

TIM2_CC3/PA3

PA4

PA5

PA6

12

24

13141516 17181920212223

(HS) high sink capability

1. The CAN interface is only available on the STM8AF/H51xx product line

27/100

Pinouts and pin description

Figure 6. LQFP 32-pin pinout

STM8AF61xx, STM8AF51xx

32 31 30 29 28 27 26 25

24

NRST

OSCIN/PA1

OSCOUT/PA2

1

2

3

4

5

6

7

8

PC7/SPI_MISO

PC6/SPI_MOSI

PC5/SPI_SCK

PC4 (HS)/TIM1_CC4

PC3 (HS)/TIM1_CC3

PC2 (HS)/TIM1_CC2

PC1 (HS)/TIM1_CC1

PE5/SPI_NSS

23

22

21

20

19

18

17

V

SS

VCAP

V

DD

V

DDIO

AIN12/PF4

9 1011121314 1516

(HS) high sink capability

6.2

Pin description

Table 5.

Type

Legend/abbreviation for Table 6

I= input, O = output, S = power supply

Level

Input

CM = CMOS (standard for all I/Os)

HS = High sink (8 mA)

Output

Output speed

O1 = Standard (up to 2 MHz)

O2 = Fast (up to 10 MHz)

O3 = Fast/slow programmability with slow as default state after reset

O4 = Fast/slow programmability with fast as default state after reset

Port and control Input

float = floating, wpu = weak pull-up

configuration

Output

T = true open drain, OD = open drain, PP = push pull

Reset state is shown in bold.

28/100

STM8AF61xx, STM8AF51xx

Pinouts and pin description

Table 6.

STM8A microcontroller family pin description

Pin number

Input

Output

Alternate

function

after

remap

Main

function Default alternate

Pin name

(after

reset)

function

[option bit]

1

2

1

2

1

2

1

2

NRST

I/O

X

Reset

Resonator/crystal

in

PA1/OSCIN

X

O1

X

X Port A1

X Port A2

Resonator/crystal

out

3

PA2/OSCOUT

I/O

X

4

5

6

7

8

4

5

6

7

8

4

5

6

7

8

-

V_{SSIO_1}

V_SS

S

I/O ground

4

5

6

7

Digital ground

VCAP

V_DD

1.8 V regulator capacitor

Digital power supply

I/O power supply

Timer 2 -

V_{DDIO_1}

TIM3_CC1

[AFR1]

9

-

PA3/TIM2_CC3

I/O

X

O1

X

X Port A3

channel3

10 10 10

11 11 11

-

PA4/USART_RX I/O

PA5/USART_TX I/O

X

O3

X

X Port A4 USART receive

X Port A5 USART transmit

USART

X Port A6 synchronous

clock

12 12 12

-

PA6/USART_CK I/O

X

O3

X

13

14

15

16

-

PH0

I/O

X

HS O3

O1

X

X Port H0

PH1

X Port H1

-

PH2

X Port H2

-

PH3

O1

X Port H3

17 13

18 14

19 15

20 16

21 17

-

PF7/AIN15

PF6/AIN14

PF5/AIN13

PF4/AIN12

PF3/AIN11

O1

X Port F7 Analog input 15

X Port F6 Analog input 14

X Port F5 Analog input 13

X Port F4 Analog input 12

X Port F3 Analog input 11

-

O1

-

O1

8

-

O1

ADC positive reference

voltage

22 18

-

V_REF+

V_DDA

S

23 19 13

9

S

Analog power supply

Analog ground

24 20 14 10 V_SSA

ADC negative reference

voltage

25 21

26 22

-

V_REF-

S

PF0/AIN10

I/O

X

O1

X

X Port F0 Analog input 10

29/100

Pinouts and pin description

STM8AF61xx, STM8AF51xx

Table 6.

STM8A microcontroller family pin description (continued)

Pin number

Input

Output

Alternate

function

after

remap

Main

function Default alternate

Pin name

(after

reset)

function

[option bit]

27 23 15

28 24 16

-

PB7/AIN7

PB6/AIN6

I/O

X

O1

X

X Port B7 Analog input 7

X Port B6 Analog input 6

I²C_SDA

[AFR6]

29 25 17 11 PB5/AIN5

30 26 18 12 PB4/AIN4

31 27 19 13 PB3/AIN3

I/O

X

O1

X

X Port B5 Analog input 5

X Port B4 Analog input 4

X Port B3 Analog input 3

I²C_SCL

[AFR6]

TIM1_ETR

[AFR5]

TIM1_

NCC3

[AFR5]

32 28 20 14 PB2/AIN2

33 29 21 15 PB1/AIN1

34 30 22 16 PB0/AIN0

I/O

X

O1

X

X Port B2 Analog input

X Port B1 Analog input 1

X Port B0 Analog input 0

TIM1_

NCC2

[AFR5]

TIM1_

NCC1

[AFR5]

I/O

Timer 1 - trigger

input

35

36

37

38

-

PH4/TIM1_ETR

X

O1

X

X Port H4

Timer 1 - inverted

X Port H5

PH5/ TIM1_NCC3 I/O

PH6/TIM1_NCC2 I/O

PH7/TIM1_NCC1 I/O

channel 3

Timer 1 - inverted

X Port H6

channel 2

Timer 1 - inverted

X Port H7

-

channel 2

39 31 23

40 32 24

PE7/AIN8

PE6/AIN9

I/O

X

O1

X

X Port E7 Analog input 8

X Port E7 Analog input 9

X

SPI master/slave

select

41 33 25 17 PE5/SPI_NSS

42 PC0/ADC_ETR

I/O

X

O1

X

X Port E5

-

X Port C0 ADC trigger input

Timer 1 - channel

1

43 34 26 18 PC1/TIM1_CC1

44 35 27 19 PC2/TIM1_CC2

45 36 28 20 PC3/TIM1_CC3

HS O3

X Port C1

Timer 1- channel

2

I/O

X

HS O3

X

X Port C2

Timer 1 - channel

3

X Port C3

30/100

STM8AF61xx, STM8AF51xx

Pinouts and pin description

Table 6.

STM8A microcontroller family pin description (continued)

Pin number

Input

Output

Alternate

function

after

remap

Main

function Default alternate

Pin name

(after

reset)

function

[option bit]

Timer 1 - channel

4

46 37 29 21 PC4/TIM1_CC4

47 38 30 22 PC5/SPI_SCK

I/O

X

HS O3

X

X Port C4

I/O

S

O3

X Port C5 SPI clock

I/O ground

48 39 31

49 40 32

-

V_{SSIO_2}

V_{DDIO_2}

S

I/O power supply

SPI master out/

slave in

50 41 33 23 PC6/SPI_MOSI

51 42 34 24 PC7/SPI_MISO

I/O

X

O3

X

X Port C6

X Port C7

SPI master in/

slave out

52 43 35

53 44 36

-

PG0/CAN_TX

I/O

X

O1

X

X Port G0 CAN transmit

X Port G1 CAN receive

X Port G2

PG1/CAN_RX

PG2

PG3

PG4

PI0

54 45

55 46

56 47

57 48

-

X Port G3

X Port G4

X Port I0

58

59

60

61

62

-

PI1

X Port I1

PI2

X Port I2

PI3

X Port I3

PI4

X Port I4

PI5

X Port I5

63 49

64 50

65 51

66 52

PG5

PG6

PG7

PE4

X Port G5

X Port G6

X Port G7

X

X Port E4

Timer 1 - break

input

67 53 37

-

PE3/TIM1_BKIN I/O

X

O1

X

X Port E3

68 54 38

69 55 39

-

PE2/I²C_SDA

PE1/I²C_SCL

I/O

X

O1 T⁽¹⁾X Port E2 I²C data

O1 T⁽¹⁾X Port E1 I²C clock

Configurable

clock output

70 56 40

-

PE0/CLK_CCO

I/O

X

O3

X

X Port E0

71

72

-

PI6

PI7

I/O

X

O1

X

X Port I6

X Port I7

31/100

Pinouts and pin description

STM8AF61xx, STM8AF51xx

Table 6.

STM8A microcontroller family pin description (continued)

Pin number

Input

Output

Alternate

function

after

remap

Main

function Default alternate

Pin name

(after

reset)

function

[option bit]

TIM1_BKIN

Timer 3 - channel [AFR3]/

73 57 41 25 PD0/TIM3_CC2

I/O

X

HS O3

X

X Port D0

2

CLK_CCO

[AFR2]

SWIM data

interface

74 58 42 26 PD1/SWIM

I/O

X

HS O4

HS O3

X

X Port D1

X Port D2

X Port D3

Timer 3 - channel TIM2_CC3

[AFR1]

75 59 43 27 PD2/TIM3_CC1

76 60 44 28 PD3/TIM2_CC2

1

Timer 2 - channel ADC_ETR

2

[AFR0]

BEEP

output

[AFR7]

PD4/TIM2_CC1/B

Timer 2 - channel

1

77 61 45 29

EEP

I/O

X

HS O3

O1

X

X Port D4

X Port D5

PD5/

78 62 46 30

LINUART_TX

LINUART data

transmit

LINUART data

receive

Port D6

PD6/

79 63 47 31

LINUART_RX

I/O

X

O1

X

Caution: This pin must be held low

during power on

TIM1_CC4

[AFR4]

80 64 48 32 PD7/TLI

X Port D7 Top level interrupt

1. In the open-drain output column, ‘T’ defines a true open-drain I/O (P-buffer and protection diode to V_DDare not

implemented)

6.2.1

Alternate function remapping

As shown in the rightmost column of Table 6, some alternate functions can be remapped at different I/O

ports by programming one of eight AFR (alternate function remap) option bits. Refer to Section 10:

Option bytes on page 49. When the remapping option is active, the default alternate function is no longer

available.

To use an alternate function, the corresponding peripheral must be enabled in the peripheral registers.

Alternate function remapping does not effect GPIO capabilities of the I/O ports (see the GPIO section of

the STM8A microcontroller family reference manual, RM0009).

32/100

STM8AF61xx, STM8AF51xx

Memory map

7

Memory map

Figure 7.

Register and memory map

00 0000

Up to 6 Kbytes RAM

Up to 1 Kbyte stack

Reserved

00 1800

00 4000

Up to 2 Kbytes data EEPROM

00 4800

Option and engineering bytes

Reserved

00 4900

00 5000

HW registers

00 5800

00 6000

00 6800

00 7F00

00 8000

00 8080

Reserved

2 Kbytes ROM

CPU registers

IT vectors

Up to 128 Kbytes code Flash

02 7FFF

Table 7.

Product

Stack and RAM partitioning

Stack size

RAM size

RAM end

Kbytes

Stack start

Kbytes

Dec

Hex

128

6

17FF

1024

0400

1400

33/100

Interrupt table

STM8AF61xx, STM8AF51xx

8

Interrupt table

Table 8.

Priority

STM8A interrupt table

Source

Interruptvector Wake-up

Description

block

Comments

address

from halt

-

Reset

6000h

8004h

Yes

Reset vector in ROM

TRAP

TLI

SW interrupt

External top level

interrupt

0

1

2

8008h

800Ch

8010h

Auto wake up from

halt

AWU

Yes

Clock

controller

Main clock controller

3

4

5

6

7

8

MISC

CAN

Ext interrupt E0

Ext interrupt E1

Ext interrupt E2

Ext interrupt E3

Ext interrupt E4

CAN interrupt Rx

8014h

8018h

801Ch

8020h

8024h

8028h

Yes

Port A interrupts

Port B interrupts

Port C interrupts

Port D interrupts

Port E interrupts

CAN interrupt

TX/ER/SC

9

CAN

802Ch

8030h

8034h

8038h

803Ch

8040h

8044h

8048h

10

11

12

13

14

15

16

SPI

End of transfer

Yes

Update/overflow/

trigger/break

Timer 1

Timer 2

Timer 3

Capture/compare

Update/overflow/

break

Trigger not available on

medium end timer

Capture/compare

Update/overflow/

break

Trigger not available on

medium end timer

Capture/compare

Tx complete/

ER/SPI EOT/SPI

error

USART

(SCI1)

17

804Ch

USART

(SCI1)

18

19

20

Receive data full reg.

I²C interrupts

8050h

8054h

8058h

I²C

Yes

LINUART

(SCI2)

Tx complete/error/

SPI EOT/SPI error

LINUART

(SCI2)

21

Receive data full reg.

805Ch

34/100

STM8AF61xx, STM8AF51xx

Interrupt table

Comments

Table 8.

Priority

STM8A interrupt table (continued)

Source

block

Interruptvector Wake-up

Description

address

from halt

22

23

24

ADC

Timer 4

End of conversion

Update/overflow

8060h

8064h

8068h

Reserved⁽¹⁾Reserved

1. Also unused interrupts should be initialized with “IRET” for robust programming.

35/100

Register mapping

STM8AF61xx, STM8AF51xx

9

Register mapping

Table 9.

Address

STM8A I/O port hardware register map

Reset

status

Block

Register label

Register name

00 5000h

00 5001h

00 5002h

00 5003h

00 5004h

00 5005h

00 5006h

00 5007h

00 5008h

00 5009h

00 500Ah

00 500Bh

00 500Ch

00 500Dh

00 500Eh

00 500Fh

00 5010h

00 5011h

00 5012h

00 5013h

00 5014h

00 5015h

00 5016h

00 5017h

00 5018h

00 5019h

00 501Ah

00 501Bh

00 501Ch

00 501Dh

PA_ODR

PA_IDR

Port A data output latch register

Port A input pin value register

Port A data direction register

Port A control register 1

00h

Port A

PA_DDR

PA_CR1

PA_CR2

PB_ODR

PB_IDR

PB_DDR

PB_CR1

PB_CR2

PC_ODR

PC_IDR

PC_DDR

PC_CR1

PC_CR2

PD_ODR

PD_IDR

PD_DDR

PD_CR1

PD_CR2

PE_ODR

PE_IDR

PE_DDR

PE_CR1

PE_CR2

PF_ODR

PF_IDR

PF_DDR

PF_CR1

PF_CR2

Port A control register 2

Port B data output latch register

Port B input pin value register

Port B data direction register

Port B control register 1

Port B

Port C

Port D

Port E

Port F

Port B control register 2

Port C data output latch register

Port C input pin value register

Port C data direction register

Port C control register 1

Port C control register 2

Port D data output latch register

Port D input pin value register

Port D data direction register

Port D control register 1

Port D control register 2

Port E data output latch register

Port E input pin value register

Port E data direction register

Port E control register 1

Port E control register 2

Port F data output latch register

Port F input pin value register

Port F data direction register

Port F control register 1

Port F control register 2

36/100

STM8AF61xx, STM8AF51xx

Table 9. STM8A I/O port hardware register map (continued)

Address Register name

Register mapping

Reset

status

Block

Register label

00 501Eh

00 501Fh

00 5020h

00 5021h

00 5022h

00 5023h

00 5024h

00 5025h

00 5026h

00 5027h

00 5028h

00 5029h

00 502Ah

00 502Bh

00 502Ch

PG_ODR

PG_IDR

PG_DDR

PG_CR1

PG_CR2

PH_ODR

PH_IDR

PH_DDR

PH_CR1

PH_CR2

PI_ODR

PI_IDR

Port G data output latch register

Port G input pin value register

Port G data direction register

Port G control register 1

00h

Port G

Port G control register 2

Port H data output latch register

Port H input pin value register

Port H data direction register

Port H control register 1

Port H

Port H control register 2

Port I data output latch register

Port I input pin value register

Port I data direction register

Port I control register 1

Port I

PI_DDR

PI_CR1

PI_CR2

Port I control register 2

37/100

Register mapping

STM8AF61xx, STM8AF51xx

Reset

Table 10. STM8A general hardware register map

Address

Block

Register label

Register name

status

00 5050h

to

00 5059h

Reserved area (10 bytes)

Flash control register 1

00 505Ah

00 505Bh

00 505Ch

00 505Dh

00 505Eh

FLASH_CR1

FLASH_CR2

FLASH_NCR2

FLASH _FPR

FLASH _NFPR

00h

FFh

00h

FFh

Flash control register 2

Flash complementary control register 2

Flash protection register

Flash

Flash complementary protection register

Flash in-application programming status

register

00 505Fh

FLASH _IAPSR

00h

00 5060h

to

Reserved area (2 bytes)

00 5061h

Flash program memory unprotection

register

00 5062h

Flash

FLASH _PUKR

FLASH _DUKR

00h

00 5063h

00 5064h

Reserved area (1 byte)

Data EEPROM unprotection register

00 5065h

to

Reserved area (59 bytes)

00 509Fh

00 50A0h

00 50A1h

EXTI_CR1

EXTI_CR2

External interrupt control register 1

External interrupt control register 2

00h

ITC

RST

CLK

00 50A2h

to

00 50B2h

Reserved area (17 bytes)

Reset status register

00 50B3h

RST_SR

xxh

00 50B4h

to

00 50BFh

Reserved area (12 bytes)

00 50C0h

00 50C1h

00 50C2h

CLK_ICKR

CLK_ECKR

Internal clock control register

External clock control register

Reserved area (1 byte)

01h

00h

38/100

STM8AF61xx, STM8AF51xx

Table 10. STM8A general hardware register map (continued)

Register mapping

Reset

status

Address

Block

Register label

Register name

00 50C3h

00 50C4h

CLK_CMSR

CLK_SWR

Clock master status register

Clock master switch register

E1h

xxxx

0000b

00 50C5h

CLK_SWCR

Clock switch control register

00 50C6h

00 50C7h

00 50C8h

00 50C9h

00 50CAh

00 50CBh

00 50CCh

00 50CDh

CLK_CKDIVR

CLK_PCKENR1

CLK_CSSR

Clock divider register

Peripheral clock gating register 1

Clock security system register

Configurable clock control register

Peripheral clock gating register 2

CAN clock control register

18h

FFh

00h

FFh

00h

xxh

x0h

CLK

CLK_CCOR

CLK_PCKENR2

CLK_CANCCR

CLK_HSITRIMR

CLK_SWIMCCR

HSI clock calibration trimming register

SWIM clock control register

00 50CEh

to

Reserved area (3 bytes)

00 50D0h

00 50D1h

00 50D2h

WWDG_CR

WWDG_WR

WWDG control register

WWDR window register

7Fh

WWDG

IWDG

00 50D3h

to

00 50DFh

Reserved area (13 bytes)

00 50E0h

00 50E1h

00 50E2h

IWDG_KR

IWDG_PR

IWDG_RLR

IWDG key register

IWDG prescaler register

IWDG reload register

-

00h

FFh

00 50E3h

to

Reserved area (13 bytes)

00 50EFh

00 50F0h

00 50F1h

AWU_CSR1

AWU_APR

AWU control/status register 1

00h

3Fh

AWU asynchronous prescaler buffer

register

AWU

00 50F2h

00 50F3h

AWU_TBR

AWU timebase selection register

BEEP control/status register

00h

1Fh

BEEP

BEEP_CSR

00 50F4h

to

Reserved area (12 bytes)

00 50FFh

39/100

Register mapping

STM8AF61xx, STM8AF51xx

Table 10. STM8A general hardware register map (continued)

Reset

status

Address

Block

Register label

Register name

00 5200h

00 5201h

00 5202h

00 5203h

00 5204h

00 5205h

00 5206h

00 5207h

SPI_CR1

SPI_CR2

SPI control register 1

SPI control register 2

SPI interrupt control register

SPI status register

00h

02h

00h

07h

FFh

SPI_ICR

SPI_SR

SPI

SPI_DR

SPI data register

SPI_CRCPR

SPI_RXCRCR

SPI_TXCRCR

SPI CRC polynomial register

SPI Rx CRC register

SPI Tx CRC register

00 5208h

to

Reserved area (8 bytes)

00 520Fh

00 5210h

00 5211h

00 5212h

00 5213h

00 5214h

00 5215h

00 5216h

00 5217h

00 5218h

00 5219h

00 521Ah

00 521Bh

00 521Ch

00 521Dh

00 521Eh

I2C_CR1

I2C_CR2

I²C control register 1

I²C control register 2

00h

I2C_FREQR

I2C_OARL

I2C_OARH

I²C frequency register

I²C own address register low

I²C own address register high

Reserved

I2C_DR

I2C_SR1

I²C data register

00h

02h

00h

I²C

I²C status register 1

I2C_SR2

I²C status register 2

I2C_SR3

I²C status register 3

I2C_ITR

I²C interrupt control register

I²C clock control register low

I²C clock control register high

I²C TRISE register

I2C_CCRL

I2C_CCRH

I2C_TRISER

I2C_PECR

I²C packet error checking register

00 521Fh

to

Reserved area (17 bytes)

00 522Fh

40/100

STM8AF61xx, STM8AF51xx

Table 10. STM8A general hardware register map (continued)

Register mapping

Reset

status

Address

Block

Register label

Register name

00 5230h

00 5231h

00 5232h

00 5233h

00 5234h

00 5235h

00 5236h

00 5237h

00 5238h

00 5239h

00 523Ah

USART_SR

USART_DR

USART status register

USART data register

C0h

xxh

USART_BRR1

USART_BRR2

USART_CR1

USART_CR2

USART_CR3

USART_CR4

USART_CR5

USART_GTR

USART_PSCR

USART baud rate register 1

USART baud rate register 2

USART control register 1

USART control register 2

USART control register 3

USART control register 4

USART control register 5

USART guard time register

USART prescaler register

00h

USART

00 523Bh

to

Reserved area (5 bytes)

00 523Fh

00 5240h

00 5241h

00 5242h

00 5243h

00 5244h

00 5245h

00 5246h

005247h

00 5248h

00 5249h

LINUART_SR

LINUART_DR

LINUART status register

LINUART data register

C0h

xxh

00h

LINUART_BRR1

LINUART_BRR2

LINUART_CR1

LINUART_CR2

LINUART_CR3

LINUART_CR4

LINUART baud rate register 1

LINUART baud rate register 2

LINUART control register 1

LINUART control register 2

LINUART control register 3

LINUART control register 4

Reserved

LINUART

LINUART_CR6

LINUART control register 6

00h

00 524Ah

to

Reserved area (6 bytes)

00 524Fh

41/100

Register mapping

STM8AF61xx, STM8AF51xx

Table 10. STM8A general hardware register map (continued)

Reset

status

Address

Block

Register label

Register name

00 5250h

00 5251h

00 5252h

00 5253h

00 5254h

00 5255h

00 5256h

00 5257h

00 5258h

00 5259h

00 525Ah

00 525Bh

00 525Ch

00 525Dh

00 525Eh

00 525Fh

00 5260h

00 5261h

00 5262h

00 5263h

00 5264h

00 5265h

00 5266h

00 5267h

00 5268h

00 5269h

00 526Ah

00 526Bh

00 526Ch

00 526Dh

00 526Eh

00 526Fh

TIM1_CR1

TIM1_CR2

TIM1 control register 1

TIM1 control register 2

00h

FFh

00h

TIM1_SMCR

TIM1_ETR

TIM1 slave mode control register

TIM1 external trigger register

TIM1 interrupt enable register

TIM1 status register 1

TIM1_IER

TIM1_SR1

TIM1_SR2

TIM1 status register 2

TIM1_EGR

TIM1 event generation register

TIM1 capture/compare mode register 1

TIM1 capture/compare mode register 2

TIM1 capture/compare mode register 3

TIM1 capture/compare mode register 4

TIM1 capture/compare enable register 1

TIM1 capture/compare enable register 2

TIM1 counter high

TIM1_CCMR1

TIM1_CCMR2

TIM1_CCMR3

TIM1_CCMR4

TIM1_CCER1

TIM1_CCER2

TIM1_CNTRH

TIM1_CNTRL

TIM1_PSCRH

TIM1_PSCRL

TIM1_ARRH

TIM1_ARRL

TIM1_RCR

TIM1 counter low

TIM1

TIM1 prescaler register high

TIM1 prescaler register low

TIM1 auto-reload register high

TIM1 auto-reload register low

TIM1 repetition counter register

TIM1 capture/compare register 1 high

TIM1 capture/compare register 1 low

TIM1 capture/compare register 2 high

TIM1 capture/compare register 2 low

TIM1 capture/compare register 3 high

TIM1 capture/compare register 3 low

TIM1 capture/compare register 4 high

TIM1 capture/compare register 4 low

TIM1 break register

TIM1_CCR1H

TIM1_CCR1L

TIM1_CCR2H

TIM1_CCR2L

TIM1_CCR3H

TIM1_CCR3L

TIM1_CCR4H

TIM1_CCR4L

TIM1_BKR

TIM1_DTR

TIM1 dead-time register

TIM1_OISR

TIM1 output idle state register

00 5270h

to

Reserved area (147 bytes)

00 52FFh

42/100

STM8AF61xx, STM8AF51xx

Table 10. STM8A general hardware register map (continued)

Register mapping

Reset

status

Address

Block

Register label

Register name

00 5300h

00 5301h

00 5302h

00 5303h

00 5304h

00 5305h

00 5306h

00 5307h

00 5308h

00 5309h

00 530Ah

00 530Bh

00 530Ch

00 530Dh

00 530Eh

00 530Fh

00 5310h

00 5311h

00 5312h

00 5313h

00 5314h

TIM2_CR1

TIM2_IER

TIM2 control register 1

00h

TIM2 interrupt enable register

TIM2 status register 1

00h

FFh

00h

TIM2_SR1

TIM2_SR2

TIM2 status register 2

TIM2_EGR

TIM2 event generation register

TIM2 capture/compare mode register 1

TIM2 capture/compare mode register 2

TIM2 capture/compare mode register 3

TIM2 capture/compare enable register 1

TIM2 capture/compare enable register 2

TIM2 counter high

TIM2_CCMR1

TIM2_CCMR2

TIM2_CCMR3

TIM2_CCER1

TIM2_CCER2

TIM2_CNTRH

TIM2_CNTRL

TIM2_PSCR

TIM2_ARRH

TIM2_ARRL

TIM2_CCR1H

TIM2_CCR1L

TIM2_CCR2H

TIM2_CCR2L

TIM2_CCR3H

TIM2_CCR3L

TIM2

TIM2 counter low

TIM2 prescaler register

TIM2 auto-reload register high

TIM2 auto-reload register low

TIM2 capture/compare register 1 high

TIM2 capture/compare register 1 low

TIM2 capture/compare register 2 high

TIM2 capture/compare register 2 low

TIM2 capture/compare register 3 high

TIM2 capture/compare register 3 low

00 5315h

to

Reserved area (11 bytes)

00 531Fh

43/100

Register mapping

STM8AF61xx, STM8AF51xx

Table 10. STM8A general hardware register map (continued)

Reset

status

Address

Block

Register label

Register name

00 5320h

00 5321h

00 5322h

00 5323h

00 5324h

00 5325h

00 5326h

00 5327h

00 5328h

00 5329h

00 532Ah

00 532Bh

00 532Ch

00 532Dh

00 532Eh

00 532Fh

00 5330h

TIM3_CR1

TIM3_IER

TIM3 control register 1

TIM3 interrupt enable register

TIM3 status register 1

00h

FFh

00h

TIM3_SR1

TIM3_SR2

TIM3 status register 2

TIM3_EGR

TIM3 event generation register

TIM3 capture/compare mode register 1

TIM3 capture/compare mode register 2

TIM3 capture/compare enable register 1

TIM3 counter high

TIM3_CCMR1

TIM3_CCMR2

TIM3_CCER1

TIM3_CNTRH

TIM3_CNTRL

TIM3_PSCR

TIM3_ARRH

TIM3_ARRL

TIM3_CCR1H

TIM3_CCR1L

TIM3_CCR2H

TIM3_CCR2L

TIM3

TIM3 counter low

TIM3 prescaler register

TIM3 auto-reload register high

TIM3 auto-reload register low

TIM3 capture/compare register 1 high

TIM3 capture/compare register 1 low

TIM3 capture/compare register 2 high

TIM3 capture/compare register 2 low

00 5331h

to

Reserved area (15 bytes)

00 533Fh

00 5340h

00 5341h

00 5342h

00 5343h

00 5344h

00 5345h

00 5346h

TIM4_CR1

TIM4_IER

TIM4 control register 1

TIM4 interrupt enable register

TIM4 status register

00h

FFh

TIM4_SR

TIM4

TIM4_EGR

TIM4_CNTR

TIM4_PSCR

TIM4_ARR

TIM4 event generation register

TIM4 counter

TIM4 prescaler register

TIM4 auto-reload register

00 5347h

to

Reserved area (184 bytes)

00 53FFh

44/100

STM8AF61xx, STM8AF51xx

Table 10. STM8A general hardware register map (continued)

Register mapping

Reset

status

Address

Block

Register label

Register name

00 5400h

00 5401h

00 5402h

00 5403h

00 5404h

00 5405h

00 5406h

00 5407h

ADC _CSR

ADC_CR1

ADC_CR2

ADC_CR3

ADC_DRH

ADC_DRL

ADC_TDRH

ADC_TDRL

ADC control/status register

ADC configuration register 1

ADC configuration register 2

ADC configuration register 3

ADC data register high

00h

ADC

ADC data register low

ADC Schmitt trigger disable register high

ADC Schmitt trigger disable register low

00 5408h

to

Reserved area (24 bytes)

00 541Fh

00 5420h

00 5421h

00 5422h

00 5423h

00 5424h

00 5425h

00 5426h

00 5427h

00 5428h

00 5429h

00 542Ah

00 542Bh

00 542Ch

00 542Dh

00 542Eh

00 542Fh

00 5430h

00 5431h

00 5432h

00 5433h

00 5434h

00 5435h

00 5436h

00 5437h

CAN_MCR

CAN_MSR

CAN_TSR

CAN_TPR

CAN_RFR

CAN_IER

CAN_DGR

CAN_FPSR

CAN_P0

CAN_P1

CAN_P2

CAN_P3

CAN_P4

CAN_P5

CAN_P6

CAN_P7

CAN_P8

CAN_P9

CAN_PA

CAN_PB

CAN_PC

CAN_PD

CAN_PE

CAN_PF

CAN master control register

CAN master status register

CAN transmit status register

CAN transmit priority register

CAN receive FIFO register

CAN interrupt enable register

CAN diagnosis register

CAN page selection register

CAN paged register 0

CAN paged register 1

CAN paged register 2

CAN paged register 3

CAN paged register 4

CAN paged register 5

CAN paged register 6

CAN paged register 7

CAN paged register 8

CAN paged register 9

CAN paged register A

CAN paged register B

CAN paged register C

CAN paged register D

CAN paged register E

CAN paged register F

02h

00h

0Ch

00h

0Ch

00h

CAN

45/100

Register mapping

STM8AF61xx, STM8AF51xx

Table 10. STM8A general hardware register map (continued)

Reset

status

Address

Block

Register label

Register name

00 5438h to

00 57FFh

Reserved area (968 bytes)

5800h

5801h

5802h

5803h

5804h

5805h

5806h

5807h

5808h

TU_KEYS_REG0

TU_KEYS_REG1

TU_KEYS_REG2

TU_KEYS_REG3

TU_KEYS_REG4

TU_KEYS_REG5

TU_KEYS_REG6

TU_KEYS_REG7

TU_CTL_ST

TMU key register 1 [7:0]

TMU key register 2 [7:0]

TMU key register 3 [7:0]

TMU key register 4 [7:0]

TMU key register 5 [7:0]

TMU key register 6 [7:0]]

TMU key register 7 [7:0]

TMU key register 8 [7:0]

TMU control and status register

00h

TMU

46/100

STM8AF61xx, STM8AF51xx

Register mapping

Table 11. CPU/SWIM/debug module/interrupt controller registers

Reset

status

Address

Block

Register label

Register name

00 7F00h

00 7F01h

00 7F02h

00 7F03h

00 7F04h

00 7F05h

00 7F06h

00 7F07h

00 7F08h

00 7F09h

00 7F0Ah

A

Accumulator

Program counter extended

Program counter high

Program counter low

X index register high

X index register low

Y index register high

Y index register low

Stack pointer high

00h

60h

00h

17h

FFh

28h

PCE

PCH

PCL

XH

XL

CPU

YH

YL

SPH

SPL

CCR

Stack pointer low

Condition code register

00 7F0Bh to

00 7F5Fh

Reserved area (85 bytes)

00 7F60h

00 7F70h

00 7F71h

00 7F72h

00 7F73h

00 7F74h

00 7F75h

00 7F76h

CFG

ITC

CFG_GCR

ITC_SPR1

ITC_SPR2

ITC_SPR3

ITC_SPR4

ITC_SPR5

ITC_SPR6

ITC_SPR7

Global configuration register

Interrupt software priority register 1

Interrupt software priority register 2

Interrupt software priority register 3

Interrupt software priority register 4

Interrupt software priority register 5

Interrupt software priority register 6

Interrupt software priority register 7

00h

FFh

00 7F77h

to

00 7F79h

Reserved area (3 bytes)

SWIM control status register

Reserved area (15 bytes)

00 7F80h

SWIM

SWIM_CSR

00h

00 7F81h

to

00 7F8Fh

47/100

Register mapping

STM8AF61xx, STM8AF51xx

Table 11. CPU/SWIM/debug module/interrupt controller registers (continued)

Reset

status

Address

Block

Register label

Register name

00 7F90h

00 7F91h

00 7F92h

00 7F93h

00 7F94h

00 7F95h

00 7F96h

00 7F97h

00 7F98h

00 7F99h

00 7F9Ah

DM_BK1RE

DM_BK1RH

DM_BK1RL

DM_BK2RE

DM_BK2RH

DM_BK2RL

DM_CR1

DM breakpoint 1 register extended byte

DM breakpoint 1 register high byte

DM breakpoint 1 register low byte

DM breakpoint 2 register extended byte

DM breakpoint 2 register high byte

DM breakpoint 2 register low byte

Debug module control register 1

Debug module control register 2

Debug module control/status register 1

Debug module control/status register 2

DM enable function register

FFh

00h

10h

00h

FFh

DM

DM_CR2

DM_CSR1

DM_CSR2

DM_ENFCTR

00 7F9Bh

to

Reserved area (5 bytes)

00 7F9Fh

48/100

STM8AF61xx, STM8AF51xx

Option bytes

10

Option bytes

Option bytes contain configurations for device hardware features as well as the memory protection of the

device. They are stored in a dedicated block of the memory. Each option byte has to be stored twice, for

redundancy, in a regular form (OPTx) and a complemented one (NOPTx), except for the ROP (read-out

protection) option byte and option bytes 8 to 16.

Option bytes can be modified in ICP mode (via SWIM) by accessing the EEPROM address shown in

Table 12: Option bytes below.

Option bytes can also be modified ‘on the fly’ by the application in IAP mode, except the ROP and UBC

options that can only be toggled in ICP mode (via SWIM).

Refer to the STM8 Flash programming manual (PM0047) and STM8 SWIM communication protocol and

debug modulel user manual (UM0470) for information on SWIM programming procedures.

Table 12. Option bytes

Option bits

Factory

default

setting

Option

name

Option

byte no.

Addr.

7

6

5

4

3

2

1

0

Read-out

4800h protection OPT0

(ROP)

ROP[7:0]

00h

4801h User

boot code

OPT1

UBC[7:0]

00h

FFh

00h

4802h

NOPT1

NUBC[7:0]

(UBC)

4803h Alternate OPT2

function

AFR7 AFR6 AFR5

NAFR NAFR

AFR4

AFR3

AFR2

AFR1

AFR0

remappin

g (AFR)

4804h

NOPT2

NAFR5 NAFR4 NAFR3 NAFR2 NAFR1 NAFR0

FFh

7

6

LSI

_EN

IWDG WWDG WWDG

_HW _HW _HALT

4805h

4806h

4807h

4808h

OPT3

Reserved

00h

FFh

00h

FFh

Watchdog

option

NLSI

_EN

NIWDG NWWD NWWG

_HW G_HW _HALT

NOPT3

OPT4

Reserved

EXT

CLK

CKAWU PRS

SEL C1

PRS

C0

Clock

option

NEXT NCKAW NPR

CLK

NPR

SC0

NOPT4

USEL

SC1

4809h HSE

clock

OPT5

HSECNT[7:0]

00h

FFh

480Ah

NOPT5

NHSECNT[7:0]

startup

480Bh

480Ch

OPT6

TMU[3:0]

00h

FFh

TMU

NOPT6

NTMU[3:0]

WAIT

STATE

480Dh

OPT7

Reserved

00h

FFh

Flashwait

states

NWAIT

STATE

480Eh

480Fh

NOPT7

Reserved

49/100

Option bytes

STM8AF61xx, STM8AF51xx

Table 12. Option bytes (continued)

Option bits

Factory

default

setting

Option

name

Option

byte no.

Addr.

7

6

5

4

3

2

1

0

4810h

4811h

4812h

4813h

4814h

4815h

4816h

4817h

4818h

OPT8

TMU_KEY 1 [7:0]

TMU_KEY 2 [7:0]

TMU_KEY 3 [7:0]

TMU_KEY 4 [7:0]

TMU_KEY 5 [7:0]

TMU_KEY 6 [7:0]

TMU_KEY 7 [7:0]

TMU_KEY 8 [7:0]

TMU MAX_ATT [7:0]

00h

OPT9

OPT10

OPT11

OPT12

OPT13

OPT14

OPT15

OPT16

TMU

4819h

to

Reserved

487D

487E

487F

OPT17

BL_EN [7:0]

00h

Boot-

loader

NOPT17

NBL_EN [7:0]

50/100

STM8AF61xx, STM8AF51xx

Option bytes

Table 13. Option byte description

Option byte no.

Description

ROP[7:0]: Memory readout protection (ROP)

AAh: Enable readout protection (write access via SWIM protocol)

Note: Refer to the STM8A microcontroller family reference manual

(RM0009) section on Flash/EEPROM memory readout protection for

details.

OPT0

UBC[7:0]: User boot code area

00h: No UBC, no write-protection

01h: Page 0 to 1 defined as UBC, memory write-protected

02h: Page 0 to 3 defined as UBC, memory write-protected

03h to FFh: Pages 4 to 255 defined as UBC, memory write-protected

Note: Refer to the STM8A microcontroller family reference manual

(RM0009) section on Flash/EEPROM write protection for more details.

OPT1

AFR7: Alternate function remapping option 7

0: Port D4 alternate function = TIM2_CC1

1: Port D4 alternate function = BEEP

AFR6: Alternate function remapping option 6

0: Port B5 alternate function = AIN5, port B4 alternate function = AIN4

1: Port B5 alternate function = I²C_SDA, port B4 alternate function =

I²C_SCL.

AFR5: Alternate function remapping option 5

0: Port B3 alternate function = AIN3, port B2 alternate function = AIN2,

port B1 alternate function = AIN1, port B0 alternate function = AIN0.

1: Port B3 alternate function = TIM1_ETR, port B2 alternate function =

TIM1_NCC3, port B1 alternate function = TIM1_NCC2, port B0 alternate

function = TIM1_NCC1.

AFR4: Alternate function remapping option 4

0: Port D7 alternate function = TLI

1: Port D7 alternate function = TIM1_CC4

OPT2

AFR3: Alternate function remapping option 3

0: Port D0 alternate function = TIM3_CC2

1: Port D0 alternate function = TIM1_BKIN

AFR2: Alternate function remapping option 2

0: Port D0 alternate function = TIM3_CC2

1: Port D0 alternate function = CLK_CCO

Note: AFR2 option has priority over AFR3 if both are activated

AFR1: Alternate function remapping option 1

0: Port A3 alternate function = TIM2_CC3, port D2 alternate function

TIM3_CC1.

1: Port A3 alternate function = TIM3_CC1, port D2 alternate function

TIM2_CC3.

AFR0: Alternate function remapping option 0

0: Port D3 alternate function = TIM2_CC2

1: Port D3 alternate function = ADC_ETR

51/100

Option bytes

Table 13. Option byte description (continued)

STM8AF61xx, STM8AF51xx

Option byte no.

Description

LSI_EN: Low speed internal clock enable

0: LSI clock is not available as CPU clock source

1: LSI clock is available as CPU clock source

IWDG_HW: Independent watchdog

0: IWDG Independent watchdog activated by software

1: IWDG Independent watchdog activated by hardware

OPT3

WWDG_HW: Window watchdog activation

0: WWDG window watchdog activated by software

1: WWDG window watchdog activated by hardware

WWDG_HALT: Window watchdog reset on halt

0: No reset generated on halt if WWDG active

1: Reset generated on halt if WWDG active

EXTCLK: External clock selection

0: External crystal connected to OSCIN/OSCOUT

1: External clock signal on OSCIN

CKAWUSEL: Auto wake-up unit/clock

0: LSI clock source selected for AWU

1: HSE clock with prescaler selected as clock source for for AWU

OPT4

PRSC[1:0]: AWU clock prescaler

00: 24 MHz to 128 kHz prescaler

01: 16 MHz to 128 kHz prescaler

10: 8 MHz to 128 kHz prescaler

11: 4 MHz to 128 kHz prescaler

HSECNT[7:0]: HSE crystal oscillator stabilization time

OPT5

OPT6

This configures the stabilisation time to 0.5, 8, 128, and 2048 HSE

cycles with corresponding option byte values of E1h, D2h, B4h, and 00h.

TMU[3:0]: Enable temporary memory unprotection

0101: TMU disabled (permanent ROP).

Any other value: TMU enabled.

WAIT STATE: Wait state configuration

This option configures the number of wait states inserted when reading

from the Flash/data EEPROM memory.

0: No wait state

OPT7

1: One wait state

TMU_KEY 1 [7:0]: Temporary unprotection key 0

OPT8

OPT9

Temporary unprotection key: Must be different from 00h or FFh

TMU_KEY 2 [7:0]: Temporary unprotection key 1

Temporary unprotection key: Must be different from 00h or FFh

TMU_KEY 3 [7:0]: Temporary unprotection key 2

OPT10

OPT11

Temporary unprotection key: Must be different from 00h or FFh

TMU_KEY 4 [7:0]: Temporary unprotection key 3

Temporary unprotection key: Must be different from 00h or FFh

52/100

STM8AF61xx, STM8AF51xx

Table 13. Option byte description (continued)

Option bytes

Option byte no.

Description

TMU_KEY 5 [7:0]: Temporary unprotection key 4

OPT12

Temporary unprotection key: Must be different from 00h or FFh

TMU_KEY 6 [7:0]: Temporary unprotection key 5

OPT13

OPT14

OPT15

Temporary unprotection key: Must be different from 00h or FFh

TMU_KEY 7 [7:0]: Temporary unprotection key 6

Temporary unprotection key: Must be different from 00h or FFh

TMU_KEY 8 [7:0]: Temporary unprotection key 7

Temporary unprotection key: Must be different from 00h or FFh

TMU_MAXATT [7:0]: TMU access failure counter

Every unsuccessful trial to enter the temporary unprotection procedure

increments the counter. More than eight unsuccessful trials trigger the

global erase of the code and data memory.

OPT16

OPT17

BL_EN [7:0]: Bootloader enable

If this optionbyte is set to 55h (complementary value AAh) the bootloader

program is activated also in case of a programmed code memory

(for more details, see the bootloader user manual, UM0500).

53/100

Electrical characteristics

STM8AF61xx, STM8AF51xx

11

Electrical characteristics

11.1

Parameter conditions

Unless otherwise specified, all voltages are referred to V

.

SS

11.1.1

Minimum and maximum values

Unless otherwise specified the minimum and maximum values are guaranteed in the worst

conditions of ambient temperature, supply voltage and frequencies by tests in production on

100 % of the devices with an ambient temperature at T = 25 °C and T = T (given by

A

Amax

the selected temperature range).

Data based on characterization results, design simulation and/or technology characteristics

are indicated in the table footnotes and are not tested in production.

11.1.2

Typical values

Unless otherwise specified, typical data are based on T = 25 °C, V = 5.0 V. They are

A

DD

given only as design guidelines and are not tested.

Typical ADC accuracy values are determined by characterization of a batch of samples from

a standard diffusion lot over the full temperature range^.

11.1.3

11.1.4

Typical curves

Unless otherwise specified, all typical curves are given only as design guidelines and are

not tested.

Loading capacitor

The loading conditions used for pin parameter measurement are shown in Figure 8.

Figure 8.

Pin loading conditions

STM8A pin

50 pF

54/100

STM8AF61xx, STM8AF51xx

Electrical characteristics

11.1.5

Pin input voltage

The input voltage measurement on a pin of the device is described in Figure 9.

Figure 9. Pin input voltage

STM8A pin

V

IN

11.2

Absolute maximum ratings

Stresses above those listed as ‘absolute maximum ratings’ may cause permanent damage

to the device. This is a stress rating only and functional operation of the device under these

conditions is not implied. Exposure to maximum rating conditions for extended periods may

affect device reliability.

Table 14. Voltage characteristics

Symbol

Ratings

Min

Max

Unit

(1)

V_DDx- V_SS

-0.3

6.5

Supply voltage (including V_{DDA and}V_DDIO

)

Input voltage on true open drain pins (PE1, PE2)⁽²⁾

V_SS- 0.3

V

6.5

V_DD+ 0.3

50

V_IN

Input voltage on any other pin⁽²⁾

|V_DDx- V_SS

|

Variations between different power pins

|

Variations between all the different ground pins

mV

|V_SSx- V_SS

50

see Absolute maximum

ratings (electrical

V_ESD

Electrostatic discharge voltage

sensitivity) on page 86

1. All power (V_DD, V_DDIO, V_DDA) and ground (V_SS, V_SSIO, V_SSA) pins must always be connected to the

external power supply

2. I_INJ(PIN)must never be exceeded. This is implicitly insured if V_INmaximum is respected. If V_INmaximum

cannot be respected, the injection current must be limited externally to the I_INJ(PIN)value. A positive

injection is induced by V_IN> V_DDwhile a negative injection is induced by V_IN< V_SS. For true open-drain

pads, there is no positive injection current, and the corresponding V_INmaximum must always be respected

55/100

Electrical characteristics

STM8AF61xx, STM8AF51xx

Table 15. Current characteristics

Symbol

I_VDD

Ratings

Max.

60

Unit

Total current into V_DDpower lines (source)⁽¹⁾⁽²⁾

Total current out of V_SSground lines (sink)⁽¹⁾⁽²⁾

I_VSS

60

Output current sunk by any I/O and control pin

Output current source by any I/Os and control pin

Injected current on NRST pin

20

- 20

10

I_IO

mA

(3)

Injected current on OSCIN pin

10

I_INJ(PIN)

Injected current on any other pin

10

(4)

Total injected current (sum of all I/O and control pins)

20

ΣI_INJ(PIN)

1. All power (V_DD, V_DDIO, V_DDA) and ground (V_SS, V_SSIO, V_SSA) pins must always be connected to the

external supply.

2. The total limit applies to the sum of operation and injected currents.

3. I_INJ(PIN)must never be exceeded. This is implicitly insured if V_INmaximum is respected. If V_INmaximum

cannot be respected, the injection current must be limited externally to the I_INJ(PIN)value. A positive

injection is induced by V_IN> V_DDwhile a negative injection is induced by V_IN< V_SS. For true open-drain

pads, there is no positive injection current allowed and the corresponding V_INmaximum must always be

respected.

4. When several inputs are submitted to a current injection, the maximum ΣI_INJ(PIN)is the sum of the absolute

positive and negative injected currents (instantaneous values). These results are based on

characterization with ΣI_INJ(PIN)maximum current injection on four I/O port pins of the device.

Table 16. Thermal characteristics

Symbol

T_STG

T_J

Ratings

Value

-65 to +150

150

Unit

Storage temperature range

Maximum junction temperature

°C

56/100

STM8AF61xx, STM8AF51xx

Electrical characteristics

11.3

Operating conditions

Table 17. General operating conditions

Symbol

Parameter

Conditions

Min

Max

Unit

T_A≤105 °C

T_A> 105 °C

0

24

16

f_CPU

Internal CPU clock frequency

Standard operating voltage

MHz

0

V

_DD/V_{DD_IO}

3.0

-40

5.5

85

V

Suffix A

Suffix B

°C

105

125

145

90

T_A

Ambient temperature

Suffix C

Suffix D

A suffix version

B suffix version

C suffix version

D suffix version

110

130

150

T_J

Junction temperature range

Figure 10. f

versus V

CPUmax

DD

f_CPU[MHz]

24

Functionality guaranteed

@ T_A-40 to 105 ¬×

Functionality

not guaranteed

in this area

16

12

8

Functionality

guaranteed

@ T_A-40 to 125 ¬×

4

0

3.0

4.0

5.0

5.5

Supply voltage [V]

57/100

Electrical characteristics

STM8AF61xx, STM8AF51xx

Table 18. Operating conditions at power-up/power-down

Symbol

Parameter

Conditions

Min

Max Unit

Typ

20⁽¹⁾

20⁽²⁾

V_DDrise time rate

V_DDfall time rate⁽³⁾

∞

t_VDD

µs/V

∞

Reset release

delay

TBD⁽²⁾

2.65

V_DDrising

3

ms

µs

t_TEMP

Reset generation

delay⁽³⁾

V_DDfalling

3

Power-on reset

threshold

V_IT+

V_IT-

2.8

2.73

70⁽¹⁾

2.95

2.88

V

Brown-out reset

threshold

2.58

Brown-out reset

hysteresis

V_HYS(BOR)

mV

1. Guaranteed by design, not tested in production

2. TBD = To be determined

3. Reset is always generated after a t_TEMPdelay. The application must ensure that V_DDis still above the

minimum operating voltage (V_DDmin) when the t_TEMPdelay has elapsed.

11.3.1

Supply current characteristics

The current consumption is measured as described in Figure 8 on page 54 and Figure 9 on

page 55.

Total current consumption

The MCU is placed under the following conditions:

●

All I/O pins in input mode with a static value at V or V (no load)

DD SS

●

All peripherals are disabled except if explicitly mentioned.

Subject to general operating conditions for V and T .

DD

A

Note on the run-current typical and worst-case values

●

Typical device currents values are representative of an application set-up without any

I/O activity at 25 °C. The worst case values correspond to the actual test-limits and

include both internal and external device I/O current.

During the execution of an actual application program, the number of read access

cycles to the code memory depends on its structure. A code doing arithmetical

calculations reads the memory less frequently than programs with jump, loop or data

manipulation instructions. The fast-reading access in a Flash memory needs much

more power compared to a RAM. Consequently, the run-current for EEPROM

execution depends strongly on the actual application code structure. The

measurements in the tables below were made using a short, representative code with

move, jump and arithmetic operations. The worst case, an infinite loop of ‘while’

instructions takes approximately 25 % more power. For RAM execution, such power to

program structure relations has not been observed.

58/100

STM8AF61xx, STM8AF51xx

Electrical characteristics

Table 19. Total current consumption in run, wait and slow mode at V = 5.0 V

DD

Symbol Parameter

Conditions

Typ

Max

Unit

HSE Crystal oscillator

f_CPU= f_MASTER= 24 MHz

4.4

HSE external clock

3.8

3.3

f

_CPU= f_MASTER= 24 MHz

HSE Crystal oscillator

_CPU= f_MASTER= 16 MHz

Supply

All peripherals off,

f

I_DD(RUN)current in code executed

mA

HSE external clock

f_CPU= f_MASTER= 16 MHz

run mode from RAM

6.0⁽¹⁾

2.7

HSI internal RC

f_CPU= f_MASTER= 16 MHz

2.55

1.2

HSI internal RC 16 MHz/8

f

_CPU= f_MASTER= 2 MHz

HSE Crystal oscillator

f_CPU= f_MASTER= 24 MHz

11.4

10.8

9.0

HSE external clock

f

_CPU= f_MASTER= 24 MHz

HSE Crystal oscillator

f_CPU= f_MASTER= 16 MHz

Supply

All peripherals off,

I_DD(RUN)

current in code executed

run mode from EEPROM

mA

HSE external clock

f_CPU= f_MASTER= 16 MHz

15.0⁽¹⁾

8.35

8.2

HSI internal RC

f_CPU= f_MASTER= 16 MHz

HSI internal RC 16 MHz/8

1.9

f

_CPU= f_MASTER= 2 MHz

HSE Crystal oscillator

f_CPU= f_MASTER= 24 MHz

6.9

HSE external clock

6.3

f

_CPU= f_MASTER= 24 MHz

HSE Crystal oscillator

f_CPU= f_MASTER= 16 MHz

4.3

Supply

All peripherals on,

I_DD(RUN)

current in code executed

run mode from RAM

mA

HSE external clock

8.0⁽¹⁾

3.7

f

_CPU= f_MASTER= 16 MHz

HSI internal RC

f_CPU= f_MASTER= 16 MHz

3.5

HSI internal RC 16 MHz/8

1.2

f

_CPU= f_MASTER= 2 MHz

59/100

Electrical characteristics

STM8AF61xx, STM8AF51xx

Table 19. Total current consumption in run, wait and slow mode at V = 5.0 V

DD

Symbol Parameter

Conditions

Typ

Max

Unit

HSE Crystal oscillator

f_CPU= f_MASTER= 24 MHz

13.9

HSE external clock

13.3

10.0

9.35

9.2

f

_CPU= f_MASTER= 24 MHz

HSE Crystal oscillator

Supply

All peripherals on,

current in code executed

run mode from EEPROM

f

_CPU= f_MASTER= 16 MHz

I_DD(RUN)

mA

HSE external clock

f

_CPU= f_MASTER= 16 MHz

HSI internal RC

f

_CPU= f_MASTER= 16 MHz

HSI internal RC 16 MHz/8

f_CPU= f_MASTER= 2 MHz

2.1

HSE Crystal oscillator

f_CPU= f_MASTER= 24 MHz

2.4

HSE external clock

1.8

f

_CPU= f_MASTER= 24 MHz

HSE Crystal oscillator

2.0

Supply

f

_CPU= f_MASTER= 16 MHz

CPU not clocked,

current in

I_DD(WFI)

mA

all peripherals off

wait mode

HSE external clock

4.0⁽¹⁾

1.38

1.21

1.05

1.15

1.04

0.5

f

_CPU= f_MASTER= 16 MHz

HSI internal RC

f_CPU= f_MASTER= 16 MHz

HSI internal RC 16 MHz/8

f_CPU= f_MASTER= 2 MHz

HSE external clock 16 MHz/128

f_CPU= f_MASTER= 0.125 MHz

4.0⁽¹⁾

f_CPUscaled down,

HSI internal RC 16 MHz/128

all peripherals off,

code executed

from RAM

f

_CPU= f_MASTER= 0.125 MHz

LSI internal RC 128 kHz

Supply

f

_CPU= f_MASTER= 0.128 MHz

I_DD(SLOW)

current in

slow mode

mA

HSE external clock 16 MHz/128

f_CPU= f_MASTER= 0.125 MHz

1.21

1.09

0.56

f_CPUscaled down,

HSI internal RC 16 MHz/128

f_CPU= f_MASTER= 0.125 MHz

all peripherals off,

code executed

from EEPROM

LSI internal RC 128 kHz

f

_CPU= f_MASTER= 0.128 MHz

1. Prodution test limits

60/100

STM8AF61xx, STM8AF51xx

Electrical characteristics

Table 20. Total current consumption and timing in halt, fast active halt and slow

active halt modes at V = 5.0 V

DD

Symbol

Parameter

Conditions

Typ

Max

Unit

10⁽¹⁾

Flash powered down

6.5

I_DD(H)

Supply current in halt mode

Flash in stand-by mode

Crystal osc 16 MHz/128

HSE osc 16 MHz/128

LSI RC 128 kHz

64

1050

490

150

Supply current in fast active halt

mode

µA

I_DD(FAH)

200⁽¹⁾

30⁽¹⁾

Supply current in slow active halt

mode

I_DD(SAH)

t_WU(FAH)

t_WU(SAH)

LSI RC 128 kHz

11

Wake-up time from fast active halt

mode to run mode

2⁽²⁾

µs

Wake-up time from slow active

halt mode to run mode

100⁽²⁾

1. Maximum values at 55 °C, tested in production according to the actual product temperature ranges.

2. Data based on characterization results, not tested in production.

Table 21. Total current consumption in run, wait and slow mode at V = 3.3 V

DD

Symbol Parameter

Conditions

Typ

Max

Unit

HSE Crystal oscillator

f_CPU= f_MASTER= 24 MHz

4

HSE external clock

3.8

2.9

f

_CPU= f_MASTER= 24 MHz

HSE Crystal oscillator

_CPU= f_MASTER= 16 MHz

Supply

All peripherals off,

f

I_DD(RUN)current in code executed

mA

HSE external clock

f_CPU= f_MASTER= 16 MHz

run mode from RAM

2.7

HSI internal RC

f_CPU= f_MASTER= 16 MHz

2.55

1.2

HSI internal RC 16 MHz/8

f

_CPU= f_MASTER= 2 MHz

61/100

Electrical characteristics

STM8AF61xx, STM8AF51xx

Table 21. Total current consumption in run, wait and slow mode at V = 3.3 V

DD

Symbol Parameter

Conditions

Typ

Max

Unit

HSE Crystal oscillator

f_CPU= f_MASTER= 24 MHz

11.0

HSE external clock

10.8

8.6

f

_CPU= f_MASTER= 24 MHz

HSE Crystal oscillator

Supply

All peripherals off,

current in code executed

run mode from EEPROM

f

_CPU= f_MASTER= 16 MHz

I_DD(RUN)

mA

HSE external clock

_CPU= f_MASTER= 16 MHz

8.35

8.2

f

HSI internal RC

_CPU= f_MASTER= 16 MHz

f

HSI internal RC 16 MHz/8

f_CPU= f_MASTER= 2 MHz

1.6

HSE Crystal oscillator

f_CPU= f_MASTER= 24 MHz

6.5

HSE external clock

_CPU= f_MASTER= 24 MHz

6.3

f

HSE Crystal oscillator

_CPU= f_MASTER= 16 MHz

3.9

Supply

current in code executed

run mode from RAM

All peripherals on,

f

mA

HSE external clock

_CPU= f_MASTER= 16 MHz

3.7

f

HSI internal RC

f_CPU= f_MASTER= 16 MHz

3.55

1.4

HSI internal RC 16 MHz/8

f_CPU= f_MASTER= 2 MHz

HSE Crystal oscillator

f_CPU= f_MASTER= 24 MHz

13.5

13.3

9.6

HSE external clock

_CPU= f_MASTER= 24 MHz

f

HSE Crystal oscillator

_CPU= f_MASTER= 16 MHz

Supply

current in code executed

All peripherals on,

f

mA

HSE external clock

f_CPU= f_MASTER= 16 MHz

run mode from EEPROM

9.35

9.2

HSI internal RC

f_CPU= f_MASTER= 16 MHz

HSI internal RC 16 MHz/8

1.8

f

_CPU= f_MASTER= 2 MHz

62/100

STM8AF61xx, STM8AF51xx

Electrical characteristics

Table 21. Total current consumption in run, wait and slow mode at V = 3.3 V

DD

Symbol Parameter

Conditions

Typ

Max

Unit

HSE Crystal oscillator

f_CPU= f_MASTER= 24 MHz

2.0

HSE external clock

1.8

1.6

f

_CPU= f_MASTER= 24 MHz

HSE Crystal oscillator

Supply

current in

wait mode

f

_CPU= f_MASTER= 16 MHz

CPU not clocked,

all peripherals off

I_DD(WFI)

mA

HSE external clock

1.38

1.21

1.05

1.15

1.04

0.5

f

_CPU= f_MASTER= 16 MHz

HSI internal RC

f

_CPU= f_MASTER= 16 MHz

HSI internal RC 16 MHz/8

f_CPU= f_MASTER= 2 MHz

HSE external clock 16 MHz/128

f_CPU= f_MASTER= 0.125 MHz

f_CPUscaled down,

HSI internal RC 16 MHz/128

f

all peripherals off,

code executed

from RAM

_CPU= f_MASTER= 0.125 MHz

LSI internal RC 128 kHz

f

Supply

_CPU= f_MASTER= 0.128MHz

I_DD(SLOW)

current in

slow mode

mA

HSE external clock 16 MHz/128

f_CPU= f_MASTER= 0.125 MHz

1.21

1.09

0.56

f_CPUscaled down,

HSI internal RC 16 MHz/128

f_CPU= f_MASTER= 0.125 MHz

all peripherals off,

code executed

from EEPROM

LSI internal RC 128 kHz

f_CPU= f_MASTER= 0.128 MHz

63/100

Electrical characteristics

STM8AF61xx, STM8AF51xx

Table 22. Total current consumption and timing in halt, fast active halt and slow

active halt modes at V = 3.3 V

DD

Symbol

Parameter

Conditions

Typ

Max

Unit

Flash powered down

Flash in stand-by mode

Crystal osc 16 MHz/128

HSE osc 16 MHz/128

LSI RC 128 kHz

4.7

62

I_DD(H)

Supply current in halt mode

600

490

140

Supply current in fast active halt

mode

µA

I_DD(FAH)

Supply current in slow active halt

mode

I_DD(SAH)

t_WU(FAH)

t_WU(SAH)

LSI RC 128 kHz

9

Wake-up time from fast active halt

mode to run mode

2⁽¹⁾

µs

Wake-up time from slow active

halt mode to run mode

100⁽¹⁾

1. Data based on characterization results, not tested in production

64/100

STM8AF61xx, STM8AF51xx

Electrical characteristics

On-chip peripherals

(1)

Table 23. Typical peripheral current consumption V = 5.0 V

DD

Typ.

f

=

f

=

f

=

Symbol

Parameter

Unit

master

2 MHz

master

16 MHz

0.23

0.12

0.1

24 MHz

0.34

0.19

0.16

0.05

0.15

0.18

0.07

0.91

0.34

0.05

2.4

TIM1 supply current⁽²⁾

TIM2 supply current ⁽²⁾

TIM3 supply current⁽²⁾

TIM4 supply current⁽²⁾

USART supply current⁽²⁾

LINUART supply current⁽²⁾

SPI supply current⁽²⁾

I²C supply current⁽²⁾

I_DD(TIM1)

I_DD(TIM2)

I_DD(TIM3)

I_DD(TIM4)

I_DD(USART)

I_DD(LINUART)

I_DD(SPI)

0.03

0.02

0.01

0.004

0.03

0.01

0.02

0.06

0.003

0.22

0.03

0.09

0.11

0.04

0.06

0.22

0.02

1

mA

I_{DD(I C)}

2

CAN supply current⁽³⁾

I_DD(CAN)

I_DD(AWU)

AWU supply current⁽²⁾

All digital peripherals on

I_{DD(TOT_DIG)}

ADC supply current when

converting⁽⁴⁾

I_DD(ADC)

0.93

2.5

0.95

2.9

0.96

3.1

Data EEPROM programming

current

I_{DD(EE_PROG)}

1. Typical values - not tested in production. Since the peripherals are powered by an internally regulated,

constant digital supply voltage, the values are similar in the full supply voltage range.

2. Data based on a differential I_DDmeasurement between no peripheral clocked and a single active

peripheral. This measurement does not include the pad toggling consumption.

3. Data based on a differential IDD measurement between reset configuration (CAN disabled) and a

permanent CAN data transmit sequence in loopback mode at 1 MHz. This measurement does not include

the pad toggling consumption.

4. Data based on a differential I_DDmeasurement between reset configuration and continuous A/D

conversions.

65/100

Electrical characteristics

STM8AF61xx, STM8AF51xx

Current consumption curves

Figure 11 to Figure 16 show typical current consumption measured with code executing in RAM.

Figure 11. Typ. I vs. V Figure 12. Typ. I vs. f

DD(RUN)HSE

DD

DD(RUN)HSE

CPU

@f

= 16 MHz, periph = on

@ V = 5.0 V, periph = on

CPU

DD

10

25°C

85°C

12 5°C

25°C

9

8

9

8

85°C

7

6

12 5°C

6

5

4

3

4

3

2

1

2

1

0

2.5

3

3.5

4

4.5

5

5.5

6

0

5

10

15

20

25

30

V_DD[V]

fcpu [MHz]

Figure 13. Typ. I

vs. V

Figure 14. Typ. I

vs. V

DD(RUN)HSI

DD

DD(WFI)HSE DD

@ f

= 16 MHz, periph = off

@ f

= 16 MHz, periph = on

CPU

6

5

4

3

2

1

0

4

3

2

1

0

25°C

85°C

125°C

25°C

85°C

125°C

2.5

3.5

4.5

5.5

6.5

2.5

3.5

4.5

5.5

6.5

VDD [V]

Figure 15. Typ. I

vs. f

Figure 16. Typ. I

vs. V

DD(WFI)HSE

CPU

DD(WFI)HSI DD

@ V = 5.0 V, periph = on

@ f

= 16 MHz, periph = off

DD

CPU

2.5

2

6

5

4

1.5

3

2

1

0

1

0.5

0

25°C

85°C

12 5°C

25°C

85°C

12 5°C

2.5

3

3.5

4

4.5

5

5.5

6

0

5

10

15

20

25

30

V_DD[V]

fcpu [MHz]

66/100

STM8AF61xx, STM8AF51xx

Electrical characteristics

11.3.2

External clock sources and timing characteristics

HSE user external clock

Subject to general operating conditions for V and T .

DD

A

Table 24. HSE user external clock characteristics

Symbol

Parameter

Conditions

T_A< 105 °C

T_A> 105 °C

Min

0⁽¹⁾

Typ

Max

24

Unit

MHz

V

User external clock source

frequency

f_{HSE_ext}

0⁽¹⁾

16

V_HSEdHL

V_HSEH

Comparator hysteresis

0.1 x V_DD

OSCIN input pin high level

voltage

0.7 x V_DD

V_SS

V_DD

0.3 x V_DD

+1

V

OSCIN input pin low level

voltage

V_HSEL

OSCIN input leakage

current

I_{LEAK_HSE}

V_SS< V_IN< V_DD

-1

µA

1. In case of CSS, the external clock must have a frequency above 500 kHz.

Figure 17. HSE external clock source

V

HSEH

HSEL

f

HSE

External clock

source

OSCIN

STM8A

HSE crystal/ceramic resonator oscillator

The HSE clock can be supplied using a crystal/ceramic resonator oscillator of up to 24 MHz.

All the information given in this paragraph is based on characterization results with specified

typical external components. In the application, the resonator and the load capacitors have

to be placed as close as possible to the oscillator pins in order to minimize output distortion

and start-up stabilization time. Refer to the crystal resonator manufacturer for more details

(frequency, package, accuracy...).

67/100

Electrical characteristics

STM8AF61xx, STM8AF51xx

Table 25. HSE oscillator characteristics

Symbol

Parameter

Feedback resistor

Recommended load capacitance⁽²⁾

Conditions

Min

Typ

Max

Unit

kΩ

R_F

220

C⁽¹⁾

20

pF

6 (startup)

2 (stabilized)

C = 20 pF

C = 10 pF

I_DD(HSE)HSE oscillator power consumption

mA

6 (startup)

1.5 (stabilized)

g_m

Oscillator transconductance

Startup time

5

mA/V

ms

V_DDis

stabilized

(3)

t_SU(HSE)

1

1. C is approximately equivalent to 2 x crystal Cload.

2. The oscillator selection can be optimized in terms of supply current using a high quality resonator with small R_mvalue.

Refer to crystal manufacturer for more details

3. t_SU(HSE)is the start-up time measured from the moment it is enabled (by software) to a stabilized 24 MHz oscillation is

reached. This value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer.

Figure 18. HSE oscillator circuit diagram

f

to core

HSE

R

m

R

F

C

O

L

m

C

L1

OSCIN

C

m

g

m

Resonator

Consumption

control

Resonator

STM8A

OSCOUT

C

L2

HSE oscillator critical g formula

m

f

g_mcrit= (2 × Π × HSE)²× R_m(2Co + C)²

R : Notional resistance (see crystal specification)

m

L : Notional inductance (see crystal specification)

m

C : Notional capacitance (see crystal specification)

m

Co: Shunt capacitance (see crystal specification)

C

= C = C: Grounded external capacitance

L1

L2

g >> g

m

mcrit

68/100

STM8AF61xx, STM8AF51xx

Electrical characteristics

11.3.3

Internal clock sources and timing characteristics

Subject to general operating conditions for V and T .

DD

A

High speed internal RC oscillator (HSI)

Table 26. HSI oscillator characteristics

Symbol

Parameter

Frequency

Conditions

Min

Typ

Max

Unit

f_HSI

16

MHz

Trimmed by the

application for any V_DD

and T_Aconditions

HSI oscillator user

trimming accuracy

-1⁽¹⁾

1⁽¹⁾

V_DD= 5.0 V, T_A= 25°C

V_DD= 5.0 V,

ACC_HS

2

%

25 °C ≤T_A≤85 °C

HSI oscillator accuracy

(factory calibrated)

V_DD= 5.0 V,

25 °C ≤T_A≤125 °C

-3⁽¹⁾

-5⁽¹⁾

3⁽¹⁾

5⁽¹⁾

2⁽²⁾

V_DD= 3.0 V ≤V_DD≤ 5.5 V,

-40 °C ≤T_A≤ 125 °C

HSI oscillator wake-up

time including calibration

t_su(HSI)

µs

1. Tested in production

2. Guaranteed by design, not tested in production

Figure 19. Typical HSI frequency vs V @ four temperatures

DD

3%

2%

-40°C

25°C

85°C

125°C

1%

0%

-1%

-2%

-3%

2.5

3

3.5

4

4.5

5

5.5

6

V_DD[V]

69/100

Electrical characteristics

STM8AF61xx, STM8AF51xx

Low speed internal RC oscillator (LSI)

Subject to general operating conditions for V_DDand T_A.

Table 27. LSI oscillator characteristics

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

f_LSI

Frequency

112

128

144

7⁽¹⁾

kHz

µs

t_su(LSI)LSI oscillator wake-up time

1. Data based on characterization results, not tested in production.

Figure 20. Typical LSI frequency vs V @ room temperature

DD

3%

2%

1%

25°C

0%

-1%

-2%

-3%

2.5

3

3.5

4

4.5

5

5.5

6

V_DD[V]

70/100

STM8AF61xx, STM8AF51xx

Electrical characteristics

11.3.4

Memory characteristics

RAM and hardware registers

Table 28. RAM and hardware registers

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

V_RM

Data retention mode⁽¹⁾

Halt mode (or reset)

1.8

V

1. Minimum supply voltage without losing data stored in RAM (in halt mode or under reset) or in hardware

registers (only in halt mode). Guaranteed by design, not tested in production. refer to Table 18 on page 58

for the value of V_IT-max

Flash program memory/data EEPROM memory

General conditions: T_A= -40 to 125 °C.

Table 29. Flash program memory/data EEPROM memory

Symbol

Parameter

Conditions

Min⁽¹⁾Typ Max

Unit

Operating voltage

(all modes, execution/write/erase)

V_DD

f_CPU≤24 MHz

3.0

5.5

6.6

V

Standard programming time

(including erase) for byte/word/block

(1 byte/4 bytes/128 bytes)

6

ms

t_prog

Fast programming time for 1 block

(128 bytes)

3

3.3

ms

Erase time for 1 block (128 bytes)

t_erase

T_A= 25 °C

T_A= 125 °C

T_A= 25 °C

T_A= 125 °C

T_A= 145 °C

T_A= 25 °C

T_A= 55 °C

T_A= 85 °C

1 k

100

300 k

100 k

80 k

40

Program memory endurance

erase/write cycles⁽²⁾

N_RW

cycles

Data memory endurance erase/write

cycles⁽²⁾

Program memory after cycling

20

years

hours

years

t_RET

10

Data memory retention after cycling at

the endurance limits (T, n)

Full temperature

range

1000

T_A= 25 °C

T_A= 55 °C

T_A= 85 °C

40

20

10

t_RETIIntrinsic data retention

1. Guaranteed by characterization, not tested in production.

2. The physical granularity of the memory is 4 bytes, so cycling is performed on 4 bytes even when a

write/erase operation addresses a single byte.

71/100

Electrical characteristics

STM8AF61xx, STM8AF51xx

11.3.5

I/O port pin characteristics

General characteristics

Subject to general operating conditions for V_DDand T_Aunless otherwise specified. All

unused pins must be kept at a fixed voltage, using the output mode of the I/O for example or

an external pull-up or pull-down resistor.

Table 30. I/O static characteristics

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

Input low level

voltage

V_IL

-0.3 V

0.3 x V_DD

V

Input high level

voltage

V_IH

V_DD= 5.0 V

0.7 x V_DD

V_DD+ 0.3 V

V

0.1 x

V_DD

V_hys

Hysteresis⁽¹⁾

mV

I = 3 mA

Standard I/0, V_DD= 5 V

Standard I/0, V_DD= 3 V

V_DD- 0.5 V

V_DD- 0.4 V

V_OH

I = 1.5 mA

High sink and true open

drain I/0, V_DD= 5 V

I = 8mA

0.5

V

V_OL

I = 3 mA

Standard I/0, V_DD= 5 V

Standard I/0, V_DD= 3 V

V_DD= 5 V, V_IN= V_SS

0.6

0.4

65

I = 1.5 mA

Pull-up resistor

R_pu

35

50

kΩ

Fast I/Os

Load = 50 pF

20⁽²⁾

ns

Rise and fall time

(10% - 90%)

t_R, t_F

Standard and high sink I/Os

Load = 50 pF

125⁽²⁾

ns

Input leakage

current,

analog and digital

I_lkg

V_SS≤V_IN≤V_DD

1⁽²⁾

µA

Analog input

leakage current

V_SS≤ V_IN≤ V_DD

I_{lkg ana}

I_lkg(inj)

250⁽²⁾

1⁽²⁾

nA

µA

-40 °C < T_A< 125 °C

Leakage current in

adjacent I/O⁽²⁾

Injection current 4 mA

1. Hysteresis voltage between Schmitt trigger switching levels. Based on characterization results, not tested in production.

2. Data based on characterization results, not tested in production.

72/100

STM8AF61xx, STM8AF51xx

Figure 21. Typical V and V vs V @ four temperatures

Electrical characteristics

IL

IH

DD

6

-40°C

25°C

85°C

125°C

5

4

3

2

1

0

2.5

3

3.5

4

4.5

5

5.5

6

V_DD[V]

Figure 22. Typical pull-up resistance R vs V @ four temperatures

PU

DD

60

55

50

45

40

35

30

-40°C

25°C

85°C

125°C

2.5

3

3.5

4

4.5

5

5.5

6

V_DD[V]

Figure 23. Typical pull-up current I vs V @ four temperatures

pu

DD

140

120

100

80

-40°C

25°C

85°C

125°C

60

40

20

0

1

2

3

4

5

6

V_DD[V]

Note: The pull-up is a pure resistor (slope goes through 0).

73/100

Electrical characteristics

STM8AF61xx, STM8AF51xx

Typical output level curves

Figure 24 to Figure 33 show typical output level curves measured with output on a single pin.

Figure 24. Typ. V @ V = 3.3 V (standard

Figure 25. Typ. V @ V = 5.0 V (standard

OL DD

OL

DD

ports)

-40°C

25°C

85°C

125°C

-40°C

25°C

85°C

125°C

1.5

1.25

1

1.5

1.25

1

0.75

0.5

0.25

0

0.75

0.5

0.25

0

1

2

3

4

5

6

7

0

2

4

6

8

10

12

I_OL[mA]

Figure 26. Typ. V @ V = 3.3 V (true open Figure 27. Typ. V @ V = 5.0 V (true open

OL

DD

OL

DD

drain ports)

-40°C

25°C

85°C

125°C

-40°C

25°C

85°C

125°C

2

1.75

1.5

1.25

1

2

1.75

1.5

1.25

1

0.75

0.5

0.25

0

0.75

0.5

0.25

0

2

4

6

8

10

12

14

0

5

10

15

20

25

I_OL[mA]

Figure 28. Typ. V @ V = 3.3 V (high sink

Figure 29. Typ. V @ V = 5.0 V (high sink

OL DD

OL

DD

ports)

-40°C

25°C

85°C

125°C

-40°C

25°C

85°C

125°C

1.5

1.25

1

1.5

1.25

1

0.75

0.5

0.25

0

0.75

0.5

0.25

0

2

4

6

8

10

12

14

0

5

10

15

20

25

I_OL[mA]

74/100

STM8AF61xx, STM8AF51xx

Electrical characteristics

Figure 30. Typ. V

V

@ V = 3.3 V

Figure 31. Typ. V

V

@ V = 5.0 V

DD - OH

DD

DD - OH DD

(standard ports)

-40°C

25°C

85°C

125°C

-40°C

25°C

85°C

125°C

2

1.75

1.5

1.25

1

2

1.75

1.5

1.25

1

0.75

0.5

0.25

0

0.75

0.5

0.25

0

1

2

3

4

5

6

7

0

2

4

6

8

10

12

I_OH[mA]

I

_OH[mA]

Figure 32. Typ. V

V

@ V = 3.3 V (high Figure 33. Typ. V

V

@ V = 5.0 V (high

DD - OH

DD

DD - OH DD

sink ports)

-40°C

25°C

85°C

125°C

-40°C

25°C

85°C

125°C

2

1.75

1.5

1.25

1

2

1.75

1.5

1.25

1

0.75

0.5

0.25

0

0.75

0.5

0.25

0

2

4

6

8

10

12

14

0

5

10

15

20

25

I_OH[mA]

I

_OH[mA]

75/100

Electrical characteristics

STM8AF61xx, STM8AF51xx

11.3.6

Reset pin characteristics

Subject to general operating conditions for V_DDand T_Aunless otherwise specified.

Table 31. NRST pin characteristics

Symbol

V_IL(NRST)

V_IH(NRST)

V_OL(NRST)

R_PU(NRST)

V_F(NRST)

V_NF(NRST)

Parameter

Conditions

Min

Typ

Max

Unit

NRST input low level voltage⁽¹⁾

NRST input high level voltage⁽¹⁾

NRST output low level voltage⁽¹⁾

NRST pull-up resistor⁽³⁾

TBD⁽²⁾

V_DD

V_SS

TBD⁽²⁾

30

V

I_OL=TBD⁽²⁾mA

TBD⁽²⁾

60

40

kΩ

ns

µs

NRST input filtered pulse⁽⁴⁾

NRST input not filtered pulse⁽⁴⁾

TBD⁽²⁾

1. Data based on characterization results, not tested in production.

2. TBD = To be determined.

3. The R_PUpull-up equivalent resistor is based on a resistive transistor

4. Data guaranteed by design, not tested in production.

Figure 34. Typical NRST V and V vs V @ four temperatures

IL

IH

DD

-40°C

25°C

85°C

6

5

4

3

2

1

0

125°C

2.5

3

3.5

4

4.5

5

5.5

6

V_DD[V]

76/100

STM8AF61xx, STM8AF51xx

Electrical characteristics

Figure 35. Typical NRST pull-up resistance R vs V @ four temperatures

PU

DD

-40°C

25°C

85°C

125°C

60

55

50

45

40

35

30

2.5

3

3.5

4

4.5

5

5.5

6

V_DD[V]

Figure 36. Typical NRST pull-up current I vs V @ four temperatures

pu

DD

140

120

100

80

60

-40°C

25°C

85°C

125°C

40

20

0

1

2

3

4

5

6

V_DD[V]

The reset network shown in Figure 37 protects the device against parasitic resets. The user

must ensure that the level on the NRST pin can go below the V_ILmax. level specified in

Table 30. Otherwise the reset is not taken into account internally.

Figure 37. Recommended reset pin protection

STM8A

V

DD

R_PU

External

reset

circuit

NRST

Internal reset

Filter

0.01¬µ

77/100

Electrical characteristics

STM8AF61xx, STM8AF51xx

11.3.7

TIM 1, 2, 3, and 4 timer characteristics

Subject to general operating conditions for V_DD, f_MASTER, and T_Aunless otherwise specified.

Table 32. TIM 1, 2, 3 characteristics

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

t_w(ICAP)in

t_res(TIM)

f_EXT

Input capture pulse time⁽¹⁾

Timer resolution time⁽¹⁾

Timer external clock frequency⁽¹⁾

Timer resolution⁽¹⁾

2

1

T_MASTER

MHz

24

Res_TIM

16

1

bit

16-bit counter clock period when

internal clock is selected⁽¹⁾

t_COUNTER

T_MASTER

t_{MAX_COUNT}Maximum possible count⁽¹⁾

65 536 T_MASTER

1. Not tested in production

78/100

STM8AF61xx, STM8AF51xx

Electrical characteristics

SPI serial peripheral interface

11.3.8

Unless otherwise specified, the parameters given in Table 33 are derived from tests

performed under ambient temperature, f_MASTERfrequency and V_DDsupply voltage

conditions. t_MASTER= 1/f_MASTER

.

Refer to I/O port characteristics for more details on the input/output alternate function

characteristics (NSS, SCK, MOSI, MISO).

Table 33. SPI characteristics

Symbol

Parameter

Conditions

Master mode

Slave mode

Min

Max

Unit

0

10

f_SCK

1/t_c(SCK)

SPI clock frequency

MHz

t_r(SCK)

t_f(SCK)

SPI clock rise and fall time Capacitive load: C = 30 pF

25

(1)

t_su(NSS)

NSS setup time

NSS hold time

Slave mode

4*T_MASTER

70

(1)

t_h(NSS)

(1)

t_w(SCKH)

t_w(SCKL)

Master mode,

f_MASTER= 16 MHz, f_SCK= 8 MHz

SCK high and low time

Data input setup time

110

140

(1)

Master mode

Slave mode

Master mode,

5

2

t_su(MI)

t_su(SI)

(1)

7

3

(1)

f

_MASTER= 16 MHz, f_SCK= 8 MHz

t_h(MI)

t_h(SI)

Data input hold time

(1)

Slave mode,

f_MASTER= 16 MHz, f_SCK= 8 MHz

ns

Slave mode,

f_MASTER= 16 MHz, f_SCK= 8 MHz

400

(1)(2)

(1)(3)

t_a(SO)

Data output access time

Slave mode

4*t_MASTER

t_dis(SO)

Data output disable time

Data output valid time

25

Slave mode (after enable edge),

f_MASTER= 16 MHz, f_SCK= 8 MHz

(1)

t_v(SO)

100

3

Master mode (after enable edge),

f_MASTER= 16 MHz, f_SCK= 8 MHz

t_v(MO)

Data output valid time

Data output hold time

(1)

t_h(SO)

Slave mode (after enable edge)

Master mode (after enable edge)

100

6

(1)

t_h(MO)

1. Values based on design simulation and/or characterization results, and not tested in production.

2. Min time is for the minimum time to drive the output and the max time is for the maximum time to validate the data.

3. Min time is for the minimum time to invalidate the output and the max time is for the maximum time to put the data in Hi-Z.

79/100

Electrical characteristics

STM8AF61xx, STM8AF51xx

Figure 38. SPI timing diagram where slave mode and CPHA = 0

NSS input

t

SU(NSS)

c(SCK)

h(NSS)

CPHA=0

CPOL=0

t

w(SCKH)

w(SCKL)

CPHA=0

CPOL=1

t

dis(SO)

v(SO)

r(SCK)

f(SCK)

h(SO)

t

a(SO)

MISO

OUT PUT

MSB O UT

BI T6 OUT

BIT1 IN

LSB OUT

t

su(SI)

MOSI

M SB IN

LSB IN

INPUT

t

h(SI)

ai14134

Figure 39. SPI timing diagram where slave mode and CPHA = 1

NSS input

t

SU(NSS)

c(SCK)

h(NSS)

CPHA=1

CPOL=0

t

w(SCKH)

CPHA=1

CPOL=1

t

w(SCKL)

t

r(SCK)

f(SCK)

t

v(SO)

h(SO)

dis(SO)

t

a(SO)

MISO

OUT PUT

MSB O UT

BI T6 OUT

LSB OUT

t

su(SI)

h(SI)

MOSI

M SB IN

BIT1 IN

LSB IN

INPUT

ai14135

1. Measurement points are at CMOS levels: 0.3 V_DDand 0.7 V_DD

.

80/100

STM8AF61xx, STM8AF51xx

Electrical characteristics

Figure 40. SPI timing diagram - master mode

High

NSS input

t

c(SCK)

CPHA=0

CPOL=0

CPHA=0

CPOL=1

CPHA=1

CPOL=0

CPHA=1

CPOL=1

t

w(SCKH)

r(SCK)

f(SCK)

t

su(MI)

t

w(SCKL)

MISO

INPUT

MSBIN

BIT6 IN

LSB IN

t

h(MI)

MOSI

M SB OUT

BIT1 OUT

LSB OUT

OUTUT

t

v(MO)

h(MO)

ai14136

1. Measurement points are at CMOS levels: 0.3 V_DDand 0.7 V_DD

.

81/100

Electrical characteristics

2

STM8AF61xx, STM8AF51xx

11.3.9

I C interface characteristics

2

Table 34. I C characteristics

Standard mode I²C Fast mode I²C⁽¹⁾

Unit

Symbol

Parameter

Min⁽²⁾

Max⁽²⁾

Min⁽²⁾Max⁽²⁾

t_w(SCLL)

t_w(SCLH)

t_su(SDA)

t_h(SDA)

SCL clock low time

4.7

1.3

0.6

µs

ns

µs

SCL clock high time

SDA setup time

4.0

250

100

0⁽³⁾

0⁽⁴⁾

900⁽³⁾

300

SDA data hold time

t_r(SDA)

t_r(SCL)

SDA and SCL rise time

(V_DD3 ... 5.5 V)

1000

300

t_f(SDA)

t_f(SCL)

SDA and SCL fall time

(V_DD3 ... 5.5 V)

300

t_h(STA)

t_su(STA)

t_su(STO)

START condition hold time

4.0

4.7

4.0

0.6

Repeated START condition setup time

STOP condition setup time

µs

pF

STOP to START condition time

(bus free)

t_w(STO:STA)

4.7

1.3

C_b

Capacitive load for each bus line

400

1. f_MASTER, must be at least 8 MHz to achieve max fast I²C speed (400 kHz)

Data based on standard I²C protocol requirement, not tested in production

2.

The maximum hold time of the start condition has only to be met if the interface does not stretch the low

time

3.

4.

The device must internally provide a hold time of at least 300 ns for the SDA signal in order to bridge the

undefined region of the falling edge of SCL

82/100

STM8AF61xx, STM8AF51xx

Electrical characteristics

11.3.10 10-bit ADC characteristics

Subject to general operating conditions for V_DDA, f_MASTER, and T_Aunless otherwise

specified.

Table 35. ADC characteristics

Symbol

Parameter

Conditions

Min

Max

Unit

MHz

V

Typ

f_ADC

ADC clock frequency

2

V_DDAAnalog supply

3

5.5

V_DDA

V_REF+Positive reference voltage

V_REF-Negative reference voltage

2.75

V

V_SSA

0.5

V

V_DDA

Conversion voltage range⁽¹⁾

Devices with

external V_REF+

V_REF-pins

V_AIN

V_REF-

V_REF+

/

V

Internal sample and hold

capacitor

C_ADC

3

pF

Sampling time

(1)

f_ADC= 2 MHz

1.5

7

µs

t_S

(3 x 1/f_ADC

)

t_STAB

Wake-up time from standby

Total conversion time including

t_CONVsampling time

(14 x 1/f_ADC

f_ADC= 2 MHz

7

µs

)

1. During the sample time the input capacitance C_AIN(3 pF max) can be charged/discharged by the external

source. The internal resistance of the analog source must allow the capacitance to reach its final voltage

level within t_S.After the end of the sample time t_S, changes of the analog input voltage have no effect on

the conversion result. Values for the sample clock t_Sdepend on programming.

83/100

Electrical characteristics

STM8AF61xx, STM8AF51xx

Table 36. ADC accuracy with R

< 10 kΩ R , V

= 3.3 V

DDA

AIN

Symbol

|E_T|

Parameter

Conditions

Typ

1.5

1.1

Max

Unit

Total unadjusted error⁽¹⁾

Offset error⁽¹⁾

TBD⁽¹⁾

|E_O|

Gain error⁽¹⁾

f_ADC= 2 MHz

|E_G|

LSB

-0.2/0.6

Differential linearity error⁽¹⁾

Integral linearity error⁽¹⁾

|E_D|

0.9

1

|E_L|

1. TBD = To be determined

Table 37. ADC accuracy with R

< 10 kΩ , V

= 5 V

DDA

AIN

Symbol

|E_T|

Parameter

Conditions

Typ

1.4

0.8

0.1

0.9

0.7

Max

Unit

Total unadjusted error⁽¹⁾

Offset error⁽¹⁾

3

2

1

2

|E_O|

Gain error⁽¹⁾

|E_G|

f_ADC= 2 MHz

LSB

Differential linearity error⁽¹⁾

Integral linearity error⁽¹⁾

|E_D|

|E_L|

1. ADC accuracy vs. injection current: Any positive or negative injection current within the limits specified for

I_INJ(PIN)and ΣI_INJ(PIN)in Section 11.3.5 does not affect the ADC accuracy.

Figure 41. ADC accuracy characteristics

E

G

1023

1022

1021

V

– V

DDA

SSA

1LSB

= ----------------------------------------

IDEAL

1024

(2)

E

T

(3)

7

6

5

4

3

2

1

(1)

E

O

E

L

E

D

1 LSB

IDEAL

0

1

2

3

4

5

6

7

1021102210231024

V

DDA

SSA

1. Example of an actual transfer curve

2. The ideal transfer curve

3. End point correlation line

E_T= Total unadjusted error: Maximum deviation between the actual and the ideal transfer curves.

E

_O= Offset error: Deviation between the first actual transition and the first ideal one.

_G= Gain error: Deviation between the last ideal transition and the last actual one.

_D= Differential linearity error: Maximum deviation between actual steps and the ideal one.

E_L= Integral linearity error: Maximum deviation between any actual transition and the end point correlation

line.

84/100

STM8AF61xx, STM8AF51xx

Figure 42. Typical application with ADC

Electrical characteristics

V

DD

STM8A

V

T

0.6V

R

AIN

AINx

10-bit A/D

conversion

V

AIN

C

V

T

0.6V

AIN

I

C

ADC

L

¬ 1¬

11.3.11 EMC characteristics

Susceptibility tests are performed on a sample basis during product characterization.

Functional EMS (electromagnetic susceptibility)

While executing a simple application (toggling 2 LEDs through I/O ports), the product is

stressed by two electromagnetic events until a failure occurs (indicated by the LEDs).

●

ESD: Electrostatic discharge (positive and negative) is applied on all pins of the device

until a functional disturbance occurs. This test conforms with the IEC 1000-4-2

standard.

●

FTB: A burst of fast transient voltage (positive and negative) is applied to V_DDand V_SS

through a 100 pF capacitor, until a functional disturbance occurs. This test conforms

with the IEC 1000-4-4 standard.

A device reset allows normal operations to be resumed. The test results are given in the

table below based on the EMS levels and classes defined in application note AN1709.

Designing hardened software to avoid noise problems

EMC characterization and optimization are performed at component level with a typical

application environment and simplified MCU software. It should be noted that good EMC

performance is highly dependent on the user application and the software in particular.

Therefore it is recommended that the user applies EMC software optimization and

prequalification tests in relation with the EMC level requested for his application.

Software recommendations

The software flowchart must include the management of runaway conditions such as:

●

Corrupted program counter

Unexpected reset

Critical data corruption (control registers...)

Prequalification trials

Most of the common failures (unexpected reset and program counter corruption) can be

recovered by applying a low state on the NRST pin or the oscillator pins for 1 second.

To complete these trials, ESD stress can be applied directly on the device, over the range of

specification values. When unexpected behavior is detected, the software can be hardened

to prevent unrecoverable errors occurring (see application note AN1015).

85/100

Electrical characteristics

STM8AF61xx, STM8AF51xx

Table 38. EMS data

Symbol

Parameter

Conditions

Level/class

V_DD= 3.3 V, T_A= 25 °C,

f_MASTER= 16 MHz (HSI clock),

Conforms to IEC 1000-4-2

Voltage limits to be applied on any I/O pin to

induce a functional disturbance

V_FESD

3B

V_DD= 3.3 V, T_A= 25 °C,

Fast transient voltage burst limits to be

V_EFTBapplied through 100 pF on V_DDand V_SS

f_MASTER= 16 MHz (HSI clock),

Conforms to IEC 1000-4-4

4A

pins to induce a functional disturbance

Electromagnetic interference (EMI)

Emission tests conform to the SAE J 1752/3 standard for test software, board layout and pin

loading.

Table 39. EMI data

Conditions

(1)

Max f_CPU

Symbol

Parameter

Unit

Monitored

frequency band

General conditions

8

16

24

MHz

0.1 MHz to 30 MHz

30 MHz to 130 MHz

130 MHz to 1 GHz

15

18

-1

2

17

22

3

22

16

5

V_DD= 5 V,

T_A= 25 °C,

LQFP80 package

conforming to SAE J

1752/3

Peak level

dBµV

-

S_EMI

SAE EMI level

2.5

1. Data based on characterization results, not tested in production.

Absolute maximum ratings (electrical sensitivity)

Based on two different tests (ESD and LU) using specific measurement methods, the

product is stressed to determine its performance in terms of electrical sensitivity. For more

details, refer to the application note AN1181.

Electrostatic discharge (ESD)

Electrostatic discharges (3 positive then 3 negative pulses separated by 1 second) are

applied to the pins of each sample according to each pin combination. The sample size

depends on the number of supply pins in the device (3 parts*(n+1) supply pin). This test

conforms to the JESD22-A114A/A115A standard. For more details, refer to the application

note AN1181.

86/100

STM8AF61xx, STM8AF51xx

Electrical characteristics

Maximum

Table 40. ESD absolute maximum ratings

Symbol

Ratings

Conditions

Class

Unit

value⁽¹⁾

T_A= 25°C, conforming to

JESD22-A114

Electrostatic discharge voltage

(Human body model)

V_ESD(HBM)

V_ESD(CDM)

V_ESD(MM)

3A

3

4000

T_A= 25°C, conforming to

JESD22-C101

Electrostatic discharge voltage

(Charge device model)

500

200

V

T_A= 25°C, conforming to

JESD22-A115

Electrostatic discharge voltage

(Machine model)

B

1. Data based on characterization results, not tested in production

Static latch-up

Two complementary static tests are required on 10 parts to assess the latch-up

performance.

●

A supply overvoltage (applied to each power supply pin) and

●

A current injection (applied to each input, output and configurable I/O pin) are

performed on each sample.

This test conforms to the EIA/JESD 78 IC latch-up standard. For more details, refer to the

application note AN1181.

Table 41. Electrical sensitivities

Class⁽¹⁾

Symbol

Parameter

Conditions

T_A= 25 °C

T_A= 85 °C

T_A= 125 °C

T_A= 145 °C

A

Static latch-up class

LU

1. Class description: A Class is an STMicroelectronics internal specification. All its limits are higher than the

JEDEC specifications, that means when a device belongs to class A it exceeds the JEDEC standard. B

class strictly covers all the JEDEC criteria (international standard).

87/100

Electrical characteristics

STM8AF61xx, STM8AF51xx

11.4

Thermal characteristics

The maximum chip junction temperature (T_Jmax) must never exceed the values given in

Table 17: General operating conditions on page 57.

The maximum chip-junction temperature, T_Jmax, in degrees Celsius, may be calculated

using the following equation:

T_Jmax= T_Amax+ (P_Dmaxx Θ )

JA

Where:

–

T

_Amaxis the maximum ambient temperature in ° C

Θ_JAis the package junction-to-ambient thermal resistance in ° C/W

P

_Dmaxis the sum of P_INTmaxand P_I/Omax(P_Dmax= P_INTmax+ P_I/Omax

)

P

_INTmaxis the product of I_DDand V_DD, expressed in Watts. This is the maximum

chip internal power.

_I/Omaxrepresents the maximum power dissipation on output pins

Where:

_I/Omax= Σ (V_OL*I_OL) + Σ((V_DD-V_OH)*I_OH),

–

P

taking into account the actual V_OL/I_OLand V_OH/I_OHof the I/Os at low and high level

in the application.

(1)

Table 42. Thermal characteristics

Symbol

Parameter

Value

Unit

Thermal resistance junction-ambient

LQFP 80 - 14 x 14 mm

Θ

38

°C/W

JA

Thermal resistance junction-ambient

LQFP 64 - 10 x 10 mm

Θ

46

57

59

°C/W

JA

Thermal resistance junction-ambient

LQFP 48 - 7 x 7 mm

Θ

JA

Thermal resistance junction-ambient

LQFP 32 - 7 x 7 mm

Θ

JA

1. Thermal resistances are based on JEDEC JESD51-2 with 4-layer PCB in a natural convection

environment.

11.4.1

Reference document

JESD51-2 integrated circuits thermal test method environment conditions - natural

convection (still air). Available from www.jedec.org.

88/100

STM8AF61xx, STM8AF51xx

Electrical characteristics

11.4.2

Selecting the product temperature range

When ordering the microcontroller, the temperature range is specified in the order code (see

Figure 47: STM8A order codes on page 95).

The following example shows how to calculate the temperature range needed for a given

application.

Assuming the following application conditions:

Maximum ambient temperature T_Amax= 82 °C (measured according to JESD51-2),

I_DDmax= 8 mA, V_DD= 5 V, maximum 20 I/Os used at the same time in output at low

level with I_OL= 8 mA, V_OL= 0.4 V

P_INTmax= 8 mA x 5 V= 400 mW

P_IOmax= 20 x 8 mA x 0.4 V = 64 mW

This gives: P_INTmax= 400 mW and P_IOmax64 mW:

_Dmax= 400 mW + 64 mW

P

Thus: P_Dmax= 464 mW

Using the values obtained in Table 42: Thermal characteristics on page 88 T_Jmaxis

calculated as follows:

–

For LQFP64 46°C/W

T_Jmax= 82° C + (46° C/W x 464 mW) = 82°C + 21°C = 103° C

This is within the range of the suffix B version parts (-40 < T_J< 105° C).

Parts must be ordered at least with the temperature range suffix B.

89/100

Package characteristics

STM8AF61xx, STM8AF51xx

12

Package characteristics

To meet environmental requirements, ST offers these devices in ECOPACK^®packages.

These packages have a lead-free second level interconnect. The category of second level

interconnect is marked on the package and on the inner box label, in compliance with

JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also

marked on the inner box label.

ECOPACK is an ST trademark. ECOPACK^®specifications are available at www.st.com.

90/100

STM8AF61xx, STM8AF51xx

Package characteristics

12.1

Package mechanical data

Figure 43. 80-pin low profile quad flat package (14 x 14)

D

ccc

C

D1

D3

A

A2

41

60

40

61

b

L1

E3 E1

E

L

A1

K

80

Pin 1

identification

1

c

1S_ME

Table 43. 80-pin low profile quad flat package mechanical data

mm

Typ

inches⁽¹⁾

Dim.

Min

Max

Min

Typ

Max

A

A1

A2

b

-

0.05

1.35

0.22

0.09

15.80

13.80

-

1.60

0.15

1.45

0.38

0.20

16.20

14.20

-

0.0630

0.0060

0.0571

0.0150

0.0079

0.6378

0.5591

-

0.0020

0.0531

0.0087

0.0035

0.6220

0.5433

-

1.40

0.32

-

0.0551

0.0126

-

c

D

16.00

14.00

12.35

16.00

14.00

12.35

0.65

0.60

1.00

-

0.6299

0.5512

0.4862

0.6299

0.5512

0.4862

0.0256

0.0236

0.0394

-

D1

D3

E

15.80

13.80

-

16.20

14.20

-

0.6220

0.5433

-

0.6378

0.5591

-

E1

E3

e

-

L

0.45

-

0.75

-

0.0177

-

0.0295

-

L1

ccc

k

-

0.10

7°

-

0.0039

7°

0°

3.5°

0°

3.5°

1. Values in inches are converted from mm and rounded to 4 decimal digits

91/100

Package characteristics

Figure 44. 64-pin low profile quad flat package (10 x 10)

STM8AF61xx, STM8AF51xx

A

A2

A1

D

D1

Seating plane

(0.1 x 0.004 mm)

b

e

E1 E

c

M x 45°

Pin 1 identification

L1

L

θ

1. Available only for STM8A products with up to 64 Kbytes Flash

Table 44. 64-pin low profile quad flat package mechanical data

mm

Typ

inches⁽¹⁾

Dim.

Min

Max

Min

Typ

Max

A

A1

A2

b

1.60

0.15

1.45

0.27

0.20

0.0630

0.0059

0.0571

0.0106

0.0079

0.05

1.35

0.17

0.09

0.0020

0.0531

0.0067

0.0035

1.40

0.22

0.0551

0.0087

c

D

12.00

10.00

12.00

10.00

0.50

0.4724

0.3937

0.4724

0.3937

0.0197

3.5°

D1

E

E1

e

θ

0°

3.5°

7°

0°

7°

L

0.45

0.60

0.75

0.0177

0.0236

0.0394

0.0295

L1

1.00

1. Values in inches are converted from mm and rounded to 4 decimal digits

92/100

STM8AF61xx, STM8AF51xx

Figure 45. 48-pin low profile quad flat package (7 x 7)

Package characteristics

A

D

A2

D1

A1

b

e

E1

E

c

L1

L

θ

Table 45. 48-pin low profile quad flat package mechanical data

mm

Typ

inches⁽¹⁾

Dim.

Min

Max

Min

Typ

Max

A

A1

A2

b

1.60

0.15

1.45

0.27

0.20

0.0630

0.0059

0.0571

0.0106

0.0079

0.05

1.35

0.17

0.09

0.0020

0.0531

0.0067

0.0035

1.40

0.22

0.0551

0.0087

c

D

9.00

7.00

9.00

7.00

0.50

3.5°

0.60

1.00

0.3543

0.2756

0.3543

0.2756

0.0197

3.5°

D1

E

E1

e

θ

0°

7°

0°

7°

L

0.45

0.75

0.0177

0.0236

0.0394

0.0295

L1

1. Values in inches are converted from mm and rounded to 4 decimal digits

93/100

Package characteristics

Figure 46. 32-pin low profile quad flat package (7 x 7)

STM8AF61xx, STM8AF51xx

D

A

A2

D1

A1

e

b

E1

E

c

L1

L

θ

Table 46. 32-pin low profile quad flat package mechanical data

mm

Typ

inches⁽¹⁾

Dim.

Min

Max

Min

Typ

Max

A

A1

A2

b

1.60

0.15

1.45

0.45

0.20

0.0630

0.0059

0.0571

0.0177

0.0079

0.05

1.35

0.30

0.09

0.0020

0.0531

0.0118

0.0035

1.40

0.37

0.0551

0.0146

c

D

9.00

7.00

9.00

7.00

0.80

3.5°

0.60

1.00

0.3543

0.2756

0.3543

0.2756

0.0315

3.5°

D1

E

E1

e

θ

0°

7°

0°

7°

L

0.45

0.75

0.0177

0.0236

0.0394

0.0295

L1

1. Values in inches are converted from mm and rounded to 4 decimal digits

94/100

STM8AF61xx, STM8AF51xx

Ordering information

13

Ordering information

Figure 47. STM8A order codes

(1)

STM8A

F

61

A

T

D

xxx

Y

Product family

Temperature range

STM8A....8-bit microcontroller

A....-40 °C to +85 °C

B....-40 °C to +105 °C

C....-40 °C to +125 °C

D....-40 °C to +145 °C

Memory size

2....8 Kbyte

Pin count

Program memory type

3....20 pins

F....Flash + EEPROM

6....32 pins

7....44 pins

8....48 pins

9....64 pins

A....80 pins

B....100 pins

C....128 pins

4....16 Kbyte

P....FASTROM no EEPROM

H....Flash no EEPROM

Q....FASTROM + EEPROM

6....32 Kbyte

7....48 Kbyte

8....64 Kbyte

9....96 Kbyte

A....128 Kbyte

B....256 Kbyte

Packaging

Package type

T.....LQFP

Y.... Tray

U.... Tube

U....QFN

Device family

R.... Tape and reel

X.... Tape and reel x90°

5x - CAN/LIN

6x - LIN only

1. Customer specific FASTROM code

95/100

STM8 development tools

STM8AF61xx, STM8AF51xx

14

STM8 development tools

Development tools for the STM8A microcontrollers include the

●

STice emulation system offering tracing and code profiling

●

STVD high-level language debugger including assembler and visual development

environment - seamless integration of third party C compilers

●

STVP Flash programming software

In addition, the STM8A comes with starter kits, evaluation boards and low-cost in-circuit

debugging/programming tools.

14.1

Emulation and in-circuit debugging tools

The STM8 tool line includes the STice emulation system offering a complete range of

emulation and in-circuit debugging features on a platform that is designed for versatility and

cost-effectiveness. In addition, STM8A application development is supported by a low-cost

in-circuit debugger/programmer.

The STice is the fourth generation of full-featured emulators from STMicroelectronics. It

offers new advanced debugging capabilities including tracing, profiling and code coverage

analysis to help detect execution bottlenecks and dead code.

In addition, STice offers in-circuit debugging and programming of STM8A microcontrollers

via the STM8 single wire interface module (SWIM), which allows non-intrusive debugging of

an application while it runs on the target microcontroller.

For improved cost effectiveness, STice is based on a modular design that allows you to

order exactly what you need to meet your development requirements and to adapt your

emulation system to support existing and future ST microcontrollers.

STice key features

●

Program and data trace recording up to 128 K records

Advanced breakpoints with up to 4 levels of conditions

Data breakpoints

Real-time read/write of all device ressources during emulation

Occurrence and time profiling and code coverage analysis (new features)

In-circuit debugging/programming via SWIM protocol

8-bit probe analyzer

1 input and 2 output triggers

USB 2.0 high speed interface to host PC

Power supply follower managing application voltages between 1.62 to 5.5 V

Modularity that allows you to specify the components you need to meet your

development requirements and adapt to future requirements

●

Supported by free software tools that include integrated development environment

(IDE), programming software interface and assembler for STM8

96/100

STM8AF61xx, STM8AF51xx

STM8 development tools

14.2

Software tools

STM8 development tools are supported by a complete, free software package from

STMicroelectronics that includes ST visual develop (STVD) IDE and the ST visual program-

mer (STVP) software interface. STVD provides seamless integration of the Cosmic C com-

piler for STM8, which is available in a free version that outputs up to 16 Kbytes of code.

14.2.1

STM8 toolset

STM8 toolset with STVD integrated development environment and STVP programming

software is available for free download at www.st.com/mcu. This package includes:

ST visual develop – Full-featured integrated development environment from

STMicroelectronics, featuring

●

Seamless integration of C and ASM toolsets

Full-featured debugger

Project management

Syntax highlighting editor

Integrated programming interface

Support of advanced emulation features for STice such as code profiling and coverage

ST visual programmer (STVP) – Easy-to-use, unlimited graphical interface allowing read,

write and verify of your STM8A microcontroller’s Flash memory. STVP also offers project

mode for saving programming configurations and automating programming sequences.

14.2.2

C and assembly toolchains

Control of C and assembly toolchains is seamlessly integrated into the STVD integrated

development environment, making it possible to configure and control the building of your

application directly from an easy-to-use graphical interface.

Available toolchains include:

●

C compiler for STM8 – Available in a free version that outputs up to 16 Kbytes of code.

For more information, see www.cosmic-software.com, www.raisonance.com

STM8 assembler linker – Free assembly toolchain included in the STM8 toolset,

which allows you to assemble and link your application source code.

14.3

Programming tools

During the development cycle, STice provides in-circuit programming of the STM8A Flash

microcontroller on your application board via the SWIM protocol. Additional tools are to

include a low-cost in-circuit programmer as well as ST socket boards, which provide

dedicated programming platforms with sockets for programming your STM8A.

For production environments, programmers will include a complete range of gang and

automated programming solutions from third-party tool developers already supplying

programmers for the STM8 family.

97/100

Revision history

STM8AF61xx, STM8AF51xx

15

Revision history

Table 47. Document revision history

Date

Revision

Changes

31-Jan-2008

Rev 1

Initial release

Added ‘H’ products to the datasheet (Flash no EEPROM).

Features on page 1: Updated Memories, Reset and supply

management, Communication interfaces and I/Os; reduced wakeup

pins by 1.

Table 1: Removed STM8AF6168, STM8AF6148, STM8AF6166,

STM8AF6146, STM8AF5168, STM8AF5186, STM8AF5176, and

STM8AF5166.

Section 1, Section 5, Section 6.2.1, Table 13, and Section 10:

Updated reference documentation: RM0009, PM0047, and UM0470.

Section 2: Added information about peak performance.

Section 3: Removed STM8A common features table.

Table 2: Removed STM8AF5186T, STM8AF5176T, STM8AF5168T,

and STM8AF5166T.

Table 3: Removed STM8AF6168T, STM8AF6166T, STM8AF6148T,

and STM8AF6146T.

Section 5: Made minor content changes and improved readability

and layout.

Section 5.4.3: Major modification, TMU included.

Section 5.6.2: User triming updated.

Section 5.6.3: LSI as CPU clock added.

Section 5.6.4 , Section 5.6.5: Maximum frequency conditional 32

Kbyte/128 Kbyte.

Section 5.8: Scan for 128 Kbyte removed.

22-Aug-2008

Rev 2

Section 5.9, Section 5.9.3: SPI 10 Mb/s.

Figure 3, Figure 4, and Figure 5: Amended footnote 1.

Table 5: HS output changed from 20 mA to 8 mA.

Section 7: Corrected Figure 7: Register and memory map; removed

address list; added Table 7.

Section 11.3.1 Note on typical/WC values added.

Table 10: Replaced the source blocks ‘simple USART’, ‘very low-end

timer (timer 4)’, and ‘EEPROM’ with ‘LINUART’, ‘timer4’ and

‘reserved’ respectively, added TMU registers.

Table 12: Updated OPT6 and NOPT6, added OPT7 to 17 (TMU, BL)

Table 13: Updated OPT1 UBC[7:0], OPT4 CKAWUSEL, OPT4

PRSC [1:0], and OPT6, added OPT7 to 16 (TMU).

Table 15: Amended footnotes.

Table 17: Added parameter ‘voltage and current operating

conditions’.

Table 18: Amended footnotes.

Table 19: Replaced.

Table 20: Amended maximum data and footnotes.

Table 21: Replaced.

Table 22: Added and amended I_DD(RUN)data; amended I_DD(WFI)

data; amended footnotes.

Table 23: Filled in, amended maximum data and footnotes.

Figure 11 to Figure 16: info on peripheral activity added.

Table 24: Modified f_{HSE_ext}data and added V_HSEdhldata.

98/100

STM8AF61xx, STM8AF51xx

Table 47. Document revision history (continued)

Revision history

Date

Revision

Changes

Table 26: Removed ACC_HSIparameters and replaced with ACC_HS

parameters; amended data and footnotes.

Table 28: Amended data.

Table 29: Updated names and data of N_RWand t_RETparameters.

Table 30: Added V_OHand V_OLparameters; Updated I_{lkg ana}

parameter.

Removed: Output driving current (standard ports), Output driving

current (true open drain ports), and Output driving current (high sink

ports).

Rev 2

cont’d

22-Aug-2008

Table 35: Updated f_ADC, t_S, and t_CONVdata.

Table 36: Removed the 4-MHz condition from all parameters.

Table 37: Removed the 4-MHz condition from all parameters;

updated footnote 1 and removed footnote 2.

Table 41: Added data for T_A= 145 °C.

Figure 47: Updated memory size, pin count and package type

information.

Replaced the salestype ‘STM8H61xx’ with ‘STM8AH61xx on the first

page.

Added ‘part numbers’ to heading rows of Table 1: Device summary.

Updated the 80-pin package silhouette on page 1 in line with POA

0062342-revD.

Table 10: Renamed ‘TMU key registers 0-7 [7:0]’ as ‘TMU key

registers 1-8 [7:0]’

Section 10: Updated introductory text concerning option bytes which

do not need to be saved in a complementary form.

Table 12: Renamed the option bits ‘TMU[0:3]’, ‘NTMU[0:3]’, and

‘TMU_KEY 0-7 [7:0]’ as ‘TMU[3:0]’, ‘NTMU[3:0]’, and ‘TMU_KEY 1-8

[7:0]’ respectively.

16-Sep-2008

Rev 3

Table 13: Updated values of option byte 5 (HSECNT[7:0]); inversed

the description of option byte 6 (TMU[3:0]); renamed option bytes 8

to 15 ‘TMU_KEY 0-7 [7:0]’, as ‘TMU_KEY 1-8 [7:0]’.

Updated 80-pin package information in line with POA 0062342-revD

in Figure 43 and Table 43.

99/100

STM8AF61xx, STM8AF51xx

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型号：	STM8AF5189TBR
厂家：	ST
描述：	MICROCONTROLLER, PQFP64, 10 X 10 MM, ROHS COMPLIANT, LQFP-64
文件：	总100页 (文件大小：1768K)
中文：	中文翻译
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