STM8AF5199TAXXXY [STMICROELECTRONICS]

8-BIT, FLASH, 24MHz, MICROCONTROLLER, PQFP64, 10 X 10 MM, ROHS COMPLIANT, LQFP-64;

STM8AF5199TAXXXY


型号：	STM8AF5199TAXXXY
厂家：	ST
描述：	8-BIT, FLASH, 24MHz, MICROCONTROLLER, PQFP64, 10 X 10 MM, ROHS COMPLIANT, LQFP-64
文件：	总118页 (文件大小：2173K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

STM8AF51xx STM8AF6169 STM8AF617x

STM8AF618x STM8AF619x STM8AF61Ax

Automotive 8-bit MCU, with up to 128 Kbytes Flash, data EEPROM,

10-bit ADC, timers, LIN, CAN, USART, SPI, I²C, 3 to 5.5 V

Features

■ Core

– Max f

: 24 MHz

CPU

LQFP48 7x7

LQFP32 7x7

– Advanced STM8A core with Harvard

architecture and 3-stage pipeline

– Average 1.6 cycles/instruction resulting in

LQFP80 14x14

LQFP64 10x10

10 MIPS at 16 MHz f

standard benchmark

for industry

CPU

■ Communication interfaces

■ Memories

– High speed 1 Mbit/s active CAN 2.0B

interface

– USART with clock output for synchronous

operation - LIN master mode

– Program memory: 32 to 128 Kbytes Flash

program; data retention 20 years at 55 °C

– Data memory: up to 2 Kbytes true data

EEPROM; endurance 300 kcycles

– LINUART LIN 2.1 compliant, master/slave

modes with automatic resynchronization

– RAM: 2 Kbytes to 6 Kbytes

■ Clock management

– SPI interface up to 10 Mbit/s or f

– I C interface up to 400 Kbit/s

/2

CPU

– Low-power crystal resonator oscillator with

external clock input

– Internal, user-trimmable 16 MHz RC and

low-power 128 kHz RC oscillators

– Clock security system with clock monitor

2

■ Analog to digital converter (ADC)

– 10-bit resolution, 2 LSB TUE, 1 LSB

linearity and up to 16 multiplexed channels

■ I/Os

■ Reset and supply management

– Multiple low-power modes (wait, slow, auto-

wakeup, halt) with user definable clock

gating

– Up to 72 user pins including 10 high sink

I/Os

– Highly robust I/O design, immune against

current injection

– Low consumption power-on and

power-down reset

(1)

Table 1.

Device summary

■ Interrupt management

Part numbers: STM8AF51xx (CAN)

– Nested interrupt controller with 32 interrupt

vectors

– Up to 37 external interrupts on 5 vectors

STM8AF51AA, STM8AF51A9, STM8AF51A8,

STM8AF519A, STM8AF5199, STM8AF5198,

STM8AF518A, STM8AF5189, STM8AF5188,

STM8AF5179, STM8AF5178, STM8AF5169, STM8AF5168

■ Timers

– 2 auto-reload 16-bit PWM timers with up to

3 CAPCOM channels each (IC, OC or

PWM)

– Multipurpose timer: 16-bit, 4 CAPCOM

channels, 3 complementary outputs, dead-

time insertion and flexible synchronization

– 8-bit AR system timer with 8-bit prescaler

– Auto-wakeup timer

Part numbers: STM8AF61xx

STM8AF61AA, STM8AF61A9, STM8AF61A8, STM8AF619A,

STM8AF6199, STM8AF6198, STM8AF618A, STM8AF6189,

STM8AF6188,

STM8AF6186, STM8AF6179, STM8AF6178,

STM8AF6176, STM8AF6169

1. This datasheet applies to product versions with and

without data EEPROM. In the order code, the letter ‘F’

applies to devices featuring Flash and data EEPROM.

‘F’ is replaced by ‘H’ for devices with Flash only, and

by ‘P’ for devices with FASTROM (see Table 2,

Table 3, and Figure 50).

– Window and standard watchdog timers

■ Operating temperature up to 145 °C

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1

Contents

STM8AF51xx, STM8AF61xx

Contents

1

2

3

4

5

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Product line-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Product overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

5.1

STM8A central processing unit (CPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

5.1.1

5.1.2

5.1.3

Architecture and registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

5.2

Single wire interface module (SWIM) and debug module (DM) . . . . . . . . 15

5.2.1

5.2.2

SWIM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Debug module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

5.3

5.4

Interrupt controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Flash program and data EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

5.4.1

5.4.2

5.4.3

5.4.4

Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Write protection (WP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Protection of user boot code (UBC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Read-out protection (ROP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

5.5

Clock controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

5.5.1

5.5.2

5.5.3

5.5.4

5.5.5

5.5.6

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Internal 16 MHz RC oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Internal 128 kHz RC oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Internal high-speed crystal oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

External clock input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Clock security system (CSS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

5.6

5.7

Low-power operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

5.7.1

5.7.2

5.7.3

Watchdog timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Auto-wakeup counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Beeper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

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5.7.4

5.7.5

Multipurpose and PWM timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

System timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

5.8

5.9

Analog to digital converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Communication interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

5.9.1

5.9.2

Universal synchronous/asynchronous receiver transmitter (USART) . . 21

Universal asynchronous receiver/transmitter with LIN support

(LINUART) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

5.9.3

5.9.4

5.9.5

Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

2

Inter integrated circuit (I C) interface . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Controller area network interface (beCAN) . . . . . . . . . . . . . . . . . . . . . . 25

5.10 Input/output specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

6

7

Pinouts and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

6.1

6.2

Package pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Alternate function remapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Memory and register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

7.1

7.2

Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

7.2.1

7.2.2

7.2.3

7.2.4

7.2.5

7.2.6

7.2.7

7.2.8

I/O register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Non volatile memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

CPU registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Miscellaneous registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Clock and clock controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Interrupt controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Communication interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

7.3

Analog to digital converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

8

Interrupt table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Option bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

9

10

10.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

10.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

10.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

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10.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

10.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

10.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

10.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

10.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

10.3.1 VCAP external capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

10.3.2 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

10.3.3 External clock sources and timing characteristics . . . . . . . . . . . . . . . . . 73

10.3.4 Internal clock sources and timing characteristics . . . . . . . . . . . . . . . . . 75

10.3.5 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

10.3.6 I/O port pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

10.3.7 Reset pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

10.3.8 TIM 1, 2, 3, and 4 electrical specifications . . . . . . . . . . . . . . . . . . . . . . . 85

10.3.9 SPI interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

2

10.3.10 I C interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

10.3.11 10-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

10.3.12 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

10.4 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

10.4.1 Reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

10.4.2 Selecting the product temperature range . . . . . . . . . . . . . . . . . . . . . . . . 96

11

Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

11.1 ECOPACK^{® . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97}

11.2 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

12

13

Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

Known limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

13.1 STM8A core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

13.1.1 Wait for event instruction (WFE) not available . . . . . . . . . . . . . . . . . . . 103

13.1.2 JRIL and JRIH instructions not available . . . . . . . . . . . . . . . . . . . . . . . 103

13.1.3 CPU not returning to Halt mode when the AL bit is set . . . . . . . . . . . . 103

13.1.4 Main program not resuming after ISR has reset the AL bit . . . . . . . . . 103

13.2 I²C interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

13.2.1 Misplaced NACK bit when receiving 2 bytes in master mode . . . . . . . 104

13.2.2 Data register corrupted . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

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13.2.3 Delay in STOP bit programming leading to reception of supplementary

byte 105

13.2.4 START condition badly generated after misplaced STOP . . . . . . . . . . 105

13.3 USART Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

Parity error flag (PE) not correctly set when overrun condition occurs . . . . . . . . 105

13.4 LINUART interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

13.4.1 Framing error with data byte 0x00 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

13.4.2 Framing error when receiving an identifier (ID) . . . . . . . . . . . . . . . . . . 106

13.4.3 Parity error when receiving an identifier (ID) . . . . . . . . . . . . . . . . . . . . 106

13.4.4 OR flag not correctly set in LIN master mode . . . . . . . . . . . . . . . . . . . 106

13.4.5 LIN header error when automatic resynchronization is enabled . . . . . 107

13.5 Clock controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

13.5.1 HSI RC oscillator cannot be switched off in run mode . . . . . . . . . . . . . 107

13.6 SPI Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

13.6.1 Last bit too short if SPI is disabled during communication . . . . . . . . . 107

13.7 beCAN interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

13.7.1 beCAN transmission error when sleep mode is entered during

transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

13.7.2 beCAN woken up from sleep mode with automatic wakeup interrupt . 108

13.7.3 beCAN time triggered communication mode not supported . . . . . . . . 108

13.7.4 be CAN read error in slow mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

14

STM8 development tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

14.1 Emulation and in-circuit debugging tools . . . . . . . . . . . . . . . . . . . . . . . . 110

14.1.1 STice key features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

14.2 Software tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

14.2.1 STM8 toolset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

14.2.2 C and assembly toolchains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

14.3 Programming tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

15

Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

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List of tables

STM8AF51xx, STM8AF61xx

List of tables

Table 1.

Table 2.

Table 3.

Table 4.

Table 5.

Table 6.

Table 7.

Table 8.

Device summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

STM8AF/H/P51xx product line-up with CAN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

STM8AF/H/P61xx product line-up without CAN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

PWM timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

TIM4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Legend/abbreviation for Table 7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

STM8A microcontroller family pin description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Memory model 128K. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

I/O port hardware register map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Non volatile memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

CPU registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

CFG_GCR register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

RST_SR register map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

TMU register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

CLK register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Interrupt software priority registers map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

External interrupt control register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

WWDG register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

IWDG register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

AWU register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

BEEP register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

TIM1 register map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

TIM2 register map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

TIM3 register map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

TIM4 register map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

SPI register map and reset value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Table 9.

Table 10.

Table 11.

Table 12.

Table 13.

Table 14.

Table 15.

Table 16.

Table 17.

Table 18.

Table 19.

Table 20.

Table 21.

Table 22.

Table 23.

Table 24.

Table 25.

Table 26.

Table 27.

Table 28.

Table 29.

Table 30.

Table 31.

Table 32.

Table 33.

Table 34.

Table 35.

Table 36.

Table 37.

Table 38.

Table 39.

2

I C register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

USART register map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

LINUART register map and reset value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

ADC register map and reset value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

STM8A interrupt table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Option bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Option byte description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

Operating conditions at power-up/power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

Total current consumption in run, wait and slow mode. General conditions for V

DD

apply. T = -40 °C to 145 °C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

A

Table 40.

Total current consumption in halt and active halt modes. General conditions for V

DD

apply. T = -40 °C to 55 °C unless otherwise stated . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

A

Table 41.

Table 42.

Table 43.

Table 44.

Table 45.

Table 46.

Oscillator current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

Programming current consumption. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

Typical peripheral current consumption V = 5.0 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

DD

HSE external clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

HSE oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

HSI oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

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List of tables

Table 47.

Table 48.

Table 49.

Table 50.

Table 51.

Table 52.

Table 53.

Table 54.

Table 55.

Table 56.

Table 57.

Table 58.

Table 59.

Table 60.

Table 61.

Table 62.

Table 63.

Table 64.

Table 65.

Table 66.

Table 67.

LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

Flash program memory/data EEPROM memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

Program memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

Data memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

TIM 1, 2, 3, and 4 electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

2

I C characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

ADC accuracy for V

= 5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

DDA

EMS data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

EMI data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

80-pin low profile quad flat package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

64-pin low profile quad flat package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

48-pin low profile quad flat package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

32-pin low profile quad flat package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

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List of figures

STM8AF51xx, STM8AF61xx

List of figures

Figure 1.

Figure 2.

Figure 3.

Figure 4.

Figure 5.

Figure 6.

Figure 7.

Figure 8.

Figure 9.

STM8A block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Flash memory organization of STM8A products. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

LQFP 80-pin pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

LQFP 64-pin pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

LQFP 48-pin pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

LQFP 32-pin pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Register and memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

CAN register mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

CAN page mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Figure 10. Pin loading conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

Figure 11. Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

Figure 12.

f

versus V

CPUmax DD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67

Figure 13. External capacitor C

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

EXT

Figure 14. Typ. I

Figure 15. Typ. I

Figure 16. Typ. I

Figure 17. Typ. I

Figure 18. Typ. I

Figure 19. Typ. I

vs. V @f

= 16 MHz, peripherals = on . . . . . . . . . . . . . . . . . . . . . . 71

DD(RUN)HSE

DD(RUN)HSE

DD(RUN)HSI

DD(WFI)HSE

DD(WFI)HSE

DD

CPU

vs. f

@ V = 5.0 V, peripherals = on . . . . . . . . . . . . . . . . . . . . . . . 71

CPU

DD

vs. V @ f

= 16 MHz, peripherals = off . . . . . . . . . . . . . . . . . . . . . . 72

= 16 MHz, peripherals = on . . . . . . . . . . . . . . . . . . . . . . 72

DD

CPU

vs. V @ f

DD

CPU

vs. f

@ V = 5.0 V, peripherals = on . . . . . . . . . . . . . . . . . . . . . . . . 72

CPU

DD

vs. V @ f = 16 MHz, peripherals = off . . . . . . . . . . . . . . . . . . . . . . 72

DD(WFI)HSI

DD

CPU

Figure 20. HSE external clock source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

Figure 21. HSE oscillator circuit diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

Figure 22. Typical HSI frequency vs V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

DD

Figure 23. Typical LSI frequency vs V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

DD

Figure 24. Typical V and V vs V @ four temperatures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

IL

IH

DD

Figure 25. Typical pull-up resistance R vs V @ four temperatures . . . . . . . . . . . . . . . . . . . . . . . 80

PU

DD

(1)

Figure 26. Typical pull-up current I vs V @ four temperatures . . . . . . . . . . . . . . . . . . . . . . . . . 81

pu

DD

Figure 27. Typ. V @ V = 3.3 V (standard ports). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

OL

DD

Figure 28. Typ. V @ V = 5.0 V (standard ports). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

OL

DD

Figure 29. Typ. V @ V = 3.3 V (true open drain ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

OL

DD

Figure 30. Typ. V @ V = 5.0 V (true open drain ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

OL

DD

Figure 31. Typ. V @ V = 3.3 V (high sink ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

OL

DD

Figure 32. Typ. V @ V = 5.0 V (high sink ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

OL

DD

Figure 33. Typ. V - V @ V = 3.3 V (standard ports). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

DD

OH

DD

Figure 34. Typ. V - V @ V = 5.0 V (standard ports). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

DD

OH

DD

Figure 35. Typ. V - V @ V = 3.3 V (high sink ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

DD

OH

DD

Figure 36. Typ. V - V @ V = 5.0 V (high sink ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

DD

OH

DD

Figure 37. Typical NRST V and V vs V @ four temperatures . . . . . . . . . . . . . . . . . . . . . . . . . . 83

IL

IH

DD

Figure 38. Typical NRST pull-up resistance R vs V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

PU

DD

Figure 39. Typical NRST pull-up current I vs V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

pu

DD

Figure 40. Recommended reset pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

Figure 41. SPI timing diagram in slave mode and with CPHA = 0. . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

Figure 42. SPI timing diagram in slave mode and with CPHA = 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

Figure 43. SPI timing diagram - master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

Figure 44. Typical application with ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

Figure 45. ADC accuracy characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

Figure 46. 80-pin low profile quad flat package (14 x 14) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

Figure 47. 64-pin low profile quad flat package (10 x 10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

Figure 48. 48-pin low profile quad flat package (7 x 7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

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List of figures

Figure 49. 32-pin low profile quad flat package (7 x 7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

(1)

Figure 50. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

Doc ID 14395 Rev 6

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Introduction

STM8AF51xx, STM8AF61xx

1

Introduction

This datasheet refers to the STM8AF51xx and STM8AF61xx products with 32 to 128 Kbytes

of program memory. In the order code, the letter ‘F’ refers to product versions with Flash and

data EEPROM, ‘H’ to product versions with Flash only, and ‘P’ to product versions with

FASTROM. The identifiers ‘F’, ‘H’, and ‘P’ do not coexist in a given order code.

The datasheet contains the description of family features, pinout, electrical characteristics,

mechanical data and ordering information.

●

For complete information on the STM8A microcontroller memory, registers and

peripherals, please refer to STM8A microcontroller family reference manual (RM0009).

●

●

●

For information on programming, erasing and protection of the internal Flash memory

please refer to the STM8 Flash programming manual (PM0047).

For information on the debug and SWIM (single wire interface module) refer to the

STM8 SWIM communication protocol and debug module user manual (UM0470).

For information on the STM8 core, please refer to the STM8 CPU programming manual

(PM0044).

10/118

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STM8AF51xx, STM8AF61xx

Description

2

Description

The STM8A automotive 8-bit microcontrollers covered in this datasheet offer from 32 Kbytes

to 128 Kbytes of non volatile memory and integrated true data EEPROM.

The STM8AF51xx series feature a CAN interface.

All devices of the STM8A product line provide the following benefits:

●

Reduced system cost

–

–

Integrated true data EEPROM for up to 300 kwrite/erase cycles

High system integration level with internal clock oscillators, watchdog and brown-

out reset

●

Performance and robustness

–

Peak performance 20 MIPS at 24 MHz and average performance 10 MIPS at

16 MHz CPU clock frequency

–

–

Robust I/O, independent watchdogs with separate clock source

Clock security system

●

●

Short development cycles

–

Applications scalability across a common family product architecture with

compatible pinout, memory map and modular peripherals.

–

Full documentation and a wide choice of development tools

Product longevity

–

–

Advanced core and peripherals made in a state-of-the art technology

Native automotive product family operating both at 3.3 V and 5 V supply

All STM8A and ST7 microcontrollers are supported by the same tools including

STVD/STVP development environment, the STice emulator and a low-cost, third party in-

circuit debugging tool (for more details, see Section 14: STM8 development tools on

page 110).

Doc ID 14395 Rev 6

11/118

Product line-up

STM8AF51xx, STM8AF61xx

3

Product line-up

.

Table 2.

STM8AF/H/P51xx product line-up with CAN

I/0

wakeup

pins

Prog.

RAM Data EE 10-bit

Timers

Serial

Order code

Package

(bytes) (bytes) (bytes) A/D ch. (IC/OC/PWM) interfaces

STM8AF/H/P51AAT

STM8AF/H/P519AT

STM8AF/H/P51A9T

STM8AF/H/P5199T

STM8AF/H/P5189T

STM8AF/H/P5179T

STM8AF/H/P5169T

STM8AF/H/P51A8T

STM8AF/H/P5198T

STM8AF/H/P5188T

STM8AF/H/P5178T

1. QFN package planned

128 K

96 K

LQFP80

(14x14)

72/37

56/36

6 K

2 K

128 K

96 K

64 K

48 K

32 K

128 K

96 K

64 K

48 K

16

10

LQFP64

(10x10)

CAN,

LIN(UART)

, SPI,

USART,

I²C

4 K

3 K

2 K

1x8-bit: TIM4

3x16-bit: TIM1,

TIM2, TIM3

(9/9/9)

1.5 K

1 K

6 K

2 K

LQFP48

(7x7)⁽¹⁾

40/35

4 K

3 K

1.5 K

²

Table 3.

STM8AF/H/P61xx product line-up without CAN

Data

I/0

wakeup

pins

Prog.

RAM

10-bit

Timers

Serial

Order code

Package

EE

(bytes) (bytes)

A/D ch. (IC/OC/PWM) interfaces

(bytes)

STM8AF/H/P61AAT

STM8AF/H/P619AT

STM8AF/H/P61A9T

STM8AF/H/P6199T

STM8AF/H/P6189T

STM8AF/H/P6179T

STM8AF/H/P6169T

STM8AF/H/P61A8T

STM8AF/H/P6198T

STM8AF/H/P6188T

STM8AF/H/P6178T

STM8AF/H/P6186T

128 K

LQFP80

(14x14)

72/37

56/36

96 K

6 K

128 K

2 K

96 K

16

LQFP64

(10x10)

1x8-bit: TIM4

3x16-bit:

TIM1, TIM2, SPI, USART,

64 K

48 K

32 K

128 K

96 K

64 K

48 K

64 K

4 K

3 K

2 K

LIN(UART),

1.5 K

1 K

TIM3

(9/9/9)

I²C

6 K

2 K

LQFP48

(7x7)⁽¹⁾

10

7

40/35

25/23

4 K

3 K

4 K

1.5 K

1x8-bit: TIM4

3x16-bit:

TIM1, TIM2,

TIM3 (8/8/8)

LQFP32

(7x7)⁽¹⁾

LIN(UART),

SPI, I²C

STM8AF/H/P6176T

48 K

3 K

1. QFN package planned.

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Doc ID 14395 Rev 6

STM8AF51xx, STM8AF61xx

Block diagram

4

Block diagram

Figure 1.

STM8A block diagram

Reset block

Reset

XTAL 1-24 MHz

RC int. 16 MHz

RC int. 128 kHz

Clock controller

Detector

Reset

POR

PDR

Clock to peripherals and core

Window WDG

WDG

STM8A CORE

Single wire

debug interf.

Up to 128 Kbyte

program

Debug/SWIM

LINUART

Flash

Master/slave

autosynchro

Up to 2 Kbytes

data EEPROM

400 Kbit/s

10 Mbit/s

2

Up to 6 Kbytes

RAM

I C

Boot ROM

SPI

16-bit multi-purpose

timer (TIM1)

LIN master

SPI emul.

USART

beCAN

Up to

9 CAPCOM

channels

16-bit PWM timers

(TIM2, TIM3)

1 Mbit/s

8-bit AR timer

(TIM4)

Up to

16 channels

10-bit ADC

AWU timer

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Product overview

STM8AF51xx, STM8AF61xx

5

Product overview

This section is intended to describe the family features that are actually implemented in the

products covered by this datasheet.

For more detailed information on each feature please refer to the STM8A microcontroller

family reference manual (RM0009).

5.1

STM8A central processing unit (CPU)

The 8-bit STM8A core is a modern CISC core and has been designed for code efficiency

and performance. It contains 21 internal registers (six directly addressable in each execution

context), 20 addressing modes including indexed indirect and relative addressing and 80

instructions.

5.1.1

Architecture and registers

●

●

●

●

Harvard architecture

3-stage pipeline

32-bit wide program memory bus with single cycle fetching for most instructions

X and Y 16-bit index registers, enabling indexed addressing modes with or without

offset and read-modify-write type data manipulations

●

●

●

●

8-bit accumulator

24-bit program counter with 16-Mbyte linear memory space

16-bit stack pointer with access to a 64 Kbyte stack

8-bit condition code register with seven condition flags for the result of the last

instruction.

5.1.2

5.1.3

Addressing

●

●

20 addressing modes

Indexed indirect addressing mode for look-up tables located anywhere in the address

space

●

Stack pointer relative addressing mode for efficient implementation of local variables

and parameter passing

Instruction set

●

●

●

●

●

●

●

80 instructions with 2-byte average instruction size

Standard data movement and logic/arithmetic functions

8-bit by 8-bit multiplication

16-bit by 8-bit and 16-bit by 16-bit division

Bit manipulation

Data transfer between stack and accumulator (push/pop) with direct stack access

Data transfer using the X and Y registers or direct memory-to-memory transfers

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STM8AF51xx, STM8AF61xx

Product overview

5.2

Single wire interface module (SWIM) and debug module (DM)

5.2.1

SWIM

The single wire interface module, SWIM, together with an integrated debug module, permits

non-intrusive, real-time in-circuit debugging and fast memory programming. The interface

can be activated in all device operation modes and can be connected to a running device

(hot plugging).The maximum data transmission speed is 145 bytes/ms.

5.2.2

Debug module

The non-intrusive debugging module features a performance close to a full-flavored

emulator. Besides memory and peripheral operation, CPU operation can also be monitored

in real-time by means of shadow registers.

●

●

●

R/W of RAM and peripheral registers in real-time

R/W for all resources when the application is stopped

Breakpoints on all program-memory instructions (software breakpoints), except the

interrupt vector table

●

Two advanced breakpoints and 23 predefined breakpoint configurations

5.3

Interrupt controller

●

●

●

●

Nested interrupts with three software priority levels

24 interrupt vectors with hardware priority

Five vectors for external interrupts (up to 37 depending on the package)

Trap and reset interrupts

5.4

Flash program and data EEPROM

●

●

●

32 Kbytes to 128 Kbytes of single voltage program Flash memory

Up to 2 Kbytes true (not emulated) data EEPROM

Read while write: Writing in the data memory is possible while executing code in the

program memory

●

The device setup is stored in a user option area in the non volatile memory

5.4.1

Architecture

●

●

●

●

The memory is organized in blocks of 128 bytes each

Read granularity: 1 word = 4 bytes

Write/erase granularity: 1 word (4 bytes) or 1 block (128 bytes) in parallel

Writing, erasing, word and block management is handled automatically by the memory

interface.

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Product overview

STM8AF51xx, STM8AF61xx

5.4.2

Write protection (WP)

Write protection in application mode is intended to avoid unintentional overwriting of the

memory. The write protection can be removed temporarily by executing a specific sequence

in the user software.

5.4.3

Protection of user boot code (UBC)

If the user chooses to update the program memory using a specific boot code to perform in

application programming (IAP), this boot code needs to be protected against unwanted

modification.

In the STM8A a memory area of up to 128 Kbytes can be protected from overwriting at user

option level. Other than the standard write protection, the UBC protection can exclusively be

modified via the debug interface, the user software cannot modify the UBC protection status.

The UBC memory area contains the reset and interrupt vectors and its size can be adjusted

in increments of 512 bytes by programming the UBC and NUBC option bytes

(see Section 9: Option bytes on page 58).

Figure 2.

Flash memory organization of STM8A products

Data memory area

Option bytes

Data

EEPROM

memory

Programmable area from 1 Kbyte

(first two pages) up to program memory

end - maximum 128 Kbytes

UBC area

Remains write protected during IAP

Flash

program

memory

Program memory area

Write access possible for IAP

5.4.4

Read-out protection (ROP)

The STM8A provides a read-out protection of the code and data memory which can be

activated by an option byte setting (see the ROP option byte in section 10).

The read-out protection prevents reading and writing program memory, data memory and

option bytes via the debug module and SWIM interface. This protection is active in all device

operation modes. Any attempt to remove the protection by overwriting the ROP option byte

triggers a global erase of the program and data memory.

The ROP circuit may provide a temporary access for debugging or failure analysis. The

temporary read access is protected by a user defined, 8-byte keyword stored in the option

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STM8AF51xx, STM8AF61xx

Product overview

byte area. This keyword must be entered via the SWIM interface to temporarily unlock the

device.

If desired, the temporary unlock mechanism can be permanently disabled by the user

throughOPT6/NOPT6 option bytes.

5.5

Clock controller

The clock controller distributes the system clock coming from different oscillators to the core

and the peripherals. It also manages clock gating for low-power modes and ensures clock

robustness.

5.5.1

Features

●

Clock sources

–

–

–

Internal 16 MHz and 128 kHz RC oscillators

Crystal/resonator oscillator

External clock input

●

●

Reset: After reset the microcontroller restarts by default with an internal 2-MHz clock

(16 MHz/8). The clock source and speed can be changed by the application program

as soon as the code execution starts.

Safe clock switching: Clock sources can be changed safely on the fly in run mode

through a configuration register. The clock signal is not switched until the new clock

source is ready. The design guarantees glitch-free switching.

●

●

Clock management: To reduce power consumption, the clock controller can stop the

clock to the core, individual peripherals or memory.

Wakeup: In case the device wakes up from low-power modes, the internal RC

oscillator (16 MHz/8) is used for quick startup. After a stabilization time, the device

switches to the clock source that was selected before halt mode was entered.

●

●

Clock security system (CSS): The CSS permits monitoring of external clock sources

and automatic switching to the internal RC (16 MHz/8) in case of a clock failure.

Configurable main clock output (CCO): This feature permits to outputs a clock signal

for use by the application.

5.5.2

Internal 16 MHz RC oscillator

●

●

Default clock after reset 2 MHz (16 MHz/8)

Fast wakeup time

User trimming

The register CLK_HSITRIMR with two trimming bits plus one additional bit for the sign

permits frequency tuning by the application program. The adjustment range covers all

possible frequency variations versus supply voltage and temperature. This trimming does

not change the initial production setting.

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Product overview

STM8AF51xx, STM8AF61xx

5.5.3

Internal 128 kHz RC oscillator

The frequency of this clock is 128 kHz and it is independent from the main clock. It drives

the independent watchdog or the AWU wakeup timer.

In systems which do not need independent clock sources for the watchdog counters, the

128 kHz signal can be used as the system clock. This configuration has to be enabled by

setting an option byte (OPT3/OPT3N, bit LSI_EN).

5.5.4

Internal high-speed crystal oscillator

The internal high-speed crystal oscillator can be selected to deliver the main clock in normal

run mode. It operates with quartz crystals and ceramic resonators.

●

●

●

Frequency range: 1 MHz to 24 MHz

Crystal oscillation mode: preferred fundamental

I/Os: standard I/O pins multiplexed with OSCIN, OSCOUT

5.5.5

5.5.6

External clock input

An external clock signal can be applied to the OSCIN input pin of the crystal oscillator. The

frequency range is 0 to 24 MHz.

Clock security system (CSS)

The clock security system protects against a system stall in case of an external crystal clock

failure.

In case of a clock failure an interrupt is generated and the high-speed internal clock (HSI) is

automatically selected with a frequency of 2 MHz (16 MHz/8).

5.6

Low-power operating modes

The product features various low-power modes:

●

Slow mode: prescaled CPU clock, selected peripherals at full clock speed

●

Active halt mode: CPU and peripheral clocks are stopped, the device cyclically goes

back to run mode, controlled by the AWU timer. Wakeup through external events is

possible.

●

Halt mode: CPU and peripheral clocks are stopped, the device remains powered on.

Wakeup is triggered by an external interrupt.

In all modes the CPU and peripherals remain permanently powered on, the system clock is

applied only to selected modules. The RAM content is preserved and the brown-out reset

circuit remains activated.

5.7

Timers

5.7.1

Watchdog timers

The watchdog system is based on two independent timers providing maximum security to

the applications. The watchdog timer activity is controlled by the application program or

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Product overview

option bytes. Once the watchdog is activated, it cannot be disabled by the user program

without going through reset.

Window watchdog timer

The window watchdog is used to detect the occurrence of a software fault, usually

generated by external interferences or by unexpected logical conditions, which cause the

application program to abandon its normal sequence.

The window function can be used to trim the watchdog behavior to match the application

timing perfectly. The application software must refresh the counter before time-out and

during a limited time window. If the counter is refreshed outside this time window, a reset is

issued.

Independent watchdog timer

The independent watchdog peripheral can be used to resolve malfunctions due to hardware

or software failures.

It is clocked by the 128 kHz LSI internal RC clock source, and thus stays active even in case

of a CPU clock failure. If the hardware watchdog feature is enabled through the device

option bits, the watchdog is automatically enabled at power-on, and generates a reset

unless the key register is written by software before the counter reaches the end of count.

5.7.2

5.7.3

Auto-wakeup counter

This counter is used to cyclically wakeup the device in active halt mode. It can be clocked by

the internal 128 kHz internal low-frequency RC oscillator or external clock

Beeper

This function generates a rectangular signal in the range of 1, 2 or 4 kHz which can be

output on a pin. This is useful when audible sounds without interference need to be

generated for use in the application.

5.7.4

Multipurpose and PWM timers

STM8A devices described in this datasheet, contain up to three 16-bit multipurpose and

PWM timers providing nine CAPCOM channels in total. A CAPCOM channel can be used

either as input compare, output compare or PWM channel. These timers are named TIM1,

TIM2 and TIM3.

Table 4.

Timer

PWM timers

Counter Counter Prescaler

Inverted Repetition trigger External Break

Channels

width

type

factor

outputs

counter

unit

trigger

input

TIM1

TIM2

16-bit

Up/down 1 to 65536

4

3

3

Yes

Yes

Yes

Yes

2ⁿ

16-bit

16-bit

Up

None

None

No

No

No

No

No

No

No

No

n = 0 to 15

2ⁿ

TIM3

Up

2

n = 0 to 15

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Product overview

STM8AF51xx, STM8AF61xx

TIM1: Multipurpose PWM timer

This is a high-end timer designed for a wide range of control applications. With its

complementary outputs, dead-time control and center-aligned PWM capability, the field of

applications is extended to motor control, lighting and bridge driver.

●

16-bit up, down and up/down AR (auto-reload) counter with 16-bit fractional prescaler.

●

Four independent CAPCOM channels configurable as input capture, output compare,

PWM generation (edge and center aligned mode) and single pulse mode output

●

Trigger module which allows the interaction of TIM1 with other on-chip peripherals. In

the present implementation it is possible to trigger the ADC upon a timer event.

●

●

●

●

External trigger to change the timer behavior depending on external signals

Break input to force the timer outputs into a defined state

Three complementary outputs with adjustable dead time

Interrupt sources: 4 x input capture/output compare, 1 x overflow/update, 1 x break

TIM2 and TIM3: 16-bit PWM timers

●

●

●

●

16-bit auto-reload up-counter

15-bit prescaler adjustable to fixed power of two ratios 1…32768

Timers with three or two individually configurable CAPCOM channels

Interrupt sources: 2 or 3 x input capture/output compare, 1 x overflow/update

5.7.5

System timer

The typical usage of this timer (TIM4) is the generation of a clock tick.

Table 5.

Timer

TIM4

Counter Counter Prescaler

width

Inverted Repetition trigger External Break

Channels

type

factor

outputs

counter

unit

trigger

input

2ⁿ

TIM4

8-bit

Up

0

None

No

No

No

No

n = 0 to 7

●

●

●

8-bit auto-reload, adjustable prescaler ratio to any power of two from 1 to 128

Clock source: master clock

Interrupt source: 1 x overflow/update

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Product overview

5.8

Analog to digital converter (ADC)

The STM8A products described in this datasheet contain a 10-bit successive approximation

ADC with up to 16 multiplexed input channels, depending on the package.

ADC features:

●

●

●

●

●

●

●

●

●

10-bit resolution

Single and continuous conversion modes

Programmable prescaler: f

divided by 2 to 18

MASTER

Conversion trigger on timer events, and external events

Interrupt generation at end of conversion

Selectable alignment of 10-bit data in 2 x 8 bit result registers

Shadow registers for data consistency

ADC input range: VSSA = VIN = VDDA

Schmitt-trigger on analog inputs can be disabled to reduce power consumption

5.9

Communication interfaces

5.9.1

Universal synchronous/asynchronous receiver transmitter (USART)

The devices covered by this datasheet contain one USART interface. The USART can

operate in standard SCI mode (serial communication interface, asynchronous) or in SPI

emulation mode. It is equipped with a 16 bit fractional prescaler. It features LIN master

support.

Detailed feature list:

●

●

●

Full duplex, asynchronous communications

NRZ standard format (mark/space)

High-precision baud rate generator system

–

Common programmable transmit and receive baud rates up to f

/16

MASTER

●

●

●

Programmable data word length (8 or 9 bits)

Configurable stop bits: Support for 1 or 2 stop bits

LIN master mode:

–

–

LIN break and delimiter generation

LIN break and delimiter detection with separate flag and interrupt source for

readback checking.

●

●

●

Transmitter clock output for synchronous communication

Separate enable bits for transmitter and receiver

Transfer detection flags:

–

–

–

Receive buffer full

Transmit buffer empty

End of transmission flags

●

Parity control:

–

–

Transmits parity bit

Checks parity of received data byte

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Product overview

STM8AF51xx, STM8AF61xx

●

Four error detection flags:

–

–

–

–

Overrun error

Noise error

Frame error

Parity error

●

Six interrupt sources with flags:

–

–

–

–

–

–

Transmit data register empty

Transmission complete

Receive data register full

Idle line received

Parity error

LIN break and delimiter detection

●

Two interrupt vectors:

–

–

Transmitter interrupt

Receiver interrupt

●

●

●

Reduced power consumption mode

Wakeup from mute mode (by idle line detection or address mark detection)

Two receiver wakeup modes:

–

–

Address bit (MSB)

Idle line

5.9.2

Universal asynchronous receiver/transmitter with LIN support

(LINUART)

The devices covered by this datasheet contain one LINUART interface. The interface is

available on all the supported packages. The LINUART is an asynchronous serial

communication interface which supports extensive LIN functions tailored for LIN slave

applications. In LIN mode it is compliant to the LIN standards rev 1.2 to rev 2.1.

Detailed feature list:

LIN mode

Master mode

●

LIN break and delimiter generation

●

LIN break and delimiter detection with separate flag and interrupt source for read back

checking.

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STM8AF51xx, STM8AF61xx

Slave mode

Product overview

●

●

●

●

Autonomous header handling – one single interrupt per valid header

Mute mode to filter responses

Identifier parity error checking

LIN automatic resynchronization, allowing operation with internal RC oscillator (HSI)

clock source

●

●

Break detection at any time, even during a byte reception

Header errors detection:

–

–

–

–

–

Delimiter too short

Synch field error

Deviation error (if automatic resynchronization is enabled)

Framing error in synch field or identifier field

Header time-out

UART mode

●

●

Full duplex, asynchronous communications - NRZ standard format (mark/space)

High-precision baud rate generator

A common programmable transmit and receive baud rates up to f

–

/16

MASTER

●

●

●

●

●

●

●

Programmable data word length (8 or 9 bits) – 1 or 2 stop bits – parity control

Separate enable bits for transmitter and receiver

Error detection flags

Reduced power consumption mode

Multi-processor communication - enter mute mode if address match does not occur

Wakeup from mute mode (by idle line detection or address mark detection)

Two receiver wakeup modes:

–

–

Address bit (MSB)

Idle line

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Product overview

STM8AF51xx, STM8AF61xx

5.9.3

Serial peripheral interface (SPI)

The devices covered by this datasheet contain one SPI. The SPI is available on all the

supported packages.

●

●

●

●

●

●

●

Maximum speed: 8 Mbit/s or f

/2 both for master and slave

MASTER

Full duplex synchronous transfers

Simplex synchronous transfers on two lines with a possible bidirectional data line

Master or slave operation - selectable by hardware or software

CRC calculation

1 byte Tx and Rx buffer

Slave mode/master mode management by hardware or software for both master and

slave

●

●

●

●

●

Programmable clock polarity and phase

Programmable data order with MSB-first or LSB-first shifting

Dedicated transmission and reception flags with interrupt capability

SPI bus busy status flag

Hardware CRC feature for reliable communication:

–

–

CRC value can be transmitted as last byte in Tx mode

CRC error checking for last received byte

2

5.9.4

Inter integrated circuit (I C) interface

2

The devices covered by this datasheet contain one I C interface. The interface is available

on all the supported packages.

2

●

I C master features:

–

Clock generation

–

Start and stop generation

2

●

I C slave features:

2

–

–

Programmable I C address detection

Stop bit detection

●

●

Generation and detection of 7-bit/10-bit addressing and general call

Supports different communication speeds:

–

–

Standard speed (up to 100 kHz),

Fast speed (up to 400 kHz)

●

●

Status flags:

–

–

–

Transmitter/receiver mode flag

End-of-byte transmission flag

2

I C busy flag

Error flags:

–

–

–

–

Arbitration lost condition for master mode

Acknowledgement failure after address/data transmission

Detection of misplaced start or stop condition

Overrun/underrun if clock stretching is disabled

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Product overview

●

Interrupt:

–

–

–

Successful address/data communication

Error condition

Wakeup from halt

●

Wakeup from halt on address detection in slave mode

5.9.5

Controller area network interface (beCAN)

The beCAN controller (basic enhanced CAN), interfaces the CAN network and supports the

CAN protocol version 2.0A and B. It is equipped with a receive FIFO and a very versatile

filter bank. Together with a filter match index, this allows a very efficient message handling in

today’s car network architectures. The CPU is significantly unloaded. The maximum

transmission speed is 1 Mbit/s.

Transmission

●

●

Three transmit mailboxes

Configurable transmit priority by identifier or order request

Reception

●

●

●

●

●

●

●

11- and 29-bit ID

1 receive FIFO (3 messages deep)

Software-efficient mailbox mapping at a unique address space

FMI (filter match index) stored with message for quick message association

Configurable FIFO overrun

Time stamp on SOF reception

6 filter banks, 2 x 32 bytes (scalable to 4 x 16-bit) each, enabling various masking

configurations, such as 12 filters for 29-bit ID or 48 filters for 11-bit ID.

●

Filtering modes (mixable):

–

–

Mask mode permitting ID range filtering

ID list mode

Interrupt management

●

●

Maskable interrupt

Software-efficient mailbox mapping at a unique address space

5.10

Input/output specifications

The product features four I/O types:

●

●

●

●

Standard I/O 2 MHz

Fast I/O up to 10 MHz

High sink 8 mA, 2 MHz

2

True open drain (I C interface)

To decrease EMI (electromagnetic interference), high sink I/Os have a limited maximum

slew rate. The rise and fall times are similar to those of standard I/Os.

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Product overview

STM8AF51xx, STM8AF61xx

The analog inputs are equipped with a low leakage analog switch. Additionally, the schmitt-

trigger input stage on the analog I/Os can be disabled in order to reduce the device standby

consumption.

STM8A I/Os are designed to withstand current injection. For a negative injection current of

4 mA, the resulting leakage current in the adjacent input does not exceed 1 µA. Thanks to

this feature, external protection diodes against current injection are no longer required.

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STM8AF51xx, STM8AF61xx

Pinouts and pin description

6

Pinouts and pin description

6.1

Package pinouts

Figure 3.

LQFP 80-pin pinout

60

59

58

57

56

55

54

53

52

51

50

49

48

47

46

45

44

43

42

41

1

2

3

4

5

6

7

8

NRST

OSCIN/PA1

OSCOUT/PA2

PI3

PI2

PI1

PI0

V

SSIO_1

V

PG4

PG3

PG2

PG1/CAN_RX

PG0/CAN_TX

PC7/SPI_MISO

PC6/SPI_MOSI

SS

VCAP

V

DD

(1)

V

DDIO_1

(1)

9

TIM2_CC3/PA3

10

11

12

13

14

15

16

17

18

19

20

USART_RX/PA4

USART_TX/PA5

USART_CK/PA6

(HS) PH0

V

V

DDIO_2

SSIO_2

(HS) PH1

PC5/SPI_SCK

PH2

PH3

AIN15/PF7

AIN14/PF6

AIN13/PF5

AIN12/PF4

PC4 (HS)/TIM1_CC4

PC3 (HS)/TIM1_CC3

PC2 (HS)/TIM1_CC2

PC1 (HS)/TIM1_CC1

PC0/ADC_ETR

PE5/SPI_NSS

1. The CAN interface is only available on the STM8AF/H/P51xx product line.

2. HS stands for high sink capability.

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Pinouts and pin description

Figure 4. LQFP 64-pin pinout

STM8AF51xx, STM8AF61xx

64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49

48

PI0

NRST

OSCIN/PA1

OSCOUT/PA2

1

PG4

PG3

PG2

PG1/CAN_RX

PG0/CAN_TX

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

2

3

4

5

6

7

8

9

V

SSIO_1

(1)

V

SS

(1)

VCAP

PC7/SPI_MISO

PC6/SPI_MOSI

V

DD

V

DDIO_1

V

TIM2_CC3/PA3

USART_RX/PA4

USART_TX/PA5

USART_CK/PA6

DDIO_2

V

10

11

12

SSIO_2

PC5/SPI_SCK

PC4 (HS)/TIM1_CC4

PC3 (HS)/TIM1_CC3

PC2 (HS)/TIM1_CC2

PC1 (HS)/TIM1_CC1

PE5/SPI_NSS

AIN15/PF7 13

AIN14/PF6

14

AIN13/PF5 15

AIN12/PF4 16

1718 1920212223242526272829303132

1. The CAN interface is only available on the STM8AF/H/P51xx product line.

2. HS stands for high sink capability.

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STM8AF51xx, STM8AF61xx

Figure 5. LQFP 48-pin pinout

Pinouts and pin description

48 47 46 45 4443424140393837

36

NRST

OSCIN/PA1

PG1/CAN_Rx

PG0/CAN_Tx

35

1

2

OSCOUT/PA2

3

4

34 PC7/SPI_MISO

33 PC6/SPI_MOSI

V

SSIO_1

V

32

31

30

29

28

27

26

25

5

6

7

8

9

10

11

V

V

SS

DDIO_2

VCAP

SSIO_2

V

PC5/SPI_SCK

DD

V

PC4 (HS)/TIM1_CC4

PC3 (HS)/TIM1_CC3

PC2 (HS)/TIM1_CC2

PC1 (HS)/TIM1_CC1

PE5/SPI_NSS

DDIO_1

TIM2_CC3/PA3

USART_RX/PA4

USART_TX/PA5

USART_CK/PA6

12

24

1314 15161718192021 2223

1. The CAN interface is only available on the STM8AF/H/P51xx product line.

2. HS stands for high sink capability.

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Pinouts and pin description

Figure 6. LQFP 32-pin pinout

STM8AF51xx, STM8AF61xx

32 31 30 29 28 27 26 25

24

NRST

OSCIN/PA1

OSCOUT/PA2

1

2

3

4

5

6

7

8

PC7/SPI_MISO

PC6/SPI_MOSI

PC5/SPI_SCK

PC4 (HS)/TIM1_CC4

PC3 (HS)/TIM1_CC3

PC2 (HS)/TIM1_CC2

PC1 (HS)/TIM1_CC1

PE5/SPI_NSS

23

22

21

20

19

18

17

V

SS

VCAP

V

DD

V

DDIO

AIN12/PF4

9 101112 13141516

1. HS stands for high sink capability.

Table 6.

Legend/abbreviation for Table 7

I= input, O = output, S = power supply

Type

Input

CM = CMOS (standard for all I/Os)

HS = high sink (8 mA)

Level

Output

O1 = Standard (up to 2 MHz)

O2 = Fast (up to 10 MHz)

O3 = Fast/slow programmability with slow as default state after reset

O4 = Fast/slow programmability with fast as default state after reset

Output speed

Input

float = floating, wpu = weak pull-up

Port and control

configuration

Output

T = true open drain, OD = open drain, PP = push pull

30/118

Doc ID 14395 Rev 6

STM8AF51xx, STM8AF61xx

Pinouts and pin description

Table 7.

STM8A microcontroller family pin description

Pin number

Input

Output

Alternate

function

after

remap

[option bit]

Main

function

(after

Default

alternate

function

Pin name

reset)

1

2

1

2

1

2

1

2

NRST

I/O

-

X

X

—

—

—

—

—

—

X

—

X

Reset

—

—

Resonator/

crystal in

PA1/OSCIN⁽¹⁾I/O

X

O1

Port A1

Port A2

Resonator/

crystal out

3

3

3

3

PA2/OSCOUT I/O

X

X

X

—

O1

X

X

—

4

5

6

7

8

4

5

6

7

8

4

5

6

7

8

-

V_{SSIO_1}

V_SS

S

S

S

S

S

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

I/O ground

Digital ground

—

—

—

—

—

4

5

6

7

VCAP

V_DD

— 1.8 V regulator capacitor

—

—

Digital power supply

I/O power supply

V_{DDIO_1}

Timer 2 -

Port A3

TIM3_CC1

[AFR1]

9

9

9

-

-

-

PA3/TIM2_CC3 I/O

PA4/USART_RX I/O

PA5/USART_TX I/O

X

X

X

X

X

X

X

X

X

—

—

—

O1

O3

O3

X

X

X

X

X

X

channel 3

USART

Port A4

10 10 10

11 11 11

—

—

receive

USART

Port A5

transmit

USART

Port A6 synchronous

clock

12 12 12

-

PA6/USART_CK I/O

X

X

X

—

O3

X

X

—

13

14

15

16

-

-

-

-

-

-

-

-

-

-

-

-

PH0

PH1

PH2

PH3

I/O

I/O

I/O

I/O

X

X

X

X

X

X

X

X

—

—

—

—

HS O3

HS O3

X

X

X

X

X

X

X

X

Port H0

Port H1

Port H2

Port H3

—

—

—

—

—

—

—

—

—

—

O1

O1

Analog

input 15

17 13

18 14

19 15

20 16

21 17

22 18

-

-

-

-

-

-

-

-

PF7/AIN15

PF6/AIN14

PF5/AIN13

PF4/AIN12

PF3/AIN11

V_REF+

I/O

I/O

I/O

I/O

I/O

S

X

X

X

X

—

—

—

—

—

—

—

—

—

—

—

—

O1

O1

O1

O1

O1

—

X

X

X

X

Port F7

Port F6

Port F5

Port F4

Port F3

—

—

—

—

—

—

Analog

input 14

Analog

input 13

-

X

X

X

X

Analog

input 12

8

-

X

X

X

X

Analog

input 11

X

X

X

X

ADC positive reference

voltage

-

—

—

—

—

Doc ID 14395 Rev 6

31/118

Pinouts and pin description

STM8AF51xx, STM8AF61xx

Alternate

Table 7.

STM8A microcontroller family pin description (continued)

Pin number

Input

Output

Main

function

(after

Default

alternate

function

function

after

remap

Pin name

reset)

[option bit]

23 19 13

9

V_DDA

V_SSA

S

S

—

—

—

—

—

—

—

—

—

—

—

—

—

—

Analog power supply

Analog ground

—

—

24 20 14 10

ADC negative reference

voltage

25 21

26 22

-

-

-

-

V_REF-

S

—

X

—

X

—

—

—

—

—

—

X

—

X

—

—

Analog

Port F0

PF0/AIN10

I/O

O1

input 10

27 23 15

28 24 16

-

-

PB7/AIN7

PB6/AIN6

I/O

I/O

X

X

X

X

X

X

—

—

O1

O1

X

X

X

X

Port B7 Analog input 7

Port B6 Analog input 6

—

—

I²C_SDA

[AFR6]

29 25 17 11

30 26 18 12

31 27 19 13

PB5/AIN5

PB4/AIN4

PB3/AIN3

I/O

I/O

I/O

X

X

X

X

X

X

X

X

X

—

—

—

O1

O1

O1

X

X

X

X

X

X

Port B5 Analog input 5

Port B4 Analog input 4

Port B3 Analog input 3

I²C_SCL

[AFR6]

TIM1_ETR

[AFR5]

TIM1_NCC

3

[AFR5]

32 28 20 14

33 29 21 15

34 30 22 16

PB2/AIN2

PB1/AIN1

PB0/AIN0

I/O

I/O

I/O

X

X

X

X

X

X

—

—

O1

O1

X

X

X

X

Port B2 Analog input

Port B1 Analog input 1

Port B0 Analog input 0

TIM1_NCC

2

[AFR5]

TIM1_NCC

1

[AFR5]

X

X

X

X

X

X

X

—

—

—

O1

O1

O1

X

X

X

X

X

X

Timer 1 -

Port H4

35

36

-

-

-

-

-

-

PH4/TIM1_ETR I/O

—

—

—

—

trigger input

Timer 1 -

PH5/

I/O

Port H5

Port H6

Port H7

inverted

channel 3

TIM1_NCC3

Timer 1 -

inverted

channel 2

PH6/

I/O

37

38

-

-

-

-

-

X

X

X

X

—

—

—

—

O1

O1

X

X

X

X

—

—

TIM1_NCC2

Timer 1 -

inverted

PH7/

I/O

-

-

TIM1_NCC1

channel 2

39 31 23

40 32 24

PE7/AIN8

PE6/AIN9

I/O

I/O

X

X

X

X

—

X

—

—

O1

O1

X

X

X

X

Port E7 Analog input 8

Port E7 Analog input 9

—

—

SPI master/

Port E5

41 33 25 17 PE5/SPI_NSS I/O

X

X

X

—

O1

X

X

—

slave select

32/118

Doc ID 14395 Rev 6

STM8AF51xx, STM8AF61xx

Pinouts and pin description

Alternate

Table 7.

STM8A microcontroller family pin description (continued)

Pin number

Input

Output

Main

function

(after

Default

alternate

function

function

after

remap

Pin name

reset)

[option bit]

ADC trigger

input

42

-

-

-

PC0/ADC_ETR I/O

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

—

O1

X

X

X

X

X

X

X

X

X

X

Port C0

Port C1

Port C2

Port C3

—

—

—

—

—

Timer 1 -

channel 1

43 34 26 18 PC1/TIM1_CC1 I/O

44 35 27 19 PC2/TIM1_CC2 I/O

45 36 28 20 PC3/TIM1_CC3 I/O

HS O3

HS O3

HS O3

HS O3

Timer 1-

channel 2

Timer 1 -

channel 3

Timer 1 -

channel 4

46 37 29 21 PC4/TIM1_CC4 I/O

47 38 30 22 PC5/SPI_SCK I/O

Port C4

Port C5

X

X

X

—

—

—

O3

—

X

X

SPI clock

—

—

—

48 39 31

49 40 32

-

-

V_{SSIO_2}

V_{DDIO_2}

S

S

—

—

—

—

—

—

—

—

—

—

I/O ground

—

I/O power supply

SPI master

50 41 33 23 PC6/SPI_MOSI I/O

51 42 34 24 PC7/SPI_MISO I/O

X

X

X

X

X

X

—

—

O3

O3

X

X

X

X

Port C6

out/

slave in

—

—

SPI master in/

slave out

Port C7

52 43 35

53 44 36

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

PG0/CAN_Tx I/O

PG1/CAN_Rx I/O

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

—

—

—

—

—

—

—

—

—

—

—

—

—

—

X

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

O1

O1

O1

O1

O1

O1

O1

O1

O1

O1

O1

O1

O1

O1

O1

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

Port G0 CAN transmit

Port G1 CAN receive

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

54 45

55 46

56 47

57 48

-

-

-

-

-

-

-

-

-

-

-

-

-

PG2

PG3

PG4

PI0

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

Port G2

Port G3

Port G4

Port I0

Port I1

Port I2

Port I3

Port I4

Port I5

Port G5

Port G6

Port G7

Port E4

—

—

—

—

—

—

—

—

—

—

—

—

—

58

59

60

61

62

-

-

-

-

-

PI1

PI2

PI3

PI4

PI5

63 49

64 50

65 51

66 52

PG5

PG6

PG7

PE4

Doc ID 14395 Rev 6

33/118

Pinouts and pin description

STM8AF51xx, STM8AF61xx

Alternate

Table 7.

STM8A microcontroller family pin description (continued)

Pin number

Input

Output

Main

function

(after

Default

alternate

function

function

after

remap

Pin name

reset)

[option bit]

Timer 1 -

break input

67 53 37

-

PE3/TIM1_BKIN I/O

X

X

X

—

O1

X

X

Port E3

—

68 54 38

69 55 39

-

-

PE2/I²C_SDA I/O

PE1/I²C_SCL I/O

X

X

X

X

X

X

—

—

O1 T⁽²⁾

O1 T⁽²⁾

-

-

Port E2

Port E1

I²C data

I²C clock

—

—

Configurable

clock output

70 56 40

-

PE0/CLK_CCO I/O

X

X

X

—

O3

X

X

Port E0

—

71

72

-

-

-

-

-

-

PI6

PI7

I/O

I/O

X

X

X

X

—

—

—

—

O1

O1

X

X

X

X

Port I6

Port I7

—

—

—

—

TIM1_BKIN

[AFR3]/

CLK_CCO

[AFR2]

Timer 3 -

channel 2

73 57 41 25 PD0/TIM3_CC2 I/O

X

X

X

HS O3

X

X

Port D0

SWIM data

interface

74 58 42 26

PD1/SWIM

I/O

X

X

X

X

X

X

X

X

X

HS O4

HS O3

HS O3

X

X

X

X

X

X

Port D1

Port D2

Port D3

—

Timer 3 -

channel 1

TIM2_CC3

[AFR1]

75 59 43 27 PD2/TIM3_CC1 I/O

76 60 44 28 PD3/TIM2_CC2 I/O

PD4/TIM2_CC1/

Timer 2 -

channel 2

ADC_ETR

[AFR0]

BEEP

output

[AFR7]

Timer 2 -

channel 1

77 61 45 29

I/O

X

X

X

X

X

X

HS O3

X

X

X

X

Port D4

BEEP

PD5/

LINUART_TX

LINUART

data transmit

78 62 46 30

I/O

—

—

—

O1

O1

O1

Port D5

Port D6

—

—

LINUART

data receive

PD6/

LINUART_RX

79 63 47 31

80 64 48 32

I/O

I/O

X

X

X

X

X

X

X

X

X

X

Top level

interrupt

PD7/TLI⁽³⁾

Port D7

—

1. In halt/active halt mode, this pin behaves as follows:

- The input/output path is disabled.

- If the HSE clock is used for wakeup, the internal weak pull-up is disabled.

- If the HSE clock is off, the internal weak pull-up setting is used. It is configured through Px_CR1[7:0] bits of the

corresponding port control register. Px_CR1[7:0] bits must be set correctly to ensure that the pin is not left floating in

halt/active halt mode.

2. In the open-drain output column, ‘T’ defines a true open-drain I/O (P-buffer and protection diode to V_DDare not

implemented)

3. If this pin is configured as interrupt pin, it will trigger the TLI.

34/118

Doc ID 14395 Rev 6

STM8AF51xx, STM8AF61xx

Pinouts and pin description

6.2

Alternate function remapping

As shown in the rightmost column of Table 7, some alternate functions can be remapped at

different I/O ports by programming one of eight AFR (alternate function remap) option bits.

Refer to Section 9: Option bytes on page 58. When the remapping option is active, the

default alternate function is no longer available.

To use an alternate function, the corresponding peripheral must be enabled in the peripheral

registers.

Alternate function remapping does not effect GPIO capabilities of the I/O ports (see the

GPIO section of the STM8A microcontroller family reference manual, RM0009).

Doc ID 14395 Rev 6

35/118

Memory and register map

STM8AF51xx, STM8AF61xx

7

Memory and register map

7.1

Memory map

Figure 7.

Register and memory map

00 0000

Up to 6 Kbytes RAM

Stack

RAM end address

Reserved

00 4000

00 4800

Up to 2 Kbytes data EEPROM

Option bytes

Reserved

00 4900

00 5000

HW registers

00 5800

00 6000

00 6800

00 7F00

00 8000

00 8080

Reserved

2 Kbytes boot ROM

CPU registers

IT vectors

Up to 128 Kbytes

Flash program memory

Memory end address

Table 8.

Memory model 128K

Programmemory Programmemory

RAM end

address

Stack roll-over

address

RAM size

size

end address

128K

96K

64K

48K

32K

27FFFh

1FFFFh

17FFFh

13FFFh

0FFFFh

6K

6K

4K

3K

2K

17FFh

17FFh

0FFFh

0BFFh

07FFh

1400h

1400h

n/a ⁽¹⁾

n/a⁽¹⁾

n/a⁽¹⁾

1. if the device is containing the super set silicon (salestype contains SSS), the roll-over address is the same

as on the 128K device. For more information on stack handling refer to section 2.1.2 in the reference

manual RM0009. For more information on salestype composition, refer to section 13 in the present

document.

36/118

Doc ID 14395 Rev 6

STM8AF51xx, STM8AF61xx

Memory and register map

7.2

Register map

In this section the memory and register map of the devices covered by this datasheet is

described. For a detailed description of the functionality of the registers, refer to the

reference manual RM009.

7.2.1

I/O register map

Table 9.

Address

I/O port hardware register map

Reset

status

Block

Register label

Register name

00 5000h

00 5001h

00 5002h

00 5003h

00 5004h

00 5005h

00 5006h

00 5007h

00 5008h

00 5009h

00 500Ah

00 500Bh

00 500Ch

00 500Dh

00 500Eh

00 500Fh

00 5010h

00 5011h

00 5012h

00 5013h

00 5014h

00 5015h

00 5016h

00 5017h

00 5018h

PA_ODR

PA_IDR

Port A data output latch register

Port A input pin value register

Port A data direction register

Port A control register 1

00h

00h

00h

00h

00h

00h

00h

00h

00h

00h

00h

00h

00h

00h

00h

00h

00h

00h

02h

00h

00h

00h

00h

00h

00h

Port A

PA_DDR

PA_CR1

PA_CR2

PB_ODR

PB_IDR

PB_DDR

PB_CR1

PB_CR2

PC_ODR

PB_IDR

PC_DDR

PC_CR1

PC_CR2

PD_ODR

PD_IDR

PD_DDR

PD_CR1

PD_CR2

PE_ODR

PE_IDR

PE_DDR

PE_CR1

PE_CR2

Port A control register 2

Port B data output latch register

Port B input pin value register

Port B data direction register

Port B control register 1

Port B

Port C

Port D

Port E

Port B control register 2

Port C data output latch register

Port C input pin value register

Port C data direction register

Port C control register 1

Port C control register 2

Port D data output latch register

Port D input pin value register

Port D data direction register

Port D control register 1

Port D control register 2

Port E data output latch register

Port E input pin value register

Port E data direction register

Port E control register 1

Port E control register 2

Doc ID 14395 Rev 6

37/118

Memory and register map

Table 9. I/O port hardware register map (continued)

Address Register name

STM8AF51xx, STM8AF61xx

Reset

status

Block

Register label

00 5019h

00 501Ah

00 501Bh

00 501Ch

00 501Dh

00 501Eh

00 501Fh

00 5020h

00 5021h

00 5022h

00 5023h

00 5024h

00 5025h

00 5026h

00 5027h

00 5028h

00 5029h

00 502Ah

00 502Bh

00 502Ch

PF_ODR

PF_IDR

PF_DDR

PF_CR1

PF_CR2

PG_ODR

PG_IDR

PG_DDR

PG_CR1

PG_CR2

PH_ODR

PH_IDR

PH_DDR

PH_CR1

PH_CR2

PI_ODR

PI_IDR

Port F data output latch register

Port F input pin value register

Port F data direction register

Port F control register 1

00h

00h

00h

00h

00h

00h

00h

00h

00h

00h

00h

00h

00h

00h

00h

00h

00h

00h

00h

00h

Port F

Port F control register 2

Port G data output latch register

Port G input pin value register

Port G data direction register

Port G control register 1

Port G

Port H

Port I

Port G control register 2

Port H data output latch register

Port H input pin value register

Port H data direction register

Port H control register 1

Port H control register 2

Port I data output latch register

Port I input pin value register

Port I data direction register

Port I control register 1

PI_DDR

PI_CR1

PI_CR2

Port I control register 2

7.2.2

Non volatile memory

Table 10. Non volatile memory

Address Register name

7

6

5

4

3

2

1

0

FLASH_CR1

00 505Ah

-

-

-

-

HALT AHALT

IE

0

FIX

0

Reset value

0

0

0

0

0

0

FLASH_CR2

00 505Bh

OPT

0

WPRG

0

ERASE

0

FPRG

0

-

-

-

PRG

0

Reset value

0

0

0

FLASH_NCR2

00 505Ch

NOPT NWPRG NERASE NFPRG

-

-

-

NPRG

1

Reset value

1

1

1

1

1

1

1

FLASH_FPR

00 505Dh

WPB7

0

WPB6

0

WPB5

0

WPB4 WPB3 WPB2 WPB1

WPB0

0

Reset value

0

0

0

0

FLASH_NFPR NWPB7 NWPB6 NWPB5 NWPB4 NWPB3 NWPB2 NWPB1

NWPB0

1

00 505Eh

38/118

Reset value

1

1

1

1

1

1

1

Doc ID 14395 Rev 6

STM8AF51xx, STM8AF61xx

Memory and register map

Table 10. Non volatile memory (continued)

Address Register name

7

6

5

4

3

2

1

0

FLASH_IAPSR

00 505Fh

-

HVOFF

1

-

-

DUL

0

EOP

0

PUL

0

WR_PG_DIS

0

Reset value

0

0

0

00 5060h

to

Reserved

00 5061h

FLASH_PUKR

00 5062h

PUK7

0

PUK6

0

PUK5

0

PUK4

0

PUK3

0

PUK2

0

PUK1

0

PUK0

0

Reset value

00 5063h

Reserved

FLASH_DUKR

00 5064h

DUK7

0

DUK6

0

DUK5

0

DUK4

0

DUK3

0

DUK2

0

DUK1

0

DUK0

0

Reset value

7.2.3

CPU registers

Table 11. CPU registers

Reset

status

Address

Block

Register label

Register name

00 7F00h

00 7F01h

00 7F02h

00 7F03h

00 7F04h

00 7F05h

00 7F06h

00 7F07h

00 7F08h

00 7F09h

00 7F0Ah

A

Accumulator

Program counter extended

Program counter high

Program counter low

X index register high

X index register low

Y index register high

Y index register low

Stack pointer high

00h

00h

80h

00h

00h

00h

00h

00h

17h⁽²⁾

FFh

28h

PCE

PCH

PCL

XH

CPU⁽¹⁾

XL

YH

YL

SPH

SPL

CC

Stack pointer low

Condition code register

1. Accessible by debug module only

2. Product dependent value, see Figure 7: Register and memory map.

7.2.4

Miscellaneous registers

Global configuration register

Table 12. CFG_GCR register map

Address Register name

7

6

5

4

3

2

1

0

CFG_GCR

00 7F60h

-

-

-

-

-

-

AL

0

SWD

0

Reset value

0

0

0

0

0

0

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Memory and register map

STM8AF51xx, STM8AF61xx

Reset status register

Table 13. RST_SR register map

Address Register name

7

6

5

4

3

2

1

0

RST_SR

00 50B3h

-

-

-

EMCF SWIMF ILLOPF IWDGF

WWDGF

x

Reset value

x

x

x

x

x

x

x

Temporary memory unprotection key registers

Table 14. TMU register map and reset values

Address Register name

7

6

5

4

3

2

1

0

TMU_K1

00 5800h

K7

0

K6

0

K5

0

K4

0

K3

0

K2

0

K1

0

K0

0

Reset value

TMU_K2

00 5801h

K7

0

K6

0

K5

0

K4

0

K3

0

K2

0

K1

0

K0

0

Reset value

TMU_K3

00 5802h

K7

0

K6

0

K5

0

K4

0

K3

0

K2

0

K1

0

K0

0

Reset value

TMU_K4

00 5803h

K7

0

K6

0

K5

0

K4

0

K3

0

K2

0

K1

0

K0

0

Reset value

TMU_K5

00 5804h

K7

0

K6

0

K5

0

K4

0

K3

0

K2

0

K1

0

K0

0

Reset value

TMU_K6

00 5805h

K7

0

K6

0

K5

0

K4

0

K3

0

K2

0

K1

0

K0

0

Reset value

TMU_K8

00 5807h

K7

0

K6

0

K5

0

K4

0

K3

0

K2

0

K1

0

K0

0

Reset value

TMU_CSR

00 5808h

-

-

-

-

ROPS TIMUE TMUB

TMUS

0

Reset value

0

0

0

0

0

0

0

7.2.5

Clock and clock controller

Table 15. CLK register map and reset values

Register

Address

7

6

5

4

3

2

1

0

name

-

-

SWUAH LSIRDY

LSIEN

FHWU

HSIRDY

0

HSIEN

CLK_ICKR

00 50C0h

Reset

value

0

-

0

-

0

-

0

-

0

-

0

-

1

CLK_

ECKR

HSERDY HSEEN

00 50C1h

00 50C2h

Reset

value

0

0

0

0

0

0

0

0

Reserved

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Doc ID 14395 Rev 6

STM8AF51xx, STM8AF61xx

Memory and register map

Table 15. CLK register map and reset values (continued)

Register

Address

7

6

5

4

3

2

1

0

name

CLK_

CMSR

CKM7

CKM6

CKM5

CKM4

CKM3

CKM2

CKM1

CKM0

00 50C3h

Reset

value

1

1

1

0

0

0

0

1

SWI7

SWI6

SWI5

SWI4

SWI3

SWI2

SWI1

SWI0

CLK_SWR

00 50C4h

00 50C5h

Reset

value

1

-

1

-

1

-

0

-

0

0

0

1

CLK_

SWCR

SWIF

SWIEN

SWEN

SWBSY

Reset

value

x

-

x

-

x

-

x

0

0

0

0

CLK_

CKDIVR

HSIDIV1 HSIDIV0 CPUDIV2 CPUDIV1 CPUDIV

00 50C6h

00 50C7h

00 50C8h

00 50C9h

Reset

value

0

0

0

1

1

0

0

0

PCK

EN17

PCK

EN16

PCK

EN15

PCK

EN14

PCK

EN13

PCK

EN12

PCK

EN11

PCK

EN10

CLK_

PCKENR1

Reset

value

1

-

1

-

1

-

1

-

1

1

1

1

CLK_

CSSR

CSSD

CSSDIE

AUX

CSSEN

Reset

value

0

-

0

0

0

0

0

0

0

CCOBSY CCORDY

CCOEN

CCO

SEL3

CCO

SEL2

CCO

SEL1

CCO

SEL0

CLK_

CCOR

Reset

value

0

-

0

0

0

-

0

0

0

-

0

-

PCK

EN27

PCK

EN26

PCK

EN23

PCK

EN22

CLK_PCK

ENR2

00 50CAh

00 50CBh

00 50CCh

Reset

value

1

-

1

-

1

-

1

1

-

1

-

1

1

CLK_CAN

CCR

CANDIV2 CANDIV1 CANDIV0

Reset

value

0

-

0

-

0

-

0

-

0

-

0

0

0

HSI

TRIM2

HSI

TRIM1

HSI

TRIM0

CLK_HSIT

RIMR

Reset

value

0

-

0

-

0

x

-

x

-

x

-

x

-

x

-

SWI

MCLK

CLK_SWI

MCCR

00 50CDh

Reset

value

0

0

0

0

0

0

0

0

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Memory and register map

STM8AF51xx, STM8AF61xx

7.2.6

Interrupt controller

Interrupt software priority registers

Table 16. Interrupt software priority registers map

Register

Address

7

6

5

4

3

2

1

0

name

Reserved Reserved

VECT3S VECT3S VECT2S VECT2S VECT1S VECT1S

ITC_SPR1

Reset

PR1

PR0

PR1

PR0

PR1

PR0

00 7F70h

value

1

1

1

1

1

1

1

1

VECT7S VECT7S VECT6S VECT6S VECT5S VECT5S VECT4S VECT4S

ITC_SPR2

Reset

PR1

PR0

PR1

PR0

PR1

PR0

PR1

PR0

00 7F71h

00 7F72h

00 7F73h

00 7F74h

00 7F75h

00 7F76h

value

1

1

1

1

1

1

1

1

VECT11 VECT11 VECT10 VECT10 VECT9S VECT9S VECT8S VECT8S

SPR1

ITC_SPR3

Reset

SPR0

SPR1

SPR0

PR1

PR0

PR1

PR0

value

1

1

1

1

1

1

1

1

VECT15 VECT15 VECT14 VECT14 VECT13 VECT13 VECT12 VECT12

SPR1

ITC_SPR4

Reset

SPR0

SPR1

SPR0

SPR1

SPR0

SPR1

SPR0

value

1

1

1

1

1

1

1

1

VECT19 VECT19 VECT18 VECT18 VECT17 VECT17 VECT16 VECT16

SPR1

ITC_SPR5

Reset

SPR0

SPR1

SPR0

SPR1

SPR0

SPR1

SPR0

value

1

1

1

1

1

1

1

1

VECT23 VECT23 VECT22 VECT22 VECT21 VECT21 VECT20 VECT20

SPR1

ITC_SPR6

Reset

SPR0

SPR1

SPR0

SPR1

SPR0

SPR1

SPR0

value

1

1

1

1

1

1

1

1

Reserved Reserved Reserved Reserved Reserved Reserved

VECT24 VECT24

SPR1

ITC_SPR7

Reset

SPR0

value

1

1

1

1

1

1

1

1

External interrupt control register

Table 17. External interrupt control register map

Register

Address

00 50A0h

00 50A1h

7

6

5

4

3

2

1

0

name

PDIS1

0

PDIS0

0

PCIS1

0

PCIS0

0

PBIS1

0

PBIS0

0

PAIS1

0

PAIS0

0

EXTI_CR1

Reset value

Reserved Reserved Reserved Reserved Reserved

TLIS

0

PEIS1

0

PEIS0

0

EXTI_CR2

Reset value

0

0

0

0

0

42/118

Doc ID 14395 Rev 6

STM8AF51xx, STM8AF61xx

Memory and register map

7.2.7

Timers

Window watchdog timer

Table 18. WWDG register map and reset values

Register

Address

00 50D1h

00 50D2h

7

6

5

4

3

2

1

0

name

WDGA

0

T6

1

T5

1

T4

1

T3

1

T2

1

T1

1

T0

1

WWDG_CR

Reset value

-

W6

1

W5

1

W4

1

W3

1

W2

1

W1

1

W0

1

WWDG_WR

Reset value

0

Independent watchdog timer

Table 19. IWDG register map

Register

Address

00 50E0h

00 50E1h

00 50E2h

7

6

5

4

3

2

1

0

name

KEY7

x

KEY6

x

KEY5

x

KEY4

x

KEY3

x

KEY2

x

KEY1

x

KEY0

x

IWDG_KR

Reset value

-

-

-

-

-

PR2

0

PR1

0

PR0

0

IWDG_PR

Reset value

0

0

0

0

0

RL7

1

RL6

1

RL5

1

RL4

1

RL3

1

RL2

1

RL1

1

RL0

1

IWDG_RLR

Reset value

Auto-wakeup counter and beeper

Table 20. AWU register map

Register

Address

00 50F0h

00 50F1h

00 50F2h

7

6

5

4

3

2

1

0

name

AWU_CSR

Reset value

-

-

AWUF

0

AWUEN

0

-

-

-

MSR

0

0

0

0

0

0

AWU_APR

Reset value

-

-

APR5

1

APR4

1

APR3

1

APR2

1

APR1

1

APR0

1

0

0

AWU_TBR

Reset value

-

-

-

-

AWUTB3 AWUTB2 AWUTB1 AWUTB0

0

0

0

0

0

0

0

0

Table 21. BEEP register map

Register

Address

7

6

5

4

3

2

1

0

name

BEEP_CSR

BEEP

SEL2

BEEP

SEL1

BEEP

EN

BEEP

DIV4

BEEP

DIV3

BEEP

DIV2

BEEP

DIV1

BEEP

DIV0

00 50F3h

0

0

0

0

0

0

0

0

Reset value

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Memory and register map

STM8AF51xx, STM8AF61xx

TIM1

Table 22. TIM1 register map

Address Register name

7

6

5

4

3

2

1

0

ARPE

0

CMS1

0

CMS0

0

DIR

0

OPM

0

URS

0

UDIS

0

CEN

0

TIM1_CR1

00 5250h

Reset value

TI1S

0

MMS2

0

MMS1

0

MMS0

0

-

COMS

0

-

CCPC

0

TIM1_CR2

00 5251h

Reset value

0

0

MSM

0

TS2

0

TS1

0

TS0

0

-

SMS2

0

SMS1

0

SMS0

0

TIM1_SMCR

00 5252h

Reset value

0

ETP

0

ECE

0

ETPS1

0

ETPS0

0

EFT3

0

EFT2

0

EFT1

0

EFT0

0

TIM1_ETR

00 5253h

Reset value

BIE

0

TIE

0

COMIE

0

CC4IE

0

CC3IE

0

CC2IE

0

CC1IE

0

UIE

0

TIM1_IER

00 5254h

Reset value

BIF

0

TIF

0

COMIF

0

CC4IF

0

CC3IF

0

CC2IF

0

CC1IF

0

UIF

0

TIM1_SR1

00 5255h

Reset value

-

-

-

CC4OF CC3OF CC2OF

CC1OF

0

-

TIM1_SR2

00 5256h

Reset value

0

0

0

0

0

0

0

BG

0

TG

0

COMG

0

CC4G

0

CC3G

0

CC2G

0

CC1G

0

UG

0

TIM1_EGR

00 5257h

Reset value

TIM1_CCMR1 OC1CE OC1M2 OC1M1 OC1M0 OC1PE

(output mode)

OC1FE

CC1S1

CC1S0

Reset value

0

0

0

0

0

0

0

0

00 5258h

00 5259h

00 525Ah

TIM1_CCMR1

(input mode)

Reset value

IC1F3

IC1F2

IC1F1

IC1F0 IC1PSC1 IC1PSC0 CC1S1

CC1S0

0

0

0

0

0

0

0

0

TIM1_ CCMR2 OC2CE OC2M2 OC2M1 OC2M0 OC2PE

(output mode)

OC2FE

CC2S1

CC2S0

Reset value

0

0

0

0

0

0

0

0

TIM1_CCMR2

(input mode)

Reset value

IC2F3

IC2F2

IC2F1

IC2F0 IC2PSC1 IC2PSC0 CC2S1

CC2S0

0

0

0

0

0

0

0

0

TIM1_CCMR3 OC3CE OC3M2 OC3M1 OC3M0 OC3PE

(output mode)

OC3FE

CC3S1

CC3S0

Reset value

0

0

0

0

0

0

0

0

TIM1_CCMR3

(input mode)

Reset value

IC3F3

IC3F2

IC3F1

IC3F0 IC3PSC1 IC3PSC0 CC3S1

CC3S0

0

0

0

0

0

0

0

0

44/118

Doc ID 14395 Rev 6

STM8AF51xx, STM8AF61xx

Memory and register map

Table 22. TIM1 register map (continued)

Address Register name

7

6

5

4

3

2

1

0

TIM1_CCMR4 OC4CE OC4M2 OC4M1 OC4M0 OC4PE

(output mode)

OC4FE

CC4S1

CC4S0

Reset value

0

0

0

0

0

0

0

0

00 525Bh

TIM1_CCMR4

(input mode)

Reset value

IC4F3

IC4F2

IC4F1

IC4F0 IC4PSC1 IC4PSC0 CC4S1

CC4S0

0

0

0

0

0

0

0

0

TIM1_CCER1 CC2NP CC2NE

CC2P

0

CC2E

0

CC1NP CC1NE

CC1P

0

CC1E

0

00525Ch

00525Dh

00 525Eh

00 525Fh

00 5260h

00 5261h

00 5262h

00 5263h

00 5264h

00 5265h

00 5266h

00 5267h

00 5268h

00 5269h

00 526Ah

00 526Bh

00526Ch

Reset value

0

0

0

0

TIM1_CCER2

Reset value

-

-

CC4P

0

CC4E

0

CC3NP CC3NE

CC3P

0

CC3E

0

0

0

0

0

TIM1_CNTRH

Reset value

CNT15

0

CNT14

0

CNT13

0

CNT12

0

CNT11

0

CNT10

0

CNT9

0

CNT8

0

TIM1_CNTRL

Reset value

CNT7

0

CNT6

0

CNT5

0

CNT4

0

CNT3

0

CNT2

0

CNT1

0

CNT0

0

TIM1_PSCRH

Reset value

PSC15

0

PSC14

0

PSC13

0

PSC12

0

PSC11

0

PSC10

0

PSC9

0

PSC8

0

TIM1_PSCRL

Reset value

PSC7

0

PSC6

0

PSC5

0

PSC4

0

PSC3

0

PSC2

0

PSC1

0

PSC0

0

TIM1_ARRH

Reset value

ARR15 ARR14 ARR13 ARR12

ARR11

1

ARR10

1

ARR9

1

ARR8

1

1

1

1

1

TIM1_ARRL

Reset value

ARR7

1

ARR6

1

ARR5

1

ARR4

1

ARR3

1

ARR2

1

ARR1

1

ARR0

1

TIM1_RCR

Reset value

REP7

0

REP6

0

REP5

0

REP4

0

REP3

0

REP2

0

REP1

0

REP0

0

TIM1_CCR1H CCR115 CCR114 CCR113 CCR112 CCR111 CCR110 CCR19

CCR18

0

Reset value

0

0

0

0

0

0

0

TIM1_CCR1L

Reset value

CCR17 CCR16 CCR15 CCR14 CCR13

CCR12

0

CCR11

0

CCR10

0

0

0

0

0

0

TIM1_CCR2H CCR215 CCR214 CCR213 CCR212 CCR211 CCR210 CCR29

CCR28

0

Reset value

0

0

0

0

0

0

0

TIM1_CCR2L

Reset value

CCR27 CCR26 CCR25 CCR24 CCR23

CCR22 CCR21 0 CCR20

0

0

0

0

0

0

0

TIM1_CCR3H CCR315 CCR314 CCR313 CCR312 CCR311 CCR310 CCR39

CCR38

0

Reset value

0

0

0

0

0

0

0

TIM1_CCR3L

Reset value

CCR37 CCR36 CCR35 CCR34 CCR33

CCR32

0

CCR31

0

CCR3

0 0

0

0

0

0

0

TIM1_CCR4H CCR415 CCR414 CCR413 CCR412 CCR411 CCR410 CCR49 0 CCR48

Reset value

0

0

0

0

0

0

0

TIM1_CCR4L

Reset value

CCR47 CCR46 CCR45 CCR44 CCR43

CCR42

0

CCR41

0

CCR40

0

0

0

0

0

0

Doc ID 14395 Rev 6

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Memory and register map

STM8AF51xx, STM8AF61xx

Table 22. TIM1 register map (continued)

Address Register name

7

6

5

4

3

2

1

0

TIM1_BKR

00526Dh

MOE

0

AOE

0

BKP

0

BKE

0

OSSR

0

OSSI

0

LOCK

0

LOCK

0

Reset value

TIM1_DTR

00 526Eh

DTG7

0

DTG6

0

DTG5

0

DTG4

0

DTG3

0

DTG2

0

DTG1

0

DTG0

0

Reset value

TIM1_OISR

00 526Fh

-

OIS4

0

OIS3N

0

OIS3

0

OIS2N

0

OIS2

0

OIS1N

0

OIS1

0

Reset value

0

TIM2

Table 23. TIM2 register map

Address Register name

7

6

5

4

3

2

1

0

TIM2_CR1

00 5300h

ARPE

0

-

-

-

OPM

0

URS

0

UDIS

0

CEN

0

Reset value

0

0

0

TIM2_IER

00 5301h

-

-

-

-

CC3IE

0

CC2IE

0

CC1IE

0

UIE

0

Reset value

0

0

0

0

TIM2_SR1

00 5302h

-

-

-

-

CC3IF

0

CC2IF

0

CC1IF

0

UIF

0

Reset value

0

0

0

0

TIM2_SR2

00 5303h

-

-

-

-

CC3OF

0

CC2OF CC1OF

-

Reset value

0

0

0

0

0

0

0

TIM2_EGR

00 5304h

-

-

-

-

CC3G

0

CC2G

0

CC1G

0

UG

0

Reset value

0

0

0

0

-

OC1M2 OC1M1 OC1M0 OC1PE

-

CC1S1 CC1S0

TIM2_CCMR1

(output mode)

Reset value

00 5305h

0

0

0

0

0

0

0

0

IC1F3

IC1F2

IC1F1

IC1F0 IC1PSC1 IC1PSC0 CC1S1 CC1S0

TIM2_CCMR1

(input mode)

Reset value

0

-

0

0

0

0

0

-

0

0

OC2M2 OC2M1 OC2M0 OC2PE

CC2S1 CC2S0

TIM2_ CCMR2

(output mode)

Reset value

00 5306h

0

0

0

0

0

0

0

0

IC2F3

IC2F2

IC2F1

IC2F0 IC2PSC1 IC2PSC0 CC2S1 CC2S0

TIM2_CCMR2

(input mode)

Reset value

0

-

0

0

0

0

0

-

0

0

OC3M2 OC3M1 OC3M0 OC3PE

CC3S1 CC3S0

TIM2_CCMR3

(output mode)

Reset value

00 5307h

0

0

0

0

0

0

0

0

IC3F3

IC3F2

IC3F1

IC3F0 IC3PSC1 IC3PSC0 CC3S1 CC3S0

TIM2_CCMR3

(input mode)

Reset value

0

0

0

0

0

0

0

0

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Doc ID 14395 Rev 6

STM8AF51xx, STM8AF61xx

Memory and register map

Table 23. TIM2 register map (continued)

Address Register name

7

6

5

4

3

2

1

0

TIM2_CCER1

00 5308h

-

-

CC2P

0

CC2E

0

-

-

CC1P

0

CC1E

0

Reset value

0

0

0

0

TIM2_CCER2

00 5309h

-

-

-

-

-

-

CC3P

0

CC3E

0

Reset value

0

0

0

0

0

0

TIM2_CNTRH CNT15

CNT14

0

CNT13

0

CNT12

0

CNT11

0

CNT10

0

CNT9

0

CNT8

0

00 530Ah

00 530Bh

00 530Ch

00 530Dh

00 530Eh

00 530Fh

00 5310h

00 5311h

00 5312h

00 5313h

00 5314h

Reset value

0

TIM2_CNTRL

Reset value

CNT7

0

CNT6

0

CNT5

0

CNT4

0

CNT3

0

CNT2

0

CNT1

0

CNT0

0

TIM2_PSCR

Reset value

-

-

-

-

PSC3

0

PSC2

0

PSC1

0

PSC0

0

0

0

0

0

TIM2_ARRH

Reset value

ARR15 ARR14 ARR13 ARR12

ARR11

1

ARR10

1

ARR9

1

ARR8

1

1

1

1

1

TIM2_ARRL

Reset value

ARR7

1

ARR6

1

ARR5

1

ARR4

1

ARR3

1

ARR2

1

ARR1

1

ARR0

1

TIM2_CCR1H CCR115 CCR114 CCR113 CCR112 CCR111 CCR110 CCR19 CCR18

Reset value

0

0

0

0

0

0

0

0

TIM2_CCR1L

Reset value

CCR17 CCR16 CCR15 CCR14

CCR13

0

CCR12

0

CCR11 CCR10

0

0

0

0

0

0

TIM2_CCR2H CCR215 CCR214 CCR213 CCR212 CCR211 CCR210 CCR29 CCR28

Reset value

0

0

0

0

0

0

0

0

TIM2_CCR2L

Reset value

CCR27 CCR26 CCR25 CCR24

CCR23

0

CCR22

0

CCR21 CCR20

0

0

0

0

0

0

TIM2_CCR3H CCR315 CCR314 CCR313 CCR312 CCR311 CCR310 CCR39 CCR38

Reset value

0

0

0

0

0

0

0

0

TIM2_CCR3L

Reset value

CCR37 CCR36 CCR35 CCR34

CCR33

0

CCR32

0

CCR31 CCR30

0

0

0

0

0

0

TIM3

Table 24. TIM3 register map

Address Register name

7

6

5

4

3

2

1

0

TIM3_CR1

00 5320h

ARPE

0

-

-

-

OPM

0

URS

0

UDIS

0

CEN

0

Reset value

0

0

0

TIM3_IER

00 5321h

-

-

-

-

-

CC2IE

0

CC1IE

0

UIE

0

Reset value

0

0

0

0

0

TIM3_SR1

00 5322h

-

-

-

-

-

CC2IF

0

CC1IF

0

UIF

0

Reset value

0

0

0

0

0

TIM3_SR2

00 5323h

-

-

-

-

-

CC2OF CC1OF

-

Reset value

0

0

0

0

0

0

0

0

Doc ID 14395 Rev 6

47/118

Memory and register map

STM8AF51xx, STM8AF61xx

Table 24. TIM3 register map (continued)

Address Register name

7

6

5

4

3

2

1

0

TIM3_EGR

00 5324h

-

-

-

-

-

CC2G

0

CC1G

0

UG

0

Reset value

0

0

0

0

0

-

OC1M2 OC1M1 OC1M0 OC1PE

-

CC1S1 CC1S0

TIM3_CCMR1

(output mode)

Reset value

00 5325h

0

0

0

0

0

0

0

0

IC1F3

IC1F2

IC1F1

IC1F0 IC1PSC1 IC1PSC0 CC1S1 CC1S0

TIM3_CCMR1

(input mode)

Reset value

0

-

0

0

0

0

0

-

0

0

OC2M2 OC2M1 OC2M0 OC2PE

CC2S1 CC2S0

TIM3_ CCMR2

(output mode)

Reset value

00 5326h

0

0

0

0

0

0

0

0

IC2F3

IC2F2

IC2F1

IC2F0 IC2PSC1 IC2PSC0 CC2S1 CC2S0

TIM3_CCMR2

(input mode)

Reset value

0

-

0

-

0

0

0

-

0

-

0

0

CC2P

CC2E

CC1P

CC1E

TIM3_CCER1

00 5327h

Reset value

0

0

0

0

0

0

0

0

TIM3_CNTRH CNT15

CNT14

0

CNT13

0

CNT12

0

CNT11

0

CNT10

0

CNT9

0

CNT8

0

00 5328h

00 5329h

00 532Ah

00 532Bh

00 532Ch

00 532Dh

00 532Eh

00 532Fh

00 5330h

Reset value

0

TIM3_CNTRL

Reset value

CNT7

0

CNT6

0

CNT5

0

CNT4

0

CNT3

0

CNT2

0

CNT1

0

CNT0

0

TIM3_PSCR

Reset value

-

-

-

-

PSC3

0

PSC2

0

PSC1

0

PSC0

0

0

0

0

0

TIM3_ARRH

Reset value

ARR15 ARR14 ARR13 ARR12

ARR11

1

ARR10

1

ARR9

1

ARR8

1

1

1

1

1

TIM3_ARRL

Reset value

ARR7

1

ARR6

1

ARR5

1

ARR4

1

ARR3

1

ARR2

1

ARR1

1

ARR0

1

TIM3_CCR1H CCR115 CCR114 CCR113 CCR112 CCR111 CCR110 CCR19 CCR18

Reset value

0

0

0

0

0

0

0

0

TIM3_CCR1L

Reset value

CCR17 CCR16 CCR15 CCR14

CCR13

0

CCR12

0

CCR11 CCR10

0

0

0

0

0

0

TIM3_CCR2H CCR215 CCR214 CCR213 CCR212 CCR211 CCR210 CCR29 CCR28

Reset value

0

0

0

0

0

0

0

0

TIM3_CCR2L

Reset value

CCR27 CCR26 CCR25 CCR24

CCR23

0

CCR22

0

CCR21 CCR20

0

0

0

0

0

0

48/118

Doc ID 14395 Rev 6

STM8AF51xx, STM8AF61xx

Memory and register map

TIM4

Table 25. TIM4 register map

Address Register name

7

6

5

4

3

2

1

0

TIM4_CR1

00 5340h

ARPE

0

-

-

-

OPM

0

URS

0

UDIS

0

CEN

0

Reset value

0

0

0

TIM4_IER

00 5341h

-

-

-

-

-

-

-

UIE

0

Reset value

0

0

0

0

0

0

0

TIM4_SR1

00 5342h

-

-

-

-

-

-

-

UIF

0

Reset value

0

0

0

0

0

0

0

TIM4_EGR

00 5343h

-

-

-

-

-

-

-

UG

0

Reset value

0

0

0

0

0

0

0

TIM4_CNTR

00 5344h

CNT7

0

CNT6

0

CNT5

0

CNT4

0

CNT3

0

CNT2

0

CNT1

0

CNT0

0

Reset value

TIM4_PSCR

00 5345h

-

-

-

-

-

PSC2

0

PSC1

0

PSC0

0

Reset value

0

0

0

0

0

TIM4_ARR

00 5346h

ARR7

1

ARR6

1

ARR5

1

ARR4

1

ARR3

1

ARR2

1

ARR1

1

ARR0

1

Reset value

7.2.8

Communication interfaces

Serial peripheral interface (SPI)

Table 26. SPI register map and reset value

Register

Address

005200h

005201h

005202h

005203h

005204h

005205h

7

6

5

4

3

2

1

0

name

SPI_CR1

LSBFIRST SPE

BR2

0

BR1

0

BR1

0

MSTR

CPOL

0

CPHA

0

Reset value

0

0

0

SPI_CR2

BDM

0

BDOE CRCEN CRCNEXT Reserved RXONLY

SSM

0

SSI

0

Reset value

0

0

0

0

0

SPI_ICR

TXIE

0

RXIE ERRIE

WKIE

0

Reserved Reserved Reserved Reserved

Reset value

0

0

0

0

0

0

SPI_SR

BSY

0

OVR MODF CRCERR

WKUP

0

Reserved

0

TXE

1

RXNE

0

Reset value

0

0

0

SPI_DR

MSB

0

-

-

-

-

-

-

LSB

0

Reset value

0

0

0

0

0

0

SPI_CRCPR

Reset value

MSB

0

-

-

-

-

-

-

LSB

1

0

0

0

0

1

1

Doc ID 14395 Rev 6

49/118

Memory and register map

STM8AF51xx, STM8AF61xx

Table 26. SPI register map and reset value (continued)

Register

Address

7

6

5

4

3

2

1

0

name

MSB

-

-

-

-

-

-

LSB

SPI_

RXCRCR

005206h

Reset value

0

0

-

0

-

0

-

0

-

0

-

0

-

0

MSB

LSB

SPI_

TXCRCR

005207h

Reset value

0

0

0

0

0

0

0

0

Inter integrated circuit (I²C) interface

2

Table 27. I C register map

Address Register name

7

6

5

4

3

2

1

0

I2C_CR1

ENGC

-

-

-

-

-

PE

NO

STRETCH

00 5210h

00 5211h

00 5212h

00 5213h

0

Reset value

0

-

0

-

0

-

0

0

0

0

SWRST

POS

ACK

STOP

START

I2C_CR2

Reset value

0

-

0

-

0

0

0

0

0

0

FREQ5 FREQ4 FREQ3 FREQ2

FREQ1

FREQ0

I2C_

FREQR

Reset value

0

0

0

0

0

0

0

0

ADD7

ADD6 ADD5

ADD4

ADD3

ADD2

ADD1

ADD0

I2C_OARL

Reset value

0

0

0

-

0

-

0

-

0

0

0

-

I2C_OARH

ADD9

ADD8

ADD

ADD

MODE

CONF

00 5214h

0

0

Reset value

0

0

Reserved

DR4

0

0

0

0

00 5215h

00 5216h

DR7

DR6

DR5

DR3

DR2

DR1

DR0

I2C_DR

Reset value

0

0

0

-

0

0

0

0

0

TxE

RxNE

STOPF

ADD10

BTF

ADDR

SB

I2C_SR1

00 5217h

00 5218h

Reset value

0

-

0

-

0

0

-

0

0

0

0

WUFH

OVR

AF

ARLO

BERR

I2C_SR2

Reset value

0

0

0

0

0

0

0

0

50/118

Doc ID 14395 Rev 6

STM8AF51xx, STM8AF61xx

Memory and register map

2

Table 27. I C register map (continued)

Address Register name

7

6

5

4

3

2

1

0

GEN

CALL

-

-

-

-

TRA

BUSY

MSL

I2C_SR3

00 5219h

Reset value

0

-

0

-

0

-

0

-

0

0

0

0

-

ITBUFEN ITEVTEN ITERREN

I2C_ITR

00 521Ah

Reset value

0

0

0

0

0

0

0

0

CCR7

CCR6 CCR5

CCR4

CCR3

CCR2

CCR1

CCR0

I2C_CCRL

00 521Bh

Reset value

0

0

0

-

0

-

0

0

0

0

FS

DUTY

CCR11 CCR10

CCR9

CCR8

I2C_CCRH

00 521Ch

Reset value

0

-

0

-

0

0

0

0

0

0

TRISE5 TRISE4 TRISE3 TRISE2 TRISE1

TRISE0

I2C_

TRISER

00 521Dh

Reset value

0

0

0

0

0

0

1

0

Universal synchronous/asynchronous receiver transmitter (USART)

Table 28. USART register map

Address

Register name

7

6

5

4

3

2

1

0

USART_SR

Reset value

TXE

1

TC

1

RXNE

0

IDLE

0

OR

0

NF

0

FE

0

PE

0

00 5230h

USART_DR

Reset value

DR7

x

DR6

x

DR5

x

DR4

x

DR3

x

DR2

x

DR1

x

DR0

x

00 5231h

00 5232h

00 5233h

00 5234h

00 5235h

00 5236h

00 5237h

USART_BRR1

Reset value

USART_DIV[11:4]

00000000

USART_BRR2

Reset value

USART_DIV[15:12]

0000

USART_DIV[3:0]

0000

USART_CR1

Reset value

R8

0

T8

0

USARTD

0

M

0

-

PCEN

0

PS

0

PIEN

0

0

USART_CR2

Reset value

TIEN

0

TCIEN

0

RIEN

0

ILIEN

0

TEN

0

REN

0

RWU

0

SBK

0

USART_CR3

Reset value

-

LINEN

0

STOP

00

CKEN

0

CPOL

0

CPHA LBCL

0

0

0

USART_CR4

Reset value

-

LBDIEN

0

LBDL

0

LBDF

0

-

-

-

-

0

0

0

0

0

Doc ID 14395 Rev 6

51/118

Memory and register map

STM8AF51xx, STM8AF61xx

Universal asynchronous receiver/transmitter with LIN support (LINUART)

Table 29. LINUART register map and reset value

Address Register name

7

6

5

4

3

2

1

0

LINUART_SR

00 5240h

TXE

1

TC

1

RXNE

0

IDLE

0

OR/LHE

0

NF

0

FE

0

PE

0

Reset value

LINUART_DR

005241h

DR7

0

DR6

0

DR5

0

DR4

0

DR3

0

DR2

0

DR1

0

DR0

0

Reset value

LINUART_BRR1

00 5242h

LDIV[11:8]

00000000

Reset value

LINUART_BRR2

00 5243h

LDIV[15:12]

0000

UARTD

LDIV[3:0]

0000

Reset value

LINUART_CR1

00 5244h

R8

0

T8

0

M

WAKE

0

PCEN

0

PS

0

PIEN

0

Reset value

0

0

LINUART_CR2

00 5245h

TIEN

0

TCIEN

0

RIEN

0

ILIEN

0

TEN

0

REN

0

RWU

0

SBK

0

Reset value

LINUART_CR3

00 5246h

-

LINEN

0

STOP

00

-

-

-

-

Reset value

0

0

0

0

0

LINUART_CR4

00 5247h

-

LBDIEN LBDL

LBDF

0

ADD[3:0]

0000

Reset value

0

0

0

00 5248h

Reserved

LINUART_CR6

00 5249h

LDUM

0

-

LSLV

0

LASE

0

-

LHDIEN

LHDF

0

LSF

0

Reset value

0

0

0

52/118

Doc ID 14395 Rev 6

STM8AF51xx, STM8AF61xx

CAN

Memory and register map

Figure 8.

CAN register mapping

5420h

5421h

5422h

5423h

5424h

5425h

5426h

5427h

CAN master control register

CAN master status register

CAN transmit status register

CAN transmit priority register

CAN receive FIFO register

CAN_MCR

CAN_MSR

CAN_TSR

CAN_TPR

CAN_RFR

CAN_IER

CAN interrupt enable register

CAN diagnostic register

CAN_DGR

CAN_PSR

CAN page selection register

Paged register 0

Paged register 1

Paged register 2

Paged register 3

Paged register 4

Paged register 5

Paged register 6

Paged register 7

Paged register 8

Paged register 9

Paged register 10

Paged register 11

Paged register 12

Paged register 13

XXh

Paged register 14

Paged register 15

Doc ID 14395 Rev 6

53/118

Memory and register map

STM8AF51xx, STM8AF61xx

Figure 9.

CAN page mapping

Page 2

Page 3

Page 4

Page 0

Page 1

00h

01h

02h

03h

04h

05h

06h

07h

08h

09h

0Ah

0Bh

0Ch

0Dh

0Eh

0Fh

CAN_F2R1

CAN_F2R2

CAN_F2R3

CAN_F2R4

CAN_F4R1

CAN_F4R2

CAN_F4R3

CAN_F4R4

CAN_F0R1

CAN_F0R2

CAN_F0R3

CAN_F0R4

CAN_MCSR

CAN_MDLCR

CAN_MIDR1

CAN_MIDR2

CAN_MCSR

CAN_MDLCR

CAN_MIDR1

CAN_MIDR2

CAN_F2R5

CAN_F2R6

CAN_F2R7

CAN_F2R8

CAN_F4R5

CAN_F4R6

CAN_F4R7

CAN_F4R8

CAN_F5R1

CAN_F5R2

CAN_F5R3

CAN_F5R4

CAN_F0R5

CAN_F0R6

CAN_F0R7

CAN_F0R8

CAN_MIDR3

CAN_MIDR4

CAN_MDAR1

CAN_MDAR2

CAN_MDAR3

CAN_MIDR3

CAN_MIDR4

CAN_MDAR1

CAN_MDAR5

CAN_MDAR6

CAN_F3R1

CAN_F3R2

CAN_F3R3

CAN_F3R4

CAN_F1R1

CAN_F1R2

CAN_F1R3

CAN_F1R4

CAN_MDAR4

CAN_MDAR5

CAN_MDAR6

CAN_MDAR4

CAN_MDAR5

CAN_MDAR6

CAN_MDAR7

CAN_MDAR8

CAN_MDAR7

CAN_MDAR8

CAN_F3R5

CAN_F3R6

CAN_F5R5

CAN_F5R6

CAN_F1R5

CAN_F1R6

CAN_F1R7

CAN_MTSRL

CAN_MTSRH

CAN_F3R7

CAN_F5R7

CAN_MTSRL

CAN_F3R8

CAN_F5R8

CAN_MTSRH

Tx mailbox 1

Page 6

CAN_F1R8

Acceptance filter 0:1

Page 7

Acceptance filter 2:3

Acceptance filter 4:5

Tx mailbox 0

Page 5

00h

01h

02h

03h

04h

05h

06h

07h

08h

09h

0Ah

0Bh

0Ch

0Dh

0Eh

0Fh

CAN_MCSR

CAN_MDLCR

CAN_MIDR1

CAN_MIDR2

CAN_ESR

CAN_EIER

CAN_TECR

CAN_RECR

CAN_MFMIR

CAN_MDLCR

CAN_MIDR1

CAN_MIDR2

CAN_MIDR3

CAN_MIDR4

CAN_MDAR1

CAN_MDAR2

CAN_MDAR3

CAN_BTR1

CAN_BTR2

Reserved

CAN_MIDR3

CAN_MIDR4

CAN_MDAR1

CAN_MDAR2

CAN_MDAR3

Reserved

CAN_FMR1

CAN_MDAR4

CAN_MDAR5

CAN_MDAR6

CAN_FMR2

CAN_FCR1

CAN_FCR2

CAN_MDAR4

CAN_MDAR5

CAN_MDAR6

CAN_MDAR7

CAN_MDAR8

CAN_FCR3

Reserved

CAN_MDAR7

CAN_MDAR8

CAN_MTSRL

CAN_MTSRH

Reserved

Reserved

CAN_MTSRL

CAN_MTSRH

Receive FIFO

Tx Mailbox 2

(if TXM2E = 1

Configuration/diagnostic

in CAN_DGR register)

54/118

Doc ID 14395 Rev 6

STM8AF51xx, STM8AF61xx

Memory and register map

7.3

Analog to digital converter (ADC)

Table 30. ADC register map and reset value

Address Register name

7

6

5

4

3

2

1

0

ADC _CSR

005400h

EOC

0

-

EOCIE

0

-

CH3

0

CH2

0

CH1

0

CH0

0

Reset value

0

0

ADC_CR1

005401h

-

SPSEL2 SPSEL1 SPSEL0

-

-

CONT

0

ADON

0

Reset value

0

0

0

0

0

0

ADC_CR2

005402h

-

EXTTRIG EXTSEL1 EXTSEL0 ALIGN

-

-

-

Reset value

0

0

0

0

0

0

0

0

00 5403h

Reserved

ADC_DRH1

005404h

DATA9

0

DATA8

0

DATA7

0

DATA6

0

DATA5

0

DATA4

0

DATA3

0

DATA2

0

Reset value

ADC_DRL1

005405h

-

-

-

-

-

-

DATA1

0

DATA0

0

Reset value

0

0

0

0

0

0

ADC_TDRH

005406h

TD15

0

TD14

0

TD13

0

TD12

0

TD11

0

TD10

0

TD9

0

TD8

0

Reset value

ADC_TDRL

005407h

TD7

0

TD6

0

TD5

0

TD4

0

TD3

0

TD2

0

TD1

0

TD0

0

Reset value

Doc ID 14395 Rev 6

55/118

Interrupt table

STM8AF51xx, STM8AF61xx

8

Interrupt table

(1)

Table 31. STM8A interrupt table

Source

Interruptvector Wakeup

Priority

Description

Comments

block

address

from halt

—

—

Reset

TRAP

Reset

SW interrupt

6000h

8004h

Yes

—

Reset vector in ROM

—

External top level

interrupt

0

1

2

TLI

8008h

800Ch

8010h

—

Yes

—

—

—

—

Auto-wakeup from

halt

AWU

Clock

controller

Main clock controller

3

4

5

6

7

8

MISC

MISC

MISC

MISC

MISC

CAN

External interrupt E0

External interrupt E1

External interrupt E2

External interrupt E3

External interrupt E4

CAN interrupt Rx

8014h

8018h

801Ch

8020h

8024h

8028h

Yes

Yes

Yes

Yes

Yes

Yes

Port A interrupts

Port B interrupts

Port C interrupts

Port D interrupts

Port E interrupts

—

CAN interrupt

TX/ER/SC

9

CAN

SPI

802Ch

8030h

8034h

—

Yes

—

—

—

—

10

11

End of transfer

Update/overflow/

trigger/break

Timer 1

12

13

14

15

16

Timer 1

Timer 2

Timer 2

Timer 3

Timer 3

Capture/compare

Update/overflow

Capture/compare

Update/overflow

Capture/compare

8038h

803Ch

8040h

8044h

8048h

—

—

—

—

—

—

—

—

—

—

USART

(SCI1)

17

Tx complete

804Ch

—

—

USART

(SCI1)

18

19

20

Receive data full reg.

I²C interrupts

8050h

8054h

8058h

—

Yes

—

—

—

—

I²C

LINUART

(SCI2)

Tx complete/error

LINUART

(SCI2)

21

22

Receive data full reg.

End of conversion

805Ch

8060h

—

—

—

—

ADC

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Table 31. STM8A interrupt table (continued)

Interrupt table

(1)

Source

block

Interruptvector Wakeup

Priority

Description

Comments

address

from halt

23

Timer 4

Update/overflow

8064h

—

—

End of programming/

24

EEPROM write in not allowed

area

8068h

—

—

1. All unused interrupts must be initialized with ‘IRET’ for robust programming.

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Option bytes

STM8AF51xx, STM8AF61xx

9

Option bytes

Option bytes contain configurations for device hardware features as well as the memory

protection of the device. They are stored in a dedicated block of the memory. Each option

byte has to be stored twice, for redundancy, in a regular form (OPTx) and a complemented

one (NOPTx), except for the ROP (read-out protection) option byte and option bytes 8 to 16.

Option bytes can be modified in ICP mode (via SWIM) by accessing the EEPROM address

shown in Table 32: Option bytes below.

Option bytes can also be modified ‘on the fly’ by the application in IAP mode, except the

ROP and UBC options that can only be changed in ICP mode (via SWIM).

Refer to the STM8 Flash programming manual (PM0047) and STM8 SWIM communication

protocol and debug module user manual (UM0470) for information on SWIM programming

procedures.

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Table 32. Option bytes

Option bytes

Option

Option

name

Option bits

Factory

default

setting

Addr.

byte

no.

7

6

5

4

3

2

1

0

Read-out

4800h protection

(ROP)

OPT0

ROP[7:0]

00h

4801h User boot OPT1

code

UBC[7:0]

00h

FFh

00h

4802h

NOPT1

NUBC[7:0]

(UBC)

4803h Alternate

function

OPT2

AFR7 AFR6 AFR5 AFR4 AFR3

AFR2

AFR1

AFR0

remapping

(AFR)

4804h

NOPT2 NAFR7 NAFR6 NAFR5 NAFR4 NAFR3 NAFR2 NAFR1 NAFR0

FFh

LSI_

EN

IWDG

_HW

WWD

G _HW _HALT

WWDG

4805h

OPT3

NOPT3

OPT4

Reserved

Reserved

Reserved

Reserved

00h

FFh

00h

FFh

Watchdog

option

NLSI_ NIWD

EN

NWWD NWWG

G_HW

4806h

G_HW

_HALT

EXT

CLK

CKAW

USEL

4807h

Clock

PRSC1 PRSC0

option

NEXT NCKAW

NPRSC

4808h

NOPT4

NPRSC1

0

CLK

HSECNT[7:0]

NHSECNT[7:0]

TMU[3:0]

USEL

4809h

OPT5

NOPT5

OPT6

00h

FFh

00h

FFh

HSE clock

startup

480Ah

480Bh

TMU

480Ch

NOPT6

NTMU[3:0]

WAIT

STATE

480Dh

OPT7

Reserved

Reserved

00h

FFh

Flash wait

states

NWAIT

STATE

480Eh

NOPT7

480Fh

4810h

4811h

4812h

4813h

Reserved

OPT8

OPT9

TMU_KEY 1 [7:0]

TMU_KEY 2 [7:0]

TMU_KEY 3 [7:0]

TMU_KEY 4 [7:0]

TMU_KEY 5 [7:0]

TMU_KEY 6 [7:0]

TMU_KEY 7 [7:0]

TMU_KEY 8 [7:0]

00h

00h

00h

00h

00h

00h

00h

00h

00h

OPT10

OPT11

OPT12

OPT13

OPT14

OPT15

OPT16

4814h

4815h

4816h

4817h

4818h

TMU

TMU MAX_ATT [7:0]

4819h

to

Reserved

487D

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Option bytes

STM8AF51xx, STM8AF61xx

Table 32. Option bytes (continued)

Option

Option

name

Option bits

Factory

default

setting

Addr.

byte

no.

7

6

5

4

3

2

1

0

487E

487F

OPT17

BL [7:0]

00h

Boot-

loader⁽¹⁾

NOPT

17

NBL [7:0]

00h

1. This option consists of two bytes that must have a complementary value in order to be valid. If the option is invalid, it has no

effect.

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Option bytes

Table 33. Option byte description

Option byte no.

Description

ROP[7:0]: Memory readout protection (ROP)

AAh: Enable readout protection (write access via SWIM protocol)

Note: Refer to the STM8A microcontroller family reference manual

(RM0009) section on Flash/EEPROM memory readout protection for

details.

OPT0

UBC[7:0]: User boot code area

00h: No UBC, no write-protection

01h: Page 0 to 1 defined as UBC, memory write-protected

02h: Page 0 to 3 defined as UBC, memory write-protected

03h to FFh: Pages 4 to 255 defined as UBC, memory write-protected

Note: Refer to the STM8A microcontroller family reference manual

(RM0009) section on Flash/EEPROM write protection for more details.

OPT1

AFR7: Alternate function remapping option 7

0: Port D4 alternate function = TIM2_CC1

1: Port D4 alternate function = BEEP

AFR6: Alternate function remapping option 6

0: Port B5 alternate function = AIN5, port B4 alternate function = AIN4

1: Port B5 alternate function = I²C_SDA, port B4 alternate function =

I²C_SCL.

AFR5: Alternate function remapping option 5

0: Port B3 alternate function = AIN3, port B2 alternate function = AIN2,

port B1 alternate function = AIN1, port B0 alternate function = AIN0.

1: Port B3 alternate function = TIM1_ETR, port B2 alternate function =

TIM1_NCC3, port B1 alternate function = TIM1_NCC2, port B0 alternate

function = TIM1_NCC1.

AFR4: Alternate function remapping option 4

0: Port D7 alternate function = TLI

1: Reserved

OPT2

AFR3: Alternate function remapping option 3

0: Port D0 alternate function = TIM3_CC2

1: Port D0 alternate function = TIM1_BKIN

AFR2: Alternate function remapping option 2

0: Port D0 alternate function = TIM3_CC2

1: Port D0 alternate function = CLK_CCO

Note: AFR2 option has priority over AFR3 if both are activated

AFR1: Alternate function remapping option 1

0: Port A3 alternate function = TIM2_CC3, port D2 alternate function

TIM3_CC1.

1: Port A3 alternate function = TIM3_CC1, port D2 alternate function

TIM2_CC3.

AFR0: Alternate function remapping option 0

0: Port D3 alternate function = TIM2_CC2

1: Port D3 alternate function = ADC_ETR

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Option bytes

Table 33. Option byte description (continued)

STM8AF51xx, STM8AF61xx

Option byte no.

Description

LSI_EN: Low speed internal clock enable

0: LSI clock is not available as CPU clock source

1: LSI clock is available as CPU clock source

IWDG_HW: Independent watchdog

0: IWDG Independent watchdog activated by software

1: IWDG Independent watchdog activated by hardware

OPT3

WWDG_HW: Window watchdog activation

0: WWDG window watchdog activated by software

1: WWDG window watchdog activated by hardware

WWDG_HALT: Window watchdog reset on halt

0: No reset generated on halt if WWDG active

1: Reset generated on halt if WWDG active

EXTCLK: External clock selection

0: External crystal connected to OSCIN/OSCOUT

1: External clock signal on OSCIN

CKAWUSEL: Auto-wakeup unit/clock

0: LSI clock source selected for AWU

1: HSE clock with prescaler selected as clock source for AWU

OPT4

PRSC[1:0]: AWU clock prescaler

00: 24 MHz to 128 kHz prescaler

01: 16 MHz to 128 kHz prescaler

10: 8 MHz to 128 kHz prescaler

11: 4 MHz to 128 kHz prescaler

HSECNT[7:0]: HSE crystal oscillator stabilization time

OPT5

OPT6

This configures the stabilization time to 0.5, 8, 128, and 2048 HSE

cycles with corresponding option byte values of E1h, D2h, B4h, and 00h.

TMU[3:0]: Enable temporary memory unprotection

0101: TMU disabled (permanent ROP).

Any other value: TMU enabled.

WAIT STATE: Wait state configuration

This option configures the number of wait states inserted when reading

from the Flash/data EEPROM memory.

0: No wait state

OPT7

1: One wait state

TMU_KEY 1 [7:0]: Temporary unprotection key 0

OPT8

OPT9

Temporary unprotection key: Must be different from 00h or FFh

TMU_KEY 2 [7:0]: Temporary unprotection key 1

Temporary unprotection key: Must be different from 00h or FFh

TMU_KEY 3 [7:0]: Temporary unprotection key 2

OPT10

OPT11

Temporary unprotection key: Must be different from 00h or FFh

TMU_KEY 4 [7:0]: Temporary unprotection key 3

Temporary unprotection key: Must be different from 00h or FFh

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Table 33. Option byte description (continued)

Option bytes

Option byte no.

Description

TMU_KEY 5 [7:0]: Temporary unprotection key 4

OPT12

Temporary unprotection key: Must be different from 00h or FFh

TMU_KEY 6 [7:0]: Temporary unprotection key 5

OPT13

OPT14

OPT15

Temporary unprotection key: Must be different from 00h or FFh

TMU_KEY 7 [7:0]: Temporary unprotection key 6

Temporary unprotection key: Must be different from 00h or FFh

TMU_KEY 8 [7:0]: Temporary unprotection key 7

Temporary unprotection key: Must be different from 00h or FFh

TMU_MAXATT [7:0]: TMU access failure counter

Every unsuccessful trial to enter the temporary unprotection procedure

increments the counter. More than eight unsuccessful trials trigger the

global erase of the code and data memory.

OPT16

OPT17

BL[7:0]: Bootloader enable

If this option byte is set to 55h (complementary value AAh) the

bootloader program is activated also in case of a programmed code

memory (for more details, see the bootloader user manual, UM0500).

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Electrical characteristics

STM8AF51xx, STM8AF61xx

10

Electrical characteristics

10.1

Parameter conditions

Unless otherwise specified, all voltages are referred to V

.

SS

10.1.1

Minimum and maximum values

Unless otherwise specified the minimum and maximum values are guaranteed in the worst

conditions of ambient temperature, supply voltage and frequencies by tests in production on

100% of the devices with an ambient temperature at T = -40 °C, T = 25 °C, and

A

A

T = T

(given by the selected temperature range).

A

Amax

Data based on characterization results, design simulation and/or technology characteristics

are indicated in the table footnotes and are not tested in production.

10.1.2

Typical values

Unless otherwise specified, typical data are based on T = 25 °C, V = 5.0 V. They are

A

DD

given only as design guidelines and are not tested.

Typical ADC accuracy values are determined by characterization of a batch of samples from

a standard diffusion lot over the full temperature range^.

10.1.3

10.1.4

Typical curves

Unless otherwise specified, all typical curves are given only as design guidelines and are

not tested.

Loading capacitor

The loading conditions used for pin parameter measurement are shown in Figure 10.

Figure 10. Pin loading conditions

STM8A pin

50 pF

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Electrical characteristics

10.1.5

Pin input voltage

The input voltage measurement on a pin of the device is described in Figure 11.

Figure 11. Pin input voltage

STM8A pin

V

IN

10.2

Absolute maximum ratings

Stresses above those listed as ‘absolute maximum ratings’ may cause permanent damage

to the device. This is a stress rating only and functional operation of the device under these

conditions is not implied. Exposure to maximum rating conditions for extended periods may

affect device reliability.

Table 34. Voltage characteristics

Symbol

Ratings

Min

Max

Unit

(1)

V

_DDx- V_DDSupply voltage (including V_{DDA and}V_DDIO

)

-0.3

V_SS- 0.3

V_SS- 0.3

—

6.5

6.5

V

Input voltage on true open drain pins (PE1, PE2)⁽²⁾

Input voltage on any other pin⁽²⁾

V_IN

V

V_DD+ 0.3

50

|V_DDx- V_DD| Variations between different power pins

mV

|V_SSx- V_SS| Variations between all the different ground pins

—

50

see Absolute maximum ratings

(electrical sensitivity) on

page 93

V_ESD

Electrostatic discharge voltage

1. All power (V_DD, V_DDIO, V_DDA) and ground (V_SS, V_SSIO, V_SSA) pins must always be connected to the

external power supply

2. I_INJ(PIN)must never be exceeded. This is implicitly insured if V_INmaximum is respected. If V_INmaximum

cannot be respected, the injection current must be limited externally to the I_INJ(PIN)value. A positive

injection is induced by V_IN> V_DDwhile a negative injection is induced by V_IN< V_SS. For true open-drain

pads, there is no positive injection current, and the corresponding V_INmaximum must always be respected

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Electrical characteristics

STM8AF51xx, STM8AF61xx

Table 35. Current characteristics

Symbol

Ratings

Max.

Unit

I_VDDIO

I_VSSIO

Total current into V_DDIOpower lines (source)^(1)(2)(3)

Total current out of V_{SS IO}ground lines (sink)^(1)(2)(3)

Output current sunk by any I/O and control pin

Output current source by any I/Os and control pin

Injected current on any pin

100

100

20

I_IO

mA

-20

10

(4)

I_INJ(PIN)

I_INJ(TOT)

Sum of injected currents

50

1. All power (V_DD, V_DDIO, V_DDA) and ground (V_SS, V_SSIO, V_SSA) pins must always be connected to the

external supply.

2. The total limit applies to the sum of operation and injected currents.

3. V_DDIOincludes the sum of the positive injection currents. V_SSIOincludes the sum of the negative injection

currents.

4. This condition is implicitly insured if VIN maximum is respected. If VIN maximum cannot be respected, the

injection current must be limited externally to the IINJ(PIN) value. A positive injection is induced by VIN >

VDD while a negative injection is induced by VIN < VSS. For true open-drain pads, there is no positive

injection current allowed and the corresponding VIN maximum must always be respected.

Table 36. Thermal characteristics

Symbol

Ratings

Value

Unit

T_STG

T_J

Storage temperature range

-65 to 150

160

°C

Maximum junction temperature

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STM8AF51xx, STM8AF61xx

Electrical characteristics

10.3

Operating conditions

Table 37. General operating conditions

Symbol

Parameter

Conditions

Min

Max

Unit

1 wait state

T_A= -40 °C to 145 °C

16

24⁽¹⁾

f_CPU

Internal CPU clock frequency

MHz

0 wait state

T_A= -40 °C to 145 °C

0

16

V_DD/V_DDIOStandard operating voltage

—

ESR ≤ 0.3 Ω at 1 MHz

Suffix A

3.0

5.5

3300

85

V

C_EXT

V_CAPexternal capacitor⁽²⁾

470

nF

Suffix B

105

125

145

90

T_A

Ambient temperature

Suffix C

Suffix D

-40

°C

A suffix version

B suffix version

C suffix version

D suffix version

110

130

150

T_J

Junction temperature range

1. For devices with less than 96 Kbyte of program memory, the 24 MHz are only achievable using the super

set silicon (salestype contains SSS)

2. Care should be taken when selecting the capacitor, due to its tolerance, as well as its dependency on

temperature, DC bias and frequency in addition to other factors. 470 nF 10 % is acceptable, taking into

account all tolerances.

Figure 12. f

versus V

DD

CPUmax

f_CPU[MHz]

24

16

Functionality guaranteed

Functionality

not guaranteed

in this area

(1)

@ T -40 to 145 °C at 1 waitstate

A

12

8

Functionality guaranteed

@ T -40 to 145 °C at 0 waitstate

A

4

0

3.0

4.0

5.0

5.5

Supply voltage [V]

1. For devices with less than 96 Kbyte of program memory, the 24 MHz are only achievable using the super

set silicon (salestype contains SSS)

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Electrical characteristics

STM8AF51xx, STM8AF61xx

Table 38. Operating conditions at power-up/power-down

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

V_DDrise time rate

V_DDfall time rate

—

—

2⁽¹⁾

2⁽¹⁾

—

—

—

3

t_VDD

µs/V

Reset release delay

Reset generation delay

V_DDrising

—

—

ms

µs

t_TEMP

V

_DDfalling

—

3

Power-on reset

threshold⁽²⁾

V_IT+

V_IT-

—

2.65

2.58

—

2.8

2.95

2.88

V

Brown-out reset

threshold

—

—

2.73

70⁽¹⁾

Brown-out reset

hysteresis

V_HYS(BOR)

mV

1. Guaranteed by design, not tested in production.

2. If V_DDis below 3 V, the code execution is guaranteed above the V_IT-and V_IT+thresholds. RAM content is

kept. The EEPROM programming sequence must not be initiated.

10.3.1

VCAP external capacitor

Stabilization for the main regulator is achieved connecting an external capacitor C

to the

EXT

V

pin. C

is specified in Table 37. Care should be taken to limit the series inductance

CAP

EXT

to less than 15 nH.

Figure 13. External capacitor C

EXT

ESR

C

ESL

Rleak

1. Legend: ESR is the equivalent series resistance and ESL is the equivalent inductance.

10.3.2

Supply current characteristics

The current consumption is measured as described in Figure 10 on page 64 and Figure 11

on page 65.

If not explicitly stated, general conditions of temperature and voltage apply.

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STM8AF51xx, STM8AF61xx

Electrical characteristics

Table 39. Total current consumption in run, wait and slow mode. General conditions for V

DD

apply. T = -40 °C to 145 °C

A

Symbol

Parameter

Conditions

f_CPU= 24 MHz 1 ws

Typ

Max

Unit

8.7

7.4

16.8⁽²⁾⁽³⁾

All peripherals

f_CPU= 16 MHz

f_CPU= 8 MHz

f_CPU= 4 MHz

f_CPU= 2 MHz

f_CPU= 24 MHz

f_CPU= 16 MHz

14

clocked, code

executed from

EEPROM, HSE

external clock

Supply current in

run mode

(1)

I_DD(RUN)

4.0

7.4⁽²⁾

4.1⁽²⁾

2.5

2.4

1.5

4.4

6.0⁽²⁾⁽³⁾

3.7

5.0

All peripherals

Supply current in clocked, code

(1)

I_DD(RUN)

f

_CPU= 8 MHz

2.2

3.0⁽²⁾

2.0⁽²⁾

1.5

run mode

executed from RAM,

HSE external clock

f_CPU= 4 MHz

f_CPU= 2 MHz

f_CPU= 24 MHz

f_CPU= 16 MHz

1.4

mA

1.0

2.4

3.1⁽²⁾⁽³⁾

1.65

1.15

0.90

0.80

2.5

CPU stopped, all

peripherals off, HSE

external clock

Supply current in

wait mode

(1)

I_DD(WFI)

f_CPU= 8 MHz

1.9⁽²⁾

1.6⁽²⁾

1.5

f_CPU= 4 MHz

f_CPU= 2 MHz

External clock 16 MHz

f_CPU= 125 kHz

f_CPUscaled down,

Supply current in all peripherals off,

1.50

1.50

1.95

(1)

I_DD(SLOW)

slow mode

code executed from

RAM

LSI internal RC

f_CPU= 128 kHz

1.80⁽²⁾

1. The current due to I/O utilization is not taken into account in these values.

2. Values not tested in production. Design guidelines only.

3. For devices with less than 96 Kbyte of program memory, the 24 MHz are only achievable using the super set silicon

(salestype contains SSS)

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Electrical characteristics

STM8AF51xx, STM8AF61xx

Table 40. Total current consumption in halt and active halt modes. General conditions for V

DD

apply. T = -40 °C to 55 °C unless otherwise stated

A

Symbol

Parameter

Conditions

Typ

Max

Unit

Clocks stopped,

Flash in power-down mode

5

35⁽¹⁾

I_DD(H)

Supply current in halt mode

Clocks stopped,

Flash in power-down mode,

T_A= 25 °C

5

25

External clock 16 MHz

f_MASTER= 125 kHz

µA

770

900⁽¹⁾

I_DD(FAH)Supply current in fast active halt mode

I_DD(SAH)Supply current in slow active halt mode

LSI clock 128 kHz

LSI clock 128 kHz

150

25

230⁽¹⁾

42⁽¹⁾

LSI clock 128 kHz,

T_A= 25 °C

25

10

50

30

Wakeup time from fast active halt

t_WU(FAH)

mode

30⁽¹⁾

80⁽¹⁾

T_A= -40 °C to 145 °C

µs

Wakeup time from slow active halt

t_WU(SAH)

mode

1. Data based on characterization results. Not tested in production.

Current consumption for on-chip peripherals

Table 41. Oscillator current consumption

Symbol

Parameter

Conditions

Typ

Max⁽¹⁾

Unit

Quartz or

ceramic

resonator,

CL = 33 pF

V_DD= 5 V

f

f

_OSC= 24 MHz

1

2.0⁽³⁾

—

HSE oscillator current

consumption⁽²⁾

_OSC= 16 MHz

f_OSC= 8 MHz

_OSC= 24 MHz

0.6

I_DD(OSC)

0.57

—

mA

Quartz or

ceramic

resonator,

CL = 33 pF

V_DD= 3.3 V

f

0.5

1.0⁽³⁾

—

HSE oscillator current

consumption⁽²⁾

f_OSC= 16 MHz

f_OSC= 8 MHz

0.25

I_DD(OSC)

0.18

—

1. During startup, the oscillator current consumption may reach 6 mA.

2. The supply current of the oscillator can be further optimized by selecting a high quality resonator with small R_mvalue. Refer

to crystal manufacturer for more details

3. Informative data.

Table 42. Programming current consumption

Symbol

Parameter

Conditions

Typ

Max

Unit

V_DD= 5 V, -40 °C to 145 °C, erasing

I_DD(PROG)Programming current

and programming data or program

memory

1.0

1.7

mA

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Electrical characteristics

(1)

Table 43. Typical peripheral current consumption V = 5.0 V

DD

Typ.

= 2 MHz f

Typ.

= 16 MHz f =24 MHz

master

Typ.

Symbol

Parameter

Unit

f

master

master

I_DD(TIM1)

I_DD(TIM2)

I_DD(TIM3)

I_DD(TIM4)

TIM1 supply current⁽²⁾

TIM2 supply current ⁽²⁾

TIM3 supply current⁽²⁾

TIM4 supply current⁽²⁾

0.03

0.02

0.01

0.004

0.03

0.03

0.01

0.02

0.06

0.003

0.22

0.23

0.12

0.1

0.34

0.19

0.16

0.05

0.15

0.18

0.07

0.91

0.40

0.05

2.4

0.03

0.09

0.11

0.04

0.06

0.30

0.02

1

I_DD(USART)USART supply current⁽²⁾

I_DD(LINUART)LINUART supply current⁽²⁾

mA

I_DD(SPI)

I_{DD(I C)}

I_DD(CAN)

I_DD(AWU)

SPI supply current⁽²⁾

I²C supply current⁽²⁾

CAN supply current⁽³⁾

AWU supply current⁽²⁾

2

I_{DD(TOT_DIG)}All digital peripherals on

ADC supply current when

I_DD(ADC)

0.93

0.95

0.96

converting⁽⁴⁾

1. Typical values not tested in production. Since the peripherals are powered by an internally regulated, constant digital

supply voltage, the values are similar in the full supply voltage range.

2. Data based on a differential I_DDmeasurement between no peripheral clocked and a single active peripheral. This

measurement does not include the pad toggling consumption.

3. Data based on a differential IDD measurement between reset configuration (CAN disabled) and a permanent CAN data

transmit sequence in loopback mode at 1 MHz. This measurement does not include the pad toggling consumption.

4. Data based on a differential I_DDmeasurement between reset configuration and continuous A/D conversions.

Current consumption curves

Figure 14 to Figure 19 show typical current consumption measured with code executing in RAM.

Figure 14. Typ. I

vs. V

Figure 15. Typ. I

vs. f

DD(RUN)HSE

DD

DD(RUN)HSE CPU

@f

= 16 MHz, peripherals = on

@ V = 5.0 V, peripherals = on

CPU

DD

10

10

25°C

85°C

12 5°C

25°C

85°C

12 5°C

9

8

9

8

7

7

6

6

5

5

4

3

4

3

2

1

2

1

0

0

2.5

3

3.5

4

4.5

5

5.5

6

0

5

10

15

20

25

30

V_DD[V]

fcpu [MHz]

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Electrical characteristics

STM8AF51xx, STM8AF61xx

Figure 16. Typ. I

vs. V

Figure 17. Typ. I

vs. V

DD(RUN)HSI

DD

DD(WFI)HSE DD

@ f

= 16 MHz, peripherals = off

@ f

= 16 MHz, peripherals = on

CPU

CPU

6

5

4

3

2

1

0

4

3

2

1

0

25°C

85°C

125°C

25°C

85°C

125°C

2.5

3.5

4.5

5.5

6.5

2.5

3.5

4.5

5.5

6.5

VDD [V]

VDD [V]

Figure 18. Typ. I

vs. f

Figure 19. Typ. I

vs. V

DD(WFI)HSE

CPU

DD(WFI)HSI DD

@ V = 5.0 V, peripherals = on

@ f

= 16 MHz, peripherals = off

DD

CPU

2.5

2

6

5

4

1.5

3

2

1

0

1

0.5

0

25°C

85°C

12 5°C

25°C

85°C

12 5°C

2.5

3

3.5

4

4.5

5

5.5

6

0

5

10

15

20

25

30

V_DD[V]

fcpu [MHz]

72/118

Doc ID 14395 Rev 6

STM8AF51xx, STM8AF61xx

Electrical characteristics

10.3.3

External clock sources and timing characteristics

HSE external clock

An HSE clock can be generated by feeding an external clock signal of up to 24 MHz to the

OSCIN pin.

Clock characteristics are subject to general operating conditions for V and T .

DD

A

Table 44. HSE external clock characteristics

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

User external clock source

frequency

f_{HSE_ext}

T_A= -40 °C to 145 °C

0⁽¹⁾

—

—

—

24⁽²⁾

—

MHz

V_HSEdHLComparator hysteresis

—

—

0.1 x V_DD

0.7 x V_DD

OSCIN high-level input pin

voltage

V_HSEH

V_DD

V

OSCIN low-level input pin

voltage

V_HSEL

—

V_SS

-1

—

—

0.3 x V_DD

+1

I_{LEAK_HSE}OSCIN input leakage current

V_SS< V_IN< V_DD

µA

1. If CSS is used, the external clock must have a frequency above 500 kHz.

2. For devices with less than 96 Kbyte of program memory, the 24 MHz are only achievable using the super set silicon

(salestype contains SSS)

Figure 20. HSE external clock source

V

V

HSEH

HSEL

f

HSE

External clock

source

OSCIN

STM8A

HSE crystal/ceramic resonator oscillator

The HSE clock can be supplied using a crystal/ceramic resonator oscillator of up to 24 MHz.

All the information given in this paragraph is based on characterization results with specified

typical external components. In the application, the resonator and the load capacitors have

to be placed as close as possible to the oscillator pins in order to minimize output distortion

and startup stabilization time. Refer to the crystal resonator manufacturer for more details

(frequency, package, accuracy...).

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Electrical characteristics

STM8AF51xx, STM8AF61xx

Table 45. HSE oscillator characteristics

Symbol

Parameter

Feedback resistor

Conditions

Min

Typ

Max

Unit

R_F

—

—

—

—

—

5

220

—

—

20

—

kΩ

pF

(1)

C_L1/C_L2

g_m

Recommended load capacitance

Oscillator trans conductance

—

mA/V

V

_DDis

(2)

t_SU(HSE)

Startup time

—

2.8

—

ms

stabilized

1. The oscillator needs two load capacitors, C_L1and C_L2, to act as load for the crystal. The total load capacitance (Cload) is

(C_L1* C_L2)/(C_L1+ C_L2). If C_L1= C_L2, Cload = C_L1/2. Some oscillators have built-in load capacitors, C_L1and C_L2

.

2. This value is the startup time, measured from the moment it is enabled (by software) until a stabilized 24 MHz oscillation is

reached. It can vary with the crystal type that is used.

Figure 21. HSE oscillator circuit diagram

f

to core

HSE

R

m

R

F

C

O

L

m

C

L1

OSCIN

C

m

g

m

Resonator

Current control

Resonator

STM8A

OSCOUT

C

L2

HSE oscillator critical g_mformula

The crystal characteristics have to be checked with the following formula:

Equation 1

g

_m» g_mcrit

where g

can be calculated with the crystal parameters as follows:

mcrit

Equation 2

g_mcrit= (2 × Π × ^fHSE)²× R_m(2Co + C)²

R : Notional resistance (see crystal specification)

m

L : Notional inductance (see crystal specification)

m

C : Notional capacitance (see crystal specification)

m

Co: Shunt capacitance (see crystal specification)

C

= C = C: Grounded external capacitance

L1

L2

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Doc ID 14395 Rev 6

STM8AF51xx, STM8AF61xx

Electrical characteristics

10.3.4

Internal clock sources and timing characteristics

Subject to general operating conditions for V and T .

DD

A

High-speed internal RC oscillator (HSI)

Table 46. HSI oscillator characteristics

Symbol

Parameter

Frequency

Conditions

Min

Typ

Max

Unit

f_HSI

—

—

16

—

MHz

Trimmed by the application

for any V_DDand T_A

conditions

HSI oscillator user

trimming accuracy

-1

—

1

ACC_HS

%

HSI oscillator accuracy

(factory calibrated)

V_DD= 3.0 V ≤ V_DD≤ 5.5 V,

-40 °C ≤ T_A≤ 145 °C

-5

—

—

5

t_su(HSI)HSI oscillator wakeup time

—

—

2⁽¹⁾

µs

1. Guaranteed by characterization, not tested in production

Figure 22. Typical HSI frequency vs V

DD

3%

2%

-40°C

25°C

85°C

125°C

1%

0%

-1%

-2%

-3%

2.5

3

3.5

4

4.5

5

5.5

6

V_DD[V]

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Electrical characteristics

STM8AF51xx, STM8AF61xx

Low-speed internal RC oscillator (LSI)

Subject to general operating conditions for V and T .

DD

A

Table 47. LSI oscillator characteristics

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

f_LSI

Frequency

—

—

112

—

128

—

144

7⁽¹⁾

kHz

µs

t_su(LSI)LSI oscillator wakeup time

1. Data based on characterization results, not tested in production.

Figure 23. Typical LSI frequency vs V

DD

3%

2%

1%

25°C

0%

-1%

-2%

-3%

2.5

3

3.5

4

4.5

5

5.5

6

V_DD[V]

76/118

Doc ID 14395 Rev 6

STM8AF51xx, STM8AF61xx

Electrical characteristics

10.3.5

Memory characteristics

Flash program memory/data EEPROM memory

General conditions: T = -40 °C to 145 °C.

A

Table 48. Flash program memory/data EEPROM memory

Symbol

Parameter

Conditions

Min⁽¹⁾Typ Max

Unit

f

_CPUis 16 to 24 MHz

with 1 ws⁽²⁾

Operating voltage

(all modes, execution/write/erase)

V_DD

3.0

—

5.5

f_CPUis 0 to 16 MHz

with 0 ws

V

f_CPUis 16 to 24 MHz

with 1 ws⁽²⁾

f_CPUis 0 to 16 MHz

with 0 ws

V_DD

Operating voltage (code execution)

2.6

—

—

6

5.5

6.6

Standard programming time

(including erase) for byte/word/block

(1 byte/4 bytes/128 bytes)

—

t_prog

ms

ms

Fast programming time for 1 block

(128 bytes)

—

—

—

—

3

3

3.3

3.3

t_eraseErase time for 1 block (128 bytes)

1. Guaranteed by characterization, not tested in production.

2. For devices with less than 96 Kbyte of program memory, the 24 MHz are only achievable using the super

set silicon (salestype contains SSS)

Table 49. Program memory

Symbol

Parameter

Condition

Min

Max

Unit

T_WE

Temperature for writing and erasing

—

-40

125

°C

Program memory endurance

(erase/write cycles)⁽¹⁾

N_WE

T_A= 25 °C

1000

—

cycles

years

T_A= 25 °C

T_A= 55 °C

40

20

—

—

t_RET

Data retention time

1. The physical granularity of the memory is four bytes, so cycling is performed on four bytes even when a

write/erase operation addresses a single byte.

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Electrical characteristics

STM8AF51xx, STM8AF61xx

Table 50. Data memory

Symbol

Parameter

Condition

Min

Max

Unit

125

145⁽¹⁾

—

T_WE

Temperature for writing and erasing

—

-40

°C

Data memory endurance⁽²⁾

(erase/write cycles)

T_A= 25 °C

T_A= -40°C to 125 °C

T_A= 25 °C

300 k

100 k⁽³⁾

40⁽³⁾⁽⁴⁾

20⁽³⁾⁽⁴⁾

N_WE

cycles

years

—

—

t_RET

Data retention time

T_A= 55 °C

—

1. Target value, to be confirmed.

2. The physical granularity of the memory is four bytes, so cycling is performed on four bytes even when a

write/erase operation addresses a single byte.

3. More information on the relationship between data retention time and number of write/erase cycles is

available in a separate technical document.

4. Retention time for 256B of data memory after up to 1000 cycles at 125 °C.

78/118

Doc ID 14395 Rev 6

STM8AF51xx, STM8AF61xx

Electrical characteristics

10.3.6

I/O port pin characteristics

General characteristics

Subject to general operating conditions for V and T unless otherwise specified. All

DD

A

unused pins must be kept at a fixed voltage, using the output mode of the I/O for example or

an external pull-up or pull-down resistor.

Table 51. I/O static characteristics

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

V_IL

Low-level input voltage

High-level input voltage

-0.3 V

0.3 x V_DD

V_IH

0.7 x V_DD

V_DD+ 0.3 V

—

0.1 x

V_DD

V_hys

Hysteresis⁽¹⁾

—

—

—

—

—

Standard I/0, V_DD= 5 V,

I = 3 mA

V

_DD- 0.5 V

—

—

V_OH

High-level output voltage

Standard I/0, V_DD= 3 V,

I = 1.5 mA

V

_DD- 0.4 V

High sink and true open

drain I/0, V_DD= 5 V

I = 8 mA

—

—

—

—

0.5

0.6

V_OL

Low-level output voltage

Pull-up resistor

Standard I/0, V_DD= 5 V

I = 3 mA

V

Standard I/0, V_DD= 3 V

I = 1.5 mA

—

35

—

—

50

—

0.4

65

R_pu

V_DD= 5 V, V_IN= V_SS

kΩ

Fast I/Os

Load = 50 pF

20⁽²⁾

Rise and fall time

(10% - 90%)

t_R, t_F

ns

Standard and high sink I/Os

Load = 50 pF

—

—

—

—

—

—

—

—

—

—

—

—

125⁽²⁾

1

Digital input pad leakage

current

I_lkg

V_SS≤ V_IN≤ V_DD

µA

nA

V_SS≤ V_IN≤ V_DD

-40 °C < T_A< 125 °C

250

500

1⁽²⁾

60

Analog input pad leakage

current

I_{lkg ana}

V_SS≤ V_IN≤ V_DD

-40 °C < T_A< 145 °C

Leakage current in

adjacent I/O⁽²⁾

I_lkg(inj)

I_DDIO

Injection current 4 mA

µA

Total current on either

V_DDIOor V_SSIO

Including injection currents

mA

1. Hysteresis voltage between Schmitt trigger switching levels. Based on characterization results, not tested in production.

2. Data based on characterization results, not tested in production.

Doc ID 14395 Rev 6

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Electrical characteristics

STM8AF51xx, STM8AF61xx

Figure 24. Typical V and V vs V @ four temperatures

IL

IH

DD

6

5

4

3

2

1

0

-40°C

25°C

85°C

125°C

2.5

3

3.5

4

4.5

5

5.5

6

V_DD[V]

Figure 25. Typical pull-up resistance R vs V @ four temperatures

PU

DD

60

55

50

45

40

35

30

-40°C

25°C

85°C

125°C

2.5

3

3.5

4

4.5

5

5.5

6

V_DD[V]

80/118

Doc ID 14395 Rev 6

STM8AF51xx, STM8AF61xx

Electrical characteristics

(1)

Figure 26. Typical pull-up current I vs V @ four temperatures

pu

DD

140

120

100

80

-40°C

25°C

85°C

125°C

60

40

20

0

0

1

2

3

4

5

6

V_DD[V]

1. The pull-up is a pure resistor (slope goes through 0).

Typical output level curves

Figure 27 to Figure 36 show typical output level curves measured with output on a single pin.

Figure 27. Typ. V @ V = 3.3 V (standard

Figure 28. Typ. V @ V = 5.0 V (standard

OL DD

OL

DD

ports)

ports)

-40°C

25°C

85°C

125°C

-40°C

25°C

85°C

125°C

1.5

1.25

1

1.5

1.25

1

0.75

0.5

0.25

0

0.75

0.5

0.25

0

0

1

2

3

4

5

6

7

0

2

4

6

8

10

12

I

_OL[mA]

I_OL[mA]

Figure 29. Typ. V @ V = 3.3 V (true open Figure 30. Typ. V @ V = 5.0 V (true open

OL

DD

OL

DD

drain ports)

drain ports)

-40°C

25°C

85°C

125°C

-40°C

25°C

85°C

125°C

2

1.75

1.5

1.25

1

2

1.75

1.5

1.25

1

0.75

0.5

0.25

0

0.75

0.5

0.25

0

0

2

4

6

8

10

12

14

0

5

10

15

20

25

I_OL[mA]

I_OL[mA]

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Electrical characteristics

STM8AF51xx, STM8AF61xx

Figure 31. Typ. V @ V = 3.3 V (high sink

Figure 32. Typ. V @ V = 5.0 V (high sink

OL DD

OL

DD

ports)

ports)

-40°C

25°C

85°C

125°C

-40°C

25°C

85°C

125°C

1.5

1.25

1

1.5

1.25

1

0.75

0.5

0.25

0

0.75

0.5

0.25

0

0

2

4

6

8

10

12

14

0

5

10

15

20

25

I_OL[mA]

I_OL[mA]

Figure 33. Typ. V

V

@ V = 3.3 V

Figure 34. Typ. V

V

@ V = 5.0 V

DD - OH

DD

DD - OH DD

(standard ports)

(standard ports)

-40°C

25°C

85°C

125°C

-40°C

25°C

85°C

125°C

2

1.75

1.5

1.25

1

2

1.75

1.5

1.25

1

0.75

0.5

0.25

0

0.75

0.5

0.25

0

0

1

2

3

4

5

6

7

0

2

4

6

8

10

12

I_OH[mA]

I_OH[mA]

Figure 35. Typ. V

V

@ V = 3.3 V (high Figure 36. Typ. V

V

@ V = 5.0 V (high

DD - OH

DD

DD - OH DD

sink ports)

sink ports)

-40°C

25°C

85°C

125°C

-40°C

25°C

85°C

125°C

2

1.75

1.5

1.25

1

2

1.75

1.5

1.25

1

0.75

0.5

0.25

0

0.75

0.5

0.25

0

0

2

4

6

8

10

12

14

0

5

10

15

20

25

I_OH[mA]

I_OH[mA]

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STM8AF51xx, STM8AF61xx

Electrical characteristics

10.3.7

Reset pin characteristics

Subject to general operating conditions for V and T unless otherwise specified.

DD

A

Table 52. NRST pin characteristics

Symbol Parameter

Conditions

Min

Typ

Max

Unit

V_IL(NRST)NRST low-level input voltage⁽¹⁾

V_IH(NRST)NRST high-level input voltage⁽¹⁾

—

—

V_SS

—

—

—

40

—

0.3 x V_DD

V_DD

—

0.7 x V_DD

V_OL(NRST)NRST low-level output voltage⁽¹⁾I_OL= 3 mA

0.6

V

R_PU(NRST)NRST pull-up resistor

—

—

30

85

60

kΩ

ns

V_F(NRST)NRST input filtered pulse⁽¹⁾

315

1. Data based on characterization results, not tested in production.

Figure 37. Typical NRST V and V vs V @ four temperatures

IL

IH

DD

-40°C

6

5

4

3

2

1

0

25°C

85°C

125°C

2.5

3

3.5

4

4.5

5

5.5

6

V

_DD[V]

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Electrical characteristics

Figure 38. Typical NRST pull-up resistance R vs V

STM8AF51xx, STM8AF61xx

PU

DD

-40°C

25°C

85°C

125°C

60

55

50

45

40

35

30

2.5

3

3.5

4

4.5

5

5.5

6

V_DD[V]

Figure 39. Typical NRST pull-up current I vs V

pu

DD

140

120

100

80

60

-40°C

25°C

85°C

125°C

40

20

0

0

1

2

3

4

5

6

V_DD[V]

The reset network shown in Figure 40 protects the device against parasitic resets.

Figure 40. Recommended reset pin protection

STM8A

V_DD

R_PU

External

reset

circuit

NRST

Internal reset

Filter

0.01

84/118

Doc ID 14395 Rev 6

STM8AF51xx, STM8AF61xx

Electrical characteristics

10.3.8

TIM 1, 2, 3, and 4 electrical specifications

Subject to general operating conditions for V , f

and T .

A

DD MASTER

Table 53. TIM 1, 2, 3, and 4 electrical specifications

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

f_EXT

Timer external clock frequency⁽¹⁾

—

—

—

24

MHz

1. Not tested in production. For devices with less than 96 Kbyte of program memory, the 24 MHz are only

achievable using the super set silicon (salestype contains SSS).

Doc ID 14395 Rev 6

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Electrical characteristics

STM8AF51xx, STM8AF61xx

SPI interface

10.3.9

Unless otherwise specified, the parameters given in Table 54 are derived from tests

performed under ambient temperature, f frequency, and V supply voltage

MASTER

DD

conditions. t

= 1/f

.

MASTER

MASTER

Refer to I/O port characteristics for more details on the input/output alternate function

characteristics (NSS, SCK, MOSI, MISO).

Table 54. SPI characteristics

Symbol

Parameter

Conditions

Min

Max

Unit

Master mode

Slave mode

0

0

0

10

f_SCK

1/t_c(SCK)

SPI clock frequency

V_DD< 4.5 V

V_DD= 4.5 V to 5.5 V

6⁽¹⁾

8⁽¹⁾

MHz

t_r(SCK)

t_f(SCK)

SPI clock rise and fall time Capacitive load: C = 30 pF

—

25⁽²⁾

(3)

t_su(NSS)

NSS setup time

NSS hold time

Slave mode

Slave mode

Master mode,

4 * t_MASTER

70

—

—

(3)

t_h(NSS)

(3)

t_w(SCKH)

t_w(SCKL)

SCK high and low time

Data input setup time

110

140

(3)

f_MASTER= 8 MHz, f_SCK= 4 MHz

(3)

Master mode

Slave mode

Master mode

Slave mode

Slave mode

Slave mode

5

—

t_su(MI)

t_su(SI)

(3)

5

—

(3)

7

—

—

t_h(MI)

t_h(SI)

ns

Data input hold time

(3)

10

—

25

—

—

—

31

12

(3)(4)

t_a(SO)

Data output access time

Data output disable time

3* t_MASTER

(3)(5)

t_dis(SO)

V_DD< 4.5 V

75

53

30

—

—

Slave mode

(after enable edge)

(3)

(3)

t_v(SO)

Data output valid time

Data output valid time

Data output hold time

V_DD= 4.5 V to 5.5 V

t_v(MO)

Master mode (after enable edge)

Slave mode (after enable edge)

Master mode (after enable edge)

(3)

t_h(SO)

(3)

t_h(MO)

1. f_MAXis f_MASTER/2.

2. The pad has to be configured accordingly (fast mode).

3. Values based on design simulation and/or characterization results, and not tested in production.

4. Min time is for the minimum time to drive the output and the max time is for the maximum time to validate the data.

5. Min time is for the minimum time to invalidate the output and the max time is for the maximum time to put the data in Hi-Z.

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Doc ID 14395 Rev 6

STM8AF51xx, STM8AF61xx

Electrical characteristics

Figure 41. SPI timing diagram in slave mode and with CPHA = 0

NSS input

t

t

t

SU(NSS)

c(SCK)

h(NSS)

CPHA=0

CPOL=0

t

t

w(SCKH)

w(SCKL)

CPHA=0

CPOL=1

t

t

t

t

t

dis(SO)

v(SO)

r(SCK)

f(SCK)

h(SO)

t

a(SO)

MISO

OUT PUT

MSB O UT

BI T6 OUT

BIT1 IN

LSB OUT

t

su(SI)

MOSI

M SB IN

LSB IN

INPUT

t

h(SI)

ai14134

1. Measurement points are at CMOS levels: 0.3 V_DDand 0.7 V_DD

.

Figure 42. SPI timing diagram in slave mode and with CPHA = 1

NSS input

t

t

t

SU(NSS)

t

c(SCK)

h(NSS)

CPHA=1

CPOL=0

w(SCKH)

CPHA=1

CPOL=1

t

w(SCKL)

t

t

r(SCK)

f(SCK)

t

t

t

v(SO)

h(SO)

dis(SO)

t

a(SO)

MISO

OUT PUT

MSB O UT

BI T6 OUT

LSB OUT

t

t

su(SI)

h(SI)

MOSI

M SB IN

BIT1 IN

LSB IN

INPUT

ai14135

1. Measurement points are at CMOS levels: 0.3 V_DDand 0.7 V_DD

.

Doc ID 14395 Rev 6

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Electrical characteristics

STM8AF51xx, STM8AF61xx

Figure 43. SPI timing diagram - master mode

High

NSS input

t

c(SCK)

CPHA=0

CPOL=0

CPHA=0

CPOL=1

CPHA=1

CPOL=0

CPHA=1

CPOL=1

t

t

t

t

w(SCKH)

w(SCKL)

r(SCK)

f(SCK)

t

su(MI)

MISO

INPUT

MSBIN

BIT6 IN

LSB IN

t

h(MI)

MOSI

M SB OUT

BIT1 OUT

LSB OUT

OUTUT

t

t

v(MO)

h(MO)

ai14136

1. Measurement points are at CMOS levels: 0.3 V_DDand 0.7 V_DD

.

88/118

Doc ID 14395 Rev 6

STM8AF51xx, STM8AF61xx

Electrical characteristics

2

10.3.10 I C interface characteristics

2

Table 55. I C characteristics

Standard mode I²C Fast mode I²C⁽¹⁾

Symbol

Parameter

Unit

Min⁽²⁾

Max⁽²⁾

Min⁽²⁾Max⁽²⁾

t_w(SCLL)SCL clock low time

t_w(SCLH)SCL clock high time

t_su(SDA)SDA setup time

4.7

4.0

—

—

—

—

1.3

0.6

—

—

µs

250

0⁽³⁾

100

0⁽⁴⁾

—

t_h(SDA)

SDA data hold time

900⁽³⁾

t_r(SDA)

t_r(SCL)

SDA and SCL rise time

(V_DD3 V to 5.5 V)

ns

—

—

1000

300

—

—

300

300

t_f(SDA)

t_f(SCL)

SDA and SCL fall time

(V_DD3 V to 5.5 V)

t_h(STA)

START condition hold time

4.0

4.7

4.0

—

—

—

0.6

0.6

0.6

—

—

—

µs

t_su(STA)Repeated START condition setup time

t_su(STO)STOP condition setup time

µs

µs

pF

STOP to START condition time

t_w(STO:STA)

(bus free)

4.7

—

1.3

—

—

C_b

Capacitive load for each bus line

—

400

400

1. f_MASTER, must be at least 8 MHz to achieve max fast I²C speed (400 kHz)

Data based on standard I²C protocol requirement, not tested in production

2.

The maximum hold time of the start condition has only to be met if the interface does not stretch the low

time

3.

4.

The device must internally provide a hold time of at least 300 ns for the SDA signal in order to bridge the

undefined region of the falling edge of SCL

Doc ID 14395 Rev 6

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Electrical characteristics

STM8AF51xx, STM8AF61xx

10.3.11 10-bit ADC characteristics

Subject to general operating conditions for V

specified.

, f

and T unless otherwise

DDA MASTER

A

Table 56. ADC characteristics

Symbol

Parameter

Conditions

Min

111 kHz

3

Typ

—

Max

Unit

f_ADC

ADC clock frequency

—

—

—

—

4 MHz kHz/MHz

V_DDAAnalog supply

—

5.5

V_REF+Positive reference voltage

V_REF-Negative reference voltage

2.75

—

V_DDA

V_SSA

V_SSA

—

—

0.5

V

—

V_DDA

Conversion voltage range⁽¹⁾

Devices with

external V_REF+

V_AIN

/

V_REF-

—

V_REF+

V_REF-pins

C_sampInternal sample and hold capacitor

—

—

—

—

—

—

1.5

0.75

7

3

pF

µs

f_ADC= 2 MHz

—

—

—

Sampling time

(3 x 1/f_ADC

(1)

t_S

)

f

f

_ADC= 4 MHz

_ADC= 2 MHz

t_STABWakeup time from standby

f_ADC= 4 MHz

f_ADC= 2 MHz

3.5

7

Total conversion time including

t_CONVsampling time

—

—

—

—

—

30

f_ADC= 4 MHz

—

3.5

—

(14 x 1/f_ADC

)

R_switchEquivalent switch resistance

kΩ

1. During the sample time, the sampling capacitance, C_samp(3 pF typ), can be charged/discharged by the

external source. The internal resistance of the analog source must allow the capacitance to reach its final

voltage level within t_S.After the end of the sample time t_S, changes of the analog input voltage have no

effect on the conversion result.

Figure 44. Typical application with ADC

V_DD

STM8A

V_T

Rswitch

0.6V

R_AIN

AINx

10-bit A/D

conversion

V_AIN

T_s

C_AIN

V_T

0.6V

I_L

C_samp

1. Legend: R_AIN= external resistance, C_AIN= capacitors, C_samp= internal sample and hold capacitor.

90/118

Doc ID 14395 Rev 6

STM8AF51xx, STM8AF61xx

Electrical characteristics

Table 57. ADC accuracy for V

= 5 V

DDA

Symbol

Parameter

Conditions

Typ

Max⁽¹⁾

Unit

|E_T|

|E_O|

|E_G|

|E_D|

|E_L|

|E_T|

|E_O|

|E_G|

|E_D|

|E_L|

Total unadjusted error⁽²⁾

Offset error⁽²⁾

1.4

0.8

3⁽³⁾

3

Gain error⁽²⁾

f_ADC= 2 MHz

0.1

2

Differential linearity error⁽²⁾

Integral linearity error⁽²⁾

Total unadjusted error⁽²⁾

Offset error⁽²⁾

0.9

1

0.7

1.5

4⁽⁴⁾

4⁽⁴⁾

3⁽⁴⁾

2⁽⁴⁾

1.5⁽⁴⁾

LSB

1.9⁽⁴⁾

1.3⁽⁴⁾

0.6⁽⁴⁾

1.5⁽⁴⁾

1.2⁽⁴⁾

Gain error⁽²⁾

f_ADC= 4 MHz

Differential linearity error⁽²⁾

Integral linearity error⁽²⁾

1. Max value is based on characterization, not tested in production.

2. ADC accuracy vs. injection current: Any positive or negative injection current within the limits specified for

I_INJ(PIN)and ΣI_INJ(PIN)in Section 10.3.6 does not affect the ADC accuracy.

3. TUE 2LSB can be reached on specific salestypes in the whole temperature range.

4. Target values.

Figure 45. ADC accuracy characteristics

E_G

1023

V

– V

1022

1021

DDA

SSA

1LSB

= ----------------------------------------

IDEAL

1024

(2)

E_T

(3)

7

6

5

4

3

2

1

(1)

E_O

E_L

E_D

1 LSB_IDEAL

0

1

2

3

4

5

6

7

1021102210231024

V_SSA

V

DDA

1. Example of an actual transfer curve

2. The ideal transfer curve

3. End point correlation line

E_T= Total unadjusted error: Maximum deviation between the actual and the ideal transfer curves.

E

E

E

_O= Offset error: Deviation between the first actual transition and the first ideal one.

_G= Gain error: Deviation between the last ideal transition and the last actual one.

_D= Differential linearity error: Maximum deviation between actual steps and the ideal one.

E_L= Integral linearity error: Maximum deviation between any actual transition and the end point correlation

line.

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Electrical characteristics

STM8AF51xx, STM8AF61xx

10.3.12 EMC characteristics

Susceptibility tests are performed on a sample basis during product characterization.

Functional EMS (electromagnetic susceptibility)

While executing a simple application (toggling 2 LEDs through I/O ports), the product is

stressed by two electromagnetic events until a failure occurs (indicated by the LEDs).

●

ESD: Electrostatic discharge (positive and negative) is applied on all pins of the device

until a functional disturbance occurs. This test conforms with the IEC 1000-4-2

standard.

●

FTB: A burst of fast transient voltage (positive and negative) is applied to V and V

DD

SS

through a 100 pF capacitor, until a functional disturbance occurs. This test conforms

with the IEC 1000-4-4 standard.

A device reset allows normal operations to be resumed. The test results are given in the

table below based on the EMS levels and classes defined in application note AN1709.

Designing hardened software to avoid noise problems

EMC characterization and optimization are performed at component level with a typical

application environment and simplified MCU software. It should be noted that good EMC

performance is highly dependent on the user application and the software in particular.

Therefore it is recommended that the user applies EMC software optimization and

prequalification tests in relation with the EMC level requested for his application.

Software recommendations

The software flowchart must include the management of runaway conditions such as:

●

●

●

Corrupted program counter

Unexpected reset

Critical data corruption (control registers...)

Prequalification trials

Most of the common failures (unexpected reset and program counter corruption) can be

recovered by applying a low state on the NRST pin or the oscillator pins for 1 second.

To complete these trials, ESD stress can be applied directly on the device, over the range of

specification values. When unexpected behavior is detected, the software can be hardened

to prevent unrecoverable errors occurring (see application note AN1015).

Table 58. EMS data

Symbol

Parameter

Conditions

Level/class

V_DD= 3.3 V, T_A= 25 °C,

f_MASTER= 16 MHz (HSI clock),

Conforms to IEC 1000-4-2

Voltage limits to be applied on any I/O pin

to induce a functional disturbance

V_FESD

3B

Fast transient voltage burst limits to be

V_EFTBapplied through 100 pF on V_DDand V_SS

pins to induce a functional disturbance

V_DD= 3.3 V, T_A= 25 °C,

f_MASTER= 16 MHz (HSI clock),

Conforms to IEC 1000-4-4

4A

92/118

Doc ID 14395 Rev 6

STM8AF51xx, STM8AF61xx

Electrical characteristics

Electromagnetic interference (EMI)

Emission tests conform to the SAE J 1752/3 standard for test software, board layout and pin

loading.

Table 59. EMI data

Conditions

(1)

Max f_CPU

Symbol

Parameter

Unit

General

Monitored

8

16

24

conditions

frequency band

MHz MHz MHz

0.1 MHz to 30 MHz

30 MHz to 130 MHz

130 MHz to 1 GHz

—

15

18

-1

2

17

22

3

22

16

5

V_DD= 5 V,

T_A= 25 °C,

LQFP80 package

conforming to SAE

J 1752/3

Peak level

S_EMI

dBµV

SAE EMI level

2.5

2.5

1. Data based on characterization results, not tested in production.

Absolute maximum ratings (electrical sensitivity)

Based on two different tests (ESD and LU) using specific measurement methods, the

product is stressed to determine its performance in terms of electrical sensitivity. For more

details, refer to the application note AN1181.

Electrostatic discharge (ESD)

Electrostatic discharges (3 positive then 3 negative pulses separated by 1 second) are

applied to the pins of each sample according to each pin combination. The sample size

depends on the number of supply pins in the device (3 parts*(n+1) supply pin). This test

conforms to the JESD22-A114A/A115A standard. For more details, refer to the application

note AN1181.

Table 60. ESD absolute maximum ratings

Maximum

Symbol

Ratings

Conditions

Class

Unit

value⁽¹⁾

Electrostatic discharge voltage

(human body model)

T_A= 25 °C, conforming to

V_ESD(HBM)

3A

3

4000

JESD22-A114

V

Electrostatic discharge voltage

(charge device model)

T_A= 25 °C, conforming to

V_ESD(CDM)

500

JESD22-C101

1. Data based on characterization results, not tested in production

Doc ID 14395 Rev 6

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Electrical characteristics

Static latch-up

STM8AF51xx, STM8AF61xx

Two complementary static tests are required on 10 parts to assess the latch-up

performance.

●

A supply overvoltage (applied to each power supply pin) and

A current injection (applied to each input, output and configurable I/O pin) are

performed on each sample.

●

This test conforms to the EIA/JESD 78 IC latch-up standard. For more details, refer to the

application note AN1181.

Table 61. Electrical sensitivities

Symbol

Parameter

Conditions

Class⁽¹⁾

T_A= 25 °C

T_A= 85 °C

T_A= 125 °C

T_A= 145 °C

LU

Static latch-up class

A

1. Class description: A Class is an STMicroelectronics internal specification. All its limits are higher than the

JEDEC specifications, that means when a device belongs to class A it exceeds the JEDEC standard. B

class strictly covers all the JEDEC criteria (international standard).

94/118

Doc ID 14395 Rev 6

STM8AF51xx, STM8AF61xx

Electrical characteristics

10.4

Thermal characteristics

In case the maximum chip junction temperature (T

) specified in Table 37: General

Jmax

operating conditions on page 67 is exceeded, the functionality of the device cannot be

guaranteed.

T

, in degrees Celsius, may be calculated using the following equation:

Jmax

Equation 3

T

= T

+ (P

x Θ )

Jmax

Amax

Dmax JA

where:

T

is the maximum ambient temperature in °C

Amax

Θ

is the package junction-to-ambient thermal resistance in ° C/W

JA

P

is the sum of P

and P

(P

= P

+ P

)

I/Omax

Dmax

INTmax

I/Omax

Dmax

INTmax

P

is the product of I and V , expressed in Watts. This is the maximum chip

INTmax

DD

DD

internal power.

P

represents the maximum power dissipation on output pins

I/Omax

where:

Equation 4

P

= Σ (V * I ) + Σ((V - V ) * I

)

OH

I/Omax

OL

OL

DD

OH

taking into account the actual V / I and V / I of the I/Os at low- and high-level in the

OL OL

OH OH

application.

(1)

Table 62. Thermal characteristics

Symbol

Parameter

Value

Unit

Thermal resistance junction-ambient

LQFP 80 - 14 x 14 mm

Θ_JA

38

°C/W

Thermal resistance junction-ambient

LQFP 64 - 10 x 10 mm

Θ_JA

Θ_JA

Θ_JA

46

57

59

°C/W

°C/W

°C/W

Thermal resistance junction-ambient

LQFP 48 - 7 x 7 mm

Thermal resistance junction-ambient

LQFP 32 - 7 x 7 mm

1. Thermal resistances are based on JEDEC JESD51-2 with 4-layer PCB in a natural convection

environment.

10.4.1

Reference document

JESD51-2 integrated circuits thermal test method environment conditions - natural

convection (still air). Available from www.jedec.org.

Doc ID 14395 Rev 6

95/118

Electrical characteristics

STM8AF51xx, STM8AF61xx

10.4.2

Selecting the product temperature range

When ordering the microcontroller, the temperature range is specified in the order code (see

Figure 50: Ordering information scheme(1) on page 102).

The following example shows how to calculate the temperature range needed for a given

application.

Assuming the following application conditions:

–

–

–

–

–

Maximum ambient temperature T

= 82 °C (measured according to JESD51-2)

Amax

I

= 8 mA

DDmax

V

= 5 V

DD

maximum 20 I/Os used at the same time in output at low-level with I = 8 mA

OL

V

= 0.4 V

OL

Equation 5

P

= 8 mA x 5 V = 400 mW

INTmax

Equation 6

P

= 20 x 8 mA x 0.4 V = 64 mW

64 mW:

IOmax

This gives:

P

= 400 mW and P

INTmax

IOmax

Equation 7

P

= 400 mW + 64 mW

Dmax

Thus:

P

= 464 mW.

Dmax

Using the values obtained in Table 62: Thermal characteristics on page 95 T

is

Jmax

calculated as follows:

For LQFP64 46 °C/W

Equation 8

T

= 82 °C + (46 °C/W x 464 mW) = 82 °C + 21 °C = 103 ° C

jmax

This is within the range of the suffix B version parts (-40 °C < T < 105 ° C).

j

Parts must be ordered at least with the temperature range suffix B.

96/118

Doc ID 14395 Rev 6

STM8AF51xx, STM8AF61xx

Package characteristics

11

Package characteristics

11.1

ECOPACK^®

In order to meet environmental requirements, ST offers these devices in different grades of

®

®

ECOPACK packages, depending on their level of environmental compliance. ECOPACK

specifications, grade definitions and product status are available at: www.st.com.

®

ECOPACK is an ST trademark.

Doc ID 14395 Rev 6

97/118

Package characteristics

STM8AF51xx, STM8AF61xx

11.2

Package mechanical data

Figure 46. 80-pin low profile quad flat package (14 x 14)

D

ccc

C

D1

D3

A

A2

41

60

40

61

b

L1

E3 E1

E

L

A1

K

80

Pin 1

identification

1

c

1S_ME

Table 63. 80-pin low profile quad flat package mechanical data

mm

Typ

inches⁽¹⁾

Dim.

Min

Max

Min

Typ

Max

A

A1

A2

b

—

0.05

1.35

0.22

0.09

15.80

13.80

—

—

—

1.60

0.15

1.45

0.38

0.20

16.20

14.20

—

—

0.0020

0.0531

0.0087

0.0035

0.6220

0.5433

—

—

0.0630

0.0060

0.0571

0.0150

0.0079

0.6378

0.5591

—

—

1.40

0.32

—

0.0551

0.0126

—

c

D

16.00

14.00

12.35

16.00

14.00

12.35

0.65

0.60

1.00

—

0.6299

0.5512

0.4862

0.6299

0.5512

0.4862

0.0256

0.0236

0.0394

—

D1

D3

E

15.80

13.80

—

16.20

14.20

—

0.6220

0.5433

—

0.6378

0.5591

—

E1

E3

e

—

—

—

—

L

0.45

—

0.75

—

0.0177

—

0.0295

—

L1

ccc

k

—

0.10

7°

—

0.0039

7°

0°

3.5°

0°

3.5°

1. Values in inches are converted from mm and rounded to 4 decimal digits

98/118

Doc ID 14395 Rev 6

STM8AF51xx, STM8AF61xx

Figure 47. 64-pin low profile quad flat package (10 x 10)

Package characteristics

A

A2

A1

D

D1

Seating plane

(0.1 x 0.004 mm)

b

e

E1 E

c

M x 45¬

Pin 1 identification

L1

L

θ

Table 64. 64-pin low profile quad flat package mechanical data

mm

Typ

inches⁽¹⁾

Dim.

Min

Max

Min

Typ

Max

A

A1

A2

b

—

0.05

1.35

0.17

0.09

—

—

—

1.60

0.15

1.45

0.27

0.20

—

—

0.0020

0.0531

0.0067

0.0035

—

—

0.0630

0.0059

0.0571

0.0106

0.0079

—

—

1.40

0.22

—

0.0551

0.0087

—

c

D

12.00

10.00

12.00

10.00

0.50

3.5°

0.60

1.00

0.4724

0.3937

0.4724

0.3937

0.0197

3.5°

D1

E

—

—

—

—

—

—

—

—

E1

e

—

—

—

—

—

—

—

—

θ

0°

7°

0°

7°

L

0.45

—

0.75

—

0.0177

—

0.0236

0.0394

0.0295

—

L1

1. Values in inches are converted from mm and rounded to 4 decimal digits

Doc ID 14395 Rev 6

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Package characteristics

Figure 48. 48-pin low profile quad flat package (7 x 7)

STM8AF51xx, STM8AF61xx

A

D

A2

D1

A1

b

e

E1

E

c

L1

L

θ

Table 65. 48-pin low profile quad flat package mechanical data

mm

Typ

inches⁽¹⁾

Dim.

Min

Max

Min

Typ

Max

A

A1

A2

b

—

0.05

1.35

0.17

0.09

—

—

—

1.60

0.15

1.45

0.27

0.20

—

—

0.0020

0.0531

0.0067

0.0035

—

—

0.0630

0.0059

0.0571

0.0106

0.0079

—

—

1.40

0.22

—

0.0551

0.0087

—

c

D

9.00

7.00

9.00

7.00

0.50

3.5°

0.60

1.00

0.3543

0.2756

0.3543

0.2756

0.0197

3.5°

D1

E

—

—

—

—

—

—

—

—

E1

e

—

—

—

—

—

—

—

—

θ

0°

7°

0°

7°

L

0.45

—

0.75

—

0.0177

—

0.0236

0.0394

0.0295

—

L1

1. Values in inches are converted from mm and rounded to 4 decimal digits

100/118

Doc ID 14395 Rev 6

STM8AF51xx, STM8AF61xx

Figure 49. 32-pin low profile quad flat package (7 x 7)

Package characteristics

D

A

A2

D1

A1

e

b

E1

E

c

L1

L

θ

Table 66. 32-pin low profile quad flat package mechanical data

mm

Typ

inches⁽¹⁾

Dim.

Min

Max

Min

Typ

Max

A

A1

A2

b

—

0.05

1.35

0.30

0.09

—

—

—

1.60

0.15

1.45

0.45

0.20

—

—

0.0020

0.0531

0.0118

0.0035

—

—

0.0630

0.0059

0.0571

0.0177

0.0079

—

—

1.40

0.37

—

0.0551

0.0146

—

c

D

9.00

7.00

9.00

7.00

0.80

3.5°

0.60

1.00

0.3543

0.2756

0.3543

0.2756

0.0315

3.5°

D1

E

—

—

—

—

—

—

—

—

E1

e

—

—

—

—

—

—

—

—

θ

0°

7°

0°

7°

L

0.45

—

0.75

—

0.0177

—

0.0236

0.0394

0.0295

—

L1

1. Values in inches are converted from mm and rounded to 4 decimal digits

Doc ID 14395 Rev 6

101/118

Ordering information

STM8AF51xx, STM8AF61xx

12

Ordering information

(1)

Figure 50. Ordering information scheme

XXX⁽¹⁾

Y

Example:

STM8A

F

61

A

A

T

D

Product class

8-bit automotive microcontroller

Program memory type

F = Flash + EEPROM

P = FASTROM

H = Flash no EEPROM

Device family

51 = CAN/LIN

61 = LIN only

Program memory size

6 = 32 Kbytes

7 = 48 Kbytes

8 = 64 Kbytes

9 = 96 Kbytes

A= 128 Kbytes

Pin count

6 = 32 pins

8 = 48 pins

9= 64 pins

A = 80 pins

Package type

T = LQFP

Temperature range

A = -40 to 85 °C

B = -40 to 105 °C

C = -40 to 125 °C

D= -40 to 145 °C

Packing

Y = Tray

U = Tube

X = Tape and reel compliant with EIA 481-C

1. Customer specific FASTROM code or custom device configuration. This field shows ‘SSS’ if the device

contains a super set silicon, usually equipped with bigger memory and more I/Os. This silicon is supposed

to be replaced later by the target silicon.

2. For a list of available options (e.g. memory size, package) and orderable part numbers or for further

information on any aspect of this device, please go to www.st.com or contact the ST Sales Office nearest

to you.

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Known limitations

13

Known limitations

13.1

STM8A core

13.1.1

Wait for event instruction (WFE) not available

Description

The WFE instruction is not implemented in the devices covered by this datasheet. This

instruction is used to synchronize the device with external computing resources. For further

details on this instruction, refer to the STM8 CPU programming manual (PM0044) on

www.st.com.

Workaround

None.

13.1.2

JRIL and JRIH instructions not available

Description

JRIL (jump if port INT pin = 0) and JRIH (jump if port INT pin = 1) are not supported by the

devices covered by this datasheet. These instructions perform conditional jumps: JRIL and

JRIH jump if one of the external interrupt lines is low and high, respectively.

In the devices covered by this datasheet, JRIL is equivalent to an unconditional jump and

JRIH is equivalent to NOP. For further details on these instructions, refer to the STM8 CPU

programming manual (PM0044) on www.st.com.

Workaround

None.

13.1.3

CPU not returning to Halt mode when the AL bit is set

Description

When the AL bit of the CFG_GCR register is set, the CPU does not return to Halt mode after

exiting an interrupt service routine (ISR). It returns to the main program and executes the

next instruction after the HALT instruction.

Workaround

None.

13.1.4

Main program not resuming after ISR has reset the AL bit

Description

If the CPU is in wait for interrupt state and the AL bit is set, the CPU returns to wait for

interrupt state after executing an ISR. To continue executing the main program, the AL bit

must be reset by the ISR. When AL is reset just before exiting the ISR, the CPU may remain

stalled.

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Workaround

Reset the AL bit at least two instructions before the IRET instruction.

13.2

I²C interface

13.2.1

Misplaced NACK bit when receiving 2 bytes in master mode

Description

When receiving two bytes in master mode, the usual sequence is the following:

1. Set POS and ACK bits of the I2C_CR2 register to 1.

2. Wait for ADDR event (address sent bit in I2C_SR1 register). When ADDR is set to 1,

program ACK to 0 and clear ADDR.

3. Wait for BTF event (byte transfer finished bit in I2C_SR1 register). When BTF is set to

1, program the STOP bit to 1 in the I2C_CR2 register, and read the 2 received bytes.

The NACK bit may be sent erroneously after the first byte.

Workaround

Use a different software sequence to clear ADDR and ACK bits:

1. Wait till ADDR flag is set.

2. Mask interrupts.

3. Clear ADDR bit.

4. Clear ACK bit.

5. Re-enable interrupts.

As the TLI interrupt is not maskable, this software workaround can not be implemented in

applications using the TLI interrupt.

13.2.2

Data register corrupted

Description

The content of the shift register may be shifted to the left by 1 bit and the second read

operation will return an incorrect value when the following conditions are met:

●

BTF bit (last data received) set to 1

●

Software sequence (SET STOP, READ N-1, READ N) delayed (for instance by an

interrupt)

●

N-1 byte not read before the next SCL rising edge.

Workaround

Mask all active interrupts between the SET STOP and the READ N-1 instructions. As TLI is

not maskable, this software workaround can not be implemented in applications using the

TLI interrupt.

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Known limitations

13.2.3

Delay in STOP bit programming leading to reception of supplementary

byte

Description

When receiving one byte in master mode, the STOP bit in the I2C_CR2 register is

programmed just after ADDR bit is cleared in order to generate a STOP condition after the

reception of the byte. If the programming of the STOP bit is delayed after the end of the first

byte reception, the master may receive another byte before the STOP condition is generated

and a wrong data will be received.

Workaround

Mask interrupts while clearing the ADDR bit and programming the STOP bit. As TLI is not

maskable, this software workaround can not be implemented in applications using the TLI

interrupt.

13.2.4

START condition badly generated after misplaced STOP

Description

When the START bit is set in the I2C_CR2 register and a misplaced STOP occurs on the

bus thus leading to a bus error, the START condition on the bus may be badly generated by

2

the I C peripheral (glitch on SDA resulting in SDA and SCL tied low simultaneously).

Workaround

When a bus error is detected (through a flag and/or interrupt), check if a START condition

was requested through the I2C_CR2 register. If so, a STOP condition should be generated

followed by a new START condition. This does not avoid the badly generated START

condition, but allows to resynchronize the network on the new START condition.

13.3

USART Interface

Parity error flag (PE) not correctly set when overrun condition occurs

Description

If an overrun condition occurs, the parity error flag (PE) of the UART_SR register is not set

for the frame which caused the overrun condition. The PE flag represents the status of the

last correctly received frame.

Workaround

None.

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13.4

LINUART interface

13.4.1

Framing error with data byte 0x00

Description

If the LINUART interface is configured in LIN slave mode, and the active mode with break

detection length is set to 11 (LBDL bit of UART_CR4 register set to 1), FE and RXNE flags

are not set when receiving a 0x00 data byte with a framing error, followed by a recessive

state. This occurs only if the dominant state length is between 9.56 and 10.56 times the

baud rate.

Workaround

The LIN software driver can handle this exceptional case by implementing frame timeouts to

comply with the LIN standard. This method has been implemented in ST LIN 2.1 driver

package which passed the LIN compliance tests.

13.4.2

13.4.3

13.4.4

Framing error when receiving an identifier (ID)

Description

If an ID framing error occurs when the LINUART is in active mode, both LHE and LHDF

flags are set at the end of the LIN header with ID framing error.

Workaround

The LIN software driver can handle this case by checking both LHE and LHDF flags upon

header reception.

Parity error when receiving an identifier (ID)

Description

If an ID parity error occurs, the LINUART wakes up from mute mode and both LHE and

LHDF are set at the end of the LIN header with parity error. The PE flag is also set.

Workaround

The LIN software driver can handle this case by checking all the flags upon header

reception.

OR flag not correctly set in LIN master mode

Description

When the LINUART operates in master mode, the OR flag is not set if an overrun condition

occurs.

Workaround

The LIN software driver can detect this case through a LIN protocol error.

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Known limitations

13.4.5

LIN header error when automatic resynchronization is enabled

Description

If the LINUART is configured in LIN slave mode (LSLV bit set in LINUART_CR6 register) and

the automatic resynchronization is enabled (LASE bit set in LINUART_CR6), the LHE flag

may be set instead of LHDF flag when receiving a valid header.

Workaround

None.

13.5

Clock controller

13.5.1

HSI RC oscillator cannot be switched off in run mode

Description

The internal 16 MHz RC oscillator cannot be switched off in run mode, even if the HSIEN bit

is programmed to 0.

Workaround

None.

13.6

SPI Interface

13.6.1

Last bit too short if SPI is disabled during communication

Description

When the SPI interface operates in master mode and the baud rate generator prescaler is

equal to 2, the SPI is disabled during ongoing communications, and the data and clock

output signals are switched off at the last strobing edge of the SPI clock.

As a consequence the length of the last bit is out of range and its reception on the bus is not

ensured.

Workaround

Check if a communication is ongoing before disabling the SPI interface. This can be done by

monitoring the BSY bit in the SPI_SR register.

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13.7

beCAN interface

13.7.1

beCAN transmission error when sleep mode is entered during

transmission

Description

If sleep mode entry is requested while a transmission is ongoing or a transmission request

is pending, the beCAN T pin will have a spurious behavior incompliant with the CAN

x

protocol.

No error frame will be sent and the device will enter sleep mode.

Workaround

Ensure that no transmission is ongoing and that no transmission request is pending before

putting the beCAN in sleep mode. This can be done by checking the beCAN control and

status registers before entering sleep mode. Refer to section 24.4.3 Sleep mode (low

power) of the RM0009 reference manual.

13.7.2

beCAN woken up from sleep mode with automatic wakeup

interrupt

Description

Waking up the beCAN from sleep mode using the automatic wakeup interrupt triggers an

interrupt on each CAN Rx falling edge until the bus is idle.

Workaround

To have a wakeup interrupt triggered only on the first falling edge of the CAN Rx pin, perform

the following actions:

1. Disable the automatic wakeup interrupt.

2. Clear the WKUI flag.

3. Disable the sleep mode in the ISR.

13.7.3

beCAN time triggered communication mode not supported

Description

The time triggered communication mode described in section 24.4.4 of the STM8A

reference manual (RM0009) is not supported.

TTCM bit must be kept at 0 in the CAN_MCR register (time triggered communication mode

disabled), and TGT bit in CAN_MDLCR must be initialized to 0 (CAN_MTSRH and

CAN_MTSRL registers not sent).

Workaround

None.

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Known limitations

13.7.4

be CAN read error in slow mode

Description

The read byte may be corrupted when the CPU is in slow mode and a FIFO read operation

is performed while a message transmission is ongoing. This happens because the

transmission mailboxes and the receive FIFOs share the same address/data lines for read

and write operations.

Workaround

To prevent this problem from occurring, the CPU clock must be the master clock

(CLK_CKDIVR[2:0] = 000b) when the user application starts reading the FIFO (CPU clock

divider changed to /1). After the FIFO read operation is complete, the CPU clock divider

(slow mode) could be applied again.

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STM8AF51xx, STM8AF61xx

14

STM8 development tools

Development tools for the STM8A microcontrollers include the

●

STice emulation system offering tracing and code profiling

●

STVD high-level language debugger including assembler and visual development

environment - seamless integration of third party C compilers

●

STVP Flash programming software

In addition, the STM8A comes with starter kits, evaluation boards and low-cost in-circuit

debugging/programming tools.

14.1

Emulation and in-circuit debugging tools

The STM8 tool line includes the STice emulation system offering a complete range of

emulation and in-circuit debugging features on a platform that is designed for versatility and

cost-effectiveness. In addition, STM8A application development is supported by a low-cost

in-circuit debugger/programmer.

The STice is the fourth generation of full-featured emulators from STMicroelectronics. It

offers new advanced debugging capabilities including tracing, profiling and code coverage

analysis to help detect execution bottlenecks and dead code.

In addition, STice offers in-circuit debugging and programming of STM8A microcontrollers

via the STM8 single wire interface module (SWIM), which allows non-intrusive debugging of

an application while it runs on the target microcontroller.

For improved cost effectiveness, STice is based on a modular design that allows you to

order exactly what you need to meet your development requirements and to adapt your

emulation system to support existing and future ST microcontrollers.

14.1.1

STice key features

●

●

●

●

●

●

●

●

●

●

●

Program and data trace recording up to 128 K records

Advanced breakpoints with up to 4 levels of conditions

Data breakpoints

Real-time read/write of all device resources during emulation

Occurrence and time profiling and code coverage analysis (new features)

In-circuit debugging/programming via SWIM protocol

8-bit probe analyzer

1 input and 2 output triggers

USB 2.0 high-speed interface to host PC

Power supply follower managing application voltages between 1.62 to 5.5 V

Modularity that allows you to specify the components you need to meet your

development requirements and adapt to future requirements

●

Supported by free software tools that include integrated development environment

(IDE), programming software interface and assembler for STM8.

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STM8 development tools

14.2

Software tools

STM8 development tools are supported by a complete, free software package from

STMicroelectronics that includes ST visual develop (STVD) IDE and the ST visual program-

mer (STVP) software interface. STVD provides seamless integration of the Cosmic C com-

piler for STM8, which is available in a free version that outputs up to 16 Kbytes of code.

14.2.1

STM8 toolset

The STM8 toolset with STVD integrated development environment and STVP programming

software is available for free download at www.st.com/mcu. This package includes:

ST visual develop

Full-featured integrated development environment from STMicroelectronics, featuring:

●

●

●

●

●

●

Seamless integration of C and ASM toolsets

Full-featured debugger

Project management

Syntax highlighting editor

Integrated programming interface

Support of advanced emulation features for STice such as code profiling and coverage

ST visual programmer (STVP)

Easy-to-use, unlimited graphical interface allowing read, write and verification of the STM8A

microcontroller’s Flash memory. STVP also offers project mode for saving programming

configurations and automating programming sequences.

14.2.2

C and assembly toolchains

Control of C and assembly toolchains is seamlessly integrated into the STVD integrated

development environment, making it possible to configure and control the building of your

application directly from an easy-to-use graphical interface. Available toolchains include:

C compiler for STM8

Available in a free version that outputs up to 16 Kbytes of code. For more information, see

www.cosmic-software.com, www.raisonance.com

STM8 assembler linker

Free assembly toolchain included in the STM8 toolset, which allows you to assemble and

link your application source code.

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14.3

Programming tools

During the development cycle, STice provides in-circuit programming of the STM8A Flash

microcontroller on your application board via the SWIM protocol. Additional tools are to

include a low-cost in-circuit programmer as well as ST socket boards, which provide

dedicated programming platforms with sockets for programming your STM8A.

For production environments, programmers will include a complete range of gang and

automated programming solutions from third-party tool developers already supplying

programmers for the STM8 family.

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Revision history

15

Revision history

Table 67. Document revision history

Date

Revision

Changes

31-Jan-2008

Rev 1

Initial release

Added ‘H’ products to the datasheet (Flash no EEPROM).

Features on page 1: Updated Memories, Reset and supply

management, Communication interfaces and I/Os; reduced wakeup

pins by 1.

Table 1: Removed STM8AF6168, STM8AF6148, STM8AF6166,

STM8AF6146, STM8AF5168, STM8AF5186, STM8AF5176, and

STM8AF5166.

Section 1, Section 5, Section 6.2, Table 33, and Section 9: Updated

reference documentation: RM0009, PM0047, and UM0470.

Section 2: Added information about peak performance.

Section 3: Removed STM8A common features table.

Table 2: Removed STM8AF5186T, STM8AF5176T, STM8AF5168T,

and STM8AF5166T.

Table 3: Removed STM8AF6168T, STM8AF6166T, STM8AF6148T,

and STM8AF6146T.

Section 5: Made minor content changes and improved readability

and layout.

Section 5.5.3: Major modification, TMU included.

Section 5.5.2: User trimming updated.

Section 5.5.3: LSI as CPU clock added.

Section 5.5.4 , Section 5.5.5: Maximum frequency conditional 32

Kbyte/128 Kbyte.

Section 5.8: Scan for 128 Kbyte removed.

22-Aug-2008

Rev 2

Section 5.9, Section 5.9.3: SPI 10 Mb/s.

Figure 3, Figure 4, and Figure 5: Amended footnote 1.

Table 6: HS output changed from 20 mA to 8 mA.

Section 7: Corrected Figure 7: Register and memory map; removed

address list; added Table 8.

Section 10.3.2 Note on typical/WC values added.

Table 14: Replaced the source blocks ‘simple USART’, ‘very low-end

timer (timer 4)’, and ‘EEPROM’ with ‘LINUART’, ‘timer4’ and

‘reserved’ respectively, added TMU registers.

Table 32: Updated OPT6 and NOPT6, added OPT7 to 17 (TMU, BL)

Table 33: Updated OPT1 UBC[7:0], OPT4 CKAWUSEL, OPT4

PRSC [1:0], and OPT6, added OPT7 to 16 (TMU).

Table 35: Amended footnotes.

Table 37: Added parameter ‘voltage and current operating

conditions’.

Table 38: Amended footnotes.

Table 39: Replaced.

Table 40: Amended maximum data and footnotes.

Table 21: Replaced.

Table 22: Added and amended I_DD(RUN)data; amended I_DD(WFI)

data; amended footnotes.

Table 43: Filled in, amended maximum data and footnotes.

Figure 14 to Figure 19: info on peripheral activity added.

Table 44: Modified f_{HSE_ext}data and added V_HSEdhldata.

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Revision history

Table 67. Document revision history (continued)

STM8AF51xx, STM8AF61xx

Date

Revision

Changes

Table 46: Removed ACC_HSIparameters and replaced with ACC_HS

parameters; amended data and footnotes.

Amended data of ‘RAM and hardware registers’ table.

Table 48: Updated names and data of N_RWand t_RETparameters.

Table 51: Added V_OHand V_OLparameters; Updated I_{lkg ana}

parameter.

Removed: Output driving current (standard ports), Output driving

current (true open drain ports), and Output driving current (high sink

ports).

Table 56: Updated f_ADC, t_S, and t_CONVdata.

ADC accuracy for V_DDA= 3.3 V table: Removed the 4-MHz condition

from all parameters.

Rev 2

cont’d

22-Aug-2008

Table 57: Removed the 4-MHz condition from all parameters;

updated footnote 1 and removed footnote 2.

Table 61: Added data for T_A= 145 °C.

Figure 50: Updated memory size, pin count and package type

information.

Replaced the salestype ‘STM8H61xx’ with ‘STM8AH61xx on the first

page.

Added ‘part numbers’ to heading rows of Table 1: Device summary.

Updated the 80-pin package silhouette on page 1 in line with POA

0062342-revD.

Table 14: Renamed ‘TMU key registers 0-7 [7:0]’ as ‘TMU key

registers 1-8 [7:0]’

Section 9: Updated introductory text concerning option bytes which

do not need to be saved in a complementary form.

Table 14: Renamed the option bits ‘TMU[0:3]’, ‘NTMU[0:3]’, and

‘TMU_KEY 0-7 [7:0]’ as ‘TMU[3:0]’, ‘NTMU[3:0]’, and ‘TMU_KEY 1-8

[7:0]’ respectively.

16-Sep-2008

Rev 3

Table 33: Updated values of option byte 5 (HSECNT[7:0]); inverted

the description of option byte 6 (TMU[3:0]); renamed option bytes 8

to 15 ‘TMU_KEY 0-7 [7:0]’, as ‘TMU_KEY 1-8 [7:0]’.

Updated 80-pin package information in line with POA 0062342-revD

in Figure 46 and Table 63.

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Table 67. Document revision history (continued)

Revision history

Date

Revision

Changes

Added ‘STM8AH61xx’ and ‘STM8AH51xx to document header.

Updated Features on page 1 (memories, timers, operating

temperature, ADC and I/Os).

Updated Table 1: Device summary

Updated Kbytes value of program memory in Chapter 1: Introduction

Chapter 2: Description

– Changed the first two lines from the top.

Updated Figure 1: STM8A block diagram

Updated Chapter 5: Product overview

In Figure 5: LQFP 48-pin pinout, added USART function to pins 10,

11, and 12; added CAN Tx and CAN Rx functions to pins 35 and 36

respectively.

Section 6.2: Pin description

– Deleted text below the Table 6: Legend/abbreviation for Table 7

Table 7: STM8A microcontroller family pin description

– 68th, 69th pin (LQFP80): replaced X with a dash for PP output

– Added a table footnote

Updated Figure 7: Register and memory map

Table 8: Memory model 128K

– Updated footnote

Deleted the table “Stack and RAM partitioning“

Table 31: STM8A interrupt table.

– Updated priorities 13, 15, 17, 20 and 24

– Changed table footnote

01-Jul-2009

Rev 4

Updated Chapter 7.2: Register map

Updated Table 50: Data memory, Table 51: I/O static characteristics,

and Table 52: NRST pin characteristics.

Section 10.1.1: Minimum and maximum values.

– Added ambient temperature T_A= -40 °C

Updated Table 34: Voltage characteristics

Updated Table 35: Current characteristics

Updated Table 36: Thermal characteristics

UpdatedTable 37: General operating conditions

UpdatedTable 38: Operating conditions at power-up/power-down.

Figure 12: fCPUmax versus VDD.

– Updated temperature ranges in functional area

– Added a figure footnote

Removed ‘total current consumption’ and ‘note on the run-current

typical values’.

Replaced Table 39: Total current consumption in run, wait and slow

mode. General conditions for VDD apply. TA = -40 °C to 145 °C

Replaced Table 40: Total current consumption in halt and active halt

modes. General conditions for VDD apply. TA = -40 °C to 55 °C

unless otherwise stated.

Removed Table 21: Total current consumption in run, wait and slow

mode. General conditions for V_DDapply. T_A= -40 °C to 145 °C

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Revision history

Table 67. Document revision history (continued)

STM8AF51xx, STM8AF61xx

Date

Revision

Changes

Removed Table 22: Total current consumption and timing in halt, fast

active halt and slow active halt modes at V_DD= 3.3 V.

Added Table 41: Oscillator current consumption

Added Table 42: Programming current consumption.

Updated Table 43: Typical peripheral current consumption VDD = 5.0

V

Changed Section : HSE external clock title from “HSE user external

clock“

Updated Table 44: HSE external clock characteristics

Updated Table 45: HSE oscillator characteristics.

Figure 21: HSE oscillator circuit diagram.

– Changed ‘consumption control’ to ‘current control’

HSE oscillator critical gm formula.

– Clarified formula

Updated Table 46: HSI oscillator characteristics.

Removed ‘RAM and hardware registers’

Removed Table 29: RAM and hardware registers.

Updated Table 48: Flash program memory/data EEPROM memory.

Added Table 49: Program memory

Added Table 50: Data memory.

Updated Table 51: I/O static characteristics

Updated Table 52: NRST pin characteristics

Updated Table 53: TIM 1, 2, 3, and 4 electrical specifications

Section 10.3.9: SPI interface

01-Jul-2009

Rev 4

Changed title from “SPI serial peripheral interface“

Updated Table 54: SPI characteristics.

Figure 41: SPI timing diagram in slave mode and with CPHA = 0

– Changed title

– Added footnote 1.

Figure 42: SPI timing diagram in slave mode and with CPHA = 1

– Changed title

Updated Table 56: ADC characteristics.

Updated Figure 44: Typical application with ADC and added legend.

Removed Table 36: ADC accuracy for V_DDA= 3.3 V

Updated Table 57: ADC accuracy for VDDA = 5 V

Updated Table 59: EMI data

Updated Table 61: Electrical sensitivities

Added Section 11.1: ECOPACK®.

Figure 47: 64-pin low profile quad flat package (10 x 10)

– Deleted footnote

Updated Figure 50: Ordering information scheme(1).

Added Chapter 13: Known limitations.

Updated Table 1: Device summary:

22-Oct-2009

Rev 5

– Added STM8AF5178, STM8AF519A and STM8AF619A.

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Table 67. Document revision history (continued)

Revision history

Date

Revision

Changes

Updated title on cover page.

Modified cover page header to clarify the part numbers covered by

the datasheets. Updated Note 1 below Table 1: Device summary to

add ‘P’ order codes.

Changed definition of ‘P’ order codes.

‘Q’ order codes (FASTROM and EEPROM) removed.

Content of Section 5: Product overview reorganized. Table 7: STM8A

microcontroller family pin description: updated PD7/TLI alternate

function, removed caution note for e, soit:

PD6/ LINUART_RX, and added Note 1 to PA1/OSCIN.

Renamed Section 7 Memory and register map, and content merged

with section 9. Register map. Updated Figure 7: Register and

memory map.

13-Apr-2010

Rev 6

Renamed BL_EN and NBL_EN, BL and NBL, respectively, in

Table 32: Option bytes.

Updated AFR4 definition in Table 33: Option byte description.Added

C_EXTin Table 37: General operating conditions, and Section 10.3.1:

VCAP external capacitor.

Update t_VDDin Table 38: Operating conditions at power-up/power-

down.

Moved Table 43: Typical peripheral current consumption VDD = 5.0 V

to Section : Current consumption for on-chip peripherals.

Removed V_ESD(MM)from Table 60: ESD absolute maximum ratings.

Adapted Section 12: Ordering information to the devices supported

by the datasheet.

Updated Section 13: Known limitations.

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Doc ID 14395 Rev 6

相关型号：

STM8AF5199TBU

8-BIT, FLASH, 24MHz, MICROCONTROLLER, PQFP64, 10 X 10 MM, ROHS COMPLIANT, LQFP-64

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STMICROELECTR

STM8AF5199TBX

8-BIT, FLASH, 24MHz, MICROCONTROLLER, PQFP64, 10 X 10 MM, ROHS COMPLIANT, LQFP-64

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STMICROELECTR

STM8AF5199TBXXXX

8-BIT, FLASH, 24MHz, MICROCONTROLLER, PQFP64, 10 X 10 MM, ROHS COMPLIANT, LQFP-64

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STMICROELECTR

STM8AF5199TBXXXY

8-BIT, FLASH, 24MHz, MICROCONTROLLER, PQFP64, 10 X 10 MM, ROHS COMPLIANT, LQFP-64

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STMICROELECTR

STM8AF5199TBY

8-BIT, FLASH, 24MHz, MICROCONTROLLER, PQFP64, 10 X 10 MM, ROHS COMPLIANT, LQFP-64

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STMICROELECTR

STM8AF5199TCR

MICROCONTROLLER, PQFP64, 10 X 10 MM, ROHS COMPLIANT, LQFP-64

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STMICROELECTR

STM8AF5199TCU

8-BIT, FLASH, 24MHz, MICROCONTROLLER, PQFP64, 10 X 10 MM, ROHS COMPLIANT, LQFP-64

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STMICROELECTR

STM8AF5199TCXXXU

8-BIT, FLASH, 24MHz, MICROCONTROLLER, PQFP64, 10 X 10 MM, ROHS COMPLIANT, LQFP-64

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-

STMICROELECTR

STM8AF5199TCXXXY

8-BIT, FLASH, 24MHz, MICROCONTROLLER, PQFP64, 10 X 10 MM, ROHS COMPLIANT, LQFP-64

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STMICROELECTR

STM8AF5199TCY

8-BIT, FLASH, 24MHz, MICROCONTROLLER, PQFP64, 10 X 10 MM, ROHS COMPLIANT, LQFP-64

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-

STMICROELECTR

STM8AF5199TDXXXU

8-BIT, FLASH, 24MHz, MICROCONTROLLER, PQFP64, 10 X 10 MM, ROHS COMPLIANT, LQFP-64

Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-

STMICROELECTR

STM8AF5199TDXXXX

8-BIT, FLASH, 24MHz, MICROCONTROLLER, PQFP64, 10 X 10 MM, ROHS COMPLIANT, LQFP-64

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STMICROELECTR

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