STM8AF6248TCX [STMICROELECTRONICS]
Automotive 8-bit MCU with 16 Kbytes Flash, LIN, 16 MHz CPU, integrated EEPROM;![STM8AF6248TCX](http://pdffile.icpdf.com/pdf1/p00185/img/icpdf/STM8AF_1046803_icpdf.jpg)
型号: | STM8AF6248TCX |
厂家: | ![]() |
描述: | Automotive 8-bit MCU with 16 Kbytes Flash, LIN, 16 MHz CPU, integrated EEPROM 闪存 可编程只读存储器 电动程控只读存储器 电可擦编程只读存储器 |
文件: | 总89页 (文件大小:1362K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
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STM8AF6x26/4x/66/68
Automotive 8-bit MCU, with up to 32 Kbytes Flash, data EEPROM,
10-bit ADC, timers, LIN, SPI, I2C, 3 to 5.5 V
Datasheet −production data
Features
■ Core
– Max f
: 16 MHz
LQFP48 7x7
LQFP32 7x7
CPU
– Advanced STM8A core with Harvard
architecture and 3-stage pipeline
– Average 1.6 cycles/instruction resulting in
VFQFPN32 5x5
10 MIPS at 16 MHz f
standard benchmark
for industry
CPU
– Window and independent watchdog timers
■ Memories
■ Communication interfaces
– Flash Program memory: 16 to 32 Kbytes
Flash; data retention 20 years at 55 °C
after 1 kcycle
– LINUART
– LIN 2.1 compliant, master/slave modes
with automatic resynchronization
– Data memory: 0.5 to 1 Kbyte true data
EEPROM; endurance 300 kcycles
– SPI interface up to 10 Mbit/s or f
– I C interface up to 400 Kbit/s
/2
MASTER
2
– RAM: 1 to 2 Kbytes
■ Analog-to-digital converter (ADC)
■ Clock management
– 10-bit accuracy, 2LSB TUE accuracy, 2LSB
TUE linearity ADC and up to 10 multiplexed
channels with individual data buffer
– Low-power crystal resonator oscillator with
external clock input
– Internal, user-trimmable 16 MHz RC and
low-power 128 kHz RC oscillators
– Clock security system with clock monitor
– Analog watchdog, scan and continuous
sampling mode
■ I/Os
■ Reset and supply management
– Wait/auto-wakeup/Halt low-power modes
with user definable clock gating
– Up to 38 user pins including 10 HS I/Os
– Highly robust I/O design, immune against
current injection
– Low consumption power-on and power-
down reset
■ Operating temperature up to 150 °C
■ Qualification conforms to AEC-Q100 rev G
■ Interrupt management
(1)
– Nested interrupt controller with 32 vectors
– Up to 34 external interrupts on 5 vectors
Table 1.
Device summary
Part numbers: STM8AF622x/4x STM8AF6266/68
■ Timers
STM8AF6268, STM8AF6248, STM8AF6266, STM8AF6246,
STM8AF6226
– Up to 2 general purpose 16-bit PWM timers
with up to 3 CAPCOM channels each (IC,
OC or PWM)
– Advanced control timer: 16-bit, 4 CAPCOM
channels, 3 complementary outputs, dead-
time insertion and flexible synchronization
(2)
(2)
Part numbers: STM8AF612x/4x STM8AF6166/68
STM8AF6168, STM8AF6148, STM8AF6166, STM8AF6146,
STM8AF6126
1. In the order code, ‘F’ applies to devices with Flash program
memory and data EEPROM while ‘H’ refers to devices with
Flash program memory only. ‘F’ is replaced by ‘P’ for devices
with FASTROM (see Tables 2 and 3, and Figure 47).
– 8-bit AR basic timer with 8-bit prescaler
– Auto-wakeup timer
2. Not recommended for new design.
July 2012
Doc ID 14952 Rev 6
1/89
This is information on a product in full production.
www.st.com
1
Contents
STM8AF61xx, STM8AF62xx
Contents
1
2
3
4
5
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Product line-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Product overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
5.1
STM8A central processing unit (CPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
5.1.1
5.1.2
5.1.3
Architecture and registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
5.2
Single wire interface module (SWIM) and debug module (DM) . . . . . . . . 13
5.2.1
5.2.2
SWIM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Debug module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5.3
5.4
Interrupt controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Flash program and data EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5.4.1
5.4.2
5.4.3
5.4.4
Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Write protection (WP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Protection of user boot code (UBC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Read-out protection (ROP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5.5
Clock controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5.5.1
5.5.2
5.5.3
5.5.4
5.5.5
5.5.6
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
16 MHz high-speed internal RC oscillator (HSI) . . . . . . . . . . . . . . . . . . 15
128 kHz low-speed internal RC oscillator (LSI) . . . . . . . . . . . . . . . . . . . 16
16 MHz high-speed external crystal oscillator (HSE) . . . . . . . . . . . . . . 16
External clock input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Clock security system (CSS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5.6
5.7
Low-power operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
5.7.1
5.7.2
5.7.3
Watchdog timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Auto-wakeup counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Beeper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
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Contents
5.7.4
5.7.5
Advanced control and general purpose timers . . . . . . . . . . . . . . . . . . . 18
Basic timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
5.8
5.9
Analog-to-digital converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Communication interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
5.9.1
5.9.2
5.9.3
Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
2
Inter integrated circuit (I C) interface . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Universal asynchronous receiver/transmitter with LIN support
(LINUART) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
5.10 Input/output specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
6
7
Pinouts and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
6.1
6.2
Package pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Alternate function remapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Memory and register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
7.1
7.2
Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
8
Interrupt table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Option bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
9
10
10.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
10.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
10.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
10.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
10.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
10.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
10.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
10.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
10.3.1 VCAP external capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
10.3.2 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
10.3.3 External clock sources and timing characteristics . . . . . . . . . . . . . . . . . 54
10.3.4 Internal clock sources and timing characteristics . . . . . . . . . . . . . . . . . 56
10.3.5 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
10.3.6 I/O port pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
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Contents
STM8AF61xx, STM8AF62xx
10.3.7 Reset pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
10.3.8 TIM 1, 2, 3, and 4 timer specifications . . . . . . . . . . . . . . . . . . . . . . . . . . 65
10.3.9 SPI serial peripheral interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
2
10.3.10 I C interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
10.3.11 10-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
10.3.12 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
10.4 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
10.4.1 Reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
10.4.2 Selecting the product temperature range . . . . . . . . . . . . . . . . . . . . . . . . 74
11
Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
11.1 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
12
13
Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
STM8 development tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
13.1 Emulation and in-circuit debugging tools . . . . . . . . . . . . . . . . . . . . . . . . . 82
13.1.1 STice key features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
13.2 Software tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
13.2.1 STM8 toolset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
13.2.2 C and assembly toolchains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
13.3 Programming tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
14
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
4/89
Doc ID 14952 Rev 6
STM8AF61xx, STM8AF62xx
List of tables
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
Device summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
STM8AF62xx product line-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
STM8AF/H61xx product line-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Peripheral clock gating bit assignments in CLK_PCKENR1/2 registers. . . . . . . . . . . . . . . 16
Advanced control and general purpose timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
TIM4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
ADC naming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Communication peripheral naming correspondence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Legend/abbreviation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
STM8AF61xx/62xx (32 Kbytes) microcontroller pin description . . . . . . . . . . . . . . . . . . . . . 26
Memory model for the devices covered in this datasheet. . . . . . . . . . . . . . . . . . . . . . . . . . 29
I/O port hardware register map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
General hardware register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
CPU/SWIM/debug module/interrupt controller registers. . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Temporary memory unprotection registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
STM8A interrupt table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Option bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Option byte description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Operating lifetime . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Operating conditions at power-up/power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Total current consumption in Run, Wait and Slow mode.
General conditions for V apply, T = -40 to 150 °C . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
DD
A
Table 26.
Total current consumption in Halt and Active-halt modes.
General conditions for V apply, T = -40 to 55 °C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
DD
A
Table 27.
Table 28.
Table 29.
Table 30.
Table 31.
Table 32.
Table 33.
Table 34.
Table 35.
Table 36.
Table 37.
Table 38.
Table 39.
Table 40.
Table 41.
Table 42.
Table 43.
Table 44.
Table 45.
Table 46.
Oscillator current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Programming current consumption. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Typical peripheral current consumption V = 5.0 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
DD
HSE user external clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
HSE oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
HSI oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Flash program memory/data EEPROM memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Flash program memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Data memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
TIM 1, 2, 3, and 4 electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
2
I C characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
ADC accuracy for V
= 5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
DDA
EMS data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
EMI data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
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List of tables
STM8AF61xx, STM8AF62xx
Table 47.
Table 48.
Table 49.
Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
VFQFPN 32-lead very thin fine pitch quad flat no-lead package
mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
LQFP 48-pin low profile quad flat package mechanical data . . . . . . . . . . . . . . . . . . . . . . . 77
LQFP 32-pin low profile quad flat package mechanical data . . . . . . . . . . . . . . . . . . . . . . . 79
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Table 50.
Table 51.
Table 52.
6/89
Doc ID 14952 Rev 6
STM8AF61xx, STM8AF62xx
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
STM8A block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Flash memory organization of STM8A products. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
VFQFPN/LQFP 32-pin pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
LQFP 48-pin pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Register and memory map of STM8A products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Pin loading conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
f
versus V
CPUmax
DD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
External capacitor C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
EXT
Figure 10. Typ. I
Figure 11. Typ. I
Figure 12. Typ. I
Figure 13. Typ. I
Figure 14. Typ. I
Figure 15. Typ. I
vs. V @f
= 16 MHz, peripheral = on . . . . . . . . . . . . . . . . . . . . . . . 53
DD(RUN)HSE
DD(RUN)HSE
DD(RUN)HSI
DD(WFI)HSE
DD(WFI)HSE
DD
CPU
vs. f
@ V = 5.0 V, peripheral = on . . . . . . . . . . . . . . . . . . . . . . . . 53
CPU
DD
vs. V @ f
= 16 MHz, peripheral = off . . . . . . . . . . . . . . . . . . . . . . . 54
= 16 MHz, peripheral = on . . . . . . . . . . . . . . . . . . . . . . . 54
DD
CPU
vs. V @ f
DD
CPU
vs. f
@ V = 5.0 V, peripheral = on . . . . . . . . . . . . . . . . . . . . . . . . . 54
CPU
DD
vs. V @ f = 16 MHz, peripheral = off . . . . . . . . . . . . . . . . . . . . . . . 54
DD(WFI)HSI
DD
CPU
Figure 16. HSE external clock source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Figure 17. HSE oscillator circuit diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Figure 18. Typical HSI frequency vs V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
DD
Figure 19. Typical LSI frequency vs V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
DD
Figure 20. Typical V and V vs V @ four temperatures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
IL
IH
DD
Figure 21. Typical pull-up resistance R vs V @ four temperatures . . . . . . . . . . . . . . . . . . . . . . . 60
PU
DD
Figure 22. Typical pull-up current I vs V @ four temperatures . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
pu
DD
Figure 23. Typ. V @ V = 3.3 V (standard ports). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
OL
DD
Figure 24. Typ. V @ V = 5.0 V (standard ports). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
OL
DD
Figure 25. Typ. V @ V = 3.3 V (true open drain ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
OL
DD
Figure 26. Typ. V @ V = 5.0 V (true open drain ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
OL
DD
Figure 27. Typ. V @ V = 3.3 V (high sink ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
OL
DD
Figure 28. Typ. V @ V = 5.0 V (high sink ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
OL
DD
Figure 29. Typ. V - V @ V = 3.3 V (standard ports). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
DD
OH
DD
Figure 30. Typ. V - V @ V = 5.0 V (standard ports). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
DD
OH
DD
Figure 31. Typ. V - V @ V = 3.3 V (high sink ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
DD
OH
DD
Figure 32. Typ. V - V @ V = 5.0 V (high sink ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
DD
OH
DD
Figure 33. Typical NRST V and V vs V @ four temperatures . . . . . . . . . . . . . . . . . . . . . . . . . . 63
IL
IH
DD
Figure 34. Typical NRST pull-up resistance R vs V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
PU
DD
Figure 35. Typical NRST pull-up current I vs V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
pu
DD
Figure 36. Recommended reset pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Figure 37. SPI timing diagram where slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Figure 38. SPI timing diagram where slave mode and CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Figure 39. SPI timing diagram - master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Figure 40. Typical application with ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Figure 41. ADC accuracy characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Figure 42. VFQFPN 32-lead very thin fine pitch quad flat no-lead package (5 x 5). . . . . . . . . . . . . . . 76
Figure 43. LQFP 48-pin low profile quad flat package (7 x 7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Figure 44. LQFP 48-pin recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Figure 45. LQFP 32-pin low profile quad flat package (7 x 7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Figure 46. LQFP 32-pin recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
(1)
Figure 47. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
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Introduction
STM8AF61xx, STM8AF62xx
1
Introduction
This datasheet refers to the STM8AF61xx (STM8AF612x, STM8AF614x, STM8AF6166,
and STM8AF6168) and STM8AF62xx products with 16 to 32 Kbytes of Flash program
memory.
In the order code, the letter ‘F’ refers to product versions with data EEPROM and ‘H’ refers
to product versions without data EEPROM. The identifiers ‘F’ and ‘H’ do not coexist in a
given order code.
The datasheet contains the description of family features, pinout, electrical characteristics,
mechanical data and ordering information.
●
For complete information on the STM8A microcontroller memory, registers and
peripherals, please refer to STM8S and STM8A microcontroller families reference
manual (RM0016).
●
●
●
For information on programming, erasing and protection of the internal Flash memory
please refer to the STM8 Flash programming manual (PM0051).
For information on the debug and SWIM (single wire interface module) refer to the
STM8 SWIM communication protocol and debug module user manual (UM0470).
For information on the STM8 core, please refer to the STM8 CPU programming manual
(PM0044).
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STM8AF61xx, STM8AF62xx
Description
2
Description
The STM8AF61xx and STM8AF62xx automotive 8-bit microcontrollers offer from 16 to 32
Kbytes of Flash program memory and integrated true data EEPROM. They are referred to
as medium density STM8A devices in the STM8S and STM8A microcontroller families
reference manual (RM0016).
All devices of the STM8A product line provide the following benefits: reduced system cost,
performance and robustness, short development cycles, and product longevity.
The system cost is reduced thanks to an integrated true data EEPROM for up to 300 k
write/erase cycles and a high system integration level with internal clock oscillators,
watchdog, and brown-out reset.
Device performance is ensured by a clock frequency of up to 16 MHz CPU and enhanced
characteristics which include robust I/O, independent watchdogs (with a separate clock
source), and a clock security system.
Short development cycles are guaranteed due to application scalability across a common
family product architecture with compatible pinout, memory map and and modular
peripherals. Full documentation is offered with a wide choice of development tools.
Product longevity is ensured in the STM8A family thanks to their advanced core which is
made in a state-of-the art technology for automotive applications with 3.3 V to 5 V operating
supply.
All STM8A and ST7 microcontrollers are supported by the same tools including
STVD/STVP development environment, the STice emulator and a low-cost, third party in-
circuit debugging tool.
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Product line-up
STM8AF61xx, STM8AF62xx
3
Product line-up
²
Table 2.
STM8AF62xx product line-up
Medium
density
Flash
I/0
wakeup
pins
RAM Data EE 10-bit
Timers
Serial
interfaces
Order code
Package
program (bytes) (bytes) A/D ch. (IC/OC/PWM)
memory
(bytes)
STM8AF/P6268
STM8AF/P6248
32 K
16 K
2 K
2 K
1 K
1x8-bit: TIM4
3x16-bit: TIM1, LIN(UART),
LQFP48
(7x7)
10
38/35
25/23
25/23
TIM2, TIM3
(9/9/9)
SPI, I²C
0.5 K
STM8AF/P6266
STM8AF/P6246
STM8AF/P6226
STM8AF/P6266
32 K
16 K
8 K
2 K
2 K
2 K
2 K
1 K
0.5 K
384
1x8-bit: TIM4
3x16-bit: TIM1, LIN(UART),
LQFP32
(7x7)
7
7
TIM2, TIM3
(8/8/8)
SPI, I²C
32 K
1 K
1x8-bit: TIM4
3x16-bit: TIM1, LIN(UART),
VFQFPN32
TIM2, TIM3
(8/8/8)
SPI, I²C
STM8AF/P6246
16 K
2 K
0.5 K
²
(1)
Table 3.
STM8AF/H61xx product line-up
Medium
density
Flash
I/0
wakeup
pins
RAM Data EE 10-bit
Timers
Serial
Order code
Package
program (bytes) (bytes) A/D ch. (IC/OC/PWM) interfaces
memory
(bytes)
STM8AF/H/P6168
STM8AF/H/P6148
32 K
16 K
2 K
1 K
1 K
1x8-bit: TIM4
3x16-bit: TIM1, LIN(UART),
TIM2, TIM3
(9/9/9)
LQFP48
(7x7)
10
7
38/35
25/23
SPI, I²C
0.5 K
STM8AF/H/P6166
STM8AF/H/P6146
STM8AF/H/P6126
32 K
16 K
8 K
2 K
1 K
512
1 K
0.5 K
384
1x8-bit: TIM4
3x16-bit: TIM1, LIN(UART),
TIM2, TIM3
(8/8/8)
LQFP32
(7x7)
SPI, I²C
1. These devices are not recommended for new design.
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STM8AF61xx, STM8AF62xx
Block diagram
4
Block diagram
Figure 1.
STM8A block diagram
Reset block
Reset
XTAL 1 - 16 MHz
RC int. 16 MHz
Clock controller
Detector
Reset
POR
BOR
RC int. 128 kHz
Clock to peripherals and core
Window WDG
IWDG
STM8A CORE
Single wire
debug interf.
Up to 32 Kbytes
program
Debug/SWIM
LINUART
Flash
Master/slave
automatic
resynchronization
Up to 1 Kbytes
data EEPROM
400 Kbit/s
2
Up to 2 Kbytes
RAM
I C
Boot ROM
10 Mbit/s
SPI
16-bit advanced control
timer (TIM1)
16 channels
10-bit ADC
Up to
9 CAPCOM
channels
16-bit general purpose
timers (TIM2, TIM3)
8-bit basic timer
(TIM4)
AWU timer
1. Legend:
ADC: Analog-to-digital converter
beCAN: Controller area network
BOR: Brownout reset
I²C: Inter-integrated circuit multimaster interface
IWDG: Independent window watchdog
LINUART: Local interconnect network universal asynchronous receiver transmitter
POR: Power on reset
SPI: Serial peripheral interface
SWIM: Single wire interface module
USART: Universal synchronous asynchronous receiver transmitter
Window WDG: Window watchdog
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Product overview
STM8AF61xx, STM8AF62xx
5
Product overview
This section is intended to describe the family features that are actually implemented in the
products covered by this datasheet.
For more detailed information on each feature please refer to the STM8S and STM8A
microcontroller families reference manual (RM0016).
5.1
STM8A central processing unit (CPU)
The 8-bit STM8A core is a modern CISC core and has been designed for code efficiency
and performance. It contains 21 internal registers (six directly addressable in each execution
context), 20 addressing modes including indexed indirect and relative addressing and 80
instructions.
5.1.1
Architecture and registers
●
●
●
●
Harvard architecture
3-stage pipeline
32-bit wide program memory bus with single cycle fetching for most instructions
X and Y 16-bit index registers, enabling indexed addressing modes with or without
offset and read-modify-write type data manipulations
●
●
●
●
8-bit accumulator
24-bit program counter with 16-Mbyte linear memory space
16-bit stack pointer with access to a 64 Kbyte stack
8-bit condition code register with seven condition flags for the result of the last
instruction.
5.1.2
5.1.3
Addressing
●
●
20 addressing modes
Indexed indirect addressing mode for look-up tables located anywhere in the address
space
●
Stack pointer relative addressing mode for efficient implementation of local variables
and parameter passing
Instruction set
●
●
●
●
●
●
●
80 instructions with 2-byte average instruction size
Standard data movement and logic/arithmetic functions
8-bit by 8-bit multiplication
16-bit by 8-bit and 16-bit by 16-bit division
Bit manipulation
Data transfer between stack and accumulator (push/pop) with direct stack access
Data transfer using the X and Y registers or direct memory-to-memory transfers
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STM8AF61xx, STM8AF62xx
Product overview
5.2
Single wire interface module (SWIM) and debug module (DM)
5.2.1
SWIM
The single wire interface module, SWIM, together with an integrated debug module, permits
non-intrusive, real-time in-circuit debugging and fast memory programming. The interface
can be activated in all device operation modes and can be connected to a running device
(hot plugging).The maximum data transmission speed is 145 bytes/ms.
5.2.2
Debug module
The non-intrusive debugging module features a performance close to a full-flavored
emulator. Besides memory and peripheral operation, CPU operation can also be monitored
in real-time by means of shadow registers.
●
●
●
R/W of RAM and peripheral registers in real-time
R/W for all resources when the application is stopped
Breakpoints on all program-memory instructions (software breakpoints), except the
interrupt vector table
●
Two advanced breakpoints and 23 predefined breakpoint configurations
5.3
5.4
Interrupt controller
●
●
●
●
Nested interrupts with three software priority levels
21 interrupt vectors with hardware priority
Five vectors for external interrupts (up to 34 depending on the package)
Trap and reset interrupts
Flash program and data EEPROM
●
●
●
8 Kbytes to 32 Kbytes of medium density single voltage program Flash memory
Up to 1 Kbytes true (not emulated) data EEPROM
Read while write: writing in the data memory is possible while executing code in the
Flash program memory
The whole Flash program memory and data EEPROM are factory programmed with 0x00.
5.4.1
Architecture
●
●
●
●
The memory is organized in blocks of 128 bytes each
Read granularity: 1 word = 4 bytes
Write/erase granularity: 1 word (4 bytes) or 1 block (128 bytes) in parallel
Writing, erasing, word and block management is handled automatically by the memory
interface.
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Product overview
STM8AF61xx, STM8AF62xx
5.4.2
Write protection (WP)
Write protection in application mode is intended to avoid unintentional overwriting of the
memory. The write protection can be removed temporarily by executing a specific sequence
in the user software.
5.4.3
Protection of user boot code (UBC)
If the user chooses to update the Flash program memory using a specific boot code to
perform in application programming (IAP), this boot code needs to be protected against
unwanted modification.
In the STM8A a memory area of up to 32 Kbytes can be protected from overwriting at user
option level. Other than the standard write protection, the UBC protection can exclusively be
modified via the debug interface, the user software cannot modify the UBC protection status.
The UBC memory area contains the reset and interrupt vectors and its size can be adjusted
in increments of 512 bytes by programming the UBC and NUBC option bytes
(see Section 9: Option bytes on page 41).
Figure 2.
Flash memory organization of STM8A products
Programmable area
maximum 32 Kbytes
UBC area
Remains write protected during IAP
Flash
program
memory
Flash program memory area
Write access possible for IAP
Data memory area (1 Kbytes)
Option bytes
Data
EEPROM
memory
5.4.4
Read-out protection (ROP)
The STM8A provides a read-out protection of the code and data memory which can be
activated by an option byte setting (see the ROP option byte in section 10).
The read-out protection prevents reading and writing Flash program memory, data memory
and option bytes via the debug module and SWIM interface. This protection is active in all
device operation modes. Any attempt to remove the protection by overwriting the ROP
option byte triggers a global erase of the program and data memory.
The ROP circuit may provide a temporary access for debugging or failure analysis. The
temporary read access is protected by a user defined, 8-byte keyword stored in the option
byte area. This keyword must be entered via the SWIM interface to temporarily unlock the
device.
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STM8AF61xx, STM8AF62xx
Product overview
If desired, the temporary unlock mechanism can be permanently disabled by the user
through OPT6/NOPT6 option bytes.
5.5
Clock controller
The clock controller distributes the system clock coming from different oscillators to the core
and the peripherals. It also manages clock gating for low-power modes and ensures clock
robustness.
5.5.1
Features
●
Clock sources:
–
–
–
–
16 MHz high-speed internal RC oscillator (HSI)
128 kHz low-speed internal RC (LSI)
1-16 MHz high-speed external crystal (HSE)
Up to 16 MHz high-speed user-external clock (HSE user-ext)
●
●
Reset: After reset the microcontroller restarts by default with an internal 2-MHz clock
(16 MHz/8). The clock source and speed can be changed by the application program
as soon as the code execution starts.
Safe clock switching: Clock sources can be changed safely on the fly in Run mode
through a configuration register. The clock signal is not switched until the new clock
source is ready. The design guarantees glitch-free switching.
●
●
Clock management: To reduce power consumption, the clock controller can stop the
clock to the core or individual peripherals.
Wakeup: In case the device wakes up from low-power modes, the internal RC
oscillator (16 MHz/8) is used for quick startup. After a stabilization time, the device
switches to the clock source that was selected before Halt mode was entered.
●
●
Clock security system (CSS): The CSS permits monitoring of external clock sources
and automatic switching to the internal RC (16 MHz/8) in case of a clock failure.
Configurable main clock output (CCO): This feature permits to outputs a clock signal
for use by the application.
5.5.2
16 MHz high-speed internal RC oscillator (HSI)
●
●
Default clock after reset 2 MHz (16 MHz/8)
Fast wakeup time
User trimming
The register CLK_HSITRIMR with three trimming bits plus one additional bit for the sign
permits frequency tuning by the application program. The adjustment range covers all
possible frequency variations versus supply voltage and temperature. This trimming does
not change the initial production setting.
For reason of compatibility with other devices from the STM8A family, a special mode
with only two trimming bits plus sign can be selected. This selection is controlled
with the HSITRIM0 bit in the option byte registers OPT3 and NOPT3.
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Product overview
STM8AF61xx, STM8AF62xx
5.5.3
128 kHz low-speed internal RC oscillator (LSI)
The frequency of this clock is 128 kHz and it is independent from the main clock. It drives
the independent watchdog or the AWU wakeup timer.
In systems which do not need independent clock sources for the watchdog counters, the
128 kHz signal can be used as the system clock. This configuration has to be enabled by
setting an option byte (OPT3/OPT3N, bit LSI_EN).
5.5.4
16 MHz high-speed external crystal oscillator (HSE)
The external high-speed crystal oscillator can be selected to deliver the main clock in
normal Run mode. It operates with quartz crystals and ceramic resonators.
●
●
●
Frequency range: 1 MHz to 16 MHz
Crystal oscillation mode: preferred fundamental
I/Os: standard I/O pins multiplexed with OSCIN, OSCOUT
5.5.5
5.5.6
External clock input
An external clock signal can be applied to the OSCIN input pin of the crystal oscillator. The
frequency range is 0 to 16 MHz.
Clock security system (CSS)
The clock security system protects against a system stall in case of an external crystal clock
failure.
In case of a clock failure an interrupt is generated and the high-speed internal clock (HSI) is
automatically selected with a frequency of 2 MHz (16 MHz/8).
Table 4.
Bit
Peripheral clock gating bit assignments in CLK_PCKENR1/2 registers
Peripheral
clock
Peripheral
clock
Peripheral
clock
Peripheral
clock
Bit
Bit
Bit
PCKEN17
PCKEN16
PCKEN15
PCKEN14
TIM1
TIM3
TIM2
TIM4
PCKEN13 LINUART PCKEN27 Reserved PCKEN23
PCKEN12 Reserved PCKEN26 Reserved PCKEN22
ADC
AWU
PCKEN11
PCKEN10
SPI
I2C
PCKEN25 Reserved PCKEN21 Reserved
PCKEN24 Reserved PCKEN20 Reserved
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STM8AF61xx, STM8AF62xx
Product overview
5.6
Low-power operating modes
For efficient power management, the application can be put in one of four different low
power modes. You can configure each mode to obtain the best compromise between lowest
power consumption, fastest start-up time and available wakeup sources.
●
●
Wait mode
In this mode, the CPU is stopped but peripherals are kept running. The wakeup is
performed by an internal or external interrupt or reset.
Active-halt mode with regulator on
In this mode, the CPU and peripheral clocks are stopped. An internal wakeup is
generated at programmable intervals by the auto wake up unit (AWU). The main
voltage regulator is kept powered on, so current consumption is higher than in Active-
halt mode with regulator off, but the wakeup time is faster. Wakeup is triggered by the
internal AWU interrupt, external interrupt or reset.
●
●
Active-halt mode with regulator off
This mode is the same as Active-halt with regulator on, except that the main voltage
regulator is powered off, so the wake up time is slower.
Halt mode
CPU and peripheral clocks are stopped, the main voltage regulator is powered off.
Wakeup is triggered by external event or reset.
In all modes the CPU and peripherals remain permanently powered on, the system clock is
applied only to selected modules. The RAM content is preserved and the brown-out reset
circuit remains activated.
5.7
Timers
5.7.1
Watchdog timers
The watchdog system is based on two independent timers providing maximum security to
the applications. The watchdog timer activity is controlled by the application program or
option bytes. Once the watchdog is activated, it cannot be disabled by the user program
without going through reset.
Window watchdog timer
The window watchdog is used to detect the occurrence of a software fault, usually
generated by external interferences or by unexpected logical conditions, which cause the
application program to abandon its normal sequence.
The window function can be used to trim the watchdog behavior to match the application
timing perfectly. The application software must refresh the counter before time-out and
during a limited time window. If the counter is refreshed outside this time window, a reset is
issued.
Doc ID 14952 Rev 6
17/89
Product overview
STM8AF61xx, STM8AF62xx
Independent watchdog timer
The independent watchdog peripheral can be used to resolve malfunctions due to hardware
or software failures.
It is clocked by the 128 kHz LSI internal RC clock source, and thus stays active even in case
of a CPU clock failure. If the hardware watchdog feature is enabled through the device
option bits, the watchdog is automatically enabled at power-on, and generates a reset
unless the key register is written by software before the counter reaches the end of count.
5.7.2
Auto-wakeup counter
This counter is used to cyclically wakeup the device in Active-halt mode. It can be clocked by
the internal 128 kHz internal low-frequency RC oscillator or external clock.
LSI clock can be internally connected to TIM3 input capture channel 1 for calibration.
5.7.3
5.7.4
Beeper
This function generates a rectangular signal in the range of 1, 2 or 4 kHz which can be
output on a pin. This is useful when audible sounds without interference need to be
generated for use in the application.
Advanced control and general purpose timers
STM8A devices described in this datasheet, contain up to three 16-bit advanced control and
general purpose timers providing nine CAPCOM channels in total. A CAPCOM channel can
be used either as input compare, output compare or PWM channel. These timers are
named TIM1, TIM2 and TIM3.
Table 5.
Timer
Advanced control and general purpose timers
Counter Counter Prescaler
Inverted Repetition trigger External Break
Channels
width
type
factor
outputs
counter
unit
trigger
input
TIM1
TIM2
16-bit
Up/down 1 to 65536
4
3
3
Yes
Yes
Yes
Yes
2n
16-bit
16-bit
Up
None
None
No
No
No
No
No
No
No
No
n = 0 to 15
2n
TIM3
Up
2
n = 0 to 15
18/89
Doc ID 14952 Rev 6
STM8AF61xx, STM8AF62xx
Product overview
TIM1: Advanced control timer
This is a high-end timer designed for a wide range of control applications. With its
complementary outputs, dead-time control and center-aligned PWM capability, the field of
applications is extended to motor control, lighting and bridge driver.
●
16-bit up, down and up/down AR (auto-reload) counter with 16-bit fractional prescaler.
●
Four independent CAPCOM channels configurable as input capture, output compare,
PWM generation (edge and center aligned mode) and single pulse mode output
●
Trigger module which allows the interaction of TIM1 with other on-chip peripherals. In
the present implementation it is possible to trigger the ADC upon a timer event.
●
●
●
●
External trigger to change the timer behavior depending on external signals
Break input to force the timer outputs into a defined state
Three complementary outputs with adjustable dead time
Interrupt sources: 4 x input capture/output compare, 1 x overflow/update, 1 x break
TIM2 and TIM3: 16-bit general purpose timers
●
●
●
●
16-bit auto-reload up-counter
15-bit prescaler adjustable to fixed power of two ratios 1…32768
Timers with three or two individually configurable CAPCOM channels
Interrupt sources: 2 or 3 x input capture/output compare, 1 x overflow/update
5.7.5
Basic timer
The typical usage of this timer (TIM4) is the generation of a clock tick.
Table 6.
Timer
TIM4
Counter Counter Prescaler
width
Inverted Repetition trigger External Break
Channels
type
factor
outputs
counter
unit
trigger
input
2n
TIM4
8-bit
Up
0
None
No
No
No
No
n = 0 to 7
●
●
●
8-bit auto-reload, adjustable prescaler ratio to any power of two from 1 to 128
Clock source: master clock
Interrupt source: 1 x overflow/update
Doc ID 14952 Rev 6
19/89
Product overview
STM8AF61xx, STM8AF62xx
5.8
Analog-to-digital converter (ADC)
The STM8A products described in this datasheet contain a 10-bit successive approximation
ADC with up to 16 multiplexed input channels, depending on the package.
The ADC name differs between the datasheet and the STM8A/S reference manual (see
Table 7).
Table 7.
ADC naming
Peripheral name in reference manual
(RM0016)
Peripheral name in datasheet
ADC
ADC1
ADC features
●
●
●
●
●
●
●
●
●
●
●
●
●
10-bit resolution
Single and continuous conversion modes
Programmable prescaler: f divided by 2 to 18
MASTER
Conversion trigger on timer events and external events
Interrupt generation at end of conversion
Selectable alignment of 10-bit data in 2 x 8 bit result register
Shadow registers for data consistency
ADC input range: V
Analog watchdog
≤V ≤V
IN DDA
SSA
Schmitt-trigger on analog inputs can be disabled to reduce power consumption
Scan mode (single and continuous)
Dedicated result register for each conversion channel
Buffer mode for continuous conversion
Note:
An additional AIN12 analog input is not selectable in ADC scan mode or with analog
watchdog. Values converted from AIN12 are stored only into the ADC_DRH/ADC_DRL
registers.
5.9
Communication interfaces
The following sections give a brief overview of the communication peripheral. Some
peripheral names differ between the datasheet and the STM8A/S reference manual (see
Table 8).
Table 8.
Communication peripheral naming correspondence
Peripheral name in reference manual
Peripheral name in datasheet
(RM0016)
LINUART
UART2
20/89
Doc ID 14952 Rev 6
STM8AF61xx, STM8AF62xx
Product overview
5.9.1
Serial peripheral interface (SPI)
The devices covered by this datasheet contain one SPI. The SPI is available on all the
supported packages.
●
●
●
●
●
●
●
Maximum speed: 10 Mbit/s or f
/2 both for master and slave
MASTER
Full duplex synchronous transfers
Simplex synchronous transfers on two lines with a possible bidirectional data line
Master or slave operation - selectable by hardware or software
CRC calculation
1 byte Tx and Rx buffer
Slave mode/master mode management by hardware or software for both master and
slave
●
●
●
●
●
Programmable clock polarity and phase
Programmable data order with MSB-first or LSB-first shifting
Dedicated transmission and reception flags with interrupt capability
SPI bus busy status flag
Hardware CRC feature for reliable communication:
–
–
CRC value can be transmitted as last byte in Tx mode
CRC error checking for last received byte
2
5.9.2
Inter integrated circuit (I C) interface
2
The devices covered by this datasheet contain one I C interface. The interface is available
on all the supported packages.
2
●
I C master features:
–
Clock generation
–
Start and stop generation
2
●
I C slave features:
2
–
–
Programmable I C address detection
Stop bit detection
●
●
Generation and detection of 7-bit/10-bit addressing and general call
Supports different communication speeds:
–
–
Standard speed (up to 100 kHz),
Fast speed (up to 400 kHz)
●
●
Status flags:
–
–
–
Transmitter/receiver mode flag
End-of-byte transmission flag
2
I C busy flag
Error flags:
–
–
–
–
Arbitration lost condition for master mode
Acknowledgement failure after address/data transmission
Detection of misplaced start or stop condition
Overrun/underrun if clock stretching is disabled
Doc ID 14952 Rev 6
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Product overview
STM8AF61xx, STM8AF62xx
●
Interrupt:
–
–
–
Successful address/data communication
Error condition
Wakeup from Halt
●
Wakeup from Halt on address detection in slave mode
5.9.3
Universal asynchronous receiver/transmitter with LIN support
(LINUART)
The devices covered by this datasheet contain one LINUART interface. The interface is
available on all the supported packages. The LINUART is an asynchronous serial
communication interface which supports extensive LIN functions tailored for LIN slave
applications. In LIN mode it is compliant to the LIN standards rev 1.2 to rev 2.1.
Detailed feature list:
LIN mode
Master mode:
●
LIN break and delimiter generation
●
LIN break and delimiter detection with separate flag and interrupt source for read back
checking.
Slave mode:
●
●
●
●
Autonomous header handling – one single interrupt per valid header
Mute mode to filter responses
Identifier parity error checking
LIN automatic resynchronization, allowing operation with internal RC oscillator (HSI)
clock source
●
●
Break detection at any time, even during a byte reception
Header errors detection:
–
–
–
–
–
Delimiter too short
Synch field error
Deviation error (if automatic resynchronization is enabled)
Framing error in synch field or identifier field
Header time-out
22/89
Doc ID 14952 Rev 6
STM8AF61xx, STM8AF62xx
UART mode
Product overview
●
●
Full duplex, asynchronous communications - NRZ standard format (mark/space)
High-precision baud rate generator
A common programmable transmit and receive baud rates up to f
–
/16
MASTER
●
●
●
●
●
●
●
Programmable data word length (8 or 9 bits) – 1 or 2 stop bits – parity control
Separate enable bits for transmitter and receiver
Error detection flags
Reduced power consumption mode
Multi-processor communication - enter mute mode if address match does not occur
Wakeup from mute mode (by idle line detection or address mark detection)
Two receiver wakeup modes:
–
–
Address bit (MSB)
Idle line
5.10
Input/output specifications
The product features four different I/O types:
●
●
●
●
Standard I/O 2 MHz
Fast I/O up to 10 MHz
High sink 8 mA, 2 MHz
2
True open drain (I C interface)
To decrease EMI (electromagnetic interference), high sink I/Os have a limited maximum
slew rate. The rise and fall times are similar to those of standard I/Os.
The analog inputs are equipped with a low leakage analog switch. Additionally, the schmitt-
trigger input stage on the analog I/Os can be disabled in order to reduce the device standby
consumption.
STM8A I/Os are designed to withstand current injection. For a negative injection current of
4 mA, the resulting leakage current in the adjacent input does not exceed 1 µA. Thanks to
this feature, external protection diodes against current injection are no longer required.
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Pinouts and pin description
STM8AF61xx, STM8AF62xx
6
Pinouts and pin description
6.1
Package pinouts
Figure 3.
VFQFPN/LQFP 32-pin pinout
32 31 30 29 28 27 26 25
24
NRST
OSCIN/PA1
OSCOUT/PA2
1
2
3
4
5
6
7
8
PC7/SPI_MISO
PC6/SPI_MOSI
PC5/SPI_SCK
PC4 (HS)/TIM1_CH4
PC3 (HS)/TIM1_CH3
PC2 (HS)/TIM1_CH2
PC1 (HS)/TIM1_CH1
PE5/SPI_NSS
23
22
21
20
19
18
17
V
SS
VCAP
V
DD
V
DDIO
AIN12/PF4
9 101112 13141516
1. (HS) high sink capability.
24/89
Doc ID 14952 Rev 6
STM8AF61xx, STM8AF62xx
Figure 4. LQFP 48-pin pinout
Pinouts and pin description
48474645 44 43 42 41 40 39 38 37
36
NRST
OSCIN/PA1
OSCOUT/PA2
PG1
35 PG0
34 PC7/SPI_MISO
1
2
3
V
33
32
31
30
29
28
27
26
25
4
5
6
7
8
9
10
11
PC6/SPI_MOSI
SSIO_1
V
V
SS
DDIO_2
VCAP
V
SSIO_2
V
PC5/SPI_SCK
DD
V
PC4 (HS)/TIM1_CH4
PC3 (HS)/TIM1_CH3
PC2 (HS)/TIM1_CH2
PC1 (HS)/TIM1_CH1
PE5/SPI_NSS
DDIO_1
TIM2_CH3/PA3
PA4
PA5
PA6
12
24
13141516171819 20212223
2. (HS) high sink capability.
Table 9.
Legend/abbreviation
Type
I= input, O = output, S = power supply
Level
Input
CM = CMOS (standard for all I/Os)
HS = High sink (8 mA)
Output
Output speed
O1 = Standard (up to 2 MHz)
O2 = Fast (up to 10 MHz)
O3 = Fast/slow programmability with slow as default state after reset
O4 = Fast/slow programmability with fast as default state after reset
Port and control
configuration
Input
float = floating, wpu = weak pull-up
Output
T = true open drain, OD = open drain, PP = push pull
Bold X (pin state after reset release).
Reset state
Unless otherwise specified, the pin state is the same during the reset phase (i.e.
“under reset”) and after internal reset release (i.e. at reset state).
Doc ID 14952 Rev 6
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Pinouts and pin description
STM8AF61xx, STM8AF62xx
(1)(2)
Table 10. STM8AF61xx/62xx (32 Kbytes) microcontroller pin description
Pin
Input
Output
number
Alternate
function after
remap
Default alternate
function
Pin name
[option bit]
1
2
3
4
5
6
7
8
-
1
2
3
-
NRST
I/O
I/O
I/O
S
-
X
X
-
X
X
X
-
-
-
-
-
-
-
-
-
-
-
-
-
O1
O1
-
-
X
X
-
-
Reset
—
PA1/OSCIN(3)
PA2/OSCOUT
VSSIO_1
X Port A1 Resonator/crystal in
X Port A2 Resonator/crystal out
—
—
—
—
—
—
—
—
X
-
-
-
-
-
-
I/O ground
4
5
6
7
8
VSS
S
-
-
-
-
-
Digital ground
VCAP
S
-
-
-
-
-
1.8 V regulator capacitor
Digital power supply
I/O power supply
VDD
S
-
-
-
-
-
VDDIO_1
S
-
-
-
-
-
PF4/AIN12(4)(5)
I/O
X
X
O1
X
X Port F4 Analog input 12
TIM3_CH1
[AFR1]
9
-
PA3/TIM2_CH3
I/O
X
X
X
-
O1
X
X Port A3 Timer 2 - channel 3
10
11
12
13
-
-
PA4
PA5
PA6
VDDA
I/O
I/O
I/O
S
X
X
X
-
X
X
X
-
X
X
X
-
-
-
-
-
-
-
-
O3
O3
O3
-
X
X
X
-
X Port A4
X Port A5
X Port A6
—
—
—
—
—
—
—
-
9
-
-
Analog power supply
Analog ground
14 10 VSSA
S
-
-
-
-
-
15
16
-
-
PB7/AIN7
PB6/AIN6
I/O
I/O
X
X
X
X
X
X
O1
O1
X
X
X Port B7 Analog input 7
X Port B6 Analog input 6
I2C_SDA
[AFR6]
17 11 PB5/AIN5
18 12 PB4/AIN4
19 13 PB3/AIN3
I/O
I/O
I/O
X
X
X
X
X
X
X
X
X
-
-
-
O1
O1
O1
X
X
X
X Port B5 Analog input 5
X Port B4 Analog input 4
X Port B3 Analog input 3
I2C_SCL
[AFR6]
TIM1_ETR
[AFR5]
TIM1_
NCC3
[AFR5]
20 14 PB2/AIN2
21 15 PB1/AIN1
22 16 PB0/AIN0
I/O
I/O
I/O
X
X
X
X
X
X
X
X
X
-
-
-
O1
O1
O1
X
X
X
X Port B2 Analog input
X Port B1 Analog input 1
X Port B0 Analog input 0
TIM1_
NCC2
[AFR5]
TIM1_
NCC1
[AFR5]
26/89
Doc ID 14952 Rev 6
STM8AF61xx, STM8AF62xx
Pinouts and pin description
(1)(2)
Table 10. STM8AF61xx/62xx (32 Kbytes) microcontroller pin description
Pin
(continued)
Input
Output
number
Alternate
Default alternate
function
function after
remap
Pin name
[option bit]
23
24
-
PE7/AIN8
PE6/AIN9
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
S
X
X
X
X
X
X
X
X
-
X
X
X
X
X
X
X
X
-
-
-
-
O1
O1
O1
X
X
X
X
X
X
X
X
-
X Port E7 Analog input 8
X Port E7 Analog input 9
X Port E5 SPI master/slave select —
—
X
X
X
X
X
X
X
-
—
25 17 PE5/SPI_NSS
26 18 PC1/TIM1_CH1
27 19 PC2/TIM1_CH2
28 20 PC3/TIM1_CH3
29 21 PC4/TIM1_CH4
30 22 PC5/SPI_SCK
HS O3
HS O3
HS O3
HS O3
O3
X Port C1 Timer 1 - channel 1
X Port C2 Timer 1- channel 2
X Port C3 Timer 1 - channel 3
X Port C4 Timer 1 - channel 4
X Port C5 SPI clock
—
—
—
—
—
—
—
31
32
-
-
VSSIO_2
VDDIO_2
-
-
-
-
-
-
I/O ground
S
-
-
-
-
I/O power supply
SPI master out/
slave in
33 23 PC6/SPI_MOSI
34 24 PC7/SPI_MISO
I/O
X
X
X
-
O3
X
X Port C6
—
I/O
I/O
I/O
X
X
X
X
X
X
X
X
X
X
-
X
-
-
-
-
-
-
-
O3
O1
O1
O1
X
X
X
X
X Port C7 SPI master in/ slave out —
35
36
37
38
39
-
-
-
-
-
PG0
PG1
X Port G0
X Port G1
-
-
—
—
—
—
—
-
PE3/TIM1_BKIN I/O
X
X
X
X Port E3 Timer 1 - break input
PE2/I2C_SDA
PE1/I2C_SCL
I/O
I/O
O1 T(6)
O1 T(6)
-
-
Port E2 I2C data
Port E1 I2C clock
-
Configurable clock
output
40
-
PE0/CLK_CCO
I/O
X
X
X
-
O3
X
X Port E0
—
TIM1_BKIN
[AFR3]/
CLK_CCO
[AFR2]
41 25 PD0/TIM3_CH2
I/O
X
X
X
HS O3
X
X Port D0 Timer 3 - channel 2
42 26 PD1/SWIM(7)
I/O
I/O
X
X
X
X
HS O4
HS O3
X
X
X Port D1 SWIM data interface
X Port D2 Timer 3 - channel 1
—
TIM2_CH3
[AFR1]
43 27 PD2/TIM3_CH1
X
X
ADC_ETR
[AFR0]
44 28 PD3/TIM2_CH2
I/O
I/O
I/O
X
X
X
X
X
X
X
X
X
HS O3
HS O3
X
X
X
X Port D3 Timer 2 - channel 2
X Port D4 Timer 2 - channel 1
PD4/TIM2_CH1/
BEEP output
[AFR7]
45 29
BEEP
PD5/
46 30
-
O1
X Port D5 LINUART data transmit —
LINUART_TX
Doc ID 14952 Rev 6
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Pinouts and pin description
STM8AF61xx, STM8AF62xx
(1)(2)
Table 10. STM8AF61xx/62xx (32 Kbytes) microcontroller pin description
Pin
(continued)
Input
Output
number
Alternate
Default alternate
function
function after
remap
Pin name
[option bit]
LINUART
X Port D6 data
PD6/
LINUART_RX
47 31
I/O
I/O
X
X
X
X
X
X
-
-
O1
O1
X
X
—
receive
48 32 PD7/TLI(8)
X Port D7 Top level interrupt
—
1. Refer to Table 9 for the definition of the abbreviations.
2. Reset state is shown in bold.
3. In Halt/Active-halt mode this pad behaves in the following way:
- the input/output path is disabled
- if the HSE clock is used for wakeup, the internal weak pull up is disabled
- if the HSE clock is off, internal weak pull up setting from corresponding OR bit is used
By managing the OR bit correctly, it must be ensured that the pad is not left floating during Halt/Active-halt.
4. On this pin, a pull-up resistor as specified in Table 37. I/O static characteristics is enabled during the reset phase of the
product.
5. AIN12 is not selectable in ADC scan mode or with analog watchdog.
6. In the open-drain output column, ‘T’ defines a true open-drain I/O (P-buffer, week pull-up, and protection diode to VDD are
not implemented)
7. The PD1 pin is in input pull-up during the reset phase and after reset release.
8. If this pin is configured as interrupt pin, it will trigger the TLI.
6.2
Alternate function remapping
As shown in the rightmost column of Table 10, some alternate functions can be remapped at
different I/O ports by programming one of eight AFR (alternate function remap) option bits.
Refer to Section 9: Option bytes on page 41. When the remapping option is active, the
default alternate function is no longer available.
To use an alternate function, the corresponding peripheral must be enabled in the peripheral
registers.
Alternate function remapping does not effect GPIO capabilities of the I/O ports (see the
GPIO section of the STM8S and STM8A microcontroller families reference manual,
RM0016).
28/89
Doc ID 14952 Rev 6
STM8AF61xx, STM8AF62xx
Memory and register map
7
Memory and register map
7.1
Memory map
Figure 5.
Register and memory map of STM8A products
00 0000
Up to 2 Kbytes RAM
stack
Reserved
RAM end
00 4000
Up to 1 Kbyte data EEPROM
00 4400
Reserved
Option bytes
Reserved
00 4800
00 4900
00 5000
HW registers
Reserved
00 581D
00 6000
00 6800
00 7F00
00 8000
00 8080
2 Kbytes of Boot ROM
CPU/SWIM/Debug/ITC registers
IT vectors
Up to 32 Kbytes of
Flash program memory
Flash Program memory end
Table 11. Memory model for the devices covered in this datasheet
Flash program
Flash program
memory size
RAM end
address
Stack roll-over
address
memory end
address
RAM size
32K
16K
8K
0x00 0FFFF
0x00 0BFFF
0x00 09FFF
2K
0x00 07FF
0x00 0600
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Memory and register map
STM8AF61xx, STM8AF62xx
7.2
Register map
In this section the memory and register map of the devices covered by this datasheet is
described. For a detailed description of the functionality of the registers, refer to the
reference manual RM0016.
Table 12. I/O port hardware register map
Reset
Address
Block
Register label
Register name
status
0x00 5000
0x00 5001
0x00 5002
0x00 5003
0x00 5004
0x00 5005
0x00 5006
0x00 5007
0x00 5008
0x00 5009
0x00 500A
0x00 500B
0x00 500C
0x00 500D
0x00 500E
0x00 500F
0x00 5010
0x00 5011
0x00 5012
0x00 5013
0x00 5014
0x00 5015
0x00 5016
0x00 5017
0x00 5018
0x00 5019
0x00 501A
0x00 501B
0x00 501C
0x00 501D
PA_ODR
PA_IDR
Port A data output latch register
Port A input pin value register
Port A data direction register
Port A control register 1
0x00
0xXX(1)
0x00
Port A
PA_DDR
PA_CR1
PA_CR2
PB_ODR
PB_IDR
PB_DDR
PB_CR1
PB_CR2
PC_ODR
PB_IDR
PC_DDR
PC_CR1
PC_CR2
PD_ODR
PD_IDR
PD_DDR
PD_CR1
PD_CR2
PE_ODR
PE_IDR
PE_DDR
PE_CR1
PE_CR2
PF_ODR
PF_IDR
PF_DDR
PF_CR1
PF_CR2
0x00
Port A control register 2
0x00
Port B data output latch register
Port B input pin value register
Port B data direction register
Port B control register 1
0x00
0xXX(1)
Port B
Port C
Port D
Port E
Port F
0x00
0x00
Port B control register 2
0x00
Port C data output latch register
Port C input pin value register
Port C data direction register
Port C control register 1
0x00
0xXX(1)
0x00
0x00
Port C control register 2
0x00
Port D data output latch register
Port D input pin value register
Port D data direction register
Port D control register 1
0x00
0xXX(1)
0x00
0x02
Port D control register 2
0x00
Port E data output latch register
Port E input pin value register
Port E data direction register
Port E control register 1
0x00
0xXX(1)
0x00
0x00
Port E control register 2
0x00
Port F data output latch register
Port F input pin value register
Port F data direction register
Port F control register 1
0x00
0xXX(1)
0x00
0x00
Port F control register 2
0x00
30/89
Doc ID 14952 Rev 6
STM8AF61xx, STM8AF62xx
Table 12. I/O port hardware register map (continued)
Memory and register map
Reset
Address
Block
Register label
Register name
status
0x00 501E
0x00 501F
0x00 5020
0x00 5021
0x00 5022
PG_ODR
PG_IDR
PG_DDR
PG_CR1
PG_CR2
Port G data output latch register
Port G input pin value register
Port G data direction register
Port G control register 1
0x00
0xXX(1)
0x00
Port G
0x00
Port G control register 2
0x00
1. Depends on the external circuitry.
Table 13. General hardware register map
Reset
status
Address
Block
Register label
Register name
0x00 505A
0x00 505B
0x00 505C
0x00 505D
FLASH_CR1
FLASH_CR2
Flash control register 1
Flash control register 2
0x00
0x00
0xFF
0x00
FLASH_NCR2 Flash complementary control register 2
FLASH_FPR
Flash protection register
Flash
Flash complementary protection
register
0x00 505E
0x00 505F
FLASH_NFPR
0xFF
0x40
Flash in-application programming
status register
FLASH_IAPSR
0x00 5060 to
0x00 5061
Reserved area (2 bytes)
Flash Program memory unprotection
register
0x00 5062
Flash
Flash
FLASH_PUKR
FLASH_DUKR
0x00
0x00
0x00 5063
0x00 5064
Reserved area (1 byte)
Data EEPROM unprotection register
0x00 5065 to
0x00 509F
Reserved area (59 bytes)
0x00 50A0
0x00 50A1
EXTI_CR1
EXTI_CR2
External interrupt control register 1
External interrupt control register 2
0x00
0x00
ITC
RST
CLK
0x00 50A2 to
0x00 50B2
Reserved area (17 bytes)
Reset status register
0x00 50B3
RST_SR
0xXX(1)
0x00 50B4 to
0x00 50BF
Reserved area (12 bytes)
0x00 50C0
0x00 50C1
0x00 50C2
CLK_ICKR
CLK_ECKR
Internal clock control register
External clock control register
Reserved area (1 byte)
0x01
0x00
Doc ID 14952 Rev 6
31/89
Memory and register map
Table 13. General hardware register map (continued)
STM8AF61xx, STM8AF62xx
Reset
Address
Block
Register label
Register name
status
0x00 50C3
0x00 50C4
0x00 50C5
0x00 50C6
0x00 50C7
0x00 50C8
0x00 50C9
0x00 50CA
0x00 50CB
0x00 50CC
CLK_CMSR
CLK_SWR
Clock master status register
Clock master switch register
Clock switch control register
Clock divider register
0xE1
0xE1
0xXX
0x18
0xFF
0x00
0x00
0xFF
CLK_SWCR
CLK_CKDIVR
CLK_PCKENR1
CLK_CSSR
CLK
Peripheral clock gating register 1
Clock security system register
Configurable clock control register
Peripheral clock gating register 2
Reserved area (1 byte)
CLK_CCOR
CLK_PCKENR2
CLK_HSITRIMR HSI clock calibration trimming register
0x00
CLK
0bXXXX
XXX0
0x00 50CD
CLK_SWIMCCR
SWIM clock control register
0x00 50CE
to 0x0050D0
Reserved area (3 bytes)
0x00 50D1
0x00 50D2
WWDG_CR
WWDG_WR
WWDG control register
WWDR window register
0x7F
0x7F
WWDG
0x0050D3to
0x00 50DF
Reserved area (13 bytes)
0x00 50E0
0x00 50E1
0x00 50E2
IWDG_KR
IWDG_PR
IWDG_RLR
IWDG key register
IWDG prescaler register
IWDG reload register
0xXX(2)
0x00
IWDG
0xFF
0x00 50E3 to
0x00 50EF
Reserved area (13 bytes)
0x00 50F0
0x00 50F1
AWU_CSR1
AWU_APR
AWU control/status register 1
0x00
0x3F
AWU asynchronous prescaler buffer
register
AWU
0x00 50F2
0x00 50F3
AWU_TBR
AWU timebase selection register
BEEP control/status register
0x00
0x1F
BEEP
BEEP_CSR
0x00 50F4 to
0x00 50FF
Reserved area (12 bytes)
32/89
Doc ID 14952 Rev 6
STM8AF61xx, STM8AF62xx
Table 13. General hardware register map (continued)
Memory and register map
Reset
Address
Block
Register label
Register name
status
0x00 5200
0x00 5201
0x00 5202
0x00 5203
0x00 5204
0x00 5205
0x00 5206
0x00 5207
SPI_CR1
SPI_CR2
SPI control register 1
SPI control register 2
SPI interrupt control register
SPI status register
0x00
0x00
0x00
0x02
0x00
0x07
0xFF
0xFF
SPI_ICR
SPI_SR
SPI
SPI_DR
SPI data register
SPI_CRCPR
SPI_RXCRCR
SPI_TXCRCR
SPI CRC polynomial register
SPI Rx CRC register
SPI Tx CRC register
0x00 5208 to
0x00 520F
Reserved area (8 bytes)
0x00 5210
0x00 5211
0x00 5212
0x00 5213
0x00 5214
0x00 5215
0x00 5216
0x00 5217
0x00 5218
0x00 5219
0x00 521A
0x00 521B
0x00 521C
0x00 521D
I2C_CR1
I2C_CR2
I2C control register 1
I2C control register 2
0x00
0x00
0x00
0x00
0x00
I2C_FREQR
I2C_OARL
I2C_OARH
I2C frequency register
I2C own address register low
I2C own address register high
Reserved area (1 byte)
I2C data register
I2C_DR
I2C_SR1
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x02
I2C
I2C status register 1
I2C_SR2
I2C status register 2
I2C_SR3
I2C status register 3
I2C_ITR
I2C interrupt control register
I2C clock control register low
I2C clock control register high
I2C TRISE register
I2C_CCRL
I2C_CCRH
I2C_TRISER
0x00 521E to
0x00 523F
Reserved area (24 bytes)
Doc ID 14952 Rev 6
33/89
Memory and register map
Table 13. General hardware register map (continued)
STM8AF61xx, STM8AF62xx
Reset
Address
Block
Register label
Register name
status
0x00 5240
0x00 5241
0x00 5242
0x00 5243
0x00 5244
0x00 5245
0x00 5246
0x00 5247
0x00 5248
0x00 5249
UART2_SR
UART2_DR
LINUART status register
LINUART data register
0xC0
0xXX
0x00
0x00
0x00
0x00
0x00
0x00
UART2_BRR1
UART2_BRR2
UART2_CR1
UART2_CR2
UART2_CR3
UART2_CR4
LINUART baud rate register 1
LINUART baud rate register 2
LINUART control register 1
LINUART control register 2
LINUART control register 3
LINUART control register 4
Reserved
LINUART
UART2_CR6
LINUART control register 6
0x00
0x00 524A to
0x00 524F
Reserved area (6 bytes)
0x00 5250
0x00 5251
0x00 5252
0x00 5253
0x00 5254
0x00 5255
0x00 5256
0x00 5257
0x00 5258
0x00 5259
0x00 525A
0x00 525B
TIM1_CR1
TIM1_CR2
TIM1_SMCR
TIM1_ETR
TIM1_IER
TIM1 control register 1
TIM1 control register 2
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
TIM1 slave mode control register
TIM1 external trigger register
TIM1 Interrupt enable register
TIM1 status register 1
TIM1_SR1
TIM1_SR2
TIM1_EGR
TIM1 status register 2
TIM1 event generation register
TIM1_CCMR1 TIM1 capture/compare mode register 1
TIM1_CCMR2 TIM1 capture/compare mode register 2
TIM1_CCMR3 TIM1 capture/compare mode register 3
TIM1_CCMR4 TIM1 capture/compare mode register 4
TIM1
TIM1 capture/compare enable register
0x00 525C
0x00 525D
TIM1_CCER1
1
0x00
0x00
TIM1 capture/compare enable register
TIM1_CCER2
2
0x00 525E
0x00 525F
0x00 5260
0x00 5261
0x00 5262
0x00 5263
0x00 5264
TIM1_CNTRH
TIM1_CNTRL
TIM1_PSCRH
TIM1_PSCRL
TIM1_ARRH
TIM1_ARRL
TIM1_RCR
TIM1 counter high
TIM1 counter low
0x00
0x00
0x00
0x00
0xFF
0xFF
0x00
TIM1 prescaler register high
TIM1 prescaler register low
TIM1 auto-reload register high
TIM1 auto-reload register low
TIM1 repetition counter register
34/89
Doc ID 14952 Rev 6
STM8AF61xx, STM8AF62xx
Table 13. General hardware register map (continued)
Memory and register map
Reset
Address
Block
Register label
Register name
status
0x00 5265
0x00 5266
0x00 5267
0x00 5268
0x00 5269
0x00 526A
0x00 526B
0x00 526C
0x00 526D
0x00 526E
0x00 526F
TIM1_CCR1H
TIM1_CCR1L
TIM1_CCR2H
TIM1_CCR2L
TIM1_CCR3H
TIM1_CCR3L
TIM1_CCR4H
TIM1_CCR4L
TIM1_BKR
TIM1 capture/compare register 1 high
TIM1 capture/compare register 1 low
TIM1 capture/compare register 2 high
TIM1 capture/compare register 2 low
TIM1 capture/compare register 3 high
TIM1 capture/compare register 3 low
TIM1 capture/compare register 4 high
TIM1 capture/compare register 4 low
TIM1 break register
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
TIM1
TIM1_DTR
TIM1 dead-time register
TIM1_OISR
TIM1 output idle state register
0x00 5270 to
0x00 52FF
Reserved area (147 bytes)
TIM2 control register 1
0x00 5300
0x00 5301
0x00 5302
0x00 5303
0x00 5304
0x00 5305
0x00 5306
0x00 5307
TIM2_CR1
TIM2_IER
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
TIM2 interrupt enable register
TIM2 status register 1
TIM2_SR1
TIM2_SR2
TIM2 status register 2
TIM2_EGR
TIM2_CCMR1
TIM2_CCMR2
TIM2_CCMR3
TIM2 event generation register
TIM2 capture/compare mode register 1
TIM2 capture/compare mode register 2
TIM2 capture/compare mode register 3
TIM2 capture/compare enable register
1
0x00 5308
0x00 5309
TIM2_CCER1
TIM2_CCER2
0x00
0x00
TIM2 capture/compare enable register
2
TIM2
0x00 530A
0x00 530B
00 530C0x
0x00 530D
0x00 530E
0x00 530F
0x00 5310
0x00 5311
0x00 5312
0x00 5313
TIM2_CNTRH
TIM2_CNTRL
TIM2_PSCR
TIM2_ARRH
TIM2_ARRL
TIM2_CCR1H
TIM2_CCR1L
TIM2_CCR2H
TIM2_CCR2L
TIM2_CCR3H
TIM2 counter high
0x00
0x00
0x00
0xFF
0xFF
0x00
0x00
0x00
0x00
0x00
TIM2 counter low
TIM2 prescaler register
TIM2 auto-reload register high
TIM2 auto-reload register low
TIM2 capture/compare register 1 high
TIM2 capture/compare register 1 low
TIM2 capture/compare reg. 2 high
TIM2 capture/compare register 2 low
TIM2 capture/compare register 3 high
Doc ID 14952 Rev 6
35/89
Memory and register map
Table 13. General hardware register map (continued)
STM8AF61xx, STM8AF62xx
Reset
Address
Block
Register label
Register name
status
0x00 5314
TIM2
TIM2_CCR3L
TIM2 capture/compare register 3 low
Reserved area (11 bytes)
0x00
0x00 5315 to
0x00 531F
0x00 5320
0x00 5321
0x00 5322
0x00 5323
0x00 5324
0x00 5325
0x00 5326
TIM3_CR1
TIM3_IER
TIM3_SR1
TIM3_SR2
TIM3_EGR
TIM3 control register 1
TIM3 interrupt enable register
TIM3 status register 1
0x00
0x00
0x00
0x00
0x00
0x00
0x00
TIM3 status register 2
TIM3 event generation register
TIM3_CCMR1 TIM3 capture/compare mode register 1
TIM3_CCMR2 TIM3 capture/compare mode register 2
TIM3 capture/compare enable register
0x00 5327
TIM3_CCER1
1
0x00
TIM3
0x00 5328
0x00 5329
0x00 532A
0x00 532B
0x00 532C
0x00 532D
0x00 532E
0x00 532F
0x00 5330
TIM3_CNTRH
TIM3_CNTRL
TIM3_PSCR
TIM3_ARRH
TIM3_ARRL
TIM3_CCR1H
TIM3_CCR1L
TIM3_CCR2H
TIM3_CCR2L
TIM3 counter high
0x00
0x00
0x00
0xFF
0xFF
0x00
0x00
0x00
0x00
TIM3 counter low
TIM3 prescaler register
TIM3 auto-reload register high
TIM3 auto-reload register low
TIM3 capture/compare register 1 high
TIM3 capture/compare register 1 low
TIM3 capture/compare register 2 high
TIM3 capture/compare register 2 low
0x00 5331 to
0x00 533F
Reserved area (15 bytes)
0x00 5340
0x00 5341
0x00 5342
0x00 5343
0x00 5344
0x00 5345
0x00 5346
TIM4_CR1
TIM4_IER
TIM4 control register 1
TIM4 interrupt enable register
TIM4 status register
0x00
0x00
0x00
0x00
0x00
0x00
0xFF
TIM4_SR
TIM4
TIM4_EGR
TIM4_CNTR
TIM4_PSCR
TIM4_ARR
TIM4 event generation register
TIM4 counter
TIM4 prescaler register
TIM4 auto-reload register
0x00 5347 to
0x00 53DF
Reserved area (185 bytes)
36/89
Doc ID 14952 Rev 6
STM8AF61xx, STM8AF62xx
Table 13. General hardware register map (continued)
Memory and register map
Reset
Address
Block
Register label
Register name
status
0x00 53E0
0x00 53E1
0x00 53E2
0x00 53E3
0x00 53E4
0x00 53E5
0x00 53E6
0x00 53E7
0x00 53E8
0x00 53E9
0x00 53EA
0x00 53EB
0x00 53EC
0x00 53ED
0x00 53EE
0x00 53EF
0x00 53F0
0x00 53F1
0x00 53F2
0x00 53F3
ADC _DB0RH
ADC _DB0RL
ADC _DB1RH
ADC _DB1RL
ADC _DB2RH
ADC _DB2RL
ADC _DB3RH
ADC _DB3RL
ADC _DB4RH
ADC _DB4RL
ADC _DB5RH
ADC _DB5RL
ADC _DB6RH
ADC _DB6RL
ADC _DB7RH
ADC _DB7RL
ADC _DB8RH
ADC _DB8RL
ADC _DB9RH
ADC _DB9RL
ADC data buffer register 0 high
ADC data buffer register 0 low
ADC data buffer register 1 high
ADC data buffer register 1 low
ADC data buffer register 2 high
ADC data buffer register 2 low
ADC data buffer register 3 high
ADC data buffer register 3 low
ADC data buffer register 4 high
ADC data buffer register 4 low
ADC data buffer register 5 high
ADC data buffer register 5 low
ADC data buffer register 6 high
ADC data buffer register 6 low
ADC data buffer register 7 high
ADC data buffer register 7 low
ADC data buffer register 8 high
ADC data buffer register 8 low
ADC data buffer register 9 high
ADC data buffer register 9 low
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
ADC
0x00 53F4 to
0x00 53FF
Reserved area (12 bytes)
0x00 5400
0x00 5401
0x00 5402
0x00 5403
0x00 5404
0x00 5405
ADC _CSR
ADC_CR1
ADC_CR2
ADC_CR3
ADC_DRH
ADC_DRL
ADC control/status register
ADC configuration register 1
ADC configuration register 2
ADC configuration register 3
ADC data register high
0x00
0x00
0x00
0x00
0xXX
0xXX
ADC data register low
ADC
ADC Schmitt trigger disable register
high
0x00 5406
0x00 5407
ADC_TDRH
ADC_TDRL
0x00
0x00
ADC Schmitt trigger disable register
low
0x00 5408
0x00 5409
0x00 540A
ADC _HTRH
ADC_HTRL
ADC _LTRH
ADC high threshold register high
ADC high threshold register low
ADC low threshold register high
0xFF
0x03
0x00
Doc ID 14952 Rev 6
37/89
Memory and register map
Table 13. General hardware register map (continued)
STM8AF61xx, STM8AF62xx
Reset
Address
Block
Register label
Register name
status
0x00 540B
0x00 540C
0x00 540D
0x00 540E
0x00 540F
ADC_LTRL
ADC _AWSRH
ADC_AWSRL
ADC _AWCRH
ADC _AWCRH
ADC low threshold register low
ADC watchdog status register high
ADC watchdog status register low
ADC watchdog control register high
ADC watchdog control register low
0x00
0x00
0x00
0x00
0x00
ADC
0x00 5410 to
0x00 541F
Reserved area (16 bytes)
1. Depends on the previous reset source.
2. Write only register.
Table 14. CPU/SWIM/debug module/interrupt controller registers
Reset
status
Address
Block
Register label
Register name
0x00 7F00
0x00 7F01
0x00 7F02
0x00 7F03
0x00 7F04
0x00 7F05
0x00 7F06
0x00 7F07
0x00 7F08
0x00 7F09
0x00 7F0A
A
Accumulator
Program counter extended
Program counter high
Program counter low
X index register high
X index register low
Y index register high
Y index register low
Stack pointer high
0x00
0x00
0x80
0x00
0x00
0x00
0x00
0x00
0x17(2)
0xFF
0x28
PCE
PCH
PCL
XH
CPU(1)
XL
YH
YL
SPH
SPL
CC
Stack pointer low
Condition code register
0x00 7F0B to
0x00 7F5F
Reserved area (85 bytes)
0x00 7F60
0x00 7F70
0x00 7F71
0x00 7F72
0x00 7F73
0x00 7F74
0x00 7F75
CPU
ITC
CFG_GCR
ITC_SPR1
ITC_SPR2
ITC_SPR3
ITC_SPR4
ITC_SPR5
ITC_SPR6
Global configuration register
Interrupt software priority register 1
Interrupt software priority register 2
Interrupt software priority register 3
Interrupt software priority register 4
Interrupt software priority register 5
Interrupt software priority register 6
0x00
0xFF
0xFF
0xFF
0xFF
0xFF
0xFF
0x00 7F76 to
0x00 7F79
Reserved area (4 bytes)
0x00 7F80
SWIM
SWIM_CSR
SWIM control status register
0x00
38/89
Doc ID 14952 Rev 6
STM8AF61xx, STM8AF62xx
Memory and register map
Table 14. CPU/SWIM/debug module/interrupt controller registers (continued)
Reset
status
Address
Block
Register label
Register name
0x00 7F81 to
0x00 7F8F
Reserved area (15 bytes)
0x00 7F90
0x00 7F91
0x00 7F92
0x00 7F93
0x00 7F94
0x00 7F95
0x00 7F96
0x00 7F97
0x00 7F98
0x00 7F99
0x00 7F9A
DM_BK1RE
DM_BK1RH
DM_BK1RL
DM_BK2RE
DM_BK2RH
DM_BK2RL
DM_CR1
DM breakpoint 1 register extended byte
DM breakpoint 1 register high byte
DM breakpoint 1 register low byte
DM breakpoint 2 register extended byte
DM breakpoint 2 register high byte
DM breakpoint 2 register low byte
DM debug module control register 1
DM debug module control register 2
DM debug module control/status register 1
DM debug module control/status register 2
DM enable function register
0xFF
0xFF
0xFF
0xFF
0xFF
0xFF
0x00
0x00
0x10
0x00
0xFF
DM
DM_CR2
DM_CSR1
DM_CSR2
DM_ENFCTR
0x00 7F9B to
0x00 7F9F
Reserved area (5 bytes)
1. Accessible by debug module only
2. Product dependent value, see Figure 5: Register and memory map of STM8A products.
Table 15. Temporary memory unprotection registers
Reset
status
Address
Block
Register label
Register name
0x00 5800
0x00 5801
0x00 5802
0x00 5803
0x00 5804
0x00 5805
0x00 5806
0x00 5807
TMU_K1
TMU_K2
TMU_K3
TMU_K4
TMU_K5
TMU_K6
TMU_K7
TMU_K8
Temporary memory unprotection key register 1
Temporary memory unprotection key register 2
Temporary memory unprotection key register 3
Temporary memory unprotection key register 4
Temporary memory unprotection key register 5
Temporary memory unprotection key register 6
Temporary memory unprotection key register 7
Temporary memory unprotection key register 8
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
TMU
Temporary memory unprotection control and status
register
0x00 5808
TMU_CSR
0x00
Doc ID 14952 Rev 6
39/89
Interrupt table
STM8AF61xx, STM8AF62xx
8
Interrupt table
Table 16. STM8A interrupt table
Source
Interruptvector Wakeup
Priority
Description
Comments
block
address
from Halt
—
—
0
Reset
Reset
0x00 6000
0x00 8004
0x00 8008
0x00 800C
Yes
—
Reset vector in ROM
TRAP
TLI
SW interrupt
—
—
—
External top level interrupt
Auto-wakeup from Halt
—
1
AWU
Yes
Clock
controller
2
Main clock controller
0x00 8010
—
—
3
4
MISC
Ext interrupt E0
Ext interrupt E1
Ext interrupt E2
Ext interrupt E3
Ext interrupt E4
—
0x00 8014
0x00 8018
0x00 801C
0x00 8020
0x00 8024
—
Yes
Yes
Yes
Yes
Yes
—
Port A interrupts
Port B interrupts
Port C interrupts
Port D interrupts
Port E interrupts
—
MISC
5
MISC
6
MISC
7
MISC
8
Reserved(1)
Reserved(1)
SPI
9
—
—
—
—
10
End of transfer
0x00 8030
Yes
—
Update/overflow/
trigger/break
11
Timer 1
0x00 8034
—
—
12
13
14
15
16
17
18
19
20
21
22
23
Timer 1
Timer 2
Timer 2
Timer 3
Timer 3
Reserved(1)
Reserved(1)
I2C
Capture/compare
Update/overflow
Capture/compare
Update/overflow
Capture/compare
—
0x00 8038
0x00 803C
0x00 8040
0x00 8044
0x00 8048
—
—
—
—
—
—
—
—
Yes
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
I2C interrupts
Tx complete/error
Receive data full reg.
End of conversion
Update/overflow
0x00 8054
0x00 8058
0x00 805C
0x00 8060
0x00 8064
LINUART
LINUART
ADC
Timer 4
End of Programming/
24
EEPROM
0x00 8068
—
—
Write in not allowed area
1. All reserved and unused interrupts must be initialized with ‘IRET’ for robust programming.
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STM8AF61xx, STM8AF62xx
Option bytes
9
Option bytes
Option bytes contain configurations for device hardware features as well as the memory
protection of the device. They are stored in a dedicated block of the memory. Each option
byte has to be stored twice, for redundancy, in a regular form (OPTx) and a complemented
one (NOPTx), except for the ROP (read-out protection) option byte and option bytes 8 to 16.
Option bytes can be modified in ICP mode (via SWIM) by accessing the EEPROM address
shown in Table 17: Option bytes below.
Option bytes can also be modified ‘on the fly’ by the application in IAP mode, except the
ROP and UBC options that can only be toggled in ICP mode (via SWIM).
Refer to the STM8 Flash programming manual (PM0051) and STM8 SWIM communication
protocol and debug module user manual (UM0470) for information on SWIM programming
procedures.
Table 17. Option bytes
Option bits
Factory
default
setting
Option
name
Option
byte no.
Addr.
7
6
5
4
3
2
1
0
Read-out
protection OPT0
(ROP)
0x00
4800
ROP[7:0]
0x00
0x00
4801
OPT1
Reserved
Reserved
UBC[5:0]
NUBC[5:0]
0x00
0xFF
0x00
0xFF
0x00
0xFF
0x00
0xFF
0x00
0xFF
User boot
code
(UBC)
0x00
4802
NOPT1
0x00
4803
Alternate
function
remapping
(AFR)
OPT2
NOPT2
OPT3
AFR7 AFR6 AFR5
NAFR NAFR NAFR
AFR4
AFR3
AFR2
AFR1
AFR0
0x00
4804
NAFR
4
NAFR
3
NAFR
2
NAFR NAFR
1
7
6
5
0
0x00
4805
16MHZ
TRIM0
LSI
_EN
IWDG WWDG WWDG
_HW _HW _HALT
Reserved
Watchdog
option
0x00
4806
N16MHZ NLSI
NIWDG NWWD NWWG
_HW G_HW _HALT
NOPT3
OPT4
Reserved
TRIM0
_EN
0x00
4807
EXT
CLK
CKAWU PRS
SEL C1
PRS
C0
Reserved
Reserved
Clock
option
0x00
4808
NEXT NCKAW NPR
CLK USEL SC1
NPR
SC0
NOPT4
OPT5
0x00
4809
HSECNT[7:0]
HSE clock
startup
0x00
480A
NOPT5
NHSECNT[7:0]
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Option bytes
STM8AF61xx, STM8AF62xx
Table 17. Option bytes (continued)
Option bits
Factory
default
setting
Option
name
Option
byte no.
Addr.
7
6
5
4
3
2
1
0
0x00
480B
OPT6
NOPT6
OPT7
TMU[3:0]
0x00
TMU
0x00
480C
NTMU[3:0]
0xFF
0x00
0xFF
0x00
480D
WAIT
STATE
Reserved
Flash wait
states
0x00
480E
NWAIT
STATE
NOPT7
Reserved
0x00
480F
Reserved
0x00
4810
OPT8
OPT9
TMU_KEY 1 [7:0]
TMU_KEY 2 [7:0]
TMU_KEY 3 [7:0]
TMU_KEY 4 [7:0]
TMU_KEY 5 [7:0]
TMU_KEY 6 [7:0]
TMU_KEY 7 [7:0]
TMU_KEY 8 [7:0]
TMU_MAXATT [7:0]
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0xC7
0x00
4811
0x00
4812
OPT10
OPT11
OPT12
OPT13
OPT14
OPT15
OPT16
0x00
4813
0x00
4814
TMU
0x00
4815
0x00
4816
0x00
4817
0x00
4818
0x00
4819
to
Reserved
487D
0x00
487E
OPT17
BL [7:0]
0x00
0xFF
Boot-
loader(1)
0x00
487F
NOPT17
NBL[7:0]
1. This option consists of two bytes that must have a complementary value in order to be valid. If the option is invalid, it has no
effect on EMC reset.
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STM8AF61xx, STM8AF62xx
Option bytes
Table 18. Option byte description
Option byte no.
Description
ROP[7:0]: Memory readout protection (ROP)
0xAA: Enable readout protection (write access via SWIM protocol)
Note: Refer to the STM8S and STM8A microcontroller families reference
manual (RM0016) section on Flash/EEPROM memory readout
protection for details.
OPT0
UBC[5:0]: User boot code area
0x00: No UBC, no write-protection
0x01: Page 0 to 1 defined as UBC, memory write-protected
0x02: Page 0 to 3 defined as UBC, memory write-protected
0x03 to 0x3F: Pages 4 to 63 defined as UBC, memory write-protected
Note: Refer to the STM8S and STM8A microcontroller families reference
manual (RM0016) section on Flash/EEPROM write protection for more
details.
OPT1
AFR7: Alternate function remapping option 7
0: Port D4 alternate function = TIM2_CH1
1: Port D4 alternate function = BEEP
AFR6: Alternate function remapping option 6
0: Port B5 alternate function = AIN5, port B4 alternate function = AIN4
1: Port B5 alternate function = I2C_SDA, port B4 alternate function =
I2C_SCL.
AFR5: Alternate function remapping option 5
0: Port B3 alternate function = AIN3, port B2 alternate function = AIN2,
port B1 alternate function = AIN1, port B0 alternate function = AIN0.
1: Port B3 alternate function = TIM1_ETR, port B2 alternate function =
TIM1_CH3N, port B1 alternate function = TIM1_CH2N, port B0 alternate
function = TIM1_CH1N.
AFR4: Alternate function remapping option 4
Reserved, bit must be kept at "0"
OPT2
AFR3: Alternate function remapping option 3
0: Port D0 alternate function = TIM3_CH2
1: Port D0 alternate function = TIM1_BKIN
AFR2: Alternate function remapping option 2
0: Port D0 alternate function = TIM3_CH2
1: Port D0 alternate function = CLK_CCO
Note: AFR2 option has priority over AFR3 if both are activated
AFR1: Alternate function remapping option 1
0: Port A3 alternate function = TIM2_CH3, port D2 alternate function
TIM3_CH1.
1: Port A3 alternate function = TIM3_CH1, port D2 alternate function
TIM2_CH3.
AFR0: Alternate function remapping option 0
0: Port D3 alternate function = TIM2_CH2
1: Port D3 alternate function = ADC_ETR
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Option bytes
Table 18. Option byte description (continued)
STM8AF61xx, STM8AF62xx
Option byte no.
Description
HSITRIM: Trimming option for 16 MHz internal RC oscillator
0: 3-bit on-the-fly trimming (compatible with devices based on the 128K
silicon)
1: 4-bit on-the-fly trimming
LSI_EN: Low speed internal clock enable
0: LSI clock is not available as CPU clock source
1: LSI clock is available as CPU clock source
IWDG_HW: Independent watchdog
OPT3
0: IWDG independent watchdog activated by software
1: IWDG independent watchdog activated by hardware
WWDG_HW: Window watchdog activation
0: WWDG window watchdog activated by software
1: WWDG window watchdog activated by hardware
WWDG_HALT: Window watchdog reset on Halt
0: No reset generated on Halt if WWDG active
1: Reset generated on Halt if WWDG active
EXTCLK: External clock selection
0: External crystal connected to OSCIN/OSCOUT
1: External clock signal on OSCIN
CKAWUSEL: Auto-wakeup unit/clock
0: LSI clock source selected for AWU
1: HSE clock with prescaler selected as clock source for AWU
OPT4
PRSC[1:0]: AWU clock prescaler
00: Reserved
01: 16 MHz to 128 kHz prescaler
10: 8 MHz to 128 kHz prescaler
11: 4 MHz to 128 kHz prescaler
HSECNT[7:0]: HSE crystal oscillator stabilization time
This configures the stabilization time to 0.5, 8, 128, and 2048 HSE
cycles with corresponding option byte values of 0xE1, 0xD2, 0xB4, and
0x00.
OPT5
OPT6
TMU[3:0]: Enable temporary memory unprotection
0101: TMU disabled (permanent ROP).
Any other value: TMU enabled.
OPT7
OPT8
Reserved
TMU_KEY 1 [7:0]: Temporary unprotection key 0
Temporary unprotection key: Must be different from 0x00 or 0xFF
TMU_KEY 2 [7:0]: Temporary unprotection key 1
OPT9
OPT10
OPT11
Temporary unprotection key: Must be different from 0x00 or 0xFF
TMU_KEY 3 [7:0]: Temporary unprotection key 2
Temporary unprotection key: Must be different from 0x00 or 0xFF
TMU_KEY 4 [7:0]: Temporary unprotection key 3
Temporary unprotection key: Must be different from 0x00 or 0xFF
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STM8AF61xx, STM8AF62xx
Table 18. Option byte description (continued)
Option bytes
Option byte no.
Description
TMU_KEY 5 [7:0]: Temporary unprotection key 4
OPT12
Temporary unprotection key: Must be different from 0x00 or 0xFF
TMU_KEY 6 [7:0]: Temporary unprotection key 5
OPT13
OPT14
OPT15
Temporary unprotection key: Must be different from 0x00 or 0xFF
TMU_KEY 7 [7:0]: Temporary unprotection key 6
Temporary unprotection key: Must be different from 0x00 or 0xFF
TMU_KEY 8 [7:0]: Temporary unprotection key 7
Temporary unprotection key: Must be different from 0x00 or 0xFF
TMU_MAXATT [7:0]: TMU access failure counter
TMU_MAXATT can be initialized with the desired value only if TMU is
disabled (TMU[3:0]=0101 in OPT6 option byte).
OPT16
OPT17
When TMU is enabled, any attempt to temporary remove the readout
protection by using wrong key values increments the counter.
When the option byte value reaches 0x08, the Flash memory and data
EEPROM are erased.
BL [7:0]: Bootloader enable
If this option byte is set to 0x55 (complementary value 0xAA) the
bootloader program is activated also in case of a programmed code
memory
(for more details, see the bootloader user manual, UM0560).
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Electrical characteristics
STM8AF61xx, STM8AF62xx
10
Electrical characteristics
10.1
Parameter conditions
Unless otherwise specified, all voltages are referred to V
.
SS
10.1.1
Minimum and maximum values
Unless otherwise specified the minimum and maximum values are guaranteed in the worst
conditions of ambient temperature, supply voltage and frequencies by tests in production on
100 % of the devices with an ambient temperature at T = -40 °C, T = 25 °C, and T =
A
A
A
T
(given by the selected temperature range).
Amax
Data based on characterization results, design simulation and/or technology characteristics
are indicated in the table footnotes and are not tested in production.
10.1.2
Typical values
Unless otherwise specified, typical data are based on T = 25 °C, V = 5.0 V. They are
A
DD
given only as design guidelines and are not tested.
Typical ADC accuracy values are determined by characterization of a batch of samples from
a standard diffusion lot over the full temperature range.
10.1.3
10.1.4
Typical curves
Unless otherwise specified, all typical curves are given only as design guidelines and are
not tested.
Loading capacitor
The loading conditions used for pin parameter measurement are shown in Figure 6.
Figure 6.
Pin loading conditions
STM8A pin
50 pF
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STM8AF61xx, STM8AF62xx
Electrical characteristics
10.1.5
Pin input voltage
The input voltage measurement on a pin of the device is described in Figure 7.
Figure 7. Pin input voltage
STM8A pin
V
IN
10.2
Absolute maximum ratings
Stresses above those listed as ‘absolute maximum ratings’ may cause permanent damage
to the device. This is a stress rating only and functional operation of the device under these
conditions is not implied. Exposure to maximum rating conditions for extended periods may
affect device reliability.
Table 19. Voltage characteristics
Symbol
Ratings
Min
Max
6.5
Unit
(1)
V
DDx - VSS Supply voltage (including VDDA and VDDIO
)
-0.3
V
Input voltage on true open drain pins (PE1, PE2)(2)
6.5
VSS - 0.3
VIN
V
Input voltage on any other pin(2)
VSS - 0.3
VDD + 0.3
|VDDx - VDD
|
Variations between different power pins
Variations between all the different ground pins
-
-
50
50
mV
|VSSx - VSS
|
see Absolute maximum ratings
(electrical sensitivity) on
page 72
VESD
Electrostatic discharge voltage
1. All power (VDD, VDDIO, VDDA) and ground (VSS, VSSIO, VSSA) pins must always be connected to the
external power supply
2. IINJ(PIN) must never be exceeded. This is implicitly insured if VIN maximum is respected. If VIN maximum
cannot be respected, the injection current must be limited externally to the IINJ(PIN) value. A positive
injection is induced by VIN > VDD while a negative injection is induced by VIN < VSS. For true open-drain
pads, there is no positive injection current, and the corresponding VIN maximum must always be respected
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Electrical characteristics
STM8AF61xx, STM8AF62xx
Table 20. Current characteristics
Symbol
IVDDIO
IVSSIO
Ratings
Max.
Unit
Total current into VDDIO power lines (source)(1)(2)(3)
Total current out of VSS IO ground lines (sink)(1)(2)(3)
Output current sunk by any I/O and control pin
Output current source by any I/Os and control pin
Injected current on any pin
100
100
20
IIO
mA
-20
10
(4)
IINJ(PIN)
IINJ(TOT)
Sum of injected currents
50
1. All power (VDD, VDDIO, VDDA) and ground (VSS, VSSIO, VSSA) pins must always be connected to the
external supply.
2. The total limit applies to the sum of operation and injected currents.
3. VDDIO includes the sum of the positive injection currents. VSSIO includes the sum of the negative injection
currents.
4. This condition is implicitly insured if VIN maximum is respected. If VIN maximum cannot be respected, the
injection current must be limited externally to the IINJ(PIN) value. A positive injection is induced by VIN > VDD
while a negative injection is induced by VIN < VSS. For true open-drain pads, there is no positive injection
current allowed and the corresponding VIN maximum must always be respected.
Table 21. Thermal characteristics
Symbol
Ratings
Value
Unit
TSTG
TJ
Storage temperature range
−65 to 150
°C
Maximum junction temperature
160
(1)
Table 22. Operating lifetime
Symbol
Ratings
Value
Unit
−40 to 125 °C
−40 to 150 °C
Grade 1
Grade 0
OLF
Conforming to AEC-Q100 rev G
1. For detailed mission profile analysis, please contact your local ST Sales Office.
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Doc ID 14952 Rev 6
STM8AF61xx, STM8AF62xx
Electrical characteristics
10.3
Operating conditions
Table 23. General operating conditions
Symbol
fCPU
Parameter
Conditions
Min
Max
Unit
Internal CPU clock frequency
Standard operating voltage
TA = -40 °C to 150 °C
-
0
16
MHz
V
VDD/VDDIO
3.0
5.5
CEXT: capacitance of external
capacitor
470
3300
nF
(1)
VCAP
ESR of external capacitor
ESL of external capacitor
-
-
-
-
-
0.3
15
Ω
at 1 MHz(2)
nH
LQFP32
VFQFPN32
LQFP48
Suffix A
85
Power dissipation (all
temperature ranges)
PD
200
88
mW
85
Suffix B
105
125
150
90
TA
Ambient temperature
Suffix C
Suffix D(3)
-40
°C
Suffix A
Suffix B
110
130
155
TJ
Junction temperature range
Suffix C
Suffix D(3)
1. Care should be taken when selecting the capacitor, due to its tolerance, as well as the parameter
dependency on temperature, DC bias and frequency in addition to other factors. The parameter maximum
value must be respected for the full application range.
2. This frequency of 1 MHz as a condition for VCAP parameters is given by design of internal regulator.
3. Available on STM8AF62xx devices only.
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Electrical characteristics
Figure 8.
STM8AF61xx, STM8AF62xx
f
versus V
CPUmax
DD
fCPU [MHz]
24
Functionality
not guaranteed
in this area
16
12
8
Functionality guaranteed
@ TA -40 to 150 °C
4
0
3.0
4.0
5.0
5.5
Supply voltage [V]
1. This figure is valid only for STM8AF62xx devices.
Table 24. Operating conditions at power-up/power-down
Symbol
Parameter
Conditions
Min
Max
Unit
Typ
2(1)
VDD rise time rate
-
-
∞
tVDD
µs/V
2(1)
VDD fall time rate
-
-
∞
-
Reset release delay
Reset generation delay
VDD rising
-
-
3
3
ms
µs
tTEMP
V
DD falling
-
Power-on reset
threshold(2)
VIT+
-
2.65
2.58
-
2.8
2.95
2.88
-
V
Brown-out reset
threshold
VIT-
-
-
2.73
70(1)
Brown-out reset
hysteresis
VHYS(BOR)
mV
1. Guaranteed by design, not tested in production
2. If VDD is below 3 V, the code execution is guaranteed above the VIT- and VIT+ thresholds. RAM content is
kept. The EEPROM programming sequence must not be initiated.
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Electrical characteristics
10.3.1
VCAP external capacitor
Stabilization for the main regulator is achieved connecting an external capacitor C
to the
EXT
V
pin. C
is specified in Table 23. Care should be taken to limit the series inductance
CAP
EXT
to less than 15 nH.
Figure 9. External capacitor C
EXT
ESR
C
ESL
Rleak
1. Legend: ESR is the equivalent series resistance and ESL is the equivalent inductance.
10.3.2
Supply current characteristics
The current consumption is measured as described in Figure 6 on page 46 and Figure 7 on
page 47.
If not explicitly stated, general conditions of temperature and voltage apply.
Table 25. Total current consumption in Run, Wait and Slow mode.
General conditions for V apply, T = −40 to 150 °C
DD
A
Symbol
Parameter
Conditions
Typ
7.4
4.0
Max
14
Unit
fCPU = 16 MHz
fCPU = 8 MHz
All peripherals
clocked, code
7.4(2)
Supply
current in
Run mode
executed from Flash
program memory,
HSE external clock
(without resonator)
(1)
IDD(RUN)
4.1(2)
2.5
fCPU = 4 MHz
fCPU = 2 MHz
fCPU = 16 MHz
fCPU = 8 MHz
2.4
1.5
3.7
2.2
5.0
All peripherals
clocked, code
3.0(2)
Supply
current in
Run mode
executed from RAM
and EEPROM, HSE
external clock
(1)
IDD(RUN)
2.0(2)
1.5
fCPU = 4 MHz
fCPU = 2 MHz
fCPU = 16 MHz
fCPU = 8 MHz
1.4
1.0
(without resonator)
mA
1.65
1.15
2.5
1.9(2)
Supply
current in
Wait mode
CPU stopped, all
peripherals off, HSE
external clock
(1)
IDD(WFI)
1.6(2)
1.5
fCPU = 4 MHz
fCPU = 2 MHz
0.90
0.80
Ext. clock 16 MHz
fCPU = 125 kHz
fCPU scaled down,
all peripherals off,
code executed from
RAM
1.50
1.50
1.95
Supply
current in
Slow mode
(1)
IDD(SLOW)
LSI internal RC
fCPU = 128 kHz
1.80(2)
1. The current due to I/O utilization is not taken into account in these values.
2. Values not tested in production. Design guidelines only.
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Electrical characteristics
STM8AF61xx, STM8AF62xx
Table 26. Total current consumption in Halt and Active-halt modes.
General conditions for V apply, T = −40 to 55 °C
DD
A
Conditions
Main
Clock source and
Symbol
Parameter
Typ
Max
Unit
voltage
regulator
(MVR)(1)
Flash
specific
temperature
condition
mode(2)
35(3)
25
Clocks stopped
5
5
Power-
down
IDD(H)
Supply current in Halt mode
Off
On
Off
Clocks stopped,
TA = 25 °C
Ext. clock 16 MHz
fMASTER = 125 kHz
900(3)
770
Supply current in Active-halt
mode with regulator on
Power-
down
µA
230(3)
42(3)
LSI clock 128 kHz
LSI clock 128 kHz
150
25
IDD(AH)
Supply current in Active-halt
mode with regulator off
Power-
down
LSI clock 128 kHz,
TA = 25 °C
25
10
50
30
Wakeup time from Active-
halt mode with regulator on
30(3)
80(3)
On
Off
Operating
mode
tWU(AH)
TA = -40 to 150 °C
µs
Wakeup time from Active-
halt mode with regulator off
1. Configured by the REGAH bit in the CLK_ICKR register.
2. Configured by the AHALT bit in the FLASH_CR1 register.
3. Data based on characterization results. Not tested in production.
Current consumption for on-chip peripherals
Table 27. Oscillator current consumption
Max(1)
Symbol
Parameter
Conditions
Typ
Unit
Quartz or
fOSC = 24 MHz
fOSC = 16 MHz
1
2.0(3)
-
ceramic
resonator,
CL = 33 pF
VDD = 5 V
HSE oscillator current
consumption(2)
0.6
IDD(OSC)
f
OSC = 8 MHz
0.57
-
mA
Quartz or
ceramic
resonator,
CL = 33 pF
VDD = 3.3 V
f
OSC = 24 MHz
0.5
1.0(3)
-
HSE oscillator current
consumption(2)
fOSC = 16 MHz
fOSC = 8 MHz
0.25
IDD(OSC)
0.18
-
1. During startup, the oscillator current consumption may reach 6 mA.
2. The supply current of the oscillator can be further optimized by selecting a high quality resonator with small
Rm value. Refer to crystal manufacturer for more details
3. Informative data.
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STM8AF61xx, STM8AF62xx
Electrical characteristics
Table 28. Programming current consumption
Symbol
Parameter
Conditions
Typ
Max
Unit
VDD = 5 V, -40 °C to 150 °C,
erasing and programming data
or Flash program memory
IDD(PROG) Programming current
1.0
1.7
mA
(1)
Table 29. Typical peripheral current consumption V = 5.0 V
DD
Typ. f
=
Typ. f
=
master
master
Symbol
Parameter
Unit
2 MHz
16 MHz
IDD(TIM1)
TIM1 supply current(2)
TIM2 supply current (2)
TIM3 supply current(2)
TIM4 supply current(2)
LINUART supply current(2)
SPI supply current(2)
I2C supply current(2)
0.03
0.02
0.01
0.004
0.03
0.01
0.02
0.003
0.22
0.23
0.12
0.1
IDD(TIM2)
IDD(TIM3)
IDD(TIM4)
IDD(LINUART)
IDD(SPI)
0.03
0.11
0.04
0.06
0.02
1
mA
IDD(I C)
2
IDD(AWU)
AWU supply current(2)
IDD(TOT_DIG)
All digital peripherals on
ADC supply current when
converting(3)
IDD(ADC)
0.93
0.95
1. Typical values not tested in production. Since the peripherals are powered by an internally regulated,
constant digital supply voltage, the values are similar in the full supply voltage range.
2. Data based on a differential IDD measurement between no peripheral clocked and a single active
peripheral. This measurement does not include the pad toggling consumption.
3. Data based on a differential IDD measurement between reset configuration and continuous A/D
conversions.
Current consumption curves
Figure 10 to Figure 15 show typical current consumption measured with code executing in
RAM.
Figure 10. Typ. I
vs. V
Figure 11. Typ. I
vs. f
DD(RUN)HSE
DD
DD(RUN)HSE CPU
@f
= 16 MHz, peripheral = on
@ V = 5.0 V, peripheral = on
CPU
DD
10
10
25°C
85°C
12 5°C
25°C
85°C
12 5°C
9
8
9
8
7
7
6
6
5
5
4
3
4
3
2
1
2
1
0
0
2.5
3
3.5
4
4.5
5
5.5
6
0
5
10
15
20
25
30
VDD [V]
fcpu [MHz]
Doc ID 14952 Rev 6
53/89
Electrical characteristics
STM8AF61xx, STM8AF62xx
Figure 12. Typ. I
vs. V
Figure 13. Typ. I
vs. V
DD(RUN)HSI
DD
DD(WFI)HSE DD
@ f
= 16 MHz, peripheral = off
@ f
= 16 MHz, peripheral = on
CPU
CPU
6
5
4
3
2
1
0
4
3
2
1
0
25°C
85°C
125°C
25°C
85°C
125°C
2.5
3.5
4.5
5.5
6.5
2.5
3.5
4.5
5.5
6.5
VDD [V]
VDD [V]
Figure 14. Typ. I
vs. f
Figure 15. Typ. I
vs. V
DD(WFI)HSE
CPU
DD(WFI)HSI DD
@ V = 5.0 V, peripheral = on
@ f
= 16 MHz, peripheral = off
DD
CPU
2.5
2
6
5
4
1.5
3
2
1
0
1
0.5
0
25°C
85°C
12 5°C
25°C
85°C
12 5°C
2.5
3
3.5
4
4.5
5
5.5
6
0
5
10
15
20
25
30
VDD [V]
fcpu [MHz]
10.3.3
External clock sources and timing characteristics
HSE user external clock
Subject to general operating conditions for V and T .
DD
A
Table 30. HSE user external clock characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
User external clock source
frequency
TA is -40 to
150 °C
fHSE_ext
VHSEdHL
VHSEH
0(1)
-
-
-
16
-
MHz
Comparator hysteresis
-
-
0.1 x VDD
0.7 x VDD
OSCIN input pin high level
voltage
VDD
V
OSCIN input pin low level
voltage
VHSEL
-
VSS
-1
-
-
0.3 x VDD
+1
OSCIN input leakage
current
ILEAK_HSE
VSS < VIN < VDD
µA
1. In CSS is used, the external clock must have a frequency above 500 kHz.
54/89
Doc ID 14952 Rev 6
STM8AF61xx, STM8AF62xx
Figure 16. HSE external clock source
Electrical characteristics
V
V
HSEH
HSEL
f
HSE
External clock
source
OSCIN
STM8A
HSE crystal/ceramic resonator oscillator
The HSE clock can be supplied using a crystal/ceramic resonator oscillator of up to 16 MHz.
All the information given in this paragraph is based on characterization results with specified
typical external components. In the application, the resonator and the load capacitors have
to be placed as close as possible to the oscillator pins in order to minimize output distortion
and startup stabilization time. Refer to the crystal resonator manufacturer for more details
(frequency, package, accuracy...).
Table 31. HSE oscillator characteristics
Symbol Parameter
RF Feedback resistor
L1/CL2
gm
Conditions
Min
Typ
Max
Unit
-
-
-
-
-
220
-
20
-
kΩ
pF
(1)
C
Recommended load capacitance
Oscillator transconductance
-
-
5
mA/V
VDD is
stabilized
(2)
tSU(HSE)
Startup time
-
2.8
-
ms
1. The oscillator needs two load capacitors, CL1 and CL2, to act as load for the crystal. The total load capacitance (Cload) is
(CL1 * CL2)/(CL1 + CL2). If CL1 = CL2, Cload = CL1 / 2. Some oscillators have built-in load capacitors, CL1 and CL2
.
2. This value is the startup time, measured from the moment it is enabled (by software) until a stabilized 16 MHz oscillation is
reached. It can vary with the crystal type that is used.
Figure 17. HSE oscillator circuit diagram
f
to core
HSE
R
m
R
F
C
O
L
m
C
L1
OSCIN
C
m
g
m
Resonator
Current control
Resonator
STM8A
OSCOUT
C
L2
Doc ID 14952 Rev 6
55/89
Electrical characteristics
STM8AF61xx, STM8AF62xx
HSE oscillator critical gm formula
The crystal characteristics have to be checked with the following formula:
g
m » gmcrit
where g
can be calculated with the crystal parameters as follows:
mcrit
f
gmcrit = (2 × Π × HSE)2 × Rm(2Co + C)2
R : Notional resistance (see crystal specification)
m
L : Notional inductance (see crystal specification)
m
C : Notional capacitance (see crystal specification)
m
Co: Shunt capacitance (see crystal specification)
C
= C = C: Grounded external capacitance
L1
L2
10.3.4
Internal clock sources and timing characteristics
Subject to general operating conditions for V and T .
DD
A
High speed internal RC oscillator (HSI)
Table 32. HSI oscillator characteristics
Symbol
Parameter
Frequency
Conditions
Min
Typ
Max
Unit
fHSI
-
16
-
-
MHz
Trimmed by the application
for any VDD and TA
conditions
-1(1)
1(1)
HSI oscillator user
trimming accuracy
-0.5(1)
-
0.5(1)
ACCHS
%
HSI oscillator accuracy
(factory calibrated)
VDD = 3.0 V ≤ VDD ≤ 5.5 V,
-40 °C ≤ TA ≤ 150 °C
-5
-
-
-
5
tsu(HSI) HSI oscillator wakeup time
2(2)
µs
1. Depending on option byte setting (OPT3 and NOPT3)
2. Guaranteed by characterization, not tested in production
56/89
Doc ID 14952 Rev 6
STM8AF61xx, STM8AF62xx
Figure 18. Typical HSI frequency vs V
Electrical characteristics
DD
3%
2%
-40°C
25°C
85°C
125°C
1%
0%
-1%
-2%
-3%
2.5
3
3.5
4
4.5
5
5.5
6
VDD [V]
Low speed internal RC oscillator (LSI)
Subject to general operating conditions for V and T .
DD
A
Table 33. LSI oscillator characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
fLSI
Frequency
LSI oscillator wakeup time
-
-
112
-
128
-
144
7(1)
kHz
µs
tsu(LSI)
1. Data based on characterization results, not tested in production.
Figure 19. Typical LSI frequency vs V
DD
3%
2%
1%
25°C
0%
-1%
-2%
-3%
2.5
3
3.5
4
4.5
5
5.5
6
VDD [V]
Doc ID 14952 Rev 6
57/89
Electrical characteristics
STM8AF61xx, STM8AF62xx
10.3.5
Memory characteristics
Flash program memory/data EEPROM memory
General conditions: TA = -40 to 150 °C.
Table 34. Flash program memory/data EEPROM memory
Symbol
Parameter
Conditions
Min Typ Max
Unit
Operating voltage
(all modes, execution/write/erase)
fCPU is 0 to 16 MHz
with 0 ws
VDD
3.0
2.6
-
-
5.5
5.5
V
Operating voltage
(code execution)
fCPU is 0 to 16 MHz
with 0 ws
VDD
Standard programming time
(including erase) for byte/word/block
(1 byte/4 bytes/128 bytes)
-
-
6
6.6
tprog
ms
ms
Fast programming time for 1 block
(128 bytes)
-
-
-
-
3
3
3.3
3.3
terase
Erase time for 1 block (128 bytes)
Table 35. Flash program memory
Symbol
Parameter
Condition
Min
Max
Unit
TWE
Temperature for writing and erasing
-
-40
150
°C
Flash program memory endurance
(erase/write cycles)(1)
NWE
TA = 25 °C
1000
-
cycles
TA = 25 °C
TA = 55 °C
40
20
-
-
tRET
Data retention time
years
1. The physical granularity of the memory is four bytes, so cycling is performed on four bytes even when a
write/erase operation addresses a single byte.
Table 36. Data memory
Symbol
Parameter
Condition
Min
Max
Unit
TWE
Temperature for writing and erasing
-40
150
°C
Data memory endurance(1)
(erase/write cycles)
TA = 25 °C
TA = -40°C to 125 °C
TA = 25 °C
300 k
-
-
-
-
NWE
cycles
years
100 k(2)
40(2)(3)
20(2)(3)
tRET
Data retention time
TA = 55 °C
1. The physical granularity of the memory is four bytes, so cycling is performed on four bytes even when a
write/erase operation addresses a single byte.
2. More information on the relationship between data retention time and number of write/erase cycles is
available in a separate technical document.
3. Retention time for 256B of data memory after up to 1000 cycles at 125 °C.
58/89
Doc ID 14952 Rev 6
STM8AF61xx, STM8AF62xx
Electrical characteristics
10.3.6
I/O port pin characteristics
General characteristics
Subject to general operating conditions for VDD and TA unless otherwise specified. All
unused pins must be kept at a fixed voltage, using the output mode of the I/O for example or
an external pull-up or pull-down resistor.
Table 37. I/O static characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VIL
VIH
Input low level voltage
Input high level voltage
-0.3 V
0.3 x VDD
0.7 x VDD
VDD + 0.3 V
0.1 x
VDD
Vhys
Hysteresis(1)
-
-
-
-
—
Standard I/0, VDD = 5 V,
I = 3 mA
V
DD - 0.5 V
-
-
VOH
Output high level voltage
Standard I/0, VDD = 3 V,
I = 1.5 mA
V
DD - 0.4 V
High sink and true open
drain I/0, VDD = 5 V
I = 8 mA
-
-
-
-
0.5
0.6
VOL
Output low level voltage
Pull-up resistor
Standard I/0, VDD = 5 V
I = 3 mA
V
Standard I/0, VDD = 3 V
I = 1.5 mA
-
35
-
-
50
-
0.4
65
Rpu
VDD = 5 V, VIN = VSS
kΩ
Fast I/Os
Load = 50 pF
35(2)
Standard and high sink I/Os
Load = 50 pF
-
-
125(2)
20(2)
50(2)
1
Rise and fall time
(10% - 90%)
tR, tF
ns
Fast I/Os
Load = 20 pF
Standard and high sink I/Os
Load = 20 pF
Digital input pad leakage
current
Ilkg
VSS ≤VIN ≤VDD
-
-
-
-
-
-
-
-
-
-
µA
nA
VSS ≤ VIN ≤ VDD
-40 °C < TA < 125 °C
250
500
1(3)
60
Analog input pad leakage
current
Ilkg ana
VSS ≤ VIN ≤ VDD
-40 °C < TA < 150 °C
Leakage current in
adjacent I/O(3)
Ilkg(inj)
IDDIO
Injection current 4 mA
µA
Total current on either
Including injection currents
mA
VDDIO or VSSIO
1. Hysteresis voltage between Schmitt trigger switching levels. Based on characterization results, not tested in production.
Doc ID 14952 Rev 6
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Electrical characteristics
STM8AF61xx, STM8AF62xx
2. Guaranteed by design.
3. Data based on characterization results, not tested in production.
Figure 20. Typical V and V vs V @ four temperatures
IL
IH
DD
6
5
4
3
2
1
0
-40°C
25°C
85°C
125°C
2.5
3
3.5
4
4.5
5
5.5
6
VDD [V]
Figure 21. Typical pull-up resistance R vs V @ four temperatures
PU
DD
60
55
50
45
40
35
30
-40°C
25°C
85°C
125°C
2.5
3
3.5
4
4.5
5
5.5
6
VDD [V]
60/89
Doc ID 14952 Rev 6
STM8AF61xx, STM8AF62xx
Electrical characteristics
Figure 22. Typical pull-up current I vs V @ four temperatures
pu
DD
140
120
100
80
-40°C
25°C
85°C
125°C
60
40
20
0
0
1
2
3
4
5
6
VDD [V]
Note: The pull-up is a pure resistor (slope goes through 0).
Typical output level curves
Figure 23 to Figure 32 show typical output level curves measured with output on a single
pin.
Figure 23. Typ. V @ V = 3.3 V (standard
Figure 24. Typ. V @ V = 5.0 V (standard
OL DD
OL
DD
ports)
ports)
-40°C
25°C
85°C
125°C
-40°C
25°C
85°C
125°C
1.5
1.25
1
1.5
1.25
1
0.75
0.5
0.25
0
0.75
0.5
0.25
0
0
1
2
3
4
5
6
7
0
2
4
6
8
10
12
I
OL [mA]
IOL [mA]
Figure 25. Typ. V @ V = 3.3 V (true open Figure 26. Typ. V @ V = 5.0 V (true open
OL
DD
OL
DD
drain ports)
drain ports)
-40°C
25°C
85°C
125°C
-40°C
25°C
85°C
125°C
2
1.75
1.5
1.25
1
2
1.75
1.5
1.25
1
0.75
0.5
0.25
0
0.75
0.5
0.25
0
0
2
4
6
8
10
12
14
0
5
10
15
20
25
IOL [mA]
IOL [mA]
Doc ID 14952 Rev 6
61/89
Electrical characteristics
STM8AF61xx, STM8AF62xx
Figure 27. Typ. V @ V = 3.3 V (high sink
Figure 28. Typ. V @ V = 5.0 V (high sink
OL DD
OL
DD
ports)
ports)
-40°C
25°C
85°C
125°C
-40°C
25°C
85°C
125°C
1.5
1.25
1
1.5
1.25
1
0.75
0.5
0.25
0
0.75
0.5
0.25
0
0
2
4
6
8
10
12
14
0
5
10
15
20
25
IOL [mA]
IOL [mA]
Figure 29. Typ. V
V
@ V = 3.3 V
Figure 30. Typ. V
V
@ V = 5.0 V
DD - OH
DD
DD - OH DD
(standard ports)
(standard ports)
-40°C
25°C
85°C
125°C
-40°C
25°C
85°C
125°C
2
1.75
1.5
1.25
1
2
1.75
1.5
1.25
1
0.75
0.5
0.25
0
0.75
0.5
0.25
0
0
1
2
3
4
5
6
7
0
2
4
6
8
10
12
IOH [mA]
IOH [mA]
Figure 31. Typ. V
V
@ V = 3.3 V (high Figure 32. Typ. V
V
@ V = 5.0 V (high
DD - OH
DD
DD - OH DD
sink ports)
sink ports)
-40°C
25°C
85°C
125°C
-40°C
25°C
85°C
125°C
2
1.75
1.5
1.25
1
2
1.75
1.5
1.25
1
0.75
0.5
0.25
0
0.75
0.5
0.25
0
0
2
4
6
8
10
12
14
0
5
10
15
20
25
IOH [mA]
IOH [mA]
62/89
Doc ID 14952 Rev 6
STM8AF61xx, STM8AF62xx
Electrical characteristics
10.3.7
Reset pin characteristics
Subject to general operating conditions for VDD and TA unless otherwise specified.
Table 38. NRST pin characteristics
Symbol
Parameter
Conditions
Min
VSS
Typ
Max
0.3 x VDD
VDD
Unit
VIL(NRST)
NRST input low level voltage(1)
NRST input high level voltage(1)
-
-
-
0.7 x VDD
VIH(NRST)
VOL(NRST)
RPU(NRST)
tIFP
-
-
NRST output low level voltage(1) IOL= 3 mA
-
0.6
60
V
NRST pull-up resistor
-
-
30
85
40
-
kΩ
ns
NRST input filtered pulse(1)
315
NRST Input not filtered pulse
duration(2)
tIFP(NRST)
500
ns
1. Data based on characterization results, not tested in production.
2. Data guaranteed by design, not tested in production.
Figure 33. Typical NRST V and V vs V @ four temperatures
IL
IH
DD
-40°C
6
5
4
3
2
1
0
25°C
85°C
125°C
2.5
3
3.5
4
4.5
5
5.5
6
VDD [V]
Doc ID 14952 Rev 6
63/89
Electrical characteristics
Figure 34. Typical NRST pull-up resistance R vs V
STM8AF61xx, STM8AF62xx
PU
DD
-40°C
25°C
85°C
125°C
60
55
50
45
40
35
30
2.5
3
3.5
4
4.5
5
5.5
6
VDD [V]
Figure 35. Typical NRST pull-up current I vs V
pu
DD
140
120
100
80
60
-40°C
25°C
85°C
125°C
40
20
0
0
1
2
3
4
5
6
VDD [V]
The reset network shown in Figure 36 protects the device against parasitic resets. The user
must ensure that the level on the NRST pin can go below VIL(NRST) max (see Table 38:
NRST pin characteristics), otherwise the reset is not taken into account internally.
Figure 36. Recommended reset pin protection
STM8A
V
DD
RPU
External
reset
circuit
NRST
Internal reset
Filter
(optional)
0.1µF
64/89
Doc ID 14952 Rev 6
STM8AF61xx, STM8AF62xx
Electrical characteristics
10.3.8
TIM 1, 2, 3, and 4 timer specifications
Subject to general operating conditions for VDD, fMASTER, and TA unless otherwise specified.
Table 39. TIM 1, 2, 3, and 4 electrical specifications
Symbol
fEXT
Parameter
Conditions
Min
Typ
Max
Unit
Timer external clock frequency(1)
-
-
-
16
MHz
1. Not tested in production. On 64 Kbyte devices, the frequency is limited to 16 MHz.
SPI serial peripheral interface
10.3.9
Unless otherwise specified, the parameters given in Table 40 are derived from tests
performed under ambient temperature, fMASTER frequency and VDD supply voltage
conditions. tMASTER = 1/fMASTER
.
Refer to I/O port characteristics for more details on the input/output alternate function
characteristics (NSS, SCK, MOSI, MISO).
Table 40. SPI characteristics
Symbol
Parameter
Conditions
Min
Max
Unit
Master mode
Slave mode
0
0
0
10
fSCK
1/tc(SCK)
SPI clock frequency
VDD < 4.5 V
VDD = 4.5 V to 5.5 V
6(1)
8(1)
MHz
tr(SCK
tf(SCK)
)
SPI clock rise and fall time Capacitive load: C = 30 pF
-
25(2)
(3)
tsu(NSS)
NSS setup time
NSS hold time
Slave mode
Slave mode
4 * tMASTER
70
-
-
(3)
th(NSS)
(3)
tw(SCKH)
tw(SCKL)
SCK high and low time
Data input setup time
Master mode
tSCK/2 - 15 tSCK/2 + 15
(3)
(3)
Master mode
Slave mode
Master mode
Slave mode
Slave mode
Slave mode
5
5
-
tsu(MI)
tsu(SI)
(3)
-
(3)
7
-
th(MI)
th(SI)
ns
Data input hold time
(3)
10
-
-
(3)(4)
ta(SO)
Data output access time
Data output disable time
3* tMASTER
(3)(5)
tdis(SO)
25
-
VDD < 4.5 V
75
53
30
-
Slave mode
(after enable edge)
(3)
(3)
tv(SO)
Data output valid time
Data output valid time
Data output hold time
VDD = 4.5 V to 5.5 V
-
tv(MO)
Master mode (after enable edge)
Slave mode (after enable edge)
Master mode (after enable edge)
-
(3)
th(SO)
31
12
(3)
th(MO)
-
1. fSCK < fMASTER/2.
2. The pad has to be configured accordingly (fast mode).
3. Values based on design simulation and/or characterization results, and not tested in production.
Doc ID 14952 Rev 6
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Electrical characteristics
STM8AF61xx, STM8AF62xx
4. Min time is for the minimum time to drive the output and the max time is for the maximum time to validate the data.
5. Min time is for the minimum time to invalidate the output and the max time is for the maximum time to put the data in Hi-Z.
Figure 37. SPI timing diagram where slave mode and CPHA = 0
NSS input
t
t
t
h(NSS)
SU(NSS)
c(SCK)
CPHA=0
CPOL=0
t
t
w(SCKH)
w(SCKL)
CPHA=0
CPOL=1
t
t
t
t
t
dis(SO)
v(SO)
r(SCK)
f(SCK)
h(SO)
t
a(SO)
MISO
OUT PUT
MSB O UT
BI T6 OUT
BIT1 IN
LSB OUT
t
su(SI)
MOSI
M SB IN
LSB IN
INPUT
t
h(SI)
ai14134
1. Measurement points are at CMOS levels: 0.3 VDD and 0.7 VDD
.
Figure 38. SPI timing diagram where slave mode and CPHA = 1
NSS input
t
t
t
SU(NSS)
t
c(SCK)
h(NSS)
CPHA=1
CPOL=0
w(SCKH)
CPHA=1
CPOL=1
t
w(SCKL)
t
t
r(SCK)
f(SCK)
t
t
t
v(SO)
h(SO)
dis(SO)
t
a(SO)
MISO
OUT PUT
MSB O UT
BI T6 OUT
LSB OUT
t
t
su(SI)
h(SI)
MOSI
M SB IN
BIT1 IN
LSB IN
INPUT
ai14135
1. Measurement points are at CMOS levels: 0.3 VDD and 0.7 VDD
.
66/89
Doc ID 14952 Rev 6
STM8AF61xx, STM8AF62xx
Electrical characteristics
Figure 39. SPI timing diagram - master mode
(IGH
.33 INPUT
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T
T
Vꢆ-/ꢇ
Hꢆ-/ꢇ
AIꢀꢁꢀꢂꢃ
1. Measurement points are at CMOS levels: 0.3 VDD and 0.7 VDD
.
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Electrical characteristics
STM8AF61xx, STM8AF62xx
2
10.3.10 I C interface characteristics
2
Table 41. I C characteristics
Standard mode I2C Fast mode I2C(1)
Unit
Symbol
Parameter
Min(2)
Max(2)
Min(2) Max(2)
tw(SCLL)
tw(SCLH)
tsu(SDA)
th(SDA)
SCL clock low time
4.7
4.0
-
-
-
-
1.3
0.6
-
-
-
µs
ns
µs
SCL clock high time
SDA setup time
250
100
0(3)
0(4)
900(3)
SDA data hold time
tr(SDA)
tr(SCL)
SDA and SCL rise time
(VDD = 3 to 5.5 V)
-
1000
300
-
300
tf(SDA)
tf(SCL)
SDA and SCL fall time
(VDD = 3 to 5.5 V)
-
-
300
th(STA)
START condition hold time
4.0
4.7
4.0
-
-
-
0.6
0.6
0.6
-
-
-
tsu(STA)
tsu(STO)
Repeated START condition setup time
STOP condition setup time
µs
µs
pF
STOP to START condition time
(bus free)
tw(STO:STA)
Cb
4.7
-
1.3
-
-
Capacitive load for each bus line
-
400
400
1. fMASTER, must be at least 8 MHz to achieve max fast I2C speed (400 kHz)
Data based on standard I2C protocol requirement, not tested in production
2.
The maximum hold time of the start condition has only to be met if the interface does not stretch the low
time
3.
4.
The device must internally provide a hold time of at least 300 ns for the SDA signal in order to bridge the
undefined region of the falling edge of SCL
68/89
Doc ID 14952 Rev 6
STM8AF61xx, STM8AF62xx
Electrical characteristics
10.3.11 10-bit ADC characteristics
Subject to general operating conditions for VDDA, fMASTER, and TA unless otherwise
specified.
Table 42. ADC characteristics
Symbol
fADC
Parameter
ADC clock frequency
Analog supply
Conditions
Min
111 kHz
3
Max
Unit
Typ
-
-
-
-
-
-
4 MHz kHz/MHz
VDDA
5.5
VDDA
VREF+
VREF-
Positive reference voltage
Negative reference voltage
2.75
-
-
VSSA
VSSA
-
-
0.5
V
VDDA
Conversion voltage range(1)
Devices with
external VREF+
VREF- pins
VAIN
VREF-
VREF+
/
-
Csamp
Internal sample and hold capacitor
Sampling time
-
-
-
-
-
-
-
-
1.5
0.75
7
3
-
pF
µs
f
f
f
ADC = 2 MHz
ADC = 4 MHz
ADC = 2 MHz
(1)
tS
(3 x 1/fADC
)
-
-
tSTAB
Wakeup time from standby
fADC = 4 MHz
fADC = 2 MHz
3.5
7
-
Total conversion time including
sampling time
-
tCONV
fADC = 4 MHz
-
-
-
3.5
-
-
(14 x 1/fADC
)
Rswitch
Equivalent switch resistance
30
kΩ
1. During the sample time, the sampling capacitance, Csamp (3 pF typ), can be charged/discharged by the
external source. The internal resistance of the analog source must allow the capacitance to reach its final
voltage level within tS. After the end of the sample time tS, changes of the analog input voltage have no
effect on the conversion result.
Figure 40. Typical application with ADC
V
DD
STM8A
V
0.6V
T
Rswitch
R
AIN
AINx
10-bit A/D
conversion
V
AIN
T
s
C
V
T
0.6V
AIN
I
C
L
samp
1. Legend: RAIN = external resistance, CAIN = capacitors, Csamp = internal sample and hold capacitor.
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Electrical characteristics
STM8AF61xx, STM8AF62xx
Table 43. ADC accuracy for V
= 5 V
DDA
Max(1)
Symbol
|ET|
Parameter
Conditions
Typ
Unit
Total unadjusted error(2)
Offset error(2)
1.4
0.8
0.1
0.9
0.7
3(3)
3
|EO|
|EG|
|ED|
|EL|
|ET|
Gain error(2)
2
fADC = 2 MHz
Differential linearity error(2)
Integral linearity error(2)
Total unadjusted error(2)
1
1.5
LSB
1.9(4)
1.3(4)
0.6(4)
1.5(4)
1.2(4)
4(4)
4(4)
|EO|
|EG|
|ED|
|EL|
Offset error(2)
Gain error(2)
3(4)
fADC = 4 MHz
Differential linearity error(2)
Integral linearity error(2)
2(4)
1.5(4)
1. Max value is based on characterization, not tested in production.
2. ADC accuracy vs. injection current: Any positive or negative injection current within the limits specified for
IINJ(PIN) and ΣIINJ(PIN) in Section 10.3.6 does not affect the ADC accuracy.
3. TUE 2LSB can be reached on specific salestypes on the whole temperature range.
4. Target values.
Figure 41. ADC accuracy characteristics
E
G
1023
1022
1021
V
– V
DDA
SSA
1LSB
= ----------------------------------------
IDEAL
1024
(2)
E
T
(3)
7
6
5
4
3
2
1
(1)
E
O
E
L
E
D
1 LSB
IDEAL
7
0
V
1
2
3
4
5
6
1021102210231024
V
DDA
SSA
1. Example of an actual transfer curve
2. The ideal transfer curve
3. End point correlation line
ET = Total unadjusted error: Maximum deviation between the actual and the ideal transfer curves.
E
E
E
O = Offset error: Deviation between the first actual transition and the first ideal one.
G = Gain error: Deviation between the last ideal transition and the last actual one.
D = Differential linearity error: Maximum deviation between actual steps and the ideal one.
EL = Integral linearity error: Maximum deviation between any actual transition and the end point correlation
line.
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Doc ID 14952 Rev 6
STM8AF61xx, STM8AF62xx
Electrical characteristics
10.3.12 EMC characteristics
Susceptibility tests are performed on a sample basis during product characterization.
Functional EMS (electromagnetic susceptibility)
While executing a simple application (toggling 2 LEDs through I/O ports), the product is
stressed by two electromagnetic events until a failure occurs (indicated by the LEDs).
●
ESD: Electrostatic discharge (positive and negative) is applied on all pins of the device
until a functional disturbance occurs. This test conforms with the IEC 1000-4-2
standard.
●
FTB: A burst of fast transient voltage (positive and negative) is applied to VDD and VSS
through a 100 pF capacitor, until a functional disturbance occurs. This test conforms
with the IEC 1000-4-4 standard.
A device reset allows normal operations to be resumed. The test results are given in the
table below based on the EMS levels and classes defined in application note AN1709.
Designing hardened software to avoid noise problems
EMC characterization and optimization are performed at component level with a typical
application environment and simplified MCU software. It should be noted that good EMC
performance is highly dependent on the user application and the software in particular.
Therefore it is recommended that the user applies EMC software optimization and
prequalification tests in relation with the EMC level requested for his application.
Software recommendations
The software flowchart must include the management of runaway conditions such as:
●
●
●
Corrupted program counter
Unexpected reset
Critical data corruption (control registers...)
Prequalification trials
Most of the common failures (unexpected reset and program counter corruption) can be
recovered by applying a low state on the NRST pin or the oscillator pins for 1 second.
To complete these trials, ESD stress can be applied directly on the device, over the range of
specification values. When unexpected behavior is detected, the software can be hardened
to prevent unrecoverable errors occurring (see application note AN1015).
Table 44. EMS data
Symbol
Parameter
Conditions
Level/class
VDD = 3.3 V, TA= 25 °C,
fMASTER = 16 MHz (HSI clock),
Conforms to IEC 1000-4-2
Voltage limits to be applied on any I/O pin to
induce a functional disturbance
VFESD
3B
VDD= 3.3 V, TA= 25 °C,
fMASTER = 16 MHz (HSI clock),
Conforms to IEC 1000-4-4
Fast transient voltage burst limits to be
applied through 100 pF on VDD and VSS
pins to induce a functional disturbance
VEFTB
4A
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Electrical characteristics
STM8AF61xx, STM8AF62xx
Electromagnetic interference (EMI)
Emission tests conform to the SAE J 1752/3 standard for test software, board layout and pin
loading.
Table 45. EMI data
Conditions
(1)
Max fCPU
Symbol
Parameter
Unit
Monitored
frequency band
General conditions
8
16
MHz
MHz
0.1 MHz to 30 MHz
30 MHz to 130 MHz
130 MHz to 1 GHz
—
15
18
-1
2
17
22
3
VDD = 5 V,
TA = 25 °C,
Peak level
SEMI
LQFP80 package
conforming to SAE J
1752/3
dBµV
SAE EMI level
2.5
1. Data based on characterization results, not tested in production.
Absolute maximum ratings (electrical sensitivity)
Based on two different tests (ESD and LU) using specific measurement methods, the
product is stressed to determine its performance in terms of electrical sensitivity. For more
details, refer to the application note AN1181.
Electrostatic discharge (ESD)
Electrostatic discharges (3 positive then 3 negative pulses separated by 1 second) are
applied to the pins of each sample according to each pin combination. The sample size
depends on the number of supply pins in the device (3 parts*(n+1) supply pin). This test
conforms to the JESD22-A114A/A115A standard. For more details, refer to the application
note AN1181.
Table 46. ESD absolute maximum ratings
Maximum
Symbol
Ratings
Conditions
Class
Unit
value(1)
Electrostatic discharge voltage
(Human body model)
TA = 25°C, conforming to
VESD(HBM)
VESD(CDM)
VESD(MM)
3A
3
4000
JESD22-A114
Electrostatic discharge voltage
(Charge device model)
TA= 25°C, conforming to
500
200
V
JESD22-C101
Electrostatic discharge voltage
(Machine model)
TA= 25°C, conforming to
B
JESD22-A115
1. Data based on characterization results, not tested in production
72/89
Doc ID 14952 Rev 6
STM8AF61xx, STM8AF62xx
Static latch-up
Electrical characteristics
Two complementary static tests are required on 10 parts to assess the latch-up
performance.
●
A supply overvoltage (applied to each power supply pin) and
A current injection (applied to each input, output and configurable I/O pin) are
performed on each sample.
●
This test conforms to the EIA/JESD 78 IC latch-up standard. For more details, refer to the
application note AN1181.
Table 47. Electrical sensitivities
Class(1)
Symbol
Parameter
Conditions
TA = 25 °C
TA = 85 °C
LU
Static latch-up class
A
TA = 125 °C
TA = 150 °C(2)
1. Class description: A Class is an STMicroelectronics internal specification. All its limits are higher than the
JEDEC specifications, that means when a device belongs to class A it exceeds the JEDEC standard. B
class strictly covers all the JEDEC criteria (international standard).
2. Available on STM8AF62xx devices only.
10.4
Thermal characteristics
In case the maximum chip junction temperature (TJmax) specified in Table 23: General
operating conditions on page 49 is exceeded, the functionality of the device cannot be
guaranteed.
TJmax, in degrees Celsius, may be calculated using the following equation:
TJmax = TAmax + (PDmax x Θ )
JA
Where:
–
–
–
–
TAmax is the maximum ambient temperature in °C
JA is the package junction-to-ambient thermal resistance in ° C/W
Θ
PDmax is the sum of PINTmax and PI/Omax (PDmax = PINTmax + PI/Omax
)
PINTmax is the product of IDD and VDD, expressed in Watts. This is the maximum
chip internal power.
PI/Omax represents the maximum power dissipation on output pins
–
Where:
PI/Omax = Σ (VOL*IOL) + Σ((VDD-VOH)*IOH),
taking into account the actual VOL/IOL and VOH/IOH of the I/Os at low and high level
in the application.
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Electrical characteristics
STM8AF61xx, STM8AF62xx
(1)
Table 48. Thermal characteristics
Symbol
Parameter
Value
Unit
Thermal resistance junction-ambient
LQFP 48 - 7 x 7 mm
Θ
57
°C/W
JA
Thermal resistance junction-ambient
LQFP 32 - 7 x 7 mm
Θ
59
25
°C/W
°C/W
JA
Thermal resistance junction-ambient
VFQFPN32
Θ
JA
1. Thermal resistances are based on JEDEC JESD51-2 with 4-layer PCB in a natural convection
environment.
10.4.1
10.4.2
Reference document
JESD51-2 integrated circuits thermal test method environment conditions - natural
convection (still air). Available from www.jedec.org.
Selecting the product temperature range
When ordering the microcontroller, the temperature range is specified in the order code (see
Section 12: Ordering information).
The following example shows how to calculate the temperature range needed for a given
application.
Assuming the following application conditions:
Maximum ambient temperature TAmax= 82 °C (measured according to JESD51-2),
IDDmax = 14 mA, VDD = 5 V, maximum 20 I/Os used at the same time in output at low
level with IOL = 8 mA, VOL= 0.4 V
PINTmax = 14 mA x 5 V= 70 mW
PIOmax = 20 x 8 mA x 0.4 V = 64 mW
This gives: PINTmax = 70 mW and PIOmax 64 mW:
Dmax = 70 mW + 64 mW
P
Thus: PDmax = 134 mW.
Using the values obtained in Table 48: Thermal characteristics on page 74 TJmax is
calculated as follows:
For LQFP64 46 °C/W
T
Jmax = 82 °C + (46 °C/W x 134 mW) = 82 °C + 6 °C = 88 °C
This is within the range of the suffix B version parts (-40 < TJ < 105 °C).
Parts must be ordered at least with the temperature range suffix B.
74/89
Doc ID 14952 Rev 6
STM8AF61xx, STM8AF62xx
Package characteristics
11
Package characteristics
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
Doc ID 14952 Rev 6
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Package characteristics
STM8AF61xx, STM8AF62xx
11.1
Package mechanical data
Figure 42. VFQFPN 32-lead very thin fine pitch quad flat no-lead package (5 x 5)
Seating plane
C
ddd
C
A
A1
A3
D
e
16
9
17
8
b
E
E2
24
1
L
32
Pin # 1 ID
R = 0.30
D2
L
Bottom view
42_ME
Table 49. VFQFPN 32-lead very thin fine pitch quad flat no-lead package
mechanical data
mm
Typ
inches(1)
Dim.
Min
Max
Min
Typ
Max
A
A1
A3
b
0.800
0.000
—
0.900
0.020
0.200
0.250
5.000
3.450
5.000
3.450
0.500
0.400
—
1.000
0.050
—
0.0315
0.000
—
0.0354
0.0008
0.0079
0.0098
0.1969
0.1358
0.1969
0.1358
0.0197
0.0157
—
0.0394
0.0020
—
0.180
4.850
3.400
4.850
3.400
—
0.300
5.150
3.500
5.150
3.500
—
0.0071
0.1909
0.1339
0.1909
0.1339
—
0.0118
0.2028
0.1378
0.2028
0.1378
—
D
D2
E
E2
e
L
0.300
—
0.500
0.080
0.0118
—
0.0197
0.0031
ddd
1. Values in inches are converted from mm and rounded to 4 decimal digits
76/89
Doc ID 14952 Rev 6
STM8AF61xx, STM8AF62xx
Package characteristics
Figure 43. LQFP 48-pin low profile quad flat package (7 x 7)
D
ccc
C
D1
D3
A
A2
25
36
24
37
L1
b
E3
E1 E
48
L
13
A1
K
Pin 1
identification
1
12
c
5B_ME
Table 50. LQFP 48-pin low profile quad flat package mechanical data
mm
Typ
inches(1)
Dim.
Min
Max
Min
Typ
Max
A
A1
A2
b
—
0.050
1.350
0.170
0.090
8.800
6.800
—
—
1.600
0.150
1.450
0.270
0.200
9.200
7.200
—
—
0.0020
0.0531
0.0067
0.0035
0.3465
0.2677
—
—
0.0630
0.0059
0.0571
0.0106
0.0079
0.3622
0.2835
—
—
—
1.400
0.220
—
0.0551
0.0087
—
c
D
9.000
7.000
5.500
9.000
7.000
5.500
0.500
3.5°
0.3543
0.2756
0.2165
0.3543
0.2756
0.2165
0.0197
3.5°
D1
D3
E
8.800
6.800
—
9.200
7.200
—
0.3465
0.2677
—
0.3622
0.2835
—
E1
E3
e
—
—
—
—
θ
0°
7°
0°
7°
L
0.450
—
0.600
1.000
—
0.750
—
0.0177
—
0.0236
0.0394
—
0.0295
—
L1
ccc
—
0.080
—
0.0031
1. Values in inches are converted from mm and rounded to 4 decimal digits
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Package characteristics
Figure 44. LQFP 48-pin recommended footprint
STM8AF61xx, STM8AF62xx
ꢅꢉꢋꢅ
ꢀꢉꢍꢅ
ꢅꢉꢂꢅ
ꢂꢃ
ꢍꢋ
ꢂꢊ
ꢍꢁ
ꢅꢉꢍꢅ
ꢊꢉꢂꢅ
ꢈꢉꢊꢅ ꢋꢉꢌꢅ
ꢊꢉꢂꢅ
ꢁꢌ
ꢀꢂ
ꢀꢍ
ꢀ
ꢀꢉꢍꢅ
ꢋꢉꢌꢅ
ꢈꢉꢊꢅ
ꢋ"?&0
1. Drawing is not to scale. Dimensions are in millimeters.
78/89
Doc ID 14952 Rev 6
STM8AF61xx, STM8AF62xx
Figure 45. LQFP 32-pin low profile quad flat package (7 x 7)
Package characteristics
ccc
C
D
D1
D3
A
A2
24
17
16
25
32
L1
b
E3
E1 E
9
L
Pin 1
identification
A1
K
1
8
c
5V_ME
Table 51. LQFP 32-pin low profile quad flat package mechanical data
mm
Typ
inches(1)
Dim.
Min
Max
Min
Typ
Max
A
A1
A2
b
—
0.050
1.350
0.300
0.090
8.800
6.800
—
—
1.600
0.150
1.450
0.450
0.200
9.200
7.200
—
—
0.0020
0.0531
0.0118
0.0035
0.3465
0.2677
—
—
0.0630
0.0059
0.0571
0.0177
0.0079
0.3622
0.2835
—
—
—
1.400
0.370
—
0.0551
0.0146
—
c
D
9.000
7.000
5.600
9.000
7.000
5.600
0.800
3.5°
0.3543
0.2756
0.2205
0.3543
0.2756
0.2205
0.0315
3.5°
D1
D3
E
8.800
6.800
—
9.200
7.200
—
0.3465
0.2677
—
0.3622
0.2835
—
E1
E3
e
—
—
—
—
θ
0°
7°
0°
7°
L
0.450
—
0.600
1.000
—
0.750
—
0.0177
—
0.0236
0.0394
—
0.0295
—
L1
ccc
—
0.100
—
0.0039
1. Values in inches are converted from mm and rounded to 4 decimal digits
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Package characteristics
Figure 46. LQFP 32-pin recommended footprint
STM8AF61xx, STM8AF62xx
ꢈꢉꢁꢅ
ꢊꢉꢊꢅ
ꢅꢉꢋꢁ
ꢈꢉꢁꢅ
ꢅꢉꢌꢅ
ꢋ6?&0
1. Drawing is not to scale. Dimensions are in millimeters.
80/89
Doc ID 14952 Rev 6
STM8AF61xx, STM8AF62xx
Ordering information
12
Ordering information
(1)
Figure 47. Ordering information scheme
xxx(2)
Y
Example:
STM8A
F
62
6
8
T
D
Product class
8-bit automotive microcontroller
Program memory type
F = Flash + EEPROM
P= FASTROM
H = Flash no EEPROM(3)
Device family
61 = Silicon rev Y, LIN only(3)
62 = Silicon rev X and rev W, LIN only
Program memory size
2 = 8 Kbytes
4 = 16 Kbytes
6 = 32 Kbytes
Pin count
6 = 32 pins
8 = 48 pins
Package type
T = LQFP
U = VFQFPN
Temperature range
A = -40 to 85 °C
B = -40 to 105 °C(3)
C = -40 to 125 °C
D = -40 to 150 °C(4)
Packing
Y = Tray
U = Tube
X = Tape and reel compliant with EIA 481-C
1. For a list of available options (e.g. memory size, package) and orderable part numbers or for further
information on any aspect of this device, please go to www.st.com or contact the ST Sales Office nearest
to you.
2. Customer specific FASTROM code or custom device configuration. This field shows ‘SSS’ if the device
contains a super set silicon, usually equipped with bigger memory and more I/Os. This silicon is supposed
to be replaced later by the target silicon.
3. Not recommended for new design.
4. Available on STM8AF62xx devices.
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STM8 development tools
STM8AF61xx, STM8AF62xx
13
STM8 development tools
Development tools for the STM8A microcontrollers include the
●
STice emulation system offering tracing and code profiling
●
STVD high-level language debugger including assembler and visual development
environment - seamless integration of third party C compilers.
●
STVP Flash programming software
In addition, the STM8A comes with starter kits, evaluation boards and low-cost in-circuit
debugging/programming tools.
13.1
Emulation and in-circuit debugging tools
The STM8 tool line includes the STice emulation system offering a complete range of
emulation and in-circuit debugging features on a platform that is designed for versatility and
cost-effectiveness. In addition, STM8A application development is supported by a low-cost
in-circuit debugger/programmer.
The STice is the fourth generation of full-featured emulators from STMicroelectronics. It
offers new advanced debugging capabilities including tracing, profiling and code coverage
analysis to help detect execution bottlenecks and dead code.
In addition, STice offers in-circuit debugging and programming of STM8A microcontrollers
via the STM8 single wire interface module (SWIM), which allows non-intrusive debugging of
an application while it runs on the target microcontroller.
For improved cost effectiveness, STice is based on a modular design that allows you to
order exactly what you need to meet your development requirements and to adapt your
emulation system to support existing and future ST microcontrollers.
13.1.1
STice key features
●
●
●
●
●
●
●
●
●
●
●
Program and data trace recording up to 128 K records
Advanced breakpoints with up to 4 levels of conditions
Data breakpoints
Real-time read/write of all device resources during emulation
Occurrence and time profiling and code coverage analysis (new features)
In-circuit debugging/programming via SWIM protocol
8-bit probe analyzer
1 input and 2 output triggers
USB 2.0 high speed interface to host PC
Power supply follower managing application voltages between 1.62 to 5.5 V
Modularity that allows you to specify the components you need to meet your
development requirements and adapt to future requirements.
●
Supported by free software tools that include integrated development environment
(IDE), programming software interface and assembler for STM8.
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STM8AF61xx, STM8AF62xx
STM8 development tools
13.2
Software tools
STM8 development tools are supported by a complete, free software package from
STMicroelectronics that includes ST visual develop (STVD) IDE and the ST visual
programmer (STVP) software interface. STVD provides seamless integration of the Cosmic
and Raisonance C compilers for STM8.
13.2.1
STM8 toolset
The STM8 toolset with STVD integrated development environment and STVP programming
software is available for free download at www.st.com. This package includes:
ST visual develop
Full-featured integrated development environment from STMicroelectronics, featuring:
●
●
●
●
●
●
Seamless integration of C and ASM toolsets
Full-featured debugger
Project management
Syntax highlighting editor
Integrated programming interface
Support of advanced emulation features for STice such as code profiling and coverage
ST visual programmer (STVP)
Easy-to-use, unlimited graphical interface allowing read, write and verification of the STM8A
microcontroller’s Flash memory. STVP also offers project mode for saving programming
configurations and automating programming sequences.
13.2.2
C and assembly toolchains
Control of C and assembly toolchains is seamlessly integrated into the STVD integrated
development environment, making it possible to configure and control the building of your
application directly from an easy-to-use graphical interface.
Available toolchains include:
C compiler for STM8
All compilers are available in free version with a limited code size depending on the
compiler. For more information, refer to www.cosmic-software.com, www.raisonance.com,
and www.iar.com.
STM8 assembler linker
Free assembly toolchain included in the STM8 toolset, which allows you to assemble and
link your application source code.
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STM8 development tools
STM8AF61xx, STM8AF62xx
13.3
Programming tools
During the development cycle, STice provides in-circuit programming of the STM8A Flash
microcontroller on your application board via the SWIM protocol. Additional tools are to
include a low-cost in-circuit programmer as well as ST socket boards, which provide
dedicated programming platforms with sockets for programming your STM8A.
For production environments, programmers will include a complete range of gang and
automated programming solutions from third-party tool developers already supplying
programmers for the STM8 family.
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Revision history
14
Revision history
Table 52. Document revision history
Date
Revision
Changes
22-Aug-2008
1
Initial release
Document revised as the following:
Updated Features on page 1;
Updated Table 1: Device summary;
Updated Section 3: Product line-up;
Changed Section 5: Product overview;
Updated Section 6: Pinouts and pin description;
Changed Section 7.2: Register map;
Updated Section 8: Interrupt table;
10-Aug-2009
2
Updated Section 9: Option bytes;
Updated Section 10: Electrical characteristics;
Updated Section 11: Package characteristics;
Updated Section 12: Ordering information;
Added Section 13: STM8 development tools.
Adapted Table 10: STM8AF61xx/62xx (32 Kbytes) microcontroller
pin description.
22-Oct-2009
3
Added Section 13.4.5: LIN header error when automatic
resynchronization is enabled.
Updated title on cover page.
Added VFQFPN32 5x 5 mm package.
Added STM8AF62xx devices, and modified cover page header to
clarify the part numbers covered by the datasheets. Updated Note 1
below Table 1: Device summary.
Updated D temperature range to -40 to 150°C.
Content of Section 5: Product overview reorganized.
Renamed Section 7 Memory and register map, and content merged
with Register map section.
Renamed BL_EN and NBL_EN, BL and NBL, respectively, in
Table 17: Option bytes.
Added Table 22: Operating lifetime.
08-Jul-2010
4
Added CEXT and PD (power dissipation) in Table 23: General
operating conditions, and Section 10.3.1: VCAP external capacitor.
Suffix D maximum junction temperature (TJ) updated in Table 23:
General operating conditions.
Update tVDD in Table 24: Operating conditions at power-up/power-
down.
Moved Table 29: Typical peripheral current consumption VDD = 5.0 V
to Section : Current consumption for on-chip peripherals and
removed IDD(CAN)
.
Updated Section 12: Ordering information for the devices supported
by the datasheet.
Updated Section 13: STM8 development tools.
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Revision history
Table 52. Document revision history (continued)
STM8AF61xx, STM8AF62xx
Date
Revision
Changes
Modified references to reference manual, and Flash programming
manual in the whole document.
Added reference to AEC Q100 standard on cover page.
Renamed timer types as follows:
– Auto-reload timer to general purpose timer
– Multipurpose timer to advanced control timer
– System timer to basic timer
Introduced concept of medium density Flash program memory.
Updated timer names in Figure 1: STM8A block diagram.
Added TMU brief description in Section 5.4: Flash program and data
EEPROM, and updated TMU_MAXATT description in Table 18:
Option byte description.
Updated clock sources in clock controller features (Section 5.5.1).
Changed 16MHZTRIM0 to HSITRIM bit in Section : User trimming.
Added Table 4: Peripheral clock gating bits in Section 5.5.6.
Updated Section 5.6: Low-power operating modes.
Added calibration using TIM3 in Section 5.7.2: Auto-wakeup counter.
Added Table 7: ADC naming and Table 8: Communication peripheral
naming correspondence.
31-Jan-2011
5
Added Note 1 related AIN12 pin in Section 5.8: Analog-to-digital
converter (ADC)and Table 10: STM8AF61xx/62xx (32 Kbytes)
microcontroller pin description.
Updated SPI data rate to 10 Mbit/s or fMASTER/2 in Section 5.9.1:
Serial peripheral interface (SPI).
Added reset state in Table 9: Legend/abbreviation.
Table 10: STM8AF61xx/62xx (32 Kbytes) microcontroller pin
description: added Note 7 related to PD1/SWIM, modified Note 6,
corrected wpu input for PE1 and PE2, and renamed TIMn_CCx and
TIMn_NCCx to TIMn_CHx and TIMn_CHxN, respectively.
Section 7.2: Register map:
Replaced tables describing register maps and reset values for non-
volatile memory, global configuration, reset status, clock controller,
interrupt controller, timers, communication interfaces, and ADC, by
Table 13: General hardware register map.
Added Note 1 for Px_IDR registers in Table 12: I/O port hardware
register map. Updated register reset values for Px_IDR registers.
Added SWIM and debug module register map.
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Table 52. Document revision history (continued)
Revision history
Date
Revision
Changes
Renamed Fast Active Halt mode to Active-halt mode with regulator
on, and Slow Active Halt mode to Active-halt mode with regulator off.
Updated Table 26: Total current consumption in Halt and Active-halt
modes. General conditions for VDD apply, TA = -40 to 55 °C, in
particular IDD(FAH) and IDD(SAH) renamed IDD(AH); tWU(FAH) and
tWU(SAH) renamed tWU(AH), and temperature condition added.
Removed IDD(USART) from Table 29: Typical peripheral current
consumption VDD = 5.0 V.
Updated general conditions in Section 10.3.5: Memory
characteristics. Modified TWE maximum value in Table 35: Flash
program memory and Table 36: Data memory.
5
31-Jan-2011
(continued)
Update Ilkg ana maximum value for TA ranging from −40 to 150 °C in
Table 37: I/O static characteristics.
Added tIFP(NRST) and renamed VF(NRST) IFP in Table 38: NRST pin
t
characteristics. Added recommendations concerning NRST pin level
above Figure 36: Recommended reset pin protection, and updated
external capacitor value.
Added Raisonance compiler in Section 13.2: Software tools.
Moved know limitations to separate errata sheet.
Updated wildcards of document part numbers.
Table 1: Device summary: updated footnote 1 and added footnote 2
to all STM8AF61xx part numbers.
Section 1: Introduction: small text change in first paragraph.
Table 2: STM8AF62xx product line-up: added “P” version for all order
codes; updated RAM.
Table 3: STM8AF/H61xx product line-up: added “P” version for all
order codes.
Figure 1: STM8A block diagram: updated POR, BOR and WDG;
updated LINUART input; added legend.
Section 5.4: Flash program and data EEPROM: removed
nonrelevant bullet points and added a sentence about the factory
programme.
Table 4: Peripheral clock gating bit assignments in CLK_PCKENR1/2
registers: updated
18-Jul-2012
6
ADC features: updated ADC input range.
Table 11: Memory model for the devices covered in this datasheet:
updated 16 Kbyte and 8 Kbyte information.
Table 17: Option bytes: updated factory default setting for NOPT17;
added footnote 1.
Section 10.1.1: Minimum and maximum values: TA = -40 °C (not
40 °C).
Table 23: General operating conditions: updated VCAP
.
Table 25: Total current consumption in Run, Wait and Slow mode.
General conditions for VDD apply, TA = -40 to 150 °C: updated
conditions for IDD(RUN)
.
Table 37: I/O static characteristics: added new condition and new
max values for rise and fall time; updated footnote 2.
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Revision history
Table 52. Document revision history (continued)
STM8AF61xx, STM8AF62xx
Date
Revision
Changes
Section 10.3.7: Reset pin characteristics: updated text below
Figure 35: Typical NRST pull-up current Ipu vs VDD.
Figure 36: Recommended reset pin protection: updated unit of
capacitor.
Table 40: SPI characteristics: updated SCK high and low time
conditions and values.
Figure 39: SPI timing diagram - master mode: replaced ‘SCK input’
signals with ‘SCK output’ signals.
Updated Table 49: VFQFPN 32-lead very thin fine pitch quad flat no-
lead package mechanical data, Table 50: LQFP 48-pin low profile
(continued) quad flat package mechanical data, and Table 51: LQFP 32-pin low
profile quad flat package mechanical data.
6
18-Jul-2012
Replaced Figure 43: LQFP 48-pin low profile quad flat package (7 x
7) and Figure 45: LQFP 32-pin low profile quad flat package (7 x 7).
Added Figure 44: LQFP 48-pin recommended footprint and
Figure 46: LQFP 32-pin recommended footprint.
Figure 47: Ordering information scheme(1): added footnote 1, added
“xxx” and footnote 2, updated example and device family; added
FASTROM.
Section 13.2.2: C and assembly toolchains: added www.iar.com
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