STM8AF6288TCX_技术文档

STM8AF526x/8x/Ax

STM8AF6269/8x/Ax

Automotive 8-bit MCU, with up to 128 Kbyte Flash, data EEPROM,

10-bit ADC, timers, LIN, CAN, USART, SPI, I2C, 3 to 5.5 V

Datasheet - production data

Features

• AEC-Q10x qualified

• Core

LQFP80 14x14 mm

LQFP64 10x10 mm

LQFP48 7x7 mm

– Max f

: 24 MHz

CPU

– Advanced STM8A core with Harvard

architecture and 3-stage pipeline

– Average 1.6 cycles/instruction resulting in

10 MIPS at 16 MHz f

standard benchmark

for industry

CPU

LQFP32 7x7 mm

VFQFP32 5x5 mm

• Memories

– Highly robust I/O design, immune against

current injection

– Program memory: 32 to 128 Kbyte Flash

program; data retention 20 years at 55 °C

– Data memory: up to 2 Kbyte true data

EEPROM; endurance 300 kcycle

– RAM: 6 Kbyte

• Communication interfaces

– High speed 1 Mbit/s CAN 2.0B interface

– USART with clock output for synchronous

operation - LIN master mode

• Clock management

– LINUART LIN 2.2 compliant, master/slave

modes with automatic resynchronization

– Low-power crystal resonator oscillator with

external clock input

– SPI interface up to 10 Mbit/s or f

– I C interface up to 400 Kbit/s

/2

MASTER

2

– Internal, user-trimmable 16 MHz RC and

low-power 128 kHz RC oscillators

– Clock security system with clock monitor

• Analog to digital converter (ADC)

– 10-bit resolution, 2 LSB TUE, 1 LSB

• Reset and supply management

– Wait/auto-wakeup/Halt low-power modes

with user definable clock gating

– Low consumption power-on and power-

down reset

linearity and up to 16 multiplexed channels

• Operating temperature up to 150 °C

• Qualification conforms to AEC-Q100 grade 0

(1)

Table 1. Device summary

• Interrupt management

Reference

Part number

– Nested interrupt controller with 32 vectors

– Up to 37 external interrupts on 5 vectors

STM8AF5268, STM8AF5269,

STM8AF5286, STM8AF5288,

STM8AF5289, STM8AF528A,

STM8AF52A6, STM8AF52A8,

STM8AF52A9, STM8AF52AA

• Timers

STM8AF526x/8x/Ax

(with CAN)

– 2 general purpose 16-bit timers with up to 3

CAPCOM channels each (IC, OC, PWM)

– Advanced control timer: 16-bit, 4 CAPCOM

channels, 3 complementary outputs, dead-

time insertion and flexible synchronization

– 8-bit AR basic timer with 8-bit prescaler

– Auto-wakeup timer

STM8AF6269, STM8AF6286,

STM8AF6288, STM8AF6289,

STM8AF6269/8x/Ax STM8AF628A, STM8AF62A6,

STM8AF62A8, STM8AF62A9,

STM8AF62AA

– Window and independent watchdog timers

1. In the order code, ‘F’ applies to devices with Flash

program memory and data EEPROM. ‘F’ is replaced

by ‘P’ for devices with FASTROM (see Table 2,

Table 3 and Figure 60).

• I/Os

– Up to 68 user pins (11 high sink I/Os)

November 2016

DocID14395 Rev 15

1/125

This is information on a product in full production.

www.st.com

Contents

STM8AF526x/8x/Ax STM8AF6269/8x/Ax

Contents

1

2

3

4

5

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Product line-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Product overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

5.1

STM8A central processing unit (CPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

5.1.1

5.1.2

5.1.3

Architecture and registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

5.2

Single wire interface module (SWIM) and debug module (DM) . . . . . . . . 15

5.2.1

5.2.2

SWIM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Debug module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

5.3

5.4

Interrupt controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Flash program and data EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

5.4.1

5.4.2

5.4.3

5.4.4

Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Write protection (WP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Protection of user boot code (UBC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Read-out protection (ROP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

5.5

Clock controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

5.5.1

5.5.2

5.5.3

5.5.4

5.5.5

5.5.6

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

16 MHz high-speed internal RC oscillator (HSI) . . . . . . . . . . . . . . . . . . 17

128 kHz low-speed internal RC oscillator (LSI) . . . . . . . . . . . . . . . . . . . 18

24 MHz high-speed external crystal oscillator (HSE) . . . . . . . . . . . . . . . 18

External clock input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Clock security system (CSS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

5.6

5.7

Low-power operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

5.7.1

5.7.2

5.7.3

Watchdog timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Auto-wakeup counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Beeper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

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Contents

5.7.4

5.7.5

Advanced control and general purpose timers . . . . . . . . . . . . . . . . . . . 20

Basic timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

5.8

5.9

Analog to digital converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Communication interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

5.9.1

5.9.2

Universal synchronous/asynchronous receiver transmitter (USART) . . 22

Universal asynchronous receiver/transmitter with LIN support

(LINUART) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

5.9.3

5.9.4

5.9.5

Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

2

Inter integrated circuit (I C) interface . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Controller area network interface (beCAN) . . . . . . . . . . . . . . . . . . . . . . 26

5.10 Input/output specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

6

7

Pinouts and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

6.1

6.2

Package pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Alternate function remapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Memory and register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

7.1

7.2

Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

8

Interrupt table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Option bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

9

10

10.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

10.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

10.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

10.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

10.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

10.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

10.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

10.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

10.3.1 VCAP external capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

10.3.2 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

10.3.3 External clock sources and timing characteristics . . . . . . . . . . . . . . . . . 68

10.3.4 Internal clock sources and timing characteristics . . . . . . . . . . . . . . . . . 70

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10.3.5 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

10.3.6 I/O port pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

10.3.7 Reset pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

10.3.8 TIM 1, 2, 3, and 4 electrical specifications . . . . . . . . . . . . . . . . . . . . . . . 80

10.3.9 SPI interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

2

10.3.10 I C interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

10.3.11 10-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

10.3.12 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

11

Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

11.1 LQFP80 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

11.2 LQFP64 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

11.3 LQFP48 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

11.4 LQFP32 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

11.5 VFQFPN32 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

11.6 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

11.6.1

11.6.2

Reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

Selecting the product temperature range . . . . . . . . . . . . . . . . . . . . . . 110

12

13

Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

STM8 development tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

13.1 Emulation and in-circuit debugging tools . . . . . . . . . . . . . . . . . . . . . . . . .112

13.1.1 STice key features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

13.2 Software tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .113

13.2.1 STM8 toolset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

13.2.2 C and assembly toolchains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

13.3 Programming tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .114

14

Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

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List of tables

Table 1.

Table 2.

Table 3.

Table 4.

Table 5.

Table 6.

Table 7.

Table 8.

Table 9.

Table 10.

Table 11.

Table 12.

Table 13.

Table 14.

Table 15.

Table 16.

Table 17.

Table 18.

Table 19.

Table 20.

Table 21.

Table 22.

Table 23.

Table 24.

Table 25.

Table 26.

Device summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

STM8AF526x/8x/Ax product line-up with CAN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

STM8AF6269/8x/Ax product line-up without CAN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Peripheral clock gating bits (CLK_PCKENR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Peripheral clock gating bits (CLK_PCKENR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Advanced control and general purpose timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

TIM4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

ADC naming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Communication peripheral naming correspondence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Legend/abbreviation for the pin description table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

STM8AF526x/8x/Ax and STM8AF6269/8x/Ax pin description . . . . . . . . . . . . . . . . . . . . . . 34

Memory model 128K. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

I/O port hardware register map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

General hardware register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

CPU/SWIM/debug module/interrupt controller registers. . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Temporary memory unprotection registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

STM8A interrupt table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Option bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Option byte description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

Operating lifetime . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

Operating conditions at power-up/power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

Total current consumption in Run, Wait and Slow mode. General conditions

for V apply, T = -40 °C to 150 °C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

DD

A

Table 27.

Total current consumption in Halt and Active-halt modes. General conditions for V

DD

applied. T = -40 °C to 55 °C unless otherwise stated . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

A

Table 28.

Table 29.

Table 30.

Table 31.

Table 32.

Table 33.

Table 34.

Table 35.

Table 36.

Table 37.

Table 38.

Table 39.

Table 40.

Table 41.

Table 42.

Table 43.

Table 44.

Table 45.

Table 46.

Oscillator current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

Programming current consumption. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

Typical peripheral current consumption V = 5.0 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

DD

HSE external clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

HSE oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

HSI oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

Flash program memory/data EEPROM memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

Flash program memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

Data memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

TIM 1, 2, 3, and 4 electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

2

I C characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

ADC accuracy for V

= 5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

DDA

EMS data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

EMI data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

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6

List of tables

STM8AF526x/8x/Ax STM8AF6269/8x/Ax

Table 47.

Table 48.

Table 49.

ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

LQFP80 - 80-pin, 14 x 14 mm low-profile quad flat package

mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat

package mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

LQFP48 - 48-pin, 7 x 7 mm low-profile quad flat package

mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

LQFP32 - 32-pin, 7 x 7 mm low-profile quad flat package

mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

VFQFPN32 - 32-pin, 5 x 5 mm, 0.5 mm pitch very thin profile fine pitch quad

flat package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

Table 50.

Table 51.

Table 52.

Table 53.

Table 54.

Table 55.

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List of figures

Figure 1.

Figure 2.

Figure 3.

Figure 4.

Figure 5.

Figure 6.

Figure 7.

Figure 8.

Figure 9.

STM8AF526x/8x/Ax and STM8AF6269/8x/Ax block diagram . . . . . . . . . . . . . . . . . . . . . . 12

Flash memory organization of STM8A products. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

LQFP 80-pin pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

LQFP 64-pin pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

LQFP 48-pin pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

STM8AF62xx LQFP/VFQFPN 32-pin pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

STM8AF52x6 VFQFPN32 32-pin pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Register and memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Pin loading conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Figure 10. Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

Figure 11. fCPUmax versus VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

Figure 12. External capacitor C

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

EXT

Figure 13. Typ. I

Figure 14. Typ. I

Figure 15. Typ. I

Figure 16. Typ. I

Figure 17. Typ. I

Figure 18. Typ. I

vs. V @f

= 16 MHz, peripherals = on . . . . . . . . . . . . . . . . . . . . . . 67

DD(RUN)HSE

DD(RUN)HSI

DD(WFI)HSE

DD

CPU

vs. f

@ V = 5.0 V, peripherals = on . . . . . . . . . . . . . . . . . . . . . . . 67

CPU

DD

vs. V @ f

= 16 MHz, peripherals = off . . . . . . . . . . . . . . . . . . . . . . 67

= 16 MHz, peripherals = on . . . . . . . . . . . . . . . . . . . . . . 67

DD

CPU

vs. V @ f

DD

CPU

vs. f

@ V = 5.0 V, peripherals = on . . . . . . . . . . . . . . . . . . . . . . . . 67

CPU

DD

vs. V @ f = 16 MHz, peripherals = off . . . . . . . . . . . . . . . . . . . . . . 67

DD(WFI)HSI

DD

CPU

Figure 19. HSE external clock source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

Figure 20. HSE oscillator circuit diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

Figure 21. Typical HSI frequency vs V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

DD

Figure 22. Typical LSI frequency vs V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

DD

Figure 23. Typical V and V vs V @ four temperatures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

IL

IH

DD

Figure 24. Typical pull-up resistance R vs V @ four temperatures . . . . . . . . . . . . . . . . . . . . . . . 75

PU

DD

(1)

Figure 25. Typical pull-up current I vs V @ four temperatures . . . . . . . . . . . . . . . . . . . . . . . . . 76

pu

DD

Figure 26. Typ. V @ V = 3.3 V (standard ports). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

OL

DD

Figure 27. Typ. V @ V = 5.0 V (standard ports). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

OL

DD

Figure 28. Typ. V @ V = 3.3 V (true open drain ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

OL

DD

Figure 29. Typ. V @ V = 5.0 V (true open drain ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

OL

DD

Figure 30. Typ. V @ V = 3.3 V (high sink ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

OL

DD

Figure 31. Typ. V @ V = 5.0 V (high sink ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

OL

DD

Figure 32. Typ. V - V @ V = 3.3 V (standard ports). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

DD

OH

DD

Figure 33. Typ. V - V @ V = 5.0 V (standard ports). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

DD

OH

DD

Figure 34. Typ. V - V @ V = 3.3 V (high sink ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

DD

OH

DD

Figure 35. Typ. V - V @ V = 5.0 V (high sink ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

DD

OH

DD

Figure 36. Typical NRST V and V vs V @ four temperatures . . . . . . . . . . . . . . . . . . . . . . . . . . 78

IL

IH

DD

Figure 37. Typical NRST pull-up resistance R vs V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

PU

DD

Figure 38. Typical NRST pull-up current I vs V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

pu

DD

Figure 39. Recommended reset pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

Figure 40. SPI timing diagram in slave mode and with CPHA = 0. . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

Figure 41. SPI timing diagram in slave mode and with CPHA = 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

Figure 42. SPI timing diagram - master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

Figure 43. Typical application with ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

Figure 44. ADC accuracy characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

Figure 45. LQFP80 - 80-pin, 14 x 14 mm low-profile quad flat package outline . . . . . . . . . . . . . . . . . 90

Figure 46. LQFP80 - 80-pin, 14 x 14 mm low-profile quad flat package

recommended footprint. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

Figure 47. LQFP80 marking example (package top view). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

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8

List of figures

STM8AF526x/8x/Ax STM8AF6269/8x/Ax

Figure 48. LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat package outline . . . . . . . . . . . . . . . . . 94

Figure 49. LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat package

recommended footprint. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

Figure 50. LQFP64 marking example (package top view). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

Figure 51. LQFP48 - 48-pin, 7 x 7 mm low-profile quad flat package outline . . . . . . . . . . . . . . . . . . . 97

Figure 52. LQFP48 - 48-pin, 7 x 7 mm low-profile quad flat package

recommended footprint. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

Figure 53. LQFP48 marking example (package top view). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

Figure 54. LQFP32 - 32-pin, 7 x 7 mm low-profile quad flat package outline . . . . . . . . . . . . . . . . . . 101

Figure 55. LQFP32 - 32-pin, 7 x 7 mm low-profile quad flat package

recommended footprint. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

Figure 56. LQFP32 marking example (package top view). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

Figure 57. VFQFPN32 - 32-pin, 5x5 mm, 0.5 mm pitch very thin profile fine pitch quad

flat package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

Figure 58. VFQFPN32 - 32-pin, 5 x 5 mm, 0.5 mm pitch very thin profile fine pitch quad

flat package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

Figure 59. VFQFPN32 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

1

Figure 60. STM8AF526x/8x/Ax and STM8AF6269/8x/Ax ordering information scheme . . . . . . . . . 111

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Introduction

1

Introduction

This datasheet refers to the STM8AF526x/8x/Ax and STM8AF6269/8x/Ax products with 32

to 128 Kbyte of program memory.

In the order code, the letter ‘F’ refers to product versions with Flash and data EEPROM and

‘P’ to product versions with FASTROM. The identifiers ‘F’ and ‘P’ do not coexist in a given

order code.

The datasheet contains the description of family features, pinout, electrical characteristics,

mechanical data and ordering information.

•

For complete information on the STM8A microcontroller memory, registers and

peripherals, please refer to STM8S series and STM8AF series 8-bit microcontrollers

reference manual (RM0016).

•

For information on programming, erasing and protection of the internal Flash memory

please refer to the STM8S and STM8A Flash programming manual (PM0051).

For information on the debug and SWIM (single wire interface module) refer to the

STM8 SWIM communication protocol and debug module user manual (UM0470).

For information on the STM8 core, please refer to the STM8 CPU programming manual

(PM0044).

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114

Description

STM8AF526x/8x/Ax STM8AF6269/8x/Ax

2

Description

The STM8AF526x/8x/Ax and STM8AF6269/8x/Ax automotive 8-bit microcontrollers

described in this datasheet offer from 32 Kbyte to 128 Kbyte of non volatile memory and

integrated true data EEPROM. They are referred to as high density STM8A devices in

STM8S series and STM8AF series 8-bit microcontrollers reference manual (RM0016).

The STM8AF52 series features a CAN interface.

All devices of the STM8A product line provide the following benefits: reduced system cost,

performance and robustness, short development cycles, and product longevity.

The system cost is reduced thanks to an integrated true data EEPROM for up to 300 k

write/erase cycles and a high system integration level with internal clock oscillators,

wtachdog, and brown-out reset.

Device performance is ensured by 20 MIPS at 24 MHz CPU clock frequency and enhanced

characteristics which include robust I/O, independent watchdogs (with a separate clock

source), and a clock security system.

Short development cycles are guaranteed due to application scalability across a common

family product architecture with compatible pinout, memory map, and modular peripherals.

Full documentation is offered with a wide choice of development tools.

Product longevity is ensured in the STM8A family thanks to their advanced core which is

made in a state-of-the art technology for automotive applications with 3.3 V to 5.5 V

operating supply.

All STM8A and ST7 microcontrollers are supported by the same tools including

STVD/STVP development environment, the STice emulator and a low-cost, third party in-

circuit debugging tool.

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Product line-up

3

Product line-up

..

Table 2. STM8AF526x/8x/Ax product line-up with CAN

High

density

Flash

program (bytes)

memory

Data

EEPROM

(bytes)

10-bit

A/D

chan.

I/0

wakeup

pins

RAM

Timers

(IC/OC/PWM) interfaces

Serial

Order code

Package

(bytes)

STM8AF/P52AA

STM8AF/P528A

STM8AF/P52A9

STM8AF/P5289

STM8AF/P5269

STM8AF/P52A8

STM8AF/P5288

STM8AF/P5268

STM8AF/P5286

128 K

64 K

LQFP80

(14x14)

68/37

52/36

2 K

128 K

64 K

16

1x8-bit: TIM4

3x16-bit: TIM1, LIN(UART),

TIM2, TIM3

(9/9/9)

CAN,

LQFP64

(10x10)

SPI,

USART, I²C

32 K

1 K

2 K

1K

6 K

128 K

64 K

32 K

64 K

LQFP48

(7x7)

10

6

38/35

25/24

1x8-bit: TIM4

3x16-bit: TIM1,

TIM2, TIM3

(8/8/8)

CAN,

LIN(UART),

I²C

VFQFPN32

(5x5)

2 K

STM8AF/P52A6

128 K

Table 3. STM8AF6269/8x/Ax product line-up without CAN

High

density

Flash

program (bytes)

memory

Data

EEPROM

(bytes)

10-bit

A/D

chan.

I/0

wakeup

pins

RAM

Timers

(IC/OC/PWM) interfaces

Serial

Order code

Package

(bytes)

STM8AF/P62AA

STM8AF/P628A

STM8AF/P62A9

STM8AF/P6289

STM8AF/P6269

STM8AF/P62A8

STM8AF/P6288

128 K

64 K

LQFP80

(14x14)

68/37

52/36

38/35

2 K

128 K

64 K

16

1x8-bit: TIM4

LIN(UART),

3x16-bit: TIM1,

SPI,

LQFP64

(10x10)

2 K

1 K

TIM2, TIM3

USART, I²C

(9/9/9)

32 K

6 K

128 K

LQFP48

(7x7)

10

7

64 K

LQFP32

(7x7)

2 K

1x8-bit: TIM4

3x16-bit: TIM1, LIN(UART),

STM8AF/P6286

STM8AF/P62A6

25/23

TIM2, TIM3

(8/8/8)

SPI, I²C

VFQFPN32

(5x5)

128 K

.

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114

Block diagram

STM8AF526x/8x/Ax STM8AF6269/8x/Ax

4

Block diagram

Figure 1. STM8AF526x/8x/Ax and STM8AF6269/8x/Ax block diagram

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12/125

DocID14395 Rev 15

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Block diagram

1. Legend:

ADC: Analog-to-digital converter

beCAN: Controller area network

BOR: Brownout reset

I²C: Inter-integrated circuit multimaster interface

IWDG: Independent window watchdog

LINUART: Local interconnect network universal asynchronous receiver transmitter

POR: Power on reset

SPI: Serial peripheral interface

SWIM: Single wire interface module

USART: Universal synchronous asynchronous receiver transmitter

Window WDG: Window watchdog

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114

Product overview

STM8AF526x/8x/Ax STM8AF6269/8x/Ax

5

Product overview

This section is intended to describe the family features that are actually implemented in the

products covered by this datasheet.

For more detailed information on each feature please refer to STM8S series and STM8AF

series 8-bit microcontrollers reference manual (RM0016).

5.1

STM8A central processing unit (CPU)

The 8-bit STM8A core is a modern CISC core and has been designed for code efficiency

and performance. It contains 21 internal registers (six directly addressable in each

execution context), 20 addressing modes including indexed indirect and relative addressing

and 80 instructions.

5.1.1

Architecture and registers

•

Harvard architecture

3-stage pipeline

32-bit wide program memory bus with single cycle fetching for most instructions

X and Y 16-bit index registers, enabling indexed addressing modes with or without

offset and read-modify-write type data manipulations

•

8-bit accumulator

24-bit program counter with 16-Mbyte linear memory space

16-bit stack pointer with access to a 64 Kbyte stack

8-bit condition code register with seven condition flags for the result of the last

instruction.

5.1.2

5.1.3

Addressing

•

20 addressing modes

Indexed indirect addressing mode for look-up tables located anywhere in the address

space

•

Stack pointer relative addressing mode for efficient implementation of local variables

and parameter passing

Instruction set

•

80 instructions with 2-byte average instruction size

Standard data movement and logic/arithmetic functions

8-bit by 8-bit multiplication

16-bit by 8-bit and 16-bit by 16-bit division

Bit manipulation

Data transfer between stack and accumulator (push/pop) with direct stack access

Data transfer using the X and Y registers or direct memory-to-memory transfers

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Product overview

5.2

Single wire interface module (SWIM) and debug module (DM)

5.2.1

SWIM

The single wire interface module, SWIM, together with an integrated debug module, permits

non-intrusive, real-time in-circuit debugging and fast memory programming. The interface

can be activated in all device operation modes and can be connected to a running device

(hot plugging).The maximum data transmission speed is 145 bytes/ms.

5.2.2

Debug module

The non-intrusive debugging module features a performance close to a full-flavored

emulator. Besides memory and peripheral operation, CPU operation can also be monitored

in real-time by means of shadow registers.

•

R/W of RAM and peripheral registers in real-time

R/W for all resources when the application is stopped

Breakpoints on all program-memory instructions (software breakpoints), except the

interrupt vector table

•

Two advanced breakpoints and 23 predefined breakpoint configurations

5.3

5.4

Interrupt controller

•

Nested interrupts with three software priority levels

24 interrupt vectors with hardware priority

Five vectors for external interrupts (up to 37 depending on the package)

Trap and reset interrupts

Flash program and data EEPROM

•

32 Kbytes to 128 Kbytes of high density single voltage Flash program memory

Up to 2 Kbytes true (not emulated) data EEPROM

Read while write: writing in the data memory is possible while executing code in the

Flash program memory.

The whole Flash program memory and data EEPROM are factory programmed with 0x00.

5.4.1

Architecture

•

The memory is organized in blocks of 128 bytes each

Read granularity: 1 word = 4 bytes

Write/erase granularity: 1 word (4 bytes) or 1 block (128 bytes) in parallel

Writing, erasing, word and block management is handled automatically by the memory

interface.

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5.4.2

Write protection (WP)

Write protection in application mode is intended to avoid unintentional overwriting of the

memory. The write protection can be removed temporarily by executing a specific sequence

in the user software.

5.4.3

Protection of user boot code (UBC)

If the user chooses to update the Flash program memory using a specific boot code to

perform in application programming (IAP), this boot code needs to be protected against

unwanted modification.

In the STM8A a memory area of up to 128 Kbytes can be protected from overwriting at user

option level. Other than the standard write protection, the UBC protection can exclusively be

modified via the debug interface, the user software cannot modify the UBC protection

status.

The UBC memory area contains the reset and interrupt vectors and its size can be adjusted

in increments of 512 bytes by programming the UBC and NUBC option bytes

(see Section 9: Option bytes on page 54).

Figure 2. Flash memory organization of STM8A products

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5.4.4

Read-out protection (ROP)

The STM8A provides a read-out protection of the code and data memory which can be

activated by an option byte setting (see the ROP option byte in section 10).

The read-out protection prevents reading and writing Flash program memory, data memory

and option bytes via the debug module and SWIM interface. This protection is active in all

device operation modes. Any attempt to remove the protection by overwriting the ROP

option byte triggers a global erase of the program and data memory.

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The ROP circuit may provide a temporary access for debugging or failure analysis. The

temporary read access is protected by a user defined, 8-byte keyword stored in the option

byte area. This keyword must be entered via the SWIM interface to temporarily unlock the

device.

If desired, the temporary unlock mechanism can be permanently disabled by the user

through OPT6/NOPT6 option bytes.

5.5

Clock controller

The clock controller distributes the system clock coming from different oscillators to the core

and the peripherals. It also manages clock gating for low-power modes and ensures clock

robustness.

5.5.1

Features

•

Clock sources

–

16 MHz high-speed internal RC oscillator (HSI)

128 kHz low-speed internal RC (LSI)

1-24 MHz high-speed external crystal (HSE)

Up to 24 MHz high-speed user-external clock (HSE user-ext)

•

Reset: After reset the microcontroller restarts by default with an internal 2-MHz clock

(16 MHz/8). The clock source and speed can be changed by the application program

as soon as the code execution starts.

Safe clock switching: Clock sources can be changed safely on the fly in Run mode

through a configuration register. The clock signal is not switched until the new clock

source is ready. The design guarantees glitch-free switching.

•

Clock management: To reduce power consumption, the clock controller can stop the

clock to the core, individual peripherals or memory.

Wakeup: In case the device wakes up from low-power modes, the internal RC

oscillator (16 MHz/8) is used for quick startup. After a stabilization time, the device

switches to the clock source that was selected before Halt mode was entered.

•

Clock security system (CSS): The CSS permits monitoring of external clock sources

and automatic switching to the internal RC (16 MHz/8) in case of a clock failure.

Configurable main clock output (CCO): This feature permits to output a clock signal

for use by the application.

5.5.2

16 MHz high-speed internal RC oscillator (HSI)

•

Default clock after reset 2 MHz (16 MHz/8)

Fast wakeup time

User trimming

The register CLK_HSITRIMR with two trimming bits plus one additional bit for the sign

permits frequency tuning by the application program. The adjustment range covers all

possible frequency variations versus supply voltage and temperature. This trimming does

not change the initial production setting.

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5.5.3

128 kHz low-speed internal RC oscillator (LSI)

The frequency of this clock is 128 kHz and it is independent from the main clock. It drives

the independent watchdog or the AWU wakeup timer.

In systems which do not need independent clock sources for the watchdog counters, the

128 kHz signal can be used as the system clock. This configuration has to be enabled by

setting an option byte (OPT3/OPT3N, bit LSI_EN).

5.5.4

24 MHz high-speed external crystal oscillator (HSE)

The external high-speed crystal oscillator can be selected to deliver the main clock in

normal Run mode. It operates with quartz crystals and ceramic resonators.

•

Frequency range: 1 MHz to 24 MHz

Crystal oscillation mode: preferred fundamental

I/Os: standard I/O pins multiplexed with OSCIN, OSCOUT

5.5.5

5.5.6

External clock input

An external clock signal can be applied to the OSCIN input pin of the crystal oscillator. The

frequency range is 0 to 24 MHz.

Clock security system (CSS)

The clock security system protects against a system stall in case of an external crystal clock

failure.

In case of a clock failure an interrupt is generated and the high-speed internal clock (HSI) is

automatically selected with a frequency of 2 MHz (16 MHz/8).

Table 4. Peripheral clock gating bits (CLK_PCKENR1)

Control bit

Peripheral

PCKEN17

PCKEN16

PCKEN15

PCKEN14

PCKEN13

PCKEN12

PCKEN11

PCKEN10

TIM1

TIM3

TIM2

TIM4

LINUART

USART

SPI

I²C

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Product overview

Table 5. Peripheral clock gating bits (CLK_PCKENR2)

Control bit

Peripheral

PCKEN27

PCKEN26

PCKEN25

PCKEN24

PCKEN23

PCKEN22

PCKEN21

PCKEN20

CAN

Reserved

ADC

AWU

Reserved

5.6

Low-power operating modes

For efficient power management, the application can be put in one of four different low-

power modes. Users can configure each mode to obtain the best compromise between

lowest power consumption, fastest start-up time and available wakeup sources.

•

Wait mode

In this mode, the CPU is stopped but peripherals are kept running. The wakeup is

performed by an internal or external interrupt or reset.

•

Active-halt mode with regulator on

In this mode, the CPU and peripheral clocks are stopped. An internal wakeup is

generated at programmable intervals by the auto wake up unit (AWU). The main

voltage regulator is kept powered on, so current consumption is higher than in Active-

halt mode with regulator off, but the wakeup time is faster. Wakeup is triggered by the

internal AWU interrupt, external interrupt or reset.

•

Active-halt mode with regulator off

This mode is the same as Active-halt with regulator on, except that the main voltage

regulator is powered off, so the wake up time is slower.

Halt mode

CPU and peripheral clocks are stopped, the main voltage regulator is powered off.

Wakeup is triggered by external event or reset.

In all modes the CPU and peripherals remain permanently powered on, the system clock is

applied only to selected modules. The RAM content is preserved and the brown-out reset

circuit remains activated.

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5.7

Timers

5.7.1

Watchdog timers

The watchdog system is based on two independent timers providing maximum security to

the applications. The watchdog timer activity is controlled by the application program or

option bytes. Once the watchdog is activated, it cannot be disabled by the user program

without going through reset.

Window watchdog timer

The window watchdog is used to detect the occurrence of a software fault, usually

generated by external interferences or by unexpected logical conditions, which cause the

application program to abandon its normal sequence.

The window function can be used to trim the watchdog behavior to match the application

timing perfectly. The application software must refresh the counter before time-out and

during a limited time window. If the counter is refreshed outside this time window, a reset is

issued.

Independent watchdog timer

The independent watchdog peripheral can be used to resolve malfunctions due to hardware

or software failures.

It is clocked by the 128 kHz LSI internal RC clock source, and thus stays active even in case

of a CPU clock failure. If the hardware watchdog feature is enabled through the device

option bits, the watchdog is automatically enabled at power-on, and generates a reset

unless the key register is written by software before the counter reaches the end of count.

5.7.2

Auto-wakeup counter

This counter is used to cyclically wakeup the device in Active-halt mode. It can be clocked

by the internal 128 kHz internal low-frequency RC oscillator or external clock.

LSI clock can be internally connected to TIM3 input capture channel 1 for calibration.

5.7.3

5.7.4

Beeper

This function generates a rectangular signal in the range of 1, 2 or 4 kHz which can be

output on a pin. This is useful when audible sounds without interference need to be

generated for use in the application.

Advanced control and general purpose timers

STM8A devices described in this datasheet, contain up to three 16-bit advanced control and

general purpose timers providing nine CAPCOM channels in total. A CAPCOM channel can

be used either as input compare, output compare or PWM channel. These timers are

named TIM1, TIM2 and TIM3.

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Table 6. Advanced control and general purpose timers

Counter Counter Prescaler

Inverted Repetition trigger External Break

Timer

TIM1

TIM2

Channels

width

type

factor

outputs

counter

unit

trigger

input

16-bit

Up/down 1 to 65536

4

3

Yes

2ⁿ

16-bit

Up

None

No

n = 0 to 15

2ⁿ

TIM3

Up

2

n = 0 to 15

TIM1 - advanced control timer

This is a high-end timer designed for a wide range of control applications. With its

complementary outputs, dead-time control and center-aligned PWM capability, the field of

applications is extended to motor control, lighting and bridge driver.

•

16-bit up, down and up/down AR (auto-reload) counter with 16-bit fractional prescaler.

Four independent CAPCOM channels configurable as input capture, output compare,

PWM generation (edge and center aligned mode) and single pulse mode output

•

Trigger module which allows the interaction of TIM1 with other on-chip peripherals. In

the present implementation it is possible to trigger the ADC upon a timer event.

•

External trigger to change the timer behavior depending on external signals

Break input to force the timer outputs into a defined state

Three complementary outputs with adjustable dead time

Interrupt sources: 4 x input capture/output compare, 1 x overflow/update, 1 x break

TIM2, TIM3 - 16-bit general purpose timers

•

16-bit auto-reload up-counter

15-bit prescaler adjustable to fixed power of two ratios 1…32768

Timers with three or two individually configurable CAPCOM channels

Interrupt sources: 2 or 3 x input capture/output compare, 1 x overflow/update

5.7.5

Basic timer

The typical usage of this timer (TIM4) is the generation of a clock tick.

Table 7. TIM4

Counter Counter Prescaler

Inverted Repetition trigger External Break

Timer

Channels

width

type

factor

outputs

counter

unit

trigger

input

2ⁿ

TIM4

8-bit

Up

0

None

No

n = 0 to 7

•

8-bit auto-reload, adjustable prescaler ratio to any power of two from 1 to 128

Clock source: master clock

Interrupt source: 1 x overflow/update

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5.8

Analog to digital converter (ADC)

The STM8A products described in this datasheet contain a 10-bit successive approximation

ADC with up to 16 multiplexed input channels, depending on the package.

The ADC name differs between the datasheet and the STM8A/S reference manual (see

Table 8).

Table 8. ADC naming

Peripheral name in reference manual

Peripheral name in datasheet

(RM0016)

ADC

ADC2

ADC features

•

10-bit resolution

Single and continuous conversion modes

Programmable prescaler: f

divided by 2 to 18

MASTER

Conversion trigger on timer events, and external events

Interrupt generation at end of conversion

Selectable alignment of 10-bit data in 2 x 8 bit result registers

Shadow registers for data consistency

ADC input range: V

≤V ≤V

IN DDA

SSA

Schmitt-trigger on analog inputs can be disabled to reduce power consumption

5.9

Communication interfaces

The following sections give a brief overview of the communication peripheral. Some

peripheral names differ between the datasheet and STM8S series and STM8AF series 8-bit

microcontrollers reference manual (see Table 9).

Table 9. Communication peripheral naming correspondence

Peripheral name in reference manual

Peripheral name in datasheet

(RM0016)

USART

UART1

UART3

LINUART

5.9.1

Universal synchronous/asynchronous receiver transmitter (USART)

The devices covered by this datasheet contain one USART interface. The USART can

operate in standard SCI mode (serial communication interface, asynchronous) or in SPI

emulation mode. It is equipped with a 16 bit fractional prescaler. It features LIN master

support.

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Product overview

Detailed feature list:

•

Full duplex, asynchronous communications

NRZ standard format (mark/space)

High-precision baud rate generator system

–

Common programmable transmit and receive baud rates up to f

/16

MASTER

•

Programmable data word length (8 or 9 bits)

Configurable stop bits: Support for 1 or 2 stop bits

LIN master mode:

–

LIN break and delimiter generation

LIN break and delimiter detection with separate flag and interrupt source for

readback checking.

•

Transmitter clock output for synchronous communication

Separate enable bits for transmitter and receiver

Transfer detection flags:

–

Receive buffer full

Transmit buffer empty

End of transmission flags

•

Parity control:

–

Transmits parity bit

Checks parity of received data byte

Four error detection flags:

–

Overrun error

Noise error

Frame error

Parity error

•

Six interrupt sources with flags:

–

Transmit data register empty

Transmission complete

Receive data register full

Idle line received

Parity error

LIN break and delimiter detection

•

Two interrupt vectors:

–

Transmitter interrupt

Receiver interrupt

•

Reduced power consumption mode

Wakeup from mute mode (by idle line detection or address mark detection)

Two receiver wakeup modes:

–

Address bit (MSB)

Idle line

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5.9.2

Universal asynchronous receiver/transmitter with LIN support

(LINUART)

The devices covered by this datasheet contain one LINUART interface. The interface is

available on all the supported packages. The LINUART is an asynchronous serial

communication interface which supports extensive LIN functions tailored for LIN slave

applications. In LIN mode it is compliant to the LIN standards rev 1.2 to rev 2.2.

Detailed feature list:

LIN mode

Master mode

•

LIN break and delimiter generation

LIN break and delimiter detection with separate flag and interrupt source for read back

checking.

Slave mode

•

Autonomous header handling – one single interrupt per valid header

Mute mode to filter responses

Identifier parity error checking

LIN automatic resynchronization, allowing operation with internal RC oscillator (HSI)

clock source

•

Break detection at any time, even during a byte reception

Header errors detection:

–

Delimiter too short

Synch field error

Deviation error (if automatic resynchronization is enabled)

Framing error in synch field or identifier field

Header time-out

UART mode

•

Full duplex, asynchronous communications - NRZ standard format (mark/space)

High-precision baud rate generator

A common programmable transmit and receive baud rates up to f

–

/16

MASTER

•

Programmable data word length (8 or 9 bits) – 1 or 2 stop bits – parity control

Separate enable bits for transmitter and receiver

Error detection flags

Reduced power consumption mode

Multi-processor communication - enter mute mode if address match does not occur

Wakeup from mute mode (by idle line detection or address mark detection)

Two receiver wakeup modes:

–

Address bit (MSB)

Idle line

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5.9.3

Serial peripheral interface (SPI)

The devices covered by this datasheet contain one SPI. The SPI is available on all the

supported packages.

•

Maximum speed: 10 Mbit/s or f

/2 for master, 8 Mbit/s or f

/2 for slave

MASTER

Full duplex synchronous transfers

Simplex synchronous transfers on two lines with a possible bidirectional data line

Master or slave operation - selectable by hardware or software

CRC calculation

1 byte Tx and Rx buffer

Slave mode/master mode management by hardware or software for both master and

slave

•

Programmable clock polarity and phase

Programmable data order with MSB-first or LSB-first shifting

Dedicated transmission and reception flags with interrupt capability

SPI bus busy status flag

Hardware CRC feature for reliable communication:

–

CRC value can be transmitted as last byte in Tx mode

CRC error checking for last received byte

2

5.9.4

Inter integrated circuit (I C) interface

2

The devices covered by this datasheet contain one I C interface. The interface is available

on all the supported packages.

2

•

I C master features:

–

Clock generation

Start and stop generation

2

I C slave features:

2

–

Programmable I C address detection

Stop bit detection

•

Generation and detection of 7-bit/10-bit addressing and general call

Supports different communication speeds:

–

Standard speed (up to 100 kHz),

Fast speed (up to 400 kHz)

•

Status flags:

–

Transmitter/receiver mode flag

End-of-byte transmission flag

2

I C busy flag

Error flags:

–

Arbitration lost condition for master mode

Acknowledgement failure after address/data transmission

Detection of misplaced start or stop condition

Overrun/underrun if clock stretching is disabled

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•

Interrupt:

–

Successful address/data communication

Error condition

Wakeup from Halt

•

Wakeup from Halt on address detection in slave mode

5.9.5

Controller area network interface (beCAN)

The beCAN controller (basic enhanced CAN), interfaces the CAN network and supports the

CAN protocol version 2.0A and B. It is equipped with a receive FIFO and a very versatile

filter bank. Together with a filter match index, this allows a very efficient message handling in

today’s car network architectures. The CPU is significantly unloaded. The maximum

transmission speed is 1 Mbit/s.

Transmission

•

Three transmit mailboxes

Configurable transmit priority by identifier or order request

Reception

•

11- and 29-bit ID

1 receive FIFO (3 messages deep)

Software-efficient mailbox mapping at a unique address space

FMI (filter match index) stored with message for quick message association

Configurable FIFO overrun

Time stamp on SOF reception

6 filter banks, 2 x 32 bytes (scalable to 4 x 16-bit) each, enabling various masking

configurations, such as 12 filters for 29-bit ID or 48 filters for 11-bit ID.

•

Filtering modes (mixable):

–

Mask mode permitting ID range filtering

ID list mode

Interrupt management

•

Maskable interrupt

Software-efficient mailbox mapping at a unique address space

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5.10

Input/output specifications

The product features four I/O types:

•

Standard I/O 2 MHz

Fast I/O up to 10 MHz

High sink 8 mA, 2 MHz

2

True open drain (I C interface)

To decrease EMI (electromagnetic interference), high sink I/Os have a limited maximum

slew rate. The rise and fall times are similar to those of standard I/Os.

The analog inputs are equipped with a low leakage analog switch. Additionally, the schmitt-

trigger input stage on the analog I/Os can be disabled in order to reduce the device standby

consumption.

STM8A I/Os are designed to withstand current injection. For a negative injection current of

4 mA, the resulting leakage current in the adjacent input does not exceed 1 µA. Thanks to

this feature, external protection diodes against current injection are no longer required.

Caution:

In STM8AF5286UC device, the following I/O ports are not automatically configured by

hardware: PA3, PA4, PA5, PA6, PF4, PB6, PB7, PE0, PE1, PE2, PE3, PE6, PE7.

As a consequence, they must be put into one of the following configurations by software:

- configured as input with internal pull-up/down resistor,

- configured as output push-pull low.

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6

Pinouts and pin description

6.1

Package pinouts

Figure 3. LQFP 80-pin pinout

60

59

58

57

56

55

54

53

52

51

50

49

48

47

46

45

44

43

42

41

1

2

3

4

5

6

7

8

NRST

OSCIN/PA1

OSCOUT/PA2

PI3

PI2

PI1

PI0

V

SSIO_1

V

PG4

PG3

PG2

PG1/CAN_RX

PG0/CAN_TX

PC7/SPI_MISO

PC6/SPI_MOSI

SS

VCAP

V

DD

(1)

V

DDIO_1

(1)

9

TIM2_CH3/PA3

USART_RX/PA4

USART_TX/PA5

USART_CK/PA6

(HS) PH0

10

11

12

13

14

15

16

17

18

19

20

V

DDIO_2

SSIO_2

(HS) PH1

PC5/SPI_SCK

PH2

PH3

AIN15/PF7

AIN14/PF6

AIN13/PF5

AIN12/PF4

PC4 (HS)/TIM1_CH4

PC3 (HS)/TIM1_CH3

PC2 (HS)/TIM1_CH2

PC1 (HS)/TIM1_CH1

PC0/ADC_ETR

PE5/SPI_NSS

1. The CAN interface is only available on STM8AF52xx product lines.

2. (HS) stands for high sink capability.

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Pinouts and pin description

Figure 4. LQFP 64-pin pinout

64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49

48

PI0

NRST

OSCIN/PA1

OSCOUT/PA2

1

PG4

PG3

PG2

PG1/CAN_RX

PG0/CAN_TX

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

2

3

4

5

6

7

8

9

V

SSIO_1

(1)

V

SS

(1)

VCAP

PC7/SPI_MISO

PC6/SPI_MOSI

V

DD

V

DDIO_1

V

TIM2_CH3/PA3

USART_RX/PA4

USART_TX/PA5

USART_CK/PA6

DDIO_2

V

10

11

12

SSIO_2

PC5/SPI_SCK

PC4 (HS)/TIM1_CH4

PC3 (HS)/TIM1_CH3

PC2 (HS)/TIM1_CH2

PC1 (HS)/TIM1_CH1

PE5/SPI_NSS

AIN15/PF7 13

AIN14/PF6

14

AIN13/PF5 15

AIN12/PF4 16

1718 1920212223242526272829303132

1. The CAN interface is only available on STM8AF52xx product lines.

2. HS stands for high sink capability.

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Figure 5. LQFP 48-pin pinout

48 47 46 45 4443424140393837

36

NRST

OSCIN/PA1

PG1/CAN_RX

PG0/CAN_TX

35

1

2

OSCOUT/PA2

3

4

34 PC7/SPI_MISO

33 PC6/SPI_MOSI

V

SSIO_1

V

32

31

30

29

28

27

26

25

5

6

7

8

9

10

11

V

SS

DDIO_2

VCAP

SSIO_2

V

PC5/SPI_SCK

DD

V

PC4 (HS)/TIM1_CH4

PC3 (HS)/TIM1_CH3

PC2 (HS)/TIM1_CH2

PC1 (HS)/TIM1_CH1

PE5/SPI_NSS

DDIO_1

TIM2_CH3/PA3

USART_RX/PA4

USART_TX/PA5

USART_CK/PA6

12

24

1314 15161718192021 2223

1. The CAN interface is only available on STM8AF52xx product lines.

2. HS stands for high sink capability.

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Pinouts and pin description

Figure 6. STM8AF62xx LQFP/VFQFPN 32-pin pinout

32 31 30 29 28 27 26 25

24

NRST

OSCIN/PA1

OSCOUT/PA2

1

2

3

4

5

6

7

8

PC7/SPI_MISO

PC6/SPI_MOSI

PC5/SPI_SCK

PC4 (HS)/TIM1_CH4

PC3 (HS)/TIM1_CH3

PC2 (HS)/TIM1_CH2

PC1 (HS)/TIM1_CH1

PE5/SPI_NSS

23

22

21

20

19

18

17

V

SS

VCAP

V

DD

V

DDIO

AIN12/PF4

9 101112 13141516

1. HS stands for high sink capability.

DocID14395 Rev 15

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Figure 7. STM8AF52x6 VFQFPN32 32-pin pinout

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1. The following I/O ports are not automatically configured by hardware: PA3, PA4, PA5, PA6, PF4, PB6,

PB7, PE0, PE1, PE2, PE3, PE6, PE7. As a consequence, they must be put into one of the following

configurations by software:

- configured as input with internal pull-up/down resistor,

- configured as output push-pull low.

2. HS stands for high sink capability.

32/125

DocID14395 Rev 15

STM8AF526x/8x/Ax STM8AF6269/8x/Ax

Pinouts and pin description

Table 10. Legend/abbreviation for the pin description table

I= input, O = output, S = power supply

Type

Input

CM = CMOS (standard for all I/Os)

HS = high sink (8 mA)

Level

Output

O1 = Standard (up to 2 MHz)

O2 = Fast (up to 10 MHz)

O3 = Fast/slow programmability with slow as default state after reset

O4 = Fast/slow programmability with fast as default state after reset

Output speed

Input

float = floating, wpu = weak pull-up

Port and control

configuration

Output

T = true open drain, OD = open drain, PP = push pull

Bold X (pin state after reset release).

Reset state

Unless otherwise specified, the pin state is the same during the reset phase (i.e.

“under reset”) and after internal reset release (i.e. at reset state).

DocID14395 Rev 15

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114

Pinouts and pin description

STM8AF526x/8x/Ax STM8AF6269/8x/Ax

Table 11. STM8AF526x/8x/Ax and STM8AF6269/8x/Ax pin description

Pin number

Input

Output

Main

function

(after

Alternate

function

after remap

[option bit]

Default

alternate

function

Pin name

reset)

1

2

1

2

1

2

1

2

1

2

NRST

I/O

-

X

-

Reset

-

Resonator/

crystal in

PA1/OSCIN⁽¹⁾I/O

X

O1

X

Port A1

Port A2

Resonator/

crystal out

3

PA2/OSCOUT I/O

X

X X

-

O1

X

-

4

5

4

5

4

5

-

V_{SSIO_1}

V_SS

S

-

I/O ground

-

4

Digital ground

1.8 V regulator

capacitor

6

5

VCAP

S

-

7

8

7

8

7

8

6

7

6

7

V_DD

S

-

Digital power supply

I/O power supply

-

V_{DDIO_1}

Timer 2 -

Port A3

TIM3_CH1

[AFR1]

9

-

PA3/TIM2_CH3 I/O

PA4/USART_RX I/O

PA5/USART_TX I/O

PA6/USART_CK

X

X X

-

O1

O3

X

channel 3

USART

Port A4

10 10 10

11 11 11

-

receive

USART

Port A5

transmit

USART

12 12 12

-

8

I/O

X

X X

-

O3

X

Port A6

synchro

-

(2)

nous clock

13

14

15

16

-

PH0

PH1

PH2

PH3

I/O

X

-

HS O3

X

Port H0

Port H1

Port H2

Port H3

-

O1

Analog

input 15

17 13

18 14

19 15

20 16

21 17

-

PF7/AIN15

PF6/AIN14

PF5/AIN13

PF4/AIN12

PF3/AIN11

I/O

X

-

O1

X

Port F7

Port F6

Port F5

Port F4

Port F3

-

Analog

input 14

Analog

input 13

-

Analog

input 12

8

-

Analog

input 11

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DocID14395 Rev 15

STM8AF526x/8x/Ax STM8AF6269/8x/Ax

Pinouts and pin description

Table 11. STM8AF526x/8x/Ax and STM8AF6269/8x/Ax pin description (continued)

Pin number

Input

Output

Main

function

(after

Alternate

function

after remap

[option bit]

Default

alternate

function

Pin name

reset)

ADC positive

22 18

-

V_REF+

S

-

reference

voltage

-

23 19 13

9

V_DDA

V_SSA

S

-

Analog power supply

Analog ground

-

24 20 14 10 10

ADC negative

reference voltage

25 21

26 22

-

V_REF-

S

-

Analog

Port F0

PF0/AIN10

PB7/AIN7

PB6/AIN6

PB5/AIN5

PB4/AIN4

PB3/AIN3

PB2/AIN2

PB1/AIN1

PB0/AIN0

I/O

X

O1

X

input 10

Analog

Port B7

27 23 15

28 24 16

X X

input 7

Analog

Port B6

input 6

Analog

Port B5

I²C_SDA

[AFR6]

I²C_SCL

[AFR6]

29 25 17 11 11

30 26 18 12 12

31 27 19 13 13

32 28 20 14 14

33 29 21 15 15

34 30 22 16 16

input 5

Analog

Port B4

input 4

Analog

Port B3

TIM1_ETR

[AFR5]

input 3

Analog

Port B2

TIM1_CH3N

[AFR5]

input

Analog

Port B1

TIM1_CH2N

[AFR5]

input 1

Analog

Port B0

TIM1_CH1N

[AFR5]

input 0

Timer 1 -

35

36

37

-

PH4/TIM1_ETR I/O

X

-

O1

X

Port H4

Port H5

Port H6

trigger

input

-

Timer 1 -

inverted

channel 3

PH5/

I/O

TIM1_CH3N

Timer 1 -

inverted

channel 2

PH6/

I/O

TIM1_CH2N

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114

Pinouts and pin description

STM8AF526x/8x/Ax STM8AF6269/8x/Ax

Table 11. STM8AF526x/8x/Ax and STM8AF6269/8x/Ax pin description (continued)

Pin number

Input

Output

Main

function

(after

Alternate

function

after remap

[option bit]

Default

alternate

function

Pin name

reset)

Timer 1 -

inverted

channel 2

PH7/

TIM1_CH1N

38

-

I/O

X

-

O1

X

Port H7

-

Analog

input 8

39 31 23

40 32 24

PE7/AIN8

PE6/AIN9

I/O

X

-

O1

X

Port E7

Port E6

-

Analog

input 9

X X

SPI

master/

slave

41 33 25 17 17 PE5/SPI_NSS⁽²⁾I/O

X

-

O1

X

Port E5

Port C0

-

select

ADC

trigger

input

42

-

PC0/ADC_ETR I/O

X X

Timer 1 -

channel 1

43 34 26 18 18 PC1/TIM1_CH1 I/O

44 35 27 19 19 PC2/TIM1_CH2 I/O

45 36 28 20 20 PC3/TIM1_CH3 I/O

X

X X HS O3

X

Port C1

Port C2

Port C3

Port C4

-

Timer 1-

channel 2

Timer 1 -

channel 3

Timer 1 -

channel 4

46 37 29 21 21 PC4/TIM1_CH4 I/O

47 38 30 22 22 PC5/SPI_SCK⁽²⁾I/O

X

-

X X

-

O3

X

-

X

-

Port C5 SPI clock

I/O ground

-

48 39 31

49 40 32

-

V_{SSIO_2}

V_{DDIO_2}

S

-

I/O power supply

SPImaster

out/

slave in

PC6/SPI_MOSI

50 41 33 23

51 42 34 24

-

I/O

X

X X

-

O3

X

Port C6

-

(2)

SPImaster

in/ slave

out

PC7/SPI_MISO

X

-

O3

O1

X

Port C7

Port G0

-

(2)

CAN

transmit

52 43 35

53 44 36

-

23 PG0/CAN_TX I/O

24 PG1/CAN_RX I/O

X

-

CAN

receive

-

X

-

O1

X

Port G1

Port G2

-

54 45

-

PG2

I/O

-

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Pinouts and pin description

Table 11. STM8AF526x/8x/Ax and STM8AF6269/8x/Ax pin description (continued)

Pin number

Input

Output

Main

function

(after

Alternate

function

after remap

[option bit]

Default

alternate

function

Pin name

reset)

55 46

56 47

57 48

-

PG3

PG4

PI0

I/O

X

-

O1

X

Port G3

Port G4

Port I0

Port I1

Port I2

Port I3

Port I4

Port I5

Port G5

Port G6

Port G7

Port E4

-

X

58

59

60

61

62

-

PI1

PI2

PI3

PI4

PI5

63 49

64 50

65 51

66 52

PG5

PG6

PG7

PE4

X X

Timer 1 -

break input

67 53 37

-

PE3/TIM1_BKIN I/O

X

X X

-

O1

X

Port E3

-

68 54 38

69 55 39

-

PE2/I²C_SDA I/O

PE1/I²C_SCL I/O

X

-

X

-

O1 T⁽³⁾

-

Port E2

Port E1

I²C data

I²C clock

-

Configurab

le clock

70 56 40

-

PE0/CLK_CCO I/O

X

X X

-

O3

X

Port E0

-

output

71

72

-

PI6

PI7

I/O

X

-

O1

X

Port I6

Port I7

-

TIM1_BKIN

[AFR3]/

CLK_CCO

[AFR2]

Timer 3 -

channel 2

73 57 41 25 25 PD0/TIM3_CH2 I/O

X

X X HS O3

X

Port D0

SWIMdata

interface

74 58 42 26 26

PD1/SWIM⁽⁴⁾

I/O

X

X X HS O4

X X HS O3

X

Port D1

Port D2

Port D3

Port D4

-

Timer 3 -

channel 1

TIM2_CH3

[AFR1]

75 59 43 27 27 PD2/TIM3_CH1 I/O

Timer 2 -

channel 2

ADC_ETR

[AFR0]

76 60 44 28 28 PD3/TIM2_CH2 I/O

PD4/TIM2_CH1/

Timer 2 - BEEP output

channel 1 [AFR7]

77 61 45 29 29

I/O

BEEP

DocID14395 Rev 15

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114

Pinouts and pin description

STM8AF526x/8x/Ax STM8AF6269/8x/Ax

Table 11. STM8AF526x/8x/Ax and STM8AF6269/8x/Ax pin description (continued)

Pin number

Input

Output

Main

function

(after

Alternate

function

after remap

[option bit]

Default

alternate

function

Pin name

reset)

LINUART

data

transmit

PD5/

LINUART_TX

78 62 46 30 30

I/O

X

X X

-

O1

X

Port D5

-

LINUART

data

receive

PD6/

LINUART_RX

79 63 47 31 31

80 64 48 32 32

I/O

X

X X

-

O1

X

Port D6

Port D7

-

Top level

interrupt

PD7/TLI⁽⁵⁾

1. In Halt/Active-halt mode, this pin behaves as follows:

- The input/output path is disabled.

- If the HSE clock is used for wakeup, the internal weak pull-up is disabled.

- If the HSE clock is off, the internal weak pull-up setting is used. It is configured through Px_CR1[7:0] bits of the

corresponding port control register. Px_CR1[7:0] bits must be set correctly to ensure that the pin is not left floating in

Halt/Active-halt mode.

2. SPI and USTART are not available in STM8AF5286UC, refer to Figure 7: STM8AF52x6 VFQFPN32 32-pin pinout for the

pin names.

3. In the open-drain output column, ‘T’ defines a true open-drain I/O (P-buffer, week pull-up and protection diode to V_DDare

not implemented)

4. The PD1 pin is in input pull-up during the reset phase and after reset release.

5. If this pin is configured as interrupt pin, it will trigger the TLI.

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Pinouts and pin description

6.2

Alternate function remapping

As shown in the rightmost column of Table 11, some alternate functions can be remapped at

different I/O ports by programming one of eight AFR (alternate function remap) option bits.

Refer to Section 9: Option bytes on page 54. When the remapping option is active, the

default alternate function is no longer available.

To use an alternate function, the corresponding peripheral must be enabled in the peripheral

registers.

Alternate function remapping does not effect GPIO capabilities of the I/O ports (see the

GPIO section of STM8S series and STM8AF series 8-bit microcontrollers reference manual,

RM0016).

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114

Memory and register map

STM8AF526x/8x/Ax STM8AF6269/8x/Ax

7

Memory and register map

7.1

Memory map

Figure 8. Register and memory map

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40/125

DocID14395 Rev 15

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Memory and register map

Table 12. Memory model 128K

Flash program

memory size

RAM end

Stack roll-over

address

memory end

RAM size

address

128 K

64 K

32 K

0x00 27FFF

0x00 17FFF

0x00 0FFFF

6 K

0x00 17FF

0x00 1400

7.2

Register map

In this section the memory and register map of the devices covered by this datasheet is

described. For a detailed description of the functionality of the registers, refer to STM8S

series and STM8AF series 8-bit microcontrollers reference manual, RM0016.

Table 13. I/O port hardware register map

Reset

Address

Block

Register label

Register name

status

0x00 5000

0x00 5001

0x00 5002

0x00 5003

0x00 5004

0x00 5005

0x00 5006

0x00 5007

0x00 5008

0x00 5009

0x00 500A

0x00 500B

0x00 500C

0x00 500D

0x00 500E

0x00 500F

0x00 5010

0x00 5011

0x00 5012

0x00 5013

PA_ODR

PA_IDR

Port A data output latch register

Port A input pin value register

Port A data direction register

Port A control register 1

0x00

0xXX⁽¹⁾

0x00

Port A

PA_DDR

PA_CR1

PA_CR2

PB_ODR

PB_IDR

PB_DDR

PB_CR1

PB_CR2

PC_ODR

PB_IDR

PC_DDR

PC_CR1

PC_CR2

PD_ODR

PD_IDR

PD_DDR

PD_CR1

PD_CR2

0x00

Port A control register 2

0x00

Port B data output latch register

Port B input pin value register

Port B data direction register

Port B control register 1

0x00

0xXX⁽¹⁾

Port B

Port C

Port D

0x00

Port B control register 2

0x00

Port C data output latch register

Port C input pin value register

Port C data direction register

Port C control register 1

0x00

0xXX⁽¹⁾

0x00

Port C control register 2

0x00

Port D data output latch register

Port D input pin value register

Port D data direction register

Port D control register 1

0x00

0xXX⁽¹⁾

0x00

0x02

Port D control register 2

0x00

DocID14395 Rev 15

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114

Memory and register map

Address

STM8AF526x/8x/Ax STM8AF6269/8x/Ax

Table 13. I/O port hardware register map (continued)

Reset

status

Block

Register label

Register name

0x00 5014

0x00 5015

0x00 5016

0x00 5017

0x00 5018

0x00 5019

0x00 501A

0x00 501B

0x00 501C

0x00 501D

0x00 501E

0x00 501F

0x00 5020

0x00 5021

0x00 5022

0x00 5023

0x00 5024

0x00 5025

0x00 5026

0x00 5027

0x00 5028

0x00 5029

0x00 502A

0x00 502B

0x00 502C

PE_ODR

PE_IDR

PE_DDR

PE_CR1

PE_CR2

PF_ODR

PF_IDR

PF_DDR

PF_CR1

PF_CR2

PG_ODR

PG_IDR

PG_DDR

PG_CR1

PG_CR2

PH_ODR

PH_IDR

PH_DDR

PH_CR1

PH_CR2

PI_ODR

PI_IDR

Port E data output latch register

Port E input pin value register

Port E data direction register

Port E control register 1

0x00

0xXX⁽¹⁾

0x00

Port E

0x00

Port E control register 2

0x00

Port F data output latch register

Port F input pin value register

Port F data direction register

Port F control register 1

0x00

0xXX⁽¹⁾

Port F

Port G

Port H

Port I

0x00

Port F control register 2

0x00

Port G data output latch register

Port G input pin value register

Port G data direction register

Port G control register 1

0x00

0xXX⁽¹⁾

0x00

Port G control register 2

0x00

Port H data output latch register

Port H input pin value register

Port H data direction register

Port H control register 1

0x00

0xXX⁽¹⁾

0x00

Port H control register 2

0x00

Port I data output latch register

Port I input pin value register

Port I data direction register

Port I control register 1

0x00

0xXX⁽¹⁾

PI_DDR

PI_CR1

0x00

PI_CR2

Port I control register 2

0x00

1. Depends on the external circuitry.

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Memory and register map

Table 14. General hardware register map

Reset

status

Address

Block

Register label

Register name

0x00 505A

0x00 505B

0x00 505C

0x00 505D

0x00 505E

FLASH_CR1

FLASH_CR2

FLASH_NCR2

FLASH_FPR

FLASH_NFPR

Flash control register 1

Flash control register 2

0x00

0xFF

0x00

0xFF

Flash complementary control register 2

Flash protection register

Flash

Flash complementary protection register

Flash in-application programming status

register

0x00 505F

FLASH_IAPSR

0x40

0x00 5060 to

0x005061

Reserved area (2 bytes)

Flash Program memory unprotection

register

0x00 5062

Flash

FLASH_PUKR

FLASH_DUKR

0x00

0x00 5063

0x00 5064

Reserved area (1 byte)

Data EEPROM unprotection register

0x00 5065 to

0x00 509F

Reserved area (59 bytes)

0x00 50A0

0x00 50A1

EXTI_CR1

EXTI_CR2

External interrupt control register 1

External interrupt control register 2

0x00

ITC

RST

CLK

0x00 50A2 to

0x00 50B2

Reserved area (17 bytes)

Reset status register

0x00 50B3

RST_SR

0xXX⁽¹⁾

0x00 50B4 to

0x00 50BF

Reserved area (12 bytes)

0x00 50C0

0x00 50C1

0x00 50C2

CLK_ICKR

CLK_ECKR

Internal clock control register

External clock control register

Reserved area (1 byte)

0x01

0x00

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114

Memory and register map

Address

STM8AF526x/8x/Ax STM8AF6269/8x/Ax

Table 14. General hardware register map (continued)

Reset

status

Block

Register label

Register name

0x00 50C3

0x00 50C4

0x00 50C5

0x00 50C6

0x00 50C7

0x00 50C8

0x00 50C9

0x00 50CA

0x00 50CB

0x00 50CC

CLK_CMSR

CLK_SWR

Clock master status register

Clock master switch register

Clock switch control register

Clock divider register

0xE1

0xXX

0x18

0xFF

0x00

0xFF

CLK_SWCR

CLK_CKDIVR

CLK_PCKENR1

CLK_CSSR

Peripheral clock gating register 1

Clock security system register

Configurable clock control register

Peripheral clock gating register 2

Reserved area (1 byte)

CLK

CLK_CCOR

CLK_PCKENR2

CLK_HSITRIMR

CLK_SWIMCCR

HSI clock calibration trimming register

0x00

0bXXXX

XXX0

0x00 50CD

SWIM clock control register

Reserved area (3 bytes)

0x00 50CE

to 0x00 50D0

0x00 50D1

0x00 50D2

WWDG_CR

WWDG_WR

WWDG control register

WWDR window register

0x7F

WWDG

IWDG

0x00 50D3 to

0x00 50DF

Reserved area (13 bytes)

IWDG key register

0x00 50E0

0x00 50E1

0x00 50E2

IWDG_KR

IWDG_PR

IWDG_RLR

0xXX⁽²⁾

0x00

IWDG prescaler register

IWDG reload register

0xFF

0x00 50E3 to

0x00 50EF

Reserved area (13 bytes)

0x00 50F0

0x00 50F1

AWU_CSR1

AWU_APR

AWU control/status register 1

0x00

0x3F

AWU asynchronous prescaler buffer

register

AWU

0x00 50F2

0x00 50F3

AWU_TBR

BEEP_CSR

AWU timebase selection register

BEEP control/status register

0x00

0x1F

BEEP

0x00 50F4 to

0x00 50FF

Reserved area (12 bytes)

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Memory and register map

Table 14. General hardware register map (continued)

Reset

status

Address

Block

Register label

Register name

0x00 5200

0x00 5201

0x00 5202

0x00 5203

0x00 5204

0x00 5205

0x00 5206

0x00 5207

SPI_CR1

SPI_CR2

SPI control register 1

SPI control register 2

SPI interrupt control register

SPI status register

0x00

0x02

0x00

0x07

0xFF

SPI_ICR

SPI_SR

SPI

SPI_DR

SPI data register

SPI_CRCPR

SPI_RXCRCR

SPI_TXCRCR

SPI CRC polynomial register

SPI Rx CRC register

SPI Tx CRC register

0x00 5208 to

0x00 520F

Reserved area (8 bytes)

0x00 5210

0x00 5211

0x00 5212

0x00 5213

0x00 5214

0x00 5215

0x00 5216

0x00 5217

0x00 5218

0x00 5219

0x00 521A

0x00 521B

0x00 521C

0x00 521D

I2C_CR1

I2C_CR2

I2C control register 1

I2C control register 2

0x00

I2C_FREQR

I2C_OARL

I2C_OARH

I2C frequency register

I2C own address register low

I2C own address register high

I2C_DR

I2C_SR1

I2C data register

I2C status register 1

0x00

0x02

I2C

I2C_SR2

I2C status register 2

I2C_SR3

I2C status register 3

I2C_ITR

I2C interrupt control register

I2C clock control register low

I2C clock control register high

I2C TRISE register

I2C_CCRL

I2C_CCRH

I2C_TRISER

0x00 521E to

0x00 522F

Reserved area (18 bytes)

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114

Memory and register map

Address

STM8AF526x/8x/Ax STM8AF6269/8x/Ax

Table 14. General hardware register map (continued)

Reset

status

Block

Register label

Register name

0x00 5230

0x00 5231

0x00 5232

0x00 5233

0x00 5234

0x00 5235

0x00 5236

0x00 5237

0x00 5238

0x00 5239

0x00 523A

UART1_SR

UART1_DR

USART status register

USART data register

0xC0

0xXX

0x00

UART1_BRR1

UART1_BRR2

UART1_CR1

UART1_CR2

UART1_CR3

UART1_CR4

UART1_CR5

UART1_GTR

UART1_PSCR

USART baud rate register 1

USART baud rate register 2

USART control register 1

USART control register 2

USART control register 3

USART control register 4

USART control register 5

USART guard time register

USART prescaler register

USART

0x00 523B to

0x00 523F

Reserved area (5 bytes)

0x00 5240

0x00 5241

0x00 5242

0x00 5243

0x00 5244

0x00 5245

0x00 5246

0x00 5247

0x00 5248

0x00 5249

UART3_SR

UART3_DR

LINUART status register

LINUART data register

0xC0

0xXX

0x00

UART3_BRR1

UART3_BRR2

UART3_CR1

UART3_CR2

UART3_CR3

UART3_CR4

LINUART baud rate register 1

LINUART baud rate register 2

LINUART control register 1

LINUART control register 2

LINUART control register 3

LINUART control register 4

Reserved

LINUART

UART3_CR6

LINUART control register 6

0x00

0x00 524A to

0x00 524F

Reserved area (6 bytes)

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Memory and register map

Table 14. General hardware register map (continued)

Reset

status

Address

Block

Register label

Register name

0x00 5250

0x00 5251

0x00 5252

0x00 5253

0x00 5254

0x00 5255

0x00 5256

0x00 5257

0x00 5258

0x00 5259

0x00 525A

0x00 525B

0x00 525C

0x00 525D

0x00 525E

0x00 525F

0x00 5260

0x00 5261

0x00 5262

0x00 5263

0x00 5264

0x00 5265

0x00 5266

0x00 5267

0x00 5268

0x00 5269

0x00 526A

0x00 526B

0x00 526C

0x00 526D

0x00 526E

0x00 526F

TIM1_CR1

TIM1_CR2

TIM1 control register 1

TIM1 control register 2

0x00

0xFF

0x00

TIM1_SMCR

TIM1_ETR

TIM1 slave mode control register

TIM1 external trigger register

TIM1 Interrupt enable register

TIM1 status register 1

TIM1_IER

TIM1_SR1

TIM1_SR2

TIM1 status register 2

TIM1_EGR

TIM1 event generation register

TIM1 capture/compare mode register 1

TIM1 capture/compare mode register 2

TIM1 capture/compare mode register 3

TIM1 capture/compare mode register 4

TIM1 capture/compare enable register 1

TIM1 capture/compare enable register 2

TIM1 counter high

TIM1_CCMR1

TIM1_CCMR2

TIM1_CCMR3

TIM1_CCMR4

TIM1_CCER1

TIM1_CCER2

TIM1_CNTRH

TIM1_CNTRL

TIM1_PSCRH

TIM1_PSCRL

TIM1_ARRH

TIM1_ARRL

TIM1_RCR

TIM1 counter low

TIM1

TIM1 prescaler register high

TIM1 prescaler register low

TIM1 auto-reload register high

TIM1 auto-reload register low

TIM1 repetition counter register

TIM1 capture/compare register 1 high

TIM1 capture/compare register 1 low

TIM1 capture/compare register 2 high

TIM1 capture/compare register 2 low

TIM1 capture/compare register 3 high

TIM1 capture/compare register 3 low

TIM1 capture/compare register 4 high

TIM1 capture/compare register 4 low

TIM1 break register

TIM1_CCR1H

TIM1_CCR1L

TIM1_CCR2H

TIM1_CCR2L

TIM1_CCR3H

TIM1_CCR3L

TIM1_CCR4H

TIM1_CCR4L

TIM1_BKR

TIM1_DTR

TIM1 dead-time register

TIM1_OISR

TIM1 output idle state register

0x00 5270 to

0x00 52FF

Reserved area (147 bytes)

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Memory and register map

Address

STM8AF526x/8x/Ax STM8AF6269/8x/Ax

Table 14. General hardware register map (continued)

Reset

status

Block

Register label

Register name

0x00 5300

0x00 5301

0x00 5302

0x00 5303

0x00 5304

0x00 5305

0x00 5306

0x00 5307

0x00 5308

0x00 5309

0x00 530A

0x00 530B

00 530C0x

0x00 530D

0x00 530E

0x00 530F

0x00 5310

0x00 5311

0x00 5312

0x00 5313

0x00 5314

TIM2_CR1

TIM2_IER

TIM2 control register 1

TIM2 interrupt enable register

TIM2 status register 1

0x00

0xFF

0x00

TIM2_SR1

TIM2_SR2

TIM2 status register 2

TIM2_EGR

TIM2 event generation register

TIM2 capture/compare mode register 1

TIM2 capture/compare mode register 2

TIM2 capture/compare mode register 3

TIM2 capture/compare enable register 1

TIM2 capture/compare enable register 2

TIM2 counter high

TIM2_CCMR1

TIM2_CCMR2

TIM2_CCMR3

TIM2_CCER1

TIM2_CCER2

TIM2_CNTRH

TIM2_CNTRL

TIM2_PSCR

TIM2_ARRH

TIM2_ARRL

TIM2_CCR1H

TIM2_CCR1L

TIM2_CCR2H

TIM2_CCR2L

TIM2_CCR3H

TIM2_CCR3L

TIM2

TIM2 counter low

TIM2 prescaler register

TIM2 auto-reload register high

TIM2 auto-reload register low

TIM2 capture/compare register 1 high

TIM2 capture/compare register 1 low

TIM2 capture/compare reg. 2 high

TIM2 capture/compare register 2 low

TIM2 capture/compare register 3 high

TIM2 capture/compare register 3 low

0x00 5315 to

0x00 531F

Reserved area (11 bytes)

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Memory and register map

Table 14. General hardware register map (continued)

Reset

status

Address

Block

Register label

Register name

0x00 5320

0x00 5321

0x00 5322

0x00 5323

0x00 5324

0x00 5325

0x00 5326

0x00 5327

0x00 5328

0x00 5329

0x00 532A

0x00 532B

0x00 532C

0x00 532D

0x00 532E

0x00 532F

0x00 5330

TIM3_CR1

TIM3_IER

TIM3 control register 1

TIM3 interrupt enable register

TIM3 status register 1

0x00

0xFF

0x00

TIM3_SR1

TIM3_SR2

TIM3 status register 2

TIM3_EGR

TIM3 event generation register

TIM3 capture/compare mode register 1

TIM3 capture/compare mode register 2

TIM3 capture/compare enable register 1

TIM3 counter high

TIM3_CCMR1

TIM3_CCMR2

TIM3_CCER1

TIM3_CNTRH

TIM3_CNTRL

TIM3_PSCR

TIM3_ARRH

TIM3_ARRL

TIM3_CCR1H

TIM3_CCR1L

TIM3_CCR2H

TIM3_CCR2L

TIM3

TIM3 counter low

TIM3 prescaler register

TIM3 auto-reload register high

TIM3 auto-reload register low

TIM3 capture/compare register 1 high

TIM3 capture/compare register 1 low

TIM3 capture/compare register 2 high

TIM3 capture/compare register 2 low

0x00 5331 to

0x00 533F

Reserved area (15 bytes)

0x00 5340

0x00 5341

0x00 5342

0x00 5343

0x00 5344

0x00 5345

0x00 5346

TIM4_CR1

TIM4_IER

TIM4 control register 1

TIM4 interrupt enable register

TIM4 status register

0x00

0xFF

TIM4_SR

TIM4

TIM4_EGR

TIM4_CNTR

TIM4_PSCR

TIM4_ARR

TIM4 event generation register

TIM4 counter

TIM4 prescaler register

TIM4 auto-reload register

0x00 5347 to

0x00 53FF

Reserved area (185 bytes)

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Address

STM8AF526x/8x/Ax STM8AF6269/8x/Ax

Table 14. General hardware register map (continued)

Reset

status

Block

Register label

Register name

0x00 5400

0x00 5401

0x00 5402

0x00 5403

0x00 5404

0x00 5405

0x00 5406

0x00 5407

ADC _CSR

ADC_CR1

ADC_CR2

ADC_CR3

ADC_DRH

ADC_DRL

ADC_TDRH

ADC_TDRL

ADC control/status register

ADC configuration register 1

ADC configuration register 2

ADC configuration register 3

ADC data register high

0x00

0xXX

0x00

ADC

ADC data register low

ADC Schmitt trigger disable register high

ADC Schmitt trigger disable register low

0x00 5408 to

0x00 541F

Reserved area (24 bytes)

0x00 5420

0x00 5421

0x00 5422

0x00 5423

0x00 5424

0x00 5425

0x00 5426

0x00 5427

0x00 5428

0x00 5429

0x00 542A

0x00 542B

0x00 542C

0x00 542D

0x00 542E

0x00 542F

0x00 5430

0x00 5431

0x00 5432

0x00 5433

0x00 5434

0x00 5435

0x00 5436

CAN_MCR

CAN_MSR

CAN_TSR

CAN_TPR

CAN_RFR

CAN_IER

CAN_DGR

CAN_FPSR

CAN_P0

CAN_P1

CAN_P2

CAN_P3

CAN_P4

CAN_P5

CAN_P6

CAN_P7

CAN_P8

CAN_P9

CAN_PA

CAN_PB

CAN_PC

CAN_PD

CAN_PE

CAN master control register

CAN master status register

CAN transmit status register

CAN transmit priority register

CAN receive FIFO register

CAN interrupt enable register

CAN diagnosis register

CAN page selection register

CAN paged register 0

CAN paged register 1

CAN paged register 2

CAN paged register 3

CAN paged register 4

CAN paged register 5

CAN paged register 6

CAN paged register 7

CAN paged register 8

CAN paged register 9

CAN paged register A

CAN paged register B

CAN paged register C

CAN paged register D

CAN paged register E

0x02

0x00

0x0C

0x00

0x0C

0x00

0xXX⁽³⁾

beCAN

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Memory and register map

Table 14. General hardware register map (continued)

Reset

status

Address

Block

Register label

Register name

0x00 5437

beCAN

CAN_PF

CAN paged register F

0xXX⁽³⁾

0x00 5438 to

0x00 57FF

Reserved area (968 bytes)

1. Depends on the previous reset source.

2. Write only register.

3. If the bootloader is enabled, it is initialized to 0x00.

Table 15. CPU/SWIM/debug module/interrupt controller registers

Reset

status

Address

Block

Register label

Register name

0x00 7F00

0x00 7F01

0x00 7F02

0x00 7F03

0x00 7F04

0x00 7F05

0x00 7F06

0x00 7F07

0x00 7F08

0x00 7F09

0x00 7F0A

A

Accumulator

Program counter extended

Program counter high

Program counter low

X index register high

X index register low

Y index register high

Y index register low

Stack pointer high

0x00

0x80

0x00

0x17⁽²⁾

0xFF

0x28

PCE

PCH

PCL

XH

CPU⁽¹⁾

XL

YH

YL

SPH

SPL

CC

Stack pointer low

Condition code register

0x00 7F0B

to 0x00

7F5F

Reserved area (85 bytes)

0x00 7F60

0x00 7F70

0x00 7F71

0x00 7F72

0x00 7F73

0x00 7F74

0x00 7F75

0x00 7F76

0x00 7F77

CPU

ITC

CFG_GCR

ITC_SPR1

ITC_SPR2

ITC_SPR3

ITC_SPR4

ITC_SPR5

ITC_SPR6

ITC_SPR7

ITC_SPR8

Global configuration register

Interrupt software priority register 1

Interrupt software priority register 2

Interrupt software priority register 3

Interrupt software priority register 4

Interrupt software priority register 5

Interrupt software priority register 6

Interrupt software priority register 7

Interrupt software priority register 8

0x00

0xFF

0x00 7F78

to

Reserved area (2 bytes)

0x00 7F79

0x00 7F80

SWIM

SWIM_CSR

SWIM control status register

0x00

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Table 15. CPU/SWIM/debug module/interrupt controller registers (continued)

Reset

status

Address

Block

Register label

Register name

0x00 7F81

to

Reserved area (15 bytes)

0x00 7F8F

0x00 7F90

0x00 7F91

0x00 7F92

0x00 7F93

0x00 7F94

0x00 7F95

0x00 7F96

0x00 7F97

0x00 7F98

0x00 7F99

0x00 7F9A

DM_BK1RE

DM_BK1RH

DM_BK1RL

DM_BK2RE

DM_BK2RH

DM_BK2RL

DM_CR1

DM breakpoint 1 register extended byte

DM breakpoint 1 register high byte

DM breakpoint 1 register low byte

DM breakpoint 2 register extended byte

DM breakpoint 2 register high byte

DM breakpoint 2 register low byte

DM debug module control register 1

DM debug module control register 2

DM debug module control/status register 1

DM debug module control/status register 2

DM enable function register

0xFF

0x00

0x10

0x00

0xFF

DM

DM_CR2

DM_CSR1

DM_CSR2

DM_ENFCTR

0x00 7F9B

to 0x00

7F9F

Reserved area (5 bytes)

1. Accessible by debug module only

2. Product dependent value, see Figure 8: Register and memory map.

Table 16. Temporary memory unprotection registers

Reset

status

Address

Block

Register label

Register name

0x00 5800

0x00 5801

0x00 5802

0x00 5803

0x00 5804

0x00 5805

0x00 5806

0x00 5807

TMU_K1

TMU_K2

TMU_K3

TMU_K4

TMU_K5

TMU_K6

TMU_K7

TMU_K8

Temporary memory unprotection key register 1

Temporary memory unprotection key register 2

Temporary memory unprotection key register 3

Temporary memory unprotection key register 4

Temporary memory unprotection key register 5

Temporary memory unprotection key register 6

Temporary memory unprotection key register 7

Temporary memory unprotection key register 8

0x00

TMU

Temporary memory unprotection control and status

register

0x00 5808

TMU_CSR

0x00

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Interrupt table

8

Interrupt table

(1)

Table 17. STM8A interrupt table

Interrupt vector

address

Wakeup

from Halt

Priority Source block

Description

Comments

-

Reset

TRAP

TLI

Reset

0x00 8000

0x00 8004

0x00 8008

0x00 800C

Yes

-

SW interrupt

-

0

1

External top level interrupt

Auto-wakeup from Halt

AWU

Yes

Clock

controller

2

Main clock controller

0x00 8010

-

3

4

MISC

CAN

SPI

External interrupt E0

External interrupt E1

External interrupt E2

External interrupt E3

External interrupt E4

CAN interrupt Rx

0x00 8014

0x00 8018

0x00 801C

0x00 8020

0x00 8024

0x00 8028

0x00 802C

0x00 8030

Yes

-

Port A interrupts

Port B interrupts

5

Port C interrupts

6

Port D interrupts

7

Port E interrupts

8

-

9

CAN interrupt TX/ER/SC

End of transfer

10

Yes

Update/overflow/

trigger/break

11

Timer 1

0x00 8034

-

12

13

14

15

16

17

18

19

20

21

22

23

Timer 1

Timer 2

Timer 3

USART

I²C

Capture/compare

Update/overflow

Capture/compare

Update/overflow

Capture/compare

Tx complete

0x00 8038

0x00 803C

0x00 8040

0x00 8044

0x00 8048

0x00 804C

0x00 8050

0x00 8054

0x00 8058

0x00 805C

0x00 8060

0x00 8064

-

Receive data full reg.

I²C interrupts

-

Yes

LINUART

ADC

Tx complete/error

Receive data full reg.

End of conversion

Update/overflow

-

Timer 4

End of programming/

write in not allowed area

24

EEPROM

0x00 8068

-

1. All unused interrupts must be initialized with ‘IRET’ for robust programming.

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9

Option bytes

Option bytes contain configurations for device hardware features as well as the memory

protection of the device. They are stored in a dedicated block of the memory. Each option

byte has to be stored twice, for redundancy, in a regular form (OPTx) and a complemented

one (NOPTx), except for the ROP (read-out protection) option byte and option bytes 8 to 16.

Option bytes can be modified in ICP mode (via SWIM) by accessing the EEPROM address

shown in Table 18: Option bytes below.

Option bytes can also be modified ‘on the fly’ by the application in IAP mode, except the

ROP and UBC options that can only be changed in ICP mode (via SWIM).

Refer to the STM8 Flash programming manual (PM0047) and STM8 SWIM communication

protocol and debug module user manual (UM0470) for information on SWIM programming

procedures.

Table 18. Option bytes

Option

byte

no.

Option bits

Factory

default

setting

Option

name

Addr.

7

6

5

4

3

2

1

0

Read-out

protection

(ROP)

0x00

4800

OPT0

ROP[7:0]

0x00

4801

OPT1

NOPT1

OPT2

UBC[7:0]

0x00

0xFF

0x00

0xFF

0x00

0xFF

0x00

0xFF

0x00

0xFF

User boot

code

(UBC)

0x00

4802

NUBC[7:0]

0x00

4803

Alternate

function

remapping

(AFR)

AFR7 AFR6 AFR5 AFR4 AFR3

AFR2

AFR1

AFR0

0x00

4804

NOPT2 NAFR7 NAFR6 NAFR5 NAFR4 NAFR3 NAFR2 NAFR1 NAFR0

0x00

4805

LSI_

EN

IWDG

_HW

WWD

G _HW _HALT

WWDG

OPT3

NOPT3

OPT4

Reserved

Watchdog

option

0x00

4806

NLSI_ NIWD

EN

NWWD NWWG

G_HW

_HALT

0x00

4807

EXT

CLK

CKAW

USEL

PRSC1 PRSC0

Clock

option

0x00

4808

NEXT NCKAW

CLK

NPRSC

NOPT4

OPT5

NPRSC1

0

USEL

0x00

4809

HSECNT[7:0]

HSE clock

startup

0x00

480A

NOPT5

NHSECNT[7:0]

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Option bytes

Table 18. Option bytes (continued)

Option bits

Option

byte

no.

Factory

default

setting

Option

name

Addr.

7

6

5

4

3

2

1

0

0x00

480B

OPT6

NOPT6

OPT7

TMU[3:0]

0x00

TMU

0x00

480C

NTMU[3:0]

0xFF

0x00

0xFF

0x00

480D

WAIT

STATE

Reserved

Flash wait

states

0x00

480E

NWAIT

STATE

NOPT7

Reserved

0x00

480F

Reserved

0x00

4810

OPT8

OPT9

TMU_KEY 1 [7:0]

TMU_KEY 2 [7:0]

TMU_KEY 3 [7:0]

TMU_KEY 4 [7:0]

TMU_KEY 5 [7:0]

TMU_KEY 6 [7:0]

TMU_KEY 7 [7:0]

TMU_KEY 8 [7:0]

TMU_MAXATT [7:0]

0x00

0xC7

0x00

4811

0x00

4812

OPT10

OPT11

OPT12

OPT13

OPT14

OPT15

OPT16

0x00

4813

0x00

4814

TMU

0x00

4815

0x00

4816

0x00

4817

0x00

4818

0x00

4819

to

Reserved

487D

0x00

487E

OPT17

BL [7:0]

0x00

0xFF

Boot-

loader⁽¹⁾

0x00

487F

NOPT

17

NBL [7:0]

1. This option consists of two bytes that must have a complementary value in order to be valid. If the option is invalid, it has no

effect on EMC reset.

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Table 19. Option byte description

Option byte no.

Description

ROP[7:0]: Memory readout protection (ROP)

0xAA: Enable readout protection (write access via SWIM protocol)

Note: Refer to STM8S series and STM8AF series 8-bit microcontrollers

reference manual (RM0016) section on Flash/EEPROM memory

readout protection for details.

OPT0

UBC[7:0]: User boot code area

0x00: No UBC, no write-protection

0x01: Page 0 to 1 defined as UBC, memory write-protected

0x02: Page 0 to 3 defined as UBC, memory write-protected

0x03 to 0xFF: Pages 4 to 255 defined as UBC, memory write-protected

Note: Refer to STM8S series and STM8AF series 8-bit microcontrollers

reference manual (RM0016) section on Flash/EEPROM write protection

for more details.

OPT1

AFR7: Alternate function remapping option 7

0: Port D4 alternate function = TIM2_CH1

1: Port D4 alternate function = BEEP

AFR6: Alternate function remapping option 6

0: Port B5 alternate function = AIN5, port B4 alternate function = AIN4

1: Port B5 alternate function = I²C_SDA, port B4 alternate function =

I²C_SCL.

AFR5: Alternate function remapping option 5

0: Port B3 alternate function = AIN3, port B2 alternate function = AIN2,

port B1 alternate function = AIN1, port B0 alternate function = AIN0.

1: Port B3 alternate function = TIM1_ETR, port B2 alternate function =

TIM1_CH3N, port B1 alternate function = TIM1_CH2N, port B0 alternate

function = TIM1_CH1N.

AFR4: Alternate function remapping option 4

0: Port D7 alternate function = TLI

1: Reserved

OPT2

AFR3: Alternate function remapping option 3

0: Port D0 alternate function = TIM3_CH2

1: Port D0 alternate function = TIM1_BKIN

AFR2: Alternate function remapping option 2

0: Port D0 alternate function = TIM3_CH2

1: Port D0 alternate function = CLK_CCO

Note: AFR2 option has priority over AFR3 if both are activated

AFR1: Alternate function remapping option 1

0: Port A3 alternate function = TIM2_CH3, port D2 alternate function

TIM3_CH1.

1: Port A3 alternate function = TIM3_CH1, port D2 alternate function

TIM2_CH3.

AFR0: Alternate function remapping option 0

0: Port D3 alternate function = TIM2_CH2

1: Port D3 alternate function = ADC_ETR

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Option bytes

Table 19. Option byte description (continued)

Option byte no.

Description

LSI_EN: Low speed internal clock enable

0: LSI clock is not available as CPU clock source

1: LSI clock is available as CPU clock source

IWDG_HW: Independent watchdog

0: IWDG Independent watchdog activated by software

1: IWDG Independent watchdog activated by hardware

OPT3

WWDG_HW: Window watchdog activation

0: WWDG window watchdog activated by software

1: WWDG window watchdog activated by hardware

WWDG_HALT: Window watchdog reset on Halt

0: No reset generated on Halt if WWDG active

1: Reset generated on Halt if WWDG active

EXTCLK: External clock selection

0: External crystal connected to OSCIN/OSCOUT

1: External clock signal on OSCIN

CKAWUSEL: Auto-wakeup unit/clock

0: LSI clock source selected for AWU

1: HSE clock with prescaler selected as clock source for AWU

OPT4

PRSC[1:0]: AWU clock prescaler

00: 24 MHz to 128 kHz prescaler

01: 16 MHz to 128 kHz prescaler

10: 8 MHz to 128 kHz prescaler

11: 4 MHz to 128 kHz prescaler

HSECNT[7:0]: HSE crystal oscillator stabilization time

OPT5

OPT6

This configures the stabilization time to 0.5, 8, 128, and 2048 HSE cycles

with corresponding option byte values of 0xE1, 0xD2, 0xB4, and 0x00.

TMU[3:0]: Enable temporary memory unprotection

0101: TMU disabled (permanent ROP).

Any other value: TMU enabled.

WAIT STATE: Wait state configuration

This option configures the number of wait states inserted when reading

from the Flash/data EEPROM memory.

0: No wait state

OPT7

1: One wait state

TMU_KEY 1 [7:0]: Temporary unprotection key 0

OPT8

OPT9

Temporary unprotection key: Must be different from 0x00 or 0xFF

TMU_KEY 2 [7:0]: Temporary unprotection key 1

Temporary unprotection key: Must be different from 0x00 or 0xFF

TMU_KEY 3 [7:0]: Temporary unprotection key 2

OPT10

OPT11

Temporary unprotection key: Must be different from 0x00 or 0xFF

TMU_KEY 4 [7:0]: Temporary unprotection key 3

Temporary unprotection key: Must be different from 0x00 or 0xFF

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Option bytes

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Table 19. Option byte description (continued)

Option byte no.

Description

TMU_KEY 5 [7:0]: Temporary unprotection key 4

OPT12

Temporary unprotection key: Must be different from 0x00 or 0xFF

TMU_KEY 6 [7:0]: Temporary unprotection key 5

OPT13

OPT14

OPT15

Temporary unprotection key: Must be different from 0x00 or 0xFF

TMU_KEY 7 [7:0]: Temporary unprotection key 6

Temporary unprotection key: Must be different from 0x00 or 0xFF

TMU_KEY 8 [7:0]: Temporary unprotection key 7

Temporary unprotection key: Must be different from 0x00 or 0xFF

TMU_MAXATT [7:0]: TMU access failure counter

TMU_MAXATT can be initialized with the desired value only if TMU is

disabled (TMU[3:0]=0101 in OPT6 option byte).

OPT16

OPT17

When TMU is enabled, any attempt to temporary remove the readout

protection by using wrong key values increments the counter.

When the option byte value reaches 0x08, the Flash memory and data

EEPROM are erased.

BL[7:0]: Bootloader enable

If this option byte is set to 0x55 (complementary value 0xAA) the

bootloader program is activated also in case of a programmed code

memory (for more details, see the bootloader user manual, UM0560).

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Electrical characteristics

10

Electrical characteristics

10.1

Parameter conditions

Unless otherwise specified, all voltages are referred to V

.

SS

10.1.1

Minimum and maximum values

Unless otherwise specified the minimum and maximum values are guaranteed in the worst

conditions of ambient temperature, supply voltage and frequencies by tests in production on

100% of the devices with an ambient temperature at T = -40 °C, T = 25 °C, and

A

T = T

(given by the selected temperature range).

A

Amax

Data based on characterization results, design simulation and/or technology characteristics

are indicated in the table footnotes and are not tested in production.

10.1.2

Typical values

Unless otherwise specified, typical data are based on T = 25 °C, V = 5.0 V. They are

A

DD

given only as design guidelines and are not tested.

Typical ADC accuracy values are determined by characterization of a batch of samples from

a standard diffusion lot over the full temperature range^.

10.1.3

10.1.4

Typical curves

Unless otherwise specified, all typical curves are given only as design guidelines and are

not tested.

Loading capacitor

The loading conditions used for pin parameter measurement are shown in Figure 9.

Figure 9. Pin loading conditions

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Electrical characteristics

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10.1.5

Pin input voltage

The input voltage measurement on a pin of the device is described in Figure 10.

Figure 10. Pin input voltage

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10.2

Absolute maximum ratings

Stresses above the absolute maximum ratings listed in Table 20: Voltage characteristics,

Table 21: Current characteristics and Table 22: Thermal characteristics may cause

permanent damage to the device. These are stress ratings only, and functional operation of

the device at these conditions is not implied. Exposure to maximum rating conditions for

extended periods may affect the device’s reliability. The device’s mission profile (application

conditions) is compliant with the JEDEC JESD47 qualification standard, extended mission

profiles are available on demand.

Table 20. Voltage characteristics

Symbol

Ratings

Min

Max

Unit

(1)

V

_DDx- V_SSSupply voltage (including V_{DDA and}V_DDIO

)

-0.3

6.5

Input voltage on true open drain pins (PE1, PE2)⁽²⁾

Input voltage on any other pin⁽²⁾

V_SS- 0.3

V

V_IN

V_SS- 0.3 V_DD+ 0.3

|V_DDx- V_DD| Variations between different power pins

-

50

mV

|V_SSx- V_SS| Variations between all the different ground pins

see Absolute maximum ratings

(electrical sensitivity) on

page 88

V_ESD

Electrostatic discharge voltage

1. All power (V_DD, V_DDIO, V_DDA) and ground (V_SS, V_SSIO, V_SSA) pins must always be connected to the

external power supply

2. I_INJ(PIN)must never be exceeded. This is implicitly insured if V_INmaximum is respected. If V_INmaximum

cannot be respected, the injection current must be limited externally to the I_INJ(PIN)value. A positive

injection is induced by V_IN> V_DDwhile a negative injection is induced by V_IN< V_SS. For true open-drain

pads, there is no positive injection current, and the corresponding V_INmaximum must always be respected

60/125

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Symbol

Electrical characteristics

Table 21. Current characteristics

Ratings

Max.

Unit

I_VDDIO

I_VSSIO

Total current into V_DDIOpower lines (source)^(1)(2)(3)

Total current out of V_{SS IO}ground lines (sink)^(1)(2)(3)

Output current sunk by any I/O and control pin

Output current source by any I/Os and control pin

Injected current on any pin

100

20

I_IO

mA

-20

±10

50

(4)

I_INJ(PIN)

I_INJ(TOT)

Sum of injected currents

1. All power (V_DD, V_DDIO, V_DDA) and ground (V_SS, V_SSIO, V_SSA) pins must always be connected to the

external supply.

2. The total limit applies to the sum of operation and injected currents.

3. V_DDIOincludes the sum of the positive injection currents. V_SSIOincludes the sum of the negative injection

currents.

4. This condition is implicitly insured if VIN maximum is respected. If VIN maximum cannot be respected, the

injection current must be limited externally to the IINJ(PIN) value. A positive injection is induced by VIN >

VDD while a negative injection is induced by VIN < VSS. For true open-drain pads, there is no positive

injection current allowed and the corresponding VIN maximum must always be respected.

Table 22. Thermal characteristics

Symbol

Ratings

Value

Unit

T_STG

T_J

Storage temperature range

-65 to 150

160

°C

Maximum junction temperature

(1)

Table 23. Operating lifetime

Symbol

Ratings

Value

Unit

−40 to 125 °C

−40 to 150 °C

Grade 1

Grade 0

OLF

Conforming to AEC-Q100 rev G

1. For detailed mission profile analysis, please contact the nearest ST Sales Office.

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10.3

Operating conditions

Table 24. General operating conditions

Parameter Conditions

Symbol

Min

Max

Unit

1 wait state

T_A= -40 °C to 150 °C

16

24

f_CPU

Internal CPU clock frequency

MHz

0 wait state

T_A= -40 °C to 150 °C

0

16

5.5

V_DD/V_DDIOStandard operating voltage

-

3.0

470

V

C_EXT: capacitance of external

capacitor

3300

nF

(1)

V_CAP

ESR of external capacitor

ESL of external capacitor

-

0.3

15

Ω

at 1 MHz⁽²⁾

nH

Suffix A

Suffix C

Suffix D

Suffix A

Suffix C

Suffix D

85

T_A

Ambient temperature

- 40

125

150

90

°C

T_J

Junction temperature range

130

155

1. Care should be taken when selecting the capacitor, due to its tolerance, as well as the parameter

dependency on temperature, DC bias and frequency in addition to other factors. The parameter maximum

value must be respected for the full application range.

2. This frequency of 1 MHz as a condition for V_CAPparameters is given by design of internal regulator.

Figure 11. f

versus V

DD

CPUmax

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Electrical characteristics

Table 25. Operating conditions at power-up/power-down

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

V_DDrise time rate

V_DDfall time rate

-

2⁽¹⁾

-

t_VDD

µs/V

-

Reset release delay

Reset generation delay

V_DDrising

1

3

1.7

-

ms

µs

t_TEMP

V

_DDfalling

-

Power-on reset

threshold^{(2) (3)}

V_IT+

V_IT-

2.65

2.58

-

2.8

2.95

2.88

-

V

Brown-out reset

threshold

-

2.73

70⁽¹⁾

Brown-out reset

hysteresis

V_HYS(BOR)

mV

1. Guaranteed by design, not tested in production.

2. If V_DDis below 3 V, the code execution is guaranteed above the V_IT-and V_IT+thresholds. RAM content is

kept. The EEPROM programming sequence must not be initiated.

3. There is inrush current into V_DDpresent after device power on to charge C_EXTcapacitor. This inrush

energy depends from C_EXTcapacitor value. For example, a C_EXTof 1 μF requires Q=1 μF x 1.8 V =

1.8 μC.

10.3.1

VCAP external capacitor

Stabilization for the main regulator is achieved connecting an external capacitor C

to the

EXT

V

pin. C

is specified in Table 24. Care should be taken to limit the series inductance

CAP

EXT

to less than 15 nH.

Figure 12. External capacitor C

EXT

(6/

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(65

5/HDN

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1. Legend: ESR is the equivalent series resistance and ESL is the equivalent inductance.

10.3.2

Supply current characteristics

The current consumption is measured as described in Figure 9 on page 59 and Figure 10

on page 60.

If not explicitly stated, general conditions of temperature and voltage apply.

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Table 26. Total current consumption in Run, Wait and Slow mode. General conditions

for V apply, T = −40 °C to 150 °C

DD

A

Symbol

Parameter

Conditions

Typ

Max

Unit

f_CPU= 24 MHz 1 ws

8.7

7.4

16.8⁽²⁾

All peripherals

clocked, code

Supply current in executed from Flash

f_CPU= 16 MHz

f_CPU= 8 MHz

f_CPU= 4 MHz

f_CPU= 2 MHz

f_CPU= 24 MHz

f_CPU= 16 MHz

14

(1)

I_DD(RUN)

4.0

7.4⁽²⁾

4.1⁽²⁾

2.5

Run mode

program memory,

HSE external clock

(without resonator)

2.4

1.5

4.4

6.0⁽²⁾

All peripherals

clocked, code

executed from RAM,

HSE external clock

(without resonator)

3.7

5.0

Supply current in

Run mode

(1)

I_DD(RUN)

f

_CPU= 8 MHz

2.2

3.0⁽²⁾

2.0⁽²⁾

1.5

f_CPU= 4 MHz

f_CPU= 2 MHz

f_CPU= 24 MHz

f_CPU= 16 MHz

1.4

mA

1.0

2.4

3.1⁽²⁾

1.65

1.15

0.90

0.80

2.5

CPU stopped, all

peripherals off, HSE

external clock

Supply current in

Wait mode

(1)

I_DD(WFI)

f_CPU= 8 MHz

1.9⁽²⁾

1.6⁽²⁾

1.5

f_CPU= 4 MHz

f_CPU= 2 MHz

External clock 16 MHz

f_CPU= 125 kHz

f_CPUscaled down,

Supply current in all peripherals off,

1.50

1.95

(1)

I_DD(SLOW)

Slow mode

code executed from

RAM

LSI internal RC

f_CPU= 128 kHz

1.80⁽²⁾

1. The current due to I/O utilization is not taken into account in these values.

2. Guaranteed by design, not tested in production.

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Electrical characteristics

Table 27. Total current consumption in Halt and Active-halt modes. General conditions for V

DD

applied. T = −40 °C to 55 °C unless otherwise stated

A

Conditions

Main

Symbol

Parameter

Typ

Max

Unit

voltage

regulator

(MVR)⁽¹⁾

Flash

Clock source and

temperature condition

mode⁽²⁾

Clocks stopped

5

35⁽³⁾

25

Supply current in

Halt mode

Power-

down

I_DD(H)

Off

On

Off

Clocks stopped,

T_A= 25 °C

External clock 16 MHz

f_MASTER= 125 kHz

900⁽³⁾

Supply current in

Active-halt mode

with regulator on

770

Power-

down

µA

LSI clock 128 kHz

150

25

230⁽³⁾

42⁽³⁾

I_DD(AH)

Supply current in

Active-halt mode

with regulator off

Power-

down

LSI clock 128 kHz,

T_A= 25 °C

25

10

30

Wakeup time from

Active-halt mode

with regulator on

On

Off

30⁽³⁾

Operating

mode

t_WU(AH)

T_A=−40 to 150 °C

µs

Wakeup time from

Active-halt mode

with regulator off

50

80⁽³⁾

1. Configured by the REGAH bit in the CLK_ICKR register.

2. Configured by the AHALT bit in the FLASH_CR1 register.

3. Guaranteed by characterization results, not tested in production.

Current consumption for on-chip peripherals

Table 28. Oscillator current consumption

Symbol

Parameter

Conditions

Typ

Max⁽¹⁾

Unit

Quartz or

ceramic

resonator,

CL = 33 pF

V_DD= 5 V

f

_OSC= 24 MHz

1

2.0⁽³⁾

-

HSE oscillator current

consumption⁽²⁾

_OSC= 16 MHz

f_OSC= 8 MHz

0.6

I_DD(OSC)

0.57

-

mA

Quartz or

ceramic

resonator,

CL = 33 pF

V_DD= 3.3 V

f_OSC= 24 MHz

f_OSC= 16 MHz

0.5

1.0⁽³⁾

-

HSE oscillator current

consumption⁽²⁾

0.25

I_DD(OSC)

f_OSC= 8 MHz

0.18

-

1. During startup, the oscillator current consumption may reach 6 mA.

2. The supply current of the oscillator can be further optimized by selecting a high quality resonator with small R_mvalue. Refer

to crystal manufacturer for more details

3. Informative data.

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Table 29. Programming current consumption

Symbol

Parameter

Conditions

Typ

Max

Unit

V_DD= 5 V, -40 °C to 150 °C, erasing

and programming data or Flash

program memory

I_DD(PROG)Programming current

1.0

1.7

mA

(1)

Table 30. Typical peripheral current consumption V = 5.0 V

DD

Typ.

= 2 MHz f

Typ.

= 16 MHz f

Typ.

Symbol

Parameter

Unit

f

=24 MHz

master

I_DD(TIM1)

I_DD(TIM2)

I_DD(TIM3)

I_DD(TIM4)

TIM1 supply current⁽²⁾

TIM2 supply current ⁽²⁾

TIM3 supply current⁽²⁾

TIM4 supply current⁽²⁾

0.03

0.02

0.01

0.004

0.03

0.01

0.02

0.06

0.003

0.22

0.23

0.12

0.1

0.34

0.19

0.16

0.05

0.15

0.18

0.07

0.91

0.40

0.05

2.4

0.03

0.09

0.11

0.04

0.06

0.30

0.02

1

I_DD(USART)USART supply current⁽²⁾

I_DD(LINUART)LINUART supply current⁽²⁾

mA

I_DD(SPI)

I_{DD(I C)}

I_DD(CAN)

I_DD(AWU)

SPI supply current⁽²⁾

I²C supply current⁽²⁾

CAN supply current⁽³⁾

AWU supply current⁽²⁾

2

I_{DD(TOT_DIG)}All digital peripherals on

ADC supply current when

I_DD(ADC)

0.93

0.95

0.96

converting⁽⁴⁾

1. Typical values not tested in production. Since the peripherals are powered by an internally regulated, constant digital

supply voltage, the values are similar in the full supply voltage range.

2. Data based on a differential I_DDmeasurement between no peripheral clocked and a single active peripheral. This

measurement does not include the pad toggling consumption.

3. Data based on a differential IDD measurement between reset configuration (CAN disabled) and a permanent CAN data

transmit sequence in loopback mode at 1 MHz. This measurement does not include the pad toggling consumption.

4. Data based on a differential I_DDmeasurement between reset configuration and continuous A/D conversions.

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Current consumption curves

Electrical characteristics

Figure 13 to Figure 18 show typical current consumption measured with code executing in

RAM.

Figure 13. Typ. I

vs. V

Figure 14. Typ. I

vs. f

DD(RUN)HSE CPU

DD(RUN)HSE

DD

@f

= 16 MHz, peripherals = on

@ V = 5.0 V, peripherals = on

CPU

DD

10

25°C

85°C

12 5°C

25°C

85°C

12 5°C

9

8

9

8

7

6

5

4

3

4

3

2

1

2

1

0

2.5

3

3.5

4

4.5

5

5.5

6

0

5

10

15

20

25

30

V_DD[V]

fcpu [MHz]

Figure 15. Typ. I

vs. V

Figure 16. Typ. I

vs. V

DD

DD(RUN)HSI

DD

DD(WFI)HSE

@ f

= 16 MHz, peripherals = off

@ f

= 16 MHz, peripherals = on

CPU

6

5

4

3

2

1

0

4

3

2

1

0

25°C

85°C

25°C

85°C

125°C

2.5

3.5

4.5

5.5

6.5

2.5

3.5

4.5

5.5

6.5

VDD [V]

Figure 17. Typ. I

vs. f

Figure 18. Typ. I

vs. V

DD(WFI)HSI DD

DD(WFI)HSE

CPU

@ V = 5.0 V, peripherals = on

@ f

= 16 MHz, peripherals = off

DD

CPU

6

2.5

2

5

4

1.5

3

2

1

0

1

25°C

85°C

25°C

85°C

12 5°C

0.5

12 5°C

0

5

10

15

20

25

30

2.5

3

3.5

4

4.5

5

5.5

6

fcpu [MHz]

V_DD[V]

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10.3.3

External clock sources and timing characteristics

HSE external clock

An HSE clock can be generated by feeding an external clock signal of up to 24 MHz to the

OSCIN pin.

Clock characteristics are subject to general operating conditions for V and T .

DD

A

Table 31. HSE external clock characteristics

Symbol

f_{HSE_ext}

Parameter

Conditions

Min

Typ

Max

Unit

User external clock source

frequency

T_A= -40 °C to 150 °C

0⁽¹⁾

-

24

-

MHz

V_HSEdHLComparator hysteresis

-

0.1 x V_DD

0.7 x V_DD

OSCIN high-level input pin

V_HSEH

V_DD

voltage

V

OSCIN low-level input pin

voltage

V_HSEL

-

V_SS

-1

-

0.3 x V_DD

+1

I_{LEAK_HSE}OSCIN input leakage current

V_SS< V_IN< V_DD

µA

1. If CSS is used, the external clock must have a frequency above 500 kHz.

Figure 19. HSE external clock source

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HSE crystal/ceramic resonator oscillator

The HSE clock can be supplied using a crystal/ceramic resonator oscillator of up to 24 MHz.

All the information given in this paragraph is based on characterization results with specified

typical external components. In the application, the resonator and the load capacitors have

to be placed as close as possible to the oscillator pins in order to minimize output distortion

and startup stabilization time. Refer to the crystal resonator manufacturer for more details

(frequency, package, accuracy...).

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Electrical characteristics

Table 32. HSE oscillator characteristics

Symbol

Parameter

Feedback resistor

Conditions

Min

Typ

Max

Unit

R_F

-

220

-

20

-

kΩ

pF

(1)

C_L1/C_L2

g_m

Recommended load capacitance

Oscillator trans conductance

-

5

mA/V

V

_DDis

(2)

t_SU(HSE)

Startup time

-

2.8

-

ms

stabilized

1. The oscillator needs two load capacitors, C_L1and C_L2, to act as load for the crystal. The total load capacitance (C_Load) is

(C_L1* C_L2)/(C_L1+ C_L2). If C_L1= C_L2, C_load= C_L1/2. Some oscillators have built-in load capacitors, C_L1and C_L2

.

2. This value is the startup time, measured from the moment it is enabled (by software) until a stabilized 24 MHz oscillation is

reached. It can vary with the crystal type that is used.

Figure 20. HSE oscillator circuit diagram

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HSE oscillator critical g_mformula

The crystal characteristics have to be checked with the following formula:

Equation 1

g

_m» g_mcrit

where g

can be calculated with the crystal parameters as follows:

mcrit

Equation 2

f

g_mcrit= (2 × Π × HSE)²× R_m(2Co + C)²

R : Notional resistance (see crystal specification)

m

L : Notional inductance (see crystal specification)

m

C : Notional capacitance (see crystal specification)

m

Co: Shunt capacitance (see crystal specification)

C

= C = C: Grounded external capacitance

L1

L2

DocID14395 Rev 15

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Electrical characteristics

STM8AF526x/8x/Ax STM8AF6269/8x/Ax

10.3.4

Internal clock sources and timing characteristics

Subject to general operating conditions for V and T .

DD

A

High-speed internal RC oscillator (HSI)

Table 33. HSI oscillator characteristics

Symbol

Parameter

Frequency

Conditions

Min

Typ

Max

Unit

f_HSI

-

16

-

MHz

Trimmed by the application

for any V_DDand T_A

conditions

HSI oscillator user

trimming accuracy

-1

-

1

ACC_HS

%

HSI oscillator accuracy

(factory calibrated)

V_DD= 3.0 V ≤ V_DD≤ 5.5 V,

-40 °C ≤ T_A≤ 150 °C

-5

-

5

t_su(HSI)HSI oscillator wakeup time

-

2⁽¹⁾

µs

1. Guaranteed by characterization results, not tested in production.

Figure 21. Typical HSI frequency vs V

DD

3%

2%

-40°C

25°C

85°C

125°C

1%

0%

-1%

-2%

-3%

2.5

3

3.5

4

4.5

5

5.5

6

V_DD[V]

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Electrical characteristics

Low-speed internal RC oscillator (LSI)

Subject to general operating conditions for V and T .

DD

A

Table 34. LSI oscillator characteristics

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

f_LSI

Frequency

-

112

-

128

-

144

7⁽¹⁾

kHz

µs

t_su(LSI)LSI oscillator wakeup time

1. Guaranteed by characterization results, not tested in production.

Figure 22. Typical LSI frequency vs V

DD

3%

2%

1%

25°C

0%

-1%

-2%

-3%

2.5

3

3.5

4

4.5

5

5.5

6

V_DD[V]

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10.3.5

Memory characteristics

Flash program memory/data EEPROM memory

General conditions: T = -40 °C to 150 °C.

A

Table 35. Flash program memory/data EEPROM memory

Symbol

Parameter

Conditions

Min⁽¹⁾Typ Max

Unit

f

_CPUis 16 to 24 MHz

with 1 ws

Operating voltage

(all modes, execution/write/erase)

V_DD

3.0

-

5.5

f_CPUis 0 to 16 MHz

with 0 ws

V

f_CPUis 16 to 24 MHz

with 1 ws

f_CPUis 0 to 16 MHz

with 0 ws

V_DD

Operating voltage (code execution)

2.6

-

5.5

6.6

Standard programming time (including

erase) for byte/word/block

-

6

(1 byte/4 bytes/128 bytes)

t_prog

ms

Fast programming time for 1 block

(128 bytes)

-

3

3.3

t_eraseErase time for 1 block (128 bytes)

1. Guaranteed by characterization results, not tested in production.

Table 36. Flash program memory

Symbol

Parameter

Condition

Min

Max

Unit

T_WE

Temperature for writing and erasing

-

-40

150

°C

Flash program memory endurance

(erase/write cycles)⁽¹⁾

N_WE

T_A= 25 °C

1000

-

cycles

T_A= 25 °C

T_A= 55 °C

40

20

-

t_RET

Data retention time

years

1. The physical granularity of the memory is four bytes, so cycling is performed on four bytes even when a

write/erase operation addresses a single byte.

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Electrical characteristics

Table 37. Data memory

Condition

Symbol

Parameter

Min

Max

Unit

T_WE

Temperature for writing and erasing

-

-40

150

°C

Data memory endurance⁽¹⁾

(erase/write cycles)

T_A= 25 °C

300 k

-

N_WE

cycles

years

T_A= -40°C to 125 °C 100 k⁽²⁾

T_A= 25 °C

T_A= 55 °C

40⁽²⁾⁽³⁾

20⁽²⁾⁽³⁾

t_RET

Data retention time

1. The physical granularity of the memory is four bytes, so cycling is performed on four bytes even when a

write/erase operation addresses a single byte.

2. More information on the relationship between data retention time and number of write/erase cycles is

available in a separate technical document.

3. Retention time for 256B of data memory after up to 1000 cycles at 125 °C.

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Electrical characteristics

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10.3.6

I/O port pin characteristics

General characteristics

Subject to general operating conditions for V and T unless otherwise specified. All

DD

A

unused pins must be kept at a fixed voltage, using the output mode of the I/O for example or

an external pull-up or pull-down resistor.

Table 38. I/O static characteristics

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

V_IL

V_IH

Low-level input voltage

High-level input voltage

-0.3 V

0.3 x V_DD

0.7 x V_DD

V_DD+ 0.3 V

-

0.1 x

V_DD

V_hys

Hysteresis⁽¹⁾

-

V

Standard I/0, V_DD= 5 V,

I = 3 mA

V

_DD- 0.5 V

-

V_OH

High-level output voltage

Standard I/0, V_DD= 3 V,

I = 1.5 mA

V

_DD- 0.4 V

High sink and true open

drain I/0, V_DD= 5 V

I = 8 mA

-

0.5

0.6

V_OL

Low-level output voltage

Pull-up resistor

Standard I/0, V_DD= 5 V

I = 3 mA

V

Standard I/0, V_DD= 3 V

I = 1.5 mA

-

35

-

50

-

0.4

65

R_pu

V_DD= 5 V, V_IN= V_SS

kΩ

Fast I/Os

Load = 50 pF

35⁽²⁾

Standard and high sink I/Os

Load = 50 pF

-

125⁽²⁾

20⁽²⁾

50⁽²⁾

±1

Rise and fall time

(10% - 90%)

t_R, t_F

ns

Fast I/Os

Load = 20 pF

Standard and high sink I/Os

Load = 20 pF

Digital input pad leakage

current

I_lkg

V_SS≤ V_IN≤ V_DD

µA

nA

V_SS≤ V_IN≤ V_DD

-40 °C < T_A< 125 °C

±250

±500

±1⁽³⁾

60

Analog input pad leakage

current

I_{lkg ana}

V_SS≤ V_IN≤ V_DD

-40 °C < T_A< 150 °C

Leakage current in

adjacent I/O⁽³⁾

I_lkg(inj)

I_DDIO

Injection current ±4 mA

µA

Total current on either

Including injection currents

mA

V_DDIOor V_SSIO

1. Hysteresis voltage between Schmitt trigger switching levels. Guaranteed by characterization results, not tested in

production.

74/125

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Electrical characteristics

2. Guaranteed by design.

3. Guaranteed by characterization results, not tested in production.

Figure 23. Typical V and V vs V @ four temperatures

IL

IH

DD

6

5

4

3

2

1

0

-40°C

25°C

85°C

125°C

2.5

3

3.5

4

4.5

5

5.5

6

V_DD[V]

Figure 24. Typical pull-up resistance R vs V @ four temperatures

PU

DD

60

55

50

45

40

35

30

-40°C

25°C

85°C

125°C

2.5

3

3.5

4

4.5

5

5.5

6

V_DD[V]

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(1)

Figure 25. Typical pull-up current I vs V @ four temperatures

pu

DD

140

120

100

80

-40°C

25°C

85°C

125°C

60

40

20

0

1

2

3

4

5

6

V_DD[V]

1. The pull-up is a pure resistor (slope goes through 0).

Typical output level curves

Figure 26 to Figure 35 show typical output level curves measured with output on a single

pin.

Figure 26. Typ. V @ V = 3.3 V (standard

Figure 27. Typ. V @ V = 5.0 V (standard

OL DD

OL

DD

ports)

-40°C

25°C

85°C

125°C

-40°C

25°C

85°C

125°C

1.5

1.25

1

1.5

1.25

1

0.75

0.5

0.25

0

0.75

0.5

0.25

0

1

2

3

4

5

6

7

0

2

4

6

8

10

12

I

_OL[mA]

I_OL[mA]

Figure 28. Typ. V @ V = 3.3 V (true open

Figure 29. Typ. V @ V = 5.0 V (true open

OL DD

OL

DD

drain ports)

-40°C

25°C

85°C

125°C

-40°C

25°C

85°C

125°C

2

1.75

1.5

1.25

1

2

1.75

1.5

1.25

1

0.75

0.5

0.25

0

0.75

0.5

0.25

0

2

4

6

8

10

12

14

0

5

10

15

20

25

I_OL[mA]

76/125

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Electrical characteristics

Figure 30. Typ. V @ V = 3.3 V (high sink

Figure 31. Typ. V @ V = 5.0 V (high sink

OL DD

OL

DD

ports)

-40°C

25°C

85°C

125°C

-40°C

25°C

85°C

125°C

1.5

1.25

1

1.5

1.25

1

0.75

0.5

0.25

0

0.75

0.5

0.25

0

2

4

6

8

10

12

14

0

5

10

15

20

25

I_OL[mA]

Figure 32. Typ. V

V

@ V = 3.3 V

Figure 33. Typ. V

V

@ V = 5.0 V

DD - OH

DD

DD - OH DD

(standard ports)

-40°C

2

1.75

1.5

1.25

1

2

1.75

1.5

1.25

1

25°C

85°C

125°C

25°C

85°C

125°C

0.75

0.5

0.25

0

0.75

0.5

0.25

0

1

2

3

4

5

6

7

0

2

4

6

8

10

12

I_OH[mA]

Figure 34. Typ. V

V

@ V = 3.3 V (high

Figure 35. Typ. V

V

@ V = 5.0 V (high

DD - OH

DD

DD - OH DD

sink ports)

-40°C

2

-40°C

2

25°C

1.75

85°C

1.5

1.25

1

125°C

1.5

1.25

1

125°C

0.75

0.5

0.25

0

0.75

0.5

0.25

0

2

4

6

8

10

12

14

0

5

10

15

20

25

I_OH[mA]

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114

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STM8AF526x/8x/Ax STM8AF6269/8x/Ax

10.3.7

Reset pin characteristics

Subject to general operating conditions for V and T unless otherwise specified.

DD

A

Table 39. NRST pin characteristics

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

V_IL(NRST)NRST low-level input voltage⁽¹⁾

V_IH(NRST)NRST high-level input voltage⁽¹⁾

-

V_SS

-

0.3 x V_DD

V_DD

0.7 x V_DD

V

V_OL(NRST)NRST low-level output voltage⁽¹⁾I_OL= 3 mA

-

0.6

R_PU(NRST)NRST pull-up resistor

-

30

85

40

-

60

kΩ

t_IFP

NRST input filtered pulse⁽¹⁾

315

ns

NRST Input not filtered pulse

duration⁽²⁾

t_INFP(NRST)

-

500

-

1. Guaranteed by characterization results, not tested in production.

2. Guaranteed by design, not tested in production.

Figure 36. Typical NRST V and V vs V @ four temperatures

IL

IH

DD

-40°C

25°C

85°C

125°C

6

5

4

3

2

1

0

2.5

3

3.5

4

4.5

5

5.5

6

V_DD[V]

78/125

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Electrical characteristics

Figure 37. Typical NRST pull-up resistance R vs V

PU

DD

-40°C

60

55

50

45

40

35

30

25°C

85°C

125°C

2.5

3

3.5

4

4.5

5

5.5

6

V_DD[V]

Figure 38. Typical NRST pull-up current I vs V

pu

DD

140

120

100

80

60

-40°C

25°C

85°C

125°C

40

20

0

1

2

3

4

5

6

V_DD[V]

The reset network shown in Figure 39 protects the device against parasitic resets. The user

must ensure that the level on the NRST pin can go below V max (see Table 39:

IL(NRST)

NRST pin characteristics), otherwise the reset is not taken into account internally.

For power consumption sensitive applications, the external reset capacitor value can be

reduced to limit the charge/discharge current. If NRST signal is used to reset external

circuitry, attention must be taken to the charge/discharge time of the external capacitor to

fulfill the external devices reset timing conditions. Minimum recommended capacity is 10 nF.

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114

Electrical characteristics

STM8AF526x/8x/Ax STM8AF6269/8x/Ax

Figure 39. Recommended reset pin protection

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TIM 1, 2, 3, and 4 electrical specifications

Subject to general operating conditions for V , f

and T .

A

DD MASTER

Table 40. TIM 1, 2, 3, and 4 electrical specifications

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

f_EXT

Timer external clock frequency⁽¹⁾

-

24

MHz

1. Not tested in production.

80/125

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Electrical characteristics

SPI interface

10.3.9

Unless otherwise specified, the parameters given in Table 41 are derived from tests

performed under ambient temperature, f frequency, and V supply voltage

MASTER

DD

conditions. t

= 1/f

.

MASTER

Refer to I/O port characteristics for more details on the input/output alternate function

characteristics (NSS, SCK, MOSI, MISO).

Table 41. SPI characteristics

Symbol

Parameter

Conditions

Min

Max

Unit

Master mode

Slave mode

0

10

f_SCK

1/t_c(SCK)

SPI clock frequency

V_DD< 4.5 V

V_DD= 4.5 V to 5.5 V

6⁽¹⁾

8⁽¹⁾

MHz

t_r(SCK)

t_f(SCK)

SPI clock rise and fall time Capacitive load: C = 30 pF

-

25⁽²⁾

(3)

t_su(NSS)

NSS setup time

NSS hold time

Slave mode

4 * t_MASTER

70

-

(3)

t_h(NSS)

(3)

t_w(SCKH)

t_w(SCKL)

t_w(SCKH)

t_w(SCKL)

SCK high and low time

Data input setup time

Master mode

t_SCK/2 - 15

t_SCK/2 + 15

(3)

Master mode

Slave mode

Master mode

Slave mode

5

-

t_su(MI)

t_su(SI)

(3)

7

t_h(MI)

t_h(SI)

ns

Data input hold time

(3)

10

-

(3)(4)

t_a(SO)

Data output access time

Data output disable time

3* t_MASTER

(3)(5)

t_dis(SO)

25

-

V_DD< 4.5 V

75

53

30

-

Slave mode

(after enable edge)

(3)

t_v(SO)

Data output valid time

Data output hold time

V

_DD= 4.5 V to 5.5 V

-

t_v(MO)

Master mode (after enable edge)

Slave mode (after enable edge)

Master mode (after enable edge)

-

(3)

t_h(SO)

31

12

(3)

t_h(MO)

-

1. f_SCK< f_MASTER/2.

2. The pad has to be configured accordingly (fast mode).

3. Guaranteed by design or by characterization results, not tested in production.

4. Min time is for the minimum time to drive the output and the max time is for the maximum time to validate the data.

5. Min time is for the minimum time to invalidate the output and the max time is for the maximum time to put the data in Hi-Z.

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Figure 40. SPI timing diagram in slave mode and with CPHA = 0

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Figure 41. SPI timing diagram in slave mode and with CPHA = 1

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.

82/125

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Electrical characteristics

Figure 42. SPI timing diagram - master mode

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DocID14395 Rev 15

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Electrical characteristics

STM8AF526x/8x/Ax STM8AF6269/8x/Ax

2

10.3.10 I C interface characteristics

2

Table 42. I C characteristics

Standard mode I²C

Fast mode I²C⁽¹⁾

Symbol

Parameter

Unit

Min⁽²⁾

Max⁽²⁾

Min⁽²⁾

Max⁽²⁾

t_w(SCLL)

t_w(SCLH)

t_su(SDA)

t_h(SDA)

SCL clock low time

4.7

4.0

-

1.3

0.6

100

0⁽⁴⁾

-

µs

SCL clock high time

SDA setup time

-

250

0⁽³⁾

-

SDA data hold time

900⁽³⁾

t_r(SDA)

t_r(SCL)

SDA and SCL rise time

(V_DD3 V to 5.5 V)

ns

-

1000

300

-

300

t_f(SDA)

t_f(SCL)

SDA and SCL fall time

(V_DD3 V to 5.5 V)

t_h(STA)

t_su(STA)

t_su(STO)

START condition hold time

4.0

4.7

4.0

-

0.6

-

µs

Repeated START condition setup time

STOP condition setup time

µs

pF

STOP to START condition time

(bus free)

t_w(STO:STA)

C_b

4.7

-

1.3

-

Capacitive load for each bus line

-

400

1. f_MASTER, must be at least 8 MHz to achieve max fast I²C speed (400 kHz)

Data based on standard I²C protocol requirement, not tested in production

2.

The maximum hold time of the start condition has only to be met if the interface does not stretch the low time

3.

4.

The device must internally provide a hold time of at least 300 ns for the SDA signal in order to bridge the undefined region

of the falling edge of SCL

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Electrical characteristics

10.3.11 10-bit ADC characteristics

Subject to general operating conditions for V

specified.

, f

and T unless otherwise

DDA MASTER

A

Table 43. ADC characteristics

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

f_ADC

ADC clock frequency

-

111 kHz

3

-

4 MHz kHz/MHz

V_DDAAnalog supply

5.5

V_REF+Positive reference voltage

V_REF-Negative reference voltage

2.75

V_DDA

-

V_SSA

-

0.5

V

V_DDA

Conversion voltage range⁽¹⁾

Devices with

external V_REF+

V_REF-pins

V_AIN

/

V_REF-

-

V_REF+

C_sampInternal sample and hold capacitor

-

1.5

0.75

7

3

-

pF

µs

kΩ

f_ADC= 2 MHz

Sampling time

(3 x 1/f_ADC

(1)

t_S

)

f

_ADC= 4 MHz

_ADC= 2 MHz

-

t_STABWakeup time from standby

f_ADC= 4 MHz

f_ADC= 2 MHz

3.5

7

-

Total conversion time including

t_CONVsampling time

-

f_ADC= 4 MHz

-

3.5

-

(14 x 1/f_ADC

)

R_switchEquivalent switch resistance

30

1. During the sample time, the sampling capacitance, C_samp(3 pF typ), can be charged/discharged by the

external source. The internal resistance of the analog source must allow the capacitance to reach its final

voltage level within t_S.After the end of the sample time t_S, changes of the analog input voltage have no

effect on the conversion result.

Figure 43. Typical application with ADC

s_ꢁꢁ

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9_$,1

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9₇

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VDPS

$,1

06Yꢍꢇꢍꢄꢃ9ꢁ

1. Legend: R_AIN= external resistance, C_AIN= capacitors, C_samp= internal sample and hold capacitor.

DocID14395 Rev 15

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114

Electrical characteristics

Symbol

STM8AF526x/8x/Ax STM8AF6269/8x/Ax

Table 44. ADC accuracy for V

= 5 V

DDA

Parameter

Total unadjusted error⁽²⁾

Conditions

Typ

Max⁽¹⁾

Unit

|E_T|

|E_O|

|E_G|

|E_D|

|E_L|

|E_T|

|E_O|

|E_G|

|E_D|

|E_L|

1.4

0.8

3⁽³⁾

3

Offset error⁽²⁾

Gain error⁽²⁾

f_ADC= 2 MHz

0.1

2

Differential linearity error⁽²⁾

Integral linearity error⁽²⁾

Total unadjusted error⁽²⁾

Offset error⁽²⁾

0.9

1

0.7

1.5

4⁽⁴⁾

3⁽⁴⁾

2⁽⁴⁾

1.5⁽⁴⁾

LSB

1.9⁽⁴⁾

1.3⁽⁴⁾

0.6⁽⁴⁾

1.5⁽⁴⁾

1.2⁽⁴⁾

Gain error⁽²⁾

f_ADC= 4 MHz

Differential linearity error⁽²⁾

Integral linearity error⁽²⁾

1. Guaranteed by characterization results, not tested in production.

2. ADC accuracy vs. injection current: Any positive or negative injection current within the limits specified for

I_INJ(PIN)and ΣI_INJ(PIN)in Section 10.3.6 does not affect the ADC accuracy.

3. TUE 2LSB can be reached on specific sales types on the whole temperature range.

4. Target values.

Figure 44. ADC accuracy characteristics

E_G

1023

V

– V

1022

1021

DDA

SSA

1LSB

= ----------------------------------------

IDEAL

1024

(2)

E_T

(3)

7

6

5

4

3

2

1

(1)

E_O

E_L

E_D

1 LSB_IDEAL

0

1

2

3

4

5

6

7

1021102210231024

V_SSA

V

DDA

1. Example of an actual transfer curve

2. The ideal transfer curve

3. End point correlation line

E_T= Total unadjusted error: Maximum deviation between the actual and the ideal transfer curves.

E

_O= Offset error: Deviation between the first actual transition and the first ideal one.

E_G= Gain error: Deviation between the last ideal transition and the last actual one.

E

_D= Differential linearity error: Maximum deviation between actual steps and the ideal one.

E_L= Integral linearity error: Maximum deviation between any actual transition and the end point correlation

line.

86/125

DocID14395 Rev 15

STM8AF526x/8x/Ax STM8AF6269/8x/Ax

Electrical characteristics

10.3.12 EMC characteristics

Susceptibility tests are performed on a sample basis during product characterization.

Functional EMS (electromagnetic susceptibility)

While executing a simple application (toggling 2 LEDs through I/O ports), the product is

stressed by two electromagnetic events until a failure occurs (indicated by the LEDs).

•

ESD: Electrostatic discharge (positive and negative) is applied on all pins of the device

until a functional disturbance occurs. This test conforms with the IEC 1000-4-2

standard.

•

FTB: A burst of fast transient voltage (positive and negative) is applied to V and V

through a 100 pF capacitor, until a functional disturbance occurs. This test conforms

with the IEC 1000-4-4 standard.

DD

SS

A device reset allows normal operations to be resumed. The test results are given in the

table below based on the EMS levels and classes defined in application note AN1709.

Designing hardened software to avoid noise problems

EMC characterization and optimization are performed at component level with a typical

application environment and simplified MCU software. It should be noted that good EMC

performance is highly dependent on the user application and the software in particular.

Therefore it is recommended that the user applies EMC software optimization and

prequalification tests in relation with the EMC level requested for his application.

Software recommendations

The software flowchart must include the management of runaway conditions such as:

•

Corrupted program counter

Unexpected reset

Critical data corruption (control registers...)

Prequalification trials

Most of the common failures (unexpected reset and program counter corruption) can be

recovered by applying a low state on the NRST pin or the oscillator pins for 1 second.

To complete these trials, ESD stress can be applied directly on the device, over the range of

specification values. When unexpected behavior is detected, the software can be hardened

to prevent unrecoverable errors occurring (see application note AN1015).

Table 45. EMS data

Symbol

Parameter

Conditions

Level/class

V_DD= 3.3 V, T_A= 25 °C,

f_MASTER= 16 MHz (HSI clock),

Conforms to IEC 1000-4-2

Voltage limits to be applied on any I/O pin

to induce a functional disturbance

V_FESD

3/B

Fast transient voltage burst limits to be

V_EFTBapplied through 100 pF on V_DDand V_SS

pins to induce a functional disturbance

V_DD= 3.3 V, T_A= 25 °C,

f_MASTER= 16 MHz (HSI clock),

Conforms to IEC 1000-4-4

4/A

DocID14395 Rev 15

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114

Electrical characteristics

STM8AF526x/8x/Ax STM8AF6269/8x/Ax

Electromagnetic interference (EMI)

Emission tests conform to the IEC 61967-2 standard for test software, board layout and pin

loading.

Table 46. EMI data

Conditions

(1)

Max f_CPU

Symbol

Parameter

Unit

General

Monitored

8

16

24

conditions

frequency band

MHz MHz MHz

0.1 MHz to 30 MHz

30 MHz to 130 MHz

130 MHz to 1 GHz

-

15

18

-1

2

17

22

3

22

16

5

V_DD= 5 V,

T_A= 25 °C,

Peak level

EMI level

S_EMI

LQFP80 package

conforming to IEC

61967-2

dBµV

2.5

1. Guaranteed by characterization results, not tested in production.

Absolute maximum ratings (electrical sensitivity)

Based on two different tests (ESD and LU) using specific measurement methods, the

product is stressed to determine its performance in terms of electrical sensitivity. For more

details, refer to the application note AN1181.

Electrostatic discharge (ESD)

Electrostatic discharges (3 positive then 3 negative pulses separated by 1 second) are

applied to the pins of each sample according to each pin combination. The sample size

depends on the number of supply pins in the device (3 parts*(n+1) supply pin). This test

conforms to the JESD22-A114A/A115A standard. For more details, refer to the application

note AN1181.

Table 47. ESD absolute maximum ratings

Maximum

Symbol

Ratings

Conditions

Class

Unit

value⁽¹⁾

Electrostatic discharge voltage T_A= 25 °C, conforming

V_ESD(HBM)

V_ESD(CDM)

V_ESD(MM)

3A

3

4000

(human body model)

to JESD22-A114

Electrostatic discharge voltage T_A= 25 °C, conforming

(charge device model) to JESD22-C101

500

200

V

Electrostatic discharge voltage T_A= 25 °C, conforming

(charge device model) to JESD22-A115

B

1. Guaranteed by characterization results, not tested in production

88/125

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STM8AF526x/8x/Ax STM8AF6269/8x/Ax

Static latch-up

Electrical characteristics

Two complementary static tests are required on 10 parts to assess the latch-up

performance.

•

A supply overvoltage (applied to each power supply pin) and

A current injection (applied to each input, output and configurable I/O pin) are

performed on each sample.

This test conforms to the EIA/JESD 78 IC latch-up standard. For more details, refer to the

application note AN1181.

Table 48. Electrical sensitivities

Symbol

Parameter

Conditions

Class⁽¹⁾

T_A= 25 °C

T_A= 85 °C

T_A= 125 °C

T_A= 150 °C

LU

Static latch-up class

A

1. Class description: A Class is an STMicroelectronics internal specification. All its limits are higher than the

JEDEC specifications, that means when a device belongs to class A it exceeds the JEDEC standard. B

class strictly covers all the JEDEC criteria (international standard).

DocID14395 Rev 15

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114

Package information

STM8AF526x/8x/Ax STM8AF6269/8x/Ax

11

Package information

In order to meet environmental requirements, ST offers these devices in different grades of

®

ECOPACK packages, depending on their level of environmental compliance. ECOPACK

specifications, grade definitions and product status are available at: www.st.com.

®

ECOPACK is an ST trademark.

11.1

LQFP80 package information

Figure 45. LQFP80 - 80-pin, 14 x 14 mm low-profile quad flat package outline

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#

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1. Drawing is not to scale.

90/125

DocID14395 Rev 15

STM8AF526x/8x/Ax STM8AF6269/8x/Ax

Package information

Table 49. LQFP80 - 80-pin, 14 x 14 mm low-profile quad flat package

(1)

mechanical data

millimeters

inches

Typ

Symbol

Min

Typ

Max

Min

Max

A

A1

A2

b

-

0.050

1.350

0.220

0.090

15.800

13.800

-

1.600

0.150

1.450

0.380

0.200

16.200

14.200

-

0.0630

0.0059

0.0571

0.0150

0.0079

0.6378

0.5591

-

0.0020

0.0531

0.0087

0.0035

0.6220

0.5433

-

1.400

0.320

-

0.0551

0.0126

-

c

D

16.000

14.000

12.350

16.000

14.000

12.350

0.650

0.600

1.000

3.5°

0.6299

0.5512

0.4862

0.6299

0.5512

0.4862

0.0256

0.0236

0.0394

3.5°

D1

D3

E

15.800

13.800

-

16.200

14.200

-

0.6220

0.5433

-

0.6378

0.5591

-

E1

E3

e

-

L

0.450

-

0.750

-

0.0177

-

0.0295

-

L1

k

0°

7°

0°

7°

ccc

-

0.100

-

0.0039

1. Values in inches are converted from mm and rounded to 4 decimal digits.

DocID14395 Rev 15

91/125

114

Package information

STM8AF526x/8x/Ax STM8AF6269/8x/Ax

Figure 46. LQFP80 - 80-pin, 14 x 14 mm low-profile quad flat package

recommended footprint

ꢀꢈ

ꢅꢂ

ꢀꢂ

ꢅꢈ

ꢈꢃꢀꢊ

ꢉꢂ

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ꢂꢃꢉ

ꢉꢈ

ꢂ

ꢂꢉꢃꢄꢊ

ꢂꢀꢃꢄ

ꢂ4@'1

1. Dimensions are expressed in millimeters.

92/125

DocID14395 Rev 15

STM8AF526x/8x/Ax STM8AF6269/8x/Ax

Device marking

Package information

The following figure gives an example of topside marking orientation versus pin 1 identifier

location.

Other optional marking or inset/upset marks, which identify the parts throughout supply

chain operations, are not indicated below.

Figure 47. LQFP80 marking example (package top view)

3URGXFWꢀ

LGHQWLILFDWLRQ^ꢉꢁꢊ

999999

9999

'DWHꢀFRGH

6WDQGDUGꢀ67ꢀORJR

:

88

5HYLVLRQꢀFRGH

3LQꢀꢁꢀLGHQWLILHU

06ꢍꢇꢍꢍꢍ9ꢁ

1. Parts marked as "ES","E” or accompanied by an Engineering Sample notification letter are not yet qualified

and therefore not approved for use in production. ST is not responsible for any consequences resulting

from such use. In no event will ST be liable for the customer using any of these engineering samples in

production. ST's quality department must be contacted to run a qualification activity prior to any decision to

use these engineering samples.

DocID14395 Rev 15

93/125

114

Package information

STM8AF526x/8x/Ax STM8AF6269/8x/Ax

11.2

LQFP64 package information

Figure 48. LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat package outline

6($7,1*ꢀ3/$1(

&

ꢋꢅꢃꢏꢀPP

*$8*(ꢀ3/$1(

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&

'

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/ꢁ

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E

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ꢁꢆ

ꢁ

3,1ꢀꢁ

H

,'(17,),&$7,21

ꢏ:B0(B9ꢍ

1. Drawing is not to scale.

Table 50. LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat

package mechanical data

millimeters

Typ

inches⁽¹⁾

Symbol

Min

Max

Min

Typ

Max

A

A1

A2

b

-

1.600

-

0.0630

0.050

-

0.150

0.0020

-

0.0059

1.350

1.400

0.220

-

1.450

0.0531

0.0551

0.0087

-

0.0571

0.170

0.270

0.0067

0.0106

c

0.090

0.200

0.0035

0.0079

D

-

12.000

10.000

7.500

12.000

10.000

-

0.4724

0.3937

0.2953

0.4724

0.3937

-

D1

D3

E

E1

94/125

DocID14395 Rev 15

STM8AF526x/8x/Ax STM8AF6269/8x/Ax

Package information

Table 50. LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat

package mechanical data (continued)

millimeters

inches⁽¹⁾

Typ

Symbol

Min

Typ

Max

Min

Max

E3

e

-

7.500

0.500

3.5°

-

0.2953

0.0197

3.5°

-

7°

-

7°

K

0°

L

0.450

0.600

1.000

-

0.750

-

0.0177

0.0236

0.0394

-

0.0295

-

L1

ccc

-

0.080

0.0031

1. Values in inches are converted from mm and rounded to 4 decimal digits.

Figure 49. LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat package

recommended footprint

ꢃꢅ

ꢆꢆ

ꢂꢇꢆ

ꢂꢇꢈ

ꢃꢉ

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ꢀꢁꢇꢊ

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ꢀꢊ

ꢄꢃ

ꢀꢇꢁ

ꢀꢄ

ꢀ

ꢀꢁꢇꢊ

AIꢀꢃꢉꢂꢉC

1. Dimensions are expressed in millimeters.

DocID14395 Rev 15

95/125

114

Package information

STM8AF526x/8x/Ax STM8AF6269/8x/Ax

Device marking

The following figure gives an example of topside marking orientation versus pin 1 identifier

location.

Other optional marking or inset/upset marks, which identify the parts throughout supply

chain operations, are not indicated below.

Figure 50. LQFP64 marking example (package top view)

3URGXFWꢀ

999999

9999

LGHQWLILFDWLRQ^ꢉꢁꢊ

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06ꢍꢇꢍꢍꢄ9ꢁ

1. Parts marked as "ES","E” or accompanied by an Engineering Sample notification letter are not yet qualified

and therefore not approved for use in production. ST is not responsible for any consequences resulting

from such use. In no event will ST be liable for the customer using any of these engineering samples in

production. ST's quality department must be contacted to run a qualification activity prior to any decision to

use these engineering samples.

96/125

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Package information

11.3

LQFP48 package information

Figure 51. LQFP48 - 48-pin, 7 x 7 mm low-profile quad flat package outline

3%!4).'

0,!.%

#

ꢂꢇꢁꢈ MM

'!5'% 0,!.%

CCC

#

$

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ꢀ

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1. Drawing is not to scale.

DocID14395 Rev 15

97/125

114

Package information

STM8AF526x/8x/Ax STM8AF6269/8x/Ax

Table 51. LQFP48 - 48-pin, 7 x 7 mm low-profile quad flat package

mechanical data

millimeters

inches⁽¹⁾

Symbol

Min

Typ

Max

Min

Typ

Max

A

A1

A2

b

-

0.050

1.350

0.170

0.090

8.800

6.800

-

1.600

0.150

1.450

0.270

0.200

9.200

7.200

-

0.0020

0.0531

0.0067

0.0035

0.3465

0.2677

-

0.0630

0.0059

0.0571

0.0106

0.0079

0.3622

0.2835

-

1.400

0.220

-

0.0551

0.0087

-

c

D

9.000

7.000

5.500

9.000

7.000

5.500

0.500

0.600

1.000

3.5°

0.3543

0.2756

0.2165

0.3543

0.2756

0.2165

0.0197

0.0236

0.0394

3.5°

D1

D3

E

8.800

6.800

-

9.200

7.200

-

0.3465

0.2677

-

0.3622

0.2835

-

E1

E3

e

-

L

0.450

-

0.750

-

0.0177

-

0.0295

-

L1

k

0°

7°

0°

7°

ccc

-

0.080

-

0.0031

1. Values in inches are converted from mm and rounded to 4 decimal digits.

98/125

DocID14395 Rev 15

STM8AF526x/8x/Ax STM8AF6269/8x/Ax

Package information

Figure 52. LQFP48 - 48-pin, 7 x 7 mm low-profile quad flat package

recommended footprint

ꢂꢇꢈꢂ

ꢀꢇꢁꢂ

ꢂꢇꢆꢂ

ꢆꢄ

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ꢆꢊ

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ꢀꢇꢁꢂ

ꢈꢇꢅꢂ

ꢉꢇꢊꢂ

AIꢀꢃꢉꢀꢀD

1. Dimensions are expressed in millimeters.

Device marking

The following figure gives an example of topside marking orientation versus pin 1 identifier

location.

Other optional marking or inset/upset marks, which identify the parts throughout supply

chain operations, are not indicated below.

DocID14395 Rev 15

99/125

114

Package information

STM8AF526x/8x/Ax STM8AF6269/8x/Ax

Figure 53. LQFP48 marking example (package top view)

3URGXFWꢀ

999999

9999

LGHQWLILFDWLRQ^ꢉꢁꢊ

'DWHꢀFRGH

6WDQGDUGꢀ67ꢀORJR

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: 88

5HYLVLRQꢀFRGH

06ꢍꢇꢍꢍꢏ9ꢁ

1. Parts marked as "ES","E” or accompanied by an Engineering Sample notification letter are not yet qualified

and therefore not approved for use in production. ST is not responsible for any consequences resulting

from such use. In no event will ST be liable for the customer using any of these engineering samples in

production. ST's quality department must be contacted to run a qualification activity prior to any decision to

use these engineering samples.

100/125

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Package information

11.4

LQFP32 package information

Figure 54. LQFP32 - 32-pin, 7 x 7 mm low-profile quad flat package outline

3%!4).'

0,!.%

#

ꢂꢇꢁꢈ MM

'!5'% 0,!.%

CCC

#

+

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ꢀ

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E

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1. Drawing is not to scale.

DocID14395 Rev 15

101/125

114

Package information

STM8AF526x/8x/Ax STM8AF6269/8x/Ax

Table 52. LQFP32 - 32-pin, 7 x 7 mm low-profile quad flat package

mechanical data

millimeters

inches⁽¹⁾

Symbol

Min

Typ

Max

Min

Typ

Max

A

A1

A2

b

-

0.050

1.350

0.300

0.090

8.800

6.800

-

1.600

0.150

1.450

0.450

0.200

9.200

7.200

-

0.0020

0.0531

0.0118

0.0035

0.3465

0.2677

-

0.0630

0.0059

0.0571

0.0177

0.0079

0.3622

0.2835

-

1.400

0.370

-

0.0551

0.0146

-

c

D

9.000

7.000

5.600

9.000

7.000

5.600

0.800

0.600

1.000

3.5°

0.3543

0.2756

0.2205

0.3543

0.2756

0.2205

0.0315

0.0236

0.0394

3.5°

D1

D3

E

8.800

6.800

-

9.200

7.200

-

0.3465

0.2677

-

0.3622

0.2835

-

E1

E3

e

-

L

0.450

-

0.750

-

0.0177

-

0.0295

-

L1

k

0°

7°

0°

7°

ccc

-

0.100

-

0.0039

1. Values in inches are converted from mm and rounded to 4 decimal digits.

102/125

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Package information

Figure 55. LQFP32 - 32-pin, 7 x 7 mm low-profile quad flat package

recommended footprint

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DocID14395 Rev 15

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114

Package information

STM8AF526x/8x/Ax STM8AF6269/8x/Ax

Device marking

The following figure gives an example of topside marking orientation versus pin 1 identifier

location.

Other optional marking or inset/upset marks, which identify the parts throughout supply

chain operations, are not indicated below.

Figure 56. LQFP32 marking example (package top view)

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1. Parts marked as "ES","E” or accompanied by an Engineering Sample notification letter are not yet qualified

and therefore not approved for use in production. ST is not responsible for any consequences resulting

from such use. In no event will ST be liable for the customer using any of these engineering samples in

production. ST's quality department must be contacted to run a qualification activity prior to any decision to

use these engineering samples.

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Package information

11.5

VFQFPN32 package information

Figure 57. VFQFPN32 - 32-pin, 5x5 mm, 0.5 mm pitch very thin profile fine pitch quad

flat package outline

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DocID14395 Rev 15

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114

Package information

STM8AF526x/8x/Ax STM8AF6269/8x/Ax

Table 53. VFQFPN32 - 32-pin, 5 x 5 mm, 0.5 mm pitch very thin profile fine pitch quad

flat package mechanical data

millimeters

Typ

inches⁽¹⁾

Symbol

Min

Max

Min

Typ

Max

A

A1

A3

b

0.800

0.000

-

0.900

0.020

0.200

0.250

5.000

3.600

5.000

3.600

0.500

0.400

-

1.000

0.050

-

0.0315

0.0000

-

0.0354

0.0008

0.0079

0.0098

0.1969

0.1417

0.1969

0.1417

0.0197

0.0157

-

0.0394

0.0020

-

0.180

4.850

3.500

4.850

3.500

-

0.300

5.150

3.700

5.150

3.700

-

0.0071

0.1909

0.1378

0.1909

0.1378

-

0.0118

0.2028

0.1457

0.2028

0.1457

-

D

D2

E

E2

e

L

0.300

-

0.500

0.050

0.0118

-

0.0197

0.0020

ddd

1. Values in inches are converted from mm and rounded to 4 decimal digits.

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Package information

Figure 58. VFQFPN32 - 32-pin, 5 x 5 mm, 0.5 mm pitch very thin profile fine pitch quad

flat package recommended footprint

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1. Dimensions are expressed in millimeters.

DocID14395 Rev 15

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114

Package information

STM8AF526x/8x/Ax STM8AF6269/8x/Ax

Device marking

The following figure gives an example of topside marking orientation versus pin 1 identifier

location.

Other optional marking or inset/upset marks, which identify the parts throughout supply

chain operations, are not indicated below.

Figure 59. VFQFPN32 marking example (package top view)

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999999

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1. Parts marked as "ES","E” or accompanied by an Engineering Sample notification letter are not yet qualified

and therefore not approved for use in production. ST is not responsible for any consequences resulting

from such use. In no event will ST be liable for the customer using any of these engineering samples in

production. ST's quality department must be contacted to run a qualification activity prior to any decision to

use these engineering samples.

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Package information

11.6

Thermal characteristics

In case the maximum chip junction temperature (T

) specified in Table 24: General

Jmax

operating conditions is exceeded, the functionality of the device cannot be guaranteed.

T

, in degrees Celsius, may be calculated using the following equation:

Jmax

T

= T

+ (P

x Θ )

Jmax

Amax

Dmax JA

where:

T

is the maximum ambient temperature in ° C

Amax

Θ

is the package junction-to-ambient thermal resistance in ° C/W

JA

P

is the sum of P

and P

(P

= P

+ P

)

I/Omax

Dmax

INTmax

I/Omax

Dmax

INTmax

P

is the product of I and V , expressed in Watts. This is the maximum chip

INTmax

DD

internal power.

P

represents the maximum power dissipation on output pins

I/Omax

where:

P

= Σ (V * I ) + Σ((V - V ) * I

)

OH

I/Omax

OL

DD

OH

taking into account the actual V / I and V / I of the I/Os at low- and high-level in the

OL OL

OH OH

application.

(1)

Table 54. Thermal characteristics

Parameter

Symbol

Value

Unit

Thermal resistance junction-ambient

LQFP 80 - 14 x 14 mm

38

Thermal resistance junction-ambient

LQFP 64 - 10 x 10 mm

46

57

59

25

Thermal resistance junction-ambient

LQFP 48 - 7 x 7 mm

Θ

°C/W

JA

Thermal resistance junction-ambient

LQFP 32 - 7 x 7 mm

Thermal resistance junction-ambient

VFQFPN 32 - 5 x 5 mm

1. Thermal resistances are based on JEDEC JESD51-2 with 4-layer PCB in a natural convection

environment.

11.6.1

Reference document

JESD51-2 integrated circuits thermal test method environment conditions - natural

convection (still air). Available from www.jedec.org.

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11.6.2

Selecting the product temperature range

When ordering the microcontroller, the temperature range is specified in the order code (see

Figure 60: STM8AF526x/8x/Ax and STM8AF6269/8x/Ax ordering information scheme1 on

page 111).

The following example shows how to calculate the temperature range needed for a given

application.

Assuming the following application conditions:

–

P

Maximum ambient temperature T

= 82 °C (measured according to JESD51-2)

Amax

I

= 8 mA

DDmax

V

= 5 V

DD

maximum 20 I/Os used at the same time in output at low-level with I = 8 mA

OL

V

= 0.4 V

OL

= 8 mA x 5 V = 400 mW

INTmax

P

= 20 x 8 mA x 0.4 V = 64 mW

IOmax

This gives:

P

= 400 mW and P

64 mW

IOmax

INTmax

= 400 mW + 64 mW

Dmax

Thus:

P

= 464 mW.

Dmax

Using the values obtained in Table 54: Thermal characteristics T

is calculated as

Jmax

follows:

For LQFP64 46 °C/W

T

= 82 °C + (46 °C/W x 464 mW) = 82 °C + 21 °C = 103 ° C

jmax

This is within the range of the suffix C version parts (-40 °C < T < 125 ° C).

j

Parts must be ordered at least with the temperature range suffix C.

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Ordering information

12

Ordering information

1

Figure 60. STM8AF526x/8x/Ax and STM8AF6269/8x/Ax ordering information scheme

STM8A²

F

62

A

T

D

XXX³

Y

Example:

Product class

8-bit automotive microcontroller

Program memory type

F = Flash + EEPROM

P = FASTROM

Device family

52 = Silicon rev U and rev T, CAN/LIN

62 = Silicon rev U and rev T, LIN only

Program memory size

6 = 32 Kbyte

8 = 64 Kbyte

A= 128 Kbyte

Pin count

6 = 32 pins

8 = 48 pins

9 = 64 pins

A = 80 pins

Package type

T = LQFP

U = VFQFPN

Temperature range

A = -40 to 85 °C

C = -40 to 125 °C

D = -40 to 150 °C

Packing

Y = Tray

U = Tube

X = Tape and reel compliant with EIA 481-C

1. For a list of available options (e.g. memory size, package) and orderable part numbers or for further

information on any aspect of this device, please go to www.st.com or contact the nearest ST Sales Office.

2. Qualified and characterized according to AEC Q100 and Q003 or equivalent, advanced screening

according to AEC Q001 and Q002 or equivalent.

3. Customer specific FASTROM code or custom device configuration. This field shows ‘SSS’ if the device

contains a super set silicon, usually equipped with bigger memory and more I/Os. This silicon is supposed

to be replaced later by the target silicon.

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13

STM8 development tools

Development tools for the STM8A microcontrollers include the

•

STice emulation system offering tracing and code profiling

•

STVD high-level language debugger including assembler and visual development

environment - seamless integration of third party C compilers

•

STVP Flash programming software

In addition, the STM8A comes with starter kits, evaluation boards and low-cost in-circuit

debugging/programming tools.

13.1

Emulation and in-circuit debugging tools

The STM8 tool line includes the STice emulation system offering a complete range of

emulation and in-circuit debugging features on a platform that is designed for versatility and

cost-effectiveness. In addition, STM8A application development is supported by a low-cost

in-circuit debugger/programmer.

The STice is the fourth generation of full-featured emulators from STMicroelectronics. It

offers new advanced debugging capabilities including tracing, profiling and code coverage

analysis to help detect execution bottlenecks and dead code.

In addition, STice offers in-circuit debugging and programming of STM8A microcontrollers

via the STM8 single wire interface module (SWIM), which allows non-intrusive debugging of

an application while it runs on the target microcontroller.

For improved cost effectiveness, STice is based on a modular design that allows users to

order exactly what they need to meet their development requirements and to adapt their

emulation system to support existing and future ST microcontrollers.

13.1.1

STice key features

•

Program and data trace recording up to 128 K records

Advanced breakpoints with up to 4 levels of conditions

Data breakpoints

Real-time read/write of all device resources during emulation

Occurrence and time profiling and code coverage analysis (new features)

In-circuit debugging/programming via SWIM protocol

8-bit probe analyzer

1 input and 2 output triggers

USB 2.0 high-speed interface to host PC

Power supply follower managing application voltages between 1.62 to 5.5 V

Modularity that allows users to specify the components they need to meet their

development requirements and adapt to future requirements

•

Supported by free software tools that include integrated development environment

(IDE), programming software interface and assembler for STM8.

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STM8 development tools

13.2

Software tools

STM8 development tools are supported by a complete, free software package from STMi-

croelectronics that includes ST visual develop (STVD) IDE and the ST visual programmer

(STVP) software interface. STVD provides seamless integration of the Cosmic and Raiso-

nance C compilers for STM8.

13.2.1

STM8 toolset

The STM8 toolset with STVD integrated development environment and STVP programming

software is available for free download at www.st.com. This package includes:

ST visual develop

Full-featured integrated development environment from STMicroelectronics, featuring:

•

Seamless integration of C and ASM toolsets

Full-featured debugger

Project management

Syntax highlighting editor

Integrated programming interface

Support of advanced emulation features for STice such as code profiling and coverage

ST visual programmer (STVP)

Easy-to-use, unlimited graphical interface allowing read, write and verification of the STM8A

microcontroller’s Flash memory. STVP also offers project mode for saving programming

configurations and automating programming sequences.

13.2.2

C and assembly toolchains

Control of C and assembly toolchains is seamlessly integrated into the STVD integrated

development environment, making it possible to configure and control the building of the

application directly from an easy-to-use graphical interface. Available toolchains include:

C compiler for STM8

All compilers are available in free version with a limited code size depending on the

compiler. For more information, refer to www.cosmic-software.com, www.raisonance.com,

and www.iar.com.

STM8 assembler linker

Free assembly toolchain included in the STM8 toolset, which allows users to assemble and

link their application source code.

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13.3

Programming tools

During the development cycle, STice provides in-circuit programming of the STM8A Flash

microcontroller on the application board via the SWIM protocol. Additional tools are to

include a low-cost in-circuit programmer as well as ST socket boards, which provide

dedicated programming platforms with sockets for programming the STM8A.

For production environments, programmers will include a complete range of gang and

automated programming solutions from third-party tool developers already supplying

programmers for the STM8 family.

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Revision history

14

Revision history

Table 55. Document revision history

Changes

Date

Revision

31-Jan-2008

1

Initial release

Added ‘H’ products to the datasheet (Flash no EEPROM).

Section : Features on cover page: Updated Memories, Reset and

supply management, Communication interfaces and I/Os; reduced

wakeup pins by 1.

Table 1: Device summary: Removed STM8AF6168, STM8AF6148,

STM8AF6166, STM8AF6146, STM8AF5168, STM8AF5186,

STM8AF5176, and STM8AF5166.

Section 1: Introduction, Section 5: Product overview, Section 9:

Option bytes, Section 6.2: Alternate function remapping, Table 21:

Current characteristics: Updated reference documentation: RM0009,

PM0047, and UM0470.

Section 2: Description: added information about peak performance.

Section 3: Product line-up: Removed STM8A common features

table.

Table 4: Peripheral clock gating bits (CLK_PCKENR1): Removed

STM8AF5186T, STM8AF5176T, STM8AF5168T, and

STM8AF5166T.

Table 5: Peripheral clock gating bits (CLK_PCKENR2): Removed

STM8AF6168T, STM8AF6166T, STM8AF6148T, and

STM8AF6146T.

Section 5: Product overview: Made minor content changes and

improved readability and layout.

22-Aug-2008

2

Section 5.5.3: 128 kHz low-speed internal RC oscillator (LSI): Major

modification, TMU included.

Section 5.5.2: 16 MHz high-speed internal RC oscillator (HSI): User

trimming updated.

Section 5.5.3: 128 kHz low-speed internal RC oscillator (LSI): LSI as

CPU clock added.

Section 5.5.4: 24 MHz high-speed external crystal oscillator (HSE),

Section 5.5.5: External clock input: Maximum frequency conditional

32 Kbyte/128 Kbyte.

Section 5.8: Analog to digital converter (ADC): Scan for 128 Kbyte

removed.

Section 5.9: Communication interfaces, Section 5.9.3: Serial

peripheral interface (SPI): SPI 10 Mb/s.

Figure 3: LQFP 80-pin pinout, Figure 4: LQFP 64-pin pinout,

Figure 6: STM8AF62xx LQFP/VFQFPN 32-pin pinout: Amended

footnote 1.

Table 12: Memory model 128K: HS output changed from 20 mA to 8

mA.

Section 7: Memory and register map: Corrected Table 8: Register

and memory map; removed address list; added Table 14: General

hardware register map.

Section 10.3.2: Supply current characteristics Note on typical/WC

values added.

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Table 55. Document revision history (continued)

Date

Revision

Changes

Table 18: Typ. IDD(WFI)HSI vs. VDD @ fCPU = 16 MHz, peripherals

= off: Replaced the source blocks ‘simple USART’, ‘very low-end

timer (timer 4)’, and ‘EEPROM’ with ‘LINUART’, ‘timer4’ and

‘reserved’ respectively, added TMU registers.

Table 20: HSE oscillator circuit diagram: Updated OPT6 and NOPT6,

added OPT7 to 17 (TMU, BL)

Table 21: Typical HSI frequency vs VDD: Updated OPT1 UBC[7:0],

OPT4 CKAWUSEL, OPT4 PRSC [1:0], and OPT6, added OPT7 to

16 (TMU).

Table 23: Operating lifetime: Amended footnotes.

Table 26: Total current consumption in Run, Wait and Slow mode.

General conditions for VDD apply, TA = -40 °C to 150 °C: Added

parameter ‘voltage and current operating conditions’.

Table 27: Total current consumption in Halt and Active-halt modes.

General conditions for VDD applied. TA = -40 °C to 55 °C unless

otherwise stated: Amended footnotes.

Table 28: Oscillator current consumption: Replaced.

Table 29: Programming current consumption: Amended maximum

data and footnotes.

Table 21: Current characteristics: Replaced.

Table 22: Thermal characteristics: Added and amended I_DD(RUN)

data; amended I_DD(WFI)data; amended footnotes.

Table 32: HSE oscillator characteristics: Filled in, amended

maximum data and footnotes.

2

22-Aug-2008

Figure 13 to Figure 18: info on peripheral activity added.

(continued)

Table 33: HSI oscillator characteristics: Modified f_{HSE_ext}data and

added V_HSEdhldata.

Table 35: Flash program memory/data EEPROM memory: Removed

ACC_HSIparameters and replaced with ACC_HSparameters; amended

data and footnotes.

Amended data of ‘RAM and hardware registers’ table.

Table 37: Data memory: Updated names and data of N_RWand t_RET

parameters.

Table 40: TIM 1, 2, 3, and 4 electrical specifications: Added V_OHand

V_OLparameters; Updated I_{lkg ana}parameter.

Removed: Output driving current (standard ports), Output driving

current (true open drain ports), and Output driving current (high sink

ports).

Table 46: EMI data: Updated f_ADC, t_S, and t_CONVdata.

Table: ADC accuracy for VDDA = 3.3 V: removed the 4-MHz

condition from all parameters.

Table 47: ESD absolute maximum ratings: Removed the 4-MHz

condition from all parameters; updated footnote 1 and removed

footnote 2.

Table 51: LQFP48 - 48-pin, 7 x 7 mm low-profile quad flat package

mechanical data: Added data for T_A= 145 °C.

Figure 53: Updated memory size, pin count and package type

information.

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Revision history

Table 55. Document revision history (continued)

Date

Revision

Changes

Replaced the salestype ‘STM8H61xx’ with ‘STM8AH61xx on the first

page.

Added ‘part numbers’ to heading rows of Table 1: Device summary.

Updated the 80-pin package silhouette on cover page in line with

POA 0062342-revD.

Table 18: Renamed ‘TMU key registers 0-7 [7:0]’ as ‘TMU key

registers 1-8 [7:0]’

Section 9: Updated introductory text concerning option bytes which

do not need to be saved in a complementary form.

Table 18: Renamed the option bits ‘TMU[0:3]’, ‘NTMU[0:3]’, and

‘TMU_KEY 0-7 [7:0]’ as ‘TMU[3:0]’, ‘NTMU[3:0]’, and ‘TMU_KEY 1-8

[7:0]’ respectively.

16-Sep-2008

3

Table 21: Updated values of option byte 5 (HSECNT[7:0]); inverted

the description of option byte 6 (TMU[3:0]); renamed option bytes 8

to 15 ‘TMU_KEY 0-7 [7:0]’, as ‘TMU_KEY 1-8 [7:0]’.

Updated 80-pin package information in line with POA 0062342-revD

in Figure 45 and Table 53.

Added ‘STM8AH61xx’ and ‘STM8AH51xx to document header.

Updated : Features on page 1 (memories, timers, operating

temperature, ADC and I/Os).

Updated Table 1: Device summary

Updated Kbyte value of program memory in Section: Introduction

Changed the first two lines from the top in Section: Description.

Updated Figure 1: STM8AF526x/8x/Ax and STM8AF6269/8x/Ax

block diagram

Updated Section 5: Product overview

In Figure 5: LQFP 48-pin pinout, added USART function to pins 10,

11, and 12; added CAN Tx and CAN Rx functions to pins 35 and 36

respectively.

Section 6: Pinouts and pin description: deleted the text below the

Table 10: Legend/abbreviation for the pin description table

Table 11: STM8AF526x/8x/Ax and STM8AF6269/8x/Ax pin

description: 68th, 69th pin (LQFP80): replaced X with a dash for PP

output and Added a table footnote.

01-Jul-2009

4

Updated Figure 8: Register and memory map.

Table 12: Memory model 128K: updated footnote

Deleted the Table: Stack and RAM partitioning

Table 17: STM8A interrupt table: Updated priorities 13, 15, 17, 20

and 24 and changed table footnote

Updated Section 7: Memory and register map

Updated Table: Data memory, Table: I/O static characteristics, and

Table 39: NRST pin characteristics.

Section 10.1.1: Minimum and maximum values: added ambient

temperature T_A= -40 °C

Updated Table 20: Voltage characteristics.

Updated Table 21: Current characteristics.

Updated Table 22: Thermal characteristics.

Updated Table 24: General operating conditions.

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Table 55. Document revision history (continued)

Date

Revision

Changes

Removed table: Total current consumption and timing in halt, fast

active halt and slow active halt modes at V_DD= 3.3 V.

Added Table 28: Oscillator current consumption.

Added Table 29: Programming current consumption.

Updated Table 30: Typical peripheral current consumption VDD = 5.0

V

Updated Table 31: HSE external clock characteristics.

Updated Table 32: HSE oscillator characteristics.

Table 20: HSE oscillator circuit diagram: changed ‘consumption

control’ to ‘current control’

Section : HSE oscillator critical gm formula: clarified formula

Updated Table 33: HSI oscillator characteristics.

Removed ‘RAM and hardware registers’

Removed Table: RAM and hardware registers.

Updated Table 35: Flash program memory/data EEPROM memory

Added Table 36: Flash program memory.

Added Table 37: Data memory.

Updated Table 38: I/O static characteristics.

Updated Table 39: NRST pin characteristics.

Updated Table 40: TIM 1, 2, 3, and 4 electrical specifications

4

01-Jul-2009

(continued)

Section 10.3.9: SPI interface: changed title from “SPI serial

peripheral interface“.

Updated Table 41: SPI characteristics.

Figure 40: SPI timing diagram in slave mode and with CPHA = 0:

Changed title and added footnote.

Figure 41: SPI timing diagram in slave mode and with CPHA = 1:

changed the title.

Updated Table 43: ADC characteristics.

Updated Figure 43: Typical application with ADC.

Removed Table: ADC accuracy for VDDA = 3.3 V.

Updated Table 44: ADC accuracy for VDDA = 5 V.

Updated Table 46: EMI data.

Updated Table 48: Electrical sensitivities.

Added text about Ecopack in the Section 11: Package information.

Figure 48: LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat

package outline: deleted footnote.

Updated Figure 60: STM8AF526x/8x/Ax and STM8AF6269/8x/Ax

ordering information scheme1.

Added Section 13: STM8 development tools.

Updated Table 1: Device summary: added STM8AF5178,

STM8AF519A and STM8AF619A.

22-Oct-2009

5

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Revision history

Table 55. Document revision history (continued)

Date

Revision

Changes

Updated title on cover page.

Modified cover page header to clarify the part numbers covered by

the datasheets. Updated footnote on Table 1: Device summary to

add ‘P’ order codes.

Changed definition of ‘P’ order codes.

‘Q’ order codes (FASTROM and EEPROM) removed.

Reorganized the content of Section 5: Product overview.

Table 11: STM8AF526x/8x/Ax and STM8AF6269/8x/Ax pin

description updated PD7/TLI alternate function, removed caution

note for PD6/ LINUART_RX, and added note to PA1/OSCIN.

Renamed Section 7: Memory and register map, and merged content

with Section: Register map. Updated Figure 8: Register and memory

map.

13-Apr-2010

6

Renamed BL_EN and NBL_EN, BL and NBL, respectively, in

Table 18: Option bytes.

Updated AFR4 definition in Table 19: Option byte description.

Added C_EXTin Table 24: General operating conditions, and

Section 10.3.1: VCAP external capacitor.

Updated t_VDDin Table 25: Operating conditions at power-up/power-

down.

Moved Table 30: Typical peripheral current consumption VDD = 5.0

V to Section : Current consumption for on-chip peripherals.

Removed V_ESD(MM)from Table 47: ESD absolute maximum ratings.

Updated Section 12: Ordering information to the devices supported

by the datasheet.

Updated Section 13: STM8 development tools.

Added STM8AF5168 and STM8AF518A part number in Figure 4,

and STM8AF618A in Figure 5. Added STM8AF52xx, STM8AF6269,

STM8AF628x, and STM8AF62Ax.

Updated D temperature range to -40 to 150°C.

Updated number of I/Os on cover page.

Added Table 23: Operating lifetime.

Restored V_ESD(MM)from Table 47: ESD absolute maximum ratings.

Table 24: General operating conditions: updated V_CAPinformation.

ESL parameter, and range D maximum junction temperature (T_J).

08-Jul-2010

7

Added STM8AF52xx and STM8AF62xx, and footnote in Section 12:

Ordering information.

Updated Section 13: STM8 development tools: added Table: Product

evolution summary, and split the beCAN time triggered

communication mode limitation in two sections.

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Table 55. Document revision history (continued)

Date

Revision

Changes

Modified references to reference manual, and Flash programming

manual in the whole document.

Added reference to AEC Q100 standard on cover page.

Renamed timer types as follows:

– Auto-reload timer to general purpose timer

– Multipurpose timer to advanced control timer

– System timer to basic timer

Introduced concept of high density Flash program memory.

Updated the number of I/Os for devices in 80-, 64-, and 48-pin

packages in Table: STM8AF52xx product line-up with CAN, Table:

STM8AF62xx product line-up without CAN, Table: STM8AF/H/P51xx

product line-up with CAN, and Table: STM8AF/H/P61xx product line-

up without CAN.

Added TMU brief description in Section 5.4: Flash program and data

EEPROM, updated TMU_MAXATT description in Table 19: Option

byte description, and TMU_MAWATT reset value in Table 18: Option

bytes.

Updated clock sources in Section 5.5.1: Features.

Added Table 4: Peripheral clock gating bits (CLK_PCKENR1).

Added calibration using TIM3 in Section 5.7.2: Auto-wakeup counter.

Added Table 8: ADC naming and Table 9: Communication peripheral

naming correspondence.

30-Jan-2011

8

Updated SPI data rate to f_MASTER/2 in Section 5.9.3: Serial

peripheral interface (SPI).

Added reset state in Table 10: Legend/abbreviation for the pin

description table.

Table: STM8A microcontroller family pin description: modified

footnotes related to PD1/SWIM, corrected wpu input for PE1 and

PE2, and renamed TIMn_CCx and TIMn_NCCx to TIMn_CHx and

TIMn_CHxN, respectively.

Section: Register map: Removed CAN register CLK_CANCCR.

Removed I2C_PECR register.

Added footnote for Px_IDR registers in Table 13: I/O port hardware

register map. Updated register reset values for Px_IDR and PD_CR1

registers.

Replaced tables describing register maps and reset values for non-

volatile memory, global configuration, reset status, TMU, clock

controller, interrupt controller, timers, communication interfaces, and

ADC, by TTable 14: General hardware register map. Added debug

module register map

Renamed Fast Active Halt mode to Active-halt mode with regulator

on, and Slow Active Halt mode to Active-halt mode with regulator off,

updated Section 5.6: Low-power operating modes, and Table 27:

Total current consumption in Halt and Active-halt modes. General

conditions for VDD applied. TA = -40 °C to 55 °C unless otherwise

stated. I_DD(FAH)and I_DD(SAH)renamed I_{DD(AH); WU(FAH)}

t

and t_WU(SAH)

renamed t_WU(AH)

.

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Revision history

Table 55. Document revision history (continued)

Date

Revision

Changes

Removed note 1 in Table 24: General operating conditions and note

1 below Figure 11: fCPUmax versus VDD.

Removed note 3 in Table 26: Total current consumption in Run, Wait

and Slow mode. General conditions for VDD apply, TA = -40 °C to

150 °C.

Removed note 2 in Table 31: HSE external clock characteristics and

Table 35: Flash program memory/data EEPROM memory

Removed note 1 in Table 37: Data memory. Modified T_WEmaximum

value in Table 36: Flash program memory and Table 37: Data

memory.

Added t_IFP(NRST)and renamed V_{F(NRST) IFP}

t

in Table 39: NRST pin

characteristics.

8

30-Jan-2011

Added recommendation concerning NRST pin level, and power

consumption sensitive applications, above Figure 39:

Recommended reset pin protection, and updated external capacitor

value.

(continued)

Updated Note 1 in Table 40: TIM 1, 2, 3, and 4 electrical

specifications.

Updated Note 1 in Table 41: SPI characteristics.

Moved know limitations to separate errata sheet.

Added “not recommended for new design” note to device family 51,

memory size 7 and 9, and temperature range B, in Figure 60:

STM8AF526x/8x/Ax and STM8AF6269/8x/Ax ordering information

scheme1.

Added Raisonance compiler in Section 13.2: Software tools.

Updated wildcards of document part numbers.

Added VFQFPN package.

Added STM8AF62A6 part number.

Table 1: Device summary updated footnote 1 and added footnote 2.

Table: STM8AF52xx product line-up with CAN and Table:

STM8AF62xx product line-up without CAN: added “P” version for all

order codes; updated size of data EEPROM for 64K devices to 2K

instead of 1.5K; updated RAM.

Figure 1: STM8AF526x/8x/Ax and STM8AF6269/8x/Ax block

diagram: updated POR, BOR and WDG; removed PDR; added

legend.

18-Jul-2012

9

Section 5.4: Flash program and data EEPROM: removed non

relevant bullet points and added a sentence about the factory

program.

Added Table 4: Peripheral clock gating bits (CLK_PCKENR1) and

updated Table 5: Peripheral clock gating bits (CLK_PCKENR2)

Section : ADC features: updated ADC input range.

Table 12: Memory model 128K: updated RAM size, RAM end

addresses, and stack roll-over addresses; updated footnote 1

Table 18: Option bytes: updated factory default setting for NOPT17;

updated footnotes.

Table 20: Voltage characteristics: updated V_DDX- V_DDto V_DDX- V_SS

.

Table 24: General operating conditions: updated V_CAP

.

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Table 55. Document revision history (continued)

Date

Revision

Changes

Table 26: Total current consumption in Run, Wait and Slow mode.

General conditions for VDD apply, TA = -40 °C to 150 °C: updated

conditions for I_DD(RUN)

.

Table 38: I/O static characteristics: added new condition and new

max values for rise and fall time; updated footnote 2.

Section 10.3.7: Reset pin characteristics: updated text below

Figure 38: Typical NRST pull-up current Ipu vs VDD

Figure 39: Recommended reset pin protection: updated unit of

capacitor.

Table 41: SPI characteristics: updated SCK high and low time

conditions and values.

Figure 42: SPI timing diagram - master mode: replaced ‘SCK input’

signals with ‘SCK output’ signals.

Updated Table 49: LQFP80 - 80-pin, 14 x 14 mm low-profile quad flat

package mechanical data, Table 50: LQFP64 - 64-pin, 10 x 10 mm

low-profile quad flat package mechanical data, Table 51: LQFP48 -

48-pin, 7 x 7 mm low-profile quad flat package mechanical data,

Table 52: LQFP32 - 32-pin, 7 x 7 mm low-profile quad flat package

mechanical data, Table 53: VFQFPN32 - 32-pin, 5 x 5 mm, 0.5 mm

pitch very thin profile fine pitch quad flat package mechanical data

9

18-Jul-2012

(continued)

Replaced Figure 48: LQFP64 - 64-pin, 10 x 10 mm low-profile quad

flat package outline, Figure 51: LQFP48 - 48-pin, 7 x 7 mm low-

profile quad flat package outline and Figure 54: LQFP32 - 32-pin, 7 x

7 mm low-profile quad flat package outline

Added Figure 49: LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat

package recommended footprint, Figure 52: LQFP48 - 48-pin, 7 x

7 mm low-profile quad flat package recommended footprint and

Figure 55: LQFP32 - 32-pin, 7 x 7 mm low-profile quad flat package

recommended footprint

Updated Figure 57: VFQFPN32 - 32-pin, 5x5 mm, 0.5 mm pitch very

thin profile fine pitch quad flat package outline

Updated Figure 60: STM8AF526x/8x/Ax and STM8AF6269/8x/Ax

ordering information scheme1

Section 13.2.2: C and assembly toolchains: added www.iar.com.

Updated:

– Table 1: Device summary,

– Table: STM8AF52xx product line-up with CAN,

– Table: STM8AF/H/P51xx product line-up with CAN,

– Table: STM8AF/H/P61xx product line-up without CAN,

– Table 11: STM8AF526x/8x/Ax and STM8AF6269/8x/Ax pin

description,

31-Mar-2014

10

– The maximum speed in Section 5.9.3: Serial peripheral interface

(SPI),

– t_TEMPReset release delay /VDD rising typical and max values in

Table 25: Operating conditions at power-up/power-down,

– The symbol t_IFP(NRST)with t_INFP(NRST)in Table 39: NRST pin

characteristics,

– The address and comment for Reset in Table 17: STM8A interrupt

table.

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Revision history

Table 55. Document revision history (continued)

Date

Revision

Changes

Added:

– Figure 7: STM8AF52x6 VFQFPN32 32-pin pinout;

– the caution in Section 5.10: Input/output specifications,

– The table footnote “Not recommended for new designs” to Table:

STM8AF/H/P51xx product line-up with CAN and Table:

STM8AF/H/P61xx product line-up without CAN.

10

31-Mar-2014

13-Jun-2014

(continued)

– The figure footnotes to Figure 7: STM8AF52x6 VFQFPN32 32-pin

pinout and Figure: VFQFPN 32-lead very thin fine pitch quad flat

no-lead package (5 x 5)

11

Added STM8AF52A6 part number.

Added:

– the third table footnote to Table 25: Operating conditions at power-

up/power-down,

– Figure 47: LQFP80 marking example (package top view),

– Figure 50: LQFP64 marking example (package top view),

– Figure 53: LQFP48 marking example (package top view),

– Figure 56: LQFP32 marking example (package top view),

– Figure 59: VFQFPN32 marking example (package top view),

– the footnote about the device marking to Figure 60:

STM8AF526x/8x/Ax and STM8AF6269/8x/Ax ordering information

scheme1.

Removed STM8AF51xx and STM8AF61xx obsolete root part

numbers, and consequently “H” products:

– Table 1: Device summary,

– Section 1: Introduction,

09-Jun-2015

12

– Section 2: Description,

– Section 3: Product line-up,

– Table 12: Memory model 128K,

– Section 10.3: Operating conditions,

– Figure 60: STM8AF526x/8x/Ax and STM8AF6269/8x/Ax ordering

information scheme1.

Moved Section 11.6: Thermal characteristics to Section 11: Package

information.

Updated:

– the product naming in the document headers and captions,

– the standard reference for EMI characteristics in Table 46: EMI

data.

Updated Table 53: VFQFPN32 - 32-pin, 5 x 5 mm, 0.5 mm pitch very

thin profile fine pitch quad flat package mechanical data

13-Jun-2016

13

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Table 55. Document revision history (continued)

Date

Revision

Changes

Updated:

– Title of Figure 7: STM8AF52x6 VFQFPN32 32-pin pinout,

(previously STM8AF5286UC VFQFPN32 32-pin pinout)

– Footnotes of Figure 60: STM8AF526x/8x/Ax and

STM8AF6269/8x/Ax ordering information scheme1

– Table 11: STM8AF526x/8x/Ax and STM8AF6269/8x/Ax pin

description replaced “STM8AF5286UC VQFPN32” with

“STM8AF52x6 VQFPN32” at header row

– Section 10.2: Absolute maximum ratings

– Section : Device marking on page 93

– Section : Device marking on page 96

– Section : Device marking on page 99

– Section : Device marking on page 104

– Section : Device marking on page 108

Added:

13-Oct-2016

14

– Footnote on Figure 47: LQFP80 marking example (package top

view), Figure 50: LQFP64 marking example (package top view),

Figure 56: LQFP32 marking example (package top view),

Figure 59: VFQFPN32 marking example (package top view).

Updated header row and PA6/USART_CK pin row on Table 11:

STM8AF526x/8x/Ax and STM8AF6269/8x/Ax pin description.

10-Nov-2016

15

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型号：	STM8AF6288TCX
厂家：	ST
描述：	Automotive 8-bit MCU with 64 Kbytes Flash, LIN, 24 MHz CPU, integrated EEPROM 可编程只读存储器电动程控只读存储器电可擦编程只读存储器时钟外围集成电路
文件：	总125页 (文件大小：1608K)
中文：	中文翻译
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STM8AF6288TCX [STMICROELECTRONICS]

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