STM8S003F3 [STMICROELECTRONICS]
Value line, 16-MHz STM8S 8-bit MCU, 8-Kbyte Flash memory, 128-byte data EEPROM, 10-bit ADC, 3 timers, UART, SPI, I²C;
| 型号： | STM8S003F3 |
| 厂家： | 
ST |
| 描述： | Value line, 16-MHz STM8S 8-bit MCU, 8-Kbyte Flash memory, 128-byte data EEPROM, 10-bit ADC, 3 timers, UART, SPI, I²C 可编程只读存储器 电动程控只读存储器 电可擦编程只读存储器 |
| 文件： | 总103页 (文件大小：1512K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
STM8S003F3 STM8S003K3
Value line, 16-MHz STM8S 8-bit MCU, 8-Kbyte Flash memory,
128-byte data EEPROM, 10-bit ADC, 3 timers, UART, SPI, I²C
Datasheet - production data
Features
Core
• 16 MHz advanced STM8 core with Harvard
TSSOP20
6.5x6.4 mm
UFQFPN20
3x3 mm
LQFP32
7x7 mm
architecture and 3-stage pipeline
• Extended instruction set
Timers
Memories
• Advanced control timer: 16-bit, 4 CAPCOM
channels, 3 complementary outputs, dead-time
insertion and flexible synchronization
• Program memory: 8 Kbyte Flash memory; data
retention 20 years at 55 °C after 100 cycles
• RAM: 1 Kbyte
• 16-bit general purpose timer, with 3 CAPCOM
channels (IC, OC or PWM)
• Data memory: 128 bytes true data EEPROM;
endurance up to 100 k write/erase cycles
• 8-bit basic timer with 8-bit prescaler
• Auto wakeup timer
Clock, reset and supply management
• Window and independent watchdog timers
• 2.95 V to 5.5 V operating voltage
• Flexible clock control, 4 master clock sources
– Low-power crystal resonator oscillator
– External clock input
Communications interfaces
• UART with clock output for synchronous
operation, SmartCard, IrDA, LIN master mode
– Internal, user-trimmable 16 MHz RC
– Internal low-power 128 kHz RC
• SPI interface up to 8 Mbit/s
2
• I C interface up to 400 Kbit/s
• Clock security system with clock monitor
Analog to digital converter (ADC)
• Power management
– Low-power modes (wait, active-halt, halt)
– Switch-off peripheral clocks individually
– Permanently active, low-consumption
power-on and power-down reset
• 10-bit ADC, ± 1 LSB ADC with up to 5
multiplexed channels, scan mode and analog
watchdog
I/Os
Interrupt management
• Up to 28 I/Os on a 32-pin package including 21
• Nested interrupt controller with 32 interrupts
• Up to 27 external interrupts on 6 vectors
high-sink outputs
• Highly robust I/O design, immune against
current injection
Development support
• Embedded single-wire interface module
(SWIM) for fast on-chip programming and non-
intrusive debugging
August 2018
DS7147 Rev 10
1/103
This is information on a product in full production.
www.st.com
Contents
STM8S003F3 STM8S003K3
Contents
1
2
3
4
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Product overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.1
4.2
4.3
4.4
4.5
4.6
4.7
4.8
4.9
Central processing unit STM8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Single wire interface module (SWIM) and debug module (DM) . . . . . . . . 13
Interrupt controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Flash program memory and data EEPROM . . . . . . . . . . . . . . . . . . . . . . . 13
Clock controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Watchdog timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Auto wakeup counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Beeper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.10 TIM1 - 16-bit advanced control timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.11 TIM2 - 16-bit general purpose timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.12 TIM4 - 8-bit basic timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.13 Analog-to-digital converter (ADC1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.14 Communication interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.14.1 UART1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.14.2 SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2
4.14.3 I C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
5
Pinouts and pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
5.1
5.2
5.3
STM8S003K3 LQFP32 pinout and pin description . . . . . . . . . . . . . . . . . . 22
STM8S003F3 TSSOP20/UFQFPN20 pinout and pin description . . . . . . 25
Alternate function remapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
6
Memory and register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
6.1
6.2
Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
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6.2.1
6.2.2
6.2.3
I/O port hardware register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
General hardware register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
CPU/SWIM/debug module/interrupt controller registers . . . . . . . . . . . . 39
7
8
Interrupt vector mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Option bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
8.1
Alternate function remapping bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
9
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
9.1
Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
9.1.1
9.1.2
9.1.3
9.1.4
9.1.5
Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
9.2
9.3
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
9.3.1
9.3.2
9.3.3
9.3.4
9.3.5
9.3.6
9.3.7
9.3.8
9.3.9
VCAP external capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
External clock sources and timing characteristics . . . . . . . . . . . . . . . . . 61
Internal clock sources and timing characteristics . . . . . . . . . . . . . . . . . 63
Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
I/O port pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Reset pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
SPI serial peripheral interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
2
I C interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
9.3.10 10-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
9.3.11 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
10
Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
10.1 LQFP32 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
10.2 TSSOP20 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
10.3 UFQFPN20 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
10.4 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
10.4.1 Reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
10.4.2 Selecting the product temperature range . . . . . . . . . . . . . . . . . . . . . . . 97
DS7147 Rev 10
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4
Contents
11
STM8S003F3 STM8S003K3
Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
12
STM8 development tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
12.1 Emulation and in-circuit debugging tools . . . . . . . . . . . . . . . . . . . . . . . . . 99
12.2 Software tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
12.2.1 STM8 toolset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
12.2.2 C and assembly toolchains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
12.3 Programming tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
13
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
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List of tables
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
STM8S003F3/K3 value line features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Peripheral clock gating bit assignments in CLK_PCKENR1/2 registers. . . . . . . . . . . . . . . 15
TIM timer features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Legend/abbreviations for STM8S003F3/K3 pin description tables. . . . . . . . . . . . . . . . . . . 21
STM8S003K3 descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
STM8S003F3 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Flash, Data EEPROM and RAM boundary addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
I/O port hardware register map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
General hardware register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
CPU/SWIM/debug module/interrupt controller registers. . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Interrupt mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Option bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Option byte description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
STM8S003K3 alternate function remapping bits for 32-pin devices. . . . . . . . . . . . . . . . . . 44
STM8S003F3 alternate function remapping bits for 20-pin devices . . . . . . . . . . . . . . . . . . 45
Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Operating conditions at power-up/power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
Table 26.
Table 27.
Table 28.
Table 29.
Table 30.
Table 31.
Table 32.
Table 33.
Table 34.
Table 35.
Table 36.
Table 37.
Table 38.
Table 39.
Table 40.
Table 41.
Table 42.
Table 43.
Table 44.
Table 45.
Table 46.
Table 47.
Table 48.
Total current consumption with code execution in run mode at V = 5 V . . . . . . . . . . . . 52
DD
Total current consumption with code execution in run mode at V = 3.3 V . . . . . . . . . . . 53
DD
Total current consumption in wait mode at V = 5 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
DD
Total current consumption in wait mode at V = 3.3 V . . . . . . . . . . . . . . . . . . . . . . . . . . 54
DD
Total current consumption in active halt mode at V = 5 V . . . . . . . . . . . . . . . . . . . . . . . 55
DD
Total current consumption in active halt mode at V = 3.3 V . . . . . . . . . . . . . . . . . . . . . 55
DD
Total current consumption in halt mode at V = 5 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
DD
Total current consumption in halt mode at V = 3.3 V . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
DD
Wakeup times. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Total current consumption and timing in forced reset state . . . . . . . . . . . . . . . . . . . . . . . . 57
Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
HSE user external clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
HSE oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
HSI oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
RAM and hardware registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Flash program memory and data EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Output driving current (standard ports). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Output driving current (true open drain ports). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Output driving current (high sink ports). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
2
I C characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
ADC accuracy with R
ADC accuracy with R
< 10 kΩ , V = 5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
AIN
DD
< 10 kΩ R , V = 3.3 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
AIN
AIN
DD
EMS data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
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List of tables
STM8S003F3 STM8S003K3
Table 49.
Table 50.
Table 51.
Table 52.
Table 53.
EMI data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
LQFP32 - 32-pin, 7 x 7 mm low-profile quad flat package mechanical data. . . . . . . . . . . . 89
TSSOP20 – 20-lead thin shrink small outline, 6.5 x 4.4 mm, 0.65 mm pitch,
package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
UFQFPN20 - 20-lead, 3 x3 mm, 0.5 mm pitch, ultra thin fine pitch quad flat
Table 54.
package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Table 55.
Table 56.
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List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
STM8S003F3/K3 value line block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Flash memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
STM8S003K3 LQFP32 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
STM8S003F3 TSSOP20 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
STM8S003F3 UFQFPN20 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Memory map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Pin loading conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
f
versus V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
CPUmax
DD
Figure 10. External capacitor C
EXT
Figure 11. Typ. I
Figure 12. Typ. I
Figure 13. Typ. I
Figure 14. Typ. I
Figure 15. Typ. I
Figure 16. Typ. I
vs V , HSE user external clock, f
= 16 MHz . . . . . . . . . . . . . . . . . . . . 58
DD(RUN)
DD(RUN)
DD(RUN)
DD(WFI)
DD(WFI)
DD(WFI)
DD
CPU
vs f
, HSE user external clock, V = 5 V . . . . . . . . . . . . . . . . . . . . . . . . 58
CPU
DD
vs V , HSI RC osc, f
= 16 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
CPU
DD
vs. V HSE user external clock, f
= 16MHz . . . . . . . . . . . . . . . . . . . . . 59
DD
CPU
vs. f
, HSE user external clock, V = 5 V . . . . . . . . . . . . . . . . . . . . . . . . 60
CPU
DD
vs V , HSI RC osc, f
= 16 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
CPU
DD
Figure 17. HSE external clock source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Figure 18. HSE oscillator circuit diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Figure 19. Typical HSI frequency variation vs V at 4 temperatures. . . . . . . . . . . . . . . . . . . . . . . . . 64
DD
Figure 20. Typical LSI frequency variation vs V @ 4 temperatures . . . . . . . . . . . . . . . . . . . . . . . . 64
DD
Figure 21. Typical V and V vs V @ 4 temperatures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
IL
IH
DD
Figure 22. Typical pull-up resistance vs V @ 4 temperatures . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
DD
Figure 23. Typical pull-up current vs V @ 4 temperatures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
DD
Figure 24. Typ. V @ V = 5 V (standard ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
OL
DD
Figure 25. Typ. V @ V = 3.3 V (standard ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
OL
DD
Figure 26. Typ. V @ V = 5 V (true open drain ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
OL
DD
Figure 27. Typ. V @ V = 3.3 V (true open drain ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
OL
DD
Figure 28. Typ. V @ V = 5 V (high sink ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
OL
DD
Figure 29. Typ. V @ V = 3.3 V (high sink ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
OL
DD
Figure 30. Typ. V - V @ V = 5 V (standard ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
DD
OH
DD
Figure 31. Typ. V - V @ V = 3.3 V (standard ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
DD
OH
DD
Figure 32. Typ. V - V @ V = 5 V (high sink ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
DD
OH
DD
Figure 33. Typ. V - V @ V = 3.3 V (high sink ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
DD
OH
DD
Figure 34. Typical NRST V and V vs V @ 4 temperatures . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
IL
IH
DD
Figure 35. Typical NRST pull-up resistance vs V @ 4 temperatures . . . . . . . . . . . . . . . . . . . . . . . 76
DD
Figure 36. Typical NRST pull-up current vs V @ 4 temperatures . . . . . . . . . . . . . . . . . . . . . . . . . . 76
DD
Figure 37. Recommended reset pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Figure 38. SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
(1)
Figure 39. SPI timing diagram - slave mode and CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
(1)
Figure 40. SPI timing diagram - master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
2
Figure 41. Typical application with I C bus and timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Figure 42. ADC accuracy characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Figure 43. Typical application with ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Figure 44. LQFP32 - 32-pin, 7 x 7 mm low-profile quad flat package outline . . . . . . . . . . . . . . . . . . . 88
Figure 45. LQFP32 - 32-pin, 7 x 7 mm low-profile quad flat recommended footprint . . . . . . . . . . . . . 89
Figure 46. LQFP32 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Figure 47. TSSOP20 – 20-lead thin shrink small outline, 6.5 x 4.4 mm, 0.65 mm pitch,
package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
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8
List of figures
STM8S003F3 STM8S003K3
Figure 48. TSSOP20 – 20-lead thin shrink small outline, 6.5 x 4.4 mm, 0.65 mm pitch,
package footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Figure 49. TSSOP20 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Figure 50. UFQFPN20 - 20-lead, 3 x 3 mm, 0.5 mm pitch, ultra thin fine pitch quad flat
package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Figure 51. UFQFPN20 - 20-lead, 3 x 3 mm, 0.5 mm pitch, ultra thin fine pitch quad flat
package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Figure 52. UFQFPN20 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
(1)
Figure 53. STM8S003F3/K3 value line ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . 98
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Introduction
1
Introduction
This datasheet contains the description of the STM8S003F3/K3 value line features, pinout,
electrical characteristics, mechanical data and ordering information.
•
For complete information on the STM8S microcontroller memory, registers and
peripherals, please refer to the STM8S and STM8A microcontroller families reference
manual (RM0016).
•
For information on programming, erasing and protection of the internal Flash memory
please refer to the PM0051 (How to program STM8S and STM8A Flash program
memory and data EEPROM).
•
•
For information on the debug and SWIM (single wire interface module) refer to the
STM8 SWIM communication protocol and debug module user manual (UM0470).
For information on the STM8 core, please refer to the STM8 CPU programming manual
(PM0044).
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29
Description
STM8S003F3 STM8S003K3
2
Description
The STM8S003F3/K3 value line 8-bit microcontrollers offer 8 Kbytes of Flash program
memory, plus integrated true data EEPROM. They are referred to as low-density devices in
the STM8S microcontroller family reference manual (RM0016).
The STM8S003F3/K3 value line devices provide the following benefits: performance,
robustness and reduced system cost.
Device performance and robustness are ensured by true data EEPROM supporting up to
100000 write/erase cycles, advanced core and peripherals made in a state-of-the-art
technology at 16 MHz clock frequency, robust I/Os, independent watchdogs with separate
clock source, and a clock security system.
The system cost is reduced thanks to a high system integration level with internal clock
oscillators, watchdog, and brown-out reset.
Full documentation is offered as well as a wide choice of development tools.
Table 1. STM8S003F3/K3 value line features
Features
STM8S003K3
STM8S003F3
Pin count
32
28
27
7
20
16
16
7
Max. number of GPIOs (I/O)
External interrupt pins
Timer CAPCOM channels
Timer complementary outputs
A/D converter channels
High-sink I/Os
3
2
4
5
21
12
Low-density Flash program
memory (byte)
8 K
8 K
RAM (byte)
1 K
1 K
True data EEPROM (byte)
128(1)
128(1)
Multi purpose timer (TIM1), SPI, I2C, UART, Window WDG,
independent WDG, ADC, PWM timer (TIM2), 8-bit timer (TIM4)
Peripheral set
1. Without read-while-write capability.
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Block diagram
3
Block diagram
Figure 1. STM8S003F3/K3 value line block diagram
Reset block
Reset
XTAL 1-16 MHz
RC int. 16 MHz
RC int. 128 kHz
Clock controller
Detector
Reset
POR
BOR
Clock to peripherals and core
Window WDG
STM8 core
Independent WDG
Single wire
debug interface
Debug/SWIM
8 Kbyte
program Flash
128 byte
data EEPROM
400 Kbit/s
8 Mbit/s
I2C
1 Kbyte RAM
Up to
4 CAPCOM
channels
SPI
16-bit advanced control
timer (TIM1)
+ 3 complementary
outputs
LIN master
SPI emul.
UART1
Up to
3 CAPCOM
channels
16-bit general purpose
timer (TIM2)
up to 5
channels
ADC1
8-bit basic timer
(TIM4)
1/2/4 kHz beep
Beeper
AWU timer
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Product overview
STM8S003F3 STM8S003K3
4
Product overview
The following section intends to give an overview of the basic features of the
STM8S003F3/K3 value line functional modules and peripherals.
For more detailed information please refer to the corresponding family reference manual
(RM0016).
4.1
Central processing unit STM8
The 8-bit STM8 core is designed for code efficiency and performance.
It contains six internal registers which are directly addressable in each execution context, 20
addressing modes including indexed indirect and relative addressing and 80 instructions.
Architecture and registers
•
•
•
•
Harvard architecture
3-stage pipeline
32-bit wide program memory bus - single cycle fetching for most instructions
X and Y 16-bit index registers - enabling indexed addressing modes with or without
offset and read-modify-write type data manipulations
•
•
•
•
8-bit accumulator
24-bit program counter - 16-Mbyte linear memory space
16-bit stack pointer - access to a 64 K-level stack
8-bit condition code register - 7 condition flags for the result of the last instruction
Addressing
•
•
20 addressing modes
Indexed indirect addressing mode for look-up tables located anywhere in the address
space
•
Stack pointer relative addressing mode for local variables and parameter passing
Instruction set
•
•
•
•
•
•
•
80 instructions with 2-byte average instruction size
Standard data movement and logic/arithmetic functions
8-bit by 8-bit multiplication
16-bit by 8-bit and 16-bit by 16-bit division
Bit manipulation
Data transfer between stack and accumulator (push/pop) with direct stack access
Data transfer using the X and Y registers or direct memory-to-memory transfers
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Product overview
4.2
Single wire interface module (SWIM) and debug module (DM)
The single wire interface module and debug module permits non-intrusive, real-time in-
circuit debugging and fast memory programming.
SWIM
Single wire interface module for direct access to the debug module and memory
programming. The interface can be activated in all device operation modes. The maximum
data transmission speed is 145 byte/ms.
Debug module
The non-intrusive debugging module features a performance close to a full-featured
emulator. Beside memory and peripherals, also CPU operation can be monitored in real-
time by means of shadow registers.
•
•
•
•
R/W to RAM and peripheral registers in real-time
R/W access to all resources by stalling the CPU
Breakpoints on all program-memory instructions (software breakpoints)
Two advanced breakpoints, 23 predefined configurations
4.3
4.4
Interrupt controller
•
•
•
•
Nested interrupts with three software priority levels
32 interrupt vectors with hardware priority
Up to 27 external interrupts on six vectors including TLI
Trap and reset interrupts
Flash program memory and data EEPROM
•
•
•
8 Kbyte of Flash program single voltage Flash memory
128 byte true data EEPROM
User option byte area
Write protection (WP)
Write protection of Flash program memory and data EEPROM is provided to avoid
unintentional overwriting of memory that could result from a user software malfunction.
There are two levels of write protection. The first level is known as MASS (memory access
security system). MASS is always enabled and protects the main Flash program memory,
data EEPROM and option bytes.
To perform in-application programming (IAP), this write protection can be removed by
writing a MASS key sequence in a control register. This allows the application to modify the
content of main program memory and data EEPROM, or to reprogram the device option
bytes.
A second level of write protection, can be enabled to further protect a specific area of
memory known as UBC (user boot code). Refer to Figure 2.
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29
Product overview
STM8S003F3 STM8S003K3
The size of the UBC is programmable through the UBC option byte (Table 13), in increments
of 1 page (64-byte block) by programming the UBC option byte in ICP mode.
This divides the program memory into two areas:
•
•
Main program memory: 8 Kbyte minus UBC
User-specific boot code (UBC): Configurable up to 8 Kbyte
The UBC area remains write-protected during in-application programming. This means that
the MASS keys do not unlock the UBC area. It protects the memory used to store the boot
program, specific code libraries, reset and interrupt vectors, the reset routine and usually
the IAP and communication routines.
Figure 2. Flash memory organization
Option bytes
Data EEPROM (128 bytes)
Programmable
area from 64 bytes
UBC area
Remains write protected during IAP
(1 page) up to
8 Kbytes
(in 1 page steps)
Low density
Flash program
memory
(8 Kbytes)
Program memory area
Write access possible for IAP
MS36408V1
Read-out protection (ROP)
The read-out protection blocks reading and writing from/to the Flash program memory and
data EEPROM memory in ICP mode (and debug mode). Once the read-out protection is
activated, any attempt to toggle its status triggers a global erase of the program memory.
Even if no protection can be considered as totally unbreakable, the feature provides a very
high level of protection for a general purpose microcontroller.
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Product overview
4.5
Clock controller
The clock controller distributes the system clock (f
coming from different oscillators
MASTER)
to the core and the peripherals. It also manages clock gating for low power modes and
ensures clock robustness.
Features
•
Clock prescaler: To get the best compromise between speed and current
consumption the clock frequency to the CPU and peripherals can be adjusted by a
programmable prescaler.
•
Safe clock switching: Clock sources can be changed safely on the fly in run mode
through a configuration register. The clock signal is not switched until the new clock
source is ready. The design guarantees glitch-free switching.
•
•
Clock management: To reduce power consumption, the clock controller can stop the
clock to the core, individual peripherals or memory.
Master clock sources: Four different clock sources can be used to drive the master
clock:
–
–
–
–
1-16 MHz high-speed external crystal (HSE)
Up to 16 MHz high-speed user-external clock (HSE user-ext)
16 MHz high-speed internal RC oscillator (HSI)
128 kHz low-speed internal RC (LSI)
•
•
•
Startup clock: After reset, the microcontroller restarts by default with an internal
2 MHz clock (HSI/8). The prescaler ratio and clock source can be changed by the
application program as soon as the code execution starts.
Clock security system (CSS): This feature can be enabled by software. If an HSE
clock failure occurs, the internal RC (16 MHz/8) is automatically selected by the CSS
and an interrupt can optionally be generated.
Configurable main clock output (CCO): This outputs an external clock for use by the
application.
Table 2. Peripheral clock gating bit assignments in CLK_PCKENR1/2 registers
Peripheral
clock
Peripheral
clock
Peripheral
clock
Peripheral
clock
Bit
Bit
Bit
Bit
PCKEN17
TIM1
PCKEN13
UART1
PCKEN27 Reserved PCKEN23
ADC
AWU
PCKEN16 Reserved PCKEN12 Reserved PCKEN26 Reserved PCKEN22
PCKEN15
PCKEN14
TIM2
TIM4
PCKEN11
PCKEN10
SPI
I2C
PCKEN25 Reserved PCKEN21 Reserved
PCKEN24 Reserved PCKEN20 Reserved
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Product overview
STM8S003F3 STM8S003K3
4.6
Power management
For efficient power management, the application can be put in one of four different low-
power modes. You can configure each mode to obtain the best compromise between the
lowest power consumption, the fastest start-up time and available wakeup sources.
•
Wait mode: In this mode, the CPU is stopped, but peripherals are kept running. The
wakeup is performed by an internal or external interrupt or reset.
•
Active halt mode with regulator on: In this mode, the CPU and peripheral clocks are
stopped. An internal wakeup is generated at programmable intervals by the auto wake
up unit (AWU). The main voltage regulator is kept powered on, so current consumption
is higher than in active halt mode with regulator off, but the wakeup time is faster.
Wakeup is triggered by the internal AWU interrupt, external interrupt or reset.
•
•
Active halt mode with regulator off: This mode is the same as active halt with
regulator on, except that the main voltage regulator is powered off, so the wake up time
is slower.
Halt mode: In this mode the microcontroller uses the least power. The CPU and
peripheral clocks are stopped, the main voltage regulator is powered off. Wakeup is
triggered by external event or reset.
4.7
Watchdog timers
The watchdog system is based on two independent timers providing maximum security to
the applications.
Activation of the watchdog timers is controlled by option bytes or by software. Once
activated, the watchdogs cannot be disabled by the user program without performing a
reset.
Window watchdog timer
The window watchdog is used to detect the occurrence of a software fault, usually
generated by external interferences or by unexpected logical conditions, which cause the
application program to abandon its normal sequence.
The window function can be used to trim the watchdog behavior to match the application
perfectly.
The application software must refresh the counter before time-out and during a limited time
window.
A reset is generated in two situations:
1. Timeout: at 16 MHz CPU clock the time-out period can be adjusted between 75 µs up
to 64 ms.
2. Refresh out of window: the down-counter is refreshed before its value is lower than the
one stored in the window register.
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Product overview
Independent watchdog timer
The independent watchdog peripheral can be used to resolve processor malfunctions due to
hardware or software failures.
It is clocked by the 128 kHz LSI internal RC clock source, and thus stays active even in case
of a CPU clock failure
The IWDG time base spans from 60 µs to 1 s.
4.8
4.9
Auto wakeup counter
•
•
•
Used for auto wakeup from active halt mode
Clock source: internal 128 kHz internal low frequency RC oscillator or external clock
LSI clock can be internally connected to TIM1 input capture channel 1 for calibration
Beeper
The beeper function outputs a signal on the BEEP pin for sound generation. The signal is in
the range of 1, 2 or 4 kHz.
The beeper output port is only available through the alternate function remap option bit
AFR7.
4.10
TIM1 - 16-bit advanced control timer
This is a high-end timer designed for a wide range of control applications. With its
complementary outputs, dead-time control and center-aligned PWM capability, the field of
applications is extended to motor control, lighting and half-bridge driver.
•
•
16-bit up, down and up/down autoreload counter with 16-bit prescaler
Four independent capture/compare channels (CAPCOM) configurable as input
capture, output compare, PWM generation (edge and center aligned mode) and single
pulse mode output
•
•
•
•
•
Synchronization module to control the timer with external signals
Break input to force the timer outputs into a defined state
Three complementary outputs with adjustable dead time
Encoder mode
Interrupt sources: 3 x input capture/output compare, 1 x overflow/update, 1 x break
4.11
TIM2 - 16-bit general purpose timer
•
•
•
•
•
16-bit autoreload (AR) up-counter
15-bit prescaler adjustable to fixed power of 2 ratios 1…32768
3 individually configurable capture/compare channels
PWM mode
Interrupt sources: 3 x input capture/output compare, 1 x overflow/update
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Product overview
STM8S003F3 STM8S003K3
4.12
TIM4 - 8-bit basic timer
•
•
•
8-bit autoreload, adjustable prescaler ratio to any power of 2 from 1 to 128
Clock source: CPU clock
Interrupt source: 1 x overflow/update
Table 3. TIM timer features
Timer
synchr-
onization/
chaining
Counter
size
(bits)
CAPCOM
Counting
mode
Complem.
outputs
Ext.
trigger
Timer
Prescaler
channels
TIM1
TIM2
TIM4
16
16
8
Any integer from 1 to 65536
Any power of 2 from 1 to 32768
Any power of 2 from 1 to 128
Up/down
Up
4
3
0
3
0
0
Yes
No
No
No
Up
4.13
Analog-to-digital converter (ADC1)
STM8S003F3/K3 value line products contain a 10-bit successive approximation A/D
converter (ADC1) with up to 5 external multiplexed input channels and the following main
features:
•
•
•
•
•
•
•
•
•
•
Input voltage range: 0 to V
DDA
Conversion time: 14 clock cycles
Single and continuous, buffered continuous conversion modes
Buffer size (10 x 10 bits)
Scan mode for single and continuous conversion of a sequence of channels
Analog watchdog capability with programmable upper and lower thresholds
Analog watchdog interrupt
External trigger input
Trigger from TIM1 TRGO
End of conversion (EOC) interrupt
Note:
Additional AIN12 analog input is not selectable in ADC scan mode or with analog watchdog.
Values converted from AIN12 are stored only into the ADC_DRH/ADC_DRL registers.
4.14
Communication interfaces
The following communication interfaces are implemented:
•
UART1: full feature UART, synchronous mode, SPI master mode, SmartCard mode,
IrDA mode, LIN2.1 master capability
•
•
SPI: full and half-duplex, 8 Mbit/s
I²C: up to 400 Kbit/s
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4.14.1
UART1
Main features
•
•
•
•
•
•
•
1 Mbit/s full duplex SCI
SPI emulation
High precision baud rate generator
Smartcard emulation
IrDA SIR encoder decoder
LIN master mode
Single wire half duplex mode
Asynchronous communication (UART mode)
•
•
Full duplex communication - NRZ standard format (mark/space)
Programmable transmit and receive baud rates up to 1 Mbit/s (f
following any standard baud rate regardless of the input frequency
Separate enable bits for transmitter and receiver
Two receiver wakeup modes:
/16) and capable of
CPU
•
•
–
–
Address bit (MSB)
Idle line (interrupt)
•
•
Transmission error detection with interrupt generation
Parity control
Synchronous communication
•
•
•
•
Full duplex synchronous transfers
SPI master operation
8-bit data communication
Maximum speed: 1 Mbit/s at 16 MHz (f
/16)
CPU
LIN master mode
•
•
Emission: generates 13-bit synch. break frame
Reception: detects 11-bit break frame
4.14.2
SPI
•
•
•
•
•
•
•
Maximum speed: 8 Mbit/s (f
/2) both for master and slave
MASTER
Full duplex synchronous transfers
Simplex synchronous transfers on two lines with a possible bidirectional data line
Master or slave operation - selectable by hardware or software
CRC calculation
1 byte Tx and Rx buffer
Slave/master selection input pin
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29
Product overview
2
STM8S003F3 STM8S003K3
4.14.3
I C
•
I2C master features
–
–
Clock generation
Start and stop generation
•
I2C slave features
–
–
Programmable I2C address detection
Stop bit detection
•
•
Generation and detection of 7-bit/10-bit addressing and general call
Supports different communication speeds
–
–
Standard speed (up to 100 kHz)
Fast speed (up to 400 kHz)
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STM8S003F3 STM8S003K3
Pinouts and pin descriptions
5
Pinouts and pin descriptions
Table 4. Legend/abbreviations for STM8S003F3/K3 pin description tables
Type
I = input, O = output, S = power supply
Input
CM = CMOS
Level
Output
HS = high sink
O1 = slow (up to 2 MHz)
O2 = fast (up to 10 MHz)
Output speed
O3 = fast/slow programmability with slow as default state after reset
O4 = fast/slow programmability with fast as default state after reset
Input
float = floating, wpu = weak pull-up
Port and control
configuration
Output
T = true open drain, OD = open drain, PP = push pull
Bold x (pin state after internal reset release)
Reset state
Unless otherwise specified, the pin state is the same during the reset phase
and after the internal reset release.
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Pinouts and pin descriptions
STM8S003F3 STM8S003K3
5.1
STM8S003K3 LQFP32 pinout and pin description
Figure 3. STM8S003K3 LQFP32 pinout
32 31 30 29 28 27 26 25
24
NRST
OSCIN/PA1
OSCOUT/PA2
VSS
1
2
3
4
5
6
7
8
PC7 (HS)/SPI_MISO
PC6 (HS)/SPI_MOSI
23
22
21
20
19
18
17
PC5 (HS)/SPI_SCK
PC4 (HS)/TIM1_CH4/CLK_CCO
VCAP
PC3 (HS)/TIM1_CH3
PC2 (HS)/TIM1_CH2
PC1 (HS)/TIM1_CH1/UART1_CK
VDD
[SPI_NSS] TIM2_CH3/(HS)PA3
PF4
PE5 (HS)/SPI_NSS
9 10 11 12 13 14 15 16
MS37740V1
Table 5. STM8S003K3 descriptions
Input
Output
Alternate
function
after remap
[option bit]
Default
alternate
function
Pin name
1
2
NRST
PA1/OSCIN(2)
I/O
I/O
-
X
-
-
-
-
-
-
Reset
-
-
Resonator/
crystal in
X
X
X
O1
X
X
Port A1
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DS7147 Rev 10
STM8S003F3 STM8S003K3
Pinouts and pin descriptions
Table 5. STM8S003K3 descriptions (continued)
Input
Output
Alternate
Default
function
Pin name
alternate
after remap
function
[option bit]
Resonator/
crystal out
3
PA2/OSCOUT
I/O
X
X
X
-
O1
X
X
Port A2
-
4
5
6
VSS
S
S
S
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Digital ground
-
-
-
VCAP
VDD
1.8 V regulator capacitor
Digital power supply
SPI master/
slave select
[AFR1]
PA3/TIM2_CH3
[SPI_NSS]
Timer 2
7
I/O
X
X
X
HS O3
X
X Port A3
channel 3
8
9
PF4
PB7
I/O
I/O
I/O
I/O
I/O
X
X
X
X
X
X
X
X
-
-
-
-
-
-
-
-
O1
O1
O1
X
X
X
X Port F4
X Port B7
X Port B6
-
-
-
-
-
-
-
-
10 PB6
-
11 PB5/I2C_SDA
12 PB4/I2C_SCL
X
X
O1 T(3)
O1 T(3)
-
-
Port B5 I2C data
Port B4 I2C clock
-
Analog
Port B3 input 3/Timer 1
external trigger
PB3/AIN3
13
I/O
I/O
X
X
X
X
X
X
HS O3
HS O3
X
X
X
X
-
-
[TIM1_ETR]
Analog
input 2/Timer 1
- inverted
PB2/AIN2
14
Port B2
[TIM1_CH3N]
channel 3
Analog
PB1/AIN1
15
input 1/Timer 1
Port B1
I/O
I/O
X
X
X
X
X
X
HS O3
HS O3
X
X
X
X
-
-
[TIM1_CH2N]
- inverted
channel 2
Analog
PB0/AIN0
16
input 0/Timer 1
Port B0
[TIM1_CH1N]
- inverted
channel 1
SPI
Port E5 master/slave
select
17 PE5/SPI_NSS
I/O
I/O
X
X
X
X
X
X
HS O3
HS O3
X
X
X
X
-
-
Timer 1 -
Port C1 channel 1
UART1 clock
PC1/TIM1_CH1/
18
UART1_CK
Timer 1-
Port C2
19 PC2/TIM1_CH2
20 PC3/TIM1_CH3
I/O
I/O
X
X
X
X
X
X
HS O3
HS O3
X
X
X
X
-
-
channel 2
Timer 1 -
Port C3
channel 3
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Pinouts and pin descriptions
STM8S003F3 STM8S003K3
Table 5. STM8S003K3 descriptions (continued)
Input
Output
Alternate
Default
function
Pin name
alternate
after remap
function
[option bit]
Timer 1 -
channel
4/configurable
clock output
PC4/TIM1_CH4/C
LK_CCO
21
I/O
X
X
X
HS O3
X
X
Port C4
-
22 PC5/SPI_SCK
23 PC6/SPI_MOSI
I/O
I/O
X
X
X
X
X
X
HS O3
HS O3
X
X
X
X
Port C5 SPI clock
-
-
SPI master
out/slave in
Port C6
Port C7
SPI master in/
slave out
24 PC7/SPI_MISO
I/O
I/O
I/O
I/O
X
X
X
X
X
X
X
X
X
X
X
X
HS O3
HS O3
HS O4
HS O3
X
X
X
X
X
X
X
X
-
Configurable
clock output
[AFR5]
PD0/[TIM1_BKIN
[CLK_CCO]
Timer 1 - break
input
25
Port D0
Port D1
Port D2
SWIM data
interface
26 PD1/SWIM(4)
-
Timer 2 -
channel 3
[AFR1]
PD2
27
-
[TIM2_CH3]
Timer 2 -
Port D3 channel2/ADC
PD3/TIM2_CH2
28
I/O
I/O
X
X
X
X
X
X
HS O3
HS O3
X
X
X
X
-
-
[ADC_ETR]
external trigger
Timer 2 -
Port D4 channel
1/BEEP output
PD4/BEEP/
29
TIM2_CH1
UART1 data
Port D5
30 PD5/ UART1_TX I/O
31 PD6/ UART1_RX I/O
PD7/TLI
X
X
X
X
X
X
HS O3
HS O3
X
X
X
X
-
-
transmit
UART1 data
Port D6
receive
Timer 1 -
channel 4
[AFR6]
Top level
Port D7
32
I/O
X
X
X
HS O3
X
X
[TIM1_CH4]
interrupt
1. I/O pins used simultaneously for high-current source/sink must be uniformly spaced around the package. In
addition, the total driven current must respect the absolute maximum ratings given in Section 9: Electrical
characteristics.
2. When the MCU is in Halt/Active-halt mode, PA1 is automatically configured in input weak pull-up and
cannot be used for waking up the device. In this mode, the output state of PA1 is not driven. It is
recommended to use PA1 only in input mode if Halt/Active-halt is used in the application.
3. In the open-drain output column, "T" defines a true open-drain I/O (P-buffer, weak pull-up, and protection
diode to VDD are not implemented).
4. The PD1 pin is in input pull-up during the reset phase and after the internal reset release.
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DS7147 Rev 10
STM8S003F3 STM8S003K3
Pinouts and pin descriptions
5.2
STM8S003F3 TSSOP20/UFQFPN20 pinout and pin
description
Figure 4. STM8S003F3 TSSOP20 pinout
1
2
UART1_CK/TIM2_CH1/BEEP/(HS)PD4
UART1_TX/AIN5/(HS) PD5
20
19
18
17
16
15
14
13
12
11
PD3 (HS)/AIN4/TIM2_CH2/ADC_ETR
PD2(HS)/AIN3/[TIM2_CH3]
PD1(HS)/SWIM
3
UART1_RX/AIN6/(HS) PD6
NRST
4
PC7(HS)/SPI_MISO [TIM1_CH2]
PC6(HS)/SPI_MOSI [TIM1_CH1]
PC5 (HS)/SPI_SCK [TIM2_CH1]
OSCIN/PA1
5
6
OSCOUT/PA2
V
SS
VCAP
PC4(HS)/TIM1_CH4/CLK_CCO/AIN2/[TIM1_CH2N]
PC3(HS)/TIM1_CH3 [TLI] [TIM1_CH1N]
PB4(T)/I2C_SCL [ADC_ETR]
7
8
V
DD
9
[SPI_NSS] TIM2_CH3/(HS) PA3
10
PB5(T)/I2C_SDA [TIM1_BKIN]
MS37741V1
1. HS high sink capability.
2. (T) True open drain (P-buffer and protection diode to VDD not implemented).
3. [ ] alternate function remapping option (If the same alternate function is shown twice, it indicates an
exclusive choice not a duplication of the function).
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29
Pinouts and pin descriptions
STM8S003F3 STM8S003K3
Figure 5. STM8S003F3 UFQFPN20 pinout
20 19 18 17 16
15
14
13
1
2
3
4
5
NRST
PD1(HS)/SWIM
OSCIN/PA1
PC7(HS)/SPI_MISO[TIM1_CH2]
PC6(HS)/SPI_MOSI [TIM1_CH1]
PC5 (HS)/SPI_SCK [TIM2_CH1]
PC4(HS)/TIM1_CH4/CLK_CCO/AIN2/[TIM1_CH2N]
OSCOUT/PA2
V
SS
12
11
VCAP
6
7
8
9
10
MS36409V1
1. HS high sink capability.
2. (T) True open drain (P-buffer and protection diode to VDD not implemented).
3. [ ] alternate function remapping option (If the same alternate function is shown twice, it indicates an
exclusive choice not a duplication of the function).
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STM8S003F3 STM8S003K3
Pinouts and pin descriptions
Table 6. STM8S003F3 pin description
Pin
no.
Input
Output
Main
function
(after
Alternate
function
after remap
[option bit]
Default
alternate
function
Pin name
Type
High
OD PP
reset)
sink(1)
Timer 2 -
channel
Port D4 1/BEEP
output/
PD4/ BEEP/
18 TIM2_ CH1/
UART1 _CK
1
I/O
X
X
X
HS
O3
X
X
-
UART1clock
Analog input
Port D5 5/ UART1
datatransmit
PD5/ AIN5/
19
2
3
I/O
I/O
X
X
X
X
X
X
HS
HS
O3
O3
X
X
X
X
-
-
UART1 _TX
Analog input
Port D6 6/ UART1
data receive
PD6/ AIN6/
20
UART1 _RX
4
5
1
2
NRST
I/O
I/O
-
X
-
-
-
-
-
-
Reset
-
-
Resonator/
Port A1
PA1/ OSCIN(2)
X
X
X
O1
X
X
crystal in
Resonator/
Port A2
6
7
8
9
3
4
5
6
PA2/ OSCOUT
VSS
I/O
S
X
-
X
-
X
-
-
-
-
-
O1
X
-
X
-
-
-
-
-
crystal out
-
-
-
Digital ground
1.8 V regulator
capacitor
VCAP
S
-
-
-
-
-
VDD
S
-
-
-
-
-
Digital power supply
SPI master/
slave select
[AFR1]
PA3/ TIM2_ CH3
[SPI_ NSS]
Timer 2
Port A3
7
8
I/O
I/O
X
X
X
-
X
X
HS
-
O3
X
X
-
10
11
channel 3
Timer 1 -
break input
[AFR4]
PB5/ I2C_ SDA
[TIM1_ BKIN]
O1 T(3)
Port B5 I2C data
ADC
external
trigger
[AFR4]
9
PB4/ I2C_ SCL
I/O
I/O
X
X
-
X
X
-
O1 T(3)
-
Port B4
Port C3
I2C clock
12
13
Top level
interrupt
[AFR3]
Timer 1 -
inverted
channel 1
[AFR7]
PC3/ TIM1_CH3
Timer 1 -
channel 3
10 [TLI]
[TIM1_ CH1N]
X
HS
O3
X
X
DS7147 Rev 10
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Pinouts and pin descriptions
STM8S003F3 STM8S003K3
Table 6. STM8S003F3 pin description (continued)
Pin
no.
Input
Output
Main
function
(after
Alternate
function
after remap
[option bit]
Default
alternate
function
Pin name
Type
High
OD PP
reset)
sink(1)
Configurable
clock
output/Timer inverted
1 - channel
4/Analog
input 2
PC4/CLK_CCO/
TIM1_
CH4/AIN2/
Timer 1 -
11
I/O
X
X
X
HS
O3
X
X
Port C4
14
channel 2
[AFR7]
[TIM1_ CH2N]
Timer 2 -
channel 1
[AFR0]
PC5/ SPI_SCK
[TIM2_ CH1]
12
13
14
I/O
I/O
X
X
X
X
X
X
HS
HS
O3
O3
X
X
X
X
Port C5 SPI clock
15
16
Timer 1 -
channel 1
[AFR0]
PC6/ SPI_MOSI
[TIM1_ CH1]
SPI master
Port C6
out/slave in
Timer 1 -
channel 2
[AFR0]
PC7/ SPI_MISO
[TIM1_ CH2]
SPI master
Port C7
I/O
I/O
X
X
X
X
X
X
X
X
X
HS
HS
HS
O3
O4
O3
X
X
X
X
X
X
17
18
19
in/ slave out
SWIM data
Port D1
15 PD1/ SWIM(4)
-
interface
Timer 2 -
channel 3
[AFR1]
PD2/AIN3/
16
Analog input
I/O
Port D2
3
[TIM2_ CH3]
Analog input
4/ Timer 2 -
channel
2/ADC
external
trigger
PD3/ AIN4/
17 TIM2_ CH2/
ADC_ ETR
I/O
X
X
X
HS
O3
X
X
Port D3
-
20
1. I/O pins used simultaneously for high current source/sink must be uniformly spaced around the package. In addition, the
total driven current must respect the absolute maximum ratings.
2. When the MCU is in halt/active-halt mode, PA1 is automatically configured in input weak pull-up and cannot be used for
waking up the device. In this mode, the output state of PA1 is not driven. It is recommended d to use PA1 only in input mode
if halt/active-halt is used in the application.
3. In the open-drain output column, "T" defines a true open-drain I/O (P-buffer, weak pull-up, and protection diode to VDD are
not implemented).
4. The PD1 pin is in input pull-up during the reset phase and after internal reset release.
28/103
DS7147 Rev 10
STM8S003F3 STM8S003K3
Pinouts and pin descriptions
5.3
Alternate function remapping
As shown in the rightmost column of the pin description table, some alternate functions can
be remapped at different I/O ports by programming one of eight AFR (alternate function
remap) option bits. Refer to Section 8: Option bytes. When the remapping option is active,
the default alternate function is no longer available.
To use an alternate function, the corresponding peripheral must be enabled in the peripheral
registers.
Alternate function remapping does not effect GPIO capabilities of the I/O ports (see the
GPIO section of the family reference manual, RM0016).
DS7147 Rev 10
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29
Memory and register map
STM8S003F3 STM8S003K3
6
Memory and register map
6.1
Memory map
Figure 6. Memory map
0x00 0000
RAM
(1 Kbyte)
513 byte stack
Reserved
0x00 03FF
0x00 0800
0x00 4000
0x00 407F
Data EEPROM
Reserved
0x00 47FF
0x00 4800
0x00 480A
0x00 480B
Option bytes
Reserved
0x00 4FFF
0x00 5000
GPIO and periph. reg.
0x00 57FF
0x00 5800
Reserved
0x00 7EFF
0x00 7F00
CPU/SWIM/debug/ITC
registers
0x00 7FFF
0x00 8000
32 interrupt vectors
0x00 807F
0x00 8080
Flash program memory
(8 Kbyte)
0x00 9FFF
0x00 A000
Reserved
0x02 7FFF
MS36410V1
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STM8S003F3 STM8S003K3
Memory and register map
Table 7 lists the boundary addresses for each memory size. The top of the stack is at the
RAM end address in each case.
Table 7. Flash, Data EEPROM and RAM boundary addresses
Memory area
Flash program memory
RAM
Size (byte)
8 K
Start address
0x00 8000
End address
0x00 9FFF
0x00 03FF
1 K
0x00 0000
Data EEPROM
128
0x00 4000
0x00 407F
6.2
Register map
6.2.1
I/O port hardware register map
Table 8. I/O port hardware register map
Reset
status
Address
Block
Register label
Register name
0x00 5000
0x00 5001
0x00 5002
0x00 5003
0x00 5004
0x00 5005
0x00 5006
0x00 5007
0x00 5008
0x00 5009
0x00 500A
0x00 500B
0x00 500C
0x00 500D
0x00 500E
0x00 500F
0x00 5010
0x00 5011
0x00 5012
0x00 5013
PA_ODR
PA_IDR
Port A data output latch register
Port A input pin value register
Port A data direction register
Port A control register 1
0x00
0xXX(1)
0x00
Port A
PA_DDR
PA_CR1
PA_CR2
PB_ODR
PB_IDR
PB_DDR
PB_CR1
PB_CR2
PC_ODR
PB_IDR
PC_DDR
PC_CR1
PC_CR2
PD_ODR
PD_IDR
PD_DDR
PD_CR1
PD_CR2
0x00
Port A control register 2
0x00
Port B data output latch register
Port B input pin value register
Port B data direction register
Port B control register 1
0x00
0xXX(1)
Port B
Port C
Port D
0x00
0x00
Port B control register 2
0x00
Port C data output latch register
Port C input pin value register
Port C data direction register
Port C control register 1
0x00
0xXX(1)
0x00
0x00
Port C control register 2
0x00
Port D data output latch register
Port D input pin value register
Port D data direction register
Port D control register 1
0x00
0xXX(1)
0x00
0x02
Port D control register 2
0x00
DS7147 Rev 10
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41
Memory and register map
Address
STM8S003F3 STM8S003K3
Table 8. I/O port hardware register map (continued)
Reset
status
Block
Register label
Register name
0x00 5014
0x00 5015
0x00 5016
0x00 5017
0x00 5018
0x00 5019
0x00 501A
0x00 501B
0x00 501C
0x00 501D
PE_ODR
PE_IDR
PE_DDR
PE_CR1
PE_CR2
PF_ODR
PF_IDR
PF_DDR
PF_CR1
PF_CR2
Port E data output latch register
Port E input pin value register
Port E data direction register
Port E control register 1
0x00
0xXX(1)
0x00
Port E
0x00
Port E control register 2
0x00
Port F data output latch register
Port F input pin value register
Port F data direction register
Port F control register 1
0x00
0xXX(1)
Port F
0x00
0x00
Port F control register 2
0x00
1. Depends on the external circuitry.
6.2.2
General hardware register map
32/103
DS7147 Rev 10
STM8S003F3 STM8S003K3
Memory and register map
Table 9. General hardware register map
Reset
status
Address
Block
Register label
Register name
0x00 501E to
0x00 5059
Reserved area (60 byte)
0x00 505A
0x00 505B
0x00 505C
0x00 505D
0x00 505E
FLASH_CR1
FLASH_CR2
FLASH_NCR2
FLASH _FPR
FLASH _NFPR
Flash control register 1
Flash control register 2
0x00
0x00
0xFF
0x00
0xFF
Flash complementary control register 2
Flash protection register
Flash
Flash complementary protection register
Flash in-application programming status
register
0x00 505F
FLASH _IAPSR
0x00
0x00 5060 to
0x00 5061
Reserved area (2 byte)
Flash Program memory unprotection
register
0x00 5062
Flash
Flash
FLASH _PUKR
FLASH _DUKR
0x00
0x00
0x00 5063
0x00 5064
Reserved area (1 byte)
Data EEPROM unprotection register
0x00 5065 to
0x00 509F
Reserved area (59 byte)
0x00 50A0
0x00 50A1
EXTI_CR1
EXTI_CR2
External interrupt control register 1
External interrupt control register 2
0x00
0x00
ITC
RST
CLK
0x00 50A2 to
0x00 50B2
Reserved area (17 byte)
Reset status register
0x00 50B3
RST_SR
0xXX(1)
0x00 50B4 to
0x00 50BF
Reserved area (12 byte)
0x00 50C0
0x00 50C1
0x00 50C2
0x00 50C3
0x00 50C4
0x00 50C5
0x00 50C6
0x00 50C7
0x00 50C8
0x00 50C9
0x00 50CA
0x00 50CB
CLK_ICKR
CLK_ECKR
Internal clock control register
External clock control register
Reserved area (1 byte)
0x01
0x00
CLK_CMSR
CLK_SWR
Clock master status register
Clock master switch register
Clock switch control register
Clock divider register
0xE1
0xE1
0xXX
0x18
0xFF
0x00
0x00
0xFF
CLK_SWCR
CLK_CKDIVR
CLK_PCKENR1
CLK_CSSR
CLK
Peripheral clock gating register 1
Clock security system register
Configurable clock control register
Peripheral clock gating register 2
Reserved area (1 byte)
CLK_CCOR
CLK_PCKENR2
DS7147 Rev 10
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41
Memory and register map
STM8S003F3 STM8S003K3
Table 9. General hardware register map (continued)
Reset
status
Address
Block
Register label
Register name
0x00 50CC
0x00 50CD
CLK_HSITRIMR
CLK_SWIMCCR
HSI clock calibration trimming register
SWIM clock control register
0x00
CLK
0bXXXX
XXX0
0x00 50CE to
0x00 50D0
Reserved area (3 byte)
0x00 50D1
0x00 50D2
WWDG_CR
WWDG_WR
WWDG control register
WWDR window register
0x7F
0x7F
WWDG
0x00 50D3 to
0x00 50DF
Reserved area (13 byte)
0x00 50E0
0x00 50E1
0x00 50E2
IWDG_KR
IWDG_PR
IWDG_RLR
IWDG key register
IWDG prescaler register
IWDG reload register
0xXX(2)
0x00
IWDG
0xFF
0x00 50E3 to
0x00 50EF
Reserved area (13 byte)
0x00 50F0
0x00 50F1
0x00 50F2
0x00 50F3
AWU_CSR1
AWU_APR
AWU_TBR
BEEP_CSR
AWU control/status register 1
AWU asynchronous prescaler buffer register
AWU timebase selection register
BEEP control/status register
0x00
0x3F
0x00
0x1F
AWU
BEEP
0x00 50F4 to
0x00 50FF
Reserved area (12 byte)
0x00 5200
0x00 5201
0x00 5202
0x00 5203
0x00 5204
0x00 5205
0x00 5206
0x00 5207
SPI_CR1
SPI_CR2
SPI control register 1
SPI control register 2
SPI interrupt control register
SPI status register
0x00
0x00
0x00
0x02
0x00
0x07
0x00
0x00
SPI_ICR
SPI_SR
SPI
SPI_DR
SPI data register
SPI_CRCPR
SPI_RXCRCR
SPI_TXCRCR
SPI CRC polynomial register
SPI Rx CRC register
SPI Tx CRC register
0x00 5208 to
0x00 520F
Reserved area (8 byte)
0x00 5210
0x00 5211
0x00 5212
0x00 5213
0x00 5214
0x00 5215
I2C_CR1
I2C_CR2
I2C control register 1
I2C control register 2
I2C frequency register
I2C own address register low
I2C own address register high
Reserved
0x00
0x00
0x00
0x00
0x00
I2C_FREQR
I2C_OARL
I2C_OARH
I2C
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Memory and register map
Table 9. General hardware register map (continued)
Reset
status
Address
Block
Register label
Register name
0x00 5216
0x00 5217
0x00 5218
0x00 5219
0x00 521A
0x00 521B
0x00 521C
0x00 521D
0x00 521E
I2C_DR
I2C_SR1
I2C data register
I2C status register 1
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x02
0x00
I2C_SR2
I2C status register 2
I2C_SR3
I2C status register 3
I2C
I2C_ITR
I2C interrupt control register
I2C clock control register low
I2C clock control register high
I2C TRISE register
I2C_CCRL
I2C_CCRH
I2C_TRISER
I2C_PECR
I2C packet error checking register
0x00 521F to
0x00 522F
Reserved area (17 byte)
0x00 5230
0x00 5231
0x00 5232
0x00 5233
0x00 5234
0x00 5235
0x00 5236
0x00 5237
0x00 5238
0x00 5239
0x00 523A
UART1_SR
UART1_DR
UART1 status register
UART1 data register
0xC0
0xXX
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
UART1_BRR1
UART1_BRR2
UART1_CR1
UART1_CR2
UART1_CR3
UART1_CR4
UART1_CR5
UART1_GTR
UART1_PSCR
UART1 baud rate register 1
UART1 baud rate register 2
UART1 control register 1
UART1 control register 2
UART1 control register 3
UART1 control register 4
UART1 control register 5
UART1 guard time register
UART1 prescaler register
UART1
0x00 523B to
0x00523F
Reserved area (21 byte)
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Memory and register map
STM8S003F3 STM8S003K3
Table 9. General hardware register map (continued)
Reset
status
Address
Block
Register label
Register name
0x00 5250
0x00 5251
0x00 5252
0x00 5253
0x00 5254
0x00 5255
0x00 5256
0x00 5257
0x00 5258
0x00 5259
0x00 525A
0x00 525B
0x00 525C
0x00 525D
0x00 525E
0x00 525F
0x00 5260
0x00 5261
0x00 5262
0x00 5263
0x00 5264
0x00 5265
0x00 5266
0x00 5267
0x00 5268
0x00 5269
0x00 526A
0x00 526B
0x00 526C
0x00 526D
0x00 526E
0x00 526F
TIM1_CR1
TIM1_CR2
TIM1 control register 1
TIM1 control register 2
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0xFF
0xFF
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
TIM1_SMCR
TIM1_ETR
TIM1 slave mode control register
TIM1 external trigger register
TIM1 Interrupt enable register
TIM1 status register 1
TIM1_IER
TIM1_SR1
TIM1_SR2
TIM1 status register 2
TIM1_EGR
TIM1 event generation register
TIM1 capture/compare mode register 1
TIM1 capture/compare mode register 2
TIM1 capture/compare mode register 3
TIM1 capture/compare mode register 4
TIM1 capture/compare enable register 1
TIM1 capture/compare enable register 2
TIM1 counter high
TIM1_CCMR1
TIM1_CCMR2
TIM1_CCMR3
TIM1_CCMR4
TIM1_CCER1
TIM1_CCER2
TIM1_CNTRH
TIM1_CNTRL
TIM1_PSCRH
TIM1_PSCRL
TIM1_ARRH
TIM1_ARRL
TIM1_RCR
TIM1 counter low
TIM1
TIM1 prescaler register high
TIM1 prescaler register low
TIM1 auto-reload register high
TIM1 auto-reload register low
TIM1 repetition counter register
TIM1 capture/compare register 1 high
TIM1 capture/compare register 1 low
TIM1 capture/compare register 2 high
TIM1 capture/compare register 2 low
TIM1 capture/compare register 3 high
TIM1 capture/compare register 3 low
TIM1 capture/compare register 4 high
TIM1 capture/compare register 4 low
TIM1 break register
TIM1_CCR1H
TIM1_CCR1L
TIM1_CCR2H
TIM1_CCR2L
TIM1_CCR3H
TIM1_CCR3L
TIM1_CCR4H
TIM1_CCR4L
TIM1_BKR
TIM1_DTR
TIM1 dead-time register
TIM1_OISR
TIM1 output idle state register
0x00 5270 to
0x00 52FF
Reserved area (147 byte)
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Memory and register map
Table 9. General hardware register map (continued)
Reset
status
Address
Block
Register label
Register name
0x00 5300
0x00 5301
0x00 5302
0x00 5303
0x00 5304
0x00 5305
0x00 5306
0x00 5307
0x00 5308
0x00 5309
0x00 530A
0x00 530B
0x00 530C
0x00 530D
0x00 530E
0x00 530F
0x00 5310
0x00 5311
0x00 5312
0x00 5313
0x00 5314
0x00 5315
0x00 5316
TIM2_CR1
TIM2 control register 1
Reserved
0x00
Reserved
TIM2_IER
TIM2_SR1
TIM2 interrupt enable register
TIM2 status register 1
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0xFF
0xFF
0x00
0x00
0x00
0x00
0x00
0x00
TIM2_SR2
TIM2 status register 2
TIM2_EGR
TIM2 event generation register
TIM2 capture/compare mode register 1
TIM2 capture/compare mode register 2
TIM2 capture/compare mode register 3
TIM2 capture/compare enable register 1
TIM2 capture/compare enable register 2
TIM2 counter high
TIM2_CCMR1
TIM2_CCMR2
TIM2_CCMR3
TIM2_CCER1
TIM2_CCER2
TIM2_CNTRH
TIM2_CNTRL
TIM2_PSCR
TIM2_ARRH
TIM2_ARRL
TIM2_CCR1H
TIM2_CCR1L
TIM2_CCR2H
TIM2_CCR2L
TIM2_CCR3H
TIM2_CCR3L
TIM2
TIM2 counter low
TIM2 prescaler register
TIM2 auto-reload register high
TIM2 auto-reload register low
TIM2 capture/compare register 1 high
TIM2 capture/compare register 1 low
TIM2 capture/compare reg. 2 high
TIM2 capture/compare register 2 low
TIM2 capture/compare register 3 high
TIM2 capture/compare register 3 low
0x00 5317 to
0x00 533F
Reserved area (43 byte)
0x00 5340
0x00 5341
0x00 5342
0x00 5343
0x00 5344
0x00 5345
0x00 5346
0x00 5347
0x00 5348
TIM4_CR1
TIM4 control register 1
Reserved
0x00
Reserved
TIM4_IER
TIM4_SR
TIM4 interrupt enable register
TIM4 status register
TIM4 event generation register
TIM4 counter
0x00
0x00
0x00
0x00
0x00
0xFF
TIM4
TIM4_EGR
TIM4_CNTR
TIM4_PSCR
TIM4_ARR
TIM4 prescaler register
TIM4 auto-reload register
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Memory and register map
STM8S003F3 STM8S003K3
Table 9. General hardware register map (continued)
Reset
status
Address
Block
Register label
Register name
0x00 5349 to
0x00 53DF
Reserved area (153 byte)
ADC data buffer registers
Reserved area (12 byte)
0x00 53E0 to
0x00 53F3
ADC1
ADC_DBxR
0x00
0x00 53F4 to
0x00 53FF
0x00 5400
0x00 5401
0x00 5402
0x00 5403
0x00 5404
0x00 5405
0x00 5406
0x00 5407
0x00 5408
0x00 5409
0x00 540A
0x00 540B
0x00 540C
0x00 540D
0x00 540E
0x00 540F
ADC _CSR
ADC_CR1
ADC control/status register
ADC configuration register 1
0x00
0x00
0x00
0x00
0xXX
0xXX
0x00
0x00
0x03
0xFF
0x00
0x00
0x00
0x00
0x00
0x00
ADC_CR2
ADC configuration register 2
ADC_CR3
ADC configuration register 3
ADC_DRH
ADC data register high
ADC_DRL
ADC data register low
ADC_TDRH
ADC_TDRL
ADC_HTRH
ADC_HTRL
ADC_LTRH
ADC_LTRL
ADC_AWSRH
ADC_AWSRL
ADC_AWCRH
ADC_AWCRL
ADC Schmitt trigger disable register high
ADC Schmitt trigger disable register low
ADC high threshold register high
ADC high threshold register low
ADC low threshold register high
ADC low threshold register low
ADC analog watchdog status register high
ADC analog watchdog status register low
ADC analog watchdog control register high
ADC analog watchdog control register low
ADC1
0x00 5410 to
0x00 57FF
Reserved area (1008 byte)
1. Depends on the previous reset source.
2. Write only register.
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Memory and register map
6.2.3
CPU/SWIM/debug module/interrupt controller registers
Table 10. CPU/SWIM/debug module/interrupt controller registers
Reset
Status
Address
Block
Register Label
Register Name
0x00 7F00
0x00 7F01
0x00 7F02
0x00 7F03
0x00 7F04
0x00 7F05
0x00 7F06
0x00 7F07
0x00 7F08
0x00 7F09
0x00 7F0A
A
Accumulator
Program counter extended
Program counter high
Program counter low
X index register high
X index register low
Y index register high
Y index register low
Stack pointer high
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x03
0xFF
0x28
PCE
PCH
PCL
XH
CPU(1)
XL
YH
YL
SPH
SPL
CCR
Stack pointer low
Condition code register
0x00 7F0B to
0x00 7F5F
Reserved area (85 byte)
0x00 7F60
0x00 7F70
0x00 7F71
0x00 7F72
0x00 7F73
0x00 7F74
0x00 7F75
0x00 7F76
0x00 7F77
CPU
ITC
CFG_GCR
ITC_SPR1
ITC_SPR2
ITC_SPR3
ITC_SPR4
ITC_SPR5
ITC_SPR6
ITC_SPR7
ITC_SPR8
Global configuration register
Interrupt software priority register 1
Interrupt software priority register 2
Interrupt software priority register 3
Interrupt software priority register 4
Interrupt software priority register 5
Interrupt software priority register 6
Interrupt software priority register 7
Interrupt software priority register 8
0x00
0xFF
0xFF
0xFF
0xFF
0xFF
0xFF
0xFF
0xFF
0x00 7F78 to
0x00 7F79
Reserved area (2 byte)
SWIM control status register
Reserved area (15 byte)
0x00 7F80
SWIM
SWIM_CSR
0x00
0x00 7F81 to
0x00 7F8F
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Memory and register map
STM8S003F3 STM8S003K3
Table 10. CPU/SWIM/debug module/interrupt controller registers (continued)
Reset
Status
Address
Block
Register Label
Register Name
0x00 7F90
0x00 7F91
0x00 7F92
0x00 7F93
0x00 7F94
0x00 7F95
0x00 7F96
0x00 7F97
0x00 7F98
0x00 7F99
0x00 7F9A
DM_BK1RE
DM_BK1RH
DM_BK1RL
DM_BK2RE
DM_BK2RH
DM_BK2RL
DM_CR1
DM breakpoint 1 register extended byte
DM breakpoint 1 register high byte
DM breakpoint 1 register low byte
DM breakpoint 2 register extended byte
DM breakpoint 2 register high byte
DM breakpoint 2 register low byte
DM debug module control register 1
DM debug module control register 2
DM debug module control/status register 1
DM debug module control/status register 2
DM enable function register
0xFF
0xFF
0xFF
0xFF
0xFF
0xFF
0x00
0x00
0x10
0x00
0xFF
DM
DM_CR2
DM_CSR1
DM_CSR2
DM_ENFCTR
0x00 7F9B to
0x00 7F9F
Reserved area (5 byte)
1. Accessible by debug module only
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Interrupt vector mapping
7
Interrupt vector mapping
Table 11. Interrupt mapping
Wakeup from Wakeup from
IRQ
no.
Source
block
Description
Vector address
Halt mode
Active-halt mode
-
-
RESET
TRAP
TLI
Reset
Yes
-
Yes
-
0x00 8000
0x00 8004
0x00 8008
0x00 800C
0x00 8010
0x00 8014
0x00 8018
0x00 801C
0x00 8020
0x00 8024
0x00 8028
0x00 802C
0x00 8030
Software interrupt
0
1
2
3
4
5
6
7
8
9
10
External top level interrupt
Auto wake up from halt
Clock controller
-
-
AWU
CLK
-
Yes
-
-
EXTI0
EXTI1
EXTI2
EXTI3
EXTI4
-
Port A external interrupts
Port B external interrupts
Port C external interrupts
Port D external interrupts
Port E external interrupts
Yes(1)
Yes
Yes
Yes
Yes
Yes(1)
Yes
Yes
Yes
Yes
Reserved
Reserved
-
SPI
End of transfer
Yes
-
Yes
-
TIM1 update/overflow/underflow/
trigger/break
11
TIM1
0x00 8034
12
13
14
15
16
17
18
19
20
21
TIM1
TIM1 capture/compare
TIM2 update /overflow
TIM2 capture/compare
-
-
-
-
-
-
0x00 8038
0x00 803C
0x00 8040
0x00 8044
0x00 8048
0x00 804C
0x00 8050
0x00 8054
0x00 8058
0x00 805C
TIM2
TIM2
-
Reserved
-
Reserved
UART1
Tx complete
-
-
-
-
UART1
Receive register DATA FULL
I2C interrupt
I2C
Yes
Yes
-
-
Reserved
Reserved
ADC1 end of conversion/analog
watchdog interrupt
22
ADC1
-
-
0x00 8060
23
24
TIM4
Flash
TIM4 update/overflow
EOP/WR_PG_DIS
-
-
-
-
0x00 8064
0x00 8068
0x00 806C to
0x00 807C
Reserved
1. Except PA1
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41
Option bytes
STM8S003F3 STM8S003K3
8
Option bytes
Option bytes contain configurations for device hardware features as well as the memory
protection of the device. They are stored in a dedicated block of the memory. Except for the
ROP (read-out protection) byte, each option byte has to be stored twice, in a regular form
(OPTx) and a complemented one (NOPTx) for redundancy.
Option bytes can be modified in ICP mode (via SWIM) by accessing the EEPROM address
shown in Table 12: Option bytes below. Option bytes can also be modified ‘on the fly’ by the
application in IAP mode, except the ROP option that can only be modified in ICP mode (via
SWIM).
Refer to the STM8S Flash programming manual (PM0051) and STM8 SWIM
communication protocol and debug module user manual (UM0470) for information on SWIM
programming procedures.
Table 12. Option bytes
Option bits
Factory
default
setting
Option
name
Option
byte no.
Addr.
7
6
5
4
3
2
1
0
Read-out
0x4800
protection
(ROP)
OPT0
ROP[7:0]
UBC[7:0]
0x00
0x4801
0x4802
0x4803
OPT1
NOPT1
OPT2
0x00
0xFF
0x00
User boot code
(UBC)
NUBC[7:0]
Alternate
function
remapping
(AFR)
AFR7
AFR6
AFR5
AFR4
AFR3
AFR2
AFR1
AFR0
0x4804
0x4805
0x4806
0x4807
0x4808
NOPT2
OPT3
NAFR7
NAFR6
NAFR5
NAFR4
NAFR3
NAFR2
NAFR1
NAFR0
0xFF
0x00
0xFF
0x00
0xFF
LSI
_EN
IWDG
_HW
WWDG
_HW
WWDG
_HALT
Reserved
Reserved
HSITRIM
Misc. option
Clock option
NHSI
TRIM
NLSI
_EN
NIWDG NWWDG NWWDG
_HW
NOPT3
OPT4
_HW
_HALT
EXT
CLK
CKAWU
SEL
PRS
C1
PRS
C0
Reserved
NEXT
CLK
NCKAW
USEL
NPR
SC1
NPR
SC0
NOPT4
Reserved
0x4809
0x480A
OPT5
HSECNT[7:0]
NHSECNT[7:0]
0x00
0xFF
HSE clock
startup
NOPT5
Table 13. Option byte description
Description
Option byte no.
ROP[7:0] Memory readout protection (ROP)
0xAA: Enable readout protection (write access via SWIM protocol)
Note: Refer to the family reference manual (RM0016) section on
Flash/EEPROM memory readout protection for details.
OPT0
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Option byte no.
Option bytes
Table 13. Option byte description (continued)
Description
UBC[7:0] User boot code area
0x00: no UBC, no write-protection
0x01: Pages 0 defined as UBC, memory write-protected
0x02: Pages 0 to 1 defined as UBC, memory write-protected
Page 0 and page 1 contain the interrupt vectors.
...
0x7F: Pages 0 to 126 defined as UBC, memory write-protected
Other values: Pages 0 to 127 defined as UBC, memory-write protected.
Note: Refer to the family reference manual (RM0016) section on
Flash/EEPROM write protection for more details.
OPT1
OPT2
AFR[7:0]
Refer to the following section for alternate function remapping descriptions
of bits [7:2] and [1:0] respectively.
HSITRIM: high-speed internal clock trimming register size
0: 3-bit trimming supported in CLK_HSITRIMR register
1: 4-bit trimming supported in CLK_HSITRIMR register
LSI_EN: Low speed internal clock enable
0: LSI clock is not available as CPU clock source
1: LSI clock is available as CPU clock source
IWDG_HW: Independent watchdog
OPT3
0: IWDG Independent watchdog activated by software
1: IWDG Independent watchdog activated by hardware
WWDG_HW: Window watchdog activation
0: WWDG window watchdog activated by software
1: WWDG window watchdog activated by hardware
WWDG_HALT: Window watchdog reset on halt
0: No reset generated on halt if WWDG active
1: Reset generated on halt if WWDG active
EXTCLK: External clock selection
0: External crystal connected to OSCIN/OSCOUT
1: External clock signal on OSCIN
CKAWUSEL: Auto wakeup unit/clock
0: LSI clock source selected for AWU
1: HSE clock with prescaler selected as clock source for for AWU
OPT4
PRSC[1:0] AWU clock prescaler
0x: 16 MHz to 128 kHz prescaler
10: 8 MHz to 128 kHz prescaler
11: 4 MHz to 128 kHz prescaler
HSECNT[7:0]: HSE crystal oscillator stabilization time
This configures the stabilization time.
0x00: 2048 HSE cycles
OPT5
0xB4: 128 HSE cycles
0xD2: 8 HSE cycles
0xE1: 0.5 HSE cycles
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Option bytes
STM8S003F3 STM8S003K3
8.1
Alternate function remapping bits
Table 14. STM8S003K3 alternate function remapping bits for 32-pin devices
Option byte number
Description(1)
AFR7Alternate function remapping option 7
Reserved.
AFR6 Alternate function remapping option 6
0: AFR6 remapping option inactive: default alternate function(2)
1: Port D7 alternate function = TIM1_CH4.
AFR5 Alternate function remapping option 5
0: AFR5 remapping option inactive: default alternate function(2)
1: Port D0 alternate function = CLK_CCO.
OPT2
AFR[4:2] Alternate function remapping option 4:2
Reserved.
AFR1 Alternate function remapping option 1
0: AFR1 remapping option inactive: default alternate function(2)
1: Port A3 alternate function = SPI_NSS; port D2 alternate function
TIM2_CH3
AFR0 Alternate function remapping option 0
Reserved.
1. Do not use more than one remapping option in the same port. It is forbidden to enable both AFR1 and
AFR0
2. Refer to the pinout description.
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Option bytes
Table 15. STM8S003F3 alternate function remapping bits for 20-pin devices
Option byte number
Description
AFR7Alternate function remapping option 7
0: AFR7 remapping option inactive: default alternate function(1)
1: Port C3 alternate function = TIM1_CH1N; port C4 alternate function =
TIM1_CH2N.
AFR6 Alternate function remapping option 6
Reserved.
AFR5 Alternate function remapping option 5
Reserved.
AFR4 Alternate function remapping option 4
0: AFR4 remapping option inactive: default alternate function(1)
.
1: Port B4 alternate function = ADC_ETR; port B5 alternate function =
TIM1_BKIN.
OPT2
AFR3 Alternate function remapping option 3
0: AFR3 remapping option inactive: default alternate function(1)
1: Port C3 alternate function = TLI.
AFR2 Alternate function remapping option 2
Reserved.
AFR1 Alternate function remapping option 1 (2)
0: AFR1 remapping option inactive: default alternate function(1)
1: Port A3 alternate function = SPI_NSS; port D2 alternate function =
TIM2_CH3.
AFR0 Alternate function remapping option 0(2)
0: AFR0 remapping option inactive: Default alternate functions(1)
1: Port C5 alternate function = TIM2_CH1; port C6 alternate function =
TIM1_CH1; port C7 alternate function = TIM1_CH2.
1. Refer to the pinout description.
2. Do not use more than one remapping option in the same port. It is forbidden to enable both AFR1 and
AFR0.
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Electrical characteristics
STM8S003F3 STM8S003K3
9
Electrical characteristics
9.1
Parameter conditions
Unless otherwise specified, all voltages are referred to V
.
SS
9.1.1
Minimum and maximum values
Unless otherwise specified the minimum and maximum values are guaranteed in the worst
conditions of ambient temperature, supply voltage and frequencies by tests in production on
100% of the devices with an ambient temperature at T = 25 °C and T = T (given by
A
A
Amax
the selected temperature range).
Data based on characterization results, design simulation and/or technology characteristics
are indicated in the table footnotes and are not tested in production. Based on
characterization, the minimum and maximum values refer to sample tests and represent the
mean value plus or minus three times the standard deviation (mean ± 3 Σ).
9.1.2
Typical values
Unless otherwise specified, typical data are based on T = 25 °C, V = 5 V. They are given
A
DD
only as design guidelines and are not tested.
Typical ADC accuracy values are determined by characterization of a batch of samples from
a standard diffusion lot over the full temperature range, where 95% of the devices have an
error less than or equal to the value indicated (mean ± 2 Σ).
9.1.3
9.1.4
Typical curves
Unless otherwise specified, all typical curves are given only as design guidelines and are
not tested.
Loading capacitor
The loading conditions used for pin parameter measurement are shown in Figure 7.
Figure 7. Pin loading conditions
STM8 pin
50 pF
9.1.5
Pin input voltage
The input voltage measurement on a pin of the device is described in Figure 8.
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Figure 8. Pin input voltage
STM8 pin
V
IN
9.2
Absolute maximum ratings
Stresses above the absolute maximum ratings listed in Table 16: Voltage characteristics,
Table 17: Current characteristics and Table 18: Thermal characteristics may cause
permanent damage to the device. These are stress ratings only and functional operation of
the device at these conditions is not implied. Exposure to maximum rating conditions for
extended periods may affect the device’s reliability.
The device’s mission profile (application conditions) is compliant with JEDEC JESD47
Qualification Standard, extended mission profiles are available on demand.
Table 16. Voltage characteristics
Symbol
DDx - VSS Supply voltage(1)
Ratings
Min
Max
Unit
V
-0.3
6.5
6.5
Input voltage on true open drain pins(2)
Input voltage on any other pin(2)
VSS - 0.3
V
VIN
VSS - 0.3 VDD + 0.3
|VDDx - VDD| Variations between different power pins
-
-
50
50
mV
-
|VSSx - VSS| Variations between all the different ground pins
see Absolute maximum
ratings (electrical
VESD
Electrostatic discharge voltage
sensitivity) on page 86
1. All power (VDD) and ground (VSS) pins must always be connected to the external power supply
2. IINJ(PIN) must never be exceeded. This is implicitly insured if VIN maximum is respected. If VIN maximum
cannot be respected, the injection current must be limited externally to the IINJ(PIN) value. A positive
injection is induced by VIN>VDD while a negative injection is induced by VIN<VSS. For true open-drain pads,
there is no positive injection current, and the corresponding VIN maximum must always be respected
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Electrical characteristics
Symbol
STM8S003F3 STM8S003K3
Table 17. Current characteristics
Ratings
Max.(1)
Unit
IVDD
IVSS
Total current into VDD power lines (source)(2)
Total current out of VSS ground lines (sink)(2)
Output current sunk by any I/O and control pin
Output current source by any I/Os and control pin
Injected current on NRST pin
100
80
20
IIO
-20
±4
(3)(4)
IINJ(PIN)
Injected current on OSCIN pin
±4
Injected current on any other pin(5)
±4
(3)
mA
ΣIINJ(PIN)
Total injected current (sum of all I/O and control pins)(5)
±20
1. Data based on characterization results.
2. All power (VDD) and ground (VSS) pins must always be connected to the external supply.
3. IINJ(PIN) must never be exceeded. This is implicitly insured if VIN maximum is respected. If VIN maximum
cannot be respected, the injection current must be limited externally to the IINJ(PIN) value. A positive
injection is induced by VIN>VDD while a negative injection is induced by VIN<VSS. For true open-drain pads,
there is no positive injection current, and the corresponding VIN maximum must always be respected
4. ADC accuracy vs. negative injection current: Injecting negative current on any of the analog input pins
should be avoided as this significantly reduces the accuracy of the conversion being performed on another
analog input. It is recommended to add a Schottky diode (pin to ground) to standard analog pins which may
potentially inject negative current. Any positive injection current within the limits specified for IINJ(PIN) and
ΣIINJ(PIN) in the I/O port pin characteristics section does not affect the ADC accuracy.
5. When several inputs are submitted to a current injection, the maximum ΣIINJ(PIN) is the absolute sum of the
positive and negative injected currents (instantaneous values). These results are based on characterization
with ΣIINJ(PIN) maximum current injection on four I/O port pins of the device.
Table 18. Thermal characteristics
Symbol
Ratings
Value
Unit
TSTG
TJ
Storage temperature range
-65 to 150
150
°C
Maximum junction temperature
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9.3
Operating conditions
The device must be used in operating conditions that respect the parameters in Table 19. In
addition, full account must be taken of all physical capacitor characteristics and tolerances.
Table 19. General operating conditions
Symbol
Parameter
Conditions
Min
Max
Unit
fCPU
VDD
Internal CPU clock frequency
Standard operating voltage
-
-
0
16
MHz
V
2.95
5.5
CEXT: capacitance of external
capacitor
-
470
3300
nF
(1)
VCAP
ESR of external capacitor
ESL of external capacitor
-
-
-
-
-
0.3
15
ohm
nH
At 1 MHz(2)
TSSOP20
UFQFPN20
LQFP32
238
220
330
Power dissipation at
TA = 85° C for suffix 6
(3)
PD
mW
°C
Ambient temperature for 6
suffix version
TA
TJ
Maximum power dissipation
-
-40
-40
85
Junction temperature range
for 6 suffix version
105
1. Care should be taken when selecting the capacitor, due to its tolerance, as well as the parameter
dependency on temperature, DC bias and frequency in addition to other factors. The parameter maximum
values must be respected for the full application range.
2. This frequency of 1 MHz as a condition for VCAP parameters is given by the design of the internal regulator.
3. To calculate PDmax(TA), use the formula PDmax = (TJmax - TA)/ΘJA (see Section 10.4: Thermal
characteristics on page 96) with the value for TJmax given in Table 19 above and the value for ΘJA given in
Table 55: Thermal characteristics.
Figure 9. f
versus V
DD
CPUmax
fCPU (MHz)
Functionality
not guaranteed
in this area
16
12
8
Functionality guaranteed
@TA -40 to 85 °C
4
0
4.0
Supply voltage
2.95
5.0
5.5
MS36411V1
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Symbol
STM8S003F3 STM8S003K3
Table 20. Operating conditions at power-up/power-down
Parameter
Conditions
Min
Typ
Max
Unit
VDD rise time rate
VDD fall time rate(1)
-
-
2
2
-
-
∞
∞
tVDD
µs/V
Reset release
delay
tTEMP
VIT+
VDD rising
-
-
1.7
2.85
2.8
-
ms
V
Power-on reset
threshold
-
-
-
2.6
2.5
-
2.7
2.65
70
Brown-out reset
threshold
VIT-
V
Brown-out reset
hysteresis
VHYS(BOR)
mV
1. Reset is always generated after a tTEMP delay. The application must ensure that VDD is still above the
minimum operating voltage (VDD min) when the tTEMP delay has elapsed.
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9.3.1
VCAP external capacitor
Stabilization for the main regulator is achieved connecting an external capacitor C
to the
EXT
V
pin. C
is specified in Table 19. Care should be taken to limit the series inductance
CAP
EXT
to less than 15 nH.
Figure 10. External capacitor C
EXT
ESL
C
ESR
RLeak
MSv36488V1
1. Legend: ESR is the equivalent series resistance and ESL is the equivalent inductance.
9.3.2
Supply current characteristics
The current consumption is measured as described in Section 9.1.5: Pin input voltage.
Total current consumption in run mode
The MCU is placed under the following conditions:
•
•
All I/O pins in input mode with a static value at V or V (no load)
DD SS
All peripherals are disabled (clock stopped by Peripheral Clock Gating registers)
except if explicitly mentioned.
Subject to general operating conditions for V and T .
DD
A
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Electrical characteristics
Symbol Parameter
STM8S003F3 STM8S003K3
Table 21. Total current consumption with code execution in run mode at V = 5 V
DD
Conditions
HSE crystal osc. (16 MHz)
Typ Max (1) Unit
2.3
2
-
2.35
2
fCPU = fMASTER = 16 MHz
HSE user ext. clock (16 MHz)
HSI RC osc. (16 MHz)
Supply
1.7
current in
run mode,
code
HSE user ext. clock (16 MHz) 0.86
-
fCPU = fMASTER/128 = 125 kHz
HSI RC osc. (16 MHz)
HSI RC osc. (16 MHz/8)
0.7
0.87
executed
from RAM
fCPU = fMASTER/128 =
15.625 kHz
0.46
0.58
fCPU = fMASTER = 128 kHz
LSI RC osc. (128 kHz)
0.41
4.5
0.55
-
IDD(RUN)
mA
HSE crystal osc. (16 MHz)
HSE user ext. clock (16 MHz)
HSI RC osc.(16 MHz)
fCPU = fMASTER = 16 MHz
4.3
4.75
4.5
1.05
0.9
Supply
3.7
current in
run mode,
code
executed
from Flash
fCPU = fMASTER = 2 MHz
HSI RC osc. (16 MHz/8)(2)
0.84
0.72
fCPU = fMASTER/128 = 125 kHz
HSI RC osc. (16 MHz)
fCPU = fMASTER/128 =
15.625 kHz
HSI RC osc. (16 MHz/8)
LSI RC osc. (128 kHz)
0.46
0.42
0.58
0.57
fCPU = fMASTER = 128 kHz
1. Data based on characterization results.
2. Default clock configuration measured with all peripherals off.
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Table 22. Total current consumption with code execution in run mode at V = 3.3 V
DD
Symbol Parameter
Conditions
HSE crystal osc. (16 MHz)
Typ Max(1) Unit
1.8
2
-
2.3
2
fCPU = fMASTER = 16 MHz
HSE user ext. clock (16 MHz)
HSI RC osc. (16 MHz)
Supply
1.5
current in
run mode,
code
executed
from RAM
HSE user ext. clock (16 MHz) 0.81
-
fCPU = fMASTER/128 = 125 kHz
HSI RC osc. (16 MHz)
HSI RC osc. (16MHz/8)
0.7
0.87
fCPU = fMASTER/128 =
0.46
0.58
15.625 kHz
f
CPU = fMASTER = 128 kHz
LSI RC osc. (128 kHz)
0.41
4
0.55
-
IDD(RUN)
mA
HSE crystal osc. (16 MHz)
HSE user ext. clock (16 MHz)
HSI RC osc. (16 MHz)
fCPU = fMASTER = 16 MHz
3.9
4.7
4.5
1.05
0.9
Supply
3.7
current in
run mode,
code
executed
from Flash
fCPU = fMASTER = 2 MHz
HSI RC osc. (16 MHz/8)(2)
0.84
0.72
fCPU = fMASTER/128 = 125 kHz
HSI RC osc. (16 MHz)
fCPU = fMASTER/128 =
15.625 kHz
HSI RC osc. (16 MHz/8)
LSI RC osc. (128 kHz)
0.46
0.42
0.58
0.57
fCPU = fMASTER = 128 kHz
1. Data based on characterization results.
2. Default clock configuration, measured with all peripherals off.
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Total current consumption in wait mode
Table 23. Total current consumption in wait mode at V = 5 V
DD
Symbol Parameter
Conditions
HSE crystal osc. (16 MHz)
Typ Max(1) Unit
1.6
1.1
-
f
CPU = fMASTER = 16 MHz
HSE user ext. clock (16 MHz)
HSI RC osc. (16 MHz)
1.3
1.1
0.88
0.89
0.7
Supply
IDD(WFI) current in
wait mode
mA
f
CPU = fMASTER/128 = 125 kHz
HSI RC osc. (16 MHz)
fCPU = fMASTER/128 =
15.625 kHz
HSI RC osc. (16 MHz/8)(2)
LSI RC osc. (128 kHz)
0.45
0.4
0.57
0.54
fCPU = fMASTER = 128 kHz
1. Data based on characterization results.
2. Default clock configuration measured with all peripherals off.
Table 24. Total current consumption in wait mode at V = 3.3 V
DD
Symbol Parameter
Conditions
HSE crystal osc. (16 MHz)
Typ Max(1) Unit
1.1
1.1
-
fCPU = fMASTER = 16 MHz
HSE user ext. clock (16 MHz)
HSI RC osc. (16 MHz)
1.3
1.1
0.88
0.89
0.7
Supply
IDD(WFI) current in
wait mode
fCPU = fMASTER/128 = 125 kHz
HSI RC osc. (16 MHz)
mA
fCPU = fMASTER/128 =
HSI RC osc. (16 MHz/8)(2)
0.45
0.4
0.57
0.54
15.625 kHz
fCPU = fMASTER/128 =
15.625 kHz
LSI RC osc. (128 kHz)
1. Data based on characterization results.
2. Default clock configuration measured with all peripherals off.
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Total current consumption in active halt mode
Table 25. Total current consumption in active halt mode at V = 5 V
DD
Conditions
Max at
Mainvoltage
regulator
(MVR)(2)
Symbol
Parameter
Typ
85° C
Unit
Flash mode(3)
Clock source
(1)
HSE crystal oscillator
(16 MHz)
1030
200
970
150
-
Operating mode
LSI RC oscillator
(128 kHz)
260
-
On
HSE crystal oscillator
(16 MHz)
Supply current in
active halt mode
IDD(AH)
µA
Power-down mode
LSI RC oscillator
(128 kHz)
200
Operating mode
66
10
85
20
LSI RC oscillator
(128 kHz)
Off
Power-down mode
1. Data based on characterization results.
2. Configured by the REGAH bit in the CLK_ICKR register.
3. Configured by the AHALT bit in the FLASH_CR1 register.
Table 26. Total current consumption in active halt mode at V = 3.3 V
DD
Conditions
Max
at
Main voltage
regulator
(MVR)(2)
Symbol
Parameter
Typ
Unit
85° C
Flash mode(3)
Clock source
(1)
HSE crystal osc. (16 MHz)
LSI RC osc. (128 kHz)
HSE crystal osc. (16 MHz)
LSI RC osc. (128 kHz)
550
-
Operating mode
200 260
970
150 200
On
Off
Supply current
in active halt
mode
-
IDD(AH)
Power-down mode
µA
Operating mode
66
10
80
18
LSI RC osc. (128 kHz)
Power-down mode
1. Data based on characterization results.
2. Configured by the REGAH bit in the CLK_ICKR register.
3. Configured by the AHALT bit in the FLASH_CR1 register.
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Total current consumption in halt mode
Table 27. Total current consumption in halt mode at V = 5 V
DD
Max at
85°C(1)
Symbol
Parameter
Conditions
Typ
Unit
Flash in operating mode, HSI
clock after wakeup
63
75
20
IDD(H)
Supply current in halt mode
µA
Flash in power-down mode, HSI
clock after wakeup
6.0
1. Data based on characterization results.
Table 28. Total current consumption in halt mode at V = 3.3 V
DD
Max at
Symbol
Parameter
Conditions
Typ
Unit
85° C(1)
Flash in operating mode, HSI clock
after wakeup
60
75
17
IDD(H)
Supply current in halt mode
µA
Flash in power-down mode, HSI
clock after wakeup
4.5
1. Data based on characterization results.
Low-power mode wakeup times
Table 29. Wakeup times
Conditions
Symbol
Parameter
Typ
Max(1) Unit
(2)
0 to 16 MHz
CPU = fMASTER = 16 MHz.
Flash in operating
-
-
Wakeup time from wait
mode to run mode(3)
tWU(WFI)
f
0.56
-
1(6)
3(6)
2(6)
mode(5)
MVR voltage
regulator on(4)
Flash in power-down
-
mode(5)
Wakeup time active halt
mode to run mode.(3)
HSI (after
wakeup)
tWU(AH)
µs
Flash in operating
48(6)
50(6)
-
mode(5)
MVR voltage
regulator off(4)
Flash in power-down
-
mode(5)
Flash in operating mode(5)
52
54
-
-
Wakeup time from halt
mode to run mode(3)
tWU(H)
Flash in power-down mode(5)
1. Data guaranteed by design.
2. tWU(WFI) = 2 x 1/fmaster + 7 x 1/fCPU
3. Measured from interrupt event to interrupt vector fetch.
4. Configured by the REGAH bit in the CLK_ICKR register.
5. Configured by the AHALT bit in the FLASH_CR1 register.
6. Plus 1 LSI clock depending on synchronization.
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Total current consumption and timing in forced reset state
Table 30. Total current consumption and timing in forced reset state
Symbol
IDD(R)
tRESETBL
Parameter
Conditions
VDD = 5 V
VDD = 3.3 V
Typ
Max(1)
Unit
400
300
-
-
-
Supply current in reset state (2)
µA
µs
Reset pin release to vector fetch
-
150
1. Data guaranteed by design.
2. Characterized with all I/Os tied to VSS
.
Current consumption of on-chip peripherals
Subject to general operating conditions for V and T .
DD
A
HSI internal RC/f
= f
= 16 MHz, VDD = 5 V.
MASTER
CPU
Table 31. Peripheral current consumption
Parameter
Symbol
Typ.
Unit
IDD(TIM1)
IDD(TIM2)
IDD(TIM4)
IDD(UART1)
IDD(SPI)
TIM1 supply current (1)
210
130
50
TIM2 supply current (1)
TIM4 timer supply current (1)
UART1 supply current(1)
SPI supply current(1)
120
45
µA
IDD(I2C)
I2C supply current (1)
65
IDD(ADC1)
ADC1 supply current when converting(1)
1000
1. Data based on a differential IDD measurement between reset configuration and timer counter running at
16 MHz. No IC/OC programmed (no I/O pads toggling). Not tested in production.
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STM8S003F3 STM8S003K3
Current consumption curves
The following figures show the typical current consumption measured with code executing in
RAM.
Figure 11. Typ. I
vs V , HSE user external clock, f
= 16 MHz
CPU
DD(RUN)
DD
Figure 12. Typ. I
vs f
, HSE user external clock, V = 5 V
CPU DD
DD(RUN)
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Figure 13. Typ. I
vs V , HSI RC osc, f
= 16 MHz
DD(RUN)
DD
CPU
Figure 14. Typ. I
vs. V HSE user external clock, f
= 16MHz
CPU
DD(WFI)
DD
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STM8S003F3 STM8S003K3
Figure 15. Typ. I
vs. f
, HSE user external clock, V = 5 V
CPU DD
DD(WFI)
Figure 16. Typ. I
vs V , HSI RC osc, f = 16 MHz
CPU
DD(WFI)
DD
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9.3.3
External clock sources and timing characteristics
HSE user external clock
Subject to general operating conditions for V and T .
DD
A
Table 32. HSE user external clock characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
User external clock source
frequency
fHSE_ext
0
-
16
MHz
OSCIN input pin high level
voltage
(1)
VHSEH
-
0.7 x VDD
VSS
-
-
-
VDD + 0.3 V
0.3 x VDD
+1
V
OSCIN input pin low level
voltage
(1)
VHSEL
OSCIN input leakage
current
ILEAK_HSE
VSS < VIN < VDD
-1
µA
1. Data based on characterization results.
Figure 17. HSE external clock source
V
V
HSEH
HSEL
f
HSE
External clock
source
OSCIN
STM8
MS36489V2
HSE crystal/ceramic resonator oscillator
The HSE clock can be supplied with a 1 to 16 MHz crystal/ceramic resonator oscillator. All
the information given in this paragraph is based on characterization results with specified
typical external components. In the application, the resonator and the load capacitors have
to be placed as close as possible to the oscillator pins in order to minimize output distortion
and start-up stabilization time. Refer to the crystal resonator manufacturer for more details
(frequency, package, accuracy...).
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Table 33. HSE oscillator characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
External high speed oscillator
frequency
fHSE
-
1
-
16
MHz
RF
Feedback resistor
-
-
-
-
220
-
-
kΩ
C(1)
Recommended load capacitance (2)
20
pF
C = 20 pF,
OSC = 16 MHz
6 (startup)
-
-
-
-
f
1.6 (stabilized)(3)
IDD(HSE) HSE oscillator power consumption
mA
C = 10 pF,
fOSC = 16 MHz
6 (startup)
1.2 (stabilized)(3)
gm
Oscillator transconductance
Startup time
-
5
-
-
-
-
mA/V
ms
(4)
tSU(HSE)
VDD is stabilized
1
1. C is approximately equivalent to 2 x crystal Cload.
2. The oscillator selection can be optimized in terms of supply current using a high quality resonator with small Rm value.
Refer to crystal manufacturer for more details
3. Data based on characterization results.
4. tSU(HSE) is the start-up time measured from the moment it is enabled (by software) to a stabilized 16 MHz oscillation is
reached. This value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer.
Figure 18. HSE oscillator circuit diagram
R
m
fHSE to core
CO
RF
L
m
m
CL1
C
OSCIN
g
m
Resonator
Consumption
control
Resonator
OSCOUT
CL2
STM8
MS36490V3
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HSE oscillator critical g formula
m
gmcrit = (2 × Π × fHSE)2 × Rm(2Co + C)2
R : Notional resistance (see crystal specification)
m
L : Notional inductance (see crystal specification)
m
C : Notional capacitance (see crystal specification)
m
Co: Shunt capacitance (see crystal specification)
C =C =C: Grounded external capacitance
L1
L2
g >> g
m
mcrit
9.3.4
Internal clock sources and timing characteristics
Subject to general operating conditions for V and T .
DD
A
High speed internal RC oscillator (HSI)
Table 34. HSI oscillator characteristics
Symbol
Parameter
Frequency
Conditions
Min
Typ
Max
Unit
fHSI
-
-
16
-
MHz
User-trimmed with the
CLK_HSITRIMR register
for given VDD and TA
conditions(1)
Accuracy of HSI oscillator
-
-
1.0(2)
ACCHSI
%
Accuracy of HSI oscillator VDD = 5 V,
-5
-
-
-
5
(factory calibrated)
-40 °C ≤ TA ≤ 85 °C
HSI oscillator wakeup
time including calibration
tsu(HSI)
-
-
1.0(2)
250(3)
µs
HSI oscillator power
consumption
IDD(HSI)
-
170
µA
1. See the application note.
2. Guaranteed by design.
3. Data based on characterization results.
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Figure 19. Typical HSI frequency variation vs V at 4 temperatures
DD
Low speed internal RC oscillator (LSI)
Subject to general operating conditions for V and T .
DD
A
Table 35. LSI oscillator characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
fLSI
Frequency
-
-
-
-
-
-
128
-
7(1)
-
kHz
µs
tsu(LSI) LSI oscillator wakeup time
IDD(LSI) LSI oscillator power consumption
1. Guaranteed by design.
-
5
µA
Figure 20. Typical LSI frequency variation vs V @ 4 temperatures
DD
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9.3.5
Memory characteristics
RAM and hardware registers
Table 36. RAM and hardware registers
Symbol
Parameter
Conditions
Min
Unit
(2)
VRM
Data retention mode(1)
Halt mode (or reset)
VIT-max
V
1. Minimum supply voltage without losing data stored in RAM (in halt mode or under reset) or in hardware
registers (only in halt mode). Guaranteed by design.
2. Refer to Table 20 on page 50 for the value of VIT-max
.
Flash program memory and data EEPROM
General conditions: T = -40 to 85 °C.
A
Table 37. Flash program memory and data EEPROM
Symbol
Parameter
Conditions
Min(1) Typ Max
Unit
Operating voltage
(all modes, execution/write/erase)
VDD
fCPU ≤ 16 MHz
2.95
-
-
5.5
6.6
V
Standard programming time (including
erase) for byte/word/block
-
6.0
ms
(1 byte/4 bytes/64 bytes)
tprog
Fast programming time for 1 block (64
bytes)
-
-
-
-
3.0
3.0
-
3.3
3.3
-
ms
ms
Erase time for 1 block (64 bytes)
terase
Erase/write cycles(2)
(program memory)
100
NRW
TA = 85 °C
cycles
Erase/write cycles(2)
(data memory)
100 k
20
-
-
-
-
Data retention (program memory)
after 100 erase/write cycles at
TA = 85 °C
T
RET = 55° C
tRET
Data retention (data memory) after
10 k erase/write cycles at TA = 85 °C
years
mA
20
1.0
-
-
-
-
-
-
Data retention (data memory) after
100 k erase/write cycles at TA = 85 °C
TRET = 85° C
-
Supply current (Flash programming or
erasing for 1 to 128 bytes)
IDD
2.0
1. Data based on characterization results.
2. The physical granularity of the memory is 4 bytes, so cycling is performed on 4 bytes even when a
write/erase operation addresses a single byte.
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9.3.6
I/O port pin characteristics
General characteristics
Subject to general operating conditions for V and T unless otherwise specified. All
DD
A
unused pins must be kept at a fixed voltage: using the output mode of the I/O for example or
an external pull-up or pull-down resistor.
Table 38. I/O static characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Input low level
voltage
VIL
-0.3
-
0.3 x VDD
V
Input high level
voltage
VDD = 5 V
VIH
0.7 x VDD
-
VDD + 0.3 V
V
Vhys
Rpu
Hysteresis(1)
-
700
55
-
mV
Pull-up resistor
VDD = 5 V, VIN = VSS
30
80
kΩ
Fast I/Os
Load = 50 pF
-
-
-
-
20(2)
ns
ns
Rise and fall time
(10% - 90%)
tR, tF
Standard and high sink I/Os
Load = 50 pF
125(2)
Input leakage
current,
analog and digital
Ilkg
VSS ≤ VIN ≤ VDD
-
-
±1
µA
Analog input
leakage current
Ilkg ana
Ilkg(inj)
VSS ≤ VIN ≤ VDD
-
-
-
-
±250 (3)
±1(3)
nA
µA
Leakage current in
adjacent I/O
Injection current ±4 mA
1. Hysteresis voltage between Schmitt trigger switching levels. Based on characterization results.
2. Data guaranteed by design.
3. Data based on characterization results.
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Figure 21. Typical V and V vs V @ 4 temperatures
IL
IH
DD
Figure 22. Typical pull-up resistance vs V @ 4 temperatures
DD
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Figure 23. Typical pull-up current vs V @ 4 temperatures
DD
1. The pull-up is a pure resistor (slope goes through 0).
Table 39. Output driving current (standard ports)
Symbol
Parameter
Conditions
Min
Max
Unit
Output low level with 8 pins sunk
Output low level with 4 pins sunk
IIO = 10 mA, VDD = 5 V
IIO = 4 mA, VDD = 3.3 V
-
-
2
1(1)
-
VOL
V
Output high level with 8 pins sourced IIO = 10 mA, VDD = 5 V
Output high level with 4 pins sourced IIO = 4 mA, VDD = 3.3 V
2.8
2.1(1)
VOH
V
-
1. Data based on characterization results.
Table 40. Output driving current (true open drain ports)
Symbol
Parameter
Conditions
Max
Unit
I
IO = 10 mA, VDD = 5 V
1
VOL
Output low level with 2 pins sunk
IIO = 10 mA, VDD = 3.3 V
IIO = 20 mA, VDD = 5 V
1.5(1)
2(1)
V
1. Data based on characterization results.
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Table 41. Output driving current (high sink ports)
Symbol
Parameter
Conditions
Min
Max
Unit
Output low level with 8 pins sunk
Output low level with 4 pins sunk
Output low level with 4 pins sunk
Output high level with 8 pins sourced
Output high level with 4 pins sourced
Output high level with 4 pins sourced
IIO = 10 mA, VDD = 5 V
IIO = 10 mA, VDD = 3.3 V
IIO = 20 mA, VDD = 5 V
IIO = 10 mA, VDD = 5 V
IIO = 10 mA, VDD = 3.3 V
IIO = 20 mA, VDD = 5 V
-
-
0.8
VOL
1.0(1)
-
1.5(1)
V
4.0
2.1(1)
3.3(1)
-
-
-
VOH
1. Data based on characterization results.
Typical output level curves
Figure 25 to Figure 32 show typical output level curves measured with output on a single
pin.
Figure 24. Typ. V @ V = 5 V (standard ports)
OL
DD
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Figure 25. Typ. V @ V = 3.3 V (standard ports)
OL
DD
Figure 26. Typ. V @ V = 5 V (true open drain ports)
OL
DD
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Figure 27. Typ. V @ V = 3.3 V (true open drain ports)
OL
DD
Figure 28. Typ. V @ V = 5 V (high sink ports)
OL
DD
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Figure 29. Typ. V @ V = 3.3 V (high sink ports)
OL
DD
Figure 30. Typ. V
V
@ V = 5 V (standard ports)
DD - OH DD
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Figure 31. Typ. V
V
@ V = 3.3 V (standard ports)
DD - OH DD
Figure 32. Typ. V
V
@ V = 5 V (high sink ports)
DD - OH DD
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Figure 33. Typ. V
V
@ V = 3.3 V (high sink ports)
DD - OH DD
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9.3.7
Reset pin characteristics
Subject to general operating conditions for V and T unless otherwise specified.
DD
A
Table 42. NRST pin characteristics
Symbol
Parameter
Conditions
Min
Typ 1)
Max
Unit
VIL(NRST)
VIH(NRST)
VOL(NRST)
RPU(NRST)
tIFP(NRST)
NRST input low level voltage (1)
NRST input high level voltage (1)
NRST output low level voltage (1)
NRST pull-up resistor (2)
-
-0.3 V
-
-
0.3 x VDD
-
0.7 x VDD
VDD + 0.3
V
IOL= 2 mA
-
30
-
-
0.5
80
75
-
-
-
-
-
55
-
kΩ
ns
ns
µs
NRST input filtered pulse (3)
tINFP(NRST) NRST Input not filtered pulse (3)
tOP(NRST)
NRST output pulse (1)
500
20
-
-
-
1. Data based on characterization results.
2. The RPU pull-up equivalent resistor is based on a resistive transistor.
3. Data guaranteed by design.
Figure 34. Typical NRST V and V vs V @ 4 temperatures
IL
IH
DD
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Figure 35. Typical NRST pull-up resistance vs V @ 4 temperatures
DD
Figure 36. Typical NRST pull-up current vs V @ 4 temperatures
DD
The reset network shown in Figure 37 protects the device against parasitic resets. The user
must ensure that the level on the NRST pin can go below the V max. level specified in
IL
Table 38. Otherwise the reset is not taken into account internally. For power consumption
sensitive applications, the capacity of the external reset capacitor can be reduced to limit
charge/discharge current. If the NRST signal is used to reset the external circuitry, care
must be taken of the charge/discharge time of the external capacitor to fulfill the external
device’s reset timing conditions. The minimum recommended capacity is 10 nF.
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Figure 37. Recommended reset pin protection
STM8
VDD
RPU
External
reset
circuit
NRST
Filter
0.1 μF
(Optional)
MSv36491V1
SPI serial peripheral interface
9.3.8
Unless otherwise specified, the parameters given in Table 43 are derived from tests
performed under ambient temperature, f frequency and V supply voltage
MASTER
DD
conditions. t
= 1/f
.
MASTER
MASTER
Refer to I/O port characteristics for more details on the input/output alternate function
characteristics (NSS, SCK, MOSI, MISO).
Table 43. SPI characteristics
Symbol
Parameter
Conditions
Master mode
Slave mode
Min
Max
Unit
0
0
8
7
fSCK
1/tc(SCK)
SPI clock frequency
MHz
tr(SCK)
tf(SCK)
SPI clock rise and fall time Capacitive load: C = 30 pF
-
25
(1)
tsu(NSS)
NSS setup time
NSS hold time
Slave mode
Slave mode
4 x tMASTER
70
-
-
(1)
th(NSS)
(1)
tw(SCKH)
tw(SCKL)
SCK high and low time
Data input setup time
Master mode
tSCK/2 - 15
tSCK/2 + 15
(1)
(1)
Master mode
5
5
-
tsu(MI)
tsu(SI)
(1)
Slave mode
-
ns
(1)
Master mode
7
-
th(MI)
th(SI)
Data input hold time
(1)
Slave mode
10
-
-
(1)(2)
ta(SO)
Data output access time
Data output disable time
Data output valid time
Data output valid time
Slave mode
3 x tMASTER
(1)(3)
tdis(SO)
tv(SO)
tv(MO)
th(SO)
Slave mode
25
-
-
65
30
-
(1)
(1)
(1)
(1)
Slave mode (after enable edge)
Master mode (after enable edge)
Slave mode (after enable edge)
Master mode (after enable edge)
-
27
11
Data output hold time
th(MO)
-
1. Values based on design simulation and/or characterization results, and not tested in production.
2. Min time is for the minimum time to drive the output and the max time is for the maximum time to validate the data.
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3. Min time is for the minimum time to invalidate the output and the max time is for the maximum time to put the data in Hi-Z.
Figure 38. SPI timing diagram - slave mode and CPHA = 0
(1)
Figure 39. SPI timing diagram - slave mode and CPHA = 1
NSS input
tSU(NSS)
th(NSS)
tc(SCK)
CPHA=1
CPOL=0
CPHA=1
CPOL=1
tw(SCKH)
tw(SCKL)
tr(SCK)
tf(SCK)
th(SO)
tdis(SO)
tv(SO)
ta(SO)
MISO
MSB OUT
MSB IN
BIT6 OUT
LSB OUT
OUTPUT
th(SI)
tsu(SI)
MOSI
INPUT
LSB IN
BIT 1 IN
ai14135b
1. Measurement points are done at CMOS levels: 0.3 VDD and 0.7 VDD.
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(1)
Figure 40. SPI timing diagram - master mode
High
NSS input
t
c(SCK)
CPHA=0
CPOL=0
CPHA=0
CPOL=1
CPHA=1
CPOL=0
CPHA=1
CPOL=1
t
t
t
t
w(SCKH)
w(SCKL)
r(SCK)
t
su(MI)
f(SCK)
MISO
INPUT
BIT6 IN
LSB IN
MSB IN
t
h(MI)
MOSI
OUTPUT
BIT1 OUT
LSB OUT
MSB OUT
t
t
h(MO)
v(MO)
ai14136c
1. Measurement points are done at CMOS levels: 0.3 VDD and 0.7 VDD.
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2
STM8S003F3 STM8S003K3
9.3.9
I C interface characteristics
2
Table 44. I C characteristics
Standard mode I2C Fast mode I2C(1)
Symbol
Parameter
Unit
Min(2)
Max(2)
Min(2) Max(2)
tw(SCLL) SCL clock low time
tw(SCLH) SCL clock high time
tsu(SDA) SDA setup time
4.7
4.0
-
-
-
-
1.3
0.6
-
µs
-
250
0(3)
100
0(4)
-
th(SDA)
SDA data hold time
900(3)
tr(SDA)
tr(SCL)
ns
SDA and SCL rise time
-
-
1000
300
-
-
300
300
tf(SDA)
tf(SCL)
SDA and SCL fall time
th(STA)
START condition hold time
4.0
4.7
4.0
-
-
-
0.6
0.6
0.6
-
-
-
µs
tsu(STA) Repeated START condition setup time
tsu(STO) STOP condition setup time
µs
µs
pF
STOP to START condition time
tw(STO:STA)
(bus free)
4.7
-
1.3
-
-
Cb
Capacitive load for each bus line
-
400
400
1. fMASTER, must be at least 8 MHz to achieve max fast I2C speed (400kHz)
Data based on standard I2C protocol requirement, not tested in production
2.
The maximum hold time of the start condition has only to be met if the interface does not stretch the low
time
3.
4.
The device must internally provide a hold time of at least 300 ns for the SDA signal in order to bridge the
undefined region of the falling edge of SCL
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Electrical characteristics
Typical application with I C bus and timing diagram
2
Figure 41.
V
V
DD
DD
4.7 kΩ
STM8
4.7 kΩ
100 Ω
100 Ω
SDA
SCL
I²C bus
START REPEATED
START
START
t
su(STA)
SDA
t
r(SDA)
t
t
f(SDA)
su(SDA)
t
su(STA:STO)
STOP
t
t
h(STA)
t
w(SCLL)
h(SDA)
SCL
t
t
t
su(STO)
r(SCL)
t
f(SCL)
w(SCLH)
ai17490V2
1. Measurement points are made at CMOS levels: 0.3 x VDD and 0.7 x VDD
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9.3.10
10-bit ADC characteristics
Subject to general operating conditions for V
specified.
, f
, and T unless otherwise
DDA MASTER A
Table 45. ADC characteristics
Conditions
Symbol
Parameter
Min
Typ
Max
Unit
VDDA = 3 to 5.5 V
1
-
4
fADC
ADC clock frequency
MHz
VDDA = 4.5 to 5.5 V
-
1
-
-
6
VAIN
Conversion voltage range(1)
VSS
VDD
V
Internal sample and hold
capacitor
CADC
-
-
3
-
pF
f
ADC = 4 MHz
-
-
-
0.75
0.5
7
-
-
-
(1)
tS
Sampling time
µs
fADC = 6 MHz
tSTAB Wakeup time from standby
-
µs
µs
fADC = 4 MHz
fADC = 6 MHz
-
3.5
2.33
14
Total conversion time (including
tCONV
µs
sampling time, 10-bit resolution)
1/fADC
1. During the sample time the input capacitance CAIN (3 pF max) can be charged/discharged by the external
source. The internal resistance of the analog source must allow the capacitance to reach its final voltage
level within tS. After the end of the sample time tS, changes of the analog input voltage have no effect on
the conversion result. Values for the sample clock tS depend on programming.
Table 46. ADC accuracy with R
< 10 kΩ , V = 5 V
DD
AIN
Symbol
Parameter
Conditions
Typ
Max(1)
Unit
fADC = 2 MHz
fADC = 4 MHz
1.6
2.2
2.4
1.1
1.5
1.8
1.5
2.1
2.2
0.7
0.7
0.7
0.6
0.8
0.8
3.5
4
|ET|
Total unadjusted error (2)
f
ADC = 6 MHz
4.5
2.5
3
fADC = 2 MHz
fADC = 4 MHz
|EO|
|EG|
|ED|
|EL|
Offset error (2)
f
ADC = 6 MHz
fADC = 2 MHz
ADC = 4 MHz
3
3
Gain error (2)
f
3
LSB
fADC = 6 MHz
fADC = 2 MHz
4
1.5
1.5
1.5
1.5
2
Differential linearity error (2)
Integral linearity error (2)
fADC = 4 MHz
fADC = 6 MHz
fADC = 2 MHz
f
ADC = 4 MHz
fADC = 6 MHz
2
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1. Data based on characterization results.
2. ADC accuracy vs. negative injection current: Injecting negative current on any of the analog input pins
should be avoided as this significantly reduces the accuracy of the conversion being performed on another
analog input. It is recommended to add a Schottky diode (pin to ground) to standard analog pins which may
potentially inject negative current. Any positive injection current within the limits specified for IINJ(PIN) and
ΣIINJ(PIN) in Section 9.3.6 does not affect the ADC accuracy.
Table 47. ADC accuracy with R
Parameter
< 10 kΩ R , V = 3.3 V
AIN DD
AIN
Symbol
Conditions
Typ
Max(1)
Unit
fADC = 2 MHz
fADC = 4 MHz
fADC = 2 MHz
fADC = 4 MHz
fADC = 2 MHz
1.6
1.9
1
3.5
4
|ET|
Total unadjusted error(2)
Offset error(2)
2.5
2.5
3
|EO|
|EG|
|ED|
|EL|
1.5
1.3
2
Gain error(2)
LSB
f
ADC = 4 MHz
3
fADC = 2 MHz
fADC = 4 MHz
fADC = 2 MHz
fADC = 4 MHz
0.7
0.7
0.6
0.8
1.0
1.5
1.5
2
Differential linearity error(2)
Integral linearity error(2)
1. Data based on characterization results.
2. ADC accuracy vs. negative injection current: Injecting negative current on any of the analog input pins
should be avoided as this significantly reduces the accuracy of the conversion being performed on another
analog input. It is recommended to add a Schottky diode (pin to ground) to standard analog pins which may
potentially inject negative current. Any positive injection current within the limits specified for IINJ(PIN) and
ΣIINJ(PIN) in Section 9.3.6 does not affect the ADC accuracy.
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Figure 42. ADC accuracy characteristics
E
G
1023
1022
1021
V
– V
DDA
SSA
1LSB
= ----------------------------------------
IDEAL
1024
(2)
E
T
(3)
7
6
5
4
3
2
1
(1)
E
O
E
L
E
D
1 LSB
IDEAL
0
1
2
3
4
5
6
7
1021102210231024
V
V
DDA
SSA
1. Example of an actual transfer curve.
2. The ideal transfer curve
3. End point correlation line
ET = Total unadjusted error: maximum deviation between the actual and the ideal transfer curves.
E
O = Offset error: deviation between the first actual transition and the first ideal one.
EG = Gain error: deviation between the last ideal transition and the last actual one.
ED = Differential linearity error: maximum deviation between actual steps and the ideal one.
EL = Integral linearity error: maximum deviation between any actual transition and the end point correlation
line.
Figure 43. Typical application with ADC
V
DD
STM8
V
T
0.6V
R
AIN
AINx
10-bit A/D
conversion
V
AIN
C
V
T
0.6V
AIN
I
C
ADC
L
±1µA
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9.3.11
EMC characteristics
Susceptibility tests are performed on a sample basis during product characterization.
Functional EMS (electromagnetic susceptibility)
While executing a simple application (toggling 2 LEDs through I/O ports), the product is
stressed by two electromagnetic events until a failure occurs (indicated by the LEDs).
•
ESD: Electrostatic discharge (positive and negative) is applied on all pins of the device
until a functional disturbance occurs. This test conforms with the IEC 61000-4-2
standard.
•
FTB: A burst of fast transient voltage (positive and negative) is applied to V and V
through a 100 pF capacitor, until a functional disturbance occurs. This test conforms
with the IEC 61000-4-4 standard.
DD
SS
A device reset allows normal operations to be resumed. The test results are given in the
table below based on the EMS levels and classes defined in application note AN1709.
Designing hardened software to avoid noise problems
EMC characterization and optimization are performed at component level with a typical
application environment and simplified MCU software. It should be noted that good EMC
performance is highly dependent on the user application and the software in particular.
Therefore it is recommended that the user applies EMC software optimization and
prequalification tests in relation with the EMC level requested for his application.
Software recommendations
The software flowchart must include the management of runaway conditions such as:
•
•
•
Corrupted program counter
Unexpected reset
Critical data corruption (control registers...)
Prequalification trials
Most of the common failures (unexpected reset and program counter corruption) can be
recovered by applying a low state on the NRST pin or the oscillator pins for 1 second.
To complete these trials, ESD stress can be applied directly on the device, over the range of
specification values. When unexpected behavior is detected, the software can be hardened
to prevent unrecoverable errors occurring (see application note AN1015).
Table 48. EMS data
Symbol
Parameter
Conditions
Level/class
VDD = 3.3 V, TA = 25 °C,
fMASTER = 16 MHz,
conforming to IEC 61000-4-2
Voltage limits to be applied on any I/O pin to
induce a functional disturbance
VFESD
2B(1)
Fast transient voltage burst limits to be
VDD = 3.3 V, TA = 25 °C,
VEFTB applied through 100pF on VDD and VSS pins fMASTER = 16 MHz,
4A(1)
to induce a functional disturbance
conforming to IEC 61000-4-4
1. Data obtained with HSI clock configuration, after applying HW recommendations described in AN2860 -
EMC guidelines for STM8Smicrocontrollers.
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Electromagnetic interference (EMI)
Based on a simple application running on the product (toggling two LEDs through the I/O
ports), the product is monitored in terms of emission. Emission tests conform to the IEC
61967-2 standard for test software, board layout and pin loading.
Table 49. EMI data
Conditions
(1)
Max fHSE/fCPU
Symbol Parameter
Unit
Monitored
frequency band
General conditions
16 MHz/ 16 MHz/
8 MHz 16 MHz
0.1 MHz to 30 MHz
30 MHz to 130 MHz
130 MHz to 1 GHz
-
5
4
5
5
VDD = 5 V
TA = 25 °C
Peak level
SEMI
dBµV
-
LQFP32 package
conforming to IEC
61967-2
5
5
EMI level
2.5
2.5
1. Data based on characterization results.
Absolute maximum ratings (electrical sensitivity)
Based on three different tests (ESD, DLU and LU) using specific measurement methods,
the product is stressed in order to determine its performance in terms of electrical sensitivity.
For more details, refer to the application note AN1181.
Electrostatic discharge (ESD)
Electrostatic discharges (one positive then one negative pulse separated by 1 second) are
applied to the pins of each sample according to each pin combination. The sample size
depends on the number of supply pins in the device (3 parts*(n+1) supply pin). One model
can be simulated: the Human Body Model (HBM). This test conforms to the JESD22-
A114A/A115A standard. For more details, refer to the application note AN1181.
Table 50. ESD absolute maximum ratings
Maximum
Symbol
Ratings
Conditions
Class
Unit
value(1)
Electrostatic discharge voltage
(Human body model)
TA = 25°C, conforming to
VESD(HBM)
A
4000
V
V
JESD22-A114
Electrostatic discharge voltage
(Charge device model)
TA= 25°C, conforming to
JESD22-C101
VESD(CDM)
IV
1000
1. Data based on characterization results.
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Static latch-up
Electrical characteristics
Two complementary static tests are required on 10 parts to assess the latch-up
performance:
•
•
A supply overvoltage (applied to each power supply pin)
A current injection (applied to each input, output and configurable I/O pin) is performed
on each sample.
This test conforms to the EIA/JESD 78 IC latch-up standard. For more details, refer to the
application note AN1181.
Table 51. Electrical sensitivities
Symbol
Parameter
Conditions
Class(1)
TA = 25 °C
TA = 85 °C
A
A
LU
Static latch-up class
1. Class description: A Class is an STMicroelectronics internal specification. All its limits are higher than the
JEDEC specifications, that means when a device belongs to class A it exceeds the JEDEC standard. B
class strictly covers all the JEDEC criteria (international standard).
DS7147 Rev 10
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Package information
STM8S003F3 STM8S003K3
10
Package information
To meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at www.st.com.
ECOPACK® is an ST trademark.
10.1
LQFP32 package information
Figure 44. LQFP32 - 32-pin, 7 x 7 mm low-profile quad flat package outline
SEATING
PLANE
C
0.25 mm
GAUGE PLANE
ccc
C
K
D
D1
D3
L
L1
24
17
16
25
32
9
PIN 1
IDENTIFICATION
1
8
e
5V_ME_V2
1. Drawing is not to scale.
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Package information
Table 52. LQFP32 - 32-pin, 7 x 7 mm low-profile quad flat package mechanical data
millimeters
Typ
inches(1)
Symbol
Min
Max
Min
Typ
Max
A
A1
A2
b
-
0.050
1.350
0.300
0.090
8.800
6.800
-
-
1.600
0.150
1.450
0.450
0.200
9.200
7.200
-
-
0.0020
0.0531
0.0118
0.0035
0.3465
0.2677
-
-
0.0630
0.0059
0.0571
0.0177
0.0079
0.3622
0.2835
-
-
-
1.400
0.370
-
0.0551
0.0146
-
c
D
9.000
7.000
5.600
9.000
7.000
5.600
0.800
0.600
1.000
3.5°
0.3543
0.2756
0.2205
0.3543
0.2756
0.2205
0.0315
0.0236
0.0394
3.5°
D1
D3
E
8.800
6.800
-
9.200
7.200
-
0.3465
0.2677
-
0.3622
0.2835
-
E1
E3
e
-
-
-
-
L
0.450
-
0.750
-
0.0177
-
0.0295
-
L1
k
0°
7°
0°
7°
ccc
-
-
0.100
-
-
0.0039
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Figure 45. LQFP32 - 32-pin, 7 x 7 mm low-profile quad flat recommended footprint
0.80
1.20
24
17
25
16
0.50
0.30
7.30
6.10
9.70
7.30
32
9
8
1
1.20
6.10
9.70
5V_FP_V2
1. Dimensions are expressed in millimeters.
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Package information
STM8S003F3 STM8S003K3
Device marking for LQFP32
The following figure gives an example of topside marking orientation versus pin 1 identifier
location.
Other optional marking or inset/upset marks, which identify the parts throughout supply
chain operations, are not indicated below.
Figure 46. LQFP32 marking example (package top view)
Product
identification(1)
STM8S003
K6T6C
Date code
Standard ST logo
Y
WW
Revision code
Pin 1 identifier
R
MS37767V1
1. Parts marked as "ES", "E" or accompanied by an Engineering Sample notification letter, are not yet
qualified and therefore not yet ready to be used in production and any consequences deriving from such
usage will not be at ST charge. In no event, ST will be liable for any customer usage of these engineering
samples in production. ST Quality has to be contacted prior to any decision to use these Engineering
Samples to run qualification activity.
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Package information
10.2
TSSOP20 package information
Figure 47. TSSOP20 – 20-lead thin shrink small outline, 6.5 x 4.4 mm, 0.65 mm pitch,
package outline
D
20
11
10
c
E1
E
SEATING
PLANE
C
0.25 mm
GAUGE PLANE
1
PIN 1
IDENTIFICATION
k
aaa
C
A1
L
A
A2
L1
b
e
YA_ME_V3
1. Drawing is not to scale.
Table 53. TSSOP20 – 20-lead thin shrink small outline, 6.5 x 4.4 mm, 0.65 mm pitch,
package mechanical data
millimeters
Typ.
inches(1)
Symbol
Min.
Max.
Min.
Typ.
Max.
A
A1
A2
b
-
-
1.200
0.150
1.050
0.300
0.200
6.600
6.600
4.500
-
-
-
0.0472
0.0059
0.0413
0.0118
0.0079
0.2598
0.2598
0.1772
-
0.050
0.800
0.190
0.090
6.400
6.200
4.300
-
-
0.0020
0.0315
0.0075
0.0035
0.2520
0.2441
0.1693
-
-
1.000
-
0.0394
-
c
-
-
D(2)
6.500
6.400
4.400
0.650
0.600
1.000
-
0.2559
0.2520
0.1732
0.0256
0.0236
0.0394
-
E
E1(3)
e
L
0.450
-
0.750
-
0.0177
-
0.0295
-
L1
k
0°
8°
0°
8°
aaa
-
-
0.100
-
-
0.0039
1. Values in inches are converted from mm and rounded to four decimal digits.
2. Dimension "D" does not include mold flash, protrusions or gate burrs. Mold flash, protrusions or gate burrs
shall not exceed 0.15mm per side.
3. Dimension "E1" does not include interlead Flash or protrusions. Interlead Flash or protrusions shall not
exceed 0.25mm per side.
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Package information
STM8S003F3 STM8S003K3
Figure 48. TSSOP20 – 20-lead thin shrink small outline, 6.5 x 4.4 mm, 0.65 mm pitch,
package footprint
0.25
6.25
20
11
1.35
0.25
7.10 4.40
1.35
1
10
0.40
0.65
YA_FP_V1
1. Dimensions are expressed in millimeters.
Device marking for TSSOP20
The following figure gives an example of topside marking orientation versus pin 1 identifier
location. Other optional marking or inset/upset marks, which identify the parts throughout
supply chain operations, are not indicated below.
Figure 49. TSSOP20 marking example (package top view)
Standard ST logo
Product
identification(1)
8S003F3P6
Date code
Revision code
Pin 1 identifier
R
Y
WW
MS37768V1
1. Parts marked as "ES", "E" or accompanied by an Engineering Sample notification letter, are not yet
qualified and therefore not yet ready to be used in production and any consequences deriving from such
usage will not be at ST charge. In no event, ST will be liable for any customer usage of these engineering
samples in production. ST Quality has to be contacted prior to any decision to use these Engineering
Samples to run qualification activity.
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Package information
10.3
UFQFPN20 package information
Figure 50. UFQFPN20 - 20-lead, 3 x 3 mm, 0.5 mm pitch, ultra thin fine pitch quad flat
package outline
D
E
Pin 1
TOP VIEW
L1
D
D1
e
ddd
L3
10
L2
A3
A1
5
e
b
E
E1
1
15
20
16
L5
A
BOTTOM VIEW
SIDE VIEW
A0A5_ME_V4
1. Drawing is not to scale.
Table 54. UFQFPN20 - 20-lead, 3 x3 mm, 0.5 mm pitch, ultra thin fine pitch quad flat
package mechanical data
millimeters
Typ
inches(1)
Symbol
Min
Max
Min
Typ
Max
A
0.500
0.550
0.020
0.152
3.000
2.000
3.000
2.000
0.550
0.350
0.200
0.150
0.600
0.0197
0.0217
0.0008
0.060
0.0236
A1
A3
D
0.000
0.050
0.0000
0.0020
-
-
-
-
2.900
3.100
0.1142
0.1181
0.0790
0.1181
0.07905
0.0217
0.0138
0.0079
0.0059
0.1220
D1
E
-
-
-
-
2.900
3.100
0.1142
0.1220
E1
L1
L2
L3
L5
-
-
-
-
0.500
0.600
0.0197
0.0236
0.300
0.400
0.0118
0.0157
-
-
-
-
-
-
-
-
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Package information
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Table 54. UFQFPN20 - 20-lead, 3 x3 mm, 0.5 mm pitch, ultra thin fine pitch quad flat
package mechanical data (continued)
millimeters
Typ
inches(1)
Symbol
Min
Max
Min
Typ
Max
b
e
0.180
0.250
0.500
-
0.300
-
0.0071
0.0098
0.0197
-
0.0118
-
-
-
-
-
ddd
0.050
0.0020
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Figure 51. UFQFPN20 - 20-lead, 3 x 3 mm, 0.5 mm pitch, ultra thin fine pitch quad flat
package recommended footprint
A0A5_FP_V2
1. Dimensions are expressed in millimeters.
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Package information
Device marking for UFQFPN20
The following figure gives an example of topside marking orientation versus pin 1 identifier
location.
Other optional marking or inset/upset marks, which identify the parts throughout supply
chain operations, are not indicated below.
Figure 52. UFQFPN20 marking example (package top view)
Product
identification(1)
S033
Date code
Revision code
Y
WW
R
Dot (pin 1)
MS37769V1
1. Parts marked as "ES", "E" or accompanied by an Engineering Sample notification letter, are not yet
qualified and therefore not yet ready to be used in production and any consequences deriving from such
usage will not be at ST charge. In no event, ST will be liable for any customer usage of these engineering
samples in production. ST Quality has to be contacted prior to any decision to use these Engineering
Samples to run qualification activity.
DS7147 Rev 10
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Package information
STM8S003F3 STM8S003K3
10.4
Thermal characteristics
The maximum chip junction temperature (T
Table 19: General operating conditions.
) must never exceed the values given in
, in degrees Celsius, may be calculated
Jmax
The maximum chip-junction temperature, T
using the following equation:
Jmax
T
= T
+ (P
x Θ )
Jmax
Amax
Dmax JA
Where:
•
•
•
•
T
is the maximum ambient temperature in °C
is the package junction-to-ambient thermal resistance in ° C/W
Amax
Θ
JA
P
is the sum of P
and P
(P
= P
+ P
)
I/Omax
Dmax
INTmax
I/Omax
Dmax
INTmax
P
is the product of I and V , expressed in Watts. This is the maximum chip
INTmax
DD
DD
internal power.
•
P
P
V
represents the maximum power dissipation on output pins, where:
I/Omax
I/Omax
= Σ (V *I ) + Σ((V -V *I ), and taking account of the actual V /I and
OL OL
DD OH) OH
OL OL
/I of the I/Os at low and high level in the application.
OH OH
(1)
Table 55. Thermal characteristics
Parameter
Symbol
Value
Unit
Thermal resistance junction-ambient
LQFP 32 - 7 x 7 mm
60
Thermal resistance junction-ambient
TSSOP20 - 4.4 mm
Θ
84
90
°C/W
JA
Thermal resistance junction-ambient
UFQFPN20 -3 x 3 mm
1. Thermal resistances are based on JEDEC JESD51-2 with 4-layer PCB in a natural convection
environment.
10.4.1
Reference document
JESD51-2 integrated circuits thermal test method environment conditions - natural
convection (still air). Available from www.jedec.org.
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Package information
10.4.2
Selecting the product temperature range
When ordering the microcontroller, the temperature range is specified in the order code (see
(1)
Figure 53: STM8S003F3/K3 value line ordering information scheme ).
The following example shows how to calculate the temperature range needed for a given
application.
Assuming the following application conditions:
•
•
•
Maximum ambient temperature T
= 75 °C (measured according to JESD51-2)
Amax
I
= 8 mA, V = 5.0 V
DD
DDmax
Maximum 20 I/Os used at the same time in output at low level with
= 8 mA, V = 0.4 V
I
OL
OL
P
P
8 mA x 5.0 V = 400 mW
INTmax =
= 400 mW + 64 mW
Dmax
Thus: P
= 464 mW
Dmax
Using the values obtained in Section Table 55.: Thermal characteristics T
is calculated
Jmax
as follows for LQFP32 7 x 7 mm = 60 °C/W:
T
= 75 °C + (60 °C/W x 464 mW) = 75 °C + 27.8 °C = 102.8 °C
Jmax
This is within the range of the suffix 6 version parts (-40 < T < 105 °C).
J
In this case, parts must be ordered at least with the temperature range suffix 6.
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Ordering information
STM8S003F3 STM8S003K3
11
Ordering information
(1)
Figure 53. STM8S003F3/K3 value line ordering information scheme
Example:
STM8
S
003
K
3
T
6
TR
Product class
STM8 microcontroller
Family type
S = standard
Sub-family type(2)
00x = Value line sub-family
003 = low density
Pin count
F = 20 pins
K = 32 pins
Program memory size
3 = 8 Kbyte
Package type
T = LQFP
P = TSSOP
U = UFQFPN
Temperature range
6 = -40 °C to 85 °C
Package pitch
No character = 0.5 mm or 0.65 mm(3)
C = 0.8 mm(4)
Packing
No character = Tray or tube
TR = Tape and reel
1. For a list of available options (e.g. memory size, package) and orderable part numbers or for further
information on any aspect of this device, please go to www.st.com or contact the ST Sales Office nearest
to you.
2. Refer to Table 1: STM8S003F3/K3 value line features for detailed description.
3. TSSOP and UFQFPN packages.
4. LQFP package.
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STM8 development tools
12
STM8 development tools
Development tools for the STM8 microcontrollers include the full-featured STice emulation
system supported by a complete software tool package including C compiler, assembler and
integrated development environment with high-level language debugger. In addition, the
STM8 is to be supported by a complete range of tools including starter kits, evaluation
boards and a low-cost in-circuit debugger/programmer.
12.1
Emulation and in-circuit debugging tools
The STice emulation system offers a complete range of emulation and in-circuit debugging
features on a platform that is designed for versatility and cost-effectiveness. In addition,
STM8 application development is supported by a low-cost in-circuit debugger/programmer.
The STice is the fourth generation of full featured emulators from STMicroelectronics. It
offers new advanced debugging capabilities including profiling and coverage to help detect
and eliminate bottlenecks in application execution and dead code when fine tuning an
application.
In addition, STice offers in-circuit debugging and programming of STM8 microcontrollers via
the STM8 single wire interface module (SWIM), which allows non-intrusive debugging of an
application while it runs on the target microcontroller.
For improved cost effectiveness, STice is based on a modular design that allows users to
order exactly what they need to meet their development requirements and to adapt their
emulation system to support existing and future ST microcontrollers.
STice key features
•
•
•
•
•
•
•
•
•
•
Occurrence and time profiling and code coverage (new features)
Advanced breakpoints with up to 4 levels of conditions
Data breakpoints
Program and data trace recording up to 128 KB records
Read/write on the fly of memory during emulation
In-circuit debugging/programming via SWIM protocol
8-bit probe analyzer
1 input and 2 output triggers
Power supply follower managing application voltages between 1.62 to 5.5 V
Modularity that allows users to specify the components users need to meet their
development requirements and adapt to future requirements
•
Supported by free software tools that include integrated development environment
(IDE), programming software interface and assembler for STM8.
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STM8S003F3 STM8S003K3
12.2
Software tools
STM8 development tools are supported by a complete, free software package from
STMicroelectronics that includes ST Visual Develop (STVD) IDE and the ST Visual
Programmer (STVP) software interface. STVD provides seamless integration of the Cosmic
and Raisonance C compilers for STM8. A free version that outputs up to 16 Kbytes of code
is available.
12.2.1
STM8 toolset
STM8 toolset with STVD integrated development environment and STVP programming
software is available for free download at www.st.com. This package includes:
ST Visual Develop – Full-featured integrated development environment from ST, featuring
•
•
•
•
•
•
Seamless integration of C and ASM toolsets
Full-featured debugger
Project management
Syntax highlighting editor
Integrated programming interface
Support of advanced emulation features for STice such as code profiling and coverage
ST Visual Programmer (STVP) – Easy-to-use, unlimited graphical interface allowing read,
write and verify the user STM8 microcontroller Flash program memory, data EEPROM and
option bytes. STVP also offers project mode for saving programming configurations and
automating programming sequences.
12.2.2
C and assembly toolchains
Control of C and assembly toolchains is seamlessly integrated into the STVD integrated
development environment, making it possible to configure and control the building of user
application directly from an easy-to-use graphical interface.
Available toolchains include:
•
•
•
Cosmic C compiler for STM8 – One free version that outputs up to 16 Kbytes of code
is available. For more information, see www.cosmic-software.com.
Raisonance C compiler for STM8 – One free version that outputs up to 16 Kbytes of
code. For more information, see www.raisonance.com.
STM8 assembler linker – Free assembly toolchain included in the STVD toolset,
which allows users to assemble and link the user application source code.
12.3
Programming tools
During the development cycle, STice provides in-circuit programming of the STM8 Flash
microcontroller on user application board via the SWIM protocol. Additional tools are to
include a low-cost in-circuit programmer as well as ST socket boards, which provide
dedicated programming platforms with sockets for programming the user STM8.
For production environments, programmers will include a complete range of gang and
automated programming solutions from third-party tool developers already supplying
programmers for the STM8 family.
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Revision history
13
Revision history
Table 56. Document revision history
Date
Revision
Changes
12-Jul-2011
1
Initial release.
Added NRW and tRET for data EEPROM in Table:
Flash program memory and data EEPROM.
Updated RPU in Table: NRST pin characteristics
and Table: I/O static characteristics.
09-Jan-2012
2
Updated notes related to VCAP in Table: General
operating conditions.
Updated temperature condition for factory calibrated
ACCHSI in Table: HSI oscillator characteristics.
Changed SCK input to SCK output in Figure: SPI timing
12-Jun-2012
18-Dec-2014
21-Apr-2015
3
4
5
diagram - master mode.
Modified Figure: 20-lead, ultra thin, fine pitch quad flat
no-lead package outline (3 x 3) to add the package top
view.
Updated the package information for the 20-pin TSSOP
and the 20-pin UFQFPN.
Added package marking examples in Section: Package
information:
– Figure: LQFP32 marking example (package top view),
– Figure: TSSOP20 marking example (package top
view),
– Figure: UFQFPN20 marking example (package top
view).
Addition of the footnotes about D and E1 dimensions to
Table 53: TSSOP20 – 20-lead thin shrink small outline,
6.5 x 4.4 mm, 0.65 mm pitch, package mechanical data.
26-Jun-2015
23-Sep-2015
6
7
Update of the standard for EMI characteristics in
Section : Electromagnetic interference (EMI).
Correction of UART peripheral in Figure 1:
STM8S003F3/K3 value line block diagram.
Corrected text strings in Figure 10: External capacitor
CEXT and Figure 37: Recommended reset pin protection
PB4 line PP column value corrected in Table 5:
STM8S003K3 descriptions
20-Apr-2016
8
PD1 line “floating” and “wpu” column values corrected in
Table 6: STM8S003F3 pin description
SPI_RXCRCR and SPI_TXCRCR reset values
corrected in Table 9: General hardware register map
DS7147 Rev 10
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Revision history
STM8S003F3 STM8S003K3
Table 56. Document revision history (continued)
Date
Revision
Changes
Updated:
– All table footnotes from “Guaranteed by design, not
tested in production” to “Guaranteed by design” and
“Data based on characterization results, not tested in
production” to “Data based on characterization
results”
– Section 9.2: Absolute maximum ratings
– Section : Device marking for LQFP32 on page 90
– Section : Device marking for TSSOP20 on page 92
– Section : Device marking for UFQFPN20 on page 95
03-May-2017
9
– Table 54: UFQFPN20 - 20-lead, 3 x3 mm, 0.5 mm
pitch, ultra thin fine pitch quad flat package
mechanical data
– Figure 50: UFQFPN20 - 20-lead, 3 x 3 mm, 0.5 mm
pitch, ultra thin fine pitch quad flat package outline
– Figure 17: HSE external clock source was centered
into the frame.
Updated:
30-Aug-2018
10
– Table 34: HSI oscillator characteristics
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IMPORTANT NOTICE – PLEASE READ CAREFULLY
STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and
improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on
ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order
acknowledgement.
Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or
the design of Purchasers’ products.
No license, express or implied, to any intellectual property right is granted by ST herein.
Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product.
ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners.
Information in this document supersedes and replaces information previously supplied in any prior versions of this document.
© 2018 STMicroelectronics – All rights reserved
DS7147 Rev 10
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STMICROELECTR
STM8S003F3U6
8-BIT, FLASH, 16MHz, MICROCONTROLLER, QCC20, 3 X 3 MM, 0.50 MM PITCH, ROHS COMPLIANT, UFQFPN-20
STMICROELECTR
STM8S003F3U6CTR
Value line, 16 MHz STM8S 8-bit MCU, 8 Kbytes Flash, 128 bytes data EEPROM, 10-bit ADC, 3 timers, UART, SPI, I²C
STMICROELECTR
STM8S003F3U6TR
Value line, 16 MHz STM8S 8-bit MCU, 8 Kbytes Flash, 128 bytes data EEPROM, 10-bit ADC, 3 timers, UART, SPI, I²C
STMICROELECTR
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