STM8S105C4B3 [STMICROELECTRONICS]
Access line, 16 MHz STM8S 8-bit MCU, up to 32 Kbytes Flash, integrated EEPROM,10-bit ADC, timers, UART, SPI, I²C; 接入线路， 16兆赫STM8S 8位MCU ，最多32 KB闪存，集成的EEPROM ， 10位ADC ，定时器， UART ， SPI ， I²C
| 型号： | STM8S105C4B3 |
| 厂家： | 
ST |
| 描述： | Access line, 16 MHz STM8S 8-bit MCU, up to 32 Kbytes Flash, integrated EEPROM,10-bit ADC, timers, UART, SPI, I²C |
| 文件： | 总127页 (文件大小：1323K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
STM8S105xx
Access line, 16 MHz STM8S 8-bit MCU, up to 32 Kbytes Flash,
integrated EEPROM,10-bit ADC, timers, UART, SPI, I²C
Interrupt management
Nested interrupt controller with 32 interrupts
•
Up to 37 external interrupts on 6 vectors
•
Timers
LQFP48 7x7
LQFP44 10x10
UFQFPN32 5x5
LQFP32 7x7
2x 16-bit general purpose timers, with 2+3
CAPCOM channels (IC, OC or PWM)
•
•
Advanced control timer: 16-bit, 4 CAPCOM
channels, 3 complementary outputs, dead-time
insertion and flexible synchronization
SDIP32 400 ml
VFQFPN32 5x5
8-bit basic timer with 8-bit prescaler
Auto wake-up timer
•
•
•
Features
Core
Window and independent watchdog timers
16 MHz advanced STM8 core with Harvard
architecture and 3-stage pipeline
Communications interfaces
•
•
UART with clock output for synchronous
operation, Smartcard, IrDA, LIN
•
Extended instruction set
SPI interface up to 8 Mbit/s
I2C interface up to 400 Kbit/s
•
Memories
•
Medium-density Flash/EEPROM:
•
Program memory up to 32 Kbytes; data
retention 20 years at 55°C after 10 kcycles
-
-
Analog-to-digital converter (ADC)
10-bit, ±1 LSB ADC with up to 10 multiplexed
channels, scan mode and analog watchdog
•
Data memory up to 1 Kbytes true data
EEPROM; endurance 300 kcycles
I/Os
RAM: Up to 2 Kbytes
•
Up to 38 I/Os on a 48-pin package including 16
high sink outputs
•
•
Clock, reset and supply management
Highly robust I/O design, immune against current
injection
2.95 V to 5.5 V operating voltage
•
Flexible clock control, 4 master clock sources:
•
Low power crystal resonator oscillator
Development support
-
Embedded single wire interface module (SWIM)
for fast on-chip programming and non intrusive
debugging
External clock input
•
-
Internal, user-trimmable 16 MHz RC
-
Internal low power 128 kHz RC
-
Unique ID
Clock security system with clock monitor
•
96-bit unique key for each device
•
Power management:
•
Table 1: Device summary
Low power modes (wait, active-halt, halt)
-
Reference
Part number
Switch-off peripheral clocks individually
-
STM8S105xx
STM8S105K4, STM8S105K6, STM8S105S4, STM8S105S6,
STM8S105C4, STM8S105C6
Permanently active, low consumption power-on
•
and power-down reset
April 2010
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Contents
STM8S105xx
Contents
1 Introduction ..............................................................................................................8
2 Description ...............................................................................................................9
3 Block diagram ........................................................................................................11
4 Product overview ...................................................................................................12
4.1 Central processing unit STM8 .....................................................................................12
4.2 Single wire interface module (SWIM) and debug module (DM) ..................................12
4.3 Interrupt controller .......................................................................................................13
4.4 Flash program and data EEPROM memory ................................................................13
4.5 Clock controller ............................................................................................................14
4.6 Power management ....................................................................................................15
4.7 Watchdog timers ..........................................................................................................16
4.8 Auto wakeup counter ...................................................................................................16
4.9 Beeper ........................................................................................................................16
4.10 TIM1 - 16-bit advanced control timer .........................................................................17
4.11 TIM2, TIM3 - 16-bit general purpose timers ..............................................................17
4.12 TIM4 - 8-bit basic timer ..............................................................................................17
4.13 Analog-to-digital converter (ADC1) ............................................................................18
4.14 Communication interfaces .........................................................................................18
4.14.1 UART2 ...............................................................................................18
4.14.2 SPI .....................................................................................................19
4.14.3 I²C ......................................................................................................19
5 Pinout and pin description ...................................................................................21
5.1 STM8S105 pinouts and pin description .......................................................................22
5.1.1 Alternate function remapping ...............................................................28
6 Memory and register map .....................................................................................29
6.1 Memory map ................................................................................................................29
6.2 Register map ...............................................................................................................30
6.2.1 I/O port hardware register map ............................................................30
6.2.2 General hardware register map ...........................................................33
6.2.3 CPU/SWIM/debug module/interrupt controller registers ......................47
7 Interrupt vector mapping ......................................................................................50
8 Option bytes ...........................................................................................................52
9 Unique ID ................................................................................................................57
10 Electrical characteristics ....................................................................................58
10.1 Parameter conditions .................................................................................................58
10.1.1 Minimum and maximum values .........................................................58
10.1.2 Typical values .....................................................................................58
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10.1.3 Typical curves ....................................................................................58
10.1.4 Typical current consumption ..............................................................58
10.1.5 Loading capacitor ...............................................................................59
10.1.6 Pin input voltage .................................................................................59
10.2 Absolute maximum ratings ........................................................................................59
10.3 Operating conditions ..................................................................................................61
10.3.1 VCAP external capacitor ....................................................................64
10.3.2 Supply current characteristics ............................................................64
10.3.3 External clock sources and timing characteristics .............................76
10.3.4 Internal clock sources and timing characteristics ...............................78
10.3.5 Memory characteristics ......................................................................81
10.3.6 I/O port pin characteristics .................................................................82
10.3.7 Typical output level curves .................................................................86
10.3.8 Reset pin characteristics ....................................................................91
10.3.9 SPI serial peripheral interface ............................................................93
10.3.10 I2C interface characteristics .............................................................97
10.3.11 10-bit ADC characteristics ................................................................98
10.3.12 EMC characteristics .......................................................................102
11 Package characteristics ....................................................................................106
11.1 Ecopack packages ..................................................................................................106
11.2 Package mechanical data ........................................................................................106
11.2.1 48-pin LQFP package mechanical data ...........................................106
11.2.2 44-pin LQFP package mechanical data ...........................................108
11.2.3 32-pin LQFP package mechanical data ...........................................109
11.2.4 32-lead VFQFPN package mechanical data ....................................111
11.2.5 32-lead UFQFPN package mechanical data ....................................112
11.2.6 SDIP32 package mechanical data ...................................................114
11.3 Thermal characteristics ............................................................................................115
11.3.1 Reference document ........................................................................116
11.3.2 Selecting the product temperature range .........................................116
12 Ordering information .........................................................................................117
12.1 STM8S105 FASTROM microcontroller option list ...................................................117
13 STM8 development tools ..................................................................................122
13.1 Emulation and in-circuit debugging tools .................................................................122
13.2 Software tools ..........................................................................................................122
13.2.1 STM8 toolset ....................................................................................123
13.2.2 C and assembly toolchains ..............................................................123
13.3 Programming tools ..................................................................................................123
14 Revision history .................................................................................................124
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List of tables
STM8S105xx
List of tables
Table 1. Device summary .........................................................................................................................1
Table 2. STM8S105xx access line features .............................................................................................9
Table 3. Peripheral clock gating bit assignments in CLK_PCKENR1/2 registers ..................................15
Table 4. TIM timer features ...................................................................................................................17
Table 5. Legend/abbreviations ..............................................................................................................21
Table 6. Pin description for STM8S105 microcontrollers .......................................................................25
Table 7. Flash, Data EEPROM and RAM boundary addresses ..........................................................108
Table 8. I/O port hardware register map ..............................................................................................113
Table 9. General hardware register map ................................................................................................33
Table 10. CPU/SWIM/debug module/interrupt controller registers ......................................................114
Table 11. Interrupt mapping ....................................................................................................................50
Table 12. Option bytes ..........................................................................................................................57
Table 13. Option byte description ...........................................................................................................53
Table 14. Description of alternate function remapping bits [7:0] of OPT2 ..............................................55
Table 15. Unique ID registers (96 bits) ...................................................................................................57
Table 16. Voltage characteristics ...........................................................................................................59
Table 17. Current characteristics ...........................................................................................................60
Table 18. Thermal characteristics ..........................................................................................................61
Table 19. General operating conditions .................................................................................................62
Table 20. Operating conditions at power-up/power-down ......................................................................63
Table 21. Total current consumption with code execution in run mode at VDD = 5 V .............................64
Table 22. Total current consumption with code execution in run mode at VDD = 3.3 V ..........................76
Table 23. Total current consumption in wait mode at VDD = 5 V ............................................................67
Table 24. Total current consumption in wait mode at VDD = 3.3 V .........................................................68
Table 25. Total current consumption in active halt mode at VDD = 5 V ..................................................68
Table 26. Total current consumption in active halt mode at VDD = 3.3 V ...............................................69
Table 27. Total current consumption in halt mode at VDD = 5 V .............................................................70
Table 28. Total current consumption in halt mode at VDD = 3.3 V ..........................................................71
Table 29. Wakeup times .........................................................................................................................71
Table 30. Total current consumption and timing in forced reset state ..................................................104
Table 31. Peripheral current consumption .............................................................................................72
Table 32. HSE user external clock characteristics .................................................................................76
Table 33. HSE oscillator characteristics .................................................................................................77
Table 34. HSI oscillator characteristics ..................................................................................................78
Table 35. LSI oscillator characteristics ...................................................................................................80
Table 36. RAM and hardware registers ..................................................................................................81
Table 37. Flash program memory/data EEPROM memory ....................................................................81
Table 38. I/O static characteristics .........................................................................................................82
Table 39. Output driving current (standard ports) ..................................................................................84
Table 40. Output driving current (true open drain ports) ........................................................................85
Table 41. Output driving current (high sink ports) ..................................................................................85
Table 42. NRST pin characteristics ........................................................................................................91
Table 43. SPI characteristics ..................................................................................................................94
Table 44. I2C characteristics ..................................................................................................................97
Table 45. ADC characteristics ................................................................................................................98
Table 46. ADC accuracy with RAIN < 10 kΩ , VDDA= 5 V .......................................................................99
Table 47. ADC accuracy with RAIN < 10 kΩ RAIN, VDDA = 3.3 V ..........................................................100
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List of tables
Table 48. EMS data ..............................................................................................................................103
Table 49. EMI data ...............................................................................................................................103
Table 50. ESD absolute maximum ratings ...........................................................................................104
Table 51. Electrical sensitivities ...........................................................................................................104
Table 52. 48-pin low profile quad flat package mechanical data .........................................................106
Table 53. 44-pin low profile quad flat package mechanical data .........................................................108
Table 54. 32-pin low profile quad flat package mechanical data .........................................................124
Table 55. 32-lead very thin fine pitch quad flat no-lead package mechanical data ..............................113
Table 56. 32-lead ultra thin fine pitch quad flat no-lead package mechanical data .............................113
Table 57. 32-lead shrink plastic DIP (400 ml) package mechanical data ............................................114
Table 58. Thermal characteristics(1) ....................................................................................................115
Table 59. Document revision history ...................................................................................................124
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List of figures
STM8S105xx
List of figures
Figure 1. STM8S105xx access line block diagram ................................................................................11
Figure 2. Flash memory organisation ....................................................................................................14
Figure 3. LQFP 48-pin pinout .................................................................................................................22
Figure 4. LQFP 44-pin pinout .................................................................................................................23
Figure 5. LQFP/VFQFPN/UFQFPN 32-pin pinout ................................................................................24
Figure 6. SDIP 32-pin pinout ..................................................................................................................25
Figure 7. Memory map ...........................................................................................................................29
Figure 8. Supply current measurement conditions ................................................................................58
Figure 9. Pin loading conditions .............................................................................................................59
Figure 10. Pin input voltage ...................................................................................................................59
Figure 11. fCPUmax versus VDD ..............................................................................................................63
Figure 12. External capacitor CEXT .......................................................................................................64
Figure 13. Typ. IDD(RUN) vs. VDD , HSE user external clock, fCPU = 16 MHz ...........................................73
Figure 14. Typ. IDD(RUN) vs. fCPU , HSE user external clock, VDD= 5 V ..................................................74
Figure 15. Typ. IDD(RUN) vs. VDD , HSI RC osc, fCPU = 16 MHz ..............................................................74
Figure 16. Typ. IDD(WFI) vs. VDD , HSE user external clock, fCPU = 16 MHz ............................................75
Figure 17. Typ. IDD(WFI) vs. fCPU, HSE user external clock VDD = 5 V ....................................................75
Figure 18. Typ. IDD(WFI) vs. VDD, HSI RC osc, fCPU = 16 MHz ................................................................76
Figure 19. HSE external clocksource .....................................................................................................77
Figure 20. HSE oscillator circuit diagram ...............................................................................................78
Figure 21. Typical HSI accuracy at VDD = 5 V vs 5 temperatures ..........................................................79
Figure 22. Typical HSI accuracy vs VDD @ 4 temperatures ..................................................................80
Figure 23. Typical LSI accuracy vs VDD @ 4 temperatures ...................................................................81
Figure 24. Typical VIL and VIH vs VDD @ 4 temperatures ......................................................................83
Figure 25. Typical pull-up resistance vs VDD @ 4 temperatures ............................................................84
Figure 26. Typical pull-up current vs VDD @ 4 temperatures .................................................................84
Figure 27. Typ. VOL @ VDD = 5 V (standard ports) ................................................................................86
Figure 28. Typ. VOL @ VDD = 3.3 V (standard ports) .............................................................................87
Figure 29. Typ. VOL @ VDD = 5 V (true open drain ports) ......................................................................87
Figure 30. Typ. VOL @ VDD = 3.3 V (true open drain ports) ...................................................................88
Figure 31. Typ. VOL @ VDD = 5 V (high sink ports) ................................................................................88
Figure 32. Typ. VOL @ VDD = 3.3 V (high sink ports) .............................................................................89
Figure 33. Typ. VDD - VOH @ VDD = 5 V (standard ports) .......................................................................89
Figure 34. Typ. VDD - VOH @ VDD = 3.3 V (standard ports) ....................................................................90
Figure 35. Typ. VDD - VOH @ VDD = 5 V (high sink ports) ......................................................................90
Figure 36. Typ. VDD - VOH @ VDD = 3.3 V (high sink ports) ...................................................................91
Figure 37. Typical NRST VIL and VIH vs VDD @ 4 temperatures ...........................................................92
Figure 38. Typical NRST pull-up resistance vs VDD @ 4 temperatures .................................................92
Figure 39. Typical NRST pull-up current vs VDD @ 4 temperatures ......................................................93
Figure 40. Recommended reset pin protection ......................................................................................93
Figure 41. SPI timing diagram - slave mode and CPHA = 0 ..................................................................95
Figure 42. SPI timing diagram - slave mode and CPHA = 1(1) .............................................................96
Figure 43. SPI timing diagram - master mode(1) ...................................................................................96
Figure 44. Typical application with I2C bus and timing diagram (1) .......................................................98
Figure 45. ADC accuracy characteristics .............................................................................................101
Figure 46. Typical application with ADC ..............................................................................................102
Figure 47. 48-pin low profile quad flat package (7 x 7) ........................................................................106
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List of figures
Figure 48. 44-pin low profile quad flat package ...................................................................................108
Figure 49. 32-pin low profile quad flat package (7 x 7) ........................................................................109
Figure 50. 32-lead very thin fine pitch quad flat no-lead package (5 x 5) ............................................112
Figure 51. 32-lead ultra thin fine pitch quad flat no-lead package (5 x 5) ............................................112
Figure 52. 32-lead shrink plastic DIP (400 ml) package ......................................................................114
Figure 53. STM8S105xx access line ordering information scheme .....................................................117
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Introduction
STM8S105xx
1
Introduction
This datasheet contains the description of the device features, pinout, electrical characteristics,
mechanical data and ordering information.
For complete information on the STM8S microcontroller memory, registers and peripherals,
please refer to the STM8S microcontroller family reference manual (RM0016).
•
•
•
•
For information on programming, erasing and protection of the internal Flash memory
please refer to the STM8S Flash programming manual (PM0051).
For information on the debug and SWIM (single wire interface module) refer to the STM8
SWIM communication protocol and debug module user manual (UM0470).
For information on the STM8 core, please refer to the STM8 CPU programming manual
(PM0044).
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Description
2
Description
The STM8S105xx access line 8-bit microcontrollers offer from 16 to 32 Kbytes Flash program
memory, plus integrated true data EEPROM. They are referred to as medium-density devices
in the STM8S microcontroller family reference manual (RM0016).
All devices of the STM8S105xx access line provide the following benefits:
Reduced system cost
•
Integrated true data EEPROM for up to 300 k write/erase cycles
-
High system integration level with internal clock oscillators, watchdog and brown-out
reset.
-
Performance and robustness
•
16 MHz CPU clock frequency
-
Robust I/O, independent watchdogs with separate clock source
-
Clock security system
-
Short development cycles
•
Applications scalability across a common family product architecture with compatible
pinout, memory map and and modular peripherals.
-
-
Full documentation and a wide choice of development tools
Product longevity
•
Advanced core and peripherals made in a state-of-the art technology
-
A family of products for applications with 2.95 to 5.5 V operating supply
-
Table 2: STM8S105xx access line features
Device
STM8S105C6
STM8S105C4
STM8S105S6
STM8S105S4
STM8S105K6
STM8S105K4
Pin count
48
48
44
44
32
32
Maximum number 38
of GPIOs
38
34
34
25
25
Ext. Interrupt pins 35
35
9
31
8
31
8
23
8
23
8
Timer CAPCOM
channels
9
3
Timer
3
3
9
3
9
3
7
3
7
complementary
outputs
A/D Converter
channels
10
10
High sink I/Os
16
16
15
15
12
12
Medium density
Flash Program
memory (bytes)
32K
16K
32K
16K
32K
16K
Data EEPROM
(bytes)
1024
2K
1024
2K
1024
2K
1024
2K
1024
2K
1024
2K
RAM (bytes)
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Description
STM8S105xx
Device
STM8S105C6
STM8S105C4
STM8S105S6
STM8S105S4
STM8S105K6
STM8S105K4
2
Peripheral set
Advanced control timer (TIM1), General-purpose timers (TIM2 and TIM3), Basic timer (TIM4) SPI, I C, UART,
Window WDG, Independent WDG, ADC
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Block diagram
3
Block diagram
Figure 1: STM8S105xx access line block diagram
Reset block
Reset
XTAL 1-16 MHz
RC int. 16 MHz
RC int. 128 kHz
Clock controller
Detector
Reset
POR
BOR
Clock to peripherals and core
Window WDG
STM8 core
Independent WDG
Single wire
debug interf.
Debug/SWIM
Up to 32 Kbytes
program Flash
Master/slave
autosynchro
LIN master
SPI emul.
UART2
I2C
1 Kbytes
data EEPROM
Up to 2 Kbytes
RAM
400 Kbit/s
8 Mbit/s
Boot ROM
SPI
Up to
4 CAPCOM
channels +3
complementary
outputs
16-bit advanced control
timer (TIM1)
Up to
5 CAPCOM
channels
16-bit general purpose
timers (TIM2, TIM3)
Up to 10 channels
ADC1
8-bit basic timer
(TIM4)
1/2/4 kHz
beep
Beeper
AWU timer
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Product overview
STM8S105xx
4
Product overview
The following section intends to give an overview of the basic features of the device functional
modules and peripherals.
For more detailed information please refer to the corresponding family reference manual
(RM0016).
4.1
Central processing unit STM8
The 8-bit STM8 core is designed for code efficiency and performance.
It contains 6 internal registers which are directly addressable in each execution context, 20
addressing modes including indexed indirect and relative addressing and 80 instructions.
Architecture and registers
Harvard architecture
•
3-stage pipeline
•
32-bit wide program memory bus - single cycle fetching for most instructions
•
X and Y 16-bit index registers - enabling indexed addressing modes with or without offset
and read-modify-write type data manipulations
•
8-bit accumulator
•
24-bit program counter - 16-Mbyte linear memory space
•
16-bit stack pointer - access to a 64 K-level stack
•
8-bit condition code register - 7 condition flags for the result of the last instruction
•
Addressing
20 addressing modes
•
Indexed indirect addressing mode for look-up tables located anywhere in the address
space
•
Stack pointer relative addressing mode for local variables and parameter passing
•
Instruction set
80 instructions with 2-byte average instruction size
•
Standard data movement and logic/arithmetic functions
•
8-bit by 8-bit multiplication
•
16-bit by 8-bit and 16-bit by 16-bit division
•
Bit manipulation
•
Data transfer between stack and accumulator (push/pop) with direct stack access
•
Data transfer using the X and Y registers or direct memory-to-memory transfers
•
4.2
Single wire interface module (SWIM) and debug module (DM)
The single wire interface module and debug module permits non-intrusive, real-time in-circuit
debugging and fast memory programming.
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SWIM
Product overview
Single wire interface module for direct access to the debug module and memory programming.
The interface can be activated in all device operation modes. The maximum data transmission
speed is 145 bytes/ms.
Debug module
The non-intrusive debugging module features a performance close to a full-featured emulator.
Beside memory and peripherals, also CPU operation can be monitored in real-time by means
of shadow registers.
R/W to RAM and peripheral registers in real-time
•
R/W access to all resources by stalling the CPU
•
Breakpoints on all program-memory instructions (software breakpoints)
•
Two advanced breakpoints, 23 predefined configurations
•
4.3
4.4
Interrupt controller
Nested interrupts with three software priority levels
•
32 interrupt vectors with hardware priority
•
Up to 27 external interrupts on 6 vectors including TLI
•
Trap and reset interrupts
•
Flash program and data EEPROM memory
Up to 32 Kbytes of Flash program single voltage Flash memory
•
Up to 1 Kbytes true data EEPROM
•
Read while write: Writing in data memory possible while executing code in program memory
•
User option byte area
•
Write protection (WP)
Write protection of Flash program memory and data EEPROM is provided to avoid unintentional
overwriting of memory that could result from a user software malfunction.
There are two levels of write protection. The first level is known as MASS (memory access
security system). MASS is always enabled and protects the main Flash program memory,
data EEPROM and option bytes.
To perform in-application programming (IAP), this write protection can be removed by writing
a MASS key sequence in a control register. This allows the application to write to data
EEPROM, modify the contents of main program memory or the device option bytes.
A second level of write protection, can be enabled to further protect a specific area of memory
known as UBC (user boot code). Refer to the figure below.
The size of the UBC is programmable through the UBC option byte, in increments of 1 page
(512 bytes) by programming the UBC option byte in ICP mode.
This divides the program memory into two areas:
Main program memory: Up to 32 Kbytes minus UBC
•
User-specific boot code (UBC): Configurable up to 32 Kbytes
•
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Product overview
STM8S105xx
The UBC area remains write-protected during in-application programming. This means that
the MASS keys do not unlock the UBC area. It protects the memory used to store the boot
program, specific code libraries, reset and interrupt vectors, the reset routine and usually the
IAP and communication routines.
Figure 2: Flash memory organisation
Data memory area ( 1 Kbyte)
Option bytes
Data
EEPROM
memory
Programmable area
from 1 Kbyte
(2 first pages) up to
UBC area
Remains write protected during IAP
32 Kbytes
(1 page steps)
Medium density
Flash program memory
(up to 32 Kbytes)
Program memory area
Write access possible for IAP
Read-out protection (ROP)
The read-out protection blocks reading and writing the Flash program memory and data
EEPROM memory in ICP mode (and debug mode). Once the read-out protection is activated,
any attempt to toggle its status triggers a global erase of the program and data memory. Even
if no protection can be considered as totally unbreakable, the feature provides a very high
level of protection for a general purpose microcontroller.
4.5
Clock controller
The clock controller distributes the system clock (fMASTER) coming from different oscillators
to the core and the peripherals. It also manages clock gating for low power modes and ensures
clock robustness.
Features
Clock prescaler: To get the best compromise between speed and current consumption
the clock frequency to the CPU and peripherals can be adjusted by a programmable
prescaler.
•
Safe clock switching: Clock sources can be changed safely on the fly in run mode
through a configuration register. The clock signal is not switched until the new clock source
is ready. The design guarantees glitch-free switching.
•
Clock management: To reduce power consumption, the clock controller can stop the
clock to the core, individual peripherals or memory.
•
•
Master clock sources: Four different clock sources can be used to drive the master
clock:
1-16 MHz high-speed external crystal (HSE)
-
Up to 16 MHz high-speed user-external clock (HSE user-ext)
-
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Product overview
16 MHz high-speed internal RC oscillator (HSI)
128 kHz low-speed internal RC (LSI)
-
-
Startup clock: After reset, the microcontroller restarts by default with an internal 2 MHz
clock (HSI/8). The prescaler ratio and clock source can be changed by the application
program as soon as the code execution starts.
•
Clock security system (CSS): This feature can be enabled by software. If an HSE clock
failure occurs, the internal RC (16 MHz/8) is automatically selected by the CSS and an
interrupt can optionally be generated.
•
•
Configurable main clock output (CCO): This outputs an external clock for use by the
application.
Table 3: Peripheral clock gating bit assignments in CLK_PCKENR1/2 registers
Bit
Peripheral Bit
clock
Peripheral Bit
clock
Peripheral Bit
clock
Peripheral
clock
PCKEN1 7 TIM1
PCKEN1 6 TIM3
PCKEN1 5 TIM2
PCKEN1 4 TIM4
PCKEN1 3 UART2
PCKEN2 7 Reserved PCKEN2 3 ADC
PCKEN1 2 Reserved PCKEN2 6 Reserved PCKEN2 2 AWU
PCKEN1 1 SPI
PCKEN1 0 I2C
PCKEN2 5 Reserved PCKEN2 1 Reserved
PCKEN2 4 Reserved PCKEN2 0 Reserved
4.6
Power management
For efficent power management, the application can be put in one of four different low-power
modes. You can configure each mode to obtain the best compromise between lowest power
consumption, fastest start-up time and available wakeup sources.
Wait mode: In this mode, the CPU is stopped, but peripherals are kept running. The
wakeup is performed by an internal or external interrupt or reset.
•
•
Active halt mode with regulator on: In this mode, the CPU and peripheral clocks are
stopped. An internal wakeup is generated at programmable intervals by the auto wake up
unit (AWU). The main voltage regulator is kept powered on, so current consumption is
higher than in active halt mode with regulator off, but the wakeup time is faster. Wakeup
is triggered by the internal AWU interrupt, external interrupt or reset.
Active halt mode with regulator off: This mode is the same as active halt with regulator
on, except that the main voltage regulator is powered off, so the wake up time is slower.
•
•
Halt mode: In this mode the microcontroller uses the least power. The CPU and peripheral
clocks are stopped, the main voltage regulator is powered off. Wakeup is triggered by
external event or reset.
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Product overview
STM8S105xx
4.7
Watchdog timers
The watchdog system is based on two independent timers providing maximum security to
the applications.
Activation of the watchdog timers is controlled by option bytes or by software. Once activated,
the watchdogs cannot be disabled by the user program without performing a reset.
Window watchdog timer
The window watchdog is used to detect the occurrence of a software fault, usually generated
by external interferences or by unexpected logical conditions, which cause the application
program to abandon its normal sequence.
The window function can be used to trim the watchdog behavior to match the application
perfectly.
The application software must refresh the counter before time-out and during a limited time
window.
A reset is generated in two situations:
1. Timeout: At 16 MHz CPU clock the time-out period can be adjusted between 75 µs up to
64 ms.
2. Refresh out of window: The downcounter is refreshed before its value is lower than the
one stored in the window register.
Independent watchdog timer
The independent watchdog peripheral can be used to resolve processor malfunctions due to
hardware or software failures.
It is clocked by the 128 kHZ LSI internal RC clock source, and thus stays active even in case
of a CPU clock failure
The IWDG time base spans from 60 µs to 1 s.
4.8
4.9
Auto wakeup counter
Used for auto wakeup from active halt mode
•
Clock source: Internal 128 kHz internal low frequency RC oscillator or external clock
•
LSI clock can be internally connected to TIM3 input capture channel 1 for calibration
•
Beeper
The beeper function outputs a signal on the BEEP pin for sound generation. The signal is in
the range of 1, 2 or 4 kHz.
The beeper output port is only available through the alternate function remap option bit AFR7.
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STM8S105xx
Product overview
4.10
TIM1 - 16-bit advanced control timer
This is a high-end timer designed for a wide range of control applications. With its
complementary outputs, dead-time control and center-aligned PWM capability, the field of
applications is extended to motor control, lighting and half-bridge driver
16-bit up, down and up/down autoreload counter with 16-bit prescaler
•
Four independent capture/compare channels (CAPCOM) configurable as input capture,
output compare, PWM generation (edge and center aligned mode) and single pulse mode
output
•
Synchronization module to control the timer with external signals
•
Break input to force the timer outputs into a defined state
•
Three complementary outputs with adjustable dead time
•
Encoder mode
•
Interrupt sources: 3 x input capture/output compare, 1 x overflow/update, 1 x break
•
4.11
4.12
TIM2, TIM3 - 16-bit general purpose timers
16-bit autoreload (AR) up-counter
•
15-bit prescaler adjustable to fixed power of 2 ratios 1…32768
•
Timers with 3 or 2 individually configurable capture/compare channels
•
PWM mode
•
Interrupt sources: 2 or 3 x input capture/output compare, 1 x overflow/update
•
TIM4 - 8-bit basic timer
8-bit autoreload, adjustable prescaler ratio to any power of 2 from 1 to 128
•
Clock source: CPU clock
•
Interrupt source: 1 x overflow/update
•
Table 4: TIM timer features
Timer Counter Prescaler
Counting CAPCOM Complem. Ext.
Timer
size
(bits)
mode
channels outputs trigger synchronization/
chaining
TIM1 16
TIM2 16
TIM3 16
Any integer from 1 to Up/
4
3
2
3
0
0
Yes
No
No
No
65536
down
Any power of 2 from Up
1 to 32768
Any power of 2 from Up
1 to 32768
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Product overview
STM8S105xx
Timer Counter Prescaler
Counting CAPCOM Complem. Ext.
Timer
size
(bits)
mode
channels outputs trigger synchronization/
chaining
TIM4
8
Any power of 2 from Up
1 to 128
0
0
No
4.13
Analog-to-digital converter (ADC1)
The STM8 family products contain a 10-bit successive approximation A/D converter (ADC1)
with up to 5 external multiplexed input channels and the following main features:
Input voltage range: 0 to VDD
•
Conversion time: 14 clock cycles
•
Single and continuous and buffered continuous conversion modes
•
Buffer size (n x 10 bits) where n = number of input channels
•
Scan mode for single and continuous conversion of a sequence of channels
•
Analog watchdog capability with programmable upper and lower thresholds
•
Analog watchdog interrupt
•
External trigger input
•
Trigger from TIM1 TRGO
•
End of conversion (EOC) interrupt
•
4.14
Communication interfaces
The following communication interfaces are implemented:
UART2: Full feature UART, synchronous mode, SPI master mode, Smartcard mode, IrDA
mode, LIN2.1 master/slave capability
•
SPI : Full and half-duplex, 8 Mbit/s
•
I²C: Up to 400 Kbit/s
•
4.14.1
UART2
Main features
One Mbit/s full duplex SCI
•
SPI emulation
•
High precision baud rate generator
•
Smartcard emulation
•
IrDA SIR encoder decoder
•
LIN master mode
•
LIN slave mode
•
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STM8S105xx
Product overview
Asynchronous communication (UART mode)
Full duplex communication - NRZ standard format (mark/space)
•
Programmable transmit and receive baud rates up to 1 Mbit/s (fCPU/16) and capable of
following any standard baud rate regardless of the input frequency
•
Separate enable bits for transmitter and receiver
Two receiver wakeup modes:
•
•
Address bit (MSB)
-
Idle line (interrupt)
-
Transmission error detection with interrupt generation
Parity control
•
•
Synchronous communication
Full duplex synchronous transfers
•
SPI master operation
•
8-bit data communication
•
Maximum speed: 1 Mbit/s at 16 MHz (fCPU/16)
•
LIN master mode
Emission: Generates 13-bit synch break frame
•
Reception: Detects 11-bit break frame
•
LIN slave mode
Autonomous header handling - one single interrupt per valid message header
•
Automatic baud rate synchronization - maximum tolerated initial clock deviation ±15 %
•
Synch delimiter checking
•
11-bit LIN synch break detection - break detection always active
•
Parity check on the LIN identifier field
•
LIN error management
•
Hot plugging support
•
4.14.2
SPI
Maximum speed: 8 Mbit/s (fMASTER/2) both for master and slave
•
Full duplex synchronous transfers
•
Simplex synchronous transfers on two lines with a possible bidirectional data line
•
Master or slave operation - selectable by hardware or software
•
CRC calculation
•
1 byte Tx and Rx buffer
•
Slave/master selection input pin
•
4.14.3
I²C
I²C master features:
•
Clock generation
-
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Product overview
STM8S105xx
Start and stop generation
-
I²C slave features:
•
Programmable I2C address detection
-
Stop bit detection
-
Generation and detection of 7-bit/10-bit addressing and general call
Supports different communication speeds:
•
•
Standard speed (up to 100 kHz)
-
Fast speed (up to 400 kHz)
-
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STM8S105xx
Pinout and pin description
5
Pinout and pin description
Table 5: Legend/abbreviations
Type
I= Input, O = Output, S = Power supply
CM = CMOS
Level
Input
Output
HS = High sink
Output speed
O1 = Slow (up to 2 MHz)
O2 = Fast (up to 10 MHz)
O3 = Fast/slow programmability with slow as default state after reset
O4 = Fast/slow programmability with fast as default state after reset
Port and control
configuration
Input
float = floating, wpu = weak pull-up
Output
T = True open drain, OD = Open drain, PP =
Push pull
Reset state
Bold X
HS
(T)
High sink capability.
True open drain (P-buffer and protection diode to VDD not
implemented
[]
Alternate function remapping option
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Pinout and pin description
STM8S105xx
5.1
STM8S105 pinouts and pin description
Figure 3: LQFP 48-pin pinout
48 47 46 45 44 43 42 41 40 39 38 37
36
1
2
3
4
5
6
7
8
9
10
NRST
OSCIN/PA1
PG1
35
34
33
32
31
30
29
28
27
26
25
PG0
OSCOUT/PA2
PC7 (HS)/SPI_MISO
PC6 (HS)/SPI_MOSI
V
SSIO_1
V
SS
V
DDIO_2
VCAP
V
SSIO_2
V
PC5 (HS)/SPI_SCK
PC4 (HS)/TIM1_CH4
PC3 (HS)/TIM1_CH3
PC2 (HS)/TIM1_CH2
DD
V
DDIO_1
[TIM3_CH1] TIM2_CH3/PA3
(HS) PA4
11
12
(HS) PA5
PC1 (HS)/TIM1_CH1/UART2_CK
PE5/SPI_NSS
(HS) PA6
24
13 14 15 16 17 18 19 20 21 22 23
1. (HS) high sink capability.
2. (T) True open drain (P-buffer and protection diode to VDD not implemented).
3. [ ] alternate function remapping option (If the same alternate function is shown twice, it
indicates an exclusive choice not a duplication of the function).
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Pinout and pin description
Figure 4: LQFP 44-pin pinout
44 43 42 41 40 39 38 37 36 35 34
1
33
32
31
30
29
28
27
26
25
24
23
NRST
OSCIN/PA1
PG1
PG0
2
3
OSCOUT/PA2
PC7 (HS)/SPI_MISO
PC6 (HS)/SPI_MOSI
4
V
SSIO_1
5
V
SS
V
DDIO_2
6
VCAP
V
SSIO_2
7
V
DD
PC5 (HS)/SPI_SCK
8
V
PC3 (HS)/TIM1_CH3
PC2 (HS)/TIM1_CH2
PC1 (HS)/TIM1_CH1/UART2_CK
PE5/SPI_NSS
DDIO_1
9
(HS) PA4
(HS) PA5
(HS) PA6
10
11
12 13 14 15 16 17 18 19 20 21 22
1. (HS) high sink capability.
2. (T) True open drain (P-buffer and protection diode to VDD not implemented).
3. [ ] alternate function remapping option (If the same alternate function is shown twice, it
indicates an exclusive choice not a duplication of the function).
DocID14771 Rev 9
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Pinout and pin description
STM8S105xx
Figure 5: LQFP/VFQFPN/UFQFPN 32-pin pinout
32 31 30 29 28 27 26 25
24
23
22
21
20
19
18
17
1
2
3
4
5
6
7
8
NRST
OSCIN/PA1
PC7 (HS)/SPI_MISO
PC6 (HS)/SPI_MOSI
PC5 (HS)/SPI_SCK
OSCOUT/PA2
V
PC4 (HS)/TIM1_CH4
PC3 (HS)/TIM1_CH3
PC2 (HS)/TIM1_CH2
PC1 (HS)/TIM1_CH1/UART2_CK
PE5/SPI_NSS
SS
VCAP
V
DD
V
DDIO
AIN12/PF4
9
10 11 12 13 14 15 16
1. (HS) high sink capability.
2. [ ] alternate function remapping option (If the same alternate function is shown twice, it
indicates an exclusive choice not a duplication of the function).
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STM8S105xx
Pinout and pin description
Figure 6: SDIP 32-pin pinout
ADC_ETR/TIM2_CH2/PD3(HS)
[BEEP]TIM2_CH1/PD4(HS)
1
2
3
4
5
6
7
8
9
32
PD2(HS)/TIM3_CH1[TIM2_CH3]
31 PD1(HS)/SWIM
30
UART2_TX/PD5
UART2_RX/PD6
PD0(HS)/TIM3_CH2[TIM1_BKIN][CLK_CCO]
29 PC7(HS)/SPI_MISO
(TIM1_CH4)TLI/PD7
28
PC6(HS)/SPI_MOSI
NRST
27 PC5(HS)/SPI_SCK
OSCIN/PA1
26
PC4(HS)/TIM1_CH4
OSCOUT/PA2
25 PC3(HS)/TIM1_CH3
V
24
PC2(HS)/TIM1_CH2
SS
VCAP 10
23 PC1(HS)/TIM1_CH1/UART2_CK
V
11
12
13
14
15
22
PE5/SPI_NSS
DD
DDIO
V
21 PB0/AIN0[TIM1_CH1N]
AIN12/PF4
20
PB1/AIN1[TIM1_CH2N]
V
19 PB2/AIN2[TIM1_CH3N]
DDA
V
18
PB3/AIN3[TIM1_ETR]
SSA
[I2C_SDA]AIN5/PB5 16
17 PB4/AIN4[I2C_SCL]
105_ai15057
1. (HS) high sink capability.
2. (T) True open drain (P-buffer and protection diode to VDD not implemented).
3. [ ] alternate function remapping option (If the same alternate function is shown twice, it
indicates an exclusive choice not a duplication of the function).
Table 6: Pin description for STM8S105 microcontrollers
Pin number
Pin
name
Type Input
Output
Main function Default alternate
Alternate
function after
remap
(after reset)
function
LQFP48 LQFP44 LQFP32/ SDIP32
floating wpu Ext.
High Speed OD
interrupt sink
PP
[option bit]
VFQFPN32/
UFQFPN32
1
2
1
2
1
2
6
7
NRST
I/O
I/O
X
Reset
PA1/
OSC
IN
X
X
X
O1
O1
X
X
X
X
Port A1
Resonator/
crystal in
3
3
3
8
PA2/
OSC
OUT
I/O
X
X
Port A2
Resonator/
crystal out
4
5
6
7
8
4
5
6
7
8
-
-
V
S
S
S
S
S
I/O ground
SSIO_1
4
5
6
7
9
V
Digital ground
SS
10
11
12
VCAP
1.8 V regulator capacitor
Digital power supply
I/O power supply
V
DD
V
DDIO_1
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Pinout and pin description
STM8S105xx
Pin number
Pin
name
Type Input
Output
Main function Default alternate
Alternate
function after
remap
(after reset)
function
LQFP48 LQFP44 LQFP32/ SDIP32
floating wpu Ext.
High Speed OD
interrupt sink
PP
[option bit]
VFQFPN32/
UFQFPN32
9
-
-
-
PA3/
I/O
X
X
X
O1
X
X
Port A3
Timer 2 -
channel 3
TIM3_ CH1
[AFR1]
TIM2
_CH3
[TIM3
_CH1]
10
11
12
-
9
-
-
PA4
PA5
PA6
I/O
I/O
I/O
I/O
X
X
X
X
X
X
X
X
X
HS
HS
HS
O3
O3
O3
O1
X
X
X
X
X
X
X
X
Port A4
Port A5
Port A6
Port F4
10
11
-
-
-
X
X
-
-
(1)
8
13
PF4/
Analog input 12
AIN12
13
14
15
12
13
14
9
14
15
-
V
V
S
Analog power supply
Analog ground
DDA
10
-
S
SSA
PB7/
AIN7
I/O
X
X
X
X
X
X
X
X
X
O1
O1
O1
X
X
X
X
X
X
Port B7
Port B6
Port B5
Analog input 7
16
17
15
16
-
-
PB6/
AIN6
I/O
I/O
Analog input 6
Analog input 5
2
11
16
PB5/
AIN5
I
C_SDA
[AFR6]
2
[I C_
SDA]
2
C_SCL
[AFR6]
18
19
20
21
22
23
17
18
19
20
21
-
12
13
14
15
16
-
17
18
19
20
21
-
PB4/
AIN4
[I C_
I/O
I/O
I/O
I/O
I/O
I/O
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
O1
O1
O1
O1
O1
O1
X
X
X
X
X
X
X
X
X
X
X
X
Port B4
Port B3
Port B2
Port B1
Port B0
Port E7
Analog input 4
Analog input 3
Analog input 2
Analog input 1
Analog input 0
Analog input 8
I
2
SCL]
PB3/
TIM1_ ETR
[AFR5]
AIN3
[TIM1_
ETR]
PB2/
AIN2
[TIM1_
CH3N]
TIM1_ CH3N
[AFR5]
PB1/
AIN1
[TIM1_
CH2N]
TIM1_ CH2N
[AFR5]
PB0/
AIN0
[TIM1_
CH1N]
TIM1_ CH1N
[AFR5]
PE7/
AIN8
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STM8S105xx
Pinout and pin description
Pin number
Pin
name
Type Input
Output
Main function Default alternate
Alternate
function after
remap
(after reset)
function
LQFP48 LQFP44 LQFP32/ SDIP32
floating wpu Ext.
High Speed OD
interrupt sink
PP
[option bit]
VFQFPN32/
UFQFPN32
(2)
24
25
26
22
23
24
-
-
PE6/
AIN9
I/O
X
X
X
X
X
X
X
O1
O1
O3
X
X
X
X
X
X
Port E6
Port E5
Port C1
Analog input 9
17
18
22
23
PE5/SPI_ I/O
NSS
X
X
SPI master/slave
select
PC1/
I/O
HS
Timer 1 -
TIM1_
CH1/
UART2_CK
channel 1/ UART2
synchronous clock
27
28
29
30
25
26
-
19
20
21
22
24
25
26
27
PC2/
TIM1_
CH2
I/O
I/O
I/O
I/O
X
X
X
X
X
X
X
X
X
X
X
X
HS
HS
HS
HS
O3
O3
O3
O3
X
X
X
X
X
X
X
X
Port C2
Port C3
Port C4
Port C5
Timer 1-
channel 2
PC3/
TIM1_
CH3
Timer 1 -
channel 3
PC4/
TIM1_
CH4
Timer 1 -
channel 4
27
PC5/
SPI_
SCK
SPI clock
31
32
33
28
29
30
-
-
V
S
I/O ground
SSIO_2
-
-
V
S
I/O power supply
Port C6
DDIO_2
23
28
PC6/
SPI_
MOSI
I/O
X
X
X
X
X
X
HS
HS
O3
O3
X
X
X
X
SPI master
out/slave in
34
31
24
29
PC7/
SPI_
MISO
I/O
Port C7
SPI master in/
slave out
35
36
37
32
33
-
-
-
-
-
-
-
PG0
PG1
I/O
I/O
I/O
X
X
X
X
X
X
O1
O1
O1
X
X
X
X
X
X
Port G0
Port G1
Port E3
PE3/
TIM1_
BKIN
X
X
X
X
Timer 1 - break
input
(3)
2
38
39
40
34
35
36
-
-
-
-
-
-
PE2/
2
I/O
I/O
I/O
X
X
X
X
X
X
O1
O1
O3
T
Port E2
Port E1
Port E0
I
C data
I
C_
SDA
(3)
2
PE1/
2
T
I
C clock
I
C_
SCL
PE0/
CLK_
CCO
HS
X
X
Configurable clock
output
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Pinout and pin description
STM8S105xx
Pin number
Pin
name
Type Input
Output
Main function Default alternate
Alternate
function after
remap
(after reset)
function
LQFP48 LQFP44 LQFP32/ SDIP32
floating wpu Ext.
High Speed OD
interrupt sink
PP
[option bit]
VFQFPN32/
UFQFPN32
41
37
25
30
PD0/
TIM3_
CH2
[TIM1_
BKIN]
[CLK_
CCO]
I/O
X
X
X
HS
O3
X
X
Port D0
Timer 3 -
channel 2
TIM1_ BKIN
[AFR3]/
CLK_ CCO
[AFR2]
42
43
38
39
26
27
31
32
PD1/
SWIM
I/O
I/O
X
X
X
X
X
HS
O4
O3
X
X
X
X
Port D1
Port D2
SWIM data
interface
PD2/
TIM3_
CH1
[TIM2_
CH3]
X
X
X
HS
HS
HS
Timer 3 -
channel 1
TIM2_CH3
[AFR1]
44
45
40
41
28
29
1
2
PD3/
TIM2_
CH2
[ADC_
ETR]
I/O
I/O
X
X
X
X
O3
O3
X
X
X
X
Port D3
Port D4
Timer 2 -
channel 2
ADC_ ETR
[AFR0]
PD4/
TIM2_
CH1
Timer 2 -
channel 1
BEEP output
[AFR7]
[BEEP]
46
47
48
42
43
44
30
31
32
3
4
5
PD5/
UART2_
TX
I/O
I/O
I/O
X
X
X
X
X
X
X
X
X
O1
O1
O1
X
X
X
X
X
X
Port D5
Port D6
Port D7
UART2 data
transmit
PD6/
UART2_
RX
UART2 data
receive
PD7/
TLI
Top level interrupt
TIM1_ CH4
[AFR4]
[TIM1_
CH4]
(1)
(2)
(3)
AIN12 is not selectable in ADC scan mode or with analog watchdog.
In 44-pin package, AIN9 cannot be used by ADC scan mode.
In the open-drain output column, ‘T’ defines a true open-drain I/O (P-buffer and protection diode to V
are not implemented).
DD
5.1.1
Alternate function remapping
As shown in the rightmost column of the pin description table, some alternate functions can
be remapped at different I/O ports by programming one of eight AFR (alternate function
remap) option bits. When the remapping option is active, the default alternate function is no
longer available.
To use an alternate function, the corresponding peripheral must be enabled in the peripheral
registers.
Alternate function remapping does not effect GPIO capabilities of the I/O ports (see the GPIO
section of the family reference manual, RM0016).
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Memory and register map
6
Memory and register map
6.1
Memory map
Figure 7: Memory map
0x00 0000
RAM
(2 Kbytes)
512 bytes stack
Reserved
0x00 07FF
0x00 4000
1 Kbyte data EEPROM
Reserved
0x00 43FF
0x00 4400
0x00 47FF
0x00 4800
Option bytes
Reserved
0x00 487F
0x00 4900
0x00 4FFF
0x00 5000
GPIO and periph. reg.
Reserved
0x00 57FF
0x00 5800
0x00 5FFF
0x00 6000
2 Kbytes boot ROM
0x00 67FF
0x00 6800
Reserved
0x00 7EFF
0x00 7F00
CPU/SWIM/debug/ITC
registers
0x00 7FFF
0x00 8000
32 interrupt vectors
0x00 807F
Flash program memory
(16 to 32 Kbytes)
0x00 FFFF
0x01 0000
Reserved
0x02 7FFF
The following table lists the boundary addresses for each memory size. The top of the stack
is at the RAM end address in each case.
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Memory and register map
Memory area
STM8S105xx
Table 7: Flash, Data EEPROM and RAM boundary addresses
Size (bytes)
Start address
End address
Flash program memory 32K
0x00 8000
0x00 FFFF
0x00 BFFF
0x00 07FF
0x00 43FF
16K
2K
0x00 8000
0x00 0000
0x00 4000
RAM
Data EEPROM
1024
6.2
Register map
6.2.1
I/O port hardware register map
Table 8: I/O port hardware register map
Register label Register name
Address
Block
Reset
status
0x00 5000 Port A
0x00 5001
PA_ODR
PA_IDR
PA_DDR
PA_CR1
PA_CR2
PB_ODR
PB_IDR
PB_DDR
PB_CR1
PB_CR2
Port A data output latch register
Port A input pin value register
Port A data direction register
Port A control register 1
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00 5002
0x00 5003
0x00 5004
Port A control register 2
0x00 5005 Port B
0x00 5006
Port B data output latch register
Port B input pin value register
Port B data direction register
Port B control register 1
0x00 5007
0x00 5008
0x00 5009
Port B control register 2
30/127
DocID14771 Rev 9
STM8S105xx
Memory and register map
Address
Block
Register label Register name
Reset
status
0x00 500A Port C
0x00 500B
PC_ODR
Port C data output latch register
Port C input pin value register
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x02
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
PB_IDR
PC_DDR
PC_CR1
PC_CR2
PD_ODR
PD_IDR
PD_DDR
PD_CR1
PD_CR2
PE_ODR
PE_IDR
PE_DDR
PE_CR1
PE_CR2
PF_ODR
PF_IDR
0x00 500C
Port C data direction register
Port C control register 1
0x00 500D
0x00 500E
Port C control register 2
0x00 500F Port D
0x00 5010
Port D data output latch register
Port D input pin value register
Port D data direction register
Port D control register 1
0x00 5011
0x00 5012
0x00 5013
Port D control register 2
0x00 5014 Port E
0x00 5015
Port E data output latch register
Port E input pin value register
Port E data direction register
Port E control register 1
0x00 5016
0x00 5017
0x00 5018
Port E control register 2
0x00 5019 Port F
0x00 501A
Port F data output latch register
Port F input pin value register
Port F data direction register
Port F control register 1
0x00 501B
PF_DDR
PF_CR1
0x00 501C
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Memory and register map
STM8S105xx
Address
Block
Register label Register name
Reset
status
0x00 501D
PF_CR2
PG_ODR
PG_IDR
PG_DDR
PG_CR1
PG_CR2
PH_ODR
PH_IDR
PH_DDR
PH_CR1
PH_CR2
PI_ODR
PI_IDR
Port F control register 2
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00 501E Port G
0x00 501F
Port G data output latch register
Port G input pin value register
Port G data direction register
Port G control register 1
0x00 5020
0x00 5021
0x00 5022
Port G control register 2
0x00 5023 Port H
0x00 5024
Port H data output latch register
Port H input pin value register
Port H data direction register
Port H control register 1
0x00 5025
0x00 5026
0x00 5027
Port H control register 2
0x00 5028 Port I
0x00 5029
Port I data output latch register
Port I input pin value register
Port I data direction register
Port I control register 1
0x00 502A
PI_DDR
PI_CR1
PI_CR2
0x00 502B
0x00 502C
Port I control register 2
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STM8S105xx
Memory and register map
6.2.2
General hardware register map
Table 9: General hardware register map
Address Block
Register label
Register name
Reset
status
0x00
Reserved area (10 bytes)
5050 to
0x00
5059
FLASH_CR1
FLASH_CR2
FLASH_NCR2
Flash control register 1
Flash control register 2
0x00
0x00
0xFF
0x00
505A
Flash
0x00
505B
0x00
505C
Flash complementary control
register 2
0x00
505D
FLASH _FPR
Flash protection register
0x00
0xFF
0x00
0x00
505E
FLASH _NFPR
Flash complementary protection
register
0x00
505F
FLASH _IAPSR Flash in-application programming
status register
0x00
Reserved area (2 bytes)
5060 to
0x00
5061
0x00
5062
Flash
FLASH _PUKR
Flash program memory unprotection 0x00
register
0x00
5063
Reserved area (1 byte)
0x00
5064
Flash
FLASH _DUKR Data EEPROM unprotection register 0x00
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Memory and register map
Address Block
STM8S105xx
Register label
Register name
Reset
status
0x00
Reserved area (59 bytes)
5065 to
0x00
509F
0x00
50A0
ITC -
EXTI
EXTI_CR1
EXTI_CR2
External interrupt control register 1
External interrupt control register 2
0x00
0x00
0x00
50A1
0x00
Reserved area (17 bytes)
50A2 to
0x00
50B2
0x00
50B3
RST
RST_SR
Reset status register
xx
0x00
Reserved area (12 bytes)
50B4 to
0x00
50BF
0x00
50C0
CLK
CLK_ICKR
CLK_ECKR
Internal clock control register
External clock control register
0x01
0x00
0x00
50C1
0x00
Reserved area (1 byte)
50C2
0x00
50C3
CLK
CLK_CMSR
CLK_SWR
CLK_SWCR
Clock master status register
Clock master switch register
Clock switch control register
0xE1
0xE1
0x00
50C4
0x00
50C5
0bxxxx
0000
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DocID14771 Rev 9
STM8S105xx
Memory and register map
Address Block
Register label
Register name
Reset
status
0x00
CLK_CKDIVR
Clock divider register
0x18
50C6
0x00
50C7
CLK_PCKENR1 Peripheral clock gating register 1
0xFF
0x00
0x00
0xFF
0x00
0x00
50C8
CLK_CSSR
CLK_CCOR
Clock security system register
0x00
50C9
Configurable clock control register
0x00
50CA
CLK_PCKENR2 Peripheral clock gating register 2
0x00
CLK_CANCCR
CAN clock control register
50CB
0x00
CLK_HSITRIMR HSI clock calibration trimming register xx
50CC
0x00
CLK_SWIMCCR SWIM clock control register
x0
50CD
0x00
Reserved area (3 bytes)
50CE to
0x00
50D0
0x00
50D1
WWDG WWDG_CR
WWDG control register
WWDR window register
0x7F
0x7F
0x00
WWDG_WR
50D2
0x00
Reserved area (13 bytes)
50D3 to
0x00
50DF
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Memory and register map
Address Block
STM8S105xx
Register label
Register name
Reset
status
0x00
50E0
IWDG
IWDG_KR
IWDG key register
-
0x00
50E1
IWDG_PR
IWDG prescaler register
IWDG reload register
0x00
0xFF
0x00
50E2
IWDG_RLR
0x00
Reserved area (13 bytes)
50E3 to
0x00
50EF
0x00
50F0
AWU
AWU_CSR1
AWU_APR
AWU_TBR
BEEP_CSR
AWU control/ status register 1
0x00
0x00
50F1
AWU asynchronous prescaler buffer 0x3F
register
0x00
50F2
AWU timebase selection register
BEEP control/ status register
0x00
0x1F
0x00
50F3
BEEP
0x00
Reserved area (12 bytes)
50F4 to
0x00
50FF
00 5200h SPI
00 5201h
SPI_CR1
SPI_CR2
SPI_ICR
SPI_SR
SPI_DR
SPI control register 1
SPI control register 2
SPI interrupt control register
SPI status register
0x00
0x00
0x00
0x02
0x00
00 5202h
00 5203h
00 5204h
SPI data register
36/127
DocID14771 Rev 9
STM8S105xx
Memory and register map
Address Block
Register label
Register name
Reset
status
00 5205h
00 5206h
00 5207h
SPI_CRCPR
SPI_RXCRCR
SPI_TXCRCR
SPI CRC polynomial register
SPI Rx CRC register
0x07
0xFF
0xFF
SPI Tx CRC register
00 5208h Reserved area (8 bytes)
to 00
520Fh
00 5210h I2C
00 5211h
00 5212h
00 5213h
00 5214h
00 5215h
00 5216h
00 5217h
00 5218h
00 5219h
00 521Ah
00 521Bh
00 521Ch
00 521Dh
I2C_CR1
I2C_CR2
I2C_FREQR
I2C_OARL
I2C_OARH
Reserved
I2C_DR
I2C control register 1
0x00
0x00
0x00
0x00
0x00
I2C control register 2
I2C frequency register
I2C Own address register low
I2C own address register high
I2C data register
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x02
I2C_SR1
I2C status register 1
I2C_SR2
I2C status register 2
I2C_SR3
I2C status register 3
I2C_ITR
I2C interrupt control register
I2C clock control register low
I2C clock control register high
I2C TRISE register
I2C_CCRL
I2C_CCRH
I2C_TRISER
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Memory and register map
Address Block
00 521Eh
STM8S105xx
Register label
Register name
Reset
status
I2C_PECR
I2C packet error checking register
0x00
00 521Fh Reserved area (17 bytes)
to 00
522Fh
0x00
Reserved area (6 bytes)
5230 to
0x00
523F
0x00
5240
UART2
UART2_SR
UART2 status register
C0h
xx
0x00
5241
UART2_DR
UART2 data register
0x00
5242
UART2_BRR1
UART2_BRR2
UART2_CR1
UART2_CR2
UART2_CR3
UART2 baud rate register 1
UART2 baud rate register 2
UART2 control register 1
UART2 control register 2
UART2 control register 3
UART2 control register 4
0x00
0x00
0x00
0x00
0x00
0x00
0x00
5243
0x00
5244
0x00
5245
0x00
5246
005247
UART2_CR4
Reserved
0x00
5248
0x00
5249
UART2_CR6
UART2 control register 6
0x00
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DocID14771 Rev 9
STM8S105xx
Memory and register map
Address Block
Register label
Register name
Reset
status
0x00
524A
UART2_GTR
UART2 guard time register
UART2 prescaler register
0x00
0x00
0x00
524B
UART2_PSCR
0x00
Reserved area (4 bytes)
524C to
0x00
524F
0x00
5250
TIM1
TIM1_CR1
TIM1_CR2
TIM1_SMCR
TIM1_ETR
TIM1_IER
TIM1 control register 1
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
5251
TIM1 control register 2
0x00
5252
TIM1 slave mode control register
TIM1 external trigger register
TIM1 interrupt enable register
TIM1 status register 1
0x00
5253
0x00
5254
0x00
5255
TIM1_SR1
TIM1_SR2
TIM1_EGR
TIM1_CCMR1
0x00
5256
TIM1 status register 2
0x00
5257
TIM1 event generation register
0x00
5258
TIM1 capture/ compare mode
register 1
0x00
5259
TIM1_CCMR2
TIM1 capture/compare mode
register 2
0x00
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Memory and register map
Address Block
STM8S105xx
Register label
Register name
Reset
status
0x00
525A
TIM1_CCMR3
TIM1 capture/ compare mode
register 3
0x00
0x00
0x00
0x00
0x00
525B
TIM1_CCMR4
TIM1_CCER1
TIM1_CCER2
TIM1 capture/compare mode
register 4
0x00
525C
TIM1 capture/ compare enable
register 1
0x00
525D
TIM1 capture/compare enable
register 2
0x00
525E
TIM1_CNTRH
TIM1_CNTRL
TIM1_PSCRH
TIM1_PSCRL
TIM1_ARRH
TIM1_ARRL
TIM1_RCR
TIM1 counter high
0x00
0x00
0x00
0x00
0xFF
0xFF
0x00
0x00
525F
TIM1 counter low
0x00
5260
TIM1 prescaler register high
TIM1 prescaler register low
TIM1 auto-reload register high
TIM1 auto-reload register low
TIM1 repetition counter register
0x00
5261
0x00
5262
0x00
5263
0x00
5264
0x00
5265
TIM1_CCR1H
TIM1_CCR1L
TIM1 capture/ compare register 1 high 0x00
TIM1 capture/ compare register 1 low 0x00
0x00
5266
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STM8S105xx
Memory and register map
Address Block
Register label
Register name
Reset
status
0x00
5267
TIM1_CCR2H
TIM1 capture/ compare register 2 high 0x00
TIM1 capture/ compare register 2 low 0x00
TIM1 capture/ compare register 3 high 0x00
TIM1 capture/ compare register 3 low 0x00
TIM1 capture/ compare register 4 high 0x00
TIM1 capture/ compare register 4 low 0x00
0x00
5268
TIM1_CCR2L
TIM1_CCR3H
TIM1_CCR3L
TIM1_CCR4H
TIM1_CCR4L
TIM1_BKR
0x00
5269
0x00
526A
0x00
526B
0x00
526C
0x00
526D
TIM1 break register
0x00
0x00
0x00
0x00
526E
TIM1_DTR
TIM1 dead-time register
TIM1 output idle state register
0x00
526F
TIM1_OISR
0x00
Reserved area (147 bytes)
5270 to
0x00
52FF
0x00
5300
TIM2
TIM2_CR1
TIM2_IER
TIM2_SR1
TIM2 control register 1
TIM2 interrupt enable register
TIM2 status register 1
0x00
0x00
0x00
0x00
5301
0x00
5302
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Memory and register map
Address Block
STM8S105xx
Register label
Register name
Reset
status
0x00
5303
TIM2_SR2
TIM2 status register 2
0x00
0x00
0x00
0x00
5304
TIM2_EGR
TIM2 event generation register
0x00
5305
TIM2_CCMR1
TIM2 capture/ compare mode
register 1
0x00
5306
TIM2_CCMR2
TIM2_CCMR3
TIM2 capture/ compare mode
register 2
0x00
0x00
0x00
5307
TIM2 capture/ compare mode
register 3
0x00
5308
TIM2_CCER1
TIM2_CCER2
TIM2_CNTRH
TIM2_CNTRL
TIM2_PSCR
TIM2_ARRH
TIM2_ARRL
TIM2_CCR1H
TIM2 capture/ compare enable
register 1
0x00
0x00
0x00
0x00
0x00
0xFF
0xFF
0x00
5309
TIM2 capture/ compare enable
register 2
0x00
530A
TIM2 counter high
0x00
530B
TIM2 counter low
0x00
530C
TIM2 prescaler register
TIM2 auto-reload register high
TIM2 auto-reload register low
0x00
530D
0x00
530E
0x00
530F
TIM2 capture/ compare register 1 high 0x00
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STM8S105xx
Memory and register map
Address Block
Register label
Register name
Reset
status
0x00
5310
TIM2_CCR1L
TIM2 capture/ compare register 1 low 0x00
0x00
5311
TIM2_CCR2H
TIM2_CCR2L
TIM2_CCR3H
TIM2_CCR3L
TIM2 capture/ compare reg. 2 high
0x00
0x00
5312
TIM2 capture/ compare register 2 low 0x00
TIM2 capture/ compare register 3 high 0x00
TIM2 capture/ compare register 3 low 0x00
0x00
5313
0x00
5314
0x00
Reserved area (11 bytes)
5315 to
0x00
531F
0x00
5320
TIM3
TIM3_CR1
TIM3_IER
TIM3 control register 1
0x00
0x00
0x00
0x00
0x00
0x00
0x00
5321
TIM3 interrupt enable register
TIM3 status register 1
0x00
5322
TIM3_SR1
TIM3_SR2
TIM3_EGR
TIM3_CCMR1
0x00
5323
TIM3 status register 2
0x00
5324
TIM3 event generation register
0x00
5325
TIM3 capture/ compare mode
register 1
0x00
5326
TIM3_CCMR2
TIM3 capture/ compare mode
register 2
0x00
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Memory and register map
Address Block
STM8S105xx
Register label
Register name
Reset
status
0x00
5327
TIM3_CCER1
TIM3 capture/ compare enable
register 1
0x00
0x00
0x00
0x00
0xFF
0xFF
0x00
5328
TIM3_CNTRH
TIM3_CNTRL
TIM3_PSCR
TIM3_ARRH
TIM3_ARRL
TIM3_CCR1H
TIM3_CCR1L
TIM3_CCR2H
TIM3_CCR2L
TIM3 counter high
0x00
5329
TIM3 counter low
0x00
532A
TIM3 prescaler register
TIM3 auto-reload register high
TIM3 auto-reload register low
0x00
532B
0x00
532C
0x00
532D
TIM3 capture/ compare register 1 high 0x00
TIM3 capture/ compare register 1 low 0x00
TIM3 capture/ compare register 2 high 0x00
TIM3 capture/ compare register 2 low 0x00
0x00
532E
0x00
532F
0x00
5330
0x00
Reserved area (15 bytes)
5331 to
0x00
533F
0x00
5340
TIM4
TIM4_CR1
TIM4_IER
TIM4 control register 1
0x00
0x00
0x00
5341
TIM4 interrupt enable register
44/127
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STM8S105xx
Memory and register map
Address Block
Register label
Register name
Reset
status
0x00
5342
TIM4_SR
TIM4 status register
0x00
0x00
5343
TIM4_EGR
TIM4_CNTR
TIM4_PSCR
TIM4_ARR
TIM4 event generation register
TIM4 counter
0x00
0x00
0x00
0xFF
0x00
5344
0x00
5345
TIM4 prescaler register
TIM4 auto-reload register
0x00
5346
0x00
Reserved area (153 bytes)
5347 to
0x00
53DF
0x00
ADC1
ADC _DBxR
ADC data buffer registers
0x00
53E0 to
0x00
53F3
0x00
Reserved area (12 bytes)
53F4 to
0x00
53FF
0x00
5400
ADC1
ADC _CSR
ADC_CR1
ADC_CR2
ADC_CR3
ADC control/ status register
ADC configuration register 1
ADC configuration register 2
ADC configuration register 3
0x00
0x00
0x00
0x00
0x00
5401
0x00
5402
0x00
5403
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Memory and register map
Address Block
STM8S105xx
Register label
Register name
Reset
status
0x00
5404
ADC_DRH
ADC data register high
0x00
0x00
0x00
0x00
5405
ADC_DRL
ADC data register low
0x00
5406
ADC_TDRH
ADC Schmitt trigger disable
register high
0x00
5407
ADC_TDRL
ADC Schmitt trigger disable
register low
0x00
0x00
5408
ADC_HTRH
ADC_HTRL
ADC_LTRH
ADC_LTRL
ADC_AWSRH
ADC high threshold register high
ADC high threshold register low
ADC low threshold register high
ADC low threshold register low
0x03
0xFF
0x00
0x00
0x00
0x00
5409
0x00
540A
0x00
540B
0x00
540C
ADC analog watchdog status
register high
0x00
540D
ADC_AWSRL
ADC _AWCRH
ADC_AWCRL
ADC analog watchdog status
register low
0x00
0x00
0x00
0x00
540E
ADC analog watchdog control
register high
0x00
540F
ADC analog watchdog control
register low
0x00
Reserved area (1008 bytes)
5410 to
46/127
DocID14771 Rev 9
STM8S105xx
Memory and register map
Address Block
Register label
Register name
Reset
status
0x00
57FF
6.2.3
CPU/SWIM/debug module/interrupt controller registers
Table 10: CPU/SWIM/debug module/interrupt controller registers
Address Block
Register label Register name
Reset
status
0x00 7F00 CPU(1)
0x00 7F01
0x00 7F02
0x00 7F03
0x00 7F04
0x00 7F05
0x00 7F06
0x00 7F07
0x00 7F08
0x00 7F09
A
Accumulator
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x07
0xFF
0x28
PCE
PCH
PCL
XH
Program counter extended
Program counter high
Program counter low
X index register high
X index register low
Y index register high
Y index register low
Stack pointer high
XL
YH
YL
SPH
SPL
CCR
Stack pointer low
0x00
Condition code register
7F0A
0x00
Reserved area (85 bytes)
7F0B to
0x00
7F5F
0x00 7F60 CPU
CFG_GCR
Global configuration register
0x00
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Memory and register map
Address Block
STM8S105xx
Register label Register name
Reset
status
0x00 7F70 ITC -
SPR
ITC_SPR1
ITC_SPR2
ITC_SPR3
ITC_SPR4
ITC_SPR5
ITC_SPR6
ITC_SPR7
ITC_SPR8
Interrupt software priority register 1
0xFF
0xFF
0xFF
0xFF
0xFF
0xFF
0xFF
0xFF
0x00 7F71
0x00 7F72
0x00 7F73
0x00 7F74
0x00 7F75
0x00 7F76
0x00 7F77
Interrupt software priority register 2
Interrupt software priority register 3
Interrupt software priority register 4
Interrupt software priority register 5
Interrupt software priority register 6
Interrupt software priority register 7
Interrupt software priority register 8
0x00 7F78 Reserved area (2 bytes)
to 0x00
7F79
0x00 7F80 SWIM
SWIM_CSR
SWIM control status register
0x00
0x00 7F81 Reserved area (15 bytes)
to 0x00
7F8F
0x00 7F90 DM
0x00 7F91
0x00 7F92
0x00 7F93
0x00 7F94
0x00 7F95
0x00 7F96
DM_BK1RE
DM_BK1RH
DM_BK1RL
DM_BK2RE
DM_BK2RH
DM_BK2RL
DM_CR1
DM breakpoint 1 register extended byte
DM breakpoint 1 register high byte
DM breakpoint 1 register low byte
DM breakpoint 2 register extended byte
DM breakpoint 2 register high byte
DM breakpoint 2 register low byte
DM debug module control register 1
0xFF
0xFF
0xFF
0xFF
0xFF
0xFF
0x00
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Memory and register map
Address Block
Register label Register name
Reset
status
0x00 7F97
0x00 7F98
DM_CR2
DM debug module control register 2
DM debug module control/status
0x00
0x10
DM_CSR1
DM_CSR2
register 1
0x00 7F99
DM debug module control/status
register 2
0x00
0xFF
0x00
DM_ENFCTR DM enable function register
7F9A
0x00
Reserved area (5 bytes)
7F9B to
0x00
7F9F
(1) Accessible by debug module only
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Interrupt vector mapping
STM8S105xx
7
Interrupt vector mapping
Table 11: Interrupt mapping
IRQ Source
Description
Wakeup
from halt
mode
Wakeup from Vector
no.
block
active-halt
mode
address
RESET
TRAP
TLI
Reset
Yes
Yes
-
0x00 8000
0x00 8004
0x00 8008
0x00 800C
0x00 8010
0x00 8014
0x00 8018
0x00 801C
0x00 8020
0x00 8024
0x00 8028
0x00 802C
0x00 8030
0x00 8034
Software interrupt
-
0
External top level interrupt -
-
1
AWU
Auto wake up from halt
Clock controller
-
-
Yes
-
2
CLK
3
EXTI0
EXTI1
EXTI2
EXTI3
EXTI4
Port A external interrupts Yes(1)
Port B external interrupts Yes
Port C external interrupts Yes
Port D external interrupts Yes
Port E external interrupts Yes
Yes(1)
Yes
Yes
Yes
Yes
4
5
6
7
8
9
Reserved
-
-
10
11
SPI
End of transfer
Yes
-
Yes
-
TIM1
TIM1 update/ overflow/
underflow/ trigger/ break
12
13
14
TIM1
TIM
TIM1 capture/ compare
TIM update/ overflow
TIM capture/ compare
-
-
-
-
-
-
0x00 8038
0x00 803C
0x00 8040
TIM
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Interrupt vector mapping
Wakeup from Vector
IRQ Source
no.
Description
Wakeup
from halt
mode
block
active-halt
mode
address
15
16
17
18
19
20
21
TIM3
TIM3
Update/ overflow
Capture/ compare
Reserved
-
-
0x00 8044
0x00 8048
0x00 804C
0x00 8050
0x00 8054
0x00 8058
0x00 805C
-
-
-
-
Reserved
-
-
I2C
I2C interrupt
Tx complete
Yes
Yes
UART2
UART2
-
-
-
-
Receive register DATA
FULL
22
ADC1
ADC1 end of conversion/
analog watchdog interrupt
-
-
0x00 8060
23
24
TIM
TIM update/ overflow
EOP/ WR_PG_DIS
-
-
-
-
0x00 8064
0x00 8068
Flash
Reserved
0x00 806C
to 0x00
807C
(1) Except PA1
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Option bytes
STM8S105xx
8
Option bytes
Option bytes contain configurations for device hardware features as well as the memory
protection of the device. They are stored in a dedicated block of the memory. Except for the
ROP (read-out protection) byte, each option byte has to be stored twice, in a regular form
(OPTx) and a complemented one (NOPTx) for redundancy.
Option bytes can be modified in ICP mode (via SWIM) by accessing the EEPROM address
shown in the table below.
Option bytes can also be modified ‘on the fly’ by the application in IAP mode, except the ROP
option that can only be modified in ICP mode (via SWIM).
Refer to the STM8S Flash programming manual (PM0051) and STM8 SWIM communication
protocol and debug module user manual (UM0470) for information on SWIM programming
procedures.
Table 12: Option bytes
Addr.
Option
name
Option Option bits
byte no.
Factory
default
setting
7
6
5
4
3
2
1
0
0x4800 Read-out
protection
OPT0
ROP [7:0]
00h
(ROP)
0x4801 User boot
code(UBC)
OPT1
UBC [7:0]
00h
FFh
00h
0x4802
NOPT1 NUBC [7:0]
AFR5
AFR4
AFR3
AFR2
AFR1
AFR0
0x4803 Alternate
function
OPT2
AFR7
AFR6
remapping
0x4804
(AFR)
NOPT2 NAFR7
NAFR6 NAFR5 NAFR4
NAFR3
NAFR2 NAFR1
NAFR0 FFh
0x4805h Miscell.
option
OPT3
Reserved
HSI
TRIM
LSI_ EN
IWDG
_HW
WWDG WWDG 00h
_HW _HALT
0x4806
NOPT3 Reserved
NHSI
TRIM
NLSI_
EN
NIWDG NWWDG NWW
_HW _HW G_HALT
FFh
0x4807 Clock
option
OPT4
Reserved
EXT CLK CKAWU PRS C1 PRS C0 00h
SEL
0x4808
NOPT4 Reserved
NEXT
CLK
NCKA
WUSEL
NPRSC1 NPR
SC0
FFh
0x4809 HSE clock OPT5
startup
HSECNT [7:0]
00h
FFh
00h
0x480A
NOPT5 NHSECNT [7:0]
OPT6
0x480B Reserved
Reserved
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Option bytes
Addr.
Option
name
Option Option bits
byte no.
Factory
default
setting
7
6
5
4
3
2
1
0
NOPT6
OPT7
0x480C
Reserved
FFh
00h
FFh
00h
FFh
0x480D Reserved
0x480E
Reserved
Reserved
BL[7:0]
NOPT7
OPTBL
NOPTBL
0x487E Bootloader
0x487F
NBL[7:0]
Table 13: Option byte description
Description
ROP[7:0] Memory readout protection (ROP)
Option byte no.
OPT0
AAh: Enable readout protection (write access via SWIM protocol)
Note: Refer to the family reference manual (RM0016) section on
Flash/EEPROM memory readout protection for details.
OPT1
UBC[7:0] User boot code area
0x00: no UBC, no write-protection
0x01: Page 0 to 1 defined as UBC, memory write-protected
0x02: Page 0 to 3 defined as UBC, memory write-protected
0x03: Page 0 to 4 defined as UBC, memory write-protected
...
0x3E: Pages 0 to 63 defined as UBC, memory write-protected
Other values: Reserved
Note: Refer to the family reference manual (RM0016) section on
Flash write protection for more details.
OPT2
OPT3
AFR[7:0]
Refer to following table for the alternate function remapping
decriptions of bits [7:2].
HSITRIM:High speed internal clock trimming register size
0: 3-bit trimming supported in CLK_HSITRIMR register
1: 4-bit trimming supported in CLK_HSITRIMR register
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Option bytes
STM8S105xx
Option byte no.
Description
LSI_EN:Low speed internal clock enable
0: LSI clock is not available as CPU clock source
1: LSI clock is available as CPU clock source
IWDG_HW: Independent watchdog
0: IWDG Independent watchdog activated by software
1: IWDG Independent watchdog activated by hardware
WWDG_HW: Window watchdog activation
0: WWDG window watchdog activated by software
1: WWDG window watchdog activated by hardware
WWDG_HALT: Window watchdog reset on halt
0: No reset generated on halt if WWDG active
1: Reset generated on halt if WWDG active
OPT4
EXTCLK: External clock selection
0: External crystal connected to OSCIN/OSCOUT
1: External clock signal on OSCIN
CKAWUSEL:Auto wake-up unit/clock
0: LSI clock source selected for AWU
1: HSE clock with prescaler selected as clock source for for AWU
PRSC[1:0] AWU clock prescaler
0x: 16 MHz to 128 kHz prescaler
10: 8 MHz to 128 kHz prescaler
11: 4 MHz to 128 kHz prescaler
OPT5
HSECNT[7:0]:HSE crystal oscillator stabilization time
0x00: 2048 HSE cycles
0xB4: 128 HSE cycles
0xD2: 8 HSE cycles
0xE1: 0.5 HSE cycles
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Option bytes
Option byte no.
Description
OPT6
Reserved
OPT7
Reserved
OPTBL
BL[7:0] Bootloader option byte
For STM8S products, this option is checked by the boot ROM code
after reset. Depending on the content of addresses 0x487E, 0x487F,
and 0x8000 (reset vector), the CPU jumps to the bootloader or to
the reset vector. Refer to the UM0560 (STM8L/S bootloader manual)
for more details.
For STM8L products, the bootloader option bytes are on addresses
0xXXXX and 0xXXXX+1 (2 bytes). These option bytes control
whether the bootloader is active or not. For more details, refer to the
UM0560 (STM8L/S bootloader manual) for more details.
Table 14: Description of alternate function remapping bits [7:0] of OPT2
Option byte no.
OPT2
Description(1)
AFR7 Alternate function remapping option 7
0: AFR7 remapping option inactive: Default alternate function(2)
1: Port D4 alternate function = BEEP.
.
AFR6 Alternate function remapping option 6
0: AFR6 remapping option inactive: Default alternate functions(2)
.
1: Port B5 alternate function = I2C_SDA; port B4 alternate function
= I2C_SCL.
AFR5 Alternate function remapping option 5
0: AFR5 remapping option inactive: Default alternate functions(2)
.
1: Port B3 alternate function = TIM1_ETR; port B2 alternate function
= TIM1_NCC3; port B1 alternate function = TIM1_CH2N; port B0
alternate function = TIM1_CH1N.
AFR4 Alternate function remapping option 4
0: AFR4 remapping option inactive: Default alternate function(2)
.
1: Port D7 alternate function = TIM1_CH4.
AFR3 Alternate function remapping option 3
0: AFR3 remapping option inactive: Default alternate function(2)
.
1: Port D0 alternate function = TIM1_BKIN.
AFR2 Alternate function remapping option 2
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Option bytes
STM8S105xx
Option byte no.
Description(1)
0: AFR2 remapping option inactive: Default alternate function(2)
.
1: Port D0 alternate function = CLK_CCO.Note: AFR2 option has
priority over AFR3 if both are activated.
AFR1 Alternate function remapping option 1
0: AFR1 remapping option inactive: Default alternate functions(2)
.
1: Port A3 alternate function = TIM3_CH1; port D2 alternate function
TIM2_CH3.
AFR0 Alternate function remapping option 0
0: AFR0 remapping option inactive: Default alternate function(2)
.
1: Port D3 alternate function = ADC_ETR.
(1) Do not use more than one remapping option in the same port.
(2) Refer to pinout description.
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Unique ID
9
Unique ID
The devices feature a 96-bit unique device identifier which provides a reference number that
is unique for any device and in any context. The 96 bits of the identifier can never be altered
by the user.
The unique device identifier can be read in single bytes and may then be concatenated using
a custom algorithm.
The unique device identifier is ideally suited:
For use as serial numbers
•
For use as security keys to increase the code security in the program memory while using
and combining this unique ID with software cryptograhic primitives and protocols before
programming the internal memory.
•
To activate secure boot processes
•
Table 15: Unique ID registers (96 bits)
Address Content
description
Unique ID bits
7
6
5
4
3
2
1
0
0x48CD
0x48CE
0x48CF
0x48D0
U_ID[7:0]
X co-ordinate
on the wafer
U_ID[15:8]
U_ID[23:16]
U_ID[31:24]
U_ID[39:32]
U_ID[47:40]
U_ID[55:48]
U_ID[63:56]
U_ID[71:64]
U_ID[79:72]
U_ID[87:80]
U_ID[95:88]
Y co-ordinate
on the wafer
0x48D1 Wafer number
0x48D2
0x48D3
0x48D4
Lot number
0x48D5
0x48D6
0x48D7
0x48D8
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Electrical characteristics
STM8S105xx
10
Electrical characteristics
10.1
Parameter conditions
Unless otherwise specified, all voltages are referred to VSS
.
10.1.1
Minimum and maximum values
Unless otherwise specified the minimum and maximum values are guaranteed in the worst
conditions of ambient temperature, supply voltage and frequencies by tests in production on
100 % of the devices with an ambient temperature at TA = 25 °C and TA = TAmax (given by
the selected temperature range).
Data based on characterization results, design simulation and/or technology characteristics
are indicated in the table footnotes and are not tested in production. Based on characterization,
the minimum and maximum values refer to sample tests and represent the mean value plus
or minus three times the standard deviation (mean ± 3 Σ).
10.1.2
Typical values
Unless otherwise specified, typical data are based on TA = 25 °C, VDD = 5 V. They are given
only as design guidelines and are not tested.
Typical ADC accuracy values are determined by characterization of a batch of samples from
a standard diffusion lot over the full temperature range, where 95% of the devices have an
error less than or equal to the value indicated (mean ± 2 Σ).
10.1.3
10.1.4
Typical curves
Unless otherwise specified, all typical curves are given only as design guidelines and are not
tested.
Typical current consumption
For typical current consumption measurements, VDD, VDDIO and VDDA are connected together
in the configuration shown in the following figure.
Figure 8: Supply current measurement conditions
5 V or 3.3 V
A
V
DD
V
V
V
V
DDA
DDIO
SS
SSA
V
SSIO
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Electrical characteristics
10.1.5
Loading capacitor
The loading conditions used for pin parameter measurement are shown in the following figure.
Figure 9: Pin loading conditions
STM8 PIN
50 pF
10.1.6
Pin input voltage
The input voltage measurement on a pin of the device is described in the following figure.
Figure 10: Pin input voltage
STM8 PIN
V
IN
10.2
Absolute maximum ratings
Stresses above those listed as ‘absolute maximum ratings’ may cause permanent damage
to the device. This is a stress rating only and functional operation of the device under these
conditions is not implied. Exposure to maximum rating conditions for extended periods may
affect device reliability.
Table 16: Voltage characteristics
Symbol
Ratings
Min
Max
Unit
(1)
VDDx - VSS Supply voltage (including VDDA and VDDIO
)
-0.3
6.5
V
VIN
Input voltage on true open drain pins (PE1,
PE2)(2)
VSS - 0.3 6.5
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Electrical characteristics
STM8S105xx
Max Unit
Symbol
Ratings
Min
Input voltage on any other pin(2)
VSS - 0.3 VDD + 0.3
50
|VDDx
VDD
-
Variations between different power pins
mV
|
|VSSx - VSS| Variations between all the different ground pins
VESD Electrostatic discharge voltage
50
see Absolute maximum
ratings (electrical sensitivity)
(1) All power (VDD, VDDIO, VDDA) and ground (VSS, VSSIO, VSSA) pins must always be
connected to the external power supply
(2)
I
must never be exceeded. This is implicitly insured if VIN maximum is respected.
INJ(PIN)
If VIN maximum cannot be respected, the injection current must be limited externally to the
IINJ(PIN) value. A positive injection is induced by VIN>VDD while a negative injection is induced
by VIN<VSS. For true open-drain pads, there is no positive injection current, and the
corresponding VIN maximum must always be respected
Table 17: Current characteristics
Symbol
Ratings
Max.(1)
Unit
IVDD
Total current into VDD power lines (source)(2)
60
mA
IVSS
IIO
Total current out of VSS ground lines (sink)(2)
Output current sunk by any I/O and control pin
Output current source by any I/Os and control pin
60
20
20
ΣIIO
Total output current sourced (sum of all I/O and control 200
pins) for devices with two VDDIO pins(3)
Total output current sourced (sum of all I/O and control 100
pins) for devices with one VDDIO pin(3)
Total output current sunk (sum of all I/O and control
pins) for devices with two VSSIO pins(3)
160
80
Total output current sunk (sum of all I/O and control
pins) for devices with one VSSIO pin(3)
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Electrical characteristics
Symbol
Ratings
Max.(1)
Unit
(4) (5)
IINJ(PIN)
Injected current on NRST pin
±4
Injected current on OSCIN pin
±4
±4
Injected current on any other pin(6)
(4)
ΣIINJ(PIN)
Total injected current (sum of all I/O and control pins)(6) ±20
(1) Data based on characterization results, not tested in production.
(2) All power (VDD, VDDIO, VDDA) and ground (VSS, VSSIO, VSSA) pins must always be
connected to the external supply.
(3) I/O pins used simultaneously for high current source/sink must be uniformly spaced
around the package between the VDDIO/VSSIO pins.
(4)
I
must never be exceeded. This is implicitly insured if VIN maximum is respected.
INJ(PIN)
If VIN maximum cannot be respected, the injection current must be limited externally to the
IINJ(PIN) value. A positive injection is induced by VIN>VDD while a negative injection is induced
by VIN<VSS. For true open-drain pads, there is no positive injection current, and the
corresponding VIN maximum must always be respected
(5) Negative injection disturbs the analog performance of the device. See note in I2C interface
characteristics.
(6) When several inputs are submitted to a current injection, the maximum ΣIINJ(PIN) is the
absolute sum of the positive and negative injected currents (instantaneous values). These
results are based on characterization with ΣIINJ(PIN) maximum current injection on four I/O
port pins of the device.
Table 18: Thermal characteristics
Symbol
Ratings
Value
Unit
TSTG
Storage temperature range
-65 to 150
°C
TJ
Maximum junction temperature
150
10.3
Operating conditions
The device must be used in operating conditions that respect the parameters in the table
below. In addition, full account must be taken of all physical capacitor characteristics and
tolerances.
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Electrical characteristics
STM8S105xx
Table 19: General operating conditions
Symbol
Parameter
Conditions
Min
Max
16
Unit
fCPU
Internal CPU clock
frequency
0
MHz
VDD/ VDD_IO
Standard operating
voltage
2.95 5.5
V
VCAP
CEXT: capacitance of
external capacitor(1)
at 1 MHz
470
3300 nF
ESR of external
capacitor(1)
0.3
15
Ohm
nH
ESL of external
capacitor(1)
(2)
PD
Power dissipation at
TA = 85 °C for suffix
6or TA= 125° C for
suffix 3
44 and 48-pin devices,
with output on eight
standard ports, two high
sink ports and two open
drain ports
443
mW
simultaneously(3)
32-pin package, with
output on eight standard
ports and two high sink
ports simultaneously(3)
360
TA
Ambient temperature Maximum power
for 6 suffix version dissipation
-40
-40
85
°C
Ambient temperature Maximum power
for 3 suffix version dissipation
125
TJ
Junction temperature 6 suffix version
range
-40
-40
105
3 suffix version
130(4)
(1) Care should be taken when selecting the capacitor, due to its tolerance, as well as its
dependency on temperature, DC bias and frequency in addition to other factors.
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Electrical characteristics
(2) To calculate PDmax(TA), use the formula PDmax = (TJmax - TA)/ΘJA (see Thermal
characteristics ) with the value for TJmax given in the current table and the value for ΘJA
given in Thermal characteristics.
(3) Refer to Thermal characteristics.
(4)
T
is given by the test limit. Above this value the product behavior is not guaranteed.
Jmax
Figure 11: fCPUmax versus VDD
f
(MHz)
CPU
Functionality
16
12
8
not
guaranteed
in this area
Functionality guaranteed
@T -40 to 125 °C
A
4
0
4.0
Supply voltage
2.95
5.0
5.5
Table 20: Operating conditions at power-up/power-down
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
tVDD
VDD rise time rate
2 (1)
∞
µs/V
VDD fall time rate
2 (1)
∞
tTEMP
VIT+
Reset releasedelay VDD rising
1.7 (1) ms
Power-on reset
threshold
2.65
2.58
2.8
2.7
70
2.95
2.88
V
VIT-
Brown-out reset
threshold
VHYS(BOR) Brown-out reset
hysteresis
mV
(1) Guaranteed by design, not tested in production.
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Electrical characteristics
STM8S105xx
10.3.1
VCAP external capacitor
Stabilization for the main regulator is achieved connecting an external capacitor CEXT to the
VCAP pin. CEXT is specified in the Operating conditions section. Care should be taken to limit
the series inductance to less than 15 nH.
Figure 12: External capacitor CEXT
ESL
C
ESR
R
Leak
1. ESR is the equivalent series resistance and ESL is the equivalent inductance.
10.3.2
Supply current characteristics
The current consumption is measured as described in Pin input voltage.
10.3.2.1 Total current consumption in run mode
Table 21: Total current consumption with code execution in run mode at VDD = 5 V
Symbol Parameter
Conditions
Typ Max(1) Unit
IDD(RUN) Supply
current in run
mode, code
executed
fCPU = fMASTER
= 16 MHz
HSE crystal osc.
(16 MHz)
3.2
mA
from RAM
HSE user ext. clock
(16 MHz)
2.6 3.2
2.5 3.2
1.6 2.2
1.3 2.0
HSI RC osc.
(16 MHz)
fCPU = fMASTER/128 = HSE user ext. clock
125 kHz
(16 MHz)
HSI RC osc.
(16 MHz)
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Electrical characteristics
Symbol Parameter
Conditions
Typ Max(1) Unit
fCPU = fMASTER/128 = HSI RC osc.
0.75
15.625 kHz
(16 MH3z/8)
fCPU = fMASTER
= 128 kHz
LSI RC osc.
(128 kHz)
0.55
7.7
IDD(RUN)
Supply
fCPU = fMASTER
= 16 MHz
HSE crystal osc.
(16 MHz)
current in run
mode, code
executed
fromFlash
HSE user ext. clock
(16 MHz)
7.0
8
HSI RC osc.
(16 MHz)
7.0 8.0
fCPU = fMASTER
= 2 MHz
HSI RC osc.
(16 MHz/8)(2)
1.5
fCPU = fMASTER/128 = HSI RC osc.
1.35 2.0
0.75
125 kHz
(16 MHz)
fCPU = fMASTER/128 = HSI RC osc.
15.625 kHz
(16 MHz/8)
fCPU = fMASTER
= 128 kHz
LSI RC osc.
(128 kHz)
0.6
(1) Data based on characterization results, not tested in production.
(2) Default clock configuration measured with all peripherals off.
Table 22: Total current consumption with code execution in run mode at VDD = 3.3 V
Typ Max(1) Unit
Symbol Parameter Conditions
IDD(RUN) Supply
current
fCPU = fMASTER = 16 MHz HSE crystal osc.
(16 MHz)
2.8
mA
in run
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Electrical characteristics
STM8S105xx
Symbol Parameter Conditions
Typ Max(1) Unit
mode,
code
executed
from
HSE user ext. clock
(16 MHz)
2.6 3.2
RAM
HSI RC osc.
(16 MHz)
2.5 3.2
1.6 2.2
1.3 2.0
fCPU = fMASTER/128
= 125 kHz
HSE user ext. clock
(16 MHz)
HSI RC osc.
(16 MHz)
fCPU = fMASTER/128 =
15.625 kHz
HSI RC osc. (16 MHz/8) 0.75
fCPU = fMASTER = 128 kHz LSI RC osc.
(128 kHz)
0.55
7.3
7.0
Supply
current
in run
mode,
code
fCPU = fMASTER = 16 MHz HSE crystal osc.
(16 MHz)
HSE user ext. clock
(16 MHz)
8
executed
from
Flash
HSI RC osc.
(16 MHz)
7.0 8.0
fCPU = fMASTER = 2 MHz
HSI RC osc.
(16 MHz/8)(2)
1.5
fCPU = fMASTER/128
= 125 kHz
HSI RC osc.
(16 MHz)
1.35 2.0
0.75
fCPU = fMASTER/128 =
15.625 kHz
HSI RC osc.
(16 MHz/8)
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Symbol Parameter Conditions
Typ Max(1) Unit
fCPU = fMASTER = 128 kHz LSI RC osc.
(128 kHz)
0.6
(1) Data based on characterization results, not tested in production.
(2) Default clock configuration measured with all peripherals off.
10.3.2.2 Total current consumption in wait mode
Table 23: Total current consumption in wait mode at VDD = 5 V
Typ Max(1) Unit
Symbol Parameter
Conditions
IDD(WFI) Supply
current in
wait mode
fCPU = fMASTER
= 16 MHz
HSE crystal osc.
(16 MHz)
2.15
mA
HSE user ext. clock
(16 MHz)
1.55 2.0
1.5 1.9
1.3
HSI RC osc.
(16 MHz)
fCPU = fMASTER/128 HSI RC osc.
= 125 kHz
(16 MHz)
fCPU = fMASTER/128 HSI RC osc.
0.7
= 15.625 kHz
(16 MHz/8)(2)
fCPU = fMASTER
= 128 kHz
LSI RC osc.
(128 kHz)
0.5
(1) Data based on characterization results, not tested in production.
(2) Default clock configuration measured with all peripherals off.
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Table 24: Total current consumption in wait mode at VDD = 3.3 V
Symbol Parameter
Conditions
Typ Max(1) Unit
IDD(WFI) Supply
current in
wait mode
fCPU = fMASTER
= 16 MHz
HSE crystal osc.
(16 MHz)
1.75
mA
HSE user ext. clock
(16 MHz)
1.55 2.0
1.5 1.9
1.3
HSI RC osc.
(16 MHz)
fCPU = fMASTER/128 HSI RC osc.
= 125 kHz
(16 MHz)
fCPU = fMASTER/128 HSI RC osc.
0.7
= 15.625 kHz
(16 MHz/8)(2)
fCPU = fMASTER
128 kHz
=
LSI RC osc.
(128 kHz)
0.5
(1) Data based on characterization results, not tested in production.
(2) Default clock configuration measured with all peripherals off.
10.3.2.3 Total current consumption in active halt mode
Table 25: Total current consumption in active halt mode at VDD = 5 V
Symbol Parameter Conditions
Typ Max Max at Unit
at 85 125
°C(1) °C(1)
Main
Flash mode(3) Clock source
voltage
regulator
(MVR)(2)
IDD(AH) Supply
current in
On
Operating
mode
HSE crystal 1080
osc.
µA
active halt
mode
(16 MHz)
LSI RC osc. 200
320
400
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Symbol Parameter Conditions
Typ Max Max at Unit
at 85 125
°C(1) °C(1)
Main
Flash mode(3) Clock source
voltage
regulator
(MVR)(2)
(128 kHz)
Power-down
mode
HSE crystal 1030
osc.
(16 MHz)
LSI RC osc. 140
(128 kHz)
270
350
Off
Operating
mode
LSI RC osc. 68
(128 kHz)
120
60
220
150
Power-down
mode
12
(1) Data based on characterization results, not tested in production
(2) Configured by the REGAH bit in the CLK_ICKR register.
(3) Configured by the AHALT bit in the FLASH_CR1 register.
Table 26: Total current consumption in active halt mode at VDD = 3.3 V
Symbol Parameter Conditions Typ Max Max at Unit
at 85 125
°C(1) °C(1)
Main
Flash
Clock source
voltage mode(3)
regulator
(MVR)(2)
IDD(AH) Supply
current in
On
Operating
mode
HSE crystal
osc.
680
µA
active halt
mode
(16 MHz)
LSI RC osc.
(128 kHz)
200 320
400
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Symbol Parameter Conditions
Typ Max Max at Unit
at 85 125
°C(1) °C(1)
Main
Flash
Clock source
voltage mode(3)
regulator
(MVR)(2)
Power-down HSE crystal
630
mode
osc.
(16 MHz)
LSI RC osc.
(128 kHz)
140 270
66 120
10 60
350
220
150
Off
Operating
mode
LSI RC osc.
(128 kHz)
Power-down
mode
(1) Data based on characterization results, not tested in production.
(2) Configured by the REGAH bit in the CLK_ICKR register.
(3) Configured by the AHALT bit in the FLASH_CR1 register.
10.3.2.4 Total current consumption in halt mode
Table 27: Total current consumption in halt mode at VDD = 5 V
Symbol Parameter
Conditions
Typ Max at Max at Unit
85 °C(1) 125
°C(1)
IDD(H)
Supply current Flash in operating mode, HSI 62
90
25
150
80
µA
in halt mode
clock after wakeup
Flash in powerdown mode,
HSI clock after wakeup
6.5
(1) Data based on characterization results, not tested in production.
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Table 28: Total current consumption in halt mode at VDD = 3.3 V
Symbol Parameter
Conditions
Typ Max at Max at Unit
85 °C(1) 125
°C(1)
IDD(H)
Supply current Flash in operating mode, HSI 60
90
20
150
80
µA
in halt mode
clock after wakeup
Flash in powerdown mode,
HSI clock after wakeup
4.5
(1) Data based on characterization results, not tested in production.
10.3.2.5 Low power mode wakeup times
Table 29: Wakeup times
Conditions
Symbol Parameter
Wakeup time from
Typ
Max(1) Unit
See
0 to 16 MHz
note(2)
tWU(WFI) wait mode to run
mode(3)
fCPU = fMASTER = 16 MHz
0.56
1(6)
Wakeup time active MVR voltage
HSI
(after
wakeup)
Flash in operating
mode(5)
2(6)
halt mode to run
regulator
mode(3)
on(4)
Wakeup time active MVR voltage Flash in
HSI
(after
wakeup)
halt mode to run
regulator
power-down
3(6)
mode(3)
on(4)
mode(5)
μs
tWU(AH)
Wakeup time active MVR voltage
HSI
(after
wakeup)
Flash in operating
mode(5)
halt mode to run
regulator
48(6)
mode(3)
off(4)
Wakeup time active MVR voltage Flash in
HSI
(after
wakeup)
halt mode to run
regulator
power-down
50(6)
mode(3)
off(4)
mode(5)
Wakeup time from
Flash in operating mode(5)
52
54
tWU(H) halt mode to run
Flash in power-down mode(5)
mode(3)
(1) Data guaranteed by design, not tested in production.
(2)
t
= 2 x 1/fmaster + 6 x 1/fCPU.
WU(WFI)
(3) Measured from interrupt event to interrupt vector fetch.
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(4) Configured by the REGAH bit in the CLK_ICKR register.
(5) Configured by the AHALT bit in the FLASH_CR1 register.
(6) Plus 1 LSI clock depending on synchronization.
10.3.2.6 Total current consumption and timing in forced reset state
Table 30: Total current consumption and timing in forced reset state
Symbol
Parameter
Conditions
Typ
Max(1) Unit
IDD(R)
Supply current in reset
state(2)
VDD = 5 V
500
μA
VDD = 3.3 V
400
tRESETBL
Reset pin release to
vector fetch
150
μs
(1) Data guaranteed by design, not tested in production.
(2) Characterized with all I/Os tied to VSS
.
10.3.2.7 Current consumption of on-chip peripherals
Subject to general operating conditions for VDD and TA.
HSI internal RC/fCPU = fMASTER = 16 MHz.
Table 31: Peripheral current consumption
Symbol
Parameter
Typ.
Unit
IDD(TIM1)
TIM1 supply current(1)
230
IDD(TIM2)
IDD(TIM3)
IDD(TIM4)
IDD(UART2)
IDD(SPI)
TIM2 supply current (1)
115
90
TIM3 timer supply current (1)
TIM4 timer supply current (1)
UART2 supply current(2)
SPI supply current (2)
µA
30
110
45
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Symbol
Parameter
Typ.
Unit
2
IDD(I
IDD(ADC1)
I2C supply current (2)
65
C)
ADC1 supply current when converting(3)
955
(1) Data based on a differential IDD measurement between reset configuration and timer
counter running at 16 MHz. No IC/OC programmed (no I/O pads toggling). Not tested in
production.
(2) Data based on a differential IDD measurement between the on-chip peripheral when kept
under reset and not clocked and the on-chip peripheral when clocked and not kept under
reset. No I/O pads toggling. Not tested in production.
(3) Data based on a differential IDD measurement between reset configuration and continuous
A/D conversions. Not tested in production.
10.3.2.8 Current consumption curves
The following figures show typical current consumption measured with code executing in
RAM.
Figure 13: Typ. IDD(RUN) vs. VDD , HSE user external clock, fCPU = 16 MHz
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Figure 14: Typ. IDD(RUN) vs. fCPU , HSE user external clock, VDD= 5 V
Figure 15: Typ. IDD(RUN) vs. VDD , HSI RC osc, fCPU = 16 MHz
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Figure 16: Typ. IDD(WFI) vs. VDD , HSE user external clock, fCPU = 16 MHz
Figure 17: Typ. IDD(WFI) vs. fCPU, HSE user external clock VDD = 5 V
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Figure 18: Typ. IDD(WFI) vs. VDD, HSI RC osc, fCPU = 16 MHz
10.3.3
External clock sources and timing characteristics
HSE user external clock
Subject to general operating conditions for VDD and TA.
Table 32: HSE user external clock characteristics
Symbol Parameter
Conditions
Min
Max
Unit
fHSE_ext User external clock source
frequency
0
16
MHz
(1)
VHSEH
OSCIN input pin high level
voltage
0.7 x VDD
VDD + 0.3 V
V
(1)
VHSEL
OSCIN input pin low level
voltage
VSS
-1
0.3 x VDD
+1
ILEAK_HSE OSCIN input leakage current
VSS < VIN < VDD
μA
(1) Data based on characterization results, not tested in production.
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Figure 19: HSE external clocksource
V
V
HSEH
HSEL
f
HSE
External clock
source
OSCIN
STM8
HSE crystal/ceramic resonator oscillator
The HSE clock can be supplied with a 1 to 16 MHz crystal/ceramic resonator oscillator. All
the information given in this paragraph is based on characterization results with specified
typical external components. In the application, the resonator and the load capacitors have
to be placed as close as possible to the oscillator pins in order to minimize output distortion
and start-up stabilization time. Refer to the crystal resonator manufacturer for more details
(frequency, package, accuracy...).
Table 33: HSE oscillator characteristics
Symbol
Parameter
Conditions
Min Typ Max
Unit
fHSE
External high speed
oscillator frequency
1
16
20
MHz
RF
Feedback resistor
220
kΩ
pF
C(1)
Recommended load
capacitance(2)
IDD(HSE)
HSE oscillator power
consumption
C = 20 pF,
6 (startup)
1.6 (stabilized)(3)
fOSC = 16 MHz
mA
C = 10 pF,
6 (startup)
fOSC =16 MHz
1.2 (stabilized)(3)
gm
Oscillator
transconductance
5
mA/V
ms
(4)
tSU(HSE)
Startup time
VDD is stabilized
1
(1) C is approximately equivalent to 2 x crystal Cload.
(2) The oscillator selection can be optimized in terms of supply current using a high quality resonator with
small Rm value. Refer to crystal manufacturer for more details
(3) Data based on characterization results, not tested in production.
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(4)
t
is the start-up time measured from the moment it is enabled (by software) to a stabilized 16
SU(HSE)
MHz oscillation is reached. This value is measured for a standard crystal resonator and it can vary
significantly with the crystal manufacturer.
Figure 20: HSE oscillator circuit diagram
R
m
f
to core
HSE
C
O
R
g
L
m
F
C
L1
C
m
OSCIN
m
Resonator
Consumption
control
Resonator
OSCOUT
C
L2
STM8
HSE oscillator critical g m equation
gmcrit= (2 × Π × fHSE)2 × Rm(2Co + C)2
Rm: Notional resistance (see crystal specification)
Lm: Notional inductance (see crystal specification)
Cm: Notional capacitance (see crystal specification)
Co: Shunt capacitance (see crystal specification)
CL1= CL2 = C: Grounded external capacitance
gm >> gmcrit
10.3.4
Internal clock sources and timing characteristics
Subject to general operating conditions for VDD and TA.
High speed internal RC oscillator (HSI)
Table 34: HSI oscillator characteristics
Symbol Parameter
fHSI Frequency
Conditions
Min
Typ Max
Unit
16
MHz
ACCHSI Accuracy of HSI
oscillator
User-trimmed with
CLK_HSITRIMR register
for given VDD and TA
conditions(1)
1.0(2)
%
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Electrical characteristics
Symbol Parameter
Accuracy of HSI
Conditions
Min
Typ Max
Unit
VDD = 5 V, TA = 25°C(3)
-1.0
1.0
oscillator (factory
calibrated)
VDD = 5 V, 25 °C ≤ TA ≤
85 °C
-2.0
2.0
2.95 ≤ VDD≤ 5.5 V,-40 °C -3.0(3)
≤ TA ≤ 125 °C
3.0(3)
tsu(HSI) HSI oscillator
wakeup time
1.0(2) µs
including calibration
IDD(HSI) HSI oscillator power
consumption
170 250(3) µA
(1) Refer to application note.
(2) Guaranteed by design, not tested in production.
(3) Data based on characterization results, not tested in production.
Figure 21: Typical HSI accuracy at VDD = 5 V vs 5 temperatures
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Figure 22: Typical HSI accuracy vs VDD @ 4 temperatures
Low speed internal RC oscillator (LSI)
Subject to general operating conditions for VDD and TA.
Table 35: LSI oscillator characteristics
Symbol Parameter
Min
Typ
Max
Unit
fLSI
Frequency
110
128
146
kHz
tsu(LSI)
IDD(LSI)
LSI oscillator wakeup time
LSI oscillator power consumption
7(1)
µs
5
µA
(1) Guaranteeed by design, not tested in production.
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Figure 23: Typical LSI accuracy vs VDD @ 4 temperatures
10.3.5
Memory characteristics
RAM and hardware registers
Table 36: RAM and hardware registers
Conditions
Symbol
Parameter
Min
Unit
(2)
VRM
Data retention mode(1)
Halt mode (or reset)
VIT-max
V
(1) Minimum supply voltage without losing data stored in RAM (in halt mode or under reset)
or in hardware registers (only in halt mode). Guaranteed by design, not tested in production.
refer to Operating conditions for the value of VIT-max
(2)Refer to the Operating conditions section for the value of VIT-max
Flash program memory/data EEPROM memory
General conditions: TA = -40 to 125°C.
Table 37: Flash program memory/data EEPROM memory
Symbol Parameter
Conditions
Min(1) Typ Max
Unit
VDD Operating voltage (all modes,
fCPU ≤ 16 MHz
2.95
5.5
6.6
V
execution/write/erase)
tprog
Standard programming time
(including erase) for
6
ms
byte/word/block (1 byte/4
bytes/128 bytes)
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Symbol Parameter
Fast programming time for 1 block
Conditions
Min(1) Typ Max
Unit
3
3
3.3
3.3
ms
(128 bytes)
terase
NRW
Erase time for 1 block (128 bytes)
ms
Erase/write cycles(2)(program
memory)
TA = +85 °C
10 k
cycles
Erase/write cycles(data memory)(2) TA = +125 ° C
300 k 1M
20
tRET
Data retention (program memory) TRET = 55° C
after 10k erase/write cycles at TA
= +85 °C
years
Data retention (data memory) after TRET = 55° C
10k erase/write cycles at TA = +85
°C
20
1
Data retention (data memory) after TRET = 85° C
300 k erase/write cyclesat TA =
+125 °C
IDD
Supply current (Flash
programming or erasing for 1 to
128 bytes)
2
mA
(1) Data based on characterization results, not tested in production.
(2) The physical granularity of the memory is 4 bytes, so cycling is performed on 4 bytes
even when a write/erase operation addresses a single byte.
10.3.6
I/O port pin characteristics
General characteristics
Subject to general operating conditions for VDD and TA unless otherwise specified. All unused
pins must be kept at a fixed voltage: using the output mode of the I/O for example or an
external pull-up or pull-down resistor.
Table 38: I/O static characteristics
Symbol Parameter
Conditions
Min Typ
Max
Unit
VIL
Input low level
voltage
VDD = 5 V
-0.3
0.3 x VDD
V
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Symbol Parameter
Conditions
Min Typ
Max
Unit
VIH
Input high level
voltage
0.7 x
VDD
VDD + 0.3
V
V
Vhys
Rpu
Hysteresis(1)
Pull-up resistor
700
mV
kΩ
ns
VDD = 5 V, VIN = VSS
30
45
60
tR, tF
Rise and fall
time(10 % - 90 %)
Fast I/Os load = 50 pF
20 (2)
125 (2)
Standard and high sink
I/OsLoad = 50 pF
ns
Ilkg
Input leakage
current, analog
and digital
VSS ≤ VIN ≤ VDD
±1 (2)
µA
Ilkg ana Analog input
leakage current
VSS ≤ VIN ≤ VDD
±250 (2)
nA
µA
Ilkg(inj) Leakage current in Injection current ±4 mA
adjacent I/O(2)
±1(2)
(1) Hysteresis voltage between Schmitt trigger switching levels. Based on characterization
results, not tested in production.
(2) Data based on characterization results, not tested in production.
Figure 24: Typical VIL and VIH vs VDD @ 4 temperatures
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Figure 25: Typical pull-up resistance vs VDD @ 4 temperatures
Figure 26: Typical pull-up current vs VDD @ 4 temperatures
1. The pull-up is a pure resistor (slope goes through 0).
Table 39: Output driving current (standard ports)
Symbol Parameter Conditions Min
Max
Unit
VOL
Output low level with four pins IIO = 4 mA,
1(1)
V
sunk
VDD = 3.3 V
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Symbol Parameter
Output low level with eight
Conditions
Min
Max
Unit
IIO= 10 mA,
VDD = 5 V
2
pins sunk
VOH
Output high level with four
pins sourced
IIO = 4 mA,
VDD = 3.3 V
2(1)
2.4
V
Output high level with eight
pins sourced
IIO = 10 mA,
VDD = 5 V
(1) Data based on characterization results, not tested in production
Table 40: Output driving current (true open drain ports)
Symbol Parameter Conditions Max
IIO = 10 mA, VDD = 3.3 V 1.5(1)
Unit
VOL
Output low level with two pins
sunk
V
IIO = 10 mA, VDD = 5 V
IIO = 20 mA, VDD = 5 V
1
2(1)
(1) Data based on characterization results, not tested in production
Table 41: Output driving current (high sink ports)
Symbol Parameter
Conditions
Min
Max
Unit
VOL
Output low level with four pins IIO = 10 mA,
1.1(1)
V
sunk
VDD = 3.3 V
Output low level with eight pins IIO = 10 mA,
0.9
sunk
VDD = 5 V
Output low level with four pins IIO = 20 mA,
1.6(1)
sunk
VDD = 5 V
VOH
Output high level with four pins IIO = 10 mA,
1.9(1)
sourced
VDD = 3.3 V
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Max Unit
Symbol Parameter
Conditions
Min
Output high level with eight pins IIO = 10 mA,
3.8
sourced
VDD = 5 V
Output high level with four pins IIO = 20 mA,
2.9(1)
sourced
VDD = 5 V
(1) Data based on characterization results, not tested in production
10.3.7
Typical output level curves
The following figures show typical output level curves measured with output on a single pin.
Figure 27: Typ. VOL @ VDD = 5 V (standard ports)
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Figure 28: Typ. VOL @ VDD = 3.3 V (standard ports)
Figure 29: Typ. VOL @ VDD = 5 V (true open drain ports)
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Figure 30: Typ. VOL @ VDD = 3.3 V (true open drain ports)
Figure 31: Typ. VOL @ VDD = 5 V (high sink ports)
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Figure 32: Typ. VOL @ VDD = 3.3 V (high sink ports)
Figure 33: Typ. VDD - VOH @ VDD = 5 V (standard ports)
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Figure 34: Typ. VDD - VOH @ VDD = 3.3 V (standard ports)
Figure 35: Typ. VDD - VOH @ VDD = 5 V (high sink ports)
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Figure 36: Typ. VDD - VOH @ VDD = 3.3 V (high sink ports)
10.3.8
Reset pin characteristics
Subject to general operating conditions for VDD and TA unless otherwise specified.
Table 42: NRST pin characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VIL(NRST)
NRST input low
level voltage(1)
-0.3 V
0.3 x VDD
VIH(NRST)
VOL(NRST)
RPU(NRST)
tI FP(NRST)
tIN FP(NRST)
tOP(NRST)
NRST input high
level voltage (1)
IOL=2 mA
0.7 x VDD
VDD + 0.3
V
NRST output low
level voltage (1)
0.5
60
75
NRST pull-up
resistor(2)
30
40
kΩ
ns
μs
NRST input filtered
pulse(3)
NRST input not
filtered pulse(3)
500
20
NRST output pulse
(3)
(1) Data based on characterization results, not tested in production.
(2) The RPU pull-up equivalent resistor is based on a resistive transistor
(3) Data guaranteed by design, not tested in production.
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Figure 37: Typical NRST VIL and VIH vs VDD @ 4 temperatures
Figure 38: Typical NRST pull-up resistance vs VDD @ 4 temperatures
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Figure 39: Typical NRST pull-up current vs VDD @ 4 temperatures
The reset network shown inthe following figure protects the device against parasitic resets.
The user must ensure that the level on the NRST pin can go below the VIL max. level specified
in the I/O port pin characteristics section. Otherwise the reset is not taken into account
internally.
Figure 40: Recommended reset pin protection
STM8
VDD
RPU
External
reset
Internal reset
NRST
Filter
circuit
0.01 μF
(optional)
10.3.9
SPI serial peripheral interface
Unless otherwise specified, the parameters given in the following table are derived from tests
performed under ambient temperature, fMASTER frequency and VDD supply voltage conditions.
tMASTER = 1/fMASTER
.
Refer to I/O port characteristics for more details on the input/output alternate function
characteristics (NSS, SCK, MOSI, MISO).
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Electrical characteristics
Symbol
STM8S105xx
Table 43: SPI characteristics
Conditions
Parameter
Min
Max
Unit
fSCK
1
SPI clock
frequency
Master mode
0
8
MHz
tc(SCK)
Slave mode
0
6
tr(SCK)
tf(SCK)
SPI clock rise
and fall time
Capacitive load: C = 30 pF
25
ns
(1)
tsu(NSS)
NSS setup time Slave mode
NSS hold time Slave mode
4 x
tMASTER
ns
ns
(1)
th(NSS)
70
(1)
tw(SCKH)
SCK high and
low time
Master mode
tSCK/2 -
15
tSCK/2 +
15
ns
(1)
tw(SCKL)
(1)
tsu(MI)
Data input
setup time
Master mode
Slave mode
5
ns
ns
ns
ns
ns
ns
(1)
tsu(SI)
Data input
setup time
5
(1)
th(MI)
Data input hold Master mode
time
7
(1)
th(SI)
Data input hold Slave mode
time
10
(1) (2)
ta(SO)
Data output
access time
Slave mode
Slave mode
3 x
tMASTER
(1) (3)
tdis(SO)
Data output
disable time
25
(1)
tv(SO)
Data output
valid time
Slave mode
73
36
ns
ns
(after enable edge)
(1)
tv(MO)
Data output
valid time
Master mode
(after enable edge)
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Electrical characteristics
Symbol
Parameter
Conditions
Min
Max
Unit
(1)
th(SO)
Data output
hold time
Slave mode
28
ns
(after enable edge)
(1)
th(MO)
Master mode
12
ns
(after enable edge)
(1) Values based on design simulation and/or characterization results, and not tested in
production.
(2) Min time is for the minimum time to drive the output and the max time is for the maximum
time to validate the data.
(3) Min time is for the minimum time to invalidate the output and the max time is for the
maximum time to put the data in Hi-Z.
Figure 41: SPI timing diagram - slave mode and CPHA = 0
NSS input
t
t
t
h(NSS)
SU(NSS)
c(SCK)
CPHA=0
CPOL=0
t
t
w(SCKH)
w(SCKL)
CPHA=0
CPOL=1
t
t
t
t
t
dis(SO)
v(SO)
r(SCK)
f(SCK)
h(SO)
t
a(SO)
MISO
MSB O UT
BIT6 OUT
BIT1 IN
LSB OUT
OUT PUT
t
su(SI)
MOSI
M SB IN
LSB IN
INPUT
t
h(SI)
ai14134
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Electrical characteristics
STM8S105xx
Figure 42: SPI timing diagram - slave mode and CPHA = 1(1)
NSS input
t
t
t
h(NSS)
SU(NSS)
t
c(SCK)
CPHA=1
CPOL=0
w(SCKH)
CPHA=1
CPOL=1
t
w(SCKL)
t
t
r(SCK)
f(SCK)
t
t
t
v(SO)
h(SO)
dis(SO)
t
a(SO)
MISO
MSB O UT
BIT6 OUT
LSB OUT
OUT PUT
t
t
su(SI)
h(SI)
MOSI
M SB IN
BIT1 IN
LSB IN
INPUT
ai14135
1. Measurement points are made at CMOS levels: 0.3 VDD and 0.7 VDD
.
Figure 43: SPI timing diagram - master mode(1)
High
NSS input
t
c(SCK)
CPHA=0
CPOL=0
CPHA=0
CPOL=1
CPHA=1
CPOL=0
CPHA=1
CPOL=1
t
t
t
t
w(SCKH)
w(SCKL)
r(SCK)
f(SCK)
t
su(MI)
MISO
MSBIN
t
BIT6 IN
LSB IN
INPUT
h(MI)
MOSI
M SB OUT
BIT1 OUT
LSB OUT
OUTUT
t
t
v(MO)
h(MO)
ai14136
1. Measurement points are made at CMOS levels: 0.3 VDD and 0.7 VDD
.
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Electrical characteristics
10.3.10 I2C interface characteristics
Table 44: I2C characteristics
Standard mode I2C Fast mode I2C(1) Unit
Symbol Parameter
Min(2)
Max(2)
Min(2)
Max(2)
tw(SCLL)
tw(SCLH)
tsu(SDA)
th(SDA)
SCL clock low time
4.7
1.3
μs
μs
ns
SCL clock high time
SDA setup time
4.0
250
0(3)
0.6
100
0(4)
SDA data hold time
900(3) ns
tr(SDA)
tr(SCL)
SDA and SCL rise time
1000
300
300
300
ns
tf(SDA)
tf(SCL)
SDA and SCL fall time
ns
μs
μs
μs
μs
pF
th(STA)
START condition hold time
4.0
4.7
4.0
4.7
0.6
0.6
0.6
1.3
tsu(STA)
Repeated START condition
setup time
tsu(STO)
STOP condition setup time
tw(STO:STA) STOP to START condition time
(bus free)
Cb
Capacitive load for each bus line
400
400
(1)
f
, must be at least 8 MHz to achieve max fast I2C speed (400kHz).
MASTER
(2) Data based on standard I2C protocol requirement, not tested in production.
(3) The maximum hold time of the start condition has only to be met if the interface does not stretch the
low time.
(4) The device must internally provide a hold time of at least 300 ns for the SDA signal in order to bridge
the undefined region of the falling edge of SCL.
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Electrical characteristics
STM8S105xx
Figure 44: Typical application with I2C bus and timing diagram (1)
V
V
DD
DD
STM8S105xx
SDA
SCL
I²C bus
START REPEATED
START
START
t
su(STA)
SDA
t
t
t
r(SDA)
f(SDA)
su(SDA)
t
su(STA:STO)
STOP
t
t
t
w(SCKL)
h(SDA)
h(STA)
SCL
t
t
t
su(STO)
r(SCK)
t
f(SCK)
w(SCKH)
ai15385
1. Measurement points are made at CMOS levels: 0.3 x VDD and 0.7 x VDD
10.3.11 10-bit ADC characteristics
Subject to general operating conditions for VDDA, fMASTER, and TA unless otherwise specified.
Table 45: ADC characteristics
Symbol Parameter
Conditions
Min
Typ Max
Unit
fADC
ADC clock frequency
VDDA =2.95 to 5.5 V 1
4
MHz
VDDA =4.5 to 5.5 V
1
6
VDDA
VREF+
VREF-
VAIN
Analog supply
3
5.5
V
V
V
V
V
Positive reference voltage
Negative reference voltage
Conversion voltage range(2)
2.75(1)
VDDA
0.5(1)
V SSA
V SSA
V DDA
Devices with
external
VREF-
VREF+
VREF+/VREF- pins
CADC
Internal sample and hold
capacitor
3
pF
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STM8S105xx
Electrical characteristics
Symbol Parameter
Conditions
Min
Typ Max
Unit
(2)
tS
Sampling time
fADC = 4 MHz
0.75
µs
fADC = 6 MHz
0.5
tSTAB
Wakeup time from standby
µs
7
tCONV
Total conversion time
(including sampling time,
10-bit resolution)
fADC = 4 MHz
fADC = 6 MHz
3.5
2.33
14
µs
µs
1/fADC
(1) Data guaranteed by design, not tested in production..
(2) During the sample time the input capacitance CAIN (3 pF max) can be charged/discharged
by the external source. The internal resistance of the analog source must allow the
capacitance to reach its final voltage level within tS. After the end of the sample time tS,
changes of the analog input voltage have no effect on the conversion result. Values for the
sample clock tS depend on programming.
Table 46: ADC accuracy with RAIN < 10 kΩ , VDDA= 5 V
Symbol Parameter
Conditions
Typ
Max(1) Unit
|ET|
|EO|
|EG|
Total unadjusted error(2)
fADC = 2 MHz
1
2.5
3
LSB
fADC = 4 MHz
fADC = 6 MHz
fADC = 2 MHz
fADC = 4 MHz
fADC = 6 MHz
fADC = 2 MHz
fADC = 4 MHz
1.4
1.6
0.6
1.1
1.2
0.2
0.6
3.5
2
Offset error(2)
2.5
2.5
2
Gain error(2)
2.5
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Electrical characteristics
STM8S105xx
Symbol Parameter
Conditions
Typ
Max(1) Unit
fADC = 6 MHz
0.8
2.5
|ED|
Differential linearity error(2)
fADC = 2 MHz
fADC = 4 MHz
fADC = 6 MHz
fADC = 2 MHz
fADC = 4 MHz
fADC = 6 MHz
0.7
0.7
0.8
0.6
0.6
0.6
1.5
1.5
1.5
1.5
1.5
1.5
|EL|
Integral linearity error(2)
(1) Data based on characterisation results for LQFP80 device with VREF+/VREF-, not tested
in production.
(2) ADC accuracy vs. negative injection current: Injecting negative current on any of the
analog input pins should be avoided as this significantly reduces the accuracy of the
conversion being performed on another analog input. It is recommended to add a Schottky
diode (pin to ground) to standard analog pins which may potentially inject negative current.
Any positive injection current within the limits specified for IINJ(PIN) and ΣIINJ(PIN) in the I/O
port pin characteristics section does not affect the ADC accuracy.
Table 47: ADC accuracy with RAIN < 10 kΩ RAIN, VDDA = 3.3 V
Symbol Parameter
Conditions
Typ
Max(1) Unit
|ET|
|EO|
|EG|
|ED|
Total unadjusted error(2)
fADC = 2 MHz
1.1
2
LSB
fADC = 4 MHz
fADC = 2 MHz
fADC = 4 MHz
fADC = 2 MHz
fADC = 4 MHz
fADC = 2 MHz
1.6
0.7
1.3
0.2
0.5
0.7
2.5
1.5
2
Offset error(2)
Gain error (2)
1.5
2
Differential linearity error(2)
1
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Electrical characteristics
Symbol Parameter
Conditions
Typ
Max(1) Unit
fADC = 4 MHz
0.7
1
|EL|
Integral linearity error(2)
fADC = 2 MHz
fADC = 4 MHz
0.6
0.6
1.5
1.5
(1) Data based on characterisation results for LQFP80 device with VREF+/VREF-, not tested
in production.
(2) ADC accuracy vs. negative injection current: Injecting negative current on any of the
analog input pins should be avoided as this significantly reduces the accuracy of the
conversion being performed on another analog input. It is recommended to add a Schottky
diode (pin to ground) to standard analog pins which may potentially inject negative current.
Any positive injection current within the limits specified for IINJ(PIN) and ΣIINJ(PIN) in I/O port
pin characteristics does not affect the ADC accuracy.
Figure 45: ADC accuracy characteristics
1. Example of an actual transfer curve.
2. The ideal transfer curve
3. End point correlation line
ET = Total unadjusted error: maximum deviation between the actual and the ideal transfer
curves.
EO = Offset error: deviation between the first actual transition and the first ideal one.
EG = Gain error: deviation between the last ideal transition and the last actual one.
ED = Differential linearity error: maximum deviation between actual steps and the ideal
one.
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Electrical characteristics
STM8S105xx
EL = Integral linearity error: maximum deviation between any actual transition and the end
point correlation line.
Figure 46: Typical application with ADC
V
STM8
DD
V
T
V
0.6 V
R
AIN
AIN
AINx
10-bit A/D
conversion
V
T
0.6 V
I
L
± 1 µA
C
C
AIN
ADC
10.3.12 EMC characteristics
Susceptibility tests are performed on a sample basis during product characterization.
10.3.12.1 Functional EMS (electromagnetic susceptibility)
While executing a simple application (toggling 2 LEDs through I/O ports), the product is
stressed by two electromagnetic events until a failure occurs (indicated by the LEDs).
FESD: Functional electrostatic discharge (positive and negative) is applied on all pins of
the device until a functional disturbance occurs. This test conforms with the IEC 61000-4-2
standard.
•
FTB: A burst of fast transient voltage (positive and negative) is applied to VDD and VSS
through a 100 pF capacitor, until a functional disturbance occurs. This test conforms with
the IEC 61000-4-4 standard.
•
A device reset allows normal operations to be resumed. The test results are given in the table
below based on the EMS levels and classes defined in application note AN1709 (EMC design
guide for STMicrocontrollers).
10.3.12.2 Designing hardened software to avoid noise problems
EMC characterization and optimization are performed at component level with a typical
application environment and simplified MCU software. It should be noted that good EMC
performance is highly dependent on the user application and the software in particular.
Therefore it is recommended that the user applies EMC software optimization and
prequalification tests in relation with the EMC level requested for his application.
Prequalification trials
Most of the common failures (unexpected reset and program counter corruption) can be
recovered by applying a low state on the NRST pin or the oscillator pins for 1 second.
To complete these trials, ESD stress can be applied directly on the device, over the range of
specification values. When unexpected behavior is detected, the software can be hardened
to prevent unrecoverable errors occurring. See application note AN1015 (Software techniques
for improving microcontroller EMC performance).
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Electrical characteristics
Table 48: EMS data
Conditions
Symbol Parameter
Level/
class
VFESD Voltage limits to be
applied on any I/O pin to
induce a functional
2/B (1)
VDD = 3.3 V, TA = 25 °C, fMASTER = 16 MHz
(HSI clock), conforming to IEC 61000-4-2
disturbance
VEFTB
Fast transient voltage
burst limits to be applied
through 100 pF on VDD
and VSS pins to induce a
functional disturbance
4/A (1)
VDD= 3.3 V, TA = 25 °C ,fMASTER = 16 MHz
(HSI clock),conforming to IEC 61000-4-4
(1)Data obtained with HSI clock configuration, after applying HW recommendations described
in AN2860 (EMC guidelines for STM8S microcontrollers).
10.3.12.3 Electromagnetic interference (EMI)
Emission tests conform to the IEC61967-2 standard for test software, board layout and pin
loading.
Table 49: EMI data
Symbol Parameter Conditions
Unit
(1)
General
conditions
Monitored
frequency
band
Max fHSE/fCPU
8 MHz/ 8
MHz
8 MHz/ 16
MHz
SEMI
Peak level VDD = 5 V,
TA = +25 °C,
0.1 MHz to
30 MHz
13
23
14
19
-4
dBµV
LQFP48
package
conforming to
IEC61967-2
30 MHz to
130 MHz
130 MHz to 1 -4
GHz
SAE EMI
level
2
1.5
—
(1) Data based on characterization results, not tested in production.
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Electrical characteristics
STM8S105xx
10.3.12.4 Absolute maximum ratings (electrical sensitivity)
Based on two different tests (ESD and LU) using specific measurement methods, the product
is stressed in order to determine its performance in terms of electrical sensitivity. For more
details, refer to the application note AN1181.
10.3.12.5 Electrostatic discharge (ESD)
Electrostatic discharges (3 positive then 3 negative pulses separated by 1 second) are applied
to the pins of each sample according to each pin combination. The sample size depends on
the number of supply pins in the device (3 parts*(n+1) supply pin). This test conforms to the
JESD22-A114A/A115A standard. For more details, refer to the application note AN1181.
Table 50: ESD absolute maximum ratings
Symbol
Ratings
Conditions
Class Maximum Unit
value(1)
VESD(HBM) Electrostatic discharge
TA = +25°C,
A
2000
V
voltage (Human body model) conforming to
JESD22-A114
VESD(CDM) Electrostatic discharge
voltage (Charge device
model)
TA=+25°C, conforming IV
to JESD22-C101
1000
V
(1) Data based on characterization results, not tested in production
10.3.12.6 Static latch-up
Two complementary static tests are required on 10 parts to assess the latch-up performance:
A supply overvoltage (applied to each power supply pin)
•
A current injection (applied to each input, output and configurable I/O pin) are performed
on each sample.
•
This test conforms to the EIA/JESD 78 IC latch-up standard. For more details, refer to the
application note AN1181.
Table 51: Electrical sensitivities
Symbol Parameter
LU Static latch-up class
Conditions
Class(1)
TA = +25 °C
A
TA = +85 °C
A
A
TA = +125 °C
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Electrical characteristics
(1) Class description: A Class is an STMicroelectronics internal specification. All its limits
are higher than the JEDEC specifications, that means when a device belongs to class A it
exceeds the JEDEC standard. B class strictly covers all the JEDEC criteria (international
standard).
DocID14771 Rev 9
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Package characteristics
STM8S105xx
11
Package characteristics
11.1
Ecopack packages
To meet environmental requirements, ST offers these devices in different grades of ECOPACK®
packages, depending on their level of environmental compliance. ECOPACK® specifications,
grade definitions and product status are available at www.st.com. ECOPACK® is an ST
trademark.
11.2
Package mechanical data
11.2.1
48-pin LQFP package mechanical data
Figure 47: 48-pin low profile quad flat package (7 x 7)
D
ccc
C
D1
D3
A
A2
25
36
24
37
L1
b
E3 E1
E
48
L
13
A1
K
Pin 1
identification
1
12
c
5B_ME
Table 52: 48-pin low profile quad flat package mechanical data
Dim.
mm
Min
inches(1)
Min
Typ
Max
Typ
Max
A
1.600
0.0630
A1
A2
b
0.050
1.350
0.170
0.150
1.450
0.270
0.0020
0.0531
0.0067
0.0059
0.0571
0.0106
1.400
0.220
0.0551
0.0087
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Package characteristics
Dim.
mm
Min
inches(1)
Min
Typ
Max
Typ
Max
c
0.090
8.800
6.800
0.200
0.0035
0.3465
0.2677
0.0079
D
9.000
7.000
5.500
9.000
7.000
5.500
0.500
0.600
1.000
3.5°
9.200
7.200
0.3543
0.2756
0.2165
0.3543
0.2756
0.2165
0.0197
0.0236
0.0394
3.5°
0.3622
0.2835
D1
D3
E
8.800
6.800
9.200
7.200
0.3465
0.2677
0.3622
0.2835
E1
E3
e
L
0.450
0.0°
0.750
0.0177
0.0°
0.0295
L1
k
7.0°
7.0°
ccc
0.080
0.0031
(1) Values in inches are converted from mm and rounded to 4 decimal digits
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Package characteristics
STM8S105xx
11.2.2
44-pin LQFP package mechanical data
Figure 48: 44-pin low profile quad flat package
D
ccc
C
D1
D3
A
A2
23
33
22
34
L1
b
E3 E1
E
44
L
12
A1
K
Pin 1
identification
1
11
c
4Y_ME
Table 53: 44-pin low profile quad flat package mechanical data
Dim.
mm
Min
inches(1)
Min
Typ
Max
Typ
Max
A
1.600
0.0630
A1
A2
b
0.050
1.350
0.300
0.090
11.800
9.800
0.150
1.450
0.450
0.200
12.200
10.200
0.0020
0.0531
0.0118
0.0035
0.4646
0.3858
0.0059
0.0571
0.0177
0.0079
0.4803
0.4016
1.400
0.370
0.0551
0.0146
c
D
12.000
10.000
8.000
0.4724
0.3937
0.3150
0.4724
D1
D3
E
11.800
12.000
12.200
0.4646
0.4803
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Package characteristics
Dim.
mm
Min
inches(1)
Min
Typ
Max
Typ
Max
E1
E3
e
9.800
10.000
10.200
0.3858
0.3937
0.4016
8.000
0.800
0.600
1.000
3.5°
0.3150
0.0315
0.0236
0.0394
3.5°
L
0.450
0.0°
0.750
0.0177
0.0°
0.0295
L1
k
7.0°
7.0°
ccc
0.100
0.0039
(1) Values in inches are converted from mm and rounded to 4 decimal digits
11.2.3
32-pin LQFP package mechanical data
Figure 49: 32-pin low profile quad flat package (7 x 7)
ccc
C
D
D1
D3
A
A2
24
17
16
25
32
L1
b
E3
E1 E
9
L
Pin 1
identification
A1
K
1
8
c
5V_ME
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Package characteristics
Dim.
STM8S105xx
Table 54: 32-pin low profile quad flat package mechanical data
mm
Min
inches(1)
Typ
Max
Min
Typ
Max
A
1.600
0.0630
A1
A2
b
0.050
1.350
0.300
0.090
8.800
6.800
0.150
1.450
0.450
0.200
9.200
7.200
0.0020
0.0531
0.0118
0.0035
0.3465
0.2677
0.0059
0.0571
0.0177
0.0079
0.3622
0.2835
1.400
0.370
0.0551
0.0146
c
D
9.000
7.000
5.600
9.000
7.000
5.600
0.800
0.600
1.000
3.5°
0.3543
0.2756
0.2205
0.3543
0.2756
0.2205
0.0315
0.0236
0.0394
3.5°
D1
D3
E
8.800
6.800
9.200
7.200
0.3465
0.2677
0.3622
0.2835
E1
E3
e
L
0.450
0.0°
0.750
0.0177
0.0°
0.0295
L1
k
7.0°
7.0°
ccc
0.100
0.0039
(1) Values in inches are converted from mm and rounded to 4 decimal digits
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Package characteristics
11.2.4
32-lead VFQFPN package mechanical data
Figure 50: 32-lead very thin fine pitch quad flat no-lead package (5 x 5)
Seating plane
C
ddd
C
A
A1
A3
D
e
16
9
17
8
b
E
E2
24
1
L
32
Pin # 1 ID
R = 0.30
D2
L
Bottom view
42_ME
Note:
1. The exposed pad must be soldered to the PCB. It is recommended to connect it to
VSS.
Table 55: 32-lead very thin fine pitch quad flat no-lead package mechanical data
Dim.
mm
Min
inches(1)
Min
Typ
Max
Typ
Max
A
0.80
0
0.90
1.00
0.0315
0.0354
0.0394
A1
A3
b
0.02
0.20
0.25
5.00
0.05
0.0008
0.0079
0.0098
0.1969
0.0020
0.18
4.85
0.30
5.15
0.0071
0.1909
0.0118
0.2028
D
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Package characteristics
Dim.
STM8S105xx
mm
Min
inches(1)
Min
Typ
Max
Typ
Max
D2
E
3.20
4.85
3.20
3.45
3.70
0.1260
0.1909
0.1260
0.1457
5.00
3.45
0.50
0.40
5.15
3.70
0.1969
0.1358
0.0197
0.0157
0.2028
0.1457
E2
e
L
0.30
0.50
0.08
0.0118
0.0197
0.0031
ddd
(1) Values in inches are converted from mm and rounded to 4 decimal digits.
11.2.5
32-lead UFQFPN package mechanical data
Figure 51: 32-lead ultra thin fine pitch quad flat no-lead package (5 x 5)
AOB8_ME
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Package characteristics
Table 56: 32-lead ultra thin fine pitch quad flat no-lead package mechanical data
Dim.
mm
Min
inches(1)
Min
Typ
Max
Typ
Max
A
0.50
0
0.55
0.6
0.0197
0
0.0217
0.0236
A1
A3
b
0.02
0.20
0.25
5.00
3.45
5.00
3.45
0.50
0.40
0.05
0.0008
0.0079
0.0098
0.1969
0.1358
0.1969
0.1358
0.0197
0.0157
0.0020
0.18
4.85
3.20
4.85
3.20
0.30
5.15
3.70
5.15
3.70
0.0071
0.1909
0.1260
0.1909
0.1260
0.0118
0.2028
0.1457
0.2028
0.1457
D
D2
E
E2
e
L
0.30
0.50
0.08
0.0118
0.0197
0.0031
ddd
(1) Values in inches are converted from mm and rounded to 4 decimal digits.
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Package characteristics
STM8S105xx
11.2.6
SDIP32 package mechanical data
Figure 52: 32-lead shrink plastic DIP (400 ml) package
E
E1
A2
A1
A
L
B1
B
e
eA
eB
C
D
32
1
17
16
76_ME
Table 57: 32-lead shrink plastic DIP (400 ml) package mechanical data
Dim.
mm
Min
inches(1)
Min
Typ
Max
Typ
Max
A
3.556
0.508
3.048
0.356
0.762
0.203
27.430
9.906
7.620
3.759
5.080
0.1400
0.0200
0.1200
0.0140
0.0300
0.0079
1.0799
0.3900
0.3000
0.1480
0.2000
A1
A2
B
3.556
0.457
1.016
0.254
27.940
10.410
8.890
4.572
0.584
1.397
0.356
28.450
11.050
9.398
0.1400
0.0180
0.0400
0.0100
1.1000
0.4098
0.3500
0.1800
0.0230
0.0550
0.0140
1.1201
0.4350
0.3700
B1
C
D
E
E1
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Package characteristics
Dim.
mm
Min
inches(1)
Min
Typ
Max
Typ
Max
e
1.778
0.0700
eA
eB
L
10.160
0.4000
12.700
3.810
0.5000
0.1500
2.540
3.048
0.1000
0.1200
(1) Values in inches are converted from mm and rounded to 4 decimal digits
11.3
Thermal characteristics
The maximum chip junction temperature (TJ max) must never exceed the values given in
Operating conditions
The maximum chip-junction temperature, TJmax, in degrees Celsius, may be calculated using
the following equation:
TJmax = TAmax + (PDmax x ΘJA)
Where:
TAmax is the maximum ambient temperature in °C
•
ΘJA is the package junction-to-ambient thermal resistance in ° C/W
•
PDmax is the sum of PINTmax and PI/Omax (PDmax = PINTmax + PI/Omax
)
•
PINTmax is the product of IDD andVDD, expressed in Watts. This is the maximum chip internal
power.
•
PI/Omax represents the maximum power dissipation on output pinsWhere:PI/Omax =Σ (VOL*IOL
+ Σ((VDD-VOH)*IOH), taking into account the actual VOL/IOL and VOH/IOH of the I/Os at low
and high level in the application.
)
•
Table 58: Thermal characteristics(1)
Symbol
ΘJA
Parameter
Value
Unit
Thermal resistance junction-ambient
LQFP 48 - 7 x 7 mm
57
°C/W
ΘJA
Thermal resistance junction-ambient
LQFP 44 - 10 x 10 mm
54
°C/W
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Package characteristics
STM8S105xx
Symbol
Parameter
Value
Unit
ΘJA
Thermal resistance junction-ambient
LQFP 32 - 7 x 7 mm
60
°C/W
ΘJA
Thermal resistance junction-ambient
VQFPN 32 - 5 x 5 mm
22
°C/W
1. Thermal resistances are based on JEDEC JESD51-2 with 4-layer PCB in a natural
convection environment.
11.3.1
11.3.2
Reference document
JESD51-2 integrated circuits thermal test method environment conditions - natural convection
(still air). Available from www.jedec.org.
Selecting the product temperature range
When ordering the microcontroller, the temperature range is specified in the order code.
The following example shows how to calculate the temperature range needed for a given
application.
Assuming the following application conditions:
Maximum ambient temperature TAmaz = 82 °C (measured according to JESD51-2)
•
IDDmax = 15 mA, VDD = 5.5 V
•
Maximum 8 standard I/Os used at the same time in output at low level with IOL = 10 mA,
VOL= 2 V
•
Maximum 4 high sink I/Os used at the same time in output at low level with IOL = 20 mA,
VOL= 1.5 V
•
Maximum 2 true open drain I/Os used at the same time in output at low level with IOL
20 mA, VOL= 2 V
=
•
PINTmax = 15 mA x 5.5 V = 82.5 mW
PIOmax = (10 mA x 2 V x 8 )+(20 mA x 2 V x 2)+(20 mA x 1.5 V x 4) = 360 mW
This gives: PINTmax = 82.5 mW and PIOmax 360 mW:
PDmax = 82.5 mW + 360 mW
Thus: PDmax = 443 mW
TJmax for LQFP32 can be calculated as follows, using the thermal resistance ΘJA
TJmax = 75° C + (59° C/W x 464 mW) = 75°C + 27°C = 102° C
:
This is within the range of the suffix 6 version parts (-40 < TJ < 106° C). In this case, parts
must be ordered at least with the temperature range suffix 6.
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Ordering information
12
Ordering information
Figure 53: STM8S105xx access line ordering information scheme
Example:
C
K
4
T
TR
S
6
STM8
105
Product class
Family type
S = Standard
Sub-family type
105 = access line STM8S105x
Pin count
K = 32 pins
S = 44 pins
C = 48 pins
Program memory size
4 = 16 Kbytes
6 = 32 Kbytes
Package type
B = SDIP
T = LQFP
U = VQFPN
Temperature range
3 = -40 °C to 125 °C
6 = -40 °C to 85 °C
Package pitch
No character = 0.5 mm
C = 0.8 mm
Packing
No character = Tray or tube
TR = Tape and reel
1. For a list of available options (e.g. memory size, package) and orderable part numbers or
for further information on any aspect of this device, please go to www.st.com or contact
the ST sales office nearest to you.
12.1
STM8S105 FASTROM microcontroller option list
(last update: March 2010)
Customer
Address
.............................................................................................
.............................................................................................
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Ordering information
STM8S105xx
Contact
.............................................................................................
.............................................................................................
Phone no.
Reference FASTROM codea .............................................................................................
Preferable format for programing code is .Hex (.s19 is accepted)
If data EEPROM programing is required, a seperate file must be sent with the requested data.
Important: See the option byte section in the datasheet for authorized option byte
combinations and a detailed explanation.
Device type/memory size/package (check only one option)
FASTROM device
VFQFPN32
LQFP32
16 Kbyte
32 Kbyte
[ ] STM8S105K4
[ ] STM8S105K4
[ ] STM8S105S4
[ ] STM8S105C4
[ ] STM8S105K6
[ ] STM8S105K6
[ ] STM8S105S6
[ ] STM8S105C6
LQFP44
LQFP48
Conditioning (check only one option)
[ ] Tape & reel or [ ] Tray
Special marking (check only one option)
[ ] No [ ] Yes
Authorized characters are letters, digits, '.', '-', '/' and spaces only. Maximum character counts
are:
VFQFPN32: 1 line of 7 characters max: "_ _ _ _ _ _ _"
LQFP32: 2 lines of 7 characters max: "_ _ _ _ _ _ _" and "_ _ _ _ _ _ _"
LQFP44: 2 lines of 7 characters max: "_ _ _ _ _ _ _" and "_ _ _ _ _ _ _"
LQFP48: 2 lines of 8 characters max: "_ _ _ _ _ _ _" and "_ _ _ _ _ _ _"
Temperature range
[ ] -40°C to +85°C or [ ] -40°C to +125°C
Padding value for unused program memory (check only one option)
[ ]0xFF
[ ]0x83
[ ]0x75
Fixed value
TRAP instruction opcode
Illegal opcode (causes a reset when executed)
OPT0 memory readout protection (check only one option)
[ ] Disable or [ ] Enable
OPT1 user boot code area (UBC)
0x(_ _) fill in the hexadecimal value, refering to the datasheet and the binary format below.
FASTROM code name is assigned by STMicroelectronics.
a
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Ordering information
UBC, bit0
UBC bit1
UBC bit2
UBC bit3
UBC bit4
UBC bit5
UBC bit6
UBC bit7
[ ] 0: Reset
[ ] 1: Set
[ ] 0: Reset
[ ] 1: Set
[ ] 0: Reset
[ ] 1: Set
[ ] 0: Reset
[ ] 1: Set
[ ] 0: Reset
[ ] 1: Set
[ ] 0: Reset
[ ] 1: Set
[ ] 0: Reset
[ ] 1: Set
[ ] 0: Reset
[ ] 1: Set
OPT2 alternate function remapping
AFR0
[ ] 0: Remapping option inactive. Default alternate functions used.
Refer to pinout description.
(check only one option)
[ ] 1: Port D3 alternate function = ADC_ETR
AFR1
[ ] 0: Remapping option inactive. Default alternate functions used.
Refer to pinout description.
(check only one option)
[ ] 1: Port A3 alternate function = TIM3_CH1, port D2 alternate
function = TIM2_CH3.
AFR2
[ ] 0: Remapping option inactive. Default alternate functions used.
Refer to pinout description.
(check only one option)
[ ] 1: Port D0 alternate function = CLK_CCO.
Note: If both AFR2 and AFR3 are activated, AFR2 option
has priority over AFR3.
AFR3
[ ] 0: Remapping option inactive. Default alternate functions used.
Refer to pinout description.
(check only one option)
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Ordering information
STM8S105xx
[ ] 1: Port D0 alternate function = TIM1_BKIN.
AFR4
[ ] 0: Remapping option inactive. Default alternate functions used.
Refer to pinout description.
(check only one option)
[ ] 1: Port D7 alternate function = TIM1_CH4.
AFR5
[ ] 0: Remapping option inactive. Default alternate functions used.
Refer to pinout description.
(check only one option)
[ ] 1: Port B3 alternate function = TIM1_ETR, port B2 alternate
function = TIM1_NCC3, port B1 alternate function = TIM1_CH2N,
port B0 alternate function = TIM1_CH1N.
AFR6
[ ] 0: Remapping option inactive. Default alternate functions used.
Refer to pinout description
(check only one option)
[ ] 1: Port B5 alternate function = I2C_SDA, port B4 alternate
function = I2C_SCL.
AFR7
[ ] 0: Remapping option inactive. Default alternate functions used.
Refer to pinout description.
(check only one option)
[ ] 1: Port D4 alternate function = BEEP.
OPT3 watchdog
WWDG_HALT
[ ] 0: No reset generated on halt if WWDG active.
[ ] 1: Reset generated on halt if WWDG active.
(check only one option)
WWDG_HW
[ ] 0: WWDG activated by software.
[ ] 1: WWDG activated by hardware.
(check only one option)
IWDG_HW
[ ] 0: IWDG activated by software.
[ ] 1: IWDG activated by hardware.
(check only one option)
LSI_EN
[ ] 0: LSI clock is not available as CPU clock source.
[ ] 1: LSI clock is available as CPU clock source.
(check only one option)
HSITRIM
[ ] 0: 3-bit trimming supported in CLK_HSITRIMR
register.
(check only one option)
[ ] 1: 4-bit trimming supported in CLK_HSITRIMR
register.
OPT4 wakeup
PRSC
[ ] for 16 MHz to 128 kHz prescaler.
[ ] for 8 MHz to 128 kHz prescaler.
[ ] for 4 MHz to 128 kHz prescaler.
(check only one option)
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Ordering information
CKAWUSEL
[ ] 0: LSI clock source selected for AWU.
(check only one option)
[ ] 1: HSE clock with prescaler selected as clock source
for AWU.
EXTCLK
[ ] 0: External crystal connected to OSCIN/OSCOUT.
[ ] 1: External clock signal on OSCIN.
(check only one option)
OPT5 crystal oscillator stabilization HSECNT (check only one option)
[ ] 2048 HSE cycles
[ ] 128 HSE cycles
[ ] 8 HSE cycles
[ ] 0.5 HSE cycles
OPT6 is reserved
OPT7 is reserved
OPTBL bootloader option byte (check only one option)
Refer to the UM0560 (STM8L/S bootloader manual) for more details.
[ ] 00h
[ ] 55h
Comments:
...........................................................................................................
Supply operating range ...........................................................................................................
in the application:
Notes:
...........................................................................................................
...........................................................................................................
...........................................................................................................
Date:
Signature:
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STM8 development tools
STM8S105xx
13
STM8 development tools
Development tools for the STM8 microcontrollers include the full-featured STice emulation
system supported by a complete software tool package including C compiler, assembler and
integrated development environment with high-level language debugger. In addition, the
STM8 is to be supported by a complete range of tools including starter kits, evaluation boards
and a low-cost in-circuit debugger/programmer.
13.1
Emulation and in-circuit debugging tools
The STice emulation system offers a complete range of emulation and in-circuit debugging
features on a platform that is designed for versatility and cost-effectiveness. In addition, STM8
application development is supported by a low-cost in-circuit debugger/programmer.
The STice is the fourth generation of full featured emulators from STMicroelectronics. It offers
new advanced debugging capabilities including profiling and coverage to help detect and
eliminate bottlenecks in application execution and dead code when fine tuning an application.
In addition, STice offers in-circuit debugging and programming of STM8 microcontrollers via
the STM8 single wire interface module (SWIM), which allows non-intrusive debugging of an
application while it runs on the target microcontroller.
For improved cost effectiveness, STice is based on a modular design that allows you to order
exactly what you need to meet your development requirements and to adapt your emulation
system to support existing and future ST microcontrollers.
STice key features
Occurrence and time profiling and code coverage (new features)
•
Advanced breakpoints with up to 4 levels of conditions
•
Data breakpoints
•
Program and data trace recording up to 128 KB records
•
Read/write on the fly of memory during emulation
•
In-circuit debugging/programming via SWIM protocol
•
8-bit probe analyzer
•
1 input and 2 output triggers
•
Power supply follower managing application voltages between 1.62 to 5.5 V
•
Modularity that allows you to specify the components you need to meet your development
requirements and adapt to future requirements
•
Supported by free software tools that include integrated development environment (IDE),
programming software interface and assembler for STM8.
•
13.2
Software tools
STM8 development tools are supported by a complete, free software package from
STMicroelectronics that includes ST Visual Develop (STVD) IDE and the ST Visual
Programmer (STVP) software interface. STVD provides seamless integration of the Cosmic
and Raisonance C compilers for STM8, which are available in a free version that outputs up
to 16 Kbytes of code.
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STM8 development tools
13.2.1
STM8 toolset
STM8 toolset with STVD integrated development environment and STVP programming
software is available for free download at www.st.com/mcu. This package includes:
ST Visual Develop – Full-featured integrated development environment from ST, featuring
Seamless integration of C and ASM toolsets
•
Full-featured debugger
•
Project management
•
Syntax highlighting editor
•
Integrated programming interface
•
Support of advanced emulation features for STice such as code profiling and coverage
•
ST Visual Programmer (STVP) – Easy-to-use, unlimited graphical interface allowing read,
write and verify of your STM8 microcontroller’s Flash program memory, data EEPROM and
option bytes. STVP also offers project mode for saving programming configurations and
automating programming sequences.
13.2.2
C and assembly toolchains
Control of C and assembly toolchains is seamlessly integrated into the STVD integrated
development environment, making it possible to configure and control the building of your
application directly from an easy-to-use graphical interface.
Available toolchains include:
Cosmic C compiler for STM8 – Available in a free version that outputs up to 16 Kbytes
of code. For more information, see www.cosmic-software.com.
•
•
•
Raisonance C compiler for STM8 – Available in a free version that outputs up to
16 Kbytes of code. For more information, see www.raisonance.com.
STM8 assembler linker – Free assembly toolchain included in the STVD toolset, which
allows you to assemble and link your application source code.
13.3
Programming tools
During the development cycle, STice provides in-circuit programming of the STM8 Flash
microcontroller on your application board via the SWIM protocol. Additional tools are to include
a low-cost in-circuit programmer as well as ST socket boards, which provide dedicated
programming platforms with sockets for programming your STM8.
For production environments, programmers will include a complete range of gang and
automated programming solutions from third-party tool developers already supplying
programmers for the STM8 family.
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Revision history
STM8S105xx
14
Revision history
Table 59: Document revision history
Date
Revision
Changes
05-Jun-2008
1
Initial release.
23-Jun-2008
12-Aug-2008
2
3
Corrected number of high sink outputs to 9 in I/Os on Features.
Updated part numbers in Table 2: STM8S105xx access line
features.
Updated part numbers in Table 2: STM8S105xx access line
features.
USART renamed UART1, LINUART renamed UART2.
Added Table 7: Pin-to-pin comparison of pin 7 to 12 in 32-pin
access line devices.
17-Sep-2008
4
Removed STM8S102xx and STM8S104xx root part numbers
corresponding to devices without data EEPROM.
Updated STM8S103 pinout in Section 5.2 on page 29.
Added low and medium density Flash memory categories.
Added Note 1 in Table 17: Current characteristics.
Updated Table 12: Option bytes .
05-Feb-2009
5
Updated STM8S103 pinout in Section 5.2 on page 29
Updated number of High Sink I/Os in pinout.
TSSOP20 pinout modified (PD4 moved to pin 1 etc.)
Added WFQFN20 package
Updated Option bytes.
Added Memory and register map.
27-Feb-2009
12-May-2009
6
7
Removed STM8S103x products (separate STM8S103
datasheet created)
Updated Electrical characteristics.
Added SDIP32 silhouette and package to Features and SDIP32
package mechanical data data ; updated Pinout and pin
description and
Updated VDD range (2.95 V to 5.5 V) on Features.
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Revision history
Date
Revision
Changes
Amended name of package VQFPN32
Added Table 5 on page 22 .
Updated Auto wakeup counter.
Updated pins 25, 30, and 31 in Pinout and pin description.
Removed Table 7: Pin-to-pin comparison of pin 7 to 12 in 32-pin
access line devices.
Added Table 14: Description of alternate function remapping
bits [7:0] of OPT2.
Electrical characteristics: Updated VCAP specifications;
updated Table 15, Table 18, Table 20, Table 21, Table 22,
Table 23, Table 24, Table 25, Table 26, Table 27, Table 29,
Table 35, and Table 42; added current consumption curves ;
removed Figure 20: typical HSE frequency vs fcpu @ 4
temperatures; updated Figure 13, Figure 14, Figure 15, Figure
16 and Figure 17 ; modified HSI accuracy in Table 33 ; added
Figure 44 ; modified fSCK, tV(SO) and tV(MO) in Table 42 ;
updated figures and tables of High speed internal RC oscillator
(HSI) ; replaced Figure 23, Figure 24, Figure 26, and Figure
39 .
Package characteristics: Updated Table 58: Thermal
characteristics(1) and removed Table 57: Junction temperature
range. Updated Figure 53: STM8S105xx access line ordering
information scheme.
10-Jun-2009
21-Apr-2010
8
9
Document status changed from “preliminary data” to
“datasheet”.
Standardized name of the VFQFPN package.
Removed ‘wpu’ from I2C pins in Pinout and pin description
Added UFQFPN32 package silhouette to the title page.
Features: added unique ID.
Clock controller: updated bit positions for TIM2 and TIM3.
Beeper: added information about availability of the beeper
output port through option bit AFR7.
Analog-to-digital converter (ADC1): added a note concerning
additional AIN12 analog input.
STM8S105 pinouts and pin description: added UFQFPN32
package details; updated default alternate function of
PB2/AIN2[TIM1_CH3N] pin in the "pin description for
STM8S105 microcontrollers" table.
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Revision history
Date
STM8S105xx
Revision
Changes
Option bytes: added description of STM8L bootloader option
bytes to the option byte description table.
Added Unique ID
Operating conditions: added introductory text; removed low
power dissipation condition for TA, replaced "CEXT" by "VCAP",
and added ESR and ESL data in table "general operating
conditions".
Total current consumption in halt mode: replaced max value
of IDD(H) at 85 °C from 20 µA to 25 µA for the condition "Flash
in powerdown mode, HSI clock after wakeup in the table "total
current consumption in halt mode at VDD = 5 V.
Low power mode wakeup times: added first condition (0 to 16
MHz) for the tWU(WFI) parameter in the table "wakeup times".
Internal clock sources and timing characteristics: In the table
"HSI oscillator characteristics", replaced min and max values
of "ACCHSI factory calibrated parameter" and removed footnote
4 concerning further characterization of results.
Functional EMS (electromagnetic susceptibility): IEC 1000
replaced with IEC 61000.
Designing hardened software to avoid noise problems: IEC
1000 replaced with IEC 61000.
Electromagnetic interference (EMI): SAE J 1752/3 replaced
with IEC61967-2.
Thermal characteristics: Replaced the thermal resistance
junction ambient temperature of LQFP32 7X7 mm from 59 °C
to 60 °C in the thermal characteristics table.
Added 32-lead UFQFPN package mechanical data.
Added STM8S105 FASTROM microcontroller option list.
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Please Read Carefully
Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries
(“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products
and services described herein at anytime, without notice.
All ST products are sold pursuant to ST’s terms and conditions of sale.
Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein,
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No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document.
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the use of such third party products or services, or any intellectual property contained therein or considered as a warranty
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shall immediately voidany warranty granted by ST for the ST product or service described herein and shall not create or
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ST and the ST logo are trademarks or registered trademarks of ST in various countries.
Information in this document supersedes and replaces all information previously supplied.
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