STM8S105C4 [STMICROELECTRONICS]
Extended instruction set;
| 型号： | STM8S105C4 |
| 厂家： | 
ST |
| 描述： | Extended instruction set |
| 文件： | 总121页 (文件大小：1984K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
STM8S105C4/6 STM8S105K4/6
STM8S105S4/6
Access line, 16 MHz STM8S 8-bit MCU, up to 32 Kbyte Flash,
integrated EEPROM, 10-bit ADC, timers, UART, SPI, I²C
Datasheet - production data
Features
Core
16 MHz advanced STM8 core with Harvard
architecture and 3-stage pipeline
LQFP48 (7x7 mm)
LQFP44 (10x10 mm) LQFP32 (7x7 mm)
Extended instruction set
Memories
ꢀꢁ
Program memory: up to 32 Kbyte Flash; data
ꢂ
retention 20 years at 55 °C after 10 kcycle
UFQFPN32 (5x5 mm)
SDIP32 400ml
Data memory: up to 1 Kbyte true data
2x16-bit general purpose timer, with 2+3
EEPROM; endurance 300 kcycle
CAPCOM channels (IC, OC or PWM)
RAM: up to 2 Kbyte
8-bit basic timer with 8-bit prescaler
Auto wake-up timer
Clock, reset and supply management
2.95 to 5.5 V operating voltage
Window watchdog and independent watchdog
timers
Flexible clock control, 4 master clock sources
– Low power crystal resonator oscillator
– External clock input
Communication interfaces
UART with clock output for synchronous
– Internal, user-trimmable 16 MHz RC
– Internal low-power 128 kHz RC
operation, SmartCard, IrDA, LIN master mode
SPI interface up to 8 Mbit/s
I2C interface up to 400 kbit/s
Clock security system with clock monitor
Power management:
– Low-power modes (wait, active-halt, halt)
– Switch-off peripheral clocks individually
Analog to digital converter (ADC)
10-bit, ±1 LSB ADC with up to 10 multiplexed
Permanently active, low-consumption power-
channels, scan mode and analog watchdog
on and power-down reset
I/Os
Interrupt management
Up to 38 I/Os on a 48-pin package including
Nested interrupt controller with 32 interrupts
Up to 37 external interrupts on 6 vectors
16 high sink outputs
Highly robust I/O design, immune against
current injection
Timers
Unique ID
Advanced control timer: 16-bit, 4 CAPCOM
channels, 3 complementary outputs, dead-time
insertion and flexible synchronization
96-bit unique key for each device
September 2015
DocID14771 Rev 15
1/121
This is information on a product in full production.
www.st.com
Contents
STM8S105x4/6
Contents
1
2
3
4
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Product overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.1
4.2
4.3
4.4
4.5
4.6
4.7
4.8
4.9
Central processing unit STM8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Single wire interface module (SWIM) and debug module (DM) . . . . . . . . 14
Interrupt controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Flash program and data EEPROM memory . . . . . . . . . . . . . . . . . . . . . . . 14
Clock controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Watchdog timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Auto wakeup counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Beeper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.10 TIM1 - 16-bit advanced control timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.11 TIM2, TIM3 - 16-bit general purpose timers . . . . . . . . . . . . . . . . . . . . . . . 18
4.12 TIM4 - 8-bit basic timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.13 Analog-to-digital converter (ADC1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.14 Communication interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.14.1 UART2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.14.2 SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
2
4.14.3 I C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
5
6
Pinout and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
5.1
Alternate function remapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Memory and register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
6.1
6.2
Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
6.2.1
6.2.2
I/O port hardware register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
General hardware register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
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Contents
6.2.3
CPU/SWIM/debug module/interrupt controller registers . . . . . . . . . . . . 42
7
8
Interrupt vector mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Option byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
8.1
Alternate function remapping bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
9
Unique ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
10
10.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
10.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
10.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
10.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
10.1.4 Typical current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
10.1.5 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
10.1.6 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
10.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
10.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
10.3.1 VCAP external capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
10.3.2 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
10.3.3 External clock sources and timing characteristics . . . . . . . . . . . . . . . . . 66
10.3.4 Internal clock sources and timing characteristics . . . . . . . . . . . . . . . . . 69
10.3.5 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
10.3.6 I/O port pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
10.3.7 Typical output level curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
10.3.8 Reset pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
10.3.9 SPI serial peripheral interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
2
10.3.10 I C interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
10.3.11 10-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
10.3.12 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
11
Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
11.1 LQFP48 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
11.2 LQFP44 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
11.3 LQFP32 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
11.4 UFQFPN32 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
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4
Contents
STM8S105x4/6
11.5 SDIP32 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
12
Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
12.1 Reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
12.2 Selecting the product temperature range . . . . . . . . . . . . . . . . . . . . . . . . 107
13
14
Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
13.1 STM8S105 FASTROM microcontroller option list . . . . . . . . . . . . . . . . . 109
STM8 development tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
14.1 Emulation and in-circuit debugging tools . . . . . . . . . . . . . . . . . . . . . . . . .113
14.1.1 STice key features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
14.2 Software tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .114
14.2.1 STM8 toolset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
14.2.2 C and assembly toolchains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
14.3 Programming tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115
15
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
4/121
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STM8S105x4/6
List of tables
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
STM8S105x4/6 access line features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Peripheral clock gating bit assignments in CLK_PCKENR1/2 registers. . . . . . . . . . . . . . . 16
TIM timer features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Legend/abbreviations for pin description tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
STM8S105x4/6 pin description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Flash, data EEPROM and RAM boundary address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
I/O port hardware register map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
General hardware register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
CPU/SWIM/debug module/interrupt controller registers. . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Interrupt mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Option byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Option byte description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Alternate function remapping bits [7:0] of OPT2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Unique ID registers (96 bits) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Operating conditions at power-up/power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
Table 26.
Table 27.
Table 28.
Table 29.
Table 30.
Table 31.
Table 32.
Table 33.
Table 34.
Table 35.
Table 36.
Table 37.
Table 38.
Table 39.
Table 40.
Table 41.
Table 42.
Table 43.
Table 44.
Table 45.
Table 46.
Table 47.
Table 48.
Total current consumption with code execution in run mode at V = 5 V. . . . . . . . . . . . . 57
DD
Total current consumption with code execution in run mode at V = 3.3 V . . . . . . . . . . . 58
DD
Total current consumption in wait mode at V = 5 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
DD
Total current consumption in wait mode at V = 3.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . 59
DD
Total current consumption in active halt mode at V = 5 V . . . . . . . . . . . . . . . . . . . . . . . 59
DD
Total current consumption in active halt mode at V = 3.3 V . . . . . . . . . . . . . . . . . . . . . . 60
DD
Total current consumption in halt mode at V = 5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
DD
Total current consumption in halt mode at V = 3.3 V . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
DD
Wakeup times. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Total current consumption and timing in forced reset state . . . . . . . . . . . . . . . . . . . . . . . . 61
Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
HSE user external clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
HSE oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
HSI oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
RAM and hardware registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Flash program memory/data EEPROM memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Output driving current (standard ports). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Output driving current (true open drain ports). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Output driving current (high sink ports). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
2
I C characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
ADC accuracy with R < 10 k, V
= 5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
= 3.3 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
AIN
DDA
ADC accuracy with R < 10 k, V
AIN
DDA
EMS data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
EMI data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
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List of tables
STM8S105x4/6
Table 49.
Table 50.
Table 51.
ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
LQFP48 - 48-pin, 7 x 7 mm low-profile quad flat package
mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Table 52.
Table 53.
Table 54.
LQFP44 - 44-pin, 10 x 10 mm low-profile quad flat package
mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
LQFP32 - 32-pin, 7 x 7 mm low-profile quad flat package
mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
UFQFPN32 - 32-pin, 5x5 mm, 0.5 mm pitch ultra thin fine pitch quad flat
package mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
SDIP32 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Table 55.
Table 56.
Table 57.
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List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
STM8S105x4/6 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Flash memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
LQFP48 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
LQFP44 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
UFQFPN32/LQFP32 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
SDIP32 pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Supply current measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Pin loading conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Figure 10. Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Figure 11. versus V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Figure 12. External capacitor C
f
CPUmax
DD
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
EXT
Figure 13. Typ I
Figure 14. Typ I
Figure 15. Typ I
Figure 16. Typ I
Figure 17. Typ I
Figure 18. Typ I
vs. V HSE user external clock, f
= 16 MHz . . . . . . . . . . . . . . . . . . . . 62
DD(RUN)
DD(RUN)
DD(RUN)
DD(WFI)
DD(WFI)
DD(WFI)
DD
CPU
vs. f
HSE user external clock, V = 5 V . . . . . . . . . . . . . . . . . . . . . . . . 63
CPU
DD
vs. V HSI RC osc, f
= 16 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
CPU
DD
vs. V HSE external clock, f
= 16 MHz . . . . . . . . . . . . . . . . . . . . . . . . . 64
DD
CPU
vs. f
HSE external clock, V = 5 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
CPU
DD
vs. V HSI RC osc., f
= 16 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
CPU
DD
Figure 19. HSE external clock source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Figure 20. HSE oscillator circuit diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Figure 21. Typical HSI accuracy @ V = 5 V vs 5 temperatures. . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
DD
Figure 22. Typical HSI frequency variation vs V @ 4 temperatures . . . . . . . . . . . . . . . . . . . . . . . . 70
DD
Figure 23. Typical LSI frequency variation vs V @ 4 temperatures . . . . . . . . . . . . . . . . . . . . . . . . . 71
DD
Figure 24. Typical V and V vs V @ 4 temperatures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
IL
IH
DD
Figure 25. Typical pull-up current vs V @ 4 temperatures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
DD
Figure 26. Typical pull-up resistance vs VDD @ 4 temperatures . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Figure 27. Typ. V @ V = 3.3 V (standard ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
OL
DD
Figure 28. Typ. V @ V = 5.0 V (standard ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
OL
DD
Figure 29. Typ. V @ V = 3.3 V (true open drain ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
OL
DD
Figure 30. Typ. V @ V = 5.0 V (true open drain ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
OL
DD
Figure 31. Typ. V @ V = 3.3 V (high sink ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
OL
DD
Figure 32. Typ. V @ V = 5.0 V (high sink ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
OL
DD
Figure 33. Typ. V - V @ V = 3.3 V (standard ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
DD
OH
DD
Figure 34. Typ. V - V @ V = 5.0 V (standard ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
DD
OH
DD
Figure 35. Typ. V - V @ V = 3.3 V (high sink ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
DD
OH
DD
Figure 36. Typ. V - V @ V = 5.0 V (high sink ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
DD
OH
DD
Figure 37. Typical NRST V and V vs V @ 4 temperatures. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
IL
IH
DD
Figure 38. Typical NRST pull-up resistance R vs V @ 4 temperatures. . . . . . . . . . . . . . . . . . . . 79
PU
DD
Figure 39. Typical NRST pull-up current I vs V @ 4 temperatures. . . . . . . . . . . . . . . . . . . . . . . . 79
pu
DD
Figure 40. Recommended reset pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Figure 41. SPI timing diagram where slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Figure 42. SPI timing diagram where slave mode and CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Figure 43. SPI timing diagram - master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
2
Figure 44. Typical application with I C bus and timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Figure 45. ADC accuracy characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Figure 46. Typical application with ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Figure 47. LQFP48 - 48-pin, 7 x 7 mm low-profile quad flat package outline . . . . . . . . . . . . . . . . . . . 91
Figure 48. LQFP48 - 48-pin, 7 x 7 mm low-profile quad flat package
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8
List of figures
STM8S105x4/6
recommended footprint. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Figure 49. LQFP48 marking example (package top view). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Figure 50. LQFP44 - 44-pin, 10 x 10 mm low-profile quad flat package outline . . . . . . . . . . . . . . . . . 94
Figure 51. LQFP44 - 44-pin, 10 x 10 mm low-profile quad flat package
recommended footprint. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Figure 52. LQFP44 marking example (package top view). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Figure 53. LQFP32 - 32-pin, 7 x 7 mm low-profile quad flat package outline . . . . . . . . . . . . . . . . . . . 98
Figure 54. LQFP32 - 32-pin, 7 x 7 mm low-profile quad flat package
recommended footprint. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Figure 55. LQFP32 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Figure 56. UFQFPN32 - 32-pin, 5x5 mm, 0.5 mm pitch ultra thin fine pitch quad flat
package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Figure 57. UFQFPN32 - 32-pin, 5 x5 mm, 0.5 mm pitch ultra thin fine pitch quad flat
package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Figure 58. UFQFPN32 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Figure 59. SDIP32 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Figure 60. SDIP32 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
(1)
Figure 61. STM8S105x4/6 access line ordering information scheme . . . . . . . . . . . . . . . . . . . . . . 108
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Introduction
1
Introduction
This datasheet contains the description of the device features, pinout, electrical
characteristics, mechanical data and ordering information.
For complete information on the STM8S microcontroller memory, registers and
peripherals, please refer to the STM8S microcontroller family reference manual
(RM0016).
For information on programming, erasing and protection of the internal Flash memory
please refer to the STM8S Flash programming manual (PM0051).
For information on the debug and SWIM (single wire interface module) refer to the
STM8 SWIM communication protocol and debug module user manual (UM0470).
For information on the STM8 core, please refer to the STM8 CPU programming manual
(PM0044).
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21
Description
STM8S105x4/6
2
Description
The STM8S105x4/6 access line 8-bit microcontrollers offer from 16 to 32 Kbyte Flash
program memory, plus integrated true data EEPROM. The STM8S microcontroller family
reference manual (RM0016) refers to devices in this family as medium-density. All devices
of the STM8S105x4/6 access line provide the following benefits: reduced system cost,
performance and robustness, short development cycles, and product longevity.
The system cost is reduced thanks to an integrated true data EEPROM for up to 300 k
write/erase cycles and a high system integration level with internal clock oscillators,
watchdog and brown-out reset.
Device performance is ensured by a 16 MHz CPU clock frequency and enhanced
characteristics which include robust I/O, independent watchdogs (with a separate clock
source), and a clock security system.
Short development cycles are guaranteed due to application scalability across common
family product architecture with compatible pinout, memory map and modular peripherals.
Product longevity is ensured in the STM8S family thanks to their advanced core which is
made in a state-of-the-art technology for applications with 2.95 V to 5.5 V operating supply.
Full documentation is offered as well as a wide choice of development tools.
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Description
Table 1. STM8S105x4/6 access line features
STM8S105C6 STM8S105C4 STM8S105S6 STM8S105S4 STM8S105K6 STM8S105K4
Device
Pin count
48
48
44
44
32
32
Maximum
number of
GPIOs
38
38
34
34
25
25
Ext. Interrupt
pins
35
9
35
9
31
8
31
8
23
8
23
8
Timer
CAPCOM
channels
Timer
complementar
y outputs
3
3
3
3
3
3
A/D Converter
channels
10
16
10
16
9
9
7
7
High sink I/Os
15
15
12
12
Medium
density Flash
Program
32K
16K
32K
16K
32K
16K
memory (byte)
Data
EEPROM
(bytes)
1024
2K
1024
2K
1024
2K
1024
2K
1024
2K
1024
2K
RAM (bytes)
Advanced control timer (TIM1), General-purpose timers (TIM2 and TIM3), Basic timer (TIM4) SPI,
I2C, UART, Window WDG, Independent WDG, ADC
Peripheral set
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21
Block diagram
STM8S105x4/6
3
Block diagram
Figure 1. STM8S105x4/6 block diagram
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Product overview
4
Product overview
The following section provides an overview of the basic features of the device functional
modules and peripherals.
For more detailed information please refer to the corresponding family reference manual
(RM0016).
4.1
Central processing unit STM8
The 8-bit STM8 core is designed for code efficiency and performance.
It contains 6 internal registers which are directly addressable in each execution context, 20
addressing modes including indexed indirect and relative addressing and 80 instructions.
Architecture and registers
Harvard architecture,
3-stage pipeline,
32-bit wide program memory bus - single cycle fetching for most instructions,
X and Y 16-bit index registers - enabling indexed addressing modes with or without
offset and read-modify-write type data manipulations,
8-bit accumulator,
24-bit program counter - 16-Mbyte linear memory space,
16-bit stack pointer - access to a 64 K-level stack,
8-bit condition code register - 7 condition flags for the result of the last instruction.
Addressing
20 addressing modes,
Indexed indirect addressing mode for look-up tables located anywhere in the address
space,
Stack pointer relative addressing mode for local variables and parameter passing.
Instruction set
80 instructions with 2-byte average instruction size,
Standard data movement and logic/arithmetic functions,
8-bit by 8-bit multiplication,
16-bit by 8-bit and 16-bit by 16-bit division,
Bit manipulation,
Data transfer between stack and accumulator (push/pop) with direct stack access,
Data transfer using the X and Y registers or direct memory-to-memory transfers.
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21
Product overview
STM8S105x4/6
4.2
Single wire interface module (SWIM) and debug module (DM)
The single wire interface module and debug module permits non-intrusive, real-time in-
circuit debugging and fast memory programming.
SWIM
Single wire interface module for direct access to the debug module and memory
programming. The interface can be activated in all device operation modes. The maximum
data transmission speed is 145 bytes/ms.
Debug module
The non-intrusive debugging module features a performance close to a full-featured
emulator. Beside memory and peripherals, also CPU operation can be monitored in real-
time by means of shadow registers.
R/W to RAM and peripheral registers in real-time
R/W access to all resources by stalling the CPU
Breakpoints on all program-memory instructions (software breakpoints)
Two advanced breakpoints, 23 predefined configurations
4.3
4.4
Interrupt controller
Nested interrupts with three software priority levels,
32 interrupt vectors with hardware priority,
Up to 37 external interrupts on 6 vectors including TLI,
Trap and reset interrupts
Flash program and data EEPROM memory
Up to 32 Kbyte of Flash program single voltage Flash memory,
Up to 1 Kbyte true data EEPROM,
Read while write: writing in data memory possible while executing code in program
memory,
User option byte area.
Write protection (WP)
Write protection of Flash program memory and data EEPROM is provided to avoid
unintentional overwriting of memory that could result from a user software malfunction.
There are two levels of write protection. The first level is known as MASS (memory access
security system). MASS is always enabled and protects the main Flash program memory,
data EEPROM and option bytes.
To perform in-application programming (IAP), this write protection can be removed by
writing a MASS key sequence in a control register. This allows the application to write to
data EEPROM, modify the contents of main program memory or the device option bytes.
A second level of write protection, can be enabled to further protect a specific area of
memory known as UBC (user boot code). Refer to the figure below.
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Product overview
The size of the UBC is programmable through the UBC option byte, in increments of 1 page
(512 byte) by programming the UBC option byte in ICP mode.
This divides the program memory into two areas:
Main program memory: up to 32 Kbyte minus UBC
User-specific boot code (UBC): Configurable up to 32 Kbyte
The UBC area remains write-protected during in-application programming. This means that
the MASS keys do not unlock the UBC area. It protects the memory used to store the boot
program, specific code libraries, reset and interrupt vectors, the reset routine and usually
the IAP and communication routines.
Figure 2. Flash memory organization
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Read-out protection (ROP)
The read-out protection blocks reading and writing the Flash program memory and data
EEPROM memory in ICP mode (and debug mode). Once the read-out protection is
activated, any attempt to toggle its status triggers a global erase of the program and data
memory. Even if no protection can be considered as totally unbreakable, the feature
provides a very high level of protection for a general purpose microcontroller.
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21
Product overview
STM8S105x4/6
4.5
Clock controller
The clock controller distributes the system clock (fMASTER) coming from different
oscillators to the core and the peripherals. It also manages clock gating for low power
modes and ensures clock robustness.
Features
Clock prescaler: to get the best compromise between speed and current consumption
the clock frequency to the CPU and peripherals can be adjusted by a programmable
prescaler.
Safe clock switching: clock sources can be changed safely on the fly in run mode
through a configuration register. The clock signal is not switched until the new clock
source is ready. The design guarantees glitch-free switching.
Clock management: to reduce power consumption, the clock controller can stop the
clock to the core, individual peripherals or memory.
Master clock sources: four different clock sources can be used to drive the master
clock:
–
–
–
–
1-16 MHz high-speed external crystal (HSE)
Up to 16 MHz high-speed user-external clock (HSE user-ext)
16 MHz high-speed internal RC oscillator (HSI)
128 kHz low-speed internal RC (LSI)
Startup clock: After reset, the microcontroller restarts by default with an internal 2 MHz
clock (HSI/8). The prescaler ratio and clock source can be changed by the application
program as soon as the code execution starts.
Clock security system (CSS): This feature can be enabled by software. If an HSE
clock failure occurs, the internal RC (16 MHz/8) is automatically selected by the CSS
and an interrupt can optionally be generated.
Configurable main clock output (CCO): This outputs an external clock for use by the
application.
Table 2. Peripheral clock gating bit assignments in CLK_PCKENR1/2 registers
Peripheral
clock
Peripheral
clock
Peripheral
clock
Peripheral
clock
Bit
Bit
Bit
Bit
PCKEN17
PCKEN16
PCKEN15
PCKEN14
TIM1
TIM3
TIM2
TIM4
PCKEN13
PCKEN12
PCKEN11
PCKEN10
UART2
Reserved
SPI
PCKEN27
PCKEN26
PCKEN25
PCKEN24
Reserved
Reserved
Reserved
Reserved
PCKEN23
PCKEN22
PCKEN21
PCKEN20
ADC
AWU
Reserved
Reserved
I2C
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Product overview
4.6
Power management
For efficient power management, the application can be put in one of four different low-
power modes. You can configure each mode to obtain the best compromise between lowest
power consumption, fastest start-up time and available wakeup sources.
Wait mode: In this mode, the CPU is stopped, but peripherals are kept running. The
wakeup is performed by an internal or external interrupt or reset.
Active halt mode with regulator on: In this mode, the CPU and peripheral clocks are
stopped. An internal wakeup is generated at programmable intervals by the auto wake
up unit (AWU). The main voltage regulator is kept powered on, so current consumption
is higher than in active halt mode with regulator off, but the wakeup time is faster.
Wakeup is triggered by the internal AWU interrupt, external interrupt or reset.
Active halt mode with regulator off: This mode is the same as active halt with
regulator on, except that the main voltage regulator is powered off, so the wake up time
is slower.
Halt mode: In this mode the microcontroller uses the least power. The CPU and
peripheral clocks are stopped, the main voltage regulator is powered off. Wakeup is
triggered by external event or reset.
4.7
Watchdog timers
The watchdog system is based on two independent timers providing maximum security to
the applications.
Activation of the watchdog timers is controlled by option bytes or by software. Once
activated, the watchdogs cannot be disabled by the user program without performing a
reset.
Window watchdog timer
The window watchdog is used to detect the occurrence of a software fault, usually
generated by external interferences or by unexpected logical conditions, which cause the
application program to abandon its normal sequence.
The window function can be used to trim the watchdog behavior to match the application
perfectly.
The application software must refresh the counter before time-out and during a limited time
window.
A reset is generated in two situations:
1. Timeout: At 16 MHz CPU clock the time-out period can be adjusted between 75 µs up
to 64 ms.
2. Refresh out of window: The downcounter is refreshed before its value is lower than the
one stored in the window register.
Independent watchdog timer
The independent watchdog peripheral can be used to resolve processor malfunctions due to
hardware or software failures.
It is clocked by the 128 kHz LSI internal RC clock source, and thus stays active even in case
of a CPU clock failure
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21
Product overview
STM8S105x4/6
The IWDG time base spans from 60 µs to 1 s.
4.8
4.9
Auto wakeup counter
Used for auto wakeup from active halt mode,
Clock source: Internal 128 kHz internal low frequency RC oscillator or external clock,
LSI clock can be internally connected to TIM1 input capture channel 1 for calibration.
Beeper
The beeper function outputs a signal on the BEEP pin for sound generation. The signal is in
the range of 1, 2 or 4 kHz.
The beeper output port is only available through the alternate function remap option bit
AFR7.
4.10
4.11
18/121
TIM1 - 16-bit advanced control timer
This is a high-end timer designed for a wide range of control applications. With its
complementary outputs, dead-time control and center-aligned PWM capability, the field of
applications is extended to motor control, lighting and half-bridge driver
16-bit up, down and up/down autoreload counter with 16-bit prescaler
Four independent capture/compare channels (CAPCOM) configurable as input
capture, output compare, PWM generation (edge and center aligned mode) and single
pulse mode output
Synchronization module to control the timer with external signals
Break input to force the timer outputs into a defined state
Three complementary outputs with adjustable dead time
Encoder mode
Interrupt sources: 3 x input capture/output compare, 1 x overflow/update, 1 x break
TIM2, TIM3 - 16-bit general purpose timers
16-bit auto reload (AR) up-counter
15-bit prescaler adjustable to fixed power of 2 ratios 1…32768
Timers with 3 or 2 individually configurable capture/compare channels
PWM mode
Interrupt sources: 2 or 3 x input capture/output compare, 1 x overflow/update
DocID14771 Rev 15
STM8S105x4/6
Product overview
4.12
TIM4 - 8-bit basic timer
8-bit auto reload, adjustable prescaler ratio to any power of 2 from 1 to 128
Clock source: CPU clock
Interrupt source: 1 x overflow/update
Table 3. TIM timer features
Timer
synchronization/
chaining
Counter
size (bits)
Counting CAPCOM Complementary
Ext.
trigger
Timer
Prescaler
mode
channels
outputs
Any integer
from 1 to
65536
TIM1
TIM2
TIM3
TIM4
16
16
16
8
Up/down
4
3
Yes
No
No
No
Any power
of 2 from 1
to 32768
Up
Up
Up
3
2
0
0
0
0
No
Any power
of 2 from 1
to 32768
Any power
of 2 from 1
to 128
4.13
Analog-to-digital converter (ADC1)
The STM8S105x4/6 products contain a 10-bit successive approximation A/D converter
(ADC1) with up to 10 multiplexed input channels and the following main features:
Input voltage range: 0 to VDD
Conversion time: 14 clock cycles
Single and continuous and buffered continuous conversion modes
Buffer size (n x 10 bits) where n = number of input channels
Scan mode for single and continuous conversion of a sequence of channels
Analog watchdog capability with programmable upper and lower thresholds
Analog watchdog interrupt
External trigger input
Trigger from TIM1 TRGO
End of conversion (EOC) interrupt
Note:
Additional AIN12 analog input is not selectable in ADC scan mode or with analog watchdog.
Values converted from AIN12 are stored only into the ADC_DRH/ADC_DRL registers.
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21
Product overview
STM8S105x4/6
4.14
Communication interfaces
The following communication interfaces are implemented:
UART1: Full feature UART, synchronous mode, SPI master mode, Smartcard mode,
IrDA mode, single wire mode, LIN2.1 master capability
SPI: Full and half-duplex, 8 Mbit/s
I²C: Up to 400 kbit/s
4.14.1
UART2
Main features
1 Mbit/s full duplex SCI
SPI emulation
High precision baud rate generator
Smartcard emulation
IrDA SIR encoder decoder
LIN master mode
LIN slave mode
Asynchronous communication (UART mode)
Full duplex communication - NRZ standard format (mark/space)
Programmable transmit and receive baud rates up to 1 Mbit/s (fCPU/16) and capable
of following any standard baud rate regardless of the input frequency
Separate enable bits for transmitter and receiver
Two receiver wakeup modes:
–
–
Address bit (MSB)
Idle line (interrupt)
Transmission error detection with interrupt generation
Parity control
Synchronous communication
Full duplex synchronous transfers
SPI master operation
8-bit data communication
Maximum speed: 1 Mbit/s at 16 MHz (fCPU/16)
LIN master mode
Emission: Generates 13-bit synch. break frame
Reception: Detects 11-bit break frame
20/121
DocID14771 Rev 15
STM8S105x4/6
Product overview
LIN slave mode
Autonomous header handling - one single interrupt per valid message header
Automatic baud rate synchronization - maximum tolerated initial clock deviation ±15%
Synch delimiter checking
11-bit LIN synch break detection - break detection always active
Parity check on the LIN identifier field
LIN error management
Hot plugging support
4.14.2
SPI
Maximum speed: 8 Mbit/s (fMASTER/2) both for master and slave
Full duplex synchronous transfers
Simplex synchronous transfers on two lines with a possible bidirectional data line
Master or slave operation - selectable by hardware or software
CRC calculation
1 byte Tx and Rx buffer
Slave/master selection input pin
2
4.14.3
I C
I²C master features:
–
–
Clock generation
Start and stop generation
I²C slave features:
–
–
Programmable I2C address detection
Stop bit detection
Generation and detection of 7-bit/10-bit addressing and general call
Supports different communication speeds:
–
–
Standard speed (up to 100 kHz)
Fast speed (up to 400 kHz)
DocID14771 Rev 15
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21
Pinout and pin description
STM8S105x4/6
5
Pinout and pin description
Table 4. Legend/abbreviations for pin description tables
Type
I= Input, O = Output, S = Power supply
Input
CM = CMOS
Level
Output
HS = High sink
O1 = Slow (up to 2 MHz)
O2 = Fast (up to 10 MHz)
Output speed
O3 = Fast/slow programmability with slow as default state after reset
O4 = Fast/slow programmability with fast as default state after reset
float = floating,
Input
wpu = weak pull-up
Port and control
configuration
T = True open drain,
Output
OD = Open drain,
PP = Push pull
Bold X (pin state after internal reset release).
Reset state
Unless otherwise specified, the pin state is the same during the reset
phase and after the internal reset release.
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DocID14771 Rev 15
STM8S105x4/6
Pinout and pin description
Figure 3. LQFP48 pinout
ꢍꢃ ꢍꢑ ꢍꢇ ꢍꢏ ꢍꢍ ꢍꢀ ꢍꢁ ꢍꢂ ꢍꢄ ꢀꢐ ꢀꢃ ꢀꢑ
3*ꢂ
3*ꢄ
ꢀꢇ
ꢂ
1567
26&,1ꢉ3$ꢂ
26&287ꢉ3$ꢁ
966,2Bꢂ
ꢁ
ꢀꢏ
ꢀꢍ
ꢀꢀ
ꢀꢁ
3&ꢑꢅꢊ+6ꢌꢉ63,B0,62
3&ꢇꢅꢊ+6ꢌꢉ63,B026,ꢅ
9'',2Bꢁ
ꢀ
ꢍ
ꢏ
966
9&$3
9''
9'',2Bꢂ
ꢀꢂ 966,2Bꢁ
ꢇ
3&ꢏꢅꢊ+6ꢌꢉ63,B6&.
3&ꢍꢅꢊ+6ꢌꢉ7,0ꢂB&+ꢍꢅ
3&ꢀꢅꢊ+6ꢌꢉ7,0ꢂB&+ꢀꢅ
ꢀꢄ
ꢁꢐ
ꢁꢃ
ꢑ
ꢃ
ꢐ
>7,0ꢀB&+ꢂ@ꢅ7,0ꢁB&+ꢀꢉ3$ꢀ
ꢊ+6ꢌꢅ3$ꢍ
ꢁꢑ 3&ꢁꢅꢊ+6ꢌꢉ7,0ꢂB&+ꢁꢅ
ꢂꢄ
3&ꢂꢅꢊ+6ꢌꢉ7,0ꢂB&+ꢂꢉ8$57ꢁB&.ꢅ
3(ꢏꢉ63,B166
ꢁꢇ
ꢂꢂ
ꢂꢁ
ꢊ+6ꢌꢅ3$ꢏꢅ
ꢊ+6ꢌꢅ3$ꢇ
ꢁꢏ
ꢁꢍ
ꢂꢀ ꢂꢍ ꢂꢏ ꢂꢇ ꢂꢑ ꢂꢃ ꢂꢐ ꢁꢄ ꢁꢂ ꢁꢁ ꢁꢀ
06ꢀꢃꢀꢄꢏ9ꢂ
1. (HS) high sink capability.
2. (T) True open drain (P-buffer and protection diode to VDD not implemented).
3. [ ] alternate function remapping option (if the same alternate function is shown twice, it indicates an
exclusive choice not a duplication of the function).
DocID14771 Rev 15
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30
Pinout and pin description
STM8S105x4/6
Figure 4. LQFP44 pinout
ꢍꢍ ꢍꢀ ꢍꢁ ꢍꢂ ꢍꢄ ꢀꢐ ꢀꢃ ꢀꢑ ꢀꢇ ꢀꢏ ꢀꢍ
ꢀꢀ
ꢂ
1567
26&,1ꢉ3$ꢂ
26&287ꢉ3$ꢁ
966,2Bꢂ
3*ꢂ
3*ꢄ
ꢁ
ꢀꢁ
ꢀꢂ
ꢀꢄ
ꢁꢐ
ꢁꢃ
ꢁꢑ
ꢁꢇ
ꢁꢏ
ꢁꢍ
ꢁꢀ
ꢀ
3&ꢑꢅꢊ+6ꢌꢉ63,B0,62
3&ꢇꢅꢊ+6ꢌꢉ63,B026,
9'',2Bꢁ
ꢍ
ꢏ
966
9&$3
9''
9'',2Bꢂ
ꢊ+6ꢌꢅ3$ꢍ
ꢊ+6ꢌꢅ3$ꢏ
ꢊ+6ꢌꢅ3$ꢇ
ꢇ
966,2Bꢁ
ꢑ
3&ꢏꢅꢊ+6ꢌꢉ63,B6&.
3&ꢀꢅꢊ+6ꢌꢉ7,0ꢂB&+ꢀ
3&ꢁꢅꢊ+6ꢌꢉ7,0ꢂB&+ꢁ
3&ꢂꢅꢊ+6ꢌꢉ7,0ꢂB&+ꢂꢉ8$57ꢁB&.
3(ꢏꢉ63,B166
ꢃ
ꢐ
ꢂꢄ
ꢂꢂ
ꢂꢁ ꢂꢀ ꢂꢍ ꢂꢏ ꢂꢇ ꢂꢑ ꢂꢃ ꢂꢐ ꢁꢄ ꢁꢂ ꢁꢁ
06ꢀꢃꢀꢄꢇ9ꢂ
1. (HS) high sink capability.
2. (T) True open drain (P-buffer and protection diode to VDD not implemented).
3. [ ] alternate function remapping option (if the same alternate function is shown twice, it indicates an
exclusive choice not a duplication of the function).
24/121
DocID14771 Rev 15
STM8S105x4/6
Pinout and pin description
Figure 5. UFQFPN32/LQFP32 pinout
ꢀꢁ ꢀꢂ ꢀꢄ ꢁꢐ ꢁꢃ ꢁꢑ ꢁꢇ ꢁꢏ
ꢁꢍ
ꢁꢀ
ꢁꢁ
ꢁꢂ
ꢁꢄ
ꢂꢐ
ꢂꢃ
ꢂꢑ
ꢂ
ꢁ
ꢀ
ꢍ
ꢏ
ꢇ
ꢑ
ꢃ
1567
26&,1ꢉ3$ꢂ
26&287ꢉ3$ꢁ
966
9&$3
9''
9'',2
$,1ꢂꢁꢉ3)ꢍ
3&ꢑꢅꢊ+6ꢌꢉ63,B0,62
3&ꢇꢅꢊ+6ꢌꢉ63,B026,
3&ꢏꢅꢊ+6ꢌꢉ63,B6&.
3&ꢍꢅꢊ+6ꢌꢉ7,0ꢂB&+ꢍꢅ
3&ꢀꢅꢊ+6ꢌꢉ7,0ꢂB&+ꢀꢅ
3&ꢁꢅꢊ+6ꢌꢉ7,0ꢂB&+ꢁꢅ
3&ꢂꢅꢊ+6ꢌꢉ7,0ꢂB&+ꢂꢉ8$57ꢁB&.ꢅ
3(ꢏꢉ63,B166
ꢐ
ꢂꢄ ꢂꢂ ꢂꢁ ꢂꢀ ꢂꢍ ꢂꢏ ꢂꢇ
06ꢀꢃꢀꢄꢑ9ꢂ
1. (HS) high sink capability.
2. [ ] alternate function remapping option (if the same alternate function is shown twice, it indicates an
exclusive choice not a duplication of the function).
DocID14771 Rev 15
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30
Pinout and pin description
STM8S105x4/6
Figure 6. SDIP32 pinout
$'&B(75ꢉ7,0ꢁB&+ꢁꢉꢊ+6ꢌꢅ3'ꢀ
3'ꢁꢅꢊ+6ꢌꢉ7,0ꢀB&+ꢂꢅ>7,0ꢁB&+ꢀ@
ꢂ
ꢁ
ꢀ
ꢍ
ꢏ
ꢇ
ꢑ
ꢃ
ꢐ
ꢀꢁ
>%((3@ꢅ7,0ꢁB&+ꢂꢉꢊ+6ꢌꢅ3'ꢍ
ꢀꢂ 3'ꢂꢅꢊ+6ꢌꢉ6:,0
ꢀꢄ
8$57ꢁB7;ꢉ3'ꢏ
8$57ꢁB5;ꢉ3'ꢇ
3'ꢄꢅꢊ+6ꢌꢉ7,0ꢀB&+ꢁꢅ>7,0ꢂB%.,1@ꢅ>&/.B&&2@
ꢁꢐ 3&ꢑꢅꢊ+6ꢌꢉ63,B0,62
>7,0ꢂB&+ꢍ@ꢅ7/,ꢉ3'ꢑ
ꢁꢃ
3&ꢇꢅꢊ+6ꢌꢉ63,B026,
1567
ꢁꢑ 3&ꢏꢅꢊ+6ꢌꢉ63,B6&.
26&,1ꢉ3$ꢂ
ꢁꢇ
3&ꢍꢅꢊ+6ꢌꢉ7,0ꢂB&+ꢍ
26&287ꢉ3$ꢁ
966
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ꢁꢍ
3&ꢁꢅꢊ+6ꢌꢉ7,0ꢂB&+ꢁ
9&$3 ꢂꢄ
ꢁꢀ 3&ꢂꢅꢊ+6ꢌꢉ7,0ꢂB&+ꢂꢉ8$57ꢁB&.
9''
ꢂꢂ
ꢁꢁ
3(ꢏꢉ63,B166
9'',2
ꢂꢁ
ꢁꢂ 3%ꢄꢉ$,1ꢄꢅ>7,0ꢂB&+ꢂ1@
$,1ꢂꢁꢉ3)ꢍ
ꢂꢀ
ꢂꢍ
ꢂꢏ
ꢁꢄ
3%ꢂꢉ$,1ꢂꢅ>7,0ꢂB&+ꢁ1@
ꢂꢐ 3%ꢁꢉ$,1ꢁꢅ>7,0ꢂB&+ꢀ1@
ꢂꢃ
9''$
966$
3%ꢀꢉ$,1ꢀꢅ>7,0ꢂB(75@
>,ꢁ&B6'$@ꢅ$,1ꢏꢉ3%ꢏ ꢂꢇ
ꢂꢑ 3%ꢍꢉ$,1ꢍ>ꢅ,ꢁ&B6&/@
06ꢀꢃꢀꢄꢃ9ꢂ
1. (HS) high sink capability.
2. (T) True open drain (P-buffer and protection diode to VDD not implemented).
3. [ ] alternate function remapping option (if the same alternate function is shown twice, it indicates an
exclusive choice not a duplication of the function).
Table 5. STM8S105x4/6 pin description
Pin number
Input
Output
Alternate
function
after
remap
[option
bit]
Main
function
(after
Default
alternate
function
Pin name
Type
reset)
1
2
1
2
1
2
6
7
NRST
I/O
I/O
-
X
-
-
-
-
-
-
Reset
Resonato
Port A1 r/ crystal
in
-
PA1/ OSC IN
X
X
O1
O1
X
X
X
Resonato
Port A1 r/ crystal
in
PA2/ OSC
OUT
3
3
3
8
I/O
X
X
-
-
X
4
5
4
5
-
-
VSSIO_1
VSS
S
S
-
-
-
-
-
-
-
-
-
-
-
-
-
-
I/O ground
-
-
4
9
Digital ground
1.8 V regulator
capacitor
6
6
5
10
VCAP
S
-
-
-
-
-
-
-
-
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DocID14771 Rev 15
STM8S105x4/6
Pin number
Pinout and pin description
Table 5. STM8S105x4/6 pin description (continued)
Input
Output
Alternate
Main
function
(after
function
after
remap
[option
bit]
Default
alternate
function
Pin name
Type
reset)
7
8
7
8
6
7
11
12
VDD
S
S
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Digital power supply
I/O power supply
-
-
VDDIO_1
TIM3_
CH1
[AFR1]
PA3/TIM2_CH3
[TIM3_CH1]
Timer 2 -
Port A3
9
-
-
-
I/O
X
X
X
-
O1
X
X
channel 3
10
9
-
-
-
-
-
-
PA4
PA5
PA6
I/O
I/O
I/O
X
X
X
X
X
X
X
X
X
HS O3
HS O3
HS O3
X
X
X
X
X
X
Port A4
Port A5
Port A6
-
-
-
-
-
-
11 10
12 11
Analog
input
-
-
8
9
13 PF4/ AIN12(1)
I/O
X
X
-
-
O1
X
X
Port F4
-
12(2)
13 12
14
VDDA
VSSA
S
S
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Analog power supply
Analog ground
-
-
14 13 10 15
Analog
Port B7
15 14
16 15
-
-
-
-
PB7/ AIN7
PB6/ AIN6
I/O
I/O
X
X
X
X
X
X
-
-
O1
O1
X
X
X
X
-
-
input 7
Analog
Port B6
input 6
I
PB5/ AIN5
[I2C_ SDA]
Analog
Port B5
17 16 11 16
I/O
X
X
X
-
O1
X
X
2C_SDA
[AFR6]
input 5
PB4/ AIN4
[I2C_SCL]
Analog I2C_SCL
input 4 [AFR6]
18 17 12 17
19 18 13 18
I/O
I/O
X
X
X
X
X
X
-
-
O1
O1
X
X
X
X
Port B4
Port B3
PB3/ AIN3
[TIM1_ETR]
Analog TIM1_ET
input 3 R [AFR5]
TIM1_CH
PB2/ AIN2
[TIM1_CH3N]
Analog
3N
20 19 14 19
21 20 15 20
22 21 16 21
I/O
I/O
X
X
X
X
X
X
-
-
O1
O1
X
X
X
X
Port B2
Port B1
input 2
[AFR5]
TIM1_CH
PB1/ AIN1
[TIM1_CH2N]
Analog
2N
input 1
[AFR5]
TIM1_CH
PB0/ AIN0
[TIM1_CH1N]
Analog
1N
I/O
I/O
X
X
X
X
X
X
-
-
O1
O1
X
X
X
X
Port B0
Port E7
input 0
[AFR5]
Analog
-
23
-
-
-
PE7/ AIN8
input 8
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Pinout and pin description
STM8S105x4/6
Table 5. STM8S105x4/6 pin description (continued)
Pin number
Input
Output
Alternate
function
after
remap
[option
bit]
Main
function
(after
Default
alternate
function
Pin name
Type
reset)
Analog
24 22
-
-
PE6/ AIN9
I/O
I/O
X
X
X
X
X
X
-
-
O1
O1
X
X
X
X
Port E6
Port E5
-
-
input 9(3)
SPI
master/
slave
25 23 17 22 PE5/ SPI_NSS
select
Timer 1 -
channel
PC1/
26 24 18 23
TIM1_CH1/
UART2_CK
I/O
X
X
X
HS O3
X
X
Port C1 1/UART2
synchron
-
ous clock
PC2/
TIM1_CH2
Timer 1-
Port C2
27 25 19 24
28 26 20 25
I/O
I/O
I/O
X
X
X
X
X
X
X
X
X
HS O3
HS O3
X
X
X
X
X
X
-
-
-
channel 2
PC3/
TIM1_CH3
Timer 1 -
Port C3
channel 3
PC4/
TIM1_CH4
Timer 1 -
Port C4
29
-
21 26
HS O3
HS O3
channel 4
30 27 22 27 PC5/ SPI_SCK
I/O
S
X
-
X
-
X
-
X
-
Port C5 SPI clock
I/O ground
-
-
-
31 28
32 29
-
-
-
-
VSSIO_2
VDDIO_2
-
-
-
-
-
-
S
-
-
-
-
I/O power supply
SPI
master
out/slave
33 30 23 28 PC6/ SPI_MOSI I/O
X
X
X
X
X
X
HS O3
HS O3
X
X
X
X
Port C6
-
-
in
SPI
Port C7 masterin/
slave out
PC7/ SPI_
34 31 24 29
I/O
MISO
35 32
36 33
-
-
-
-
PG0
PG1
I/O
I/O
X
X
X
X
-
-
-
-
O1
O1
X
X
X
X
Port G0
Port G1
-
-
-
-
Timer 1 -
break
input
PE3/
TIM1_BKIN
37
-
-
-
I/O
X
X
X
-
O1
X
X
Port E3
-
T
38 34
39 35
-
-
-
-
PE2/ I 2C_ SDA I/O
PE1/ I2C_ SCL I/O
X
X
-
-
X
X
-
-
O1
O1
-
-
Port E2 I 2C data
Port E1 I 2C clock
-
-
(4)
T
(4)
28/121
DocID14771 Rev 15
STM8S105x4/6
Pin number
Pinout and pin description
Table 5. STM8S105x4/6 pin description (continued)
Input
Output
Alternate
Main
function
(after
function
after
remap
[option
bit]
Default
alternate
function
Pin name
Type
reset)
Configura
40 36
-
-
PE0/ CLK_CCO I/O
PD0/
X
X
X
X
X
X
HS O3
X
X
X
X
Port E0 ble clock
output
-
TIM1_BK
IN
[AFR3]/
CLK_CC
O [AFR2]
TIM3_CH2
[TIM1_BKIN]
Timer 3 -
Port D0
41 37 25 30
I/O
HS O3
channel 2
[CLK_CCO]
SWIM
data
interface
42 38 26 31 PD1/ SWIM(5)
PD2/
I/O
I/O
I/O
I/O
I/O
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
HS O4
X
X
X
X
X
Port D1
Port D2
Port D3
Port D4
Port D5
-
Timer 3 - TIM2_CH
channel 1 3 [AFR1]
43 39 27 32
TIM3_CH1
HS O3
HS O3
HS O3
X
X
X
X
[TIM2_CH3]
PD3/
Timer 2 - ADC_ET
channel 2 R [AFR0]
44 40 28
45 41 29
46 42 30
1
2
3
TIM2_CH2
[ADC_ETR]
PD4/
TIM2_CH1
[BEEP]
BEEP
Timer 2 -
channel 1
output
[AFR7]
UART2
data
transmit
PD5/
UART2_TX
-
O1
-
-
UART2
data
receive
PD6/
UART2_RX
47 43 31
48 44 32
4
5
I/O
I/O
X
X
X
X
X
X
-
-
O1
O1
X
X
X
X
Port D6
Port D7
PD7/ TLI
[TIM1_CH4
Top level TIM1_CH
interrupt 4 [AFR4]
1. A pull-up is applied to PF4 during the reset phase. This pin is input floating after reset release.
2. AIN12 is not selectable in ADC scan mode or with analog watchdog.
3. In 44-pin package, AIN9 cannot be used by ADC scan mode.
4. In the open-drain output column, ‘T’ defines a true open-drain I/O (P-buffer, weak pull-up and protection diode to VDD are
not implemented).
5. The PD1 pin is in input pull-up during the reset phase and after internal reset release.
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Pinout and pin description
STM8S105x4/6
5.1
Alternate function remapping
As shown in the rightmost column of the pin description table, some alternate functions can
be remapped at different I/O ports by programming one of eight AFR (alternate function
remap) option bits. When the remapping option is active, the default alternate function is no
longer available.
To use an alternate function, the corresponding peripheral must be enabled in the peripheral
registers.
Alternate function remapping does not effect GPIO capabilities of the I/O ports (see the
GPIO section of the family reference manual, RM0016).
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Memory and register map
6
Memory and register map
6.1
Memory map
Figure 7. Memory map
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The following table lists the boundary addresses for each memory size. The top of the stack
is at the RAM end address in each case.
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Memory and register map
STM8S105x4/6
Table 6. Flash, data EEPROM and RAM boundary address
Memory area
Size (byte)
Start address
End address
32 K
16 K
2 K
0x00 8000
0x00 8000
0x00 0000
0x00 4000
0x00 FFFF
0x00 BFFF
0x00 07FF
0x00 43FF
Flash program memory
RAM
Data EEPROM
1024
6.2
Register map
6.2.1
I/O port hardware register map
Table 7. I/O port hardware register map
Address
Block
Register label
Register name
Reset status
0x00 5000
0x00 5001
0x00 5002
0x00 5003
0x00 5004
0x00 5005
0x00 5006
0x00 5007
0x00 5008
0x00 5009
0x00 500A
0x00 500B
0x00 500C
0x00 500D
0x00 500E
0x00 500F
0x00 5010
0x00 5011
0x00 5012
0x00 5013
PA_ODR
PA_IDR
Port A data output latch register
Port A input pin value register
Port A data direction register
Port A control register 1
0x00
0xXX(1)
0x00
Port A
PA_DDR
PA_CR1
PA_CR2
PB_ODR
PB_IDR
PB_DDR
PB_CR1
PB_CR2
PC_ODR
PB_IDR
PC_DDR
PC_CR1
PC_CR2
PD_ODR
PD_IDR
PD_DDR
PD_CR1
PD_CR2
0x00
Port A control register 2
0x00
Port B data output latch register
Port B input pin value register
Port B data direction register
Port B control register 1
0x00
0xXX(1)
Port B
Port C
Port D
0x00
0x00
Port B control register 2
0x00
Port C data output latch register
Port C input pin value register
Port C data direction register
Port C control register 1
0x00
0xXX(1)
0x00
0x00
Port C control register 2
0x00
Port D data output latch register
Port D input pin value register
Port D data direction register
Port D control register 1
0x00
0xXX(1)
0x00
0x02
Port D control register 2
0x00
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Address
Memory and register map
Table 7. I/O port hardware register map (continued)
Block
Register label
Register name
Reset status
0x00 5014
0x00 5015
0x00 5016
0x00 5017
0x00 5018
0x00 5019
0x00 501A
0x00 501B
0x00 501C
0x00 501D
0x00 501E
0x00 501F
0x00 5020
0x00 5021
0x00 5022
0x00 5023
0x00 5024
0x00 5025
0x00 5026
0x00 5027
0x00 5028
0x00 5029
0x00 502A
0x00 502B
0x00 502C
PE_ODR
PE_IDR
PE_DDR
PE_CR1
PE_CR2
PF_ODR
PF_IDR
PF_DDR
PF_CR1
PF_CR2
PG_ODR
PG_IDR
PG_DDR
PG_CR1
PG_CR2
PH_ODR
PH_IDR
PH_DDR
PH_CR1
PH_CR2
PI_ODR
PI_IDR
Port E data output latch register
Port E input pin value register
Port E data direction register
Port E control register 1
0x00
0xXX(1)
Port E
0x00
0x00
Port E control register 2
0x00
Port F data output latch register
Port F input pin value register
Port F data direction register
Port F control register 1
0x00
0xXX(1)
Port F
Port G
Port H
Port I
0x00
0x00
Port F control register 2
0x00
Port G data output latch register
Port G input pin value register
Port G data direction register
Port G control register 1
0x00
0xXX(1)
0x00
0x00
Port G control register 2
0x00
Port H data output latch register
Port H input pin value register
Port H data direction register
Port H control register 1
0x00
0xXX(1)
0x00
0x00
Port H control register 2
0x00
Port I data output latch register
Port I input pin value register
Port I data direction register
Port I control register 1
0x00
0xXX(1)
PI_DDR
PI_CR1
0x00
0x00
PI_CR2
Port I control register 2
0x00
1. Depends on the external circuitry.
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Memory and register map
STM8S105x4/6
Reset status
6.2.2
General hardware register map
Table 8. General hardware register map
Address
Block
Register label
Register name
0x00 5050 to 0x00 5059
0x00 505A
Reserved area (10 byte)
FLASH_CR1
Flash control register 1
Flash control register 2
0x00
0x00
0x00 505B
FLASH_CR2
Flash complementary control
register 2
0x00 505C
0x00 505D
0x00 505E
FLASH_NCR2
0xFF
0x00
0xFF
Flash
FLASH _FPR
Flash protection register
Flash complementary
protection register
FLASH _NFPR
Flash in-application
programming status register
0x00 505F
FLASH _IAPSR
0x00
0x00
0x00
0x00 5060 to 0x00 5061
0x00 5062
Reserved area (2 byte)
Flash program memory
unprotection register
Flash
FLASH _PUKR
0x00 5063
Reserved area (1 byte)
Data EEPROM unprotection
register
0x00 5064
Flash
FLASH _DUKR
0x00 5065 to 0x00 509F
0x00 50A0
Reserved area (59 byte)
External interrupt control
register 1
EXTI_CR1
0x00
0x00
ITC
External interrupt control
register 2
0x00 50A1
EXTI_CR2
0x00 50A2 to 0x00 50B2
0x00 50B3
Reserved area (17 byte)
RST
RST_SR
Reset status register
0xXX(1)
0x00 50B4 to 0x00 50BF
0x00 50C0
Reserved area (12 byte)
CLK_ICKR
CLK
Internal clock control register 0x01
External clock control register 0x00
0x00 50C1
CLK_ECKR
0x00 50C2
Reserved area (1 byte)
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Address
Memory and register map
Table 8. General hardware register map (continued)
Block
Register label
CLK_CMSR
Register name
Reset status
0xE1
0x00 50C3
0x00 50C4
0x00 50C5
0x00 50C6
Clock master status register
Clock master switch register
Clock switch control register
Clock divider register
CLK_SWR
0xE1
0xXX
0x18
CLK_SWCR
CLK_CKDIVR
Peripheral clock gating
register 1
0x00 50C7
0x00 50C8
0x00 50C9
CLK_PCKENR1
CLK_CSSR
0xFF
Clock security system register 0x00
CLK
Configurable clock control
register
CLK_CCOR
0x00
Peripheral clock gating
0xFF
0x00 50CA
CLK_PCKENR2
register 2
HSI clock calibration trimming
register
0x00 50CC
0x00 50CD
CLK_HSITRIMR
CLK_SWIMCCR
0x00
SWIM clock control register
0bXXXX XXX0
0x00 50CE to 0x00 50D0 Reserved area (3 byte)
0x00 50D1
WWDG_CR
WWDG_WR
WWDG control register
WWDR window register
0x7F
0x7F
WWDG
0x00 50D2
0x00 50D3 to 00 50DF
0x00 50E0
Reserved area (13 byte)
IWDG_KR
IWDG key register
0xXX(2)
0x00
0x00 50E1
IWDG
IWDG_PR
IWDG prescaler register
IWDG reload register
0x00 50E2
IWDG_RLR
0xFF
0x00 50E3 to 0x00 50EF
0x00 50F0
Reserved area (13 byte)
AWU_CSR1
AWU control/status register 1 0x00
AWU asynchronous prescaler
0x3F
0x00 50F1
0x00 50F2
AWU_APR
AWU
buffer register
AWU timebase selection
AWU_TBR
0x00
register
0x00 50F3
BEEP
BEEP_CSR
BEEP control/status register
0x1F
0x00 50F4 to 0x00 50FF
0x00 5200
Reserved area (12 byte)
SPI_CR1
SPI control register 1
SPI control register 2
SPI interrupt control register
SPI status register
0x00
0x00
0x00
0x02
0x00
0x00 5201
SPI_CR2
0x00 5202
SPI_ICR
0x00 5203
SPI_SR
SPI
0x00 5204
SPI_DR
SPI data register
0x00 5205
SPI_CRCPR
SPI_RXCRCR
SPI_TXCRCR
SPI CRC polynomial register 0x07
0x00 5206
SPI Rx CRC register
SPI Tx CRC register
0xFF
0xFF
0x00 5207
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Memory and register map
STM8S105x4/6
Reset status
Table 8. General hardware register map (continued)
Address
Block
Register label
Register name
0x00 5208 to 0x00 520F
0x00 5210
Reserved area (8 byte)
I2C_CR1
I2C control register 1
I2C control register 2
I2C frequency register
0x00
0x00
0x00
0x00 5211
I2C_CR2
0x00 5212
I2C_FREQR
I2C_OARL
0x00 5213
I2C Own address register low 0x00
I2C Own address register
high
0x00 5214
I2C_OARH
0x00
0x00 5215
0x00 5216
0x00 5217
0x00 5218
0x00 5219
0x00 521A
0x00 521B
0x00 521C
0x00 521D
Reserved
I2C_DR
I2C data register
0x00
0x00
0x00
0x0X
0x00
I2C
I2C_SR1
I2C status register 1
I2C status register 2
I2C status register 3
I2C interrupt control register
I2C_SR2
I2C_SR3
I2C_ITR
I2C_CCRL
I2C_CCRH
I2C_TRISER
I2C Clock control register low 0x00
I2C Clock control register high 0x00
I2C TRISE register
0x02
0x00
I2C packet error checking
register
0x00 521E
I2C_PECR
0x00 521F to 0x00 522F
0x00 5230 to 0x00 523F
0x00 5240
Reserved area (17 byte)
Reserved area (6 byte)
UART2_SR
UART2 status register
0xC0
0xXX
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00 5241
UART2_DR
UART2 data register
0x00 5242
UART2_BRR1
UART2 baud rate register 1
UART2 baud rate register 2
UART2 control register 1
UART2 control register 2
UART2 control register 3
UART2 control register 4
UART2 control register 5
UART2 control register 6
UART2 guard time register
UART2 prescaler register
0x00 5243
UART2_BRR2
0x00 5244
UART2_CR1
0x00 5245
UART2_CR2
UART2
0x00 5246
UART2_CR3
0x00 5247
UART2_CR4
UART2_CR5
0x00 5248
0x00 5249
UART2_CR6
0x00 524A
UART2_GTR
0x00 524B
UART2_PSCR
0x00 524C to 0x00 524F
Reserved area (4 byte)
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Address
Memory and register map
Table 8. General hardware register map (continued)
Block
Register label
TIM1_CR1
Register name
Reset status
0x00
0x00 5250
0x00 5251
TIM1 control register 1
TIM1 control register 2
TIM1_CR2
0x00
0x00
TIM1 slave mode control
register
0x00 5252
TIM1_SMCR
0x00 5253
0x00 5254
0x00 5255
0x00 5256
TIM1_ETR
TIM1_IER
TIM1_SR1
TIM1_SR2
TIM1 external trigger register 0x00
TIM1 interrupt enable register 0x00
TIM1 status register 1
TIM1 status register 2
0x00
0x00
TIM1 event generation
register
0x00 5257
0x00 5258
0x00 5259
0x00 525A
0x00 525B
0x00 525C
0x00 525D
TIM1_EGR
0x00
0x00
0x00
0x00
0x00
0x00
0x00
TIM1 capture/compare mode
register 1
TIM1_CCMR1
TIM1_CCMR2
TIM1_CCMR3
TIM1_CCMR4
TIM1_CCER1
TIM1_CCER2
TIM1 capture/compare mode
register 2
TIM1 capture/compare mode
register 3
TIM1 capture/compare mode
register 4
TIM1 capture/compare enable
register 1
TIM1
TIM1 capture/compare enable
register 2
0x00 525E
0x00 525F
0x00 5260
0x00 5261
0x00 5262
0x00 5263
TIM1_CNTRH
TIM1_CNTRL
TIM1_PSCRH
TIM1_PSCRL
TIM1_ARRH
TIM1_ARRL
TIM1 counter high
TIM1 counter low
0x00
0x00
TIM1 prescaler register high 0x00
TIM1 prescaler register low 0x00
TIM1 auto-reload register high 0xFF
TIM1 auto-reload register low 0xFF
TIM1 repetition counter
register
0x00 5264
0x00 5265
0x00 5266
0x00 5267
0x00 5268
0x00 5269
TIM1_RCR
0x00
TIM1 capture/compare
0x00
TIM1_CCR1H
TIM1_CCR1L
TIM1_CCR2H
TIM1_CCR2L
TIM1_CCR3H
register 1 high
TIM1 capture/compare
0x00
register 1 low
TIM1 capture/compare
0x00
register 2 high
TIM1 capture/compare
0x00
register 2 low
TIM1 capture/compare
0x00
register 3 high
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Memory and register map
STM8S105x4/6
Table 8. General hardware register map (continued)
Address
0x00 526A
Block
Register label
Register name
Reset status
TIM1 capture/compare
register 3 low
TIM1_CCR3L
0x00
TIM1 capture/compare
register 4 high
0x00 526B
0x00 526C
TIM1_CCR4H
TIM1_CCR4L
0x00
0x00
TIM1 capture/compare
register 4 low
TIM1
0x00 526D
TIM1_BKR
TIM1_DTR
TIM1_OISR
TIM1 break register
0x00
0x00
0x00 526E
TIM1 dead-time register
0x00 526F
TIM1 output idle state register 0x00
0x00 5270 to 0x00 52FF
Reserved area (147 byte)
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Address
Memory and register map
Table 8. General hardware register map (continued)
Block
Register label
TIM2_CR1
Register name
Reset status
0x00
0x00 5300
0x00 5301
0x00 5302
0x00 5303
TIM2 control register 1
TIM2_IER
TIM2_SR1
TIM2_SR2
TIM2 Interrupt enable register 0x00
TIM2 status register 1
TIM2 status register 2
0x00
0x00
TIM2 event generation
register
0x00 5304
0x00 5305
0x00 5306
0x00 5307
0x00 5308
0x00 5309
TIM2_EGR
0x00
0x00
0x00
0x00
0x00
0x00
TIM2 capture/compare mode
register 1
TIM2_CCMR1
TIM2_CCMR2
TIM2_CCMR3
TIM2_CCER1
TIM2_CCER2
TIM2 capture/compare mode
register 2
TIM2 capture/compare mode
register 3
TIM2 capture/compare enable
register 1
TIM2 capture/compare enable
register 2
0x00 530A
0x00 530B
0x00 530C
0x00 530D
0x00 530E
TIM2_CNTRH
TIM2_CNTRL
TIM2_PSCR
TIM2_ARRH
TIM2_ARRL
TIM2 counter high
TIM2 counter low
0x00
0x00
0x00
TIM2
IM2 prescaler register
TIM2 auto-reload register high 0xFF
TIM2 auto-reload register low 0xFF
TIM2 capture/compare
0x00
0x00 530F
0x00 5310
0x00 5311
0x00 5312
0x00 5313
TIM2_CCR1H
TIM2_CCR1L
TIM2_CCR2H
TIM2_CCR2L
TIM2_CCR3H
TIM2_CCR3L
register 1 high
TIM2 capture/compare
0x00
register 1 low
TIM2 capture/compare reg. 2
high
0x00
TIM2 capture/compare
0x00
register 2 low
TIM2 capture/compare
0x00
register 3 high
TIM2 capture/compare
0x00
0x00 5314
register 3 low
0x00 5315 to 0x00 531F
Reserved area (11 byte)
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Memory and register map
STM8S105x4/6
Table 8. General hardware register map (continued)
Address
0x00 5320
Block
Register label
TIM3_CR1
Register name
Reset status
TIM3 control register 1
0x00
0x00 5321
0x00 5322
0x00 5323
TIM3_IER
TIM3_SR1
TIM3_SR2
TIM3 Interrupt enable register 0x00
TIM3 status register 1
TIM3 status register 2
0x00
0x00
TIM3 event generation
register
0x00 5324
0x00 5325
0x00 5326
0x00 5327
TIM3_EGR
0x00
0x00
0x00
0x00
TIM3 capture/compare mode
register 1
TIM3_CCMR1
TIM3_CCMR2
TIM3_CCER1
TIM3 capture/compare mode
register 2
TIM3 capture/compare enable
register 1
0x00 5328
0x00 5329
0x00 532A
0x00 532B
0x00 532C
TIM3
TIM3_CNTRH
TIM3_CNTRL
TIM3_PSCR
TIM3_ARRH
TIM3_ARRL
TIM3 counter high
TIM3 counter low
0x00
0x00
0x00
TIM3 prescaler register
TIM3 auto-reload register high 0xFF
TIM3 auto-reload register low 0xFF
TIM3 capture/compare
0x00
0x00 532D
0x00 532E
0x00 532F
0x00 5330
TIM3_CCR1H
TIM3_CCR1L
TIM3_CCR2H
TIM3_CCR2L
register 1 high
TIM3 capture/compare
0x00
register 1 low
TIM3 capture/compare reg. 2
high
0x00
TIM3 capture/compare
0x00
register 2 low
0x00 5331 to 0x00 533F
0x00 5340
Reserved area (15 byte)
TIM4_CR1
TIM4 control register 1
0x00
0x00 5341
TIM4_IER
TIM4 interrupt enable register 0x00
0x00 5342
TIM4_SR
TIM4 status register
0x00
0x00
TIM4 event generation
register
0x00 5343
TIM4
TIM4_EGR
0x00 5344
TIM4_CNTR
TIM4_PSCR
TIM4_ARR
TIM4 counter
0x00
0x00
0xFF
0x00 5345
TIM4 prescaler register
TIM4 auto-reload register
0x00 5346
0x00 5347 to 0x00 53DF
0x00 53E0 to 0x00 53F3
0x00 53F4 to 0x00 53FF
Reserved area (153 byte)
ADC1 ADC_DBxR
Reserved area (12 byte)
ADC data buffer registers
0x00
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Address
Memory and register map
Table 8. General hardware register map (continued)
Block
Register label
ADC_CSR
Register name
Reset status
0x00
0x00 5400
0x00 5401
0x00 5402
0x00 5403
0x00 5404
0x00 5405
ADC control/status register
ADC_CR1
ADC_CR2
ADC_CR3
ADC_DRH
ADC_DRL
ADC configuration register 1 0x00
ADC configuration register 2 0x00
ADC configuration register 3 0x00
ADC data register high
ADC data register low
0xXX
0xXX
ADC Schmitt trigger disable
register high
0x00 5406
0x00 5407
0x00 5408
0x00 5409
0x00 540A
0x00 540B
0x00 540C
0x00 540D
0x00 540E
ADC_TDRH
ADC_TDRL
ADC_HTRH
ADC_HTRL
ADC_LTRH
ADC_LTRL
0x00
0x00
0x03
0xFF
0x00
0x00
0x00
0x00
0x00
0x00
ADC Schmitt trigger disable
register low
ADC high threshold register
high
ADC1
cont’d
ADC high threshold register
low
ADC low threshold register
high
ADC low threshold register
low
ADC analog watchdog status
register high
ADC_AWSRH
ADC_AWSRL
ADC _AWCRH
ADC_AWCRL
ADC analog watchdog status
register low
ADC analog watchdog control
register high
ADC analog watchdog control
register low
0x00 540F
0x00 5410 to 0x00 57FF
Reserved area (1008 byte)
1. Depends on the previous reset source.
2. Write-only register.
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Memory and register map
STM8S105x4/6
6.2.3
CPU/SWIM/debug module/interrupt controller registers
Table 9. CPU/SWIM/debug module/interrupt controller registers
Block Register label Register name
Accumulator
Reset
status
Address
0x00 7F00
A
0x00
0x00 7F01
PCE
PCH
PCL
XH
Program counter extended 0x00
0x00 7F02
Program counter high
Program counter low
X index register high
X index register low
Y index register high
Y index register low
Stack pointer high
0x00
0x00
0x00
0x00
0x00
0x00
0x03
0xFF
0x28
0x00 7F03
0x00 7F04
0x00 7F05
CPU(1)
XL
0x00 7F06
YH
0x00 7F07
YL
0x00 7F08
SPH
SPL
CCR
0x00 7F09
Stack pointer low
0x00 7F0A
0x00 7F0B to 0x00 7F5F
Condition code register
Reserved area (85 byte)
CPU
Global configuration
register
0x00 7F60
0x00 7F70
0x00 7F71
0x00 7F72
0x00 7F73
0x00 7F74
0x00 7F75
0x00 7F76
CFG_GCR
ITC_SPR1
ITC_SPR2
ITC_SPR3
ITC_SPR4
ITC_SPR5
ITC_SPR6
ITC_SPR7
ITC_SPR8
0x00
0xFF
0xFF
0xFF
0xFF
0xFF
0xFF
0xFF
0xFF
Interrupt software priority
register 1
Interrupt software priority
register 2
Interrupt software priority
register 3
Interrupt software priority
register 4
ITC
Interrupt software priority
register 5
Interrupt software priority
register 6
Interrupt software priority
register 7
Interrupt software priority
register 8
0x00 7F77
0x00 7F78 to 0x00 7F79
0x00 7F80
Reserved area (2 byte)
SWIM control status
register
SWIM
SWIM_CSR
0x00
0x00 7F81 to 0x00 7F8F
Reserved area (15 byte)
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Address
Memory and register map
Table 9. CPU/SWIM/debug module/interrupt controller registers (continued)
Reset
status
Block
Register label
Register name
DM breakpoint 1 register
extended byte
0x00 7F90
0x00 7F91
0x00 7F92
0x00 7F93
0x00 7F94
0x00 7F95
0x00 7F96
0x00 7F97
0x00 7F98
0x00 7F99
DM_BK1RE
0xFF
DM breakpoint 1 register
high byte
DM_BK1RH
DM_BK1RL
DM_BK2RE
DM_BK2RH
DM_BK2RL
DM_CR1
0xFF
0xFF
0xFF
0xFF
0xFF
0x00
0x00
0x10
0x00
DM breakpoint 1 register
low byte
DM breakpoint 2 register
extended byte
DM breakpoint 2 register
high byte
DM
DM breakpoint 2 register
low byte
DM debug module control
register 1
DM debug module control
register 2
DM_CR2
DM debug module
control/status register 1
DM_CSR1
DM debug module
control/status register 2
DM_CSR2
0x00 7F9A
DM_ENFCTR
DM enable function register 0xFF
0x00 7F9B to 0x00 7F9F
Reserved area (5 byte)
1. Accessible by debug module only.
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Interrupt vector mapping
STM8S105x4/6
7
Interrupt vector mapping
Table 10. Interrupt mapping
Wakeup from
Description
Wakeup from
active-halt mode
IRQ no.
Source block
Vector address
halt mode
-
-
RESET
TRAP
Reset
Yes
-
Yes
-
0x00 8000
0x00 8004
Software interrupt
External top level
interrupt
0
TLI
-
-
0x00 8008
Auto wake up from
halt
1
2
3
AWU
CLK
-
Yes
-
0x00 800C
0x00 8010
0x00 8014
Clock controller
-
Port A external
interrupts
EXTI0
Yes(1)
Yes(1)
Port B external
interrupts
4
5
6
7
EXTI1
EXTI2
EXTI3
EXTI4
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
0x00 8018
0x00 801C
0x00 8020
0x00 8024
Port C external
interrupts
Port D external
interrupts
Port E external
interrupts
8
9
Reserved
Reserved
SPI
-
-
-
0x00 8028
0x00 802C
0x00 8030
-
-
-
10
End of transfer
Yes
Yes
TIM1 update/
overflow/
underflow/ trigger/
break
11
TIM1
-
-
0x00 8034
TIM1 capture/
compare
12
13
14
15
16
TIM1
TIM2
TIM2
TIM3
TIM3
-
-
-
-
-
-
-
-
-
-
0x00 8038
0x00 803C
0x00 8040
0x00 8044
0x00 8048
TIM2 update/
overflow
TIM2 capture/
compare
TIM3 update/
overflow
TIM3 capture/
compare
17
18
19
Reserved
Reserved
I2C
-
-
-
0x00 804C
0x00 8050
0x00 8054
-
-
-
I2C interrupt
Yes
Yes
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IRQ no.
Interrupt vector mapping
Vector address
Table 10. Interrupt mapping (continued)
Wakeup from
halt mode
Wakeup from
active-halt mode
Source block
Description
20
21
UART2
UART2
Tx complete
-
-
-
-
0x00 8058
0x00 805C
Receive register
DATA FULL
ADC1 end of
22
ADC1
conversion/ analog -
watchdog interrupt
-
0x00 8060
TIM4 update/
overflow
23
TIM4
Flash
-
-
-
0x00 8064
0x00 8068
24
EOP/WR_PG_DIS -
0x00 806C to
0x00 807C
Reserved
1. Except PA1.
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Option byte
STM8S105x4/6
8
Option byte
Option byte contain configurations for device hardware features as well as the memory
protection of the device. They are stored in a dedicated block of the memory. Except for the
ROP (read-out protection) byte, each option byte has to be stored twice, in a regular form
(OPTx) and a complemented one (NOPTx) for redundancy.
Option byte can be modified in ICP mode (via SWIM) by accessing the EEPROM address
shown in the table below.
Option byte can also be modified ‘on the fly’ by the application in IAP mode, except the ROP
option that can only be modified in ICP mode (via SWIM).
Refer to the STM8S Flash programming manual (PM0051) and STM8 SWIM
communication protocol and debug module user manual (UM0470) for information on SWIM
programming procedures.
Table 11. Option byte
Option
byte
no.
Option bits
3
Factory
default
setting
Option
name
Addr.
7
6
5
4
2
1
0
Read-out
protection
(ROP)
0x4800
OPT0
ROP [7:0]
0x00
0x4801
0x4802
0x4803
OPT1
NOPT1
OPT2
UBC [7:0]
0x00
0xFF
0x00
User boot
code (UBC)
NUBC [7:0]
Alternate
function
remapping
(AFR)
AFR7
AFR6
AFR5
AFR4
AFR3
AFR2
AFR1
AFR0
0x4804
NOPT2
NAFR7
NAFR6
NAFR5
NAFR4
NAFR3
NAFR2
NAFR1
NAFR0
0xFF
HSI
IWDG
_HW
WWDG
_HW
WWDG
_HALT
0x4805h
0x4806
0x4807
0x4808
OPT3
NOPT3
OPT4
Reserved
Reserved
LSI _ EN
0x00
0xFF
0x00
0xFF
TRIM
Misc. option
Clock option
NHSI
TRIM
NLSI
_ EN
NIWDG
_HW
NWWDG
_HW
NWWG
_HALT
CKAWU
SEL
Reserved
EXT CLK
PRS C1
PRS C0
NEXT
CLK
NCKA
NOPT4
Reserved
NPRSC1
NPR SC0
WUSEL
0x4809
0x480A
0x480B
0x480C
0x480D
0x480E
0x480F
0x48FD
OPT5
NOPT5
OPT6
NOPT6
OPT7
NOPT7
-
HSECNT [7:0]
NHSECNT [7:0]
Reserved
0x00
0xFF
0x00
0xFF
0x00
0xFF
-
HSE clock
startup
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
-
Reserved
-
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Option byte
Table 11. Option byte (continued)
Option bits
Option
byte
no.
Factory
default
setting
Option
Addr.
name
7
6
5
4
3
2
1
0
0x487E
Bootloader
0x487F
OPTBL
BL[7:0]
0x00
0xFF
NOPTBL
NBL[7:0]
Table 12. Option byte description
Description
Option byte no.
ROP[7:0] Memory readout protection (ROP)
0xAA: Enable readout protection (write access via SWIM protocol)
OPT0
Note: Refer to the family reference manual (RM0016) section on
Flash/EEPROM memory readout protection for details.
UBC[7:0] User boot code area
0x00: no UBC, no write-protection
0x01: Page 0 to 1 defined as UBC, memory write-protected
0x02: Page 0 to 3 defined as UBC, memory write-protected
0x03: Page 0 to 4 defined as UBC, memory write-protected
...
OPT1
0x3E: Pages 0 to 63 defined as UBC, memory write-protected
Other values: Reserved
Note: Refer to the family reference manual (RM0016) section on Flash write
protection for more details.
AFR[7:0]
Refer to the following table for the description of the alternate function
remapping description of bits [7:2].
OPT2
HSITRIM: High speed internal clock trimming register size
0: 3-bit trimming supported in CLK_HSITRIMR register
1: 4-bit trimming supported in CLK_HSITRIMR register
LSI_EN: Low speed internal clock enable
0: LSI clock is not available as CPU clock source
1: LSI clock is available as CPU clock source
IWDG_HW: Independent watchdog
OPT3
0: IWDG Independent watchdog activated by software
1: IWDG Independent watchdog activated by hardware
WWDG_HW: Window watchdog activation
0: WWDG window watchdog activated by software
1: WWDG window watchdog activated by hardware
WWDG_HALT: Window watchdog reset on halt
0: No reset generated on halt if WWDG active
1: Reset generated on halt if WWDG active
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Option byte
STM8S105x4/6
Table 12. Option byte description (continued)
Description
Option byte no.
EXTCLK: External clock selection
0: External crystal connected to OSCIN/OSCOUT
1: External clock signal on OSCIN
CKAWUSEL: Auto wake-up unit/clock
0: LSI clock source selected for AWU
OPT4
1: HSE clock with prescaler selected as clock source for AWU
PRSC[1:0] AWU clock prescaler
0x: 16 MHz to 128 kHz prescaler
10: 8 MHz to 128 kHz prescaler
11: 4 MHz to 128 kHz prescaler
HSECNT[7:0]: HSE crystal oscillator stabilization time
0x00: 2048 HSE cycles
OPT5
0xB4: 128 HSE cycles
0xD2: 8 HSE cycles
0xE1: 0.5 HSE cycles
OPT6
OPT7
Reserved
Reserved
BL[7:0]: Bootloader option byte
For STM8S products, this option is checked by the boot ROM code after
reset. Depending on the content of addresses 0x487E, 0x487F, and 0x8000
(reset vector), the CPU jumps to the bootloader or to the reset vector. Refer
to the UM0560 (STM8L/S bootloader manual) for more details.
OPTBL
For STM8L products, the bootloader option bytes are on addresses 0xXXXX
and 0xXXXX+1 (2 byte). These option bytes control whether the bootloader is
active or not. For more details, refer to the UM0560 (STM8L/S bootloader
manual) for more details.
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Option byte
8.1
Alternate function remapping bits
Table 13. Alternate function remapping bits [7:0] of OPT2
Option byte no.
Description(1)
AFR7 Alternate function remapping option 7
0: AFR7 remapping option inactive: Default alternate functions.(2)
1: Port D4 alternate function = BEEP.
AFR6 Alternate function remapping option 6
0: AFR6 remapping option inactive: Default alternate function.(2)
1: Port B5 alternate function = I2C_SDA; port B4 alternate function =
I2C_SCL.
AFR5 Alternate function remapping option 5
0: AFR5 remapping option inactive: Default alternate function.(2)
1: Port B3 alternate function = TIM1_ETR; port B2 alternate function =
TIM1_NCC3; port B1 alternate function = TIM1_CH2N; port B0 alternate
function = TIM1_CH1N.
AFR4 Alternate function remapping option 4
0: AFR4 remapping option inactive: Default alternate functions.(2)
1: Port D7 alternate function = TIM1_CH4.
OPT2
AFR3 Alternate function remapping option 3
0: AFR3 remapping option inactive: Default alternate function.(2)
1: Port D0 alternate function = TIM1_BKIN.
AFR2 Alternate function remapping option 2
0: AFR2 remapping option inactive: Default alternate functions.(2)
1: Port D0 alternate function = CLK_CCO. Note: AFR2 option has priority
over AFR3 if both are activated.
AFR1 Alternate function remapping option 1
0: AFR1 remapping option inactive: Default alternate functions.(2)
1: Port A3 alternate function = TIM3_CH1; port D2 alternate function
TIM2_CH3
AFR0 Alternate function remapping option 0
0: AFR0 remapping option inactive: Default alternate functions.(2)
1: Port D3 alternate function = ADC_ETR.
1. Do not use more than one remapping option in the same port.
2. Refer to STM8S105x4/6 pin descriptions.
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Unique ID
STM8S105x4/6
9
Unique ID
The devices feature a 96-bit unique device identifier which provides a reference number that
is unique for any device and in any context. The 96 bits of the identifier can never be altered
by the user.
The unique device identifier can be read in single byte and may then be concatenated using
a custom algorithm.
The unique device identifier is ideally suited:
For use as serial numbers
For use as security keys to increase the code security in the program memory while
using and combining this unique ID with software cryptographic primitives and
protocols before programming the internal memory.
To activate secure boot processes
Table 14. Unique ID registers (96 bits)
Content
Address
Unique ID bits
description
7
6
5
4
3
2
1
0
0x48CD
U_ID[7:0]
U_ID[15:8]
U_ID[23:16]
U_ID[31:24]
U_ID[39:32]
U_ID[47:40]
U_ID[55:48]
U_ID[63:56]
U_ID[71:64]
U_ID[79:72]
U_ID[87:80]
U_ID[95:88]
X co-ordinate on
the wafer
0x48CE
0x48CF
0x48D0
0x48D1
0x48D2
0x48D3
0x48D4
0x48D5
0x48D6
0x48D7
0x48D8
Y co-ordinate on
the wafer
Wafer number
Lot number
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Electrical characteristics
10
Electrical characteristics
10.1
Parameter conditions
Unless otherwise specified, all voltages are referred to V
.
SS
10.1.1
Minimum and maximum values
Unless otherwise specified the minimum and maximum values are guaranteed in the worst
conditions of ambient temperature, supply voltage and frequencies by tests in production on
100% of the devices with an ambient temperature at T = 25 °C, and T = T (given by
A
A
Amax
the selected temperature range).
Data based on characterization results, design simulation and/or technology characteristics
are indicated in the table footnotes and are not tested in production. Based on
characterization, the minimum and maximum values refer to sample tests and represent the
mean value plus or minus three times the standard deviation (mean ± 3 Σ).
10.1.2
Typical values
Unless otherwise specified, typical data are based on T = 25 °C, V = 5.0 V. They are
A
DD
given only as design guidelines and are not tested.
Typical ADC accuracy values are determined by characterization of a batch of samples from
a standard diffusion lot over the full temperature range, where 95% of the devices have an
error less than or equal to the value indicated (mean ± 2 Σ).
10.1.3
10.1.4
Typical curves
Unless otherwise specified, all typical curves are given only as design guidelines and are
not tested.
Typical current consumption
For typical current consumption measurements, VDD, VDDIO and VDDA are connected
together in the configuration shown in the following figure.
Figure 8. Supply current measurement conditions
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9''
9''$
9'',2
966
966$
966,2
06Yꢀꢃꢀꢄꢐ9ꢂ
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Electrical characteristics
STM8S105x4/6
10.1.5
Loading capacitor
The loading conditions used for pin parameter measurement are shown in Figure 9.
Figure 9. Pin loading conditions
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10.1.6
Pin input voltage
The input voltage measurement on a pin of the device is described in Figure 10.
Figure 10. Pin input voltage
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9,1
06Yꢀꢇꢍꢃꢂ9ꢂ
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Electrical characteristics
10.2
Absolute maximum ratings
Stresses above those listed as ‘absolute maximum ratings’ may cause permanent damage
to the device. This is a stress rating only and functional operation of the device under these
conditions is not implied. Exposure to maximum rating conditions for extended periods may
affect device reliability.
Table 15. Voltage characteristics
Symbol
Ratings
Min
Max
6.5
Unit
(1)
V
DDx - VSS
Supply voltage (including VDDA and VDDIO
)
-0.3
V
Input voltage on true open drain pins (PE1, PE2)(2)
6.5
VSS - 0.3
VIN
V
Input voltage on any other pin(2)
VSS - 0.3 VDD + 0.3
|VDDx - VDD
|
Variations between different power pins
Variations between all the different ground pins
-
-
50
50
mV
|VSSx - VSS
|
see Absolute maximum ratings
(electrical sensitivity) on
page 89
VESD
Electrostatic discharge voltage
1. All power (VDD) and ground (VSS) pins must always be connected to the external power supply
2. IINJ(PIN) must never be exceeded. This is implicitly insured if VIN maximum is respected. If VIN maximum
cannot be respected, the injection current must be limited externally to the IINJ(PIN) value. A positive
injection is induced by VIN > VDD while a negative injection is induced by VIN < VSS. For true open-drain
pads, there is no positive injection current, and the corresponding VIN maximum must always be respected
Table 16. Current characteristics
Max.(1)
Symbol
Ratings
Unit
IVDD
IVSS
Total current into VDD power lines (source)(2)
Total current out of VSS ground lines (sink)(1)
Output current sunk by any I/O and control pin
Output current source by any I/Os and control pin
100
80
mA
20
IIO
-20
Total output current sourced (sum of all I/O and control pins)
for devices with two VDDIO pins(3)
200
100
160
80
Total output current sourced (sum of all I/O and control pins)
for devices with one VDDIO pin(3)
ΣIIO
Total output current sunk (sum of all I/O and control pins) for
devices with two VSSIO pins(3)
Total output current sunk (sum of all I/O and control pins) for
devices with one VSSIO pin(3)
Injected current on NRST pin
±4
±4
(4) (5)
(4)
IINJ(PIN)
Injected current on OSCIN pin
Injected current on any other pin(6)
Total injected current (sum of all I/O and control pins)(6)
±4
ΣIINJ(PIN)
±20
1. Data based on characterization results, not tested in production.
2. All power (VDD, VDDIO, VDDA) and ground (VSS, VSSIO, VSSA) pins must always be connected to the external
supply.
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3. I/O pins used simultaneously for high current source/sink must be uniformly spaced around the package
between the VDDIO/VSSIO pins.
4. IINJ(PIN) must never be exceeded. This condition is implicitly insured if VIN maximum is respected. If VIN
maximum cannot be respected, the injection current must be limited externally to the IINJ(PIN) value. A
positive injection is induced by VIN > VDD while a negative injection is induced by VIN < VSS. For true open-
drain pads, there is no positive injection current allowed and the corresponding VIN maximum must always
be respected.
5. Negative injection disturbs the analog performance of the device. See note in Section: TIM2, TIM3 - 16-bit
general purpose timers.
6. When several inputs are submitted to a current injection, the maximum ΣIINJ(PIN) is the absolute sum of the
positive and negative injected currents (instantaneous values). These results are based on characterization
with ΣIINJ(PIN) maximum current injection on four I/O port pins of the device.
Table 17. Thermal characteristics
Symbol
Ratings
Value
Unit
TSTG
TJ
Storage temperature range
65 to 150
°C
Maximum junction temperature
150
10.3
Operating conditions
The device must be used in operating conditions that respect the parameters described in
the table below. In addition, full account must be taken of all physical capacitor
characteristics and tolerances.
Table 18. General operating conditions
Symbol
fCPU
Parameter
Conditions
Min
Max
Unit
Internal CPU clock frequency
Standard operating voltage
-
-
0
16
MHz
V
VDD/VDDIO
2.95
5.5
CEXT: capacitance of external
capacitor
-
470
3300
nF
(1)
VCAP
ESR of external capacitor
ESL of external capacitor
-
-
0.3
15
Ω
at 1 MHz(2)
nH
44- and 48-pin
devices, with output
on eight standard
ports, two high sink
ports and two open
drain ports
-
-
443
360
Power dissipation at TA = 85 °C
for suffix 6 or TA= 125° C for
suffix 3
(3)
simultaneously(4)
PD
mW
32-pin package, with
output on eight
standard ports and
two high sink ports
simultaneously(4)
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Electrical characteristics
Table 18. General operating conditions (continued)
Symbol
Parameter
Conditions
Min
Max
Unit
Ambient temperature for suffix
6 version
Maximum power
dissipation
TA
-40
85
Ambient temperature for suffix
3 version
Maximum power
dissipation
TA
TJ
-40
125
°C
Suffix 6 version
Suffix 3 version
-40
-40
105
130
Junction temperature range
1. Care should be taken when selecting the capacitor, due to its tolerance, as well as the parameter
dependency on temperature, DC bias and frequency in addition to other factors. The parameter maximum
value must be respected for the full application range.
2. This frequency of 1 MHz as a condition for VCAP parameters is given by design of internal regulator.
3. To calculate PDmax(TA), use the formula PDmax=(TJmax- TA)/JA (see Section 12: Thermal characteristics)
with the value for TJmax given in the previous table and the value for JA given in Section 12: Thermal
characteristics.
4. See Section 12: Thermal characteristics.
Figure 11. f
versus V
DD
CPUmax
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Table 19. Operating conditions at power-up/power-down
Symbol
Parameter
Conditions
Min
Max
Unit
Typ
2(1)
VDD rise time rate
-
-
-
-
tVDD
tTEMP
µs/V
ms
2(1)
-
VDD fall time rate
-
Reset release delay
VDD rising
1.7(1)
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Electrical characteristics
STM8S105x4/6
Table 19. Operating conditions at power-up/power-down (continued)
Symbol
Parameter
Conditions
Min
Max
Unit
Typ
Power-on reset
threshold
VIT+
-
2.65
2.8
2.95
V
Brown-out reset
threshold
VIT-
-
-
2.58
-
2.65
70
2.88
-
Brown-out reset
hysteresis
VHYS(BOR)
mV
1. Guaranteed by design, not tested in production.
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Electrical characteristics
10.3.1
VCAP external capacitor
The stabilization for the main regulator is achieved by connecting an external capacitor
C
to the V
pin. C
is specified in Table 18. Care should be taken to limit the series
EXT
CAP
EXT
inductance to less than 15 nH.
Figure 12. External capacitor C
EXT
(6/
&
(65
5/HDN
06Yꢀꢇꢍꢃꢃ9ꢂ
1. ESR is the equivalent series resistance and ESL is the equivalent inductance.
10.3.2
Supply current characteristics
The current consumption is measured as illustrated in Figure 10: Pin input voltage.
Total current consumption in run mode
Table 20. Total current consumption with code execution in run mode at V = 5 V
DD
Max(1)
Symbol
Parameter
Conditions
HSE crystal osc. (16 MHz)
Typ
Unit
3.2
-
HSE user ext. clock
(16 MHz)
fCPU = fMASTER = 16 MHz
2.6
2.5
3.2
3.2
2.2
2.0
-
Supply
HSI RC osc. (16 MHz)
current in
Run mode,
code
HSE user ext. clock
(16 MHz)
1.6
IDD(RUN)
mA
fCPU = fMASTER /128 = 125 kHz
executed
from RAM
HSI RC osc. (16 MHz)
HSI RC osc. (16 MHz/8)
1.3
fCPU = fMASTER /128 =
15.625 kHz
0.75
f
CPU = fMASTER = 128 kHz
LSI RC osc. (128 kHz)
0.55
7.7
-
-
HSE crystal osc. (16 MHz)
HSE user ext. clock
(16 MHz)
fCPU = fMASTER = 16 MHz
7.0
8.0
Supply
HSI RC osc. (16 MHz)
7.0
1.5
8.0
-
current in
Run mode,
code
HSI RC osc. (16 MHz/8)(2)
fCPU = fMASTER = 2 MHz
IDD(RUN)
mA
fCPU = fMASTER /128 = 125 kHz HSI RC osc. (16 MHz)
1.35
2.0
executed
from Flash
fCPU = fMASTER /128 =
HSI RC osc. (16 MHz/8)
15.625 kHz
0.75
0.6
-
-
fCPU = fMASTER = 128 kHz
LSI RC osc. (128 kHz)
1. Data based on characterization results, not tested in production.
2. Default clock configuration measured with all peripherals off.
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Electrical characteristics
STM8S105x4/6
Table 21. Total current consumption with code execution in run mode at V = 3.3 V
DD
Max(1)
Symbol
Parameter
Conditions
HSE crystal osc. (16 MHz)
Typ
Unit
2.8
-
HSE user ext. clock
(16 MHz)
fCPU = fMASTER = 16 MHz
2.6
2.5
3.2
3.2
2.2
2.0
-
Supply
HSI RC osc. (16 MHz)
current in
Run mode,
code
HSE user ext. clock
(16 MHz)
1.6
IDD(RUN)
mA
f
CPU = fMASTER /128 = 125 kHz
executed
from RAM
HSI RC osc. (16 MHz)
HSI RC osc. (16 MHz/8)
1.3
fCPU = fMASTER /128 =
15.625 kHz
0.75
fCPU = fMASTER = 128 kHz
LSI RC osc. (128 kHz)
0.55
7.3
-
-
HSE crystal osc. (16 MHz)
HSE user ext. clock
(16 MHz)
fCPU = fMASTER = 16 MHz
7.0
8.0
Supply
HSI RC osc. (16 MHz)
7.0
1.5
8.0
-
current in
Run mode,
code
HSI RC osc. (16 MHz/8)(2)
fCPU = fMASTER = 2 MHz
IDD(RUN)
mA
fCPU = fMASTER /128 = 125 kHz HSI RC osc. (16 MHz)
1.35
2.0
executed
from Flash
f
CPU = fMASTER /128 =
HSI RC osc. (16 MHz/8)
LSI RC osc. (128 kHz)
0.75
0.6
-
-
15.625 kHz
f
CPU = fMASTER = 128 kHz
1. Data based on characterization results, not tested in production.
2. Default clock configuration measured with all peripherals off.
Total current consumption in wait mode
Table 22. Total current consumption in wait mode at V = 5 V
DD
Max(1)
Symbol
Parameter
Conditions
HSE crystal osc. (16 MHz)
Typ
Unit
2.15
-
HSE user ext. clock
(16 MHz)
fCPU = fMASTER = 16 MHz
1.55
2.0
Supply
current in
wait mode
HSI RC osc. (16 MHz)
1.5
1.3
1.9
-
IDD(WFI)
mA
f
CPU = fMASTER /128 = 125 kHz HSI RC osc. (16 MHz)
fCPU = fMASTER /s128 =
15.625 kHz
HSI RC osc. (16 MHz/8)(2)
LSI RC osc. (128 kHz)
0.7
0.5
-
-
fCPU = fMASTER = 128 kHz
1. Data based on characterization results, not tested in production.
2. Default clock configuration measured with all peripherals off.
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Electrical characteristics
Table 23. Total current consumption in wait mode at V = 3.3 V
DD
Max(1)
Symbol
Parameter
Conditions
Typ
Unit
HSE crystal osc. (16 MHz)
1.75
-
HSE user ext. clock
(16 MHz)
f
CPU = fMASTER = 16 MHz
1.55
2.0
Supply
current in
wait mode
HSI RC osc. (16 MHz)
1.5
1.3
1.9
-
IDD(WFI)
mA
fCPU = fMASTER /128 = 125 kHz HSI RC osc. (16 MHz)
fCPU = fMASTER /s128 =
HSI RC osc. (16 MHz/8)(2)
15.625 kHz
0.7
0.5
-
-
f
CPU = fMASTER = 128 kHz
LSI RC osc. (128 kHz)
1. Data based on characterization results, not tested in production.
2. Default clock configuration measured with all peripherals off.
Total current consumption in active halt mode
Table 24. Total current consumption in active halt mode at V = 5 V
DD
Conditions
Main
voltage
regulator
Max at Max at
85 °C(1) 85 °C(1)
Symbol Parameter
Typ
Unit
Flash mode(3)
Clock source
(MVR)(2)
HSE crystal osc.
(16 MHz)
Operating mode
Operating mode
1080
200
-
320
-
-
400
-
LSI RC osc. (128 kHz)
On
Power down
mode
HSE crystal osc.
(16 MHz)
Supply
1030
current in
active halt
mode
IDD(AH)
µA
Power down
mode
LSI RC osc. (128 kHz)
LSI RC osc. (128 kHz)
LSI RC osc. (128 kHz)
140
68
270
120
60
350
220
150
Operating mode
Off
Power down
mode
12
1. Data based on characterization results, not tested in production.
2. Configured by the REGAH bit in the CLK_ICKR register.
3. Configured by the AHALT bit in the FLASH_CR1 register.
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Table 25. Total current consumption in active halt mode at V = 3.3 V
DD
Conditions
Main
voltage
regulator
Max at Max at
85 °C(1) 85 °C(1)
Symbol Parameter
Typ
Unit
Flash mode(3)
Clock source
(MVR)(2)
HSE crystal osc.
(16 MHz)
Operating mode
Operating mode
680
200
630
-
320
-
-
400
-
LSI RC osc. (128 kHz)
On
Power down
mode
HSE crystal osc.
(16 MHz)
Supply
current in
active halt
mode
IDD(AH)
µA
Power down
mode
LSI RC osc. (128 kHz)
LSI RC osc. (128 kHz)
LSI RC osc. (128 kHz)
140
66
270
120
60
350
220
150
Operating mode
Off
Power down
mode
10
1. Data based on characterization results, not tested in production.
2. Configured by the REGAH bit in the CLK_ICKR register.
3. Configured by the AHALT bit in the FLASH_CR1 register.
Total current consumption in halt mode
Table 26. Total current consumption in halt mode at V = 5 V
DD
Max at Max at
85 °C(1) 85 °C(1)
Symbol
Parameter
Conditions
Typ
Unit
Flash in operating mode, HSI
clock after wakeup
62
90
25
150
80
Supply current in halt
mode
IDD(H)
µA
Flash in power-down mode,
HSI clock after wakeup
6.5
1. Data based on characterization results, not tested in production.
Table 27. Total current consumption in halt mode at V = 3.3 V
DD
Max at Max at
85 °C(1) 85 °C(1)
Symbol
Parameter
Conditions
Typ
Unit
Flash in operating mode, HSI
clock after wakeup
60
90
20
150
80
Supply current in halt
mode
IDD(H)
µA
Flash in power-down mode,
HSI clock after wakeup
4.5
1. Data based on characterization results, not tested in production.
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Electrical characteristics
Low power mode wakeup times
Table 28. Wakeup times
Conditions
Max(1)
Symbol
Parameter
Typ
Unit
Wakeup time from wait
mode to run mode(2)
See note(3)
tWU(WFI)
0 to 16 MHz
-
Wakeup time from run
mode(2)
tWU(WFI)
fCPU= fMASTER= 16 MHz
0.56
1(6)
-
Flash in
MVR voltage
operating
Wakeup time active halt
mode to run mode(2)
HSI (after
wakeup)
2(6)
tWU(AH)
regulator on(4)
mode(5)
Flash in
MVR voltage
operating
Wakeup time active halt
mode to run mode(2)
HSI (after
wakeup)
3(6)
tWU(AH)
tWU(AH)
tWU(AH)
-
-
-
regulator off(4)
mode(5)
µs
Flash in
MVR voltage
operating
Wakeup time active halt
mode to run mode(2)
HSI (after
wakeup)
48(6)
50(6)
regulator off(4)
mode(5)
Flash in
MVR voltage
Wakeup time active halt
mode to run mode(2)
HSI (after
wakeup)
power-down
regulator off(4)
mode(5)
Wakeup time from halt
mode to run mode(2)
tWU(H)
Flash in operating mode(5)
52
54
-
-
Wakeup time from halt
mode to run mode(2)
tWU(H)
Flash in power-down mode(5)
1. Data based on characterization results, not tested in production.
2. Measured from interrupt event to interrupt vector fetch
3. tWU(WFI) = 2 x 1/fmaster + 67 x 1/fCPU
4. Configured by the REGAH bit in the CLK_ICKR register.
5. Configured by the AHALT bit in the FLASH_CR1 register.
6. Plus 1 LSI clock depending on synchronization.
Total current consumption and timing in forced reset state
Table 29. Total current consumption and timing in forced reset state
Max(1)
Symbol
Parameter
Conditions
Typ
Unit
VDD = 5 V
500
400
-
-
Supply current in reset
state(2)
IDD(R)
µA
VDD = 3.3 V
Reset pin release to
vector fetch
tRESETBL
-
-
150
µs
1. Data guaranteed by design, not tested in production.
2. Characterized with all I/Os tied to VSS
.
Current consumption of on-chip peripherals
Subject to general operating conditions for V and T .
DD
A
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STM8S105x4/6
HSI internal RC/f
= f
= 16 MHz, V = 5 V
CPU MASTER DD
Table 30. Peripheral current consumption
Parameter
Symbol
Typ
Unit
IDD(TIM1)
IDD(TIM2)
IDD(TIM3)
IDD(TIM4)
TIM1 supply current(1)
TIM2 supply current(1)
230
115
90
TIM3 supply current(1)
TIM4 supply current(1)
30
µA
IDD(UART2) UART2 supply current (2)
110
45
IDD(SPI)
IDD(I2C)
IDD(ADC1)
SPI supply current (2)
I2C supply current(2)
65
ADC1 supply current when converting(3)
955
1. Data based on a differential IDD measurement between reset configuration and timer counter running at
16 MHz. No IC/OC programmed (no I/O pads toggling). Not tested in production.
2. Data based on a differential IDD measurement between the on-chip peripheral when kept under reset and
not clocked and the on-chip peripheral when clocked and not kept under reset. No I/O pads toggling. Not
tested in production.
3. Data based on a differential IDD measurement between reset configuration and continuous A/D
conversions. Not tested in production.
Current consumption curves
The following figures show typical current consumption measured with code executing in
RAM.
Figure 13. Typ I
vs. V HSE user external clock, f
= 16 MHz
CPU
DD(RUN)
DD
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Electrical characteristics
Figure 14. Typ I
vs. f
HSE user external clock, V = 5 V
CPU DD
DD(RUN)
Figure 15. Typ I
vs. V HSI RC osc, f = 16 MHz
CPU
DD(RUN)
DD
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STM8S105x4/6
Figure 16. Typ I
vs. V HSE external clock, f
= 16 MHz
CPU
DD(WFI)
DD
Figure 17. Typ I
vs. f
HSE external clock, V = 5 V
CPU DD
DD(WFI)
64/121
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Electrical characteristics
Figure 18. Typ I
vs. V HSI RC osc., f
= 16 MHz
CPU
DD(WFI)
DD
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STM8S105x4/6
10.3.3
External clock sources and timing characteristics
HSE user external clock
Subject to general operating conditions for V and T .
DD
A
Table 31. HSE user external clock characteristics
Symbol
Parameter
Conditions
Min
Max
Unit
User external clock
source frequency
fHSE_ext
-
0
16
MHz
OSCIN input pin high
level voltage
(1)
VHSEH
-
0.7 x VDD
VSS
VDD + 0.3 V
0.3 x VDD
+1
V
OSCIN input pin low
level voltage
(1)
VHSEL
-
OSCIN input leakage
current
ILEAK_HSE
VSS < VIN < VDD
-1
µA
1. Data based on characterization results, not tested in production.
Figure 19. HSE external clock source
+6(+
+6(/
I
+6(
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Electrical characteristics
HSE crystal/ceramic resonator oscillator
The HSE clock can be supplied with a 1 to 16 MHz crystal/ceramic resonator oscillator. All
the information given in this paragraph is based on characterization results with specified
typical external components. In the application, the resonator and the load capacitors have
to be placed as close as possible to the oscillator pins in order to minimize output distortion
and startup stabilization time. Refer to the crystal resonator manufacturer for more details
(frequency, package, accuracy...).
Table 32. HSE oscillator characteristics
Symbol
fHSE
Parameter
Conditions
Min
Typ
Max
Unit
External high speed
oscillator frequency
-
-
-
1
-
-
220
-
16
-
MHz
k
RF
Feedback resistor
Recommended load
capacitance(2)
C(1)
-
20
pF
C = 20 pF
6 (start up)
-
-
-
-
fOSC = 16 MHz
1.6 (stabilized)(3)
HSE oscillator power
consumption
IDD(HSE)
mA
C = 10 pF
6 (start up)
1.2 (stabilized)(3)
fOSC = 16 MHz
Oscillator
transconductance
gm
tSU(HSE)
-
5
-
-
-
-
mA/V
ms
(4)
Startup time
VDD is stabilized
1
1. C is approximately equivalent to 2 x crystal Cload.
2. The oscillator selection can be optimized in terms of supply current using a high quality resonator with small Rm value.
Refer to crystal manufacturer for more details
3. Data based on characterization results, not tested in production.
4. tSU(HSE) is the start-up time measured from the moment it is enabled (by software) to a stabilized 16 MHz oscillation is
reached. This value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer.
DocID14771 Rev 15
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Electrical characteristics
STM8S105x4/6
Figure 20. HSE oscillator circuit diagram
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HSE oscillator critical gm equation
gmcrit = 2 fHSE2 Rm2Co + C2
R : Notional resistance (see crystal specification)
m
L : Notional inductance (see crystal specification)
m
C : Notional capacitance (see crystal specification)
m
Co: Shunt capacitance (see crystal specification)
C
= C = C: Grounded external capacitance
L1
L2
g
m » gmcrit
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Electrical characteristics
10.3.4
Internal clock sources and timing characteristics
Subject to general operating conditions for V and T .
DD
A
High speed internal RC oscillator (HSI)
Table 33. HSI oscillator characteristics
Symbol
Parameter
Frequency
Conditions
Min
Typ
Max
Unit
fHSI
-
-
16
-
MHz
User-trimmed with
CLK_HSITRIMR register for
given VDD and TA
conditions(1)
Accuracy of HSI oscillator
-
-
1(2)
VDD V,
-1.0
-
1.0
2.0
TA 25 °C(3)
ACCHS
%
HSI oscillator accuracy
(factory calibrated)
VDD= 5 V,
-25°C TA 85 °C
-2.0
-
2.95 V VDD 5.5 V,
-40°C TA 125 °C
-3.0(3)
-
-
3.0(3)
1.0(2)
250(3)
HSI oscillator wakeup
time including calibration
tsu(HSI)
-
-
-
-
µs
HSI oscillator power
consumption
IDD(HSI)
170
µA
1. Refer to application note.
2. Guaranteed by design, not tested in production.
3. Data based on characterization results, not tested in production.
Figure 21. Typical HSI accuracy @ V = 5 V vs 5 temperatures
DD
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Figure 22. Typical HSI frequency variation vs V @ 4 temperatures
DD
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Electrical characteristics
Low speed internal RC oscillator (LSI)
Subject to general operating conditions for V and T .
DD
A
Table 34. LSI oscillator characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
fLSI
Frequency
LSI oscillator wakeup time
-
-
-
110
128
150
7(1)
-
kHz
µs
tsu(LSI)
-
-
-
IDD(LSI) LSI oscillator power consumption
1. Guaranteed by design, not tested in production.
5
µA
Figure 23. Typical LSI frequency variation vs V @ 4 temperatures
DD
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Electrical characteristics
STM8S105x4/6
10.3.5
Memory characteristics
RAM and hardware registers
Table 35. RAM and hardware registers
Symbol
Parameter
Conditions
Min
Unit
(2)
VRM
Data retention mode(1)
Halt mode (or reset)
VIT-max
V
1. Minimum supply voltage without losing data stored in RAM (in halt mode or under reset) or in hardware
registers (only in halt mode). Guaranteed by design, not tested in production.
2. Refer to Section 10.3: Operating conditions for the value of VIT-max
.
Flash program memory/data EEPROM memory
Table 36. Flash program memory/data EEPROM memory
Symbol
Parameter
Conditions
Min(1) Typ Max
Unit
Operating voltage
(all modes, execution/write/erase)
VDD
fCPU≤ 16 MHz
2.95
-
-
5.5
6.6
V
Standard programming time (including
erase) for byte/word/block
(1 byte/4 byte/128 byte)
-
6
tprog
ms
Fast programming time for 1 block
(128 byte)
-
-
-
3
3
-
3.33
terase
Erase time for 1 block (128 byte)
-
3.33
Erase/write cycles
TA = +85 °C
TA = +125 °C
10k
-
-
(program memory)(2)
NRW
cycle
Erase/write cycles (data memory)(2)
300k 1M
Data retention (program and data
memory) after 10k erase/write cycles
at TA= +55 °C
T
T
RET = 55 °C
20
-
-
tRET
year
mA
Data retention (data memory) after
300k erase/write cycles at
TA= +125°C
RET = 85 °C
1
-
-
-
-
Supply current (Flash programming or
erasing for 1 to 128 byte)
IDD
-
2
1. Data based on characterization results, not tested in production.
2. The physical granularity of the memory is 4 byte, so cycling is performed on 4 byte even when a
write/erase operation addresses a single byte.
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Electrical characteristics
10.3.6
I/O port pin characteristics
General characteristics
Subject to general operating conditions for V and T unless otherwise specified. All
DD
A
unused pins must be kept at a fixed voltage, using the output mode of the I/O for example or
an external pull-up or pull-down resistor.
Table 37. I/O static characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VIL
Input low level voltage
Input high level voltage
Hysteresis(1)
-0.3 V
-
-
0.3 x VDD
V
VIH
Vhys
Rpu
VDD = 5 V
0.7 x VDD
VDD + 0.3 V
-
700
55
-
mV
Pull-up resistor
VDD = 5 V, VIN = VSS
30
80
k
Fast I/Os
Load = 50 pF
-
-
-
-
-
-
-
-
-
-
-
-
-
-
35(2)
125(2)
20(2)
Rise and fall time
(10% - 90%)
tR, tF
ns
ns
Standard and high sink I/Os
Load = 50 pF
Fast I/Os
Load = 20 pF
Rise and fall time
(10% - 90%)
tR, tF
Standard and high sink I/Os
Load = 20 pF
50(2)
Digital input leakage
current
Ilkg
VSS VIN VDD
VSS VIN VDD
±1(3)
µA
nA
µA
Analog input leakage
current
Ilkg ana
Ilkg(inj)
±250(3)
±1(3)
Leakage current in
adjacent I/O
Injection current ±4 mA
1. Hysteresis voltage between Schmitt trigger switching levels. Based on characterization results, not tested in production.
2. Data guaranteed by design.
3. Data based on characterization results, not tested in production
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Figure 24. Typical V and V vs V @ 4
Figure 25. Typical pull-up current vs V @ 4
IL
IH
DD
DD
temperatures
temperatures
Figure 26. Typical pull-up resistance vs VDD @ 4 temperatures
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Table 38. Output driving current (standard ports)
Symbol
Parameter
Conditions
Min
Max
Unit
IIO= 10 mA,
VDD = 5 V
Output low level with 8
pins sunk
-
2.0
VOL
IIO= 4 mA,
Output low level with 4
pins sunk
-
1.0(1)
VDD = 3.3 V
V
IIO= 10 mA,
VDD = 5 V
Output high level with 8
pins sourced
2.4
-
-
VOH
IIO= 4 mA,
Output high level with 4
pins sourced
2.0(1)
VDD = 3.3 V
1. Data based on characterization results, not tested in production
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Electrical characteristics
Table 39. Output driving current (true open drain ports)
Symbol
Parameter
Conditions
Min
Max
Unit
IIO= 10 mA,
VDD = 5 V
Output low level with 2
pins sunk
-
1.0
VOL
IIO= 10 mA,
VDD = 3.3 V
Output low level with 2
pins sunk
-
-
1.5(1)
2.0(1)
V
IIO= 10 mA,
VDD = 5 V
Output high level with 2
pins sourced
VOH
1. Data based on characterization results, not tested in production
Table 40. Output driving current (high sink ports)
Symbol
Parameter
Conditions
Min
Max
Unit
IIO= 10 mA,
Output low level with 8
pins sunk
-
0.9
V
DD = 5 V
IIO= 10 mA,
DD = 3.3 V
VOL
-
1.1(1)
V
Output low level with 4
pins sunk
IIO= 20 mA,
VDD = 5 V
-
1.6(1)
V
IIO= 10 mA,
VDD = 5 V
Output high level with 8
pins sourced
3.8
-
-
-
IIO= 10 mA,
VDD = 3.3 V
VOH
1.9(1)
2.9(1)
Output high level with 4
pins sourced
IIO= 20 mA,
VDD = 5 V
1. Data based on characterization results, not tested in production.
10.3.7
Typical output level curves
The following figures show the typical output level curves measured with the output on a
single pin.
Figure 27. Typ. V @ V = 3.3 V (standard
Figure 28. Typ. V @ V = 5.0 V (standard
OL DD
OL
DD
ports)
ports)
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Figure 29. Typ. V @ V = 3.3 V (true open
Figure 30. Typ. V @ V = 5.0 V (true open
OL DD
OL
DD
drain ports)
drain ports)
Figure 31. Typ. V @ V = 3.3 V (high sink
Figure 32. Typ. V @ V = 5.0 V (high sink
OL DD
OL
DD
ports)
ports)
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Electrical characteristics
Figure 33. Typ. V
V
@ V = 3.3 V
Figure 34. Typ. V
V
@ V = 5.0 V
DD - OH
DD
DD - OH DD
(standard ports)
(standard ports)
Figure 35. Typ. V
V
@ V = 3.3 V (high
Figure 36. Typ. V
V
@ V = 5.0 V (high
DD - OH
DD
DD - OH DD
sink ports)
sink ports)
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STM8S105x4/6
10.3.8
Reset pin characteristics
Subject to general operating conditions for V and T unless otherwise specified.
DD
A
Table 41. NRST pin characteristics
Symbol
Parameter
Conditions
-
Min
Typ
Max
Unit
NRST input low level voltage(1)
NRST input high level voltage(1)
-0.3
-
0.3 x VDD
VDD+ 0.3
VIL(NRST)
0.7 x VDD
V
VIH(NRST)
VOL(NRST)
RPU(NRST)
IOL= 2 mA
-
-
NRST output low level voltage(1) IOL= 3 mA
-
30
-
0.5
80
75
-
NRST pull-up resistor(2)
-
-
-
-
55
-
k
ns
µs
tIFP(NRST) NRST input filtered pulse(3)
tINFP(NRST) NRST Input not filtered pulse(3)
tOP(NRST) NRST output pulse(3)
500
20
-
-
-
1. Data based on characterization results, not tested in production.
2. The RPU pull-up equivalent resistor is based on a resistive transistor.
3. Data guaranteed by design, not tested in production.
Figure 37. Typical NRST V and V vs V @ 4 temperatures
IL
IH
DD
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Electrical characteristics
Figure 38. Typical NRST pull-up resistance R vs V @ 4 temperatures
PU
DD
Figure 39. Typical NRST pull-up current I vs V @ 4 temperatures
pu
DD
The reset network shown in Figure 40 protects the device against parasitic resets. The user
must ensure that the level on the NRST pin can go below V max (see Table 41:
IL(NRST)
NRST pin characteristics), otherwise the reset is not taken into account internally.
For power consumption sensitive applications, the external reset capacitor value can be
reduced to limit the charge/discharge current. If NRST signal is used to reset external
circuitry, attention must be taken to the charge/discharge time of the external capacitor to
fulfill the external devices reset timing conditions. Minimum recommended capacity is
100 nF.
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Electrical characteristics
STM8S105x4/6
Figure 40. Recommended reset pin protection
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SPI serial peripheral interface
10.3.9
Unless otherwise specified, the parameters given in Table 42 are derived from tests
performed under ambient temperature, f frequency and V supply voltage
MASTER
DD
conditions. t
= 1/f
.
MASTER
MASTER
Refer to I/O port characteristics for more details on the input/output alternate function
characteristics (NSS, SCK, MOSI, MISO).
Table 42. SPI characteristics
Symbol
Parameter
Conditions(1)
Min
Max
Unit
Master mode
0
0
8
6
fSCK
1/tc(SCK)
SPI clock frequency
MHz
Slave mode
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Table 42. SPI characteristics (continued)
Symbol
tr(SCK
Parameter
Conditions(1)
Min
Max
Unit
)
SPI clock rise and fall
time
Capacitive load:
C = 30 pF
-
25
tf(SCK)
(2)
tsu(NSS)
NSS setup time
NSS hold time
Slave mode
Slave mode
4 * tMASTER
70
-
-
(2)
th(NSS)
(2)
tw(SCKH)
tw(SCKL)
SCK high and low time
Data input setup time
Master mode
tSCK/2 - 15 tSCK/2 + 15
(2)
(2)
Master mode
Slave mode
Master mode
Slave mode
5
5
-
tsu(MI)
tsu(SI)
(2)
-
(2)
7
-
th(MI)
th(SI)
Data input hold time
(2)
10
-
-
ns
(2)(3)
ta(SO)
Data output access time Slave mode
Data output disable time Slave mode
3* tMASTER
-
(2)(4)
tdis(SO)
25
Slave mode
(after enable edge)
(2)
(2)
tv(SO)
Data output valid time
-
73
36
-
Master mode (after
enable edge)
tv(MO)
Data output valid time
Data output hold time
-
Slave mode (after
enable edge)
(2)
(2)
th(SO)
28
12
Master mode (after
enable edge)
th(MO)
-
1. Parameters are given by selecting 10 MHz I/O output frequency.
2. Values based on design simulation and/or characterization results, and not tested in production.
3. Min time is for the minimum time to drive the output and the max time is for the maximum time to validate
the data.
4. Min time is for the minimum time to invalidate the output and the max time is for the maximum time to put
the data in Hi-Z.
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Figure 41. SPI timing diagram where slave mode and CPHA = 0
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1. Measurement points are at CMOS levels: 0.3 VDD and 0.7 VDD
.
Figure 42. SPI timing diagram where slave mode and CPHA = 1
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1. Measurement points are at CMOS levels: 0.3 VDD and 0.7 VDD
.
82/121
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Electrical characteristics
Figure 43. SPI timing diagram - master mode
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1. Measurement points are at CMOS levels: 0.3 VDD and 0.7 VDD
.
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Electrical characteristics
STM8S105x4/6
2
10.3.10 I C interface characteristics
2
Table 43. I C characteristics
Standard mode I2C Fast mode I2C(1)
Symbol
Parameter
Unit
Min(2)
Max(2)
Min(2) Max(2)
tw(SCLL)
tw(SCLH)
tsu(SDA)
th(SDA)
SCL clock low time
SCL clock high time
SDA setup time
4.7
4.0
-
-
-
-
1.3
0.6
-
-
-
µs
250
100
0(3)
0(4)
900(3)
SDA data hold time
tr(SDA)
tr(SCL)
SDA and SCL rise time
(VDD = 3 to 5.5 V)
ns
-
1000
300
-
300
tf(SDA)
tf(SCL)
SDA and SCL fall time
(VDD = 3 to 5.5 V)
-
-
300
th(STA)
START condition hold time
4.0
4.7
4.0
-
-
-
0.6
0.6
0.6
-
-
-
tsu(STA)
tsu(STO)
Repeated START condition setup time
STOP condition setup time
µs
pF
STOP to START condition time
(bus free)
tw(STO:STA)
4.7
-
1.3
-
-
Cb
Capacitive load for each bus line
-
400
400
1. fMASTER, must be at least 8 MHz to achieve max fast I2C speed (400 kHz)
Data based on standard I2C protocol requirement, not tested in production
2.
The maximum hold time of the start condition has only to be met if the interface does not stretch the low
time
3.
4.
The device must internally provide a hold time of at least 300 ns for the SDA signal in order to bridge the
undefined region of the falling edge of SCL
2
Figure 44. Typical application with I C bus and timing diagram
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84/121
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Electrical characteristics
10.3.11 10-bit ADC characteristics
Subject to general operating conditions for V
specified.
, f
, and T unless otherwise
DDA MASTER A
Table 44. ADC characteristics
Symbol
Parameter
Conditions
Min
Max
4
Unit
Typ
V
DD= 2.95 to 5.5 V
1
1
-
-
fADC
ADC clock frequency
MHz
VDD= 4.5 to 5.5 V
6
VDDA
VREF+
VREF-
Analog supply
-
-
-
3.0
-
-
-
5.5
Positive reference voltage
Negative reference voltage
2.75(1)
VSSA
VSSA
VDDA
V
V
0.5(1)
VDDA
-
-
-
Conversion voltage range(2)
Devices with
external
VAIN
VREF-
VREF+
V
REF+/VREF-
-
ADC = 4 MHz
Internal sample and hold
capacitor
CADC
-
3
-
pF
µs
f
-
-
-
0.75
0.5
-
-
-
(2)
tS
Minimum sampling time
fADC = 6 MHz
-
tSTAB
Wakeup time from standby
7.0
µs
µs
fADC = 4 MHz
3.5
Minimum total conversion time
(including sampling time, 10-
bit resolution)
tCONV
f
ADC = 6 MHz
-
2.33
14
µs
1/fADC
1. Data guaranteed by design, not tested in production.
2. During the sample time, the sampling capacitance, CAIN (3 pF max), can be charged/discharged by the
external source. The internal resistance of the analog source must allow the capacitance to reach its final
voltage level within tS. After the end of the sample time tS, changes of the analog input voltage have no
effect on the conversion result. Values for the sample clock tS depend on programming.
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Electrical characteristics
Symbol
STM8S105x4/6
Table 45. ADC accuracy with R < 10 k, V
= 5 V
AIN
DDA
Typ
Max(1)
Unit
Parameter
Conditions
fADC = 2 MHz
fADC = 4 MHz
fADC = 6 MHz
fADC = 2 MHz
1.0
1.4
1.6
0.6
1.1
1.2
0.2
0.6
0.8
0.7
0.7
0.8
0.6
0.6
0.6
2.5
3.0
3.5
2.0
2.5
2.5
2.0
|ET|
|EO|
|EG|
|ED|
|EL|
Total unadjusted error(2)
Offset error(2)
f
f
ADC = 4 MHz
ADC = 6 MHz
fADC = 2 MHz
ADC = 4 MHz
Gain error(2)
2.5
2.5
1.5
1.5
1.5
1.5
1.5
1.5
LSB
f
fADC = 6 MHz
fADC = 2 MHz
Differential linearity error(2)
Integral linearity error(2)
f
f
ADC = 4 MHz
ADC = 6 MHz
fADC = 2 MHz
ADC = 4 MHz
fADC = 6 MHz
f
1. Data based on characterization results, not tested in production.
2. ADC accuracy vs. negative injection current: Injecting negative current on any of the analog input pins
should be avoided as this significantly reduces the accuracy of the conversion being performed on another
analog input. It is recommended to add a Schottky diode (pin to ground) to standard analog pins which may
potentially inject negative current. Any positive injection current within the limits specified for IINJ(PIN) and
IINJ(PIN) in Section 10.3.6 does not affect the ADC accuracy.
Table 46. ADC accuracy with R < 10 k, V
= 3.3 V
AIN
DDA
Max(1)
2.0
2.5
1.5
2.0
1.5
2.0
1.0
1.0
1.5
1.5
Symbol
Parameter
Conditions
Typ
Unit
fADC = 2 MHz
1.1
1.6
0.7
1.3
0.2
0.5
0.7
0.7
0.6
0.6
|ET|
Total unadjusted error(2)
f
ADC = 4 MHz
fADC = 2 MHz
ADC = 4 MHz
fADC = 2 MHz
ADC = 4 MHz
fADC = 2 MHz
ADC = 4 MHz
fADC = 2 MHz
ADC = 4 MHz
|EO|
|EG|
|ED|
|EL|
Offset error(2)
f
Gain error(2)
LSB
f
Differential linearity error(2)
Integral linearity error(2)
f
f
1. Data based on characterization results, not tested in production.
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2. ADC accuracy vs. negative injection current: Injecting negative current on any of the analog input pins
should be avoided as this significantly reduces the accuracy of the conversion being performed on another
analog input. It is recommended to add a Schottky diode (pin to ground) to standard analog pins which may
potentially inject negative current. Any positive injection current within the limits specified for IINJ(PIN) and
IINJ(PIN) in Section 10.3.6 does not affect the ADC accuracy.
Figure 45. ADC accuracy characteristics
E
G
1023
1022
1021
V
– V
DDA
SSA
1LSB
= ----------------------------------------
IDEAL
1024
(2)
E
T
(3)
7
6
5
4
3
2
1
(1)
E
O
E
L
E
D
1 LSB
IDEAL
7
0
V
1
2
3
4
5
6
1021102210231024
V
DDA
SSA
1. Example of an actual transfer curve
2. The ideal transfer curve
3. End point correlation line
ET = Total unadjusted error: maximum deviation between the actual and the ideal transfer curves.
EO = Offset error: deviation between the first actual transition and the first ideal one.
EG = Gain error: deviation between the last ideal transition and the last actual one.
E
D = Differential linearity error: maximum deviation between actual steps and the ideal one.
EL = Integral linearity error: maximum deviation between any actual transition and the end point correlation
line.
Figure 46. Typical application with ADC
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1. Legend: RAIN = external resistance, CAIN = capacitors, Csamp = internal sample and hold capacitor.
DocID14771 Rev 15
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Electrical characteristics
STM8S105x4/6
10.3.12 EMC characteristics
Susceptibility tests are performed on a sample basis during product characterization.
Functional EMS (electromagnetic susceptibility)
While executing a simple application (toggling 2 LEDs through I/O ports), the product is
stressed by two electromagnetic events until a failure occurs (indicated by the LEDs).
ESD: Electrostatic discharge (positive and negative) is applied on all pins of the device
until a functional disturbance occurs. This test conforms with the IEC 61000-4-2
standard.
FTB: A burst of fast transient voltage (positive and negative) is applied to V and V
through a 100 pF capacitor, until a functional disturbance occurs. This test conforms
with the IEC 61000-4-4 standard.
DD
SS
A device reset allows normal operations to be resumed. The test results are given in the
table below based on the EMS levels and classes defined in application note AN1709 (EMC
design guide for STM microcontrollers).
Designing hardened software to avoid noise problems
EMC characterization and optimization are performed at component level with a typical
application environment and simplified MCU software. It should be noted that good EMC
performance is highly dependent on the user application and the software in particular.
Therefore it is recommended that the user applies EMC software optimization and
prequalification tests in relation with the EMC level requested for his application.
Software recommendations
The software flowchart must include the management of runaway conditions such as:
Corrupted program counter
Unexpected reset
Critical data corruption (control registers...)
Prequalification trials
Most of the common failures (unexpected reset and program counter corruption) can be
recovered by applying a low state on the NRST pin or the oscillator pins for 1 second.
To complete these trials, ESD stress can be applied directly on the device, over the range of
specification values. When unexpected behavior is detected, the software can be hardened
to prevent unrecoverable errors occurring. See application note AN1015 (Software
techniques for improving microcontroller EMC performance).
Table 47. EMS data
Symbol
Parameter
Conditions
Level/class
VDD 5 V, TA25 °C,
fMASTER 16 MHz (HSI clock),
Conforms to IEC 1000-4-2
Voltage limits to be applied on any I/O pin
to induce a functional disturbance
2/B(1)
VFESD
VDD 5 V, TA25 °C,
fMASTER 16 MHz (HSI clock),
Conforms to IEC 1000-4-4
Fast transient voltage burst limits to be
applied through 100 pF on VDD and VSS
pins to induce a functional disturbance
4/A(1)
VEFTB
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Electrical characteristics
1. Data obtained with HSI clock configuration, after applying the hardware recommendations described in
AN2860 (EMC guidelines for STM8S microcontrollers).
Electromagnetic interference (EMI)
Based on a simple application running on the product (toggling 2 LEDs through the I/O
ports), the product is monitored in terms of emission. This emission test is in line with the
norm IEC 61967-2 which specifies the board and the loading of each pin.
Table 48. EMI data
Conditions
(1)
Max fHSE/fCPU
Symbol
Parameter
Unit
Monitored
frequency band
General conditions
8 MHz/ 8 MHz/
8 MHz 16 MHz
0.1 MHz to 30 MHz
30 MHz to 130 MHz
130 MHz to 1 GHz
EMI level
13
23
14
19
VDD 5 V,
TA 25 °C,
LQFP48 package.
Conforming to
IEC 61967-2
Peak level
EMI level
dBµV
-
SEMI
-4.0
2.0
-4.0
1.5
1. Data based on characterization results, not tested in production.
Absolute maximum ratings (electrical sensitivity)
Based on two different tests (ESD, DLU and LU) using specific measurement methods, the
product is stressed to determine its performance in terms of electrical sensitivity. For more
details, refer to the application note AN1181.
Electrostatic discharge (ESD)
Electrostatic discharges (a positive then a negative pulse separated by 1 second) are
applied to the pins of each sample according to each pin combination. The sample size
depends on the number of supply pins in the device (3 parts x (n+1) supply pin). One model
can be simulated: Human body model. This test conforms to the JESD22-A114A/A115A
standard. For more details, refer to the application note AN1181.
Table 49. ESD absolute maximum ratings
Maximum
Symbol
Ratings
Conditions
Class
Unit
value(1)
Electrostatic discharge voltage TA 25°C, conforming to
VESD(HBM)
VESD(CDM)
A
2000
(Human body model)
JESD22-A114
V
Electrostatic discharge voltage
(Charge device model)
TA 25°C, conforming to
IV
1000
SD22-C101
1. Data based on characterization results, not tested in production
DocID14771 Rev 15
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90
Electrical characteristics
Static latch-up
STM8S105x4/6
Two complementary static tests are required on 10 parts to assess the latch-up
performance.
A supply overvoltage (applied to each power supply pin), and
A current injection (applied to each input, output and configurable I/O pin) are
performed on each sample.
This test conforms to the EIA/JESD 78 IC latch-up standard. For more details, refer to the
application note AN1181.
Table 50. Electrical sensitivities
Class(1)
Symbol
Parameter
Conditions
TA 25 °C
TA 85 °C
TA 125 °C
LU
Static latch-up class
A
1. Class description: A Class is an STMicroelectronics internal specification. All its limits are higher than the
JEDEC specifications, that means when a device belongs to class A it exceeds the JEDEC standard. B
class strictly covers all the JEDEC criteria (international standard).
90/121
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STM8S105x4/6
Package information
11
Package information
In order to meet environmental requirements, ST offers these devices in different grades of
®
®
ECOPACK packages, depending on their level of environmental compliance. ECOPACK
specifications, grade definitions and product status are available at: www.st.com.
®
ECOPACK is an ST trademark.
11.1
LQFP48 package information
Figure 47. LQFP48 - 48-pin, 7 x 7 mm low-profile quad flat package outline
3%!4).'
0,!.%
#
ꢄꢅꢁꢀ MM
'!5'% 0,!.%
CCC
#
$
,
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ꢂꢃ
0). ꢂ
)$%.4)&)#!4)/.
ꢂ
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E
ꢀ"?-%?6ꢁ
1. Drawing is not to scale.
DocID14771 Rev 15
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107
Package information
STM8S105x4/6
Table 51. LQFP48 - 48-pin, 7 x 7 mm low-profile quad flat package
mechanical data
millimeters
inches(1)
Symbol
Min
Typ
Max
Min
Typ
Max
A
A1
A2
b
-
0.050
1.350
0.170
0.090
8.800
6.800
-
-
1.600
0.150
1.450
0.270
0.200
9.200
7.200
-
-
0.0020
0.0531
0.0067
0.0035
0.3465
0.2677
-
-
0.0630
0.0059
0.0571
0.0106
0.0079
0.3622
0.2835
-
-
-
1.400
0.220
-
0.0551
0.0087
-
c
D
9.000
7.000
5.500
9.000
7.000
5.500
0.500
0.600
1.000
3.5°
0.3543
0.2756
0.2165
0.3543
0.2756
0.2165
0.0197
0.0236
0.0394
3.5°
D1
D3
E
8.800
6.800
-
9.200
7.200
-
0.3465
0.2677
-
0.3622
0.2835
-
E1
E3
e
-
-
-
-
L
0.450
-
0.750
-
0.0177
-
0.0295
-
L1
k
0°
7°
0°
7°
ccc
-
-
0.080
-
-
0.0031
1. Values in inches are converted from mm and rounded to 4 decimal digits.
92/121
DocID14771 Rev 15
STM8S105x4/6
Package information
Figure 48. LQFP48 - 48-pin, 7 x 7 mm low-profile quad flat package
recommended footprint
ꢄꢅꢀꢄ
ꢂꢅꢁꢄ
ꢄꢅꢃꢄ
ꢃꢇ
ꢁꢀ
ꢃꢈ
ꢁꢆ
ꢄꢅꢁꢄ
ꢈꢅꢃꢄ
ꢊꢅꢈꢄ ꢀꢅꢉꢄ
ꢈꢅꢃꢄ
ꢆꢉ
ꢂꢃ
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ꢂ
ꢂꢅꢁꢄ
ꢀꢅꢉꢄ
ꢊꢅꢈꢄ
AIꢂꢆꢊꢂꢂD
1. Dimensions are expressed in millimeters.
Device marking
The following figure gives an example of topside marking orientation versus pin 1 identifier
location.
Figure 49. LQFP48 marking example (package top view)
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1. Parts marked as "ES", "E" or accompanied by an Engineering Sample notification letter, are not yet
qualified and therefore not yet ready to be used in production and any consequences deriving from such
DocID14771 Rev 15
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107
Package information
STM8S105x4/6
usage will not be at ST charge. In no event, ST will be liable for any customer usage of these engineering
samples in production. ST Quality has to be contacted prior to any decision to use these Engineering
Samples to run qualification activity.
11.2
LQFP44 package information
Figure 50. LQFP44 - 44-pin, 10 x 10 mm low-profile quad flat package outline
3%!4).'
0,!.%
#
ꢄꢅꢁꢀ MM
'!5'% 0,!.%
#
CCC
+
,
$
,ꢂ
$ꢂ
$ꢃ
ꢁꢃ
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ꢂꢁ
ꢂ
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0). ꢂ
E
)$%.4)&)#!4)/.
ꢀ:@.&
1. Drawing is not to scale.
94/121
DocID14771 Rev 15
STM8S105x4/6
Package information
Table 52. LQFP44 - 44-pin, 10 x 10 mm low-profile quad flat package
mechanical data
millimeters
inches(1)
Symbol
Min
Typ
Max
Min
Typ
Max
A
A1
A2
b
-
0.050
1.350
0.300
0.090
11.800
9.800
-
-
1.600
0.150
1.450
0.450
0.200
12.200
10.200
-
-
0.0020
0.0531
0.0118
0.0035
0.4646
0.3858
-
-
0.0630
0.0059
0.0571
0.0177
0.0079
0.4803
0.4016
-
-
-
1.400
0.370
-
0.0551
0.0146
-
c
D
12.000
10.000
8.000
12.000
10.000
8.000
0.800
0.600
1.000
3.5°
0.4724
0.3937
0.3150
0.4724
0.3937
0.3150
0.0315
0.0236
0.0394
3.5°
D1
D3
E
11.800
9.800
-
12.200
10.200
-
0.4646
0.3858
-
0.4803
0.4016
-
E1
E3
e
-
-
-
-
L
0.450
-
0.750
-
0.0177
-
0.0295
-
L1
k
0°
7°
0°
7°
ccc
-
-
0.100
-
-
0.0039
1. Values in inches are converted from mm and rounded to 4 decimal digits.
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107
Package information
STM8S105x4/6
Figure 51. LQFP44 - 44-pin, 10 x 10 mm low-profile quad flat package
recommended footprint
ꢍꢍ
ꢀꢍ
ꢄꢈꢃ
ꢂ
ꢀꢀ
ꢂꢄꢈꢀ
ꢁꢀ
ꢂꢂ
ꢂꢁ
ꢁꢁ
ꢂꢈꢁ
ꢃꢈꢏ
ꢂꢁꢈꢑ
ꢍ<B)3
1. Dimensions are expressed in millimeters.
Device marking
The following figure gives an example of topside marking orientation versus pin 1 identifier
location.
96/121
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STM8S105x4/6
Package information
Figure 52. LQFP44 marking example (package top view)
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1. Parts marked as "ES", "E" or accompanied by an Engineering Sample notification letter, are not yet
qualified and therefore not yet ready to be used in production and any consequences deriving from such
usage will not be at ST charge. In no event, ST will be liable for any customer usage of these engineering
samples in production. ST Quality has to be contacted prior to any decision to use these Engineering
Samples to run qualification activity.
DocID14771 Rev 15
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107
Package information
STM8S105x4/6
11.3
LQFP32 package information
Figure 53. LQFP32 - 32-pin, 7 x 7 mm low-profile quad flat package outline
3%!4).'
0,!.%
#
ꢄꢅꢁꢀ MM
'!5'% 0,!.%
CCC
#
+
$
$ꢂ
$ꢃ
,
,ꢂ
ꢁꢆ
ꢂꢈ
ꢂꢇ
ꢁꢀ
ꢃꢁ
ꢊ
0). ꢂ
)$%.4)&)#!4)/.
ꢂ
ꢉ
E
ꢁ7@.&@7ꢂ
1. Drawing is not to scale.
98/121
DocID14771 Rev 15
STM8S105x4/6
Package information
Table 53. LQFP32 - 32-pin, 7 x 7 mm low-profile quad flat package
mechanical data
millimeters
inches(1)
Symbol
Min
Typ
Max
Min
Typ
Max
A
A1
A2
b
-
0.050
1.350
0.300
0.090
8.800
6.800
-
-
1.600
0.150
1.450
0.450
0.200
9.200
7.200
-
-
0.0020
0.0531
0.0118
0.0035
0.3465
0.2677
-
-
0.0630
0.0059
0.0571
0.0177
0.0079
0.3622
0.2835
-
-
-
1.400
0.370
-
0.0551
0.0146
-
c
D
9.000
7.000
5.600
9.000
7.000
5.600
0.800
0.600
1.000
3.5°
0.3543
0.2756
0.2205
0.3543
0.2756
0.2205
0.0315
0.0236
0.0394
3.5°
D1
D3
E
8.800
6.800
-
9.200
7.200
-
0.3465
0.2677
-
0.3622
0.2835
-
E1
E3
e
-
-
-
-
L
0.450
-
0.750
-
0.0177
-
0.0295
-
L1
k
0°
7°
0°
7°
ccc
-
-
0.100
-
-
0.0039
1. Values in inches are converted from mm and rounded to 4 decimal digits.
DocID14771 Rev 15
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107
Package information
STM8S105x4/6
Figure 54. LQFP32 - 32-pin, 7 x 7 mm low-profile quad flat package
recommended footprint
ꢄꢅꢉꢄ
ꢂꢅꢁꢄ
ꢂꢀ
ꢃꢇ
ꢂꢁ
ꢃꢆ
ꢄꢅꢀꢄ
ꢄꢈꢀꢄ
ꢈꢅꢃꢄ
ꢇꢅꢂꢄ
ꢊꢅꢈꢄ
ꢈꢅꢃꢄ
ꢈꢂ
ꢅ
ꢄ
ꢃ
ꢂꢅꢁꢄ
ꢇꢅꢂꢄ
ꢊꢅꢈꢄ
ꢀ6?&0?6ꢁ
1. Dimensions are expressed in millimeters.
Device marking
The following figure gives an example of topside marking orientation versus pin 1 identifier
location.
Figure 55. LQFP32 marking example (package top view)
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1. Parts marked as “ES”,”E” or accompanied by an Engineering Sample notification letter, are not yet
qualified and therefore not yet ready to be used in production and any consequences deriving from such
usage will not be at ST charge. In no event, ST will be liable for any customer usage of these engineering
samples in production. ST Quality has to be contacted prior to any decision to use these Engineering
samples to run qualification activity.
100/121
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Package information
11.4
UFQFPN32 package information
Figure 56. UFQFPN32 - 32-pin, 5x5 mm, 0.5 mm pitch ultra thin fine pitch quad flat
package outline
'
$
GGG
&
$ꢂ
$ꢁ
H
&
6($7,1*
3/$1(
'ꢂ
E
H
E
(ꢁ
(ꢂ
(
ꢂ
/
ꢀꢁ
'ꢁ
/
3,1ꢅꢂꢅ,GHQWLILHU
!ꢄ"ꢉ?-%?6ꢁ
1. Drawing is not to scale.
2. All leads/pads should be soldered to the PCB to improve the lead/pad solder joint life.
3. There is an exposed die pad on the underside of the UFQFPN package. It is recommended to connect and
solder this backside pad to PCB ground.
4. Dimensions are in millimeters.
DocID14771 Rev 15
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107
Package information
STM8S105x4/6
Table 54. UFQFPN32 - 32-pin, 5x5 mm, 0.5 mm pitch ultra thin fine pitch quad flat
package mechanical data
millimeters
Typ
inches(1)
Symbol
Min
Max
Min
Typ
Max
A
A1
A3
b
0.500
0.000
-
0.550
0.020
0.152
0.230
5.000
3.500
3.500
5.000
3.500
3.500
0.500
0.400
-
0.600
0.050
-
0.0197
0.0000
-
0.0217
0.0008
0.0060
0.0091
0.1969
0.1378
0.1378
0.1969
0.1378
0.1378
0.0197
0.0157
-
0.0236
0.0020
-
0.180
4.900
3.400
3.400
4.900
3.400
3.400
-
0.280
5.100
3.600
3.600
5.100
3.600
3.600
-
0.0071
0.1929
0.1339
0.1339
0.1929
0.1339
0.1339
-
0.0110
0.2008
0.1417
0.1417
0.2008
0.1417
0.1417
-
D
D1
D2
E
E1
E2
e
L
0.300
-
0.500
0.080
0.0118
-
0.0197
0.0031
ddd
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Figure 57. UFQFPN32 - 32-pin, 5 x5 mm, 0.5 mm pitch ultra thin fine pitch quad flat
package recommended footprint
ꢏꢈꢀꢄ
ꢀꢈꢃꢄ
ꢄꢈꢇꢄ
ꢂꢁ
ꢈꢂ
ꢃ
ꢂꢀ
ꢀꢈꢍꢏ
ꢀꢈꢃꢄ
ꢏꢈꢀꢄ
ꢀꢈꢍꢏ
ꢄꢈꢏꢄ
ꢄ
ꢃꢇ
ꢄꢈꢀꢄ
ꢃꢆ
ꢅ
ꢄꢈꢑꢏ
ꢀꢈꢃꢄ
$ꢄ%ꢃB)3B9ꢁ
1. Dimensions are expressed in millimeters.
102/121
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STM8S105x4/6
Package information
Device marking
The following figure gives an example of topside marking orientation versus pin 1 identifier
location.
Figure 58. UFQFPN32 marking example (package top view)
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3
06ꢀꢃꢀꢀꢂ9ꢂ
1. Parts marked as “ES”,”E” or accompanied by an Engineering Sample notification letter, are not yet
qualified and therefore not yet ready to be used in production and any consequences deriving from such
usage will not be at ST charge. In no event, ST will be liable for any customer usage of these engineering
samples in production. ST Quality has to be contacted prior to any decision to use these Engineering
samples to run qualification activity.
DocID14771 Rev 15
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107
Package information
STM8S105x4/6
11.5
SDIP32 package information
Figure 59. SDIP32 package outline
%
%ꢂ
!ꢁ
!ꢂ
!
,
"ꢂ
"
E
E!
E"
#
$
ꢃꢁ
ꢂ
ꢂꢈ
ꢂꢇ
ꢈꢇ?-%
Table 55. SDIP32 package mechanical data
mm
inches(1)
Typ
Dim.
Min
Typ
Max
Min
Max
A
A1
A2
B
3.556
0.508
3.048
0.356
0.762
0.203
27.430
9.906
7.620
-
3.759
-
5.080
-
0.1400
0.0200
0.1200
0.0140
0.0300
0.0079
1.0799
0.3900
0.3000
-
0.1480
-
0.2000
-
3.556
0.457
1.016
0.254
27.940
10.410
8.890
1.778
10.160
4.572
0.584
1.397
0.356
28.450
11.050
9.398
-
0.1400
0.0180
0.0400
0.0100
1.1000
0.4098
0.3500
0.0700
0.4000
0.1800
0.0230
0.0550
0.0140
1.1201
0.4350
0.3700
-
B1
C
D
E
E1
e
eA
-
-
-
-
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Package information
Table 55. SDIP32 package mechanical data (continued)
mm
Typ
inches(1)
Dim.
Min
Max
Min
Typ
Max
eB
L
-
-
12.700
3.810
-
-
0.5000
0.1500
2.540
3.048
0.1000
0.1200
1. Values in inches are converted from mm and rounded to 4 decimal digits
Device marking
The following figure gives an example of topside marking orientation versus pin 1 identifier
location.
Figure 60. SDIP32 marking example (package top view)
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:88
06ꢀꢃꢀꢀꢁ9ꢂ
1. Parts marked as “ES”,”E” or accompanied by an Engineering Sample notification letter, are not yet
qualified and therefore not yet ready to be used in production and any consequences deriving from such
usage will not be at ST charge. In no event, ST will be liable for any customer usage of these engineering
samples in production. ST Quality has to be contacted prior to any decision to use these Engineering
samples to run qualification activity.
DocID14771 Rev 15
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107
Thermal characteristics
STM8S105x4/6
12
Thermal characteristics
The maximum junction temperature (T
) of the device must never exceed the values
Jmax
specified in Table 18: General operating conditions, otherwise the functionality of the device
cannot be guaranteed.
The maximum junction temperature T
following equation:
, in degrees Celsius, may be calculated using the
Jmax
T
= T
+ (P
x )
Dmax JA
Jmax
Amax
Where:
T
is the maximum ambient temperature in C
Amax
P
is the package junction-to-ambient thermal resistance in C/W
JA
is the sum of P
and P
(P
= P
+ P
)
I/Omax
Dmax
INTmax
I/Omax
Dmax
INTmax
P
is the product of I and V , expressed in Watts. This is the maximum chip
DD DD
INTmax
internal power.
P
represents the maximum power dissipation on output pins
I/Omax
Where:
P
= (V *I ) + ((V -V )*I ),
I/Omax
OL OL
DD OH OH
taking into account the actual V /I and V /I of the I/Os at low and high level in
OL OL
OH OH
the application.
(1)
Table 56. Thermal characteristics
Parameter
Symbol
Value
Unit
Thermal resistance junction-ambient
LQFP48 - 7x7 mm
Thermal resistance junction-ambient
LQFP44 - 10x10 mm
Thermal resistance junction-ambient
LQFP32 - 7x7 mm
JA
°C/W
Thermal resistance junction-ambient
UFQFPN32 - 5x5 mm
Thermal resistance junction-ambient
SDIP32 - 400 ml
1. Thermal resistances are based on JEDEC JESD51-2 with 4-layer PCB in a natural convection
environment.
12.1
Reference document
JESD51-2 integrated circuits thermal test method environment conditions - natural
convection (still air). Available from www.jedec.org.
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Thermal characteristics
12.2
Selecting the product temperature range
When ordering the microcontroller, the temperature range is specified in the order code (see
Section 13: Ordering information).
The following example shows how to calculate the temperature range needed for a given
application.
Assuming the following application conditions:
Maximum ambient temperature T
= 82°C (measured according to JESD51-2),
Amax
I
= 15 mA, V = 5.5 V
DDmax
DD
Maximum 8 standard I/Os used at the same time in output at low level with
= 10 mA, V = 2 V
I
OL
OL
Maximum 4 high sink I/Os used at the same time in output at low level with
= 20 mA, V = 1.5 V
I
OL
OL
Maximum 2 true open drain I/Os used at the same time in output at low level with
= 20 mA, V = 2 V
I
OL
OL
P
P
= 15 mA x 5.5 V= 82.5 mW
INTmax
= (10 mA x 2 V x 8) + (20 mA x 2 V x 2) + (20 mA x 1.5 V x 4) = 360 mW
IOmax
This gives: P
= 82.5 mW and P
= 360 mW:
INTmax
IOmax
P
= 82.5 mW + 360 mW
Dmax
Thus: P
= 443 mW.
Dmax
Using the values obtained in Table 56: Thermal characteristics T
is calculated as
Jmax
follows:
For LQFP32 60°C/W
T
= 82°C + (60°C/W x 443 mW) = 82°C + 27°C = 109 °C
Jmax
This is within the range of the suffix 6 version parts (-40 < T < 131°C).
J
Parts must be ordered at least with the temperature range suffix 3.
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13
Ordering information
(1)
Figure 61. STM8S105x4/6 access line ordering information scheme
Example:
STM8
S
105
K
4
T
6
TR
Product class
STM8 microcontroller
Family type
S = Standard
Sub-family type
10x = Access line
105 sub-family
Pin count
K = 32 pins
S = 44 pins
C = 48 pins
Program memory size
4 = 16 Kbyte
6 = 32 Kbyte
Package type
B = SDIP
T = LQFP
U = UFQFPN
Temperature range
3 = -40 to 125 °C
6 = -40 to 85 °C
Package pitch/thickness
Blank = 0.5 mm
C = 0.8 mm
A = 0.55 mm thickness for UFQFPN32
Packing
No character = Tray or tube
TR = Tape and reel
1. A dedicated ordering information scheme will be released if, in the future, memory programming service
(FastROM) is required The letter “P” will be added after STM8S. Three unique letters identifying the
customer application code will also be visible in the codification. Example: STM8SP103K3MACTR.
For a list of available options (for example memory size, package) and orderable part
numbers or for further information on any aspect of this device, please go to www.st.com or
contact the nearest ST Sales Office.
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13.1
STM8S105 FASTROM microcontroller option list
(last update: September 2010)
Customer
...............................................................................
Address
...............................................................................
...............................................................................
...............................................................................
...............................................................................
Contact
Phone number
FASTROM code reference(1)
1. The FASTROM code name is assigned by STMicroelectronics.
The preferable format for programing code is .Hex (.s19 is accepted)
If data EEPROM programing is required, a separate file must be sent with the requested
data.
Note:
See the option byte section in the datasheet for authorized option byte combinations and a
detailed explanation.
Device type/memory size/package (check only one option)
FASTROM device
LQFP32
16 Kbyte
32 Kbyte
[ ] STM8S105K4
[ ] STM8S105S4
[ ] STM8S105C4
[ ] STM8S105K6
[ ] STM8S105S6
[ ] STM8S105C6
LQFP44
LQFP48
Conditioning (check only one option)
[ ] Tape and reel or [ ] Tray
Special marking (check only one option)
[ ] No [ ] Yes
Authorized characters are letters, digits, '.', '-', '/' and spaces only. Maximum character
counts are:
LQFP32: 2 lines of 7 characters max: “_ _ _ _ _ _ _” and “_ _ _ _ _ _ _”
LQFP44: 2 lines of 7 characters max: “_ _ _ _ _ _ _” and “_ _ _ _ _ _ _”
LQFP48: 2 lines of 8 characters max: “_ _ _ _ _ _ _ _” and “_ _ _ _ _ _ _ _”
Temperature range
[ ] -40°C to +85°C or [ ] -40°C to +125°C
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Padding value for unused program memory (check only one option)
[ ] 0xFF
[ ] 0x83
[ ] 0x75
Fixed value
TRAP instruction code
Illegal opcode (causes a reset when executed)
OTP0 memory readout protection (check only one option)
[ ] Disable or [ ] Enable
OTP1 user boot code area (UBC)
0x(_ _) fill in the hexadecimal value, referring to the datasheet and the binary format below:
[ ] 0: Reset
UBC, bit0
[ ] 1: Set
[ ] 0: Reset
UBC, bit1
[ ] 1: Set
[ ] 0: Reset
UBC, bit2
[ ] 1: Set
[ ] 0: Reset
UBC, bit3
[ ] 1: Set
[ ] 0: Reset
UBC, bit4
[ ] 1: Set
[ ] 0: Reset
UBC, bit5
[ ] 1: Set
OTP2 alternate function remapping
[ ] 0: Remapping option inactive. Default alternate functions
used. Refer to pinout description
AFR0
(check only one option)
[ ] 1: Port D3 alternate function = ADC_ETR
[ ] 0: Remapping option inactive. Default alternate functions
AFR1
used. Refer to pinout description
(check only one option)
[ ] 1: Port A3 alternate function = TIM3_CH1, port D2 alternate
function = TIM2_CH3
[ ] 0: Remapping option inactive. Default alternate functions
used. Refer to pinout description
AFR2
[ ] 1: Port D0 alternate function = CLK_CCO
(check only one option)
Note: if both AFR2 and AFR3 are activated, AFR2 option has
priority over AFR3.
[ ] 0: Remapping option inactive. Default alternate functions
used. Refer to pinout description
AFR3
(check only one option)
[ ] 1: Port D0 alternate function = TIM1_BKIN
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[ ] 0: Remapping option inactive. Default alternate functions
used. Refer to pinout description
AFR4
(check only one option)
[ ] 1: Port D7 alternate function = TIM1_CH4
[ ] 0: Remapping option inactive. Default alternate functions
used. Refer to pinout description
AFR5
[ ] 1: Port B3 alternate function = TIM1_ETR, port B2 alternate
function = TIM1_NCC3, port B1 alternate function =
TIM1_CH2N, port B0 alternate function = TIM1_CH1N.
(check only one option)
[ ] 0: Remapping option inactive. Default alternate functions
used. Refer to pinout description
AFR6
(check only one option)
[ ] 1: Port B5 alternate function = I2C_SDA, port B4 alternate
function = I2C_SCL
[ ] 0: Remapping option inactive. Default alternate functions
used. Refer to pinout description
AFR6
(check only one option)
[ ] 1: Port D4 alternate function = BEEP.
OPT3 watchdog
WWDG_HALT
[ ] 0: No reset generated on halt if WWDG active[
[ ] 1: Reset generated on halt if WWDG active
(check only one option)
WWDG_HW
[ ] 0: WWDG activated by software
[ ] 1: WWDG activated by hardware
(check only one option)
IWDG_HW
[ ] 0: IWDG activated by software
[ ] 1: IWDG activated by hardware
(check only one option)
LSI_EN
[ ] 0: LSI clock is not available as CPU clock source
[ ] 1: LSI clock is available as CPU clock source
(check only one option)
HSITRIM
[ ] 0: 3-bit trimming supported in CLK_HSITRIMR register
[ ] 1: 4-bit trimming supported in CLK_HSITRIMR register
(check only one option)
OPT4 watchdog
[ ] for 16 MHz to 128 kHz prescaler
[ ] for 8 MHz to 128 kHz prescaler
[ ] for 4 MHz to 128 kHz prescaler
PRSC
(check only one option)
CKAWUSEL
[ ] LSI clock source selected for AWU
(check only one option)
[ ] HSE clock with prescaler selected as clock source for AWU
EXTCLK
[ ] External crystal connected to OSCIN/OSCOUT
[ ] External signal on OSCIN
(check only one option)
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OPT5 crystal oscillator stabilization HSECNT (check only one option)
[ ] 2048 HSE cycles
[ ] 128 HSE cycles
[ ] 8 HSE cycles
[ ] 0.5 HSE cycles
OTP6 is reserved
OTP7 is reserved
OTPBL bootloader option byte (check only one option)
Refer to the UM0560 (STM8L/S bootloader manual) for more details.
[ ] Disable (00h)
[ ] Enable (55h)
Comments:
.........................................................................................
Supply operating range in the application: .........................................................................................
Notes:
.........................................................................................
.........................................................................................
.........................................................................................
Date:
Signature:
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STM8 development tools
14
STM8 development tools
Development tools for the STM8 microcontrollers include the full-featured STice emulation
system supported by a complete software tool package including C compiler, assembler and
integrated development environment with high-level language debugger. In addition, the
STM8 is to be supported by a complete range of tools including starter kits, evaluation
boards and a low-cost in-circuit debugger/programmer.
14.1
Emulation and in-circuit debugging tools
The STice emulation system offers a complete range of emulation and in-circuit debugging
features on a platform that is designed for versatility and cost-effectiveness. In addition,
STM8 application development is supported by a low-cost in-circuit debugger/programmer.
The STice is the fourth generation of full featured emulators from STMicroelectronics. It
offers new advanced debugging capabilities including profiling and coverage to help detect
and eliminate bottlenecks in application execution and dead code when fine tuning an
application.
In addition, STice offers in-circuit debugging and programming of STM8 microcontrollers via
the STM8 single wire interface module (SWIM), which allows non-intrusive debugging of an
application while it runs on the target microcontroller.
For improved cost effectiveness, STice is based on a modular design that allows you to
order exactly what you need to meet your development requirements and to adapt your
emulation system to support existing and future ST microcontrollers.
14.1.1
STice key features
Occurrence and time profiling and code coverage (new features),
Advanced breakpoints with up to 4 levels of conditions,
Data breakpoints,
Program and data trace recording up to 128 KB records,
Read/write on the fly of memory during emulation,
In-circuit debugging/programming via SWIM protocol,
8-bit probe analyzer,
1 input and 2 output triggers,
Power supply follower managing application voltages between 1.62 to 5.5 V,
Modularity that allows you to specify the components you need to meet your
development requirements and adapt to future requirements.
Supported by free software tools that include integrated development environment
(IDE), programming software interface and assembler for STM8.
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STM8 development tools
STM8S105x4/6
14.2
Software tools
STM8 development tools are supported by a complete, free software package from
STMicroelectronics that includes ST Visual Develop (STVD) IDE and the ST Visual
Programmer (STVP) software interface. STVD provides seamless integration of the Cosmic
and Raisonance C compilers for STM8, which are available in a free version that outputs up
to 16 Kbytes of code.
14.2.1
STM8 toolset
The STM8 toolset with STVD integrated development environment and STVP programming
software is available for free download at www.st.com. This package includes:
ST visual develop
Full-featured integrated development environment from STMicroelectronics, featuring:
Seamless integration of C and ASM toolsets
Full-featured debugger
Project management
Syntax highlighting editor
Integrated programming interface
Support of advanced emulation features for STice such as code profiling and coverage
ST visual programmer (STVP)
Easy-to-use, unlimited graphical interface allowing read, write and verification of the STM8
Flash program memory, data EEPROM and option bytes. STVP also offers project mode for
the saving of programming configurations and the automation of programming sequences.
14.2.2
C and assembly toolchains
Control of C and assembly toolchains is seamlessly integrated into the STVD integrated
development environment, making it possible to configure and control the building of user
applications directly from an easy-to-use graphical interface.
Available toolchains include:
C compiler for STM8
Available in a free version that outputs up to 16 Kbytes of code. For more information, see
www.cosmic-software.com.
STM8 assembler linker
Free assembly toolchain included in the STVD toolset, used to assemble and link the user
application source code.
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14.3
Programming tools
During the development cycle, STice provides in-circuit programming of the STM8 Flash
microcontroller on the application board via the SWIM protocol. Additional tools include a
low-cost in-circuit programmer as well as ST socket boards, which provide dedicated
programming platforms with sockets for the STM8 programming.
For production environments, programmers will include a complete range of gang and
automated programming solutions from third-party tool developers already supplying
programmers for the STM8 family.
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15
Revision history
Table 57. Document revision history
Date
Revision
Changes
05-Jun-2018
1
Initial release.
Corrected the number of high sink outputs to 9 in I/Os in
Features.
23-Jun-2018
12-Aug-2008
2
3
Updated part numbers in STM8S105xx access line
features.
Updated the part numbers in STM8S105xx access line
features.
USART renamed UART1, LINUART renamed UART2.
Added Table: Pin-to-pin comparison of pin 7 to 12 in 32-
pin access line devices.
Removed STM8S102xx and STM8S104xx root part
numbers corresponding to devices without data
EEPROM.
Updated STM8S103 pinout section
17-Sep-2008
4
Added low and medium density Flash memory
categories.
Added Note 1 in Section: Current characteristics.
Updated Section: Option bytes.
Updated STM8S103 pinout.
Updated number of High Sink I/Os in the pinout section.
TSSOP20 pinout modified (PD4 moved to pin 1 etc.)
Added WFQFN20 package
05-Feb-2009
27-Feb-2009
5
6
Updated Section: Option bytes.
Added Section: Memory and register map.
Removed STM8S103x products (separate STM8S103
datasheet created).
Updated Section: Electrical characteristics.
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Revision history
Table 57. Document revision history (continued)
Date
Revision
Changes
Added SDIP32 silhouette and package to Features and
Section: SDIP32 package mechanical data; updated
Section: Pinout and pin description.
Updated VDD range (2.95 V to 5.5 V) on Features.
Amended name of package VQFPN32.
Added Table 5 on page 22.
Updated Section: Auto wakeup counter.
Updated pins 25, 30, and 31 in Section: Pinout and pin
description.
Removed Table 7: Pin-to-pin comparison of pin 7 to 12
in 32-pin access line devices.
Added Table: Description of alternate function
remapping bits [7:0] of OPT2.
Section: Electrical characteristics: Updated VCAP
specifications; updated Table 15, Table 18, Table 20,
Table 21, Table 22, Table 23, Table 24, Table 25, Table
26, Table 27, Table 29, Table 35, and Table 42; added
current consumption curves; removed Figure 20: typical
HSE frequency vs fcpu @ 4 temperatures; updated
Figure 13, Figure 14, Figure 15, Figure 16 and Figure
17; modified HSI accuracy in Table 33 ; added Figure
44; modified fSCK, tV(SO) and tV(MO) in Table 42; updated
figures and tables of High speed internal RC oscillator
(HSI); replaced Figure 23, Figure 24, Figure 26, and
Figure 39.
12-May-2009
7
Section Package information: updated Section: Thermal
characteristics and removed Table 57: Junction
temperature range. Updated Section: STM8S105xx
access line ordering information scheme.
Document status changed from “preliminary data” to
“datasheet”.
10-Jun-2009
8
Standardized the name of the VFQFPN package.
Removed ‘wpu’ from I2C pins Section: Pinout and pin
description
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Revision history
STM8S105x4/6
Table 57. Document revision history (continued)
Date
Revision
Changes
Added UFQFPN32 package silhouette to the title page.
In Features: added unique ID.
Section: Clock controller: updated bit positions for TIM2
and TIM3.
Section: Beeper: added information about availability of
the beeper output port through option bit AFR7.
Section: Analog-to-digital converter (ADC1): added a
note concerning additional AIN12 analog input.
Section: STM8S105 pinouts and pin description: added
UFQFPN32 package details; updated default alternate
function of PB2/AIN2[TIM1_CH3N] pin in the "Pin
description for STM8S105 microcontrollers" table.
Section: Option bytes: added description of STM8L
bootloader option bytes to the option byte description
table.
Added Section: Unique ID
Section: Operating conditions: added introductory text;
removed low power dissipation condition for TA,
replaced "CEXT" by "VCAP", and added ESR and ESL
data in table "general operating conditions".
Section: Total current consumption in halt mode:
replaced max value of IDD(H) at 85 °C from 20 µA to 25
µA for the condition "Flash in powerdown mode, HSI
clock after wakeup in the table "total current
consumption in halt mode at VDD = 5 V.
21-Apr-2010
9
Section: Low power mode wakeup times: added first
condition (0 to 16 MHz) for the tWU(WFI) parameter in the
table "wakeup times".
Section: Internal clock sources and timing
characteristics: In the table: HSI oscillator
characteristics, replaced min and max values of
ACCHSI factory calibrated parameter and removed
footnote 4 concerning further characterization of results.
Section: Functional EMS (electromagnetic
susceptibility): IEC 1000 replaced with IEC 61000.
Section: Designing hardened software to avoid noise
problems: IEC 1000 replaced with IEC 61000.
Section: Electromagnetic interference (EMI): SAE J
1752/3 replaced with IEC61967-2.
Section: Thermal characteristics: Replaced the thermal
resistance junction ambient temperature of LQFP32 7X7
mm from 59 °C to 60 °C in the thermal characteristics
table.
Added Section: 32-lead UFQFPN package mechanical
data.
Added Section STM8S105 FASTROM microcontroller
option list.
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Revision history
Table 57. Document revision history (continued)
Date
Revision
Changes
Table: Legend/Abbreviations for pinout tables: updated
"reset state"; removed "HS", (T), and "[ ]".
Section: Pin description for STM8S105 microcontrollers:
added footnotes to the PF4 and PD1 pins.
Table: I/O port hardware register map: changed reset
status of Px_IDR from 0x00 to 0xXX.
Table: General hardware register map: Standardized all
address and reset state values; updated the reset state
values of the RST_SR, CLK_SWCR, CLK_HSITRIMR,
CLK_SWIMCCR, IWDG_KR, UART2_DR, and
ADC_DRx registers; replaced reserved address "0x00
5248" with the UART2_CR5.
21-Sep-2010
10
Section: Recommended reset pin protection: replaced
0.01 µF with 0.1 µF
Updated Figure: Typical application with I2C bus and
timing diagram.
Updated Table: ADC accuracy with RAIN < 10 kohm ,
VDDA = 5 V footnote 1 in and Table: ADC accuracy with
RAIN < 10 kohm RAIN, VDDA = 3.3 V.
Section: STM8S105 FASTROM microcontroller option
list: removed bits 6 and 7 from OPT1 user boot code
area (UBC); added "disable" to 00h and "enable" to 55h
of OPTBL bootloader option byte.
Section: VFQFPN Package Mechanical data: replaced
note 1 and added note 2.
Removed VFQFPN32 package.
Modified Section: Description.
Remove weak pull-up input for PE1 and PE2 in Table:
Pin description for STM8S105 microcontrollers
Updated Table: Interrupt mapping for TIM2 and TIM4.
Updated notes related to VCAP in xm-replace_text
General operating conditions.
Added values of tR/tF for 50 pF load capacitance, and
updated note in Section: I/O static characteristics.
04-Apr-2012
11
Updated typical and maximum values of RPU in Table:
I/O static characteristics and Table: RST pin
characteristics.
Changed SCK input to SCK output in Table: SPI serial
peripheral interface.
Added JA for UFQFPN32 and SDIP32 in Table:
Thermal characteristics, and updated Section: Selecting
the product temperature range
Added UFQFPN package thickness in Figure:
STM8S105xx access line ordering information scheme
28-Jun-2012
12
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Revision history
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Table 57. Document revision history (continued)
Date
Revision
Changes
UART2_CK mapped to correct pin (pin 24) in Figure:
LQFP 44-pin pinout.
07-Feb-2014
13
Reserved area updated in Table: Option bytes.
Package Information updated in Table: 32-lead ultra thin
fine pitch quad flat no-lead package mechanical data.
Added:
– Figure 49: LQFP48 marking example (package top
view),
– Figure 52: LQFP44 marking example (package top
view),
– Figure 55: LQFP32 marking example (package top
view),
01-Jul-2015
14
– Figure 58: UFQFPN32 marking example (package top
view),
– Figure 60: SDIP32 marking example (package top
view).
Updated:
– Figure 41: SPI timing diagram where slave mode and
CPHA = 0,
– the standard for EMI data in Table 48: EMI data.
Added the footnotes related to Figure 56: UFQFPN32 -
32-pin, 5x5 mm, 0.5 mm pitch ultra thin fine pitch quad
flat package outline.
23-Sep-2015
15
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IMPORTANT NOTICE – PLEASE READ CAREFULLY
STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and
improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on
ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order
acknowledgement.
Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or
the design of Purchasers’ products.
No license, express or implied, to any intellectual property right is granted by ST herein.
Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product.
ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners.
Information in this document supersedes and replaces information previously supplied in any prior versions of this document.
© 2015 STMicroelectronics – All rights reserved
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