STM8S207SBT3BTR [STMICROELECTRONICS]
Performance line, 24 MHz STM8S 8-bit MCU, up to 128 Kbytes Flash, integrated EEPROM,10-bit ADC, timers, 2 UARTs, SPI, I²C, CAN; 性能线, 24兆赫STM8S 8位MCU ,高达128 KB闪存,集成的EEPROM , 10位ADC ,定时器, 2个UART , SPI , I²C , CAN型号: | STM8S207SBT3BTR |
厂家: | ST |
描述: | Performance line, 24 MHz STM8S 8-bit MCU, up to 128 Kbytes Flash, integrated EEPROM,10-bit ADC, timers, 2 UARTs, SPI, I²C, CAN |
文件: | 总103页 (文件大小:1740K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
STM8S207xx
STM8S208xx
Performance line, 24 MHz STM8S 8-bit MCU, up to 128 Kbytes Flash,
integrated EEPROM,10-bit ADC, timers, 2 UARTs, SPI, I²C, CAN
Features
■ Core
– Max f
: up to 24 MHz, 0 wait states @
CPU
f
CPU ≤ 16 MHz
LQFP80 14x14
LQFP48 7x7
LQFP64 14x14
LQFP44 10x10
LQFP64 10x10
LQFP32 7x7
– Advanced STM8 core with Harvard
architecture and 3-stage pipeline
– Extended instruction set
– Max 20 MIPS @ 24 MHz
■ Memories
■ Communications interfaces
– Program: up to 128 Kbytes Flash; data
retention 20 years at 55 °C after 10 kcycles
– Data: up to 2 Kbytes true data EEPROM;
endurance 300 kcycles
– High speed 1 Mbit/s active beCAN 2.0B
– UART with clock output for synchronous
operation - LIN master mode
– UART with LIN 2.1 compliant, master/slave
modes and automatic resynchronization
– SPI interface up to 10 Mbit/s
– RAM: up to 6 Kbytes
■ Clock, reset and supply management
– 2.95 to 5.5 V operating voltage
– Flexible clock control:
2
– I C interface up to 400 Kbit/s
■ 10-bit ADC with up to 16 channels
– Low power crystal resonator oscillator
– External clock input
■ I/Os
– Internal, user-trimmable 16 MHz RC
– Internal low power 128 kHz RC
– Clock security system with clock monitor
– Power management:
– Up to 68 I/Os on an 80-pin package
including 18 high sink outputs
– Highly robust I/O design, immune against
current injection
– Wait, active-halt, & halt low power modes
– Peripheral clocks switched off individually
– Permanently active, low consumption
power-on and power-down reset
– Development support
– Single wire interface module (SWIM) and
debug module (DM)
■ Unique ID
■ Interrupt management
– 96-bit unique key for each device
– Nested interrupt controller with 32
interrupts
– Up to 37 external interrupts on 6 vectors
Table 1.
Device summary
Part numbers: STM8S207xx
■ Timers
STM8S207MB, STM8S207M8, STM8S207RB,
STM8S207R8, STM8S207R6, STM8S207CB,
STM8S207C8, STM8S207C6, STM8S207SB,
STM8S207S8, STM8S207S6, STM8S207K6
– 2x 16-bit general purpose timers, with 2+3
CAPCOM channels (IC, OC or PWM)
– Advanced control timer: 16-bit, 4 CAPCOM
channels, 3 complementary outputs, dead-
time insertion and flexible synchronization
– 8-bit basic timer with 8-bit prescaler
– Auto wakeup timer
Part numbers: STM8S208xx
STM8S208MB, STM8S208RB, STM8S208R8,
STM8S208R6, STM8S208CB, STM8S208C8,
STM8S208C6, STM8S208SB, STM8S208S8,
STM8S208S6
– Window watchdog, independent watchdog
April 2010
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www.st.com
1
Contents
STM8S207xx, STM8S208xx
Contents
1
2
3
4
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Product overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.1
4.2
4.3
4.4
4.5
4.6
4.7
4.8
4.9
Central processing unit STM8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Single wire interface module (SWIM) and debug module (DM) . . . . . . . . 14
Interrupt controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Flash program and data EEPROM memory . . . . . . . . . . . . . . . . . . . . . . . 15
Clock controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Watchdog timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Auto wakeup counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Beeper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.10 TIM1 - 16-bit advanced control timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.11 TIM2, TIM3 - 16-bit general purpose timers . . . . . . . . . . . . . . . . . . . . . . . 18
4.12 TIM4 - 8-bit basic timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.13 Analog-to-digital converter (ADC2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.14 Communication interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.14.1 UART1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.14.2 UART3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.14.3 SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
2
4.14.4 I C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
4.14.5 beCAN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
5
Pinouts and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5.1
5.2
Package pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Alternate function remapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
6
Memory and register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
6.1
Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
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6.2
Register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
7
Interrupt vector mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Option bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Unique ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
8
9
10
10.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
10.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
10.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
10.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
10.1.4 Typical current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
10.1.5 Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
10.1.6 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
10.1.7 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
10.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
10.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
10.3.1 VCAP external capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
10.3.2 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
10.3.3 External clock sources and timing characteristics . . . . . . . . . . . . . . . . . 65
10.3.4 Internal clock sources and timing characteristics . . . . . . . . . . . . . . . . . 67
10.3.5 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
10.3.6 I/O port pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
10.3.7 Reset pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
10.3.8 SPI serial peripheral interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
2
10.3.9 I C interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
10.3.10 10-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
10.3.11 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
11
Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
11.1 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
11.1.1 LQFP package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
11.2 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
11.2.1 Reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
11.2.2 Selecting the product temperature range . . . . . . . . . . . . . . . . . . . . . . . . 97
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12
STM8 development tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
12.1 Emulation and in-circuit debugging tools . . . . . . . . . . . . . . . . . . . . . . . . . 98
12.2 Software tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
12.2.1 STM8 toolset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
12.2.2 C and assembly toolchains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
12.3 Programming tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
13
14
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List of tables
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Device summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
STM8S20xxx performance line features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Peripheral clock gating bit assignments in CLK_PCKENR1/2 registers. . . . . . . . . . . . . . . 16
TIM timer features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Legend/abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Flash, Data EEPROM and RAM boundary addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
I/O port hardware register map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
General hardware register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
CPU/SWIM/debug module/interrupt controller registers. . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Interrupt mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Option bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Option byte description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Unique ID registers (96 bits) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Operating conditions at power-up/power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
Table 26.
Table 27.
Table 28.
Table 29.
Table 30.
Table 31.
Table 32.
Table 33.
Table 34.
Table 35.
Table 36.
Table 37.
Table 38.
Table 39.
Table 40.
Table 41.
Table 42.
Table 43.
Table 44.
Table 45.
Table 46.
Table 47.
Table 48.
Total current consumption with code execution in run mode at V = 5 V. . . . . . . . . . . . . 58
DD
Total current consumption with code execution in run mode at V = 3.3 V . . . . . . . . . . . 59
DD
Total current consumption in wait mode at V = 5 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
DD
Total current consumption in wait mode at V = 3.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . 60
DD
Total current consumption in active halt mode at V = 5 V, T -40 to 85° C . . . . . . . . . . 61
DD
A
Total current consumption in active halt mode at V = 3.3 V . . . . . . . . . . . . . . . . . . . . . . 61
DD
Total current consumption in halt mode at V = 5 V, T -40 to 85° C . . . . . . . . . . . . . . . 62
DD
A
Total current consumption in halt mode at V = 3.3 V . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
DD
Wakeup times. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Total current consumption and timing in forced reset state . . . . . . . . . . . . . . . . . . . . . . . . 63
Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
HSE user external clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
HSE oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
HSI oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
RAM and hardware registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Flash program memory/data EEPROM memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Output driving current (standard ports). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Output driving current (true open drain ports). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Output driving current (high sink ports). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
2
I C characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
ADC accuracy with R
ADC accuracy with R
< 10 kΩ , V
= 5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
AIN
DDA
< 10 kΩ R , V
= 3.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
AIN
AIN
DDA
EMS data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
EMI data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
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List of tables
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Table 49.
Table 50.
Table 51.
Table 52.
Table 53.
Table 54.
Table 55.
Table 56.
Table 57.
Table 58.
ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
80-pin low profile quad flat package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
64-pin low profile quad flat package mechanical data (14 x 14). . . . . . . . . . . . . . . . . . . . . 91
64-pin low profile quad flat package mechanical data (10 x 10). . . . . . . . . . . . . . . . . . . . . 92
48-pin low profile quad flat package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
44-pin low profile quad flat package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
32-pin low profile quad flat package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
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List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
STM8S20xxx performance line block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Flash memory organisation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
LQFP 80-pin pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
LQFP 64-pin pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
LQFP 48-pin pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
LQFP 44-pin pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
LQFP 32-pin pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Memory map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Supply current measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Figure 10. Pin loading conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Figure 11. Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Figure 12.
f
versus V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
CPUmax
DD
Figure 13. External capacitor C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
EXT
Figure 14. Typ. I
Figure 15. Typ. I
vs V , HSI RC osc, f
= 16 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
= 16 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
DD(RUN)
DD(WFI)
DD
CPU
vs V , HSI RC osc, f
DD
CPU
Figure 16. HSE external clock source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Figure 17. HSE oscillator circuit diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Figure 18. Typical HSI frequency variation vs V at 4 temperatures. . . . . . . . . . . . . . . . . . . . . . . . . 67
DD
Figure 19. Typical LSI frequency variation vs V @ 25 °C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
DD
Figure 20. Typical V and V vs V @ 4 temperatures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
IL
IH
DD
Figure 21. Typical pull-up resistance vs V @ 4 temperatures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
DD
Figure 22. Typical pull-up current vs V @ 4 temperatures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
DD
Figure 23. Typ. V @ V = 5 V (standard ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
OL
DD
Figure 24. Typ. V @ V = 3.3 V (standard ports). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
OL
DD
Figure 25. Typ. V @ V = 5 V (true open drain ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
OL
DD
Figure 26. Typ. V @ V = 3.3 V (true open drain ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
OL
DD
Figure 27. Typ. V @ V = 5 V (high sink ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
OL
DD
Figure 28. Typ. V @ V = 3.3 V (high sink ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
OL
DD
Figure 29. Typ. V - V @ V = 5 V (standard ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
DD
OH
DD
Figure 30. Typ. V - V @ V = 3.3 V (standard ports). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
DD
OH
DD
Figure 31. Typ. V - V @ V = 5 V (high sink ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
DD
OH
DD
Figure 32. Typ. V - V @ V = 3.3 V (high sink ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
DD
OH
DD
Figure 33. Typical NRST V and V vs V @ 4 temperatures. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
IL
IH
DD
Figure 34. Typical NRST pull-up resistance vs V @ 4 temperatures. . . . . . . . . . . . . . . . . . . . . . . . 77
DD
Figure 35. Typical NRST pull-up current I vs V @ 4 temperatures . . . . . . . . . . . . . . . . . . . . . . . 77
pu
DD
Figure 36. Recommended reset pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Figure 37. SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
(1)
Figure 38. SPI timing diagram - slave mode and CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
(1)
Figure 39. SPI timing diagram - master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
2
(1)
Figure 40. Typical application with I C bus and timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Figure 41. ADC accuracy characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Figure 42. Typical application with ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Figure 43. 80-pin low profile quad flat package (14 x 14) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Figure 44. 64-pin low profile quad flat package (14 x 14) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Figure 45. 64-pin low profile quad flat package (10 x 10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Figure 46. 48-pin low profile quad flat package (7 x 7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Figure 47. 44-pin low profile quad flat package (10 x 10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Figure 48. 32-pin low profile quad flat package (7 x 7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Doc ID 14733 Rev 9
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List of figures
STM8S207xx, STM8S208xx
(1)
Figure 49. STM8S207xx/208xx performance line ordering information scheme . . . . . . . . . . . . . . 100
8/103
Doc ID 14733 Rev 9
STM8S207xx, STM8S208xx
Introduction
1
Introduction
This datasheet contains the description of the STM8S20xxx performance line features,
pinout, electrical characteristics, mechanical data and ordering information.
●
For complete information on the STM8S microcontroller memory, registers and
peripherals, please refer to the STM8S microcontroller family reference manual
(RM0016).
●
●
●
For information on programming, erasing and protection of the internal Flash memory
please refer to the STM8S Flash programming manual (PM0051).
For information on the debug and SWIM (single wire interface module) refer to the
STM8 SWIM communication protocol and debug module user manual (UM0470).
For information on the STM8 core, please refer to the STM8 CPU programming manual
(PM0044).
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Description
STM8S207xx, STM8S208xx
2
Description
The STM8S20xxx performance line 8-bit microcontrollers offer from 32 to 128 Kbytes Flash
program memory. They are referred to as high-density devices in the STM8S microcontroller
family Reference Manual (RM0016).
All devices of the STM8S20xxx performance line provide the following benefits:
●
Reduced system cost
–
–
Integrated true data EEPROM for up to 300 k write/erase cycles
High system integration level with internal clock oscillators, watchdog and brown-
out reset.
●
Performance and robustness
–
–
–
20 MIPS at 24 MHz CPU clock frequency
Robust I/O, independent watchdogs with separate clock source
Clock security system
●
●
Short development cycles
–
Applications scalability across a common family product architecture with
compatible pinout, memory map and and modular peripherals.
–
Full documentation and a wide choice of development tools
Product longevity
–
–
Advanced core and peripherals made in a state-of-the art technology
A family of products for applications with 2.95 V to 5.5 V operating supply
10/103
Doc ID 14733 Rev 9
STM8S207xx, STM8S208xx
Table 2. STM8S20xxx performance line features
Description
Device
STM8S207MB
STM8S207M8
STM8S207RB
STM8S207R8
STM8S207R6
STM8S207CB
STM8S207C8
STM8S207C6
STM8S207SB
STM8S207S8
STM8S207S6
STM8S207K6
80
80
64
64
64
48
48
48
44
44
44
32
68
68
52
52
52
38
38
38
34
34
34
25
37
37
36
36
36
35
35
35
31
31
31
23
9
9
9
9
9
9
9
9
8
8
8
8
3
3
3
3
3
3
3
3
3
3
3
3
16
16
16
16
16
10
10
10
9
18
18
16
16
16
16
16
16
15
15
15
12
128 K
64 K
128 K
64 K
32 K
128 K
64 K
32 K
128 K
64 K
32 K
32 K
2048
2048
2048
1536
1024
2048
1536
1024
1536
1536
1024
1024
6 K
6 K
6 K
4 K
2 K
6 K
4 K
2 K
4 K
4 K
2 K
2 K
No
9
9
7
STM8S208MB
STM8S208RB
STM8S208R8
STM8S208R6
STM8S208CB
STM8S208C8
STM8S208C6
STM8S208SB
STM8S208S8
STM8S208S6
80
64
64
64
48
48
48
44
44
44
68
52
52
52
38
38
38
34
34
34
37
37
37
37
35
35
35
31
31
31
9
9
9
9
9
9
9
8
8
8
3
3
3
3
3
3
3
3
3
3
16
16
16
16
10
10
10
9
18
16
16
16
16
16
16
15
15
15
128 K
128 K
64 K
32 K
128 K
64 K
32 K
128 K
64 K
2048
2048
2048
2048
2048
2048
2048
1536
1536
1536
6 K
6 K
6 K
6 K
6 K
6 K
6 K
4 K
4 K
4 K
Yes
9
9
32 K
Doc ID 14733 Rev 9
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Block diagram
STM8S207xx, STM8S208xx
3
Block diagram
Figure 1.
STM8S20xxx performance line block diagram
Reset block
Reset
XTAL 1-24 MHz
Clock controller
Detector
Reset
RC int. 16 MHz
RC int. 128 kHz
POR
BOR
Clock to peripherals and core
Window WDG
STM8 core
Independent WDG
Single wire
debug interf.
Up to 128 Kbytes
high density program
Flash
Debug/SWIM
2
400 Kbit/s
10 Mbit/s
I C
Up to 2 Kbytes
data EEPROM
Up to 6 Kbytes
RAM
SPI
Boot ROM
LIN master
SPI emul.
UART1
Up to
4 CAPCOM
channels
+ 3 complementary
outputs
16-bit advanced control
timer (TIM1)
Master/slave
autosynchro
UART3
beCAN
Up to
5 CAPCOM
channels
16-bit general purpose
timers (TIM2, TIM3)
1 Mbit/s
ADC2
16 channels
8-bit basic timer
(TIM4)
1/2/4 kHz
beep
Beeper
AWU timer
12/103
Doc ID 14733 Rev 9
STM8S207xx, STM8S208xx
Product overview
4
Product overview
The following section intends to give an overview of the basic features of the STM8S20xxx
performance line functional modules and peripherals.
For more detailed information please refer to the corresponding family reference manual
(RM0016).
4.1
Central processing unit STM8
The 8-bit STM8 core is designed for code efficiency and performance.
It contains 6 internal registers which are directly addressable in each execution context, 20
addressing modes including indexed indirect and relative addressing and 80 instructions.
Architecture and registers
●
●
●
●
Harvard architecture
3-stage pipeline
32-bit wide program memory bus - single cycle fetching for most instructions
X and Y 16-bit index registers - enabling indexed addressing modes with or without
offset and read-modify-write type data manipulations
●
●
●
●
8-bit accumulator
24-bit program counter - 16-Mbyte linear memory space
16-bit stack pointer - access to a 64 K-level stack
8-bit condition code register - 7 condition flags for the result of the last instruction
Addressing
●
●
20 addressing modes
Indexed indirect addressing mode for look-up tables located anywhere in the address
space
●
Stack pointer relative addressing mode for local variables and parameter passing
Instruction set
●
●
●
●
●
●
●
80 instructions with 2-byte average instruction size
Standard data movement and logic/arithmetic functions
8-bit by 8-bit multiplication
16-bit by 8-bit and 16-bit by 16-bit division
Bit manipulation
Data transfer between stack and accumulator (push/pop) with direct stack access
Data transfer using the X and Y registers or direct memory-to-memory transfers
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Product overview
STM8S207xx, STM8S208xx
4.2
Single wire interface module (SWIM) and debug module (DM)
The single wire interface module and debug module permits non-intrusive, real-time in-
circuit debugging and fast memory programming.
SWIM
Single wire interface module for direct access to the debug module and memory
programming. The interface can be activated in all device operation modes. The maximum
data transmission speed is 145 bytes/ms.
Debug module
The non-intrusive debugging module features a performance close to a full-featured
emulator. Beside memory and peripherals, also CPU operation can be monitored in real-
time by means of shadow registers.
●
●
●
●
R/W to RAM and peripheral registers in real-time
R/W access to all resources by stalling the CPU
Breakpoints on all program-memory instructions (software breakpoints)
Two advanced breakpoints, 23 predefined configurations
4.3
Interrupt controller
●
●
●
●
Nested interrupts with three software priority levels
32 interrupt vectors with hardware priority
Up to 37 external interrupts on six vectors including TLI
Trap and reset interrupts
14/103
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STM8S207xx, STM8S208xx
Product overview
4.4
Flash program and data EEPROM memory
●
●
●
Up to 128 Kbytes of high density Flash program single voltage Flash memory
Up to 2K bytes true data EEPROM
Read while write: Writing in data memory possible while executing code in program
memory.
●
User option byte area
Write protection (WP)
Write protection of Flash program memory and data EEPROM is provided to avoid
unintentional overwriting of memory that could result from a user software malfunction.
There are two levels of write protection. The first level is known as MASS (memory access
security system). MASS is always enabled and protects the main Flash program memory,
data EEPROM and option bytes.
To perform in-application programming (IAP), this write protection can be removed by writing
a MASS key sequence in a control register. This allows the application to write to data
EEPROM, modify the contents of main program memory or the device option bytes.
A second level of write protection, can be enabled to further protect a specific area of
memory known as UBC (user boot code). Refer to Figure 2.
The size of the UBC is programmable through the UBC option byte (Table 13.), in
increments of 1 page (512 bytes) by programming the UBC option byte in ICP mode.
This divides the program memory into two areas:
●
Main program memory: Up to 128 Kbytes minus UBC
●
User-specific boot code (UBC): Configurable up to 128 Kbytes
The UBC area remains write-protected during in-application programming. This means that
the MASS keys do not unlock the UBC area. It protects the memory used to store the boot
program, specific code libraries, reset and interrupt vectors, the reset routine and usually the
IAP and communication routines.
Figure 2.
Flash memory organisation
Data memory area (2 Kbytes)
Option bytes
Data
EEPROM
memory
Programmable area from 1 Kbyte
(2 first pages) up to 128 Kbytes
(1 page steps)
UBC area
Remains write protected during IAP
Up to
128 Kbytes
Flash
program
memory
Program memory area
Write access possible for IAP
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Product overview
STM8S207xx, STM8S208xx
Read-out protection (ROP)
The read-out protection blocks reading and writing the Flash program memory and data
EEPROM memory in ICP mode (and debug mode). Once the read-out protection is
activated, any attempt to toggle its status triggers a global erase of the program and data
memory. Even if no protection can be considered as totally unbreakable, the feature
provides a very high level of protection for a general purpose microcontroller.
4.5
Clock controller
The clock controller distributes the system clock (f
coming from different oscillators
MASTER)
to the core and the peripherals. It also manages clock gating for low power modes and
ensures clock robustness.
Features
●
●
Clock prescaler: To get the best compromise between speed and current
consumption the clock frequency to the CPU and peripherals can be adjusted by a
programmable prescaler.
Safe clock switching: Clock sources can be changed safely on the fly in run mode
through a configuration register. The clock signal is not switched until the new clock
source is ready. The design guarantees glitch-free switching.
●
●
Clock management: To reduce power consumption, the clock controller can stop the
clock to the core, individual peripherals or memory.
Master clock sources: Four different clock sources can be used to drive the master
clock:
–
–
–
–
1-24 MHz high-speed external crystal (HSE)
Up to 24 MHz high-speed user-external clock (HSE user-ext)
16 MHz high-speed internal RC oscillator (HSI)
128 kHz low-speed internal RC (LSI)
●
●
●
Startup clock: After reset, the microcontroller restarts by default with an internal 2
MHz clock (HSI/8). The prescaler ratio and clock source can be changed by the
application program as soon as the code execution starts.
Clock security system (CSS): This feature can be enabled by software. If an HSE
clock failure occurs, the internal RC (16 MHz/8) is automatically selected by the CSS
and an interrupt can optionally be generated.
Configurable main clock output (CCO): This outputs an external clock for use by the
application.
Table 3.
Bit
Peripheral clock gating bit assignments in CLK_PCKENR1/2 registers
Peripheral
clock
Peripheral
clock
Peripheral
clock
Peripheral
clock
Bit
Bit
Bit
PCKEN17
PCKEN16
PCKEN15
PCKEN14
TIM1
TIM3
TIM2
TIM4
PCKEN13
PCKEN12
PCKEN11
PCKEN10
UART3
UART1
SPI
PCKEN27
beCAN
PCKEN23
ADC
AWU
PCKEN26 Reserved PCKEN22
PCKEN25 Reserved PCKEN21 Reserved
PCKEN24 Reserved PCKEN20 Reserved
I2C
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STM8S207xx, STM8S208xx
Product overview
4.6
Power management
For efficent power management, the application can be put in one of four different low-power
modes. You can configure each mode to obtain the best compromise between lowest power
consumption, fastest start-up time and available wakeup sources.
●
Wait mode: In this mode, the CPU is stopped, but peripherals are kept running. The
wakeup is performed by an internal or external interrupt or reset.
●
Active halt mode with regulator on: In this mode, the CPU and peripheral clocks are
stopped. An internal wakeup is generated at programmable intervals by the auto wake
up unit (AWU). The main voltage regulator is kept powered on, so current consumption
is higher than in active halt mode with regulator off, but the wakeup time is faster.
Wakeup is triggered by the internal AWU interrupt, external interrupt or reset.
●
●
Active halt mode with regulator off: This mode is the same as active halt with
regulator on, except that the main voltage regulator is powered off, so the wake up time
is slower.
Halt mode: In this mode the microcontroller uses the least power. The CPU and
peripheral clocks are stopped, the main voltage regulator is powered off. Wakeup is
triggered by external event or reset.
4.7
Watchdog timers
The watchdog system is based on two independent timers providing maximum security to
the applications.
Activation of the watchdog timers is controlled by option bytes or by software. Once
activated, the watchdogs cannot be disabled by the user program without performing a
reset.
Window watchdog timer
The window watchdog is used to detect the occurrence of a software fault, usually
generated by external interferences or by unexpected logical conditions, which cause the
application program to abandon its normal sequence.
The window function can be used to trim the watchdog behavior to match the application
perfectly.
The application software must refresh the counter before time-out and during a limited time
window.
A reset is generated in two situations:
1. Timeout: At 16 MHz CPU clock the time-out period can be adjusted between 75 µs up
to 64 ms.
2. Refresh out of window: The downcounter is refreshed before its value is lower than the
one stored in the window register.
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Product overview
STM8S207xx, STM8S208xx
Independent watchdog timer
The independent watchdog peripheral can be used to resolve processor malfunctions due to
hardware or software failures.
It is clocked by the 128 kHZ LSI internal RC clock source, and thus stays active even in case
of a CPU clock failure
The IWDG time base spans from 60 µs to 1 s.
4.8
Auto wakeup counter
●
●
●
Used for auto wakeup from active halt mode
Clock source: Internal 128 kHz internal low frequency RC oscillator or external clock
LSI clock can be internally connected to TIM3 input capture channel 1 for calibration
4.9
Beeper
The beeper function outputs a signal on the BEEP pin for sound generation. The signal is in
the range of 1, 2 or 4 kHz.
4.10
TIM1 - 16-bit advanced control timer
This is a high-end timer designed for a wide range of control applications. With its
complementary outputs, dead-time control and center-aligned PWM capability, the field of
applications is extended to motor control, lighting and half-bridge driver
●
16-bit up, down and up/down autoreload counter with 16-bit prescaler
●
Four independent capture/compare channels (CAPCOM) configurable as input
capture, output compare, PWM generation (edge and center aligned mode) and single
pulse mode output
●
●
●
●
●
Synchronization module to control the timer with external signals
Break input to force the timer outputs into a defined state
Three complementary outputs with adjustable dead time
Encoder mode
Interrupt sources: 3 x input capture/output compare, 1 x overflow/update, 1 x break
4.11
TIM2, TIM3 - 16-bit general purpose timers
●
●
●
●
●
16-bit autoreload (AR) up-counter
15-bit prescaler adjustable to fixed power of 2 ratios 1…32768
Timers with 3 or 2 individually configurable capture/compare channels
PWM mode
Interrupt sources: 2 or 3 x input capture/output compare, 1 x overflow/update
18/103
Doc ID 14733 Rev 9
STM8S207xx, STM8S208xx
Product overview
4.12
TIM4 - 8-bit basic timer
●
●
●
8-bit autoreload, adjustable prescaler ratio to any power of 2 from 1 to 128
Clock source: CPU clock
Interrupt source: 1 x overflow/update
Table 4.
Timer
TIM timer features
Counter
Timer
synchr-
onization/
chaining
CAPCOM
channels
Counting
mode
Complem.
outputs
Ext.
trigger
size
Prescaler
(bits)
TIM1
TIM2
TIM3
TIM4
16
16
16
8
Any integer from 1 to 65536
Any power of 2 from 1 to 32768
Any power of 2 from 1 to 32768
Any power of 2 from 1 to 128
Up/down
Up
4
3
2
0
3
0
0
0
Yes
No
No
No
No
Up
Up
4.13
Analog-to-digital converter (ADC2)
STM8S20xxx performance line products contain a 10-bit successive approximation A/D
converter (ADC2) with up to 16 multiplexed input channels and the following main features:
●
●
●
●
●
●
●
Input voltage range: 0 to V
DDA
Dedicated voltage reference (VREF) pins available on 80 and 64-pin devices
Conversion time: 14 clock cycles
Single and continuous modes
External trigger input
Trigger from TIM1 TRGO
End of conversion (EOC) interrupt
4.14
Communication interfaces
The following communication interfaces are implemented:
●
UART1: Full feature UART, SPI emulation, LIN2.1 master capability, Smartcard mode,
IrDA mode, single wire mode.
●
●
●
●
UART3: Full feature UART, LIN2.1 master/slave capability
SPI : Full and half-duplex, 10 Mbit/s
I²C: Up to 400 Kbit/s
beCAN (rev. 2.0A,B) - 3 Tx mailboxes - up to 1 Mbit/s
Doc ID 14733 Rev 9
19/103
Product overview
STM8S207xx, STM8S208xx
4.14.1
UART1
Main features
●
●
●
●
●
●
●
One Mbit/s full duplex SCI
SPI emulation
High precision baud rate generator
Smartcard emulation
IrDA SIR encoder decoder
LIN master mode
Single wire half duplex mode
Asynchronous communication (UART mode)
●
●
Full duplex communication - NRZ standard format (mark/space)
Programmable transmit and receive baud rates up to 1 Mbit/s (f
/16) and capable of
CPU
following any standard baud rate regardless of the input frequency
Separate enable bits for transmitter and receiver
Two receiver wakeup modes:
●
●
–
–
Address bit (MSB)
Idle line (interrupt)
●
●
Transmission error detection with interrupt generation
Parity control
Synchronous communication
●
●
●
●
Full duplex synchronous transfers
SPI master operation
8-bit data communication
Maximum speed: 1 Mbit/s at 16 MHz (f
/16)
CPU
LIN master mode
●
●
Emission: Generates 13-bit synch break frame
Reception: Detects 11-bit break frame
4.14.2
UART3
Main features
●
●
●
1 Mbit/s full duplex SCI
LIN master capable
High precision baud rate generator
20/103
Doc ID 14733 Rev 9
STM8S207xx, STM8S208xx
Product overview
Asynchronous communication (UART mode)
●
●
Full duplex communication - NRZ standard format (mark/space)
Programmable transmit and receive baud rates up to 1 Mbit/s (f
/16) and capable of
CPU
following any standard baud rate regardless of the input frequency
Separate enable bits for transmitter and receiver
Two receiver wakeup modes:
●
●
–
–
Address bit (MSB)
Idle line (interrupt)
●
●
Transmission error detection with interrupt generation
Parity control
LIN master capability
●
●
Emission: Generates 13-bit synch break frame
Reception: Detects 11-bit break frame
LIN slave mode
●
●
●
●
●
●
●
Autonomous header handling - one single interrupt per valid message header
Automatic baud rate synchronization - maximum tolerated initial clock deviation 15 %
Synch delimiter checking
11-bit LIN synch break detection - break detection always active
Parity check on the LIN identifier field
LIN error management
Hot plugging support
4.14.3
SPI
●
●
●
●
●
●
●
Maximum speed: 10 Mbit/s (f
/2) both for master and slave
MASTER
Full duplex synchronous transfers
Simplex synchronous transfers on two lines with a possible bidirectional data line
Master or slave operation - selectable by hardware or software
CRC calculation
1 byte Tx and Rx buffer
Slave/master selection input pin
Doc ID 14733 Rev 9
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Product overview
2
STM8S207xx, STM8S208xx
4.14.4
I C
●
I2C master features:
–
–
Clock generation
Start and stop generation
●
I2C slave features:
–
–
Programmable I2C address detection
Stop bit detection
●
●
Generation and detection of 7-bit/10-bit addressing and general call
Supports different communication speeds:
–
–
Standard speed (up to 100 kHz)
Fast speed (up to 400 kHz)
4.14.5
beCAN
The beCAN controller (basic enhanced CAN), interfaces the CAN network and supports the
CAN protocol version 2.0A and B. It has been designed to manage a high number of
incoming messages efficiently with a minimum CPU load.
For safety-critical applications the beCAN controller provides all hardware functions to
support the CAN time triggered communication option (TTCAN).
The maximum transmission speed is 1 Mbit.
Transmission
●
●
●
Three transmit mailboxes
Configurable transmit priority by identifier or order request
Time stamp on SOF transmission
Reception
●
●
●
●
●
●
●
8-, 11- and 29-bit ID
One receive FIFO (3 messages deep)
Software-efficient mailbox mapping at a unique address space
FMI (filter match index) stored with message
Configurable FIFO overrun
Time stamp on SOF reception
Six filter banks, 2 x 32 bytes (scalable to 4 x 16-bit) each, enabling various masking
configurations, such as 12 filters for 29-bit ID or 48 filters for 11-bit ID
●
●
Filtering modes:
–
–
Mask mode permitting ID range filtering
ID list mode
Time triggered communication option
–
–
–
–
Disable automatic retransmission mode
16-bit free running timer
Configurable timer resolution
Time stamp sent in last two data bytes
22/103
Doc ID 14733 Rev 9
STM8S207xx, STM8S208xx
Pinouts and pin description
5
Pinouts and pin description
5.1
Package pinouts
Figure 3.
LQFP 80-pin pinout
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
1
2
3
4
5
6
7
8
NRST
OSCIN/PA1
OSCOUT/PA2
PI3
PI2
PI1
PI0
V
SSIO_1
V
PG4
PG3
PG2
PG1/CAN_RX
PG0/CAN_TX
PC7 (HS)/SPI_MISO
PC6 (HS)/SPI_MOSI
SS
VCAP
V
DD
V
DDIO_1
9
[TIM3_CH1] TIM2_CH3/PA3
UART1_RX/ (HS) PA4
UART1_TX/ (HS) PA5
UART1_CK/ (HS) PA6
(HS) PH0
10
11
12
13
14
15
16
17
18
19
20
V
V
DDIO_2
SSIO_2
(HS) PH1
PC5 (HS)/SPI_SCK
PH2
PH3
AIN15/PF7
AIN14/PF6
AIN13/PF5
AIN12/PF4
PC4 (HS)/TIM1_CH4
PC3 (HS)/TIM1_CH3
PC2 (HS)/TIM1_CH2
PC1 (HS)/TIM1_CH1
PC0/ADC_ETR
PE5/SPI_NSS
1. (HS) high sink capability.
2. (T) True open drain (P-buffer and protection diode to V not implemented).
DD
3. [ ] alternate function remapping option (If the same alternate function is shown twice, it indicates an exclusive choice not a
duplication of the function).
4. CAN_RX and CAN_TX is available on STM8S208xx devices only.
Doc ID 14733 Rev 9
23/103
Pinouts and pin description
Figure 4. LQFP 64-pin pinout
STM8S207xx, STM8S208xx
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
PI0
PG4
PG3
PG2
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
NRST
OSCIN/PA1
OSCOUT/PA2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
V
SSIO_1
PG1/CAN_RX
PG0/CAN_TX
PC7 (HS)/SPI_MISO
PC6 (HS)/SPI_MOSI
V
SS
VCAP
V
DD
V
DDIO_1
V
[TIM3_CH1] TIM2_CH3/PA3
UART1_RX/ (HS) PA4
UART1_TX/ (HS) PA5
UART1_CK/ (HS) PA6
AIN15/PF7
DDIO_2
V
SSIO_2
PC5 (HS)/SPI_SCK
PC4 (HS)/TIM1_CH4
PC3 (HS)/TIM1_CH3
PC2 (HS)/TIM1_CH2
PC1 (HS)/TIM1_CH1
PE5/SPI_NSS
AIN14/PF6
AIN13/PF5
AIN12/PF4
1718 19202122232425 26272829303132
1. (HS) high sink capability.
2. (T) True open drain (P-buffer and protection diode to V not implemented).
DD
3. [ ] alternate function remapping option (If the same alternate function is shown twice, it indicates an exclusive choice not a
duplication of the function).
4. CAN_RX and CAN_TX is available on STM8S208xx devices only.
24/103
Doc ID 14733 Rev 9
STM8S207xx, STM8S208xx
Figure 5. LQFP 48-pin pinout
Pinouts and pin description
48474645 4443424140393837
36
NRST
OSCIN/PA1
PG1/CAN_RX
1
2
35 PG0/CAN_TX
OSCOUT/PA2
3
4
34 PC7 (HS)/SPI_MISO
33 PC6 (HS)/SPI_MOSI
V
SSIO_1
V
32
5
6
7
8
9
10
11
V
V
SS
DDIO_2
31
30
29
28
27
26
25
VCAP
SSIO_2
V
PC5 (HS)/SPI_SCK
PC4 (HS)/TIM1_CH4
PC3 (HS)/TIM1_CH3
PC2 (HS)/TIM1_CH2
PC1 (HS)/TIM1_CH1
PE5/SPI_NSS
DD
V
DDIO_1
[TIM3_CH1] TIM2_CH3/PA3
UART1_RX/(HS) PA4
UART1_TX/(HS) PA5
UART1_CK/(HS) PA6
12
24
1314 151617181920212223
1. (HS) high sink capability.
2. (T) True open drain (P-buffer and protection diode to V not implemented).
DD
3. [ ] alternate function remapping option (If the same alternate function is shown twice, it indicates an exclusive choice not a
duplication of the function).
4. CAN_RX and CAN_TX is available on STM8S208xx devices only.
Doc ID 14733 Rev 9
25/103
Pinouts and pin description
Figure 6. LQFP 44-pin pinout
STM8S207xx, STM8S208xx
44 43 42 41 40 39 38 37 36 35 34
NRST
OSCIN/PA1
OSCOUT/PA2
1
2
3
4
5
6
PG1/CAN_RX
PG0/CAN_TX
PC7 (HS)/SPI_MISO
PC6 (HS)/SPI_MOSI
33
32
31
30
29
28
V
SSIO_1
V
V
SS
DDIO_2
VCAP
V
SSIO_2
V
7
8
9
10
11
27 PC5 (HS)/SPI_SCK
26 PC3 (HS)/TIM1_CH3
25 PC2 (HS)/TIM1_CH2
24 PC1 (HS)/TIM1_CH1
23 PE5/SPI_NSS
DD
V
DDIO_1
UART1_RX/
UART1_TX/
UART1_CK/
1213141516 171819202122
1. (HS) high sink capability.
2. (T) True open drain (P-buffer and protection diode to V not implemented).
DD
3. [ ] alternate function remapping option (If the same alternate function is shown twice, it indicates an exclusive choice not a
duplication of the function).
4. CAN_RX and CAN_TX is available on STM8S208xx devices only.
26/103
Doc ID 14733 Rev 9
STM8S207xx, STM8S208xx
Figure 7. LQFP 32-pin pinout
Pinouts and pin description
32 31 30 29 28 27 26 25
24
NRST
OSCIN/PA1
OSCOUT/PA2
1
2
3
4
5
6
7
8
PC7 (HS)/SPI_MISO
23
22
21
20
19
18
17
PC6 (HS)/SPI_MOSI
PC5 (HS)/SPI_SCK
PC4 (HS)/TIM1_CH4
PC3 (HS)/TIM1_CH3
PC2 (HS)/TIM1_CH2
PC1 (HS)/TIM1_CH1
PE5/SPI_NSS
V
SS
VCAP
V
DD
V
DDIO
AIN12/PF4
9 10111213141516
1. (HS) high sink capability.
2. [ ] alternate function remapping option (If the same alternate function is shown twice, it indicates an exclusive choice not a
duplication of the function).
Table 5.
Type
Legend/abbreviations
I= Input, O = Output, S = Power supply
Level
Input
CM = CMOS
Output
HS = High sink
Output speed
O1 = Slow (up to 2 MHz)
O2 = Fast (up to 10 MHz)
O3 = Fast/slow programmability with slow as default state after reset
O4 = Fast/slow programmability with fast as default state after reset
Port and control Input
float = floating, wpu = weak pull-up
configuration
Output
Bold X
T = True open drain, OD = Open drain, PP = Push pull
Reset state
Doc ID 14733 Rev 9
27/103
Pinouts and pin description
STM8S207xx, STM8S208xx
Table 6.
Pin description
Pin number
Input
Output
Alternate
Default
function
after remap
[option bit]
Pin name
alternate
function
1
2
1
2
1
2
1
2
1 NRST
I/O
I/O
X
Reset
Resonator/
crystal in
2 PA1/OSCIN
X
X
X
O1
O1
X
X
X
X
Port A1
Port A2
Resonator/
crystal out
3
3
3
3
3 PA2/OSCOUT
I/O
X
X
4
5
6
7
8
4
5
6
7
8
4
5
6
7
8
4
5
6
7
8
-
VSSIO_1
S
S
S
S
S
I/O ground
4 VSS
Digital ground
5 VCAP
6 VDD
1.8 V regulator capacitor
Digital power supply
I/O power supply
7 VDDIO_1
Timer 2 -
Port A3
TIM3_CH1
[AFR1]
9
9
9
-
-
-
-
PA3/TIM2_CH3
I/O
X
X
X
X
X
X
X
X
X
O1
HS O3
HS O3
X
X
X
X
X
X
channel3
10 10 10
9
PA4/UART1_RX(1) I/O
Port A4 UART1 receive
UART1
Port A5
11 11 11 10
12 12 12 11
PA5/UART1_TX
I/O
transmit
UART1
Port A6 synchronous
clock
-
PA6/UART1_CK I/O
X
X
X
HS O3
X
X
13
14
15
16
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
PH0
PH1
PH2
PH3
I/O
I/O
I/O
I/O
X
X
X
X
X
X
X
X
HS O3
HS O3
O1
X
X
X
X
X
X
X
X
Port H0
Port H1
Port H2
Port H3
O1
Analog
Port F7
17 13
18 14
19 15
20 16
21 17
22 18
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
PF7/AIN15
PF6/AIN14
PF5/AIN13
I/O
I/O
I/O
I/O
I/O
X
X
X
X
X
X
X
X
X
X
O1
O1
O1
O1
O1
X
X
X
X
X
X
X
X
X
X
input 15
Analog
Port F6
input 14
Analog
Port F5
input 13
Analog
Port F4
8 PF4/AIN12
input 12
Analog
Port F3
-
-
PF3/AIN11
VREF+
input 11
ADC positive reference
voltage
S
S
23 19 13 12 9 VDDA
Analog power supply
28/103
Doc ID 14733 Rev 9
STM8S207xx, STM8S208xx
Pinouts and pin description
Table 6.
Pin description (continued)
Pin number
Input
Output
Alternate
Default
function
Pin name
alternate
after remap
function
[option bit]
24 20 14 13 10 VSSA
S
S
Analog ground
ADC negative reference
voltage
25 21
26 22
-
-
-
-
-
-
-
-
VREF-
Analog
Port F0
PF0/AIN10
PB7/AIN7
PB6/AIN6
I/O
I/O
I/O
I/O
I/O
I/O
X
X
X
X
X
X
X
X
X
X
X
X
O1
O1
O1
O1
O1
O1
X
X
X
X
X
X
X
X
X
X
X
X
input 10
Analog
Port B7
27 23 15 14
28 24 16 15
X
X
X
X
X
input 7
Analog
Port B6
input 6
Analog
Port B5
I2C_SDA
[AFR6]
29 25 17 16 11 PB5/AIN5
30 26 18 17 12 PB4/AIN4
31 27 19 18 13 PB3/AIN3
input 5
Analog
Port B4
I2C_SCL
[AFR6]
input 4
Analog
Port B3
TIM1_ETR
[AFR5]
input 3
TIM1_
CH3N
[AFR5]
Analog
Port B2
32 28 20 19 14 PB2/AIN2
33 29 21 20 15 PB1/AIN1
34 30 22 21 16 PB0/AIN0
I/O
I/O
X
X
X
X
X
X
X
O1
O1
X
X
X
X
input 2
TIM1_
CH2N
[AFR5]
Analog
Port B1
input 1
TIM1_
CH1N
[AFR5]
Analog
Port B0
I/O
I/O
X
X
X
X
X
X
O1
O1
O1
X
X
X
X
X
X
input 0
Timer 1 -
Port H4
35
36
-
-
-
-
-
-
-
-
PH4/TIM1_ETR
trigger input
Timer 1 -
Port H5 inverted
channel 3
PH5/ TIM1_CH3N I/O
PH6/ TIM1_CH2N I/O
PH7/ TIM1_CH1N I/O
Timer 1 -
Port H6 inverted
channel 2
37
38
-
-
-
-
-
-
-
X
X
X
X
O1
O1
X
X
X
X
Timer 1 -
Port H7 inverted
channel 2
-
-
39 31 23
-
-
PE7/AIN8
PE6/AIN9
I/O
I/O
X
X
X
X
X
X
O1
O1
X
X
X
X
Port E7 Analog input 8
Port E6 Analog input 9
40 32 24 22
Doc ID 14733 Rev 9
29/103
Pinouts and pin description
STM8S207xx, STM8S208xx
Table 6.
Pin description (continued)
Pin number
Input
Output
Alternate
Default
function
Pin name
alternate
after remap
function
[option bit]
SPI
41 33 25 23 17 PE5/SPI_NSS
I/O
X
X
X
O1
X
X
Port E5 master/slave
select
ADC trigger
input
42
-
-
-
-
PC0/ADC_ETR
I/O
I/O
I/O
I/O
I/O
X
X
X
X
X
X
X
X
X
X
X
X
O1
HS O3
HS O3
HS O3
X
X
X
X
X
X
X
X
Port C0
Port C1
Port C2
Port C3
Port C4
Timer 1 -
channel 1
43 34 26 24 18 PC1/TIM1_CH1
44 35 27 25 19 PC2/TIM1_CH2
45 36 28 26 20 PC3/TIM1_CH3
Timer 1-
channel 2
Timer 1 -
channel 3
Timer 1 -
channel 4
46 37 29
-
21 PC4/TIM1_CH4
X
X
X
X
X
X
HS O3
HS O3
X
X
X
X
47 38 30 27 22 PC5/SPI_SCK
I/O
S
Port C5 SPI clock
I/O ground
48 39 31 28
49 40 32 29
-
-
VSSIO_2
VDDIO_2
S
I/O power supply
SPI master
Port C6 out/
slave in
50 41 33 30 23 PC6/SPI_MOSI
51 42 34 31 24 PC7/SPI_MISO
I/O
I/O
X
X
X
X
HS O3
X
X
SPI master in/
Port C7
X
X
X
X
HS O3
O1
X
X
X
X
slave out
beCAN
Port G0
52 43 35 32
53 44 36 33
-
PG0/CAN_TX(2) I/O
PG1/CAN_RX(2) I/O
transmit
-
-
-
-
-
-
-
-
-
-
-
-
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
O1
O1
O1
O1
O1
O1
O1
O1
O1
O1
O1
O1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Port G1 beCAN receive
Port G2
Port G3
Port G4
Port I0
54 45
55 46
56 47
57 48
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
PG2
PG3
PG4
PI0
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
58
59
60
61
62
-
-
-
-
-
PI1
Port I1
PI2
Port I2
PI3
Port I3
PI4
Port I4
PI5
Port I5
63 49
64 50
PG5
PG6
Port G5
Port G6
30/103
Doc ID 14733 Rev 9
STM8S207xx, STM8S208xx
Pinouts and pin description
Table 6.
Pin description (continued)
Pin number
Input
Output
Alternate
Default
function
Pin name
alternate
after remap
function
[option bit]
65 51
66 52
-
-
-
-
-
-
PG7
PE4
I/O
I/O
X
X
X
X
O1
O1
X
X
X
X
Port G7
X
X
Port E4
Port E3
Timer 1 -
break input
67 53 37
-
-
PE3/TIM1_BKIN I/O
X
X
O1
X
X
68 54 38 34
69 55 39 35
-
-
PE2/I2C_SDA
PE1/I2C_SCL
I/O
I/O
X
X
X
X
O1 T(3)
O1 T(3)
Port E2 I2C data
Port E1 I2C clock
Configurable
clock output
70 56 40 36
-
PE0/CLK_CCO
I/O
X
X
X
HS O3
X
X
Port E0
71
72
-
-
-
-
-
-
-
-
PI6
PI7
I/O
I/O
X
X
X
X
O1
O1
X
X
X
X
Port I6
Port I7
TIM1_BKIN
[AFR3]/
CLK_CCO
[AFR2]
Timer 3 -
channel 2
73 57 41 37 25 PD0/TIM3_CH2
I/O
X
X
X
HS O3
X
X
Port D0
SWIM data
interface
74 58 42 38 26 PD1/SWIM
75 59 43 39 27 PD2/TIM3_CH1
76 60 44 40 28 PD3/TIM2_CH2
I/O
I/O
I/O
I/O
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
HS O4
HS O3
HS O3
HS O3
O1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Port D1
Port D2
Port D3
Port D4
Port D5
Port D6
Port D7
Timer 3 -
channel 1
TIM2_CH3
[AFR1]
Timer 2 -
channel 2
ADC_ETR
[AFR0]
PD4/TIM2_CH1/B
Timer 2 -
channel 1
BEEP output
[AFR7]
77 61 45 41 29
EEP
UART3 data
transmit
78 62 46 42 30 PD5/ UART3_TX I/O
PD6/
UART3 data
receive
79 63 47 43 31
I/O
I/O
O1
UART3_RX(1)
Top level
interrupt
TIM1_CH4
[AFR4]
80 64 48 44 32 PD7/TLI
O1
1. The default state of UART1_RX and UART3_RX pins is controlled by the ROM bootloader. These pins are pulled up as
part of the bootloader activation process and returned to the floating state before a return from the bootloader.
2. The beCAN interface is available on STM8S208xx devices only
3. In the open-drain output column, ‘T’ defines a true open-drain I/O (P-buffer and protection diode to VDD are not
implemented).
Doc ID 14733 Rev 9
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Pinouts and pin description
STM8S207xx, STM8S208xx
5.2
Alternate function remapping
As shown in the rightmost column of the pin description table, some alternate functions can
be remapped at different I/O ports by programming one of eight AFR (alternate function
remap) option bits. Refer to Section 8: Option bytes on page 47. When the remapping
option is active, the default alternate function is no longer available.
To use an alternate function, the corresponding peripheral must be enabled in the peripheral
registers.
Alternate function remapping does not effect GPIO capabilities of the I/O ports (see the
GPIO section of the family reference manual, RM0016).
32/103
Doc ID 14733 Rev 9
STM8S207xx, STM8S208xx
Memory and register map
6
Memory and register map
6.1
Memory map
Figure 8.
Memory map
0x00 0000
RAM
(up to 6 Kbytes)
1024 bytes stack
Reserved
0x00 17FF
0x00 1800
0x00 3FFF
0x00 4000
Up to 2 Kbytes data EEPROM
Option bytes
0x00 47FF
0x00 4800
0x00 487F
0x00 4900
Reserved
0x00 4FFF
0x00 5000
GPIO and peripheral registers
(see Table 8 and Table 9)
0x00 57FF
0x00 5800
Reserved
0x00 5FFF
0x00 6000
2 Kbytes boot ROM
0x00 67FF
0x00 6800
Reserved
0x00 7EFF
0x00 7F00
CPU/SWIM/debug/ITC
registers
(see Table 10 )
0x00 7FFF
0x00 8000
0x00 807F
0x00 8080
32 interrupt vectors
Flash program memory
(64 to 128 Kbytes)
0x02 7FFF
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Memory and register map
STM8S207xx, STM8S208xx
Table 7 lists the boundary addresses for each memory size. The top of the stack is at the
RAM end address in each case.
Table 7.
Flash, Data EEPROM and RAM boundary addresses
Memory area
Size (bytes)
Start address
End address
128 K
64 K
32 K
0x00 8000
0x00 8000
0x00 8000
0x02 7FFF
0x01 7FFF
0x00 FFFF
Flash program memory
6 K
4 K
0x00 0000
0x00 0000
0x00 0000
0x00 4000
0x00 4000
0x00 4000
0x00 17FF
0x00 1000
0x00 07FF
0x00 47FF
0x00 45FF
0x00 43FF
RAM
2 K
2048
1536
1024
Data EEPROM
6.2
Register map
Table 8.
Address
I/O port hardware register map
Reset
status
Block
Register label
Register name
0x00 5000
0x00 5001
0x00 5002
0x00 5003
0x00 5004
0x00 5005
0x00 5006
0x00 5007
0x00 5008
0x00 5009
0x00 500A
0x00 500B
0x00 500C
0x00 500D
0x00 500E
PA_ODR
PA_IDR
Port A data output latch register
Port A input pin value register
Port A data direction register
Port A control register 1
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
Port A
PA_DDR
PA_CR1
PA_CR2
PB_ODR
PB_IDR
PB_DDR
PB_CR1
PB_CR2
PC_ODR
PB_IDR
PC_DDR
PC_CR1
PC_CR2
Port A control register 2
Port B data output latch register
Port B input pin value register
Port B data direction register
Port B control register 1
Port B
Port B control register 2
Port C data output latch register
Port C input pin value register
Port C data direction register
Port C control register 1
Port C
Port C control register 2
34/103
Doc ID 14733 Rev 9
STM8S207xx, STM8S208xx
Table 8. I/O port hardware register map (continued)
Address Register name
Memory and register map
Reset
status
Block
Register label
0x00 500F
0x00 5010
0x00 5011
0x00 5012
0x00 5013
0x00 5014
0x00 5015
0x00 5016
0x00 5017
0x00 5018
0x00 5019
0x00 501A
0x00 501B
0x00 501C
0x00 501D
0x00 501E
0x00 501F
0x00 5020
0x00 5021
0x00 5022
0x00 5023
0x00 5024
0x00 5025
0x00 5026
0x00 5027
0x00 5028
0x00 5029
0x00 502A
0x00 502B
0x00 502C
PD_ODR
PD_IDR
PD_DDR
PD_CR1
PD_CR2
PE_ODR
PE_IDR
PE_DDR
PE_CR1
PE_CR2
PF_ODR
PF_IDR
PF_DDR
PF_CR1
PF_CR2
PG_ODR
PG_IDR
PG_DDR
PG_CR1
PG_CR2
PH_ODR
PH_IDR
PH_DDR
PH_CR1
PH_CR2
PI_ODR
PI_IDR
Port D data output latch register
Port D input pin value register
Port D data direction register
Port D control register 1
0x00
0x00
0x00
0x02
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
Port D
Port D control register 2
Port E data output latch register
Port E input pin value register
Port E data direction register
Port E control register 1
Port E
Port F
Port G
Port H
Port I
Port E control register 2
Port F data output latch register
Port F input pin value register
Port F data direction register
Port F control register 1
Port F control register 2
Port G data output latch register
Port G input pin value register
Port G data direction register
Port G control register 1
Port G control register 2
Port H data output latch register
Port H input pin value register
Port H data direction register
Port H control register 1
Port H control register 2
Port I data output latch register
Port I input pin value register
Port I data direction register
Port I control register 1
PI_DDR
PI_CR1
PI_CR2
Port I control register 2
Doc ID 14733 Rev 9
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Memory and register map
STM8S207xx, STM8S208xx
Reset
Table 9.
General hardware register map
Address
Block
Register label
Register name
status
0x00 5050
to
0x00 5059
Reserved area (10 bytes)
Flash control register 1
0x00 505A
0x00 505B
0x00 505C
0x00 505D
0x00 505E
FLASH_CR1
FLASH_CR2
FLASH_NCR2
FLASH _FPR
FLASH _NFPR
0x00
0x00
0xFF
0x00
0xFF
Flash control register 2
Flash complementary control register 2
Flash protection register
Flash
Flash complementary protection register
Flash in-application programming status
register
0x00 505F
FLASH _IAPSR
0x00
0x00 5060 to
0x00 5061
Reserved area (2 bytes)
Flash Program memory unprotection
register
0x00 5062
Flash
Flash
FLASH _PUKR
FLASH _DUKR
0x00
0x00
0x00 5063
0x00 5064
Reserved area (1 byte)
Data EEPROM unprotection register
0x00 5065 to
0x00 509F
Reserved area (59 bytes)
0x00 50A0
0x00 50A1
EXTI_CR1
EXTI_CR2
External interrupt control register 1
External interrupt control register 2
0x00
0x00
ITC
RST
CLK
0x00 50A2 to
0x00 50B2
Reserved area (17 bytes)
Reset status register
0x00 50B3
RST_SR
xx
0x00 50B4 to
0x00 50BF
Reserved area (12 bytes)
0x00 50C0
0x00 50C1
0x00 50C2
CLK_ICKR
CLK_ECKR
Internal clock control register
External clock control register
Reserved area (1 byte)
0x01
0x00
36/103
Doc ID 14733 Rev 9
STM8S207xx, STM8S208xx
Table 9. General hardware register map (continued)
Address
Memory and register map
Reset
Block
Register label
Register name
status
0x00 50C3
0x00 50C4
CLK_CMSR
CLK_SWR
Clock master status register
Clock master switch register
0xE1
0xE1
0bxxxx
0000
0x00 50C5
CLK_SWCR
Clock switch control register
0x00 50C6
0x00 50C7
0x00 50C8
0x00 50C9
0x00 50CA
0x00 50CB
0x00 50CC
0x00 50CD
CLK_CKDIVR
CLK_PCKENR1
CLK_CSSR
Clock divider register
Peripheral clock gating register 1
Clock security system register
Configurable clock control register
Peripheral clock gating register 2
CAN clock control register
0x18
0xFF
0x00
0x00
0xFF
0x00
xx
CLK
CLK_CCOR
CLK_PCKENR2
CLK_CANCCR
CLK_HSITRIMR
CLK_SWIMCCR
HSI clock calibration trimming register
SWIM clock control register
x0
0x00 50CE to
0x00 50D0
Reserved area (3 bytes)
0x00 50D1
0x00 50D2
WWDG_CR
WWDG_WR
WWDG control register
WWDR window register
0x7F
0x7F
WWDG
IWDG
0x00 50D3 to
0x00 50DF
Reserved area (13 bytes)
0x00 50E0
0x00 50E1
0x00 50E2
IWDG_KR
IWDG_PR
IWDG_RLR
IWDG key register
IWDG prescaler register
IWDG reload register
-
0x00
0xFF
0x00 50E3 to
0x00 50EF
Reserved area (13 bytes)
0x00 50F0
0x00 50F1
0x00 50F2
0x00 50F3
AWU_CSR1
AWU_APR
AWU_TBR
BEEP_CSR
AWU control/status register 1
AWU asynchronous prescaler buffer register
AWU timebase selection register
BEEP control/status register
0x00
0x3F
0x00
0x1F
AWU
BEEP
0x00 50F4 to
0x00 50FF
Reserved area (12 bytes)
Doc ID 14733 Rev 9
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Memory and register map
Table 9. General hardware register map (continued)
Address
STM8S207xx, STM8S208xx
Reset
Block
Register label
Register name
status
00 5200h
00 5201h
00 5202h
00 5203h
00 5204h
00 5205h
00 5206h
00 5207h
SPI_CR1
SPI_CR2
SPI control register 1
SPI control register 2
SPI interrupt control register
SPI status register
0x00
0x00
0x00
0x02
0x00
0x07
0xFF
0xFF
SPI_ICR
SPI_SR
SPI
SPI_DR
SPI data register
SPI_CRCPR
SPI_RXCRCR
SPI_TXCRCR
SPI CRC polynomial register
SPI Rx CRC register
SPI Tx CRC register
00 5208h to
00 520Fh
Reserved area (8 bytes)
00 5210h
00 5211h
00 5212h
00 5213h
00 5214h
00 5215h
00 5216h
00 5217h
00 5218h
00 5219h
00 521Ah
00 521Bh
00 521Ch
00 521Dh
00 521Eh
I2C_CR1
I2C_CR2
I2C control register 1
I2C control register 2
0x00
0x00
0x00
0x00
0x00
I2C_FREQR
I2C_OARL
I2C_OARH
I2C frequency register
I2C own address register low
I2C own address register high
Reserved
I2C_DR
I2C_SR1
I2C data register
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x02
0x00
I2C
I2C status register 1
I2C_SR2
I2C status register 2
I2C_SR3
I2C status register 3
I2C_ITR
I2C interrupt control register
I2C clock control register low
I2C clock control register high
I2C TRISE register
I2C_CCRL
I2C_CCRH
I2C_TRISER
I2C_PECR
I2C packet error checking register
00 521Fh to
00 522Fh
Reserved area (17 bytes)
38/103
Doc ID 14733 Rev 9
STM8S207xx, STM8S208xx
Table 9. General hardware register map (continued)
Address
Memory and register map
Reset
Block
Register label
Register name
status
0x00 5230
0x00 5231
0x00 5232
0x00 5233
0x00 5234
0x00 5235
0x00 5236
0x00 5237
0x00 5238
0x00 5239
0x00 523A
UART1_SR
UART1_DR
UART1 status register
UART1 data register
0xC0
xx
UART1_BRR1
UART1_BRR2
UART1_CR1
UART1_CR2
UART1_CR3
UART1_CR4
UART1_CR5
UART1_GTR
UART1_PSCR
UART1 baud rate register 1
UART1 baud rate register 2
UART1 control register 1
UART1 control register 2
UART1 control register 3
UART1 control register 4
UART1 control register 5
UART1 guard time register
UART1 prescaler register
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
UART1
0x00 523B to
0x00 523F
Reserved area (5 bytes)
0x00 5240
0x00 5241
0x00 5242
0x00 5243
0x00 5244
0x00 5245
0x00 5246
005247
UART3_SR
UART3_DR
UART3 status register
UART3 data register
C0h
xx
UART3_BRR1
UART3_BRR2
UART3_CR1
UART3_CR2
UART3_CR3
UART3_CR4
UART3 baud rate register 1
UART3 baud rate register 2
UART3 control register 1
UART3 control register 2
UART3 control register 3
UART3 control register 4
Reserved
0x00
0x00
0x00
0x00
0x00
0x00
UART3
0x00 5248
0x00 5249
UART3_CR6
UART3 control register 6
0x00
0x00 524A to
0x00 524F
Reserved area (6 bytes)
Doc ID 14733 Rev 9
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Memory and register map
Table 9. General hardware register map (continued)
Address
STM8S207xx, STM8S208xx
Reset
Block
Register label
Register name
status
0x00 5250
0x00 5251
0x00 5252
0x00 5253
0x00 5254
0x00 5255
0x00 5256
0x00 5257
0x00 5258
0x00 5259
0x00 525A
0x00 525B
0x00 525C
0x00 525D
0x00 525E
0x00 525F
0x00 5260
0x00 5261
0x00 5262
0x00 5263
0x00 5264
0x00 5265
0x00 5266
0x00 5267
0x00 5268
0x00 5269
0x00 526A
0x00 526B
0x00 526C
0x00 526D
0x00 526E
0x00 526F
TIM1_CR1
TIM1_CR2
TIM1 control register 1
TIM1 control register 2
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0xFF
0xFF
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
TIM1_SMCR
TIM1_ETR
TIM1 slave mode control register
TIM1 external trigger register
TIM1 Interrupt enable register
TIM1 status register 1
TIM1_IER
TIM1_SR1
TIM1_SR2
TIM1 status register 2
TIM1_EGR
TIM1 event generation register
TIM1 capture/compare mode register 1
TIM1 capture/compare mode register 2
TIM1 capture/compare mode register 3
TIM1 capture/compare mode register 4
TIM1 capture/compare enable register 1
TIM1 capture/compare enable register 2
TIM1 counter high
TIM1_CCMR1
TIM1_CCMR2
TIM1_CCMR3
TIM1_CCMR4
TIM1_CCER1
TIM1_CCER2
TIM1_CNTRH
TIM1_CNTRL
TIM1_PSCRH
TIM1_PSCRL
TIM1_ARRH
TIM1_ARRL
TIM1_RCR
TIM1 counter low
TIM1
TIM1 prescaler register high
TIM1 prescaler register low
TIM1 auto-reload register high
TIM1 auto-reload register low
TIM1 repetition counter register
TIM1 capture/compare register 1 high
TIM1 capture/compare register 1 low
TIM1 capture/compare register 2 high
TIM1 capture/compare register 2 low
TIM1 capture/compare register 3 high
TIM1 capture/compare register 3 low
TIM1 capture/compare register 4 high
TIM1 capture/compare register 4 low
TIM1 break register
TIM1_CCR1H
TIM1_CCR1L
TIM1_CCR2H
TIM1_CCR2L
TIM1_CCR3H
TIM1_CCR3L
TIM1_CCR4H
TIM1_CCR4L
TIM1_BKR
TIM1_DTR
TIM1 dead-time register
TIM1_OISR
TIM1 output idle state register
0x00 5270 to
0x00 52FF
Reserved area (147 bytes)
40/103
Doc ID 14733 Rev 9
STM8S207xx, STM8S208xx
Table 9. General hardware register map (continued)
Address
Memory and register map
Reset
Block
Register label
Register name
status
0x00 5300
0x00 5301
0x00 5302
0x00 5303
0x00 5304
0x00 5305
0x00 5306
0x00 5307
0x00 5308
0x00 5309
0x00 530A
0x00 530B
00 530C0x
0x00 530D
0x00 530E
0x00 530F
0x00 5310
0x00 5311
0x00 5312
0x00 5313
0x00 5314
TIM2_CR1
TIM2_IER
TIM2 control register 1
TIM2 interrupt enable register
TIM2 status register 1
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0xFF
0xFF
0x00
0x00
0x00
0x00
0x00
0x00
TIM2_SR1
TIM2_SR2
TIM2 status register 2
TIM2_EGR
TIM2 event generation register
TIM2 capture/compare mode register 1
TIM2 capture/compare mode register 2
TIM2 capture/compare mode register 3
TIM2 capture/compare enable register 1
TIM2 capture/compare enable register 2
TIM2 counter high
TIM2_CCMR1
TIM2_CCMR2
TIM2_CCMR3
TIM2_CCER1
TIM2_CCER2
TIM2_CNTRH
TIM2_CNTRL
TIM2_PSCR
TIM2_ARRH
TIM2_ARRL
TIM2_CCR1H
TIM2_CCR1L
TIM2_CCR2H
TIM2_CCR2L
TIM2_CCR3H
TIM2_CCR3L
TIM2
TIM2 counter low
TIM2 prescaler register
TIM2 auto-reload register high
TIM2 auto-reload register low
TIM2 capture/compare register 1 high
TIM2 capture/compare register 1 low
TIM2 capture/compare reg. 2 high
TIM2 capture/compare register 2 low
TIM2 capture/compare register 3 high
TIM2 capture/compare register 3 low
0x00 5315 to
0x00 531F
Reserved area (11 bytes)
Doc ID 14733 Rev 9
41/103
Memory and register map
Table 9. General hardware register map (continued)
Address
STM8S207xx, STM8S208xx
Reset
Block
Register label
Register name
status
0x00 5320
0x00 5321
0x00 5322
0x00 5323
0x00 5324
0x00 5325
0x00 5326
0x00 5327
0x00 5328
0x00 5329
0x00 532A
0x00 532B
0x00 532C
0x00 532D
0x00 532E
0x00 532F
0x00 5330
TIM3_CR1
TIM3_IER
TIM3 control register 1
TIM3 interrupt enable register
TIM3 status register 1
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0xFF
0xFF
0x00
0x00
0x00
0x00
TIM3_SR1
TIM3_SR2
TIM3 status register 2
TIM3_EGR
TIM3 event generation register
TIM3 capture/compare mode register 1
TIM3 capture/compare mode register 2
TIM3 capture/compare enable register 1
TIM3 counter high
TIM3_CCMR1
TIM3_CCMR2
TIM3_CCER1
TIM3_CNTRH
TIM3_CNTRL
TIM3_PSCR
TIM3_ARRH
TIM3_ARRL
TIM3_CCR1H
TIM3_CCR1L
TIM3_CCR2H
TIM3_CCR2L
TIM3
TIM3 counter low
TIM3 prescaler register
TIM3 auto-reload register high
TIM3 auto-reload register low
TIM3 capture/compare register 1 high
TIM3 capture/compare register 1 low
TIM3 capture/compare register 2 high
TIM3 capture/compare register 2 low
0x00 5331 to
0x00 533F
Reserved area (15 bytes)
0x00 5340
0x00 5341
0x00 5342
0x00 5343
0x00 5344
0x00 5345
0x00 5346
TIM4_CR1
TIM4_IER
TIM4 control register 1
TIM4 interrupt enable register
TIM4 status register
0x00
0x00
0x00
0x00
0x00
0x00
0xFF
TIM4_SR
TIM4
TIM4_EGR
TIM4_CNTR
TIM4_PSCR
TIM4_ARR
TIM4 event generation register
TIM4 counter
TIM4 prescaler register
TIM4 auto-reload register
0x00 5347 to
0x00 53FF
Reserved area (185 bytes)
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Doc ID 14733 Rev 9
STM8S207xx, STM8S208xx
Table 9. General hardware register map (continued)
Address
Memory and register map
Reset
Block
Register label
Register name
status
0x00 5400
0x00 5401
0x00 5402
0x00 5403
0x00 5404
0x00 5405
0x00 5406
0x00 5407
ADC _CSR
ADC_CR1
ADC_CR2
ADC_CR3
ADC_DRH
ADC_DRL
ADC_TDRH
ADC_TDRL
ADC control/status register
ADC configuration register 1
ADC configuration register 2
ADC configuration register 3
ADC data register high
0x00
0x00
0x00
0x00
ADC2
undefined
undefined
0x00
ADC data register low
ADC Schmitt trigger disable register high
ADC Schmitt trigger disable register low
0x00
0x00 5408 to
0x00 541F
Reserved area (24 bytes)
0x00 5420
0x00 5421
0x00 5422
0x00 5423
0x00 5424
0x00 5425
0x00 5426
0x00 5427
0x00 5428
0x00 5429
0x00 542A
0x00 542B
0x00 542C
0x00 542D
0x00 542E
0x00 542F
0x00 5430
0x00 5431
0x00 5432
0x00 5433
0x00 5434
0x00 5435
0x00 5436
CAN_MCR
CAN_MSR
CAN_TSR
CAN_TPR
CAN_RFR
CAN_IER
CAN_DGR
CAN_FPSR
CAN_P0
CAN_P1
CAN_P2
CAN_P3
CAN_P4
CAN_P5
CAN_P6
CAN_P7
CAN_P8
CAN_P9
CAN_PA
CAN_PB
CAN_PC
CAN_PD
CAN_PE
CAN master control register
CAN master status register
CAN transmit status register
CAN transmit priority register
CAN receive FIFO register
CAN interrupt enable register
CAN diagnosis register
CAN page selection register
CAN paged register 0
CAN paged register 1
CAN paged register 2
CAN paged register 3
CAN paged register 4
CAN paged register 5
CAN paged register 6
CAN paged register 7
CAN paged register 8
CAN paged register 9
CAN paged register A
CAN paged register B
CAN paged register C
CAN paged register D
CAN paged register E
0x02
0x02
0x00
0x0C
0x00
0x00
0x0C
0x00
beCAN
Doc ID 14733 Rev 9
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Memory and register map
Table 9. General hardware register map (continued)
Address
STM8S207xx, STM8S208xx
Reset
Block
Register label
Register name
status
beCAN
cont’d
0x00 5437
CAN_PF
CAN paged register F
Reserved area (968 bytes)
0x00 5438 to
0x00 57FF
Table 10. CPU/SWIM/debug module/interrupt controller registers
Reset
Status
Address
Block
Register Label
Register Name
0x00 7F00
0x00 7F01
0x00 7F02
0x00 7F03
0x00 7F04
0x00 7F05
0x00 7F06
0x00 7F07
0x00 7F08
0x00 7F09
0x00 7F0A
A
Accumulator
Program counter extended
Program counter high
Program counter low
X index register high
X index register low
Y index register high
Y index register low
Stack pointer high
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x17(2)
0xFF
0x28
PCE
PCH
PCL
XH
CPU(1)
XL
YH
YL
SPH
SPL
CCR
Stack pointer low
Condition code register
0x00 7F0B to
0x00 7F5F
Reserved area (85 bytes)
0x00 7F60
0x00 7F70
0x00 7F71
0x00 7F72
0x00 7F73
0x00 7F74
0x00 7F75
0x00 7F76
0x00 7F77
CPU
ITC
CFG_GCR
ITC_SPR1
ITC_SPR2
ITC_SPR3
ITC_SPR4
ITC_SPR5
ITC_SPR6
ITC_SPR7
ITC_SPR8
Global configuration register
Interrupt software priority register 1
Interrupt software priority register 2
Interrupt software priority register 3
Interrupt software priority register 4
Interrupt software priority register 5
Interrupt software priority register 6
Interrupt software priority register 7
Interrupt software priority register 8
0x00
0xFF
0xFF
0xFF
0xFF
0xFF
0xFF
0xFF
0xFF
0x00 7F78 to
0x00 7F79
Reserved area (2 bytes)
SWIM control status register
Reserved area (15 bytes)
0x00 7F80
SWIM
SWIM_CSR
0x00
0x00 7F81 to
0x00 7F8F
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Doc ID 14733 Rev 9
STM8S207xx, STM8S208xx
Memory and register map
Table 10. CPU/SWIM/debug module/interrupt controller registers (continued)
Reset
Status
Address
Block
Register Label
Register Name
0x00 7F90
0x00 7F91
0x00 7F92
0x00 7F93
0x00 7F94
0x00 7F95
0x00 7F96
0x00 7F97
0x00 7F98
0x00 7F99
0x00 7F9A
DM_BK1RE
DM_BK1RH
DM_BK1RL
DM_BK2RE
DM_BK2RH
DM_BK2RL
DM_CR1
DM breakpoint 1 register extended byte
DM breakpoint 1 register high byte
DM breakpoint 1 register low byte
DM breakpoint 2 register extended byte
DM breakpoint 2 register high byte
DM breakpoint 2 register low byte
DM debug module control register 1
DM debug module control register 2
DM debug module control/status register 1
DM debug module control/status register 2
DM enable function register
0xFF
0xFF
0xFF
0xFF
0xFF
0xFF
0x00
0x00
0x10
0x00
0xFF
DM
DM_CR2
DM_CSR1
DM_CSR2
DM_ENFCTR
0x00 7F9B to
0x00 7F9F
Reserved area (5 bytes)
1. Accessible by debug module only
2. Product dependent value, see Figure 8: Memory map.
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Interrupt vector mapping
STM8S207xx, STM8S208xx
7
Interrupt vector mapping
Table 11. Interrupt mapping
IRQ
no.
Source
block
Wakeup from
halt mode
Wakeup from
active-halt mode
Description
Vector address
RESET
TRAP
TLI
Reset
Yes
-
Yes
-
0x00 8000
0x00 8004
0x00 8008
0x00 800C
0x00 8010
0x00 8014
0x00 8018
0x00 801C
0x00 8020
0x00 8024
0x00 8028
0x00 802C
0x00 8030
Software interrupt
0
1
External top level interrupt
Auto wake up from halt
Clock controller
-
-
AWU
-
Yes
-
2
CLK
-
3
EXTI0
EXTI1
EXTI2
EXTI3
EXTI4
beCAN
beCAN
SPI
Port A external interrupts
Port B external interrupts
Port C external interrupts
Port D external interrupts
Port E external interrupts
beCAN RX interrupt
Yes(1)
Yes
Yes
Yes
Yes
Yes
-
Yes(1)
Yes
Yes
Yes
Yes
Yes
-
4
5
6
7
8
9
beCAN TX/ER/SC interrupt
End of transfer
10
Yes
Yes
TIM1 update/overflow/underflow/
trigger/break
11
TIM1
-
-
0x00 8034
12
13
14
15
16
17
18
19
20
21
22
23
24
TIM1
TIM2
TIM1 capture/compare
TIM2 update /overflow
TIM2 capture/compare
Update/overflow
-
-
0x00 8038
0x00 803C
0x00 8040
0x00 8044
0x00 8048
0x00 804C
0x00 8050
0x00 8054
0x00 8058
0x00 805C
0x00 8060
0x00 8064
0x00 8068
-
-
TIM2
-
-
TIM3
-
-
TIM3
Capture/compare
-
-
UART1
UART1
I2C
Tx complete
-
-
Receive register DATA FULL
I2C interrupt
-
-
Yes
Yes
UART3
UART3
ADC2
TIM4
Tx complete
-
-
-
-
-
-
-
-
-
-
Receive register DATA FULL
ADC2 end of conversion
TIM4 update/overflow
EOP/WR_PG_DIS
Flash
0x00 806C to
0x00 807C
Reserved
1. Except PA1
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Doc ID 14733 Rev 9
STM8S207xx, STM8S208xx
Option bytes
8
Option bytes
Option bytes contain configurations for device hardware features as well as the memory
protection of the device. They are stored in a dedicated block of the memory. Except for the
ROP (read-out protection) byte, each option byte has to be stored twice, in a regular form
(OPTx) and a complemented one (NOPTx) for redundancy.
Option bytes can be modified in ICP mode (via SWIM) by accessing the EEPROM address
shown in Table 12: Option bytes below. Option bytes can also be modified ‘on the fly’ by the
application in IAP mode, except the ROP option that can only be modified in ICP mode (via
SWIM).
Refer to the STM8S Flash programming manual (PM0051) and STM8 SWIM
communication protocol and debug module user manual (UM0470) for information on SWIM
programming procedures.
Table 12. Option bytes
Option bits
Factory
default
setting
Option
name
Option
byte no.
Addr.
7
6
5
4
3
2
1
0
Read-out
4800h
protection
(ROP)
OPT0
ROP[7:0]
00h
4801h
4802h
4803h
OPT1
NOPT1
OPT2
UBC[7:0]
NUBC[7:0]
AFR3
00h
FFh
00h
User boot
code(UBC)
Alternate
function
remapping
(AFR)
AFR7
AFR6
AFR5
AFR4
AFR2
AFR1
AFR0
4804h
NOPT2
NAFR7
NAFR6
NAFR5
NAFR4
NAFR3
NAFR2
NAFR1
NAFR0
FFh
LSI
IWDG
_HW
WWDG
_HW
WWDG
_HALT
4805h
4806h
4807h
4808h
OPT3
Reserved
00h
FFh
00h
FFh
_EN
Watchdog
option
NLSI
_EN
NWWDG
_HW
NIWDG
_HW
NWWDG
_HALT
NOPT3
OPT4
Reserved
Reserved
Reserved
EXT
CLK
CKAWU
SEL
PRS
C1
PRS
C0
Clock option
NEXT
CLK
NCKAWUS
EL
NPR
SC1
NPR
SC0
NOPT4
4809h
480Ah
480Bh
480Ch
480Dh
480Eh
487Eh
487Fh
OPT5
HSECNT[7:0]
NHSECNT[7:0]
Reserved
00h
FFh
00h
FFh
00h
FFh
00h
FFh
HSE clock
startup
NOPT5
OPT6
Reserved
NOPT6
OPT7
Reserved
Reserved
Reserved
BL[7:0]
NBL[7:0]
Wait state
Flash wait
states
NOPT7
OPTBL
NOPTBL
Nwait state
Bootloader
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Option bytes
STM8S207xx, STM8S208xx
Table 13. Option byte description
Option byte no.
Description
ROP[7:0] Memory readout protection (ROP)
0xAA: Enable readout protection (write access via SWIM protocol)
Note: Refer to the family reference manual (RM0016) section on
Flash/EEPROM memory readout protection for details.
OPT0
UBC[7:0] User boot code area
0x00: no UBC, no write-protection
0x01: Pages 0 to 1 defined as UBC, memory write-protected
0x02: Pages 0 to 3 defined as UBC, memory write-protected
0x03: Pages 0 to 4 defined as UBC, memory write-protected
...
OPT1
0xFE: Pages 0 to 255 defined as UBC, memory write-protected
0xFF: Reserved
Note: Refer to the family reference manual (RM0016) section on
Flash/EEPROM write protection for more details.
AFR7Alternate function remapping option 7
0: Port D4 alternate function = TIM2_CH1
1: Port D4 alternate function = BEEP
AFR6 Alternate function remapping option 6
0: Port B5 alternate function = AIN5, port B4 alternate function = AIN4
1: Port B5 alternate function = I2C_SDA, port B4 alternate function =
I2C_SCL
AFR5 Alternate function remapping option 5
0: Port B3 alternate function = AIN3, port B2 alternate function = AIN2,
port B1 alternate function = AIN1, port B0 alternate function = AIN0
1: Port B3 alternate function = TIM1_ETR, port B2 alternate function =
TIM1_CH3N, port B1 alternate function = TIM1_CH2N, port B0 alternate
function = TIM1_CH1N
AFR4 Alternate function remapping option 4
0: Port D7 alternate function = TLI
1: Port D7 alternate function = TIM1_CH4
OPT2
AFR3 Alternate function remapping option 3
0: Port D0 alternate function = TIM3_CH2
1: Port D0 alternate function = TIM1_BKIN
AFR2 Alternate function remapping option 2
0: Port D0 alternate function = TIM3_CH2
1: Port D0 alternate function = CLK_CCO
Note: AFR2 option has priority over AFR3 if both are activated
AFR1 Alternate function remapping option 1
0: Port A3 alternate function = TIM2_CH3, port D2 alternate function
TIM3_CH1
1: Port A3 alternate function = TIM3_CH1, port D2 alternate function
TIM2_CH3
AFR0 Alternate function remapping option 0
0: Port D3 alternate function = TIM2_CH2
1: Port D3 alternate function = ADC_ETR
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Doc ID 14733 Rev 9
STM8S207xx, STM8S208xx
Table 13. Option byte description (continued)
Option bytes
Option byte no.
Description
LSI_EN: Low speed internal clock enable
0: LSI clock is not available as CPU clock source
1: LSI clock is available as CPU clock source
IWDG_HW: Independent watchdog
0: IWDG Independent watchdog activated by software
1: IWDG Independent watchdog activated by hardware
OPT3
WWDG_HW: Window watchdog activation
0: WWDG window watchdog activated by software
1: WWDG window watchdog activated by hardware
WWDG_HALT: Window watchdog reset on halt
0: No reset generated on halt if WWDG active
1: Reset generated on halt if WWDG active
EXTCLK: External clock selection
0: External crystal connected to OSCIN/OSCOUT
1: External clock signal on OSCIN
CKAWUSEL: Auto wakeup unit/clock
0: LSI clock source selected for AWU
1: HSE clock with prescaler selected as clock source for for AWU
OPT4
PRSC[1:0] AWU clock prescaler
00: 24 MHz to 128 kHz prescaler
01: 16 MHz to 128 kHz prescaler
10: 8 MHz to 128 kHz prescaler
11: 4 MHz to 128 kHz prescaler
HSECNT[7:0]: HSE crystal oscillator stabilization time
This configures the stabilisation time.
0x00: 2048 HSE cycles
OPT5
0xB4: 128 HSE cycles
0xD2: 8 HSE cycles
0xE1: 0.5 HSE cycles
OPT6
OPT7
Reserved
WAITSTATE Wait state configuration
This option configures the number of wait states inserted when reading
from the Flash/data EEPROM memory.
1 wait state is required if fCPU > 16 MHz.
0: No wait state
1: 1 wait state
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Option bytes
Table 13. Option byte description (continued)
STM8S207xx, STM8S208xx
Option byte no.
Description
BL[7:0] Bootloader option byte
For STM8S products, this option is checked by the boot ROM code
after reset. Depending on the content of addresses 0x487E, 0x487F,
and 0x8000 (reset vector), the CPU jumps to the bootloader or to
the reset vector. Refer to the UM0560 (STM8L/S bootloader manual)
for more details.
OPTBL
For STM8L products, the bootloader option bytes are on addresses
0xXXXX and 0xXXXX+1 (2 bytes). These option bytes control
whether the bootloader is active or not. For more details, refer to the
UM0560 (STM8L/S bootloader manual) for more details.
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STM8S207xx, STM8S208xx
Unique ID
9
Unique ID
The devices feature a 96-bit unique device identifier which provides a reference number that
is unique for any device and in any context. The 96 bits of the identifier can never be altered
by the user.
The unique device identifier can be read in single bytes and may then be concatenated
using a custom algorithm.
The unique device identifier is ideally suited:
●
For use as serial numbers
●
For use as security keys to increase the code security in the program memory while
using and combining this unique ID with software crytograhic primitives and protocols
before programming the internal memory.
●
To activate secure boot processes
Table 14. Unique ID registers (96 bits)
Unique ID bits
Content
Address
description
7
6
5
4
3
2
1
0
0x48CD
0x48CE
0x48CF
0x48D0
0x48D1
0x48D2
0x48D3
0x48D4
0x48D5
0x48D6
0x48D7
0x48D8
U_ID[7:0]
X co-ordinate on
the wafer
U_ID[15:8]
U_ID[23:16]
U_ID[31:24]
U_ID[39:32]
U_ID[47:40]
U_ID[55:48]
U_ID[63:56]
U_ID[71:64]
U_ID[79:72]
U_ID[87:80]
U_ID[95:88]
Y co-ordinate on
the wafer
Wafer number
Lot number
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Electrical characteristics
STM8S207xx, STM8S208xx
10
Electrical characteristics
10.1
Parameter conditions
Unless otherwise specified, all voltages are referred to V
.
SS
10.1.1
Minimum and maximum values
Unless otherwise specified the minimum and maximum values are guaranteed in the worst
conditions of ambient temperature, supply voltage and frequencies by tests in production on
100 % of the devices with an ambient temperature at T = 25 °C and T = T (given by
A
A
Amax
the selected temperature range).
Data based on characterization results, design simulation and/or technology characteristics
are indicated in the table footnotes and are not tested in production. Based on
characterization, the minimum and maximum values refer to sample tests and represent the
mean value plus or minus three times the standard deviation (mean 3 Σ).
10.1.2
Typical values
Unless otherwise specified, typical data are based on T = 25 °C, V = 5 V. They are given
A
DD
only as design guidelines and are not tested.
Typical ADC accuracy values are determined by characterization of a batch of samples from
a standard diffusion lot over the full temperature range, where 95% of the devices have an
error less than or equal to the value indicated (mean 2 Σ).
10.1.3
10.1.4
Typical curves
Unless otherwise specified, all typical curves are given only as design guidelines and are
not tested.
Typical current consumption
For typical current consumption measurements, V , V
and V
are connected
DD DDIO
DDA
together in the configuration shown in Figure 9.
Figure 9.
Supply current measurement conditions
5 V or 3.3 V
V
V
A
DD
DDA
V
V
V
V
DDIO
SS
SSA
SSIO
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STM8S207xx, STM8S208xx
Electrical characteristics
10.1.5
10.1.6
Pin loading conditions
Loading capacitor
The loading conditions used for pin parameter measurement are shown in Figure 10.
Figure 10. Pin loading conditions
STM8 pin
50 pF
10.1.7
Pin input voltage
The input voltage measurement on a pin of the device is described in Figure 11.
Figure 11. Pin input voltage
STM8 pin
V
IN
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Electrical characteristics
STM8S207xx, STM8S208xx
10.2
Absolute maximum ratings
Stresses above those listed as ‘absolute maximum ratings’ may cause permanent damage
to the device. This is a stress rating only and functional operation of the device under these
conditions is not implied. Exposure to maximum rating conditions for extended periods may
affect device reliability.
Table 15. Voltage characteristics
Symbol
Ratings
Min
Max
Unit
(1)
V
DDx - VSS Supply voltage (including VDDA and VDDIO
)
-0.3
6.5
6.5
Input voltage on true open drain pins (PE1, PE2)(2)
Input voltage on any other pin(2)
VSS - 0.3
VSS - 0.3
V
VIN
VDD + 0.3
50
|VDDx - VDD| Variations between different power pins
mV
|VSSx - VSS| Variations between all the different ground pins
50
see Absolute maximum
ratings (electrical
VESD
Electrostatic discharge voltage
sensitivity) on page 87
1. All power (VDD, VDDIO, VDDA) and ground (VSS, VSSIO, VSSA) pins must always be connected to the
external power supply
2. IINJ(PIN) must never be exceeded. This is implicitly insured if VIN maximum is respected. If VIN maximum
cannot be respected, the injection current must be limited externally to the IINJ(PIN) value. A positive
injection is induced by VIN>VDD while a negative injection is induced by VIN<VSS. For true open-drain pads,
there is no positive injection current, and the corresponding VIN maximum must always be respected
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STM8S207xx, STM8S208xx
Electrical characteristics
Table 16. Current characteristics
Symbol
Ratings
Max.(1)
Unit
IVDD
IVSS
Total current into VDD power lines (source)(2)
Total current out of VSS ground lines (sink)(2)
Output current sunk by any I/O and control pin
Output current source by any I/Os and control pin
60
60
20
20
IIO
Total output current sourced (sum of all I/O and control pins)
for devices with two VDDIO pins(3)
200
100
160
80
Total output current sourced (sum of all I/O and control pins)
for devices with one VDDIO pin(3)
ΣIIO
mA
Total output current sunk (sum of all I/O and control pins) for
devices with two VSSIO pins(3)
Total output current sunk (sum of all I/O and control pins) for
devices with one VSSIO pin(3)
Injected current on NRST pin
4
4
(4)(5)
IINJ(PIN)
Injected current on OSCIN pin
Injected current on any other pin(6)
Total injected current (sum of all I/O and control pins)(6)
4
(4)
ΣIINJ(PIN)
20
1. Data based on characterization results, not tested in production.
2. All power (VDD, VDDIO, VDDA) and ground (VSS, VSSIO, VSSA) pins must always be connected to the
external supply.
3. I/O pins used simultaneously for high current source/sink must be uniformly spaced around the package
between the VDDIO/VSSIO pins.
4. IINJ(PIN) must never be exceeded. This is implicitly insured if VIN maximum is respected. If VIN maximum
cannot be respected, the injection current must be limited externally to the IINJ(PIN) value. A positive
injection is induced by VIN>VDD while a negative injection is induced by VIN<VSS. For true open-drain pads,
there is no positive injection current, and the corresponding VIN maximum must always be respected
5. Negative injection disturbs the analog performance of the device. See note in Section 10.3.10: 10-bit ADC
characteristics on page 83.
6. When several inputs are submitted to a current injection, the maximum ΣIINJ(PIN) is the absolute sum of the
positive and negative injected currents (instantaneous values). These results are based on
characterization with ΣIINJ(PIN) maximum current injection on four I/O port pins of the device.
Table 17. Thermal characteristics
Symbol
Ratings
Value
Unit
TSTG
TJ
Storage temperature range
-65 to 150
150
°C
Maximum junction temperature
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Electrical characteristics
STM8S207xx, STM8S208xx
10.3
Operating conditions
The device must be used in operating conditions that respect the parameters in Table 18. In
addition, full account must be taken of all physical capacitor characteristics and tolerances.
Table 18. General operating conditions
Symbol
Parameter
Conditions
TA ≤ 105 °C
Min
Max
Unit
0
0
24
16
MHz
MHz
V
fCPU
Internal CPU clock frequency
VDD/VDD_IO Standard operating voltage
2.95
5.5
C
EXT: capacitance of
470
3300
nF
external capacitor(1)
VCAP
At 1 MHz
ESR of external capacitor(1)
ESR of external capacitor(1)
0.3
15
Ohm
nH
44, 48, 64, and 80-pin
devices, with output on 8
standard ports, 2 high sink
ports and 2 open drain ports
simultaneously(3)
443
360
Power dissipation at
TA = 85° C for suffix 6
or TA = 125° C for suffix 3
(2)
PD
mW
32-pin package, with output
on 8 standard ports and 2
high sink ports
simultaneously(3)
Ambient temperature for 6
suffix version
Maximum power dissipation
Maximum power dissipation
-40
-40
85
TA
TJ
Ambient temperature for 3
suffix version
125
°C
6 suffix version
3 suffix version
-40
-40
105
Junction temperature range
130(4)
1. Care should be taken when selecting the capacitor, due to its tolerance, as well as its dependency on
temperature, DC bias and frequency in addition to other factors.
2. To calculate PDmax(TA), use the formula PDmax = (TJmax - TA)/ΘJA (see Section 11.2: Thermal
characteristics on page 96) with the value for TJmax given in Table 18 above and the value for ΘJA given in
Table 57: Thermal characteristics.
3. Refer to Section 11.2: Thermal characteristics on page 96 for the calculation method.
4. T
is given by the test limit. Above this value the product behavior is not guaranteed.
Jmax
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STM8S207xx, STM8S208xx
Figure 12. f
Electrical characteristics
versus V
CPUmax
DD
fCPU [MHz]
24
FUNCTIONALITY GUARANTEED
@ TA -40 to 105 °C
FUNCTIONALITY
NOT GUARANTEED
IN THIS AREA
16
12
8
FUNCTIONALITY
GUARANTEED
@ TA -40 to 125 °C
4
0
2.95
4.0
5.0
5.5
SUPPLY VOLTAGE [V]
Table 19. Operating conditions at power-up/power-down
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VDD rise time rate
VDD fall time rate
2(1)
2(1)
∞
∞
tVDD
µs/V
Reset release
delay
tTEMP
VIT+
VDD rising
1.7(1)
2.95
2.88
ms
V
Power-on reset
threshold
2.65
2.58
2.8
2.73
70
Brown-out reset
threshold
VIT-
V
Brown-out reset
hysteresis
VHYS(BOR)
mV
1. Guaranteed by design, not tested in production.
10.3.1
VCAP external capacitor
Stabilization for the main regulator is achieved connecting an external capacitor C
to the
EXT
V
pin. C
is specified in Table 18. Care should be taken to limit the series inductance
CAP
EXT
to less than 15 nH.
Figure 13. External capacitor C
EXT
ESR
C
ESL
Rleak
1. Legend: ESR is the equivalent series resistance and ESL is the equivalent inductance.
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Electrical characteristics
STM8S207xx, STM8S208xx
10.3.2
Supply current characteristics
The current consumption is measured as described in Figure 9 on page 52.
Total current consumption in run mode
The MCU is placed under the following conditions:
●
All I/O pins in input mode with a static value at V or V (no load)
DD SS
●
All peripherals are disabled (clock stopped by Peripheral Clock Gating registers) except
if explicitly mentioned.
●
When the MCU is clocked at 24 MHz, T ≤105 °C and the WAITSTATE option bit is set.
A
Subject to general operating conditions for V and T .
DD
A
Table 20. Total current consumption with code execution in run mode at V = 5 V
DD
Symbol Parameter
Conditions
HSE crystal osc. (24 MHz)
Typ
Max
Unit
4.4
3.7
3.3
2.7
2.5
1.2
1.0
fCPU = fMASTER = 24 MHz,
TA ≤ 105 °C
HSE user ext. clock (24 MHz)
HSE crystal osc. (16 MHz)
HSE user ext. clock (16 MHz)
HSI RC osc. (16 MHz)
7.3(1)
Supply
fCPU = fMASTER = 16 MHz
5.8
3.4
current in
run mode,
code
executed
from RAM
HSE user ext. clock (16 MHz)
HSI RC osc. (16 MHz)
4.1(1)
1.3(1)
fCPU = fMASTER/128 = 125 kHz
fCPU = fMASTER/128 = 15.625
kHz
HSI RC osc. (16 MHz/8)
0.55
f
CPU = fMASTER = 128 kHz
LSI RC osc. (128 kHz)
0.45
11.4
IDD(RUN)
mA
HSE crystal osc. (24 MHz)
fCPU = fMASTER = 24 MHz,
HSE user ext. clock (24 MHz) 10.8
18(1)
TA ≤ 105 °C
HSE crystal osc. (16 MHz)
HSE user ext. clock (16 MHz)
HSI RC osc.(16 MHz)
9.0
Supply
fCPU = fMASTER = 16 MHz
8.2 15.2(1)
8.1 13.2(1)
1.5
current in
run mode,
code
executed
from Flash
fCPU = fMASTER = 2 MHz.
HSI RC osc. (16 MHz/8)(2)
fCPU = fMASTER/128 = 125 kHz
HSI RC osc. (16 MHz)
1.1
fCPU = fMASTER/128 = 15.625
kHz
HSI RC osc. (16 MHz/8)
LSI RC osc. (128 kHz)
0.6
fCPU = fMASTER = 128 kHz
0.55
1. Data based on characterization results, not tested in production.
2. Default clock configuration measured with all peripherals off.
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STM8S207xx, STM8S208xx
Electrical characteristics
Table 21. Total current consumption with code execution in run mode at V = 3.3 V
DD
Symbol Parameter
Conditions
HSE crystal osc. (24 MHz)
Typ Max(1) Unit
4.0
fCPU = fMASTER = 24 MHz,
TA ≤ 105 °C
HSE user ext. clock (24 MHz)
HSE crystal osc. (16 MHz)
HSE user ext. clock (16 MHz)
HSI RC osc. (16 MHz)
3.7
2.9
2.7
2.5
1.2
1.0
7.3
Supply
fCPU = fMASTER = 16 MHz
5.8
3.4
4.1
1.3
current in
run mode,
code
executed
from RAM
HSE user ext. clock (16 MHz)
HSI RC osc. (16 MHz)
f
CPU = fMASTER/128 = 125 kHz
CPU = fMASTER/128 = 15.625
f
HSI RC osc. (16MHz/8)
0.55
kHz
fCPU = fMASTER = 128 kHz
LSI RC osc. (128 kHz)
0.45
11.0
IDD(RUN)
mA
HSE crystal osc. (24 MHz)
fCPU = fMASTER = 24 MHz,
TA ≤ 105 °C
HSE user ext. clock (24 MHz) 10.8
18.0
HSE crystal osc. (16 MHz)
HSE user ext. clock (16 MHz)
HSI RC osc. (16 MHz)
8.4
8.2
8.1
1.5
1.1
Supply
fCPU = fMASTER = 16 MHz
15.2
13.2
current in
run mode,
code
executed
from Flash
fCPU = fMASTER = 2 MHz.
HSI RC osc. (16 MHz/8)(2)
fCPU = fMASTER/128 = 125 kHz
HSI RC osc. (16 MHz)
fCPU = fMASTER/128 = 15.625
kHz
HSI RC osc. (16 MHz/8)
LSI RC osc. (128 kHz)
0.6
fCPU = fMASTER = 128 kHz
0.55
1. Data based on characterization results, not tested in production.
2. Default clock configuration.
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Electrical characteristics
STM8S207xx, STM8S208xx
Total current consumption in wait mode
Table 22. Total current consumption in wait mode at V = 5 V
DD
Symbol Parameter
Conditions
HSE crystal osc. (24 MHz)
HSE user ext. clock (24 MHz)
Typ Max(1) Unit
2.4
1.8
2.0
1.4
1.2
1.0
fCPU = fMASTER = 24 MHz,
TA ≤ 105 °C
4.7
HSE crystal osc. (16 MHz)
HSE user ext. clock (16 MHz)
HSI RC osc. (16 MHz)
fCPU = fMASTER = 16 MHz
4.4
1.6
Supply
IDD(WFI) current in
wait mode
mA
f
CPU = fMASTER/128 = 125 kHz
HSI RC osc. (16 MHz)
fCPU = fMASTER/128 = 15.625
kHz
HSI RC osc. (16 MHz/8)(2)
LSI RC osc. (128 kHz)
0.55
0.5
fCPU = fMASTER = 128 kHz
1. Data based on characterization results, not tested in production.
2. Default clock configuration measured with all peripherals off.
Table 23. Total current consumption in wait mode at V = 3.3 V
DD
Symbol Parameter
Conditions
HSE crystal osc. (24 MHz)
Typ Max(1) Unit
2.0
fCPU = fMASTER = 24 MHz,
TA ≤ 105 °C
HSE user ext. clock (24 MHz)
HSE crystal osc. (16 MHz)
HSE user ext. clock (16 MHz)
HSI RC osc. (16 MHz)
1.8
1.6
1.4
1.2
1.0
4.7
fCPU = fMASTER = 16 MHz
4.4
1.6
Supply
IDD(WFI) current in
wait mode
mA
fCPU = fMASTER/128 = 125 kHz
HSI RC osc. (16 MHz)
fCPU = fMASTER/128 = 15.625
kHz
HSI RC osc. (16 MHz/8)(2)
0.55
0.5
fCPU = fMASTER/128 = 15.625
kHz
LSI RC osc. (128 kHz)
1. Data based on characterization results, not tested in production.
2. Default clock configuration measured with all peripherals off.
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STM8S207xx, STM8S208xx
Electrical characteristics
Total current consumption in active halt mode
Table 24. Total current consumption in active halt mode at V = 5 V, T -40 to 85° C
DD
A
Conditions
Max(1) Unit
Mainvoltage
regulator
(MVR)(2)
Symbol
Parameter
Typ
Flash mode(3)
Clock source
HSE crystal oscillator
(16 MHz)
1000
200
940
140
Operating mode
LSI RC oscillator
(128 kHz)
260
On
HSE crystal oscillator
(16 MHz)
Supply current in
active halt mode
IDD(AH)
µA
Powerdown mode
LSI RC oscillator
(128 kHz)
Operating mode
68
11
LSI RC oscillator
128 kHz)
Off
Powerdown mode
45
1. Data based on characterization results, not tested in production.
2. Configured by the REGAH bit in the CLK_ICKR register.
3. Configured by the AHALT bit in the FLASH_CR1 register.
Table 25. Total current consumption in active halt mode at V = 3.3 V
DD
Conditions
Typ(1) Unit
Main voltage
Symbol
Parameter
regulator
Flash mode(3)
Clock source
(MVR)(2)
HSE crystal osc. (16 MHz)
LSI RC osc. (128 kHz)
HSE crystal osc. (16 MHz)
LSI RC osc. (128 kHz)
600
200
Operating mode
On
Off
540
µA
140
Supply current in
active halt mode
IDD(AH)
Powerdown mode
Operating mode
66
9
LSI RC osc. (128 kHz)
Powerdown mode
1. Data based on characterization results, not tested in production.
2. Configured by the REGAH bit in the CLK_ICKR register.
3. Configured by the AHALT bit in the FLASH_CR1 register.
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Electrical characteristics
STM8S207xx, STM8S208xx
Total current consumption in halt mode
Table 26. Total current consumption in halt mode at V = 5 V, T -40 to 85° C
DD
A
Symbol
Parameter
Conditions
Typ
Max
Unit
Flash in operating mode, HSI
clock after wakeup
63.5
IDD(H)
Supply current in halt mode
µA
Flash in powerdown mode, HSI
clock after wakeup
6.5
35
Table 27. Total current consumption in halt mode at V = 3.3 V
DD
Symbol
Parameter
Conditions
Typ
Unit
Flash in operating mode, HSI clock after
wakeup
61.5
IDD(H)
Supply current in halt mode
µA
Flash in powerdown mode, HSI clock after
wakeup
4.5
Low power mode wakeup times
Table 28. Wakeup times
Symbol
Parameter
Conditions
Typ
Max(1) Unit
See
note(2)
Wakeup time from wait
mode to run mode(3)
tWU(WFI)
f
CPU = fMASTER = 16 MHz.
0.56
1(6)
Flash in operating
mode(5)
2(6)
MVR voltage
regulator on(4)
Flash in
powerdown
3(6)
48(6)
50(6)
mode(5)
Wakeup time active halt
mode to run mode.(3)
HSI (after
wakeup)
µs
tWU(AH)
Flash in operating
mode(5)
MVR voltage
regulator off(4)
Flash in
powerdown
mode(5)
Flash in operating mode(5)
Flash in powerdown mode(5)
52
54
Wakeup time from halt
mode to run mode(3)
tWU(H)
1. Data guaranteed by design, not tested in production.
2. tWU(WFI) = 2 x 1/fmaster + 7 x 1/fCPU
3. Measured from interrupt event to interrupt vector fetch.
4. Configured by the REGAH bit in the CLK_ICKR register.
5. Configured by the AHALT bit in the FLASH_CR1 register.
6. Plus 1 LSI clock depending on synchronization.
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Doc ID 14733 Rev 9
STM8S207xx, STM8S208xx
Electrical characteristics
Total current consumption and timing in forced reset state
Table 29. Total current consumption and timing in forced reset state
Symbol
Parameter
Conditions
DD = 5 V
VDD = 3.3 V
Typ
Max(1)
Unit
V
1.6
0.8
IDD(R)
Supply current in reset state
mA
Reset release to bootloader vector
fetch
tRESETBL
150
µs
1. Data guaranteed by design, not tested in production.
Current consumption of on-chip peripherals
Subject to general operating conditions for V and T .
DD
A
HSI internal RC/f
= f
= 16 MHz.
CPU
MASTER
Table 30. Peripheral current consumption
Symbol
Parameter
TIM1 supply current (1)
Typ.
Unit
IDD(TIM1)
IDD(TIM2)
IDD(TIM3)
IDD(TIM4)
IDD(UART1)
IDD(UART3)
IDD(SPI)
220
120
100
25
TIM2 supply current (1)
TIM3 timer supply current (1)
TIM4 timer supply current (1)
UART1 supply current (2)
UART3 supply current (2)
SPI supply current (2)
90
µA
110
40
I2C supply current (2)
50
2
IDD(I C)
IDD(CAN)
beCAN supply current (2)
ADC2 supply current when converting (3)
210
1000
IDD(ADC2)
1. Data based on a differential IDD measurement between reset configuration and timer counter running at
16 MHz. No IC/OC programmed (no I/O pads toggling). Not tested in production.
2. Data based on a differential IDD measurement between the on-chip peripheral when kept under reset and
not clocked and the on-chip peripheral when clocked and not kept under reset. No I/O pads toggling. Not
tested in production.
3. Data based on a differential IDD measurement between reset configuration and continuous A/D
conversions. Not tested in production.
Doc ID 14733 Rev 9
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Electrical characteristics
STM8S207xx, STM8S208xx
Current consumption curves
Figure 14 and Figure 15 show typical current consumption measured with code executing in
RAM.
Figure 14. Typ. I
vs V , HSI RC osc, f
= 16 MHz
DD(RUN)
DD
CPU
-40˚C
25˚C
85˚C
125˚C
4
3.5
3
2.5
2
1.5
1
0.5
0
2.5
3
3.5
4
4.5
DD [V]
5
5.5
6
V
Figure 15. Typ. I
vs V , HSI RC osc, f
= 16 MHz
CPU
DD(WFI)
DD
-40˚C
25˚C
85˚C
125˚C
2.5
2
1.5
1
0.5
0
2.5
3
3.5
4
4.5
5
5.5
6
V
DD [V]
64/103
Doc ID 14733 Rev 9
STM8S207xx, STM8S208xx
Electrical characteristics
10.3.3
External clock sources and timing characteristics
HSE user external clock
Subject to general operating conditions for V and T .
DD
A
Table 31. HSE user external clock characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
User external clock source
frequency
fHSE_ext
0
24
MHz
OSCIN input pin high level
voltage
(1)
VHSEH
0.7 x VDD
VSS
VDD + 0.3 V
0.3 x VDD
1
V
OSCIN input pin low level
voltage
(1)
VHSEL
OSCIN input leakage
current
ILEAK_HSE
VSS < VIN < VDD
-1
µA
1. Data based on characterization results, not tested in production.
Figure 16. HSE external clock source
V
V
HSEH
HSEL
f
HSE
External clock
source
OSCIN
STM8
HSE crystal/ceramic resonator oscillator
The HSE clock can be supplied with a 1 to 24 MHz crystal/ceramic resonator oscillator. All
the information given in this paragraph is based on characterization results with specified
typical external components. In the application, the resonator and the load capacitors have
to be placed as close as possible to the oscillator pins in order to minimize output distortion
and start-up stabilization time. Refer to the crystal resonator manufacturer for more details
(frequency, package, accuracy...).
Doc ID 14733 Rev 9
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Electrical characteristics
STM8S207xx, STM8S208xx
Table 32. HSE oscillator characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
External high speed oscillator
frequency
fHSE
1
24
MHz
RF
Feedback resistor
220
kΩ
C(1)
Recommended load capacitance (2)
20
pF
C = 20 pF,
OSC = 24 MHz
6 (startup)
f
2 (stabilized)(3)
IDD(HSE) HSE oscillator power consumption
mA
C = 10 pF,
6 (startup)
fOSC = 24 MHz
1.5 (stabilized)(3)
gm
Oscillator transconductance
Startup time
5
mA/V
ms
(4)
tSU(HSE)
VDD is stabilized
1
1. C is approximately equivalent to 2 x crystal Cload.
2. The oscillator selection can be optimized in terms of supply current using a high quality resonator with small Rm value.
Refer to crystal manufacturer for more details
3. Data based on characterization results, not tested in production.
4. tSU(HSE) is the start-up time measured from the moment it is enabled (by software) to a stabilized 24 MHz oscillation is
reached. This value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer.
Figure 17. HSE oscillator circuit diagram
f
to core
HSE
R
m
R
F
C
O
L
m
C
L1
OSCIN
C
m
g
m
Resonator
Consumption
control
Resonator
STM8
OSCOUT
C
L2
HSE oscillator critical g formula
m
gmcrit = (2 × Π × fHSE)2 × Rm(2Co + C)2
R : Notional resistance (see crystal specification)
m
L : Notional inductance (see crystal specification)
m
C : Notional capacitance (see crystal specification)
m
Co: Shunt capacitance (see crystal specification)
C =C =C: Grounded external capacitance
L1
L2
g >> g
m
mcrit
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Doc ID 14733 Rev 9
STM8S207xx, STM8S208xx
Electrical characteristics
10.3.4
Internal clock sources and timing characteristics
Subject to general operating conditions for V and T . f
HSE
DD
A
High speed internal RC oscillator (HSI)
Table 33. HSI oscillator characteristics
Symbol
Parameter
Frequency
Conditions
Min
Typ
Max
Unit
fHSI
16
MHz
Trimmed by the
CLK_HSITRIMR register
for given VDD and TA
conditions
Accuracy of HSI oscillator
-1(1)
1(1)
VDD = 5 V, TA = 25 °C
-1.5
-2.2
1.5
2.2
ACCHSI
VDD = 5 V,
25 °C ≤ TA ≤ 85 °C
%
Accuracy of HSI oscillator
(factory calibrated)
2.95 V ≤ VDD ≤ 5.5 V,
-40 °C ≤ TA ≤ 125 °C
-3(2)
3(2)
1(1)
HSI oscillator wakeup
time including calibration
tsu(HSI)
µs
HSI oscillator power
consumption
IDD(HSI)
170
250(2)
µA
1. Guaranteeed by design, not tested in production.
2. Data based on characterization results, not tested in production
Figure 18. Typical HSI frequency variation vs V at 4 temperatures
DD
-40˚C
25˚C
85˚C
125˚C
3%
2%
1%
0%
-1%
-2%
-3%
2.5
3
3.5
4
4.5
(V)
5
5.5
6
V
DD
ai15067
Doc ID 14733 Rev 9
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Electrical characteristics
STM8S207xx, STM8S208xx
Low speed internal RC oscillator (LSI)
Subject to general operating conditions for V and T .
DD
A
Table 34. LSI oscillator characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
fLSI
Frequency
110
128
146
7(1)
kHz
µs
tsu(LSI) LSI oscillator wakeup time
IDD(LSI) LSI oscillator power consumption
1. Guaranteeed by design, not tested in production.
5
µA
Figure 19. Typical LSI frequency variation vs V @ 25 °C
DD
3%
2%
1%
0%
-1%
-2%
-3%
2.5
3
3.5
4
4.5
5
5.5
6
VDD [V]
ai15070
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Doc ID 14733 Rev 9
STM8S207xx, STM8S208xx
Electrical characteristics
10.3.5
Memory characteristics
RAM and hardware registers
Table 35. RAM and hardware registers
Symbol
Parameter
Conditions
Min
Unit
(2)
VRM
Data retention mode(1)
Halt mode (or reset)
VIT-max
V
1. Minimum supply voltage without losing data stored in RAM (in halt mode or under reset) or in hardware
registers (only in halt mode). Guaranteed by design, not tested in production.
2. Refer to Table 19 on page 57 for the value of VIT-max
.
Flash program memory/data EEPROM memory
General conditions: T = -40 to 125 °C.
A
Table 36. Flash program memory/data EEPROM memory
Symbol
Parameter
Conditions
Min(1) Typ Max
Unit
Operating voltage
(all modes, execution/write/erase)
VDD
fCPU ≤ 24 MHz
2.95
5.5
6.6
V
Standard programming time
(including erase) for byte/word/block
(1 byte/4 bytes/128 bytes)
6
ms
tprog
Fast programming time for 1 block
(128 bytes)
3
3
3.3
3.3
ms
ms
Erase time for 1 block (128 bytes)
terase
Erase/write cycles(2)
(program memory)
TA = 85 °C
10 k
NRW
cycles
Erase/write cycles (data memory)(2)
TA = 125 ° C
300 k 1M
20
Data retention (program memory)
after 10 k erase/write cycles at
TA = 85 °C
TRET = 55° C
TRET = 55° C
Data retention (data memory) after 10
k erase/write cycles at TA = 85 °C
tRET
20
1
years
mA
Data retention (data memory) after
300k erase/write cycles at
TA = 125 °C
T
RET = 85° C
Supply current (Flash programming or
erasing for 1 to 128 bytes)
IDD
2
1. Data based on characterization results, not tested in production.
2. The physical granularity of the memory is 4 bytes, so cycling is performed on 4 bytes even when a
write/erase operation addresses a single byte.
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Electrical characteristics
STM8S207xx, STM8S208xx
10.3.6
I/O port pin characteristics
General characteristics
Subject to general operating conditions for V and T unless otherwise specified. All
DD
A
unused pins must be kept at a fixed voltage: using the output mode of the I/O for example or
an external pull-up or pull-down resistor.
Table 37. I/O static characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Input low level
voltage
VIL
-0.3
0.3 x VDD
V
Input high level
voltage
VDD = 5 V
VIH
0.7 x VDD
VDD + 0.3 V
V
Vhys
Rpu
Hysteresis(1)
700
45
mV
Pull-up resistor
VDD = 5 V, VIN = VSS
30
60
kΩ
Fast I/Os
Load = 50 pF
20 (2)
ns
ns
Rise and fall time
(10% - 90%)
tR, tF
Standard and high sink I/Os
Load = 50 pF
125 (2)
Input leakage
current,
analog and digital
Ilkg
VSS ≤ VIN ≤ VDD
1
µA
Analog input
leakage current
Ilkg ana
Ilkg(inj)
VSS ≤ VIN ≤ VDD
250 (2)
1(2)
nA
µA
Leakage current in
adjacent I/O(2)
Injection current 4 mA
1. Hysteresis voltage between Schmitt trigger switching levels. Based on characterization results, not tested in production.
2. Data based on characterization results, not tested in production.
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Doc ID 14733 Rev 9
STM8S207xx, STM8S208xx
Electrical characteristics
Figure 20. Typical V and V vs V @ 4 temperatures
IL
IH
DD
-40˚C
25˚C
85˚C
125˚C
6
5
4
3
2
1
0
2.5
3
3.5
4
4.5
5
5.5
6
V
DD [V]
Figure 21. Typical pull-up resistance vs V @ 4 temperatures
DD
-40˚C
25˚C
85˚C
125˚C
60
55
50
45
40
35
30
2.5
3
3.5
4
4.5
5
5.5
6
VDD [V]
Figure 22. Typical pull-up current vs V @ 4 temperatures
DD
140
120
100
80
-40˚C
60
25˚C
85˚C
125˚C
40
20
0
0
1
2
3
4
5
6
VDD [V]
ai15068
1. The pull-up is a pure resistor (slope goes through 0).
Doc ID 14733 Rev 9
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Electrical characteristics
STM8S207xx, STM8S208xx
Table 38. Output driving current (standard ports)
Symbol
Parameter
Conditions
Min
Max
Unit
Output low level with 8 pins sunk
Output low level with 4 pins sunk
IIO = 10 mA, VDD = 5 V
IIO = 4 mA, VDD = 3.3 V
2
VOL
V
1(1)
Output high level with 8 pins sourced IIO = 10 mA, VDD = 5 V
Output high level with 4 pins sourced IIO = 4 mA, VDD = 3.3 V
2.8
VOH
V
2.1(1)
1. Data based on characterization results, not tested in production
Table 39. Output driving current (true open drain ports)
Symbol
Parameter
Conditions
Max
Unit
I
IO = 10 mA, VDD = 5 V
1
VOL
Output low level with 2 pins sunk
IIO = 10 mA, VDD = 3.3 V
IIO = 20 mA, VDD = 5 V
1.5(1)
2(1)
V
1. Data based on characterization results, not tested in production
Table 40. Output driving current (high sink ports)
Symbol
Parameter
Conditions
Min
Max
Unit
Output low level with 8 pins sunk
Output low level with 4 pins sunk
Output low level with 4 pins sunk
Output high level with 8 pins sourced
Output high level with 4 pins sourced
Output high level with 4 pins sourced
IIO = 10 mA,VDD = 5 V
IIO = 10 mA,VDD = 3.3 V
IIO = 20 mA,VDD = 5 V
IIO = 10 mA, VDD = 5 V
IIO = 10 mA, VDD = 3.3 V
IIO = 20 mA, VDD = 5 V
0.8
1(1)
VOL
1.5(1)
V
4.0
VOH
2.1(1)
3.3(1)
1. Data based on characterization results, not tested in production
72/103
Doc ID 14733 Rev 9
STM8S207xx, STM8S208xx
Electrical characteristics
Typical output level curves
Figure 24 to Figure 31 show typical output level curves measured with output on a single
pin.
Figure 23. Typ. V @ V = 5 V (standard ports)
OL
DD
-40˚C
25˚C
85˚C
125˚C
1.5
1.25
1
0.75
0.5
0.25
0
0
2
4
6
8
10
12
I
OL [mA]
Figure 24. Typ. V @ V = 3.3 V (standard ports)
OL
DD
-40˚C
25˚C
85˚C
125˚C
1.5
1.25
1
0.75
0.5
0.25
0
VOL [V]
0
1
2
3
4
5
6
7
I
OL [mA]
Figure 25. Typ. V @ V = 5 V (true open drain ports)
OL
DD
-40˚C
25˚C
85˚C
125˚C
2
1.75
1.5
1.25
1
0.75
0.5
0.25
0
0
5
10
15
20
25
I
OL [mA]
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Electrical characteristics
STM8S207xx, STM8S208xx
Figure 26. Typ. V @ V = 3.3 V (true open drain ports)
OL
DD
-40˚C
25˚C
85˚C
125˚C
2
1.75
1.5
1.25
1
0.75
0.5
0.25
0
0
2
4
6
8
10
12
14
V
OL [V]
Figure 27. Typ. V @ V = 5 V (high sink ports)
OL
DD
-40˚C
25˚C
85˚C
125˚C
1.5
1.25
1
0.75
0.5
0.25
0
0
5
10
15
20
25
I
OL [mA]
Figure 28. Typ. V @ V = 3.3 V (high sink ports)
OL
DD
-40˚C
25˚C
85˚C
125˚C
1.5
1.25
1
0.75
0.5
0.25
0
0
2
4
6
8
10
12
14
I
OL [mA]
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STM8S207xx, STM8S208xx
Figure 29. Typ. V
Electrical characteristics
V
@ V = 5 V (standard ports)
DD - OH
DD
-40˚C
2
25˚C
1.75
1.5
85˚C
125˚C
1.25
1
0.75
0.5
0.25
0
0
2
4
6
8
10
12
IOL [mA]
Figure 30. Typ. V
V
@ V = 3.3 V (standard ports)
DD - OH
DD
-40˚C
2
25˚C
1.75
1.5
85˚C
125˚C
1.25
1
0.75
0.5
0.25
0
0
1
2
3
4
5
6
7
IOL [mA]
Figure 31. Typ. V
V
@ V = 5 V (high sink ports)
DD - OH
DD
-40˚C
2
25˚C
1.75
1.5
85˚C
125˚C
1.25
1
0.75
0.5
0.25
0
0
5
10
15
20
25
IOL [mA]
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Electrical characteristics
Figure 32. Typ. V
STM8S207xx, STM8S208xx
V
@ V = 3.3 V (high sink ports)
DD - OH
DD
-40˚C
2
25˚C
1.75
1.5
85˚C
125˚C
1.25
1
0.75
0.5
0.25
0
0
2
4
6
8
10
12
14
IOL [mA]
10.3.7
Reset pin characteristics
Subject to general operating conditions for V and T unless otherwise specified.
DD
A
Table 41. NRST pin characteristics
Symbol
Parameter
Conditions
Min
Typ 1)
Max
Unit
VIL(NRST)
VIH(NRST)
VOL(NRST)
RPU(NRST)
tIFP(NRST)
NRST Input low level voltage (1)
NRST Input high level voltage (1)
-0.3 V
0.3 x VDD
VDD + 0.3
0.5
0.7 x VDD
V
NRST Output low level voltage (1)
NRST Pull-up resistor (2)
IOL= 2 mA
30
40
60
kΩ
ns
ns
µs
NRST Input filtered pulse (3)
75
tINFP(NRST) NRST Input not filtered pulse (3)
tOP(NRST)
NRST output pulse (1)
500
15
1. Data based on characterization results, not tested in production.
2. The RPU pull-up equivalent resistor is based on a resistive transistor
3. Data guaranteed by design, not tested in production.
Figure 33. Typical NRST V and V vs V @ 4 temperatures
IL
IH
DD
-40˚C
25˚C
85˚C
125˚C
6
5
4
3
2
1
0
2.5
3
3.5
4
4.5
DD [V]
5
5.5
6
V
76/103
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STM8S207xx, STM8S208xx
Electrical characteristics
Figure 34. Typical NRST pull-up resistance vs V @ 4 temperatures
DD
-40˚C
25˚C
85˚C
125˚C
60
55
50
45
40
35
30
2.5
3
3.5
4
4.5
DD [V]
5
5.5
6
V
Figure 35. Typical NRST pull-up current I vs V @ 4 temperatures
pu
DD
140
120
100
80
60
-40˚C
25˚C
85˚C
125˚C
40
20
0
0
1
2
3
4
5
6
VDD [V]
ai15069
The reset network shown in Figure 36 protects the device against parasitic resets. The user
must ensure that the level on the NRST pin can go below the V max. level specified in
IL
Table 37. Otherwise the reset is not taken into account internally.
Figure 36. Recommended reset pin protection
STM8
V
DD
RPU
External
reset
circuit
NRST
Internal reset
Filter
0.01µF
(optional)
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Electrical characteristics
STM8S207xx, STM8S208xx
SPI serial peripheral interface
10.3.8
Unless otherwise specified, the parameters given in Table 42 are derived from tests
performed under ambient temperature, f frequency and V supply voltage
MASTER
DD
conditions. t
= 1/f
.
MASTER
MASTER
Refer to I/O port characteristics for more details on the input/output alternate function
characteristics (NSS, SCK, MOSI, MISO).
Table 42. SPI characteristics
Symbol
Parameter
Conditions
Master mode
Slave mode
Min
Max
Unit
0
0
10
6
fSCK
1/tc(SCK)
SPI clock frequency
MHz
tr(SCK)
tf(SCK)
SPI clock rise and fall time Capacitive load: C = 30 pF
25
(1)
tsu(NSS)
NSS setup time
NSS hold time
Slave mode
Slave mode
4 x tMASTER
70
(1)
th(NSS)
(1)
tw(SCKH)
tw(SCKL)
SCK high and low time
Data input setup time
Master mode
tSCK/2 - 15
tSCK/2 + 15
(1)
(1)
Master mode
5
5
tsu(MI)
tsu(SI)
(1)
Slave mode
ns
(1)
Master mode
7
th(MI)
th(SI)
Data input hold time
(1)
Slave mode
10
(1)(2)
(1)(3)
ta(SO)
Data output access time
Data output disable time
Data output valid time
Data output valid time
Slave mode
3 x tMASTER
tdis(SO)
tv(SO)
tv(MO)
th(SO)
Slave mode
25
(1)
(1)
(1)
(1)
Slave mode (after enable edge)
Master mode (after enable edge)
Slave mode (after enable edge)
Master mode (after enable edge)
75
30
31
12
Data output hold time
th(MO)
1. Values based on design simulation and/or characterization results, and not tested in production.
2. Min time is for the minimum time to drive the output and the max time is for the maximum time to validate the data.
3. Min time is for the minimum time to invalidate the output and the max time is for the maximum time to put the data in Hi-Z.
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STM8S207xx, STM8S208xx
Electrical characteristics
Figure 37. SPI timing diagram - slave mode and CPHA = 0
NSS input
t
t
t
SU(NSS)
c(SCK)
h(NSS)
CPHA=0
CPOL=0
t
t
w(SCKH)
w(SCKL)
CPHA=0
CPOL=1
t
t
t
t
t
dis(SO)
v(SO)
r(SCK)
f(SCK)
h(SO)
t
a(SO)
MISO
OUT PUT
MSB O UT
BI T6 OUT
BIT1 IN
LSB OUT
t
su(SI)
MOSI
M SB IN
LSB IN
INPUT
t
h(SI)
ai14134
(1)
Figure 38. SPI timing diagram - slave mode and CPHA = 1
NSS input
t
t
t
SU(NSS)
t
c(SCK)
h(NSS)
CPHA=1
CPOL=0
w(SCKH)
CPHA=1
CPOL=1
t
w(SCKL)
t
t
r(SCK)
f(SCK)
t
t
t
v(SO)
h(SO)
dis(SO)
t
a(SO)
MISO
OUT PUT
MSB O UT
BI T6 OUT
LSB OUT
t
t
su(SI)
h(SI)
MOSI
M SB IN
BIT1 IN
LSB IN
INPUT
ai14135
1. Measurement points are done at CMOS levels: 0.3 VDD and 0.7 VDD.
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Electrical characteristics
STM8S207xx, STM8S208xx
(1)
Figure 39. SPI timing diagram - master mode
High
NSS input
t
c(SCK)
CPHA=0
CPOL=0
CPHA=0
CPOL=1
CPHA=1
CPOL=0
CPHA=1
CPOL=1
t
t
t
t
w(SCKH)
w(SCKL)
r(SCK)
f(SCK)
t
su(MI)
MISO
INPUT
MSBIN
BIT6 IN
LSB IN
t
h(MI)
MOSI
M SB OUT
BIT1 OUT
LSB OUT
OUTUT
t
t
v(MO)
h(MO)
ai14136
1. Measurement points are done at CMOS levels: 0.3 VDD and 0.7 VDD.
80/103
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STM8S207xx, STM8S208xx
2
Electrical characteristics
10.3.9
I C interface characteristics
2
Table 43. I C characteristics
Standard mode I2C Fast mode I2C(1)
Symbol Parameter
Unit
Min(2)
Max(2)
Min(2) Max(2)
tw(SCLL) SCL clock low time
tw(SCLH) SCL clock high time
tsu(SDA) SDA setup time
4.7
4.0
1.3
0.6
µs
250
0(3)
100
th(SDA)
SDA data hold time
0(4)
900(3)
300
tr(SDA)
tr(SCL)
ns
SDA and SCL rise time
1000
300
tf(SDA)
tf(SCL)
SDA and SCL fall time
300
th(STA)
START condition hold time
4.0
4.7
4.0
0.6
0.6
0.6
µs
tsu(STA) Repeated START condition setup time
tsu(STO) STOP condition setup time
µs
µs
pF
STOP to START condition time
tw(STO:STA)
(bus free)
4.7
1.3
Cb
Capacitive load for each bus line
400
400
1. fMASTER, must be at least 8 MHz to achieve max fast I2C speed (400kHz)
Data based on standard I2C protocol requirement, not tested in production
2.
The maximum hold time of the start condition has only to be met if the interface does not stretch the low
time
3.
4.
The device must internally provide a hold time of at least 300 ns for the SDA signal in order to bridge the
undefined region of the falling edge of SCL
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Electrical characteristics
Figure 40.
STM8S207xx, STM8S208xx
2
(1)
Typical application with I C bus and timing diagram
V
V
DD
DD
STM8S20xxx
SDA
I²C bus
SCL
START REPEATED
START
START
t
su(STA)
SDA
t
t
t
r(SDA)
f(SDA)
su(SDA)
t
su(STA:STO)
STOP
t
t
t
w(SCKL)
h(SDA)
h(STA)
SCL
t
t
t
su(STO)
r(SCK)
t
f(SCK)
w(SCKH)
ai15385
1. Measurement points are done at CMOS levels: 0.3 x VDD and 0.7 x VDD
82/103
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STM8S207xx, STM8S208xx
Electrical characteristics
10.3.10 10-bit ADC characteristics
Subject to general operating conditions for V
specified.
, f
, and T unless otherwise
DDA MASTER
A
Table 44. ADC characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
4
Unit
V
DDA = 3 to 5.5 V
1
fADC
ADC clock frequency
MHz
VDDA = 4.5 to 5.5 V
1
3
6
VDDA Analog supply
5.5
VDDA
V
V
VREF+ Positive reference voltage
VREF- Negative reference voltage
2.75(1)
VSSA
VSSA
0.5(1)
VDDA
V
V
VAIN
Conversion voltage range(2)
Devices with external
REF+/VREF- pins
VREF-
VREF+
V
V
Internal sample and hold
capacitor
CADC
3
pF
f
ADC = 4 MHz
0.75
0.5
7
(2)
tS
Sampling time
µs
fADC = 6 MHz
tSTAB Wakeup time from standby
µs
µs
fADC = 4 MHz
3.5
2.33
14
Total conversion time (including
tCONV
fADC = 6 MHz
µs
sampling time, 10-bit resolution)
1/fADC
1. Data guaranteed by design, not tested in production..
2. During the sample time the input capacitance CAIN (3 pF max) can be charged/discharged by the external
source. The internal resistance of the analog source must allow the capacitance to reach its final voltage
level within tS. After the end of the sample time tS, changes of the analog input voltage have no effect on
the conversion result. Values for the sample clock tS depend on programming.
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Electrical characteristics
STM8S207xx, STM8S208xx
Table 45. ADC accuracy with R
< 10 kΩ , V
= 5 V
DDA
AIN
Symbol
Parameter
Conditions
Typ
Max(1)
Unit
fADC = 2 MHz.
fADC = 4 MHz.
fADC = 6 MHz.
fADC = 2 MHz.
fADC = 4 MHz.
fADC = 6 MHz.
fADC = 2 MHz.
fADC = 4 MHz.
fADC = 6 MHz.
fADC = 2 MHz.
fADC = 4 MHz.
1
2.5
3
|ET|
Total unadjusted error (2)
1.4
1.6
0.6
1.1
1.2
0.2
0.6
0.8
0.7
0.7
0.8
0.6
0.6
0.6
3.5
2
|EO|
|EG|
|ED|
|EL|
Offset error (2)
Gain error (2)
2.5
2.5
2
2.5
2.5
1.5
1.5
1.5
1.5
1.5
1.5
LSB
Differential linearity error (2)
Integral linearity error (2)
f
ADC = 6 MHz.
fADC = 2 MHz.
fADC = 4 MHz.
f
ADC = 6 MHz.
1. Data based on characterisation results for LQFP80 device with VREF+/VREF-, not tested in production.
2. ADC accuracy vs. negative injection current: Injecting negative current on any of the analog input pins
should be avoided as this significantly reduces the accuracy of the conversion being performed on another
analog input. It is recommended to add a Schottky diode (pin to ground) to standard analog pins which may
potentially inject negative current. Any positive injection current within the limits specified for IINJ(PIN) and
ΣIINJ(PIN) in Section 10.3.6 does not affect the ADC accuracy.
Table 46. ADC accuracy with R
< 10 kΩ R , V
= 3.3 V
DDA
AIN
AIN
Symbol
Parameter
Conditions
Typ
Max(1)
Unit
fADC = 2 MHz.
fADC = 4 MHz.
fADC = 2 MHz.
1.1
1.6
0.7
1.3
0.2
0.5
0.7
0.7
0.6
0.6
2
2.5
1.5
2
|ET|
Total unadjusted error(2)
|EO|
|EG|
|ED|
|EL|
Offset error(2)
Gain error(2)
f
ADC = 4 MHz.
fADC = 2 MHz.
fADC = 4 MHz.
fADC = 2 MHz.
fADC = 4 MHz.
fADC = 2 MHz.
1.5
2
LSB
1
Differential linearity error(2)
Integral linearity error(2)
1
1.5
1.5
f
ADC = 4 MHz.
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Doc ID 14733 Rev 9
STM8S207xx, STM8S208xx
Figure 41. ADC accuracy characteristics
Electrical characteristics
E
G
1023
1022
1021
V
– V
DDA
SSA
1LSB
= ----------------------------------------
IDEAL
1024
(2)
E
T
(3)
7
6
5
4
3
2
1
(1)
E
O
E
L
E
D
1 LSB
IDEAL
0
1
2
3
4
5
6
7
1021102210231024
V
V
DDA
SSA
1. Example of an actual transfer curve.
2. The ideal transfer curve
3. End point correlation line
ET = Total unadjusted error: maximum deviation between the actual and the ideal transfer curves.
E
E
E
O = Offset error: deviation between the first actual transition and the first ideal one.
G = Gain error: deviation between the last ideal transition and the last actual one.
D = Differential linearity error: maximum deviation between actual steps and the ideal one.
EL = Integral linearity error: maximum deviation between any actual transition and the end point correlation
line.
Figure 42. Typical application with ADC
V
DD
STM8
V
T
0.6V
R
AIN
AINx
10-bit A/D
conversion
V
AIN
C
V
T
0.6V
AIN
I
C
ADC
L
1µA
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Electrical characteristics
STM8S207xx, STM8S208xx
10.3.11 EMC characteristics
Susceptibility tests are performed on a sample basis during product characterization.
Functional EMS (electromagnetic susceptibility)
While executing a simple application (toggling 2 LEDs through I/O ports), the product is
stressed by two electromagnetic events until a failure occurs (indicated by the LEDs).
●
ESD: Electrostatic discharge (positive and negative) is applied on all pins of the device
until a functional disturbance occurs. This test conforms with the IEC 61000-4-2
standard.
●
FTB: A burst of fast transient voltage (positive and negative) is applied to V and V
DD
SS
through a 100 pF capacitor, until a functional disturbance occurs. This test conforms
with the IEC 61000-4-4 standard.
A device reset allows normal operations to be resumed. The test results are given in the
table below based on the EMS levels and classes defined in application note AN1709.
Designing hardened software to avoid noise problems
EMC characterization and optimization are performed at component level with a typical
application environment and simplified MCU software. It should be noted that good EMC
performance is highly dependent on the user application and the software in particular.
Therefore it is recommended that the user applies EMC software optimization and
prequalification tests in relation with the EMC level requested for his application.
Software recommendations
The software flowchart must include the management of runaway conditions such as:
●
●
●
Corrupted program counter
Unexpected reset
Critical data corruption (control registers...)
Prequalification trials
Most of the common failures (unexpected reset and program counter corruption) can be
recovered by applying a low state on the NRST pin or the oscillator pins for 1 second.
To complete these trials, ESD stress can be applied directly on the device, over the range of
specification values. When unexpected behavior is detected, the software can be hardened
to prevent unrecoverable errors occurring (see application note AN1015).
Table 47. EMS data
Symbol
Parameter
Conditions
Level/class
VDD = 5 V, TA = 25 °C,
fMASTER = 16 MHz,
conforming to IEC 61000-4-2
Voltage limits to be applied on any I/O pin to
induce a functional disturbance
VFESD
2B
Fast transient voltage burst limits to be
VDD = 5 V, TA = 25 °C,
VEFTB applied through 100pF on VDD and VSS pins fMASTER = 16 MHz,
4A
to induce a functional disturbance
conforming to IEC 61000-4-4
86/103
Doc ID 14733 Rev 9
STM8S207xx, STM8S208xx
Electrical characteristics
Electromagnetic interference (EMI)
Emission tests conform to the SAE IEC 61967-2 standard for test software, board layout and
pin loading.
Table 48. EMI data
Conditions
(1)
Max fHSE/fCPU
Symbol
Parameter
Unit
Monitored
frequency band
General conditions
8 MHz/ 8 MHz/ 8 MHz/
8 MHz 16 MHz 24 MHz
0.1MHz to 30 MHz
30 MHz to 130 MHz
130 MHz to 1 GHz
15
18
-1
20
21
1
24
16
4
VDD = 5 V
Peak level
dBµV
TA = 25 °C
SEMI
LQFP80 package
conforming to SAE IEC
61967-2
SAE EMI
level
SAE EMI level
2
2.5
2.5
1. Data based on characterization results, not tested in production.
Absolute maximum ratings (electrical sensitivity)
Based on two different tests (ESD and LU) using specific measurement methods, the
product is stressed in order to determine its performance in terms of electrical sensitivity.
For more details, refer to the application note AN1181.
Electrostatic discharge (ESD)
Electrostatic discharges (3 positive then 3 negative pulses separated by 1 second) are
applied to the pins of each sample according to each pin combination. The sample size
depends on the number of supply pins in the device (3 parts*(n+1) supply pin). This test
conforms to the JESD22-A114A/A115A standard. For more details, refer to the application
note AN1181.
Table 49. ESD absolute maximum ratings
Maximum
Symbol
Ratings
Conditions
Class
Unit
value(1)
Electrostatic discharge voltage
(Human body model)
TA = 25°C, conforming to
VESD(HBM)
A
2000
V
V
JESD22-A114
Electrostatic discharge voltage
(Charge device model)
TA= 25°C, conforming to
JESD22-C101
VESD(CDM)
IV
1000
1. Data based on characterization results, not tested in production.
Doc ID 14733 Rev 9
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Electrical characteristics
Static latch-up
STM8S207xx, STM8S208xx
Two complementary static tests are required on 10 parts to assess the latch-up
performance:
●
A supply overvoltage (applied to each power supply pin)
●
A current injection (applied to each input, output and configurable I/O pin) is performed
on each sample.
This test conforms to the EIA/JESD 78 IC latch-up standard. For more details, refer to the
application note AN1181.
Table 50. Electrical sensitivities
Symbol
Parameter
Conditions
Class(1)
TA = 25 °C
TA = 85 °C
TA = 125 °C
A
A
A
LU
Static latch-up class
1. Class description: A Class is an STMicroelectronics internal specification. All its limits are higher than the
JEDEC specifications, that means when a device belongs to class A it exceeds the JEDEC standard. B
class strictly covers all the JEDEC criteria (international standard).
88/103
Doc ID 14733 Rev 9
STM8S207xx, STM8S208xx
Package characteristics
11
Package characteristics
To meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at www.st.com.
ECOPACK® is an ST trademark.
Doc ID 14733 Rev 9
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Package characteristics
STM8S207xx, STM8S208xx
11.1
Package mechanical data
11.1.1
LQFP package mechanical data
Figure 43. 80-pin low profile quad flat package (14 x 14)
D
ccc
C
D1
D3
A
A2
41
60
40
61
b
L1
E3 E1
E
L
A1
K
80
Pin 1
identification
1
c
1S_ME
Table 51. 80-pin low profile quad flat package mechanical data
mm
Typ
inches(1)
Symbol
Min
Max
Min
Typ
Max
A
A1
A2
b
1.600
0.150
1.450
0.380
0.200
16.200
14.200
0.0630
0.0059
0.0571
0.0150
0.0079
0.6378
0.5591
0.050
1.350
0.220
0.090
15.800
13.800
0.0020
0.0531
0.0087
0.0035
0.6220
0.5433
1.400
0.320
0.0551
0.0126
c
D
16.000
14.000
12.350
16.000
14.000
12.350
0.650
0.6299
0.5512
0.4862
0.6299
0.5512
0.4862
0.0256
0.0236
0.0394
3.5°
D1
D3
E
15.800
13.800
16.200
14.200
0.6220
0.5433
0.6378
0.5591
E1
E3
e
L
0.450
0.0°
0.600
0.750
0.0177
0.0°
0.0295
L1
k
1.000
3.5°
7.0°
7.0°
ccc
0.100
0.0039
1. Values in inches are converted from mm and rounded to four decimal places.
Doc ID 14733 Rev 9
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STM8S207xx, STM8S208xx
Figure 44. 64-pin low profile quad flat package (14 x 14)
Package characteristics
D
ccc
C
D1
D3
A
A2
33
48
32
49
b
L1
E3 E1
E
L
A1
K
64
17
Pin 1
identification
1
16
c
1R_ME
Table 52. 64-pin low profile quad flat package mechanical data (14 x 14)
mm
Typ
inches(1)
Symbol
Min
Max
Min
Typ
Max
A
A1
A2
b
1.600
0.150
1.450
0.450
0.200
16.200
14.200
0.0630
0.0059
0.0571
0.0177
0.0079
0.6378
0.5591
0.050
1.350
0.300
0.090
15.800
13.800
0.0020
0.0531
0.0118
0.0035
0.6220
0.5433
1.400
0.370
0.0551
0.0146
C
D
16.000
14.000
12.000
16.000
14.000
12.000
0.800
0.6299
0.5512
0.4724
0.6299
0.5512
0.4724
0.0315
0.0236
0.0394
3.5 °
D1
D3
E
15.800
13.800
16.200
14.200
0.6220
0.5433
0.6378
0.5591
E1
E3
e
L
0.450
0.0 °
0.600
0.750
0.0177
0.0 °
0.0295
L1
k
1.000
3.5 °
7.0 °
7.0 °
ccc
0.100
0.0039
1. Values in inches are converted from mm and rounded to four decimal places.
Doc ID 14733 Rev 9
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Package characteristics
Figure 45. 64-pin low profile quad flat package (10 x 10)
STM8S207xx, STM8S208xx
D
ccc
C
D1
D3
A
A2
33
48
32
49
b
L1
E3 E1
E
L
A1
K
64
17
Pin 1
identification
1
16
c
5W_ME
Table 53. 64-pin low profile quad flat package mechanical data (10 x 10)
mm
Typ
inches(1)
Symbol
Min
Max
Min
Typ
Max
A
A1
A2
b
1.600
0.150
1.450
0.270
0.200
0.0630
0.0059
0.0571
0.0106
0.0079
0.050
1.350
0.170
0.090
0.0020
0.0531
0.0067
0.0035
1.400
0.220
0.0551
0.0087
C
D
12.000
10.000
12.000
10.000
0.500
0.4724
0.3937
0.4724
0.3937
0.0197
3.5000°
0.0236
0.0394
D1
E
E1
e
K
0.000°
0.450
3.500°
0.600
7.000°
0.750
0.0000°
0.0177
7.0000°
0.0295
L
L1
1.000
1. Values in inches are converted from mm and rounded to four decimal places.
92/103
Doc ID 14733 Rev 9
STM8S207xx, STM8S208xx
Figure 46. 48-pin low profile quad flat package (7 x 7)
Package characteristics
D
ccc
C
D1
D3
A
A2
25
36
24
37
L1
b
E3
E1 E
48
L
13
A1
K
Pin 1
identification
1
12
c
5B_ME
Table 54. 48-pin low profile quad flat package mechanical data
mm
inches(1)
Symbol
Min
Typ
Max
Min
Typ
Max
A
A1
A2
b
1.600
0.150
1.450
0.270
0.200
9.200
7.200
0.0630
0.0059
0.0571
0.0106
0.0079
0.3622
0.2835
0.050
1.350
0.170
0.090
8.800
6.800
0.0020
0.0531
0.0067
0.0035
0.3465
0.2677
1.400
0.220
0.0551
0.0087
c
D
9.000
7.000
5.500
9.000
7.000
5.500
0.500
0.600
1.000
3.5°
0.3543
0.2756
0.2165
0.3543
0.2756
0.2165
0.0197
0.0236
0.0394
3.5°
D1
D3
E
8.800
6.800
9.200
7.200
0.3465
0.2677
0.3622
0.2835
E1
E3
e
L
0.450
0.0°
0.750
0.0177
0.0°
0.0295
L1
k
7.0°
7.0°
ccc
0.080
0.0031
1. Values in inches are converted from mm and rounded to four decimal places.
Doc ID 14733 Rev 9
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Package characteristics
Figure 47. 44-pin low profile quad flat package (10 x 10)
STM8S207xx, STM8S208xx
D
ccc
C
D1
D3
A
A2
23
33
22
34
L1
b
E3
E1 E
44
L
12
A1
K
Pin 1
identification
1
11
c
4Y_ME
Table 55. 44-pin low profile quad flat package mechanical data
mm
Typ
inches(1)
Symbol
Min
Max
Min
Typ
Max
A
A1
A2
b
1.600
0.150
1.450
0.450
0.200
12.200
10.200
0.0630
0.0059
0.0571
0.0177
0.0079
0.4803
0.4016
0.050
1.350
0.300
0.090
11.800
9.800
0.0020
0.0531
0.0118
0.0035
0.4646
0.3858
1.400
0.370
0.0551
0.0146
c
D
12.000
10.000
8.000
12.000
10.000
8.000
0.800
0.600
1.000
3.5°
0.4724
0.3937
0.3150
0.4724
0.3937
0.3150
0.0315
0.0236
0.0394
3.5°
D1
D3
E
11.800
9.800
12.200
10.200
0.4646
0.3858
0.4803
0.4016
E1
E3
e
L
0.450
0.0°
0.750
0.0177
0.0°
0.0295
L1
k
7.0°
7.0°
ccc
0.100
0.0039
1. Values in inches are converted from mm and rounded to four decimal places.
94/103
Doc ID 14733 Rev 9
STM8S207xx, STM8S208xx
Figure 48. 32-pin low profile quad flat package (7 x 7)
Package characteristics
ccc
C
D
D1
D3
A
A2
24
17
16
25
32
L1
b
E3
E1 E
9
L
Pin 1
identification
A1
K
1
8
c
Table 56. 32-pin low profile quad flat package mechanical data
mm
Typ
inches(1)
Symbol
Min
Max
Min
Typ
Max
A
A1
A2
b
1.600
0.150
1.450
0.450
0.200
9.200
7.200
0.0630
0.0059
0.0571
0.0177
0.0079
0.3622
0.2835
0.050
1.350
0.300
0.090
8.800
6.800
0.0020
0.0531
0.0118
0.0035
0.3465
0.2677
1.400
0.370
0.0551
0.0146
c
D
9.000
7.000
5.600
9.000
7.000
5.600
0.800
0.600
1.000
3.5°
0.3543
0.2756
0.2205
0.3543
0.2756
0.2205
0.0315
0.0236
0.0394
3.5°
D1
D3
E
8.800
6.800
9.200
7.200
0.3465
0.2677
0.3622
0.2835
E1
E3
e
L
0.450
0.0°
0.750
0.0177
0.0°
0.0295
L1
k
7.0°
7.0°
ccc
0.100
0.0039
1. Values in inches are converted from mm and rounded to four decimal places.
Doc ID 14733 Rev 9
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Package characteristics
STM8S207xx, STM8S208xx
11.2
Thermal characteristics
The maximum chip junction temperature (T
) must never exceed the values given in
Jmax
Table 18: General operating conditions on page 56.
The maximum chip-junction temperature, T
using the following equation:
, in degrees Celsius, may be calculated
Jmax
T
= T
+ (P
x Θ )
Jmax
Amax
Dmax JA
Where:
●
●
●
●
T
is the maximum ambient temperature in °C
is the package junction-to-ambient thermal resistance in ° C/W
Amax
Θ
JA
P
is the sum of P
and P
(P
= P
+ P
)
I/Omax
Dmax
INTmax
I/Omax
Dmax
INTmax
P
is the product of I and V , expressed in Watts. This is the maximum chip
INTmax
DD
DD
internal power.
●
P
P
represents the maximum power dissipation on output pins, where:
I/Omax
I/Omax
= Σ (V *I ) + Σ((V -V *I ), and taking account of the actual V /I and
OL OL
DD OH) OH
OL OL
V
/I of the I/Os at low and high level in the application.
OH OH
(1)
Table 57. Thermal characteristics
Symbol
Parameter
Value
Unit
Thermal resistance junction-ambient
LQFP 80 - 14 x 14 mm
Θ
38
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
JA
Thermal resistance junction-ambient
LQFP 64 - 14 x 14 mm
Θ
45
46
57
54
60
JA
Thermal resistance junction-ambient
LQFP 64 - 10 x 10 mm
Θ
JA
Thermal resistance junction-ambient
LQFP 48 - 7 x 7 mm
Θ
JA
Thermal resistance junction-ambient
LQFP 44 - 10 x 10 mm
Θ
JA
Thermal resistance junction-ambient
LQFP 32 - 7 x 7 mm
Θ
JA
1. Thermal resistances are based on JEDEC JESD51-2 with 4-layer PCB in a natural convection
environment.
11.2.1
Reference document
JESD51-2 integrated circuits thermal test method environment conditions - natural
convection (still air). Available from www.jedec.org.
96/103
Doc ID 14733 Rev 9
STM8S207xx, STM8S208xx
Package characteristics
11.2.2
Selecting the product temperature range
When ordering the microcontroller, the temperature range is specified in the order code (see
(1)
Figure 49: STM8S207xx/208xx performance line ordering information scheme on
page 100).
The following example shows how to calculate the temperature range needed for a given
application.
Assuming the following application conditions:
●
●
●
Maximum ambient temperature T
= 82 °C (measured according to JESD51-2)
Amax
I
= 15 mA, V = 5.5 V
DD
DDmax
Maximum eight standard I/Os used at the same time in output at low level with I = 10
OL
mA, V = 2 V
OL
●
●
Maximum four high sink I/Os used at the same time in output at low level with I = 20
OL
mA, V = 1.5 V
OL
Maximum two true open drain I/Os used at the same time in output at low level with
I
= 20 mA, V = 2 V
OL
OL
P
P
15 mA x 5.5 V = 82.5 mW
INTmax =
(10 mA x 2 V x 8 ) + (20 mA x 2 V x 2) + (20 mA x 1.5 V x 4) = 360 mW
IOmax =
This gives: P
= 82.5 mW and P
360 mW:
IOmax
INTmax
P
= 82.5 mW + 360 mW
Dmax
Thus: P
= 443 mW
Dmax
Using the values obtained in Table 57: Thermal characteristics on page 96 T
is
Jmax
calculated as follows for LQFP64 10 x 10 mm = 46 °C/W:
T
= 82 °C + (46 °C/W x 443 mW) = 82 °C + 20 °C = 102 °C
Jmax
This is within the range of the suffix 6 version parts (-40 < T < 105 °C).
J
In this case, parts must be ordered at least with the temperature range suffix 6.
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STM8 development tools
STM8S207xx, STM8S208xx
12
STM8 development tools
Development tools for the STM8 microcontrollers include the full-featured STice emulation
system supported by a complete software tool package including C compiler, assembler and
integrated development environment with high-level language debugger. In addition, the
STM8 is to be supported by a complete range of tools including starter kits, evaluation
boards and a low-cost in-circuit debugger/programmer.
12.1
Emulation and in-circuit debugging tools
The STice emulation system offers a complete range of emulation and in-circuit debugging
features on a platform that is designed for versatility and cost-effectiveness. In addition,
STM8 application development is supported by a low-cost in-circuit debugger/programmer.
The STice is the fourth generation of full featured emulators from STMicroelectronics. It
offers new advanced debugging capabilities including profiling and coverage to help detect
and eliminate bottlenecks in application execution and dead code when fine tuning an
application.
In addition, STice offers in-circuit debugging and programming of STM8 microcontrollers via
the STM8 single wire interface module (SWIM), which allows non-intrusive debugging of an
application while it runs on the target microcontroller.
For improved cost effectiveness, STice is based on a modular design that allows you to
order exactly what you need to meet your development requirements and to adapt your
emulation system to support existing and future ST microcontrollers.
STice key features
●
●
●
●
●
●
●
●
●
●
Occurrence and time profiling and code coverage (new features)
Advanced breakpoints with up to 4 levels of conditions
Data breakpoints
Program and data trace recording up to 128 KB records
Read/write on the fly of memory during emulation
In-circuit debugging/programming via SWIM protocol
8-bit probe analyzer
1 input and 2 output triggers
Power supply follower managing application voltages between 1.62 to 5.5 V
Modularity that allows you to specify the components you need to meet your
development requirements and adapt to future requirements
●
Supported by free software tools that include integrated development environment
(IDE), programming software interface and assembler for STM8.
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Doc ID 14733 Rev 9
STM8S207xx, STM8S208xx
STM8 development tools
12.2
Software tools
STM8 development tools are supported by a complete, free software package from
STMicroelectronics that includes ST Visual Develop (STVD) IDE and the ST Visual
Programmer (STVP) software interface. STVD provides seamless integration of the Cosmic
and Raisonance C compilers for STM8, which are available in a free version that outputs up
to 16 Kbytes of code.
12.2.1
STM8 toolset
STM8 toolset with STVD integrated development environment and STVP programming
software is available for free download at www.st.com/mcu. This package includes:
ST Visual Develop – Full-featured integrated development environment from ST, featuring
●
●
●
●
●
●
Seamless integration of C and ASM toolsets
Full-featured debugger
Project management
Syntax highlighting editor
Integrated programming interface
Support of advanced emulation features for STice such as code profiling and coverage
ST Visual Programmer (STVP) – Easy-to-use, unlimited graphical interface allowing read,
write and verify of your STM8 microcontroller’s Flash program memory, data EEPROM and
option bytes. STVP also offers project mode for saving programming configurations and
automating programming sequences.
12.2.2
C and assembly toolchains
Control of C and assembly toolchains is seamlessly integrated into the STVD integrated
development environment, making it possible to configure and control the building of your
application directly from an easy-to-use graphical interface.
Available toolchains include:
●
●
●
Cosmic C compiler for STM8 – Available in a free version that outputs up to
16 Kbytes of code. For more information, see www.cosmic-software.com.
Raisonance C compiler for STM8 – Available in a free version that outputs up to
16 Kbytes of code. For more information, see www.raisonance.com.
STM8 assembler linker – Free assembly toolchain included in the STVD toolset,
which allows you to assemble and link your application source code.
12.3
Programming tools
During the development cycle, STice provides in-circuit programming of the STM8 Flash
microcontroller on your application board via the SWIM protocol. Additional tools are to
include a low-cost in-circuit programmer as well as ST socket boards, which provide
dedicated programming platforms with sockets for programming your STM8.
For production environments, programmers will include a complete range of gang and
automated programming solutions from third-party tool developers already supplying
programmers for the STM8 family.
Doc ID 14733 Rev 9
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Ordering information
STM8S207xx, STM8S208xx
13
Ordering information
(1)
Figure 49. STM8S207xx/208xx performance line ordering information scheme
Example:
STM8
S
208
M
B
T
6
B
TR
Product class
STM8 microcontroller
Family type
S = Standard
Sub-family type(2)
208 = Full peripheral set
207 = Intermediate peripheral set
Pin count
K = 32 pins
S = 44 pins
C = 48 pins
R = 64 pins
M = 80 pins
Program memory size
6 = 32 Kbyte
8 = 64 Kbyte
B = 128 Kbyte
Package type
T = LQFP
Temperature range
3 = -40 °C to 125 °C
6 = -40 °C to 85 °C
Package pitch
No character = 0.5 mm
B = 0.65 mm
C = 0.8 mm
Packing
No character = Tray or tube
TR = Tape and reel
1. For a list of available options (e.g. memory size, package) and orderable part numbers or for further
information on any aspect of this device, please go to www.st.com or contact the ST Sales Office nearest
to you.
2. Refer to Table 2: STM8S20xxx performance line features for detailed description.
100/103
Doc ID 14733 Rev 9
STM8S207xx, STM8S208xx
Revision history
14
Revision history
Table 58. Document revision history
Date
Revision
Changes
23-May-2008
1
Initial release.
Added part numbers on page 1 and in Table 2 on page 11.
Updated Section 4: Product overview.
05-Jun-2008
22-Jun-2008
2
3
Updated Section 10: Electrical characteristics.
Added part numbers on page 1 and in Table 2 on page 11.
Added 32 pin device pinout and ordering information.
Updated UBC option description in Table 13 on page 48.
USART renamed UART1, LINUART renamed UART3.
Max. ADC frequency increased to 6 MHz.
12-Aug-2008
4
Removed STM8S207K4 part number.
Removed LQFP64 14 x 14 mm package.
Added medium and high density Flash memory categories.
Added Section 6: Memory and register map on page 33.
Replaced beCAN3 by beCAN in Section 4.14.5: beCAN.
Updated Section 10: Electrical characteristics on page 52.
20-Oct-2008
5
Updated LQFP44 (Figure 47 and Table 55), and LQFP32 outline and
mechanical data (Figure 48, and Table 56).
Changed VDD minimum value from 3.0 to 2.95 V.
Updated number of High Sink I/Os in pinout.
08-Dec-2008
30-Jan-2009
6
7
Removed FLASH _NFPR and FLASH _FPR registers in Table 9:
General hardware register map.
Removed preliminary status.
Removed VQFN32 package.
Added STM8S207C6, STM8S207S6.
Updated external interrupts in Table 2 on page 11.
Updated Section 10: Electrical characteristics.
Document status changed from “preliminary data” to “datasheet”.
Added LQFP64 14 x 14 mm package.
Added STM8S207M8, STM8S207SB, STM8S208R8, STM8S208R6,
STM8S208C8, and STM8S208C6, STM8S208SB, STM8S208S8,
and STM8S208S6.
Replaced “CAN” with “beCAN”.
Added Table 3 to Section 4.5: Clock controller.
Updated Section 4.8: Auto wakeup counter.
10-Jul-2009
8
Added beCAN peripheral (impacting Table 1 and Figure 6).
Added footnote about CAN_RX/TX to pinout figures 3, 4, and 6.
Table 6: Removed ‘X’ from wpu column of I2C pins (no wpu
available).
Added Table 11: Interrupt mapping.
Doc ID 14733 Rev 9
101/103
Revision history
Table 58. Document revision history (continued)
STM8S207xx, STM8S208xx
Date
Revision
Changes
Section 10: Electrical characteristics: Added data for TBD values;
updated Table 15: Voltage characteristics and Table 18: General
operating conditions; updated VCAP specifications in Table 18 and in
Section 10.3.1: VCAP external capacitor; updated Figure 18;
replaced Figure 19; updated Table 35: RAM and hardware registers;
updated Figure 22 and Figure 35; added Figure 40: Typical
8
10-Jul-2009
cont’d
application with I2C bus and timing diagram(1)
.
Removed Table 56: Junction temperature range.
Added link between ordering information Figure 49 and STM8S20xx
features Table 2.
Document status changed from “preliminary data” to “datasheet”.
Table 2: STM8S20xxx performance line features: high sink I/O for
STM8S207C8 is 16 (not 13).
Table 3: Peripheral clock gating bit assignments in CLK_PCKENR1/2
registers: updated bit positions for TIM2 and TIM3.
Figure 5: LQFP 48-pin pinout: added CAN_TX and CAN_RX to pins
35 and 36; noted that these pins are available only in STM8S208xx
devices.
Figure 7: LQFP 32-pin pinout: replaced uart2 with uart3.
Table 6: Pin description: added footnotes concerning beCAN
availability and UART1_RX and UART3_RX pins.
Table 13: Option byte description: added description of STM8L
bootloader option bytes to the option byte description table.
Added Section 9: Unique ID (and listed this attribute in Features).
Section 10.3: Operating conditions: added introductory text.
13-Apr-2010
9
Table 18: General operating conditions: replaced “CEXT” with “VCAP”
and added data for ESR and ESL; removed “low power dissipation”
condition for TA.
Table 26: Total current consumption in halt mode at VDD = 5 V, TA -40
to 85° C: replaced max value of IDD(H) at 85 °C from 30 µA to 35 µA
for the condition “Flash in powerdown mode, HSI clock after
wakeup”.
Table 33: HSI oscillator characteristics: updated the ACCHSI factory
calibrated values.
Functional EMS (electromagnetic susceptibility) and Table 47:
replaced “IEC 1000” with “IEC 61000”.
Electromagnetic interference (EMI) and Table 48: replaced “SAE
J1752/3” with “IEC 61967-2”.
Table 57: Thermal characteristics: changed the thermal resistance
junction-ambient value of LQFP32 (7x7 mm) from 59 °C/W to 60
°C/W.
102/103
Doc ID 14733 Rev 9
STM8S207xx, STM8S208xx
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103/103
相关型号:
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STMICROELECTR
STM8S207SBT3CTR
Performance line, 24 MHz STM8S 8-bit MCU, up to 128 Kbytes Flash, integrated EEPROM,10-bit ADC, timers, 2 UARTs, SPI, I²C, CAN
STMICROELECTR
STM8S207SBT3TR
Performance line, 24 MHz STM8S 8-bit MCU, up to 128 Kbytes Flash, integrated EEPROM,10-bit ADC, timers, 2 UARTs, SPI, I²C, CAN
STMICROELECTR
STM8S207SBT6
Performance line, 24 MHz STM8S 8-bit MCU, up to 128 Kbytes Flash, integrated EEPROM,10-bit ADC, timers, 2 UARTs, SPI, I²C, CAN
STMICROELECTR
STM8S207SBT6B
Performance line, 24 MHz STM8S 8-bit MCU, up to 128 Kbytes Flash, integrated EEPROM,10-bit ADC, timers, 2 UARTs, SPI, I²C, CAN
STMICROELECTR
STM8S207SBT6BTR
Performance line, 24 MHz STM8S 8-bit MCU, up to 128 Kbytes Flash, integrated EEPROM,10-bit ADC, timers, 2 UARTs, SPI, I²C, CAN
STMICROELECTR
STM8S207SBT6C
Performance line, 24 MHz STM8S 8-bit MCU, up to 128 Kbytes Flash, integrated EEPROM,10-bit ADC, timers, 2 UARTs, SPI, I²C, CAN
STMICROELECTR
STM8S207SBT6CTR
Performance line, 24 MHz STM8S 8-bit MCU, up to 128 Kbytes Flash, integrated EEPROM,10-bit ADC, timers, 2 UARTs, SPI, I²C, CAN
STMICROELECTR
STM8S207SBT6TR
Performance line, 24 MHz STM8S 8-bit MCU, up to 128 Kbytes Flash, integrated EEPROM,10-bit ADC, timers, 2 UARTs, SPI, I²C, CAN
STMICROELECTR
STM8S208C6T3
Performance line, 24 MHz STM8S 8-bit MCU, up to 128 Kbytes Flash, integrated EEPROM,10-bit ADC, timers, 2 UARTs, SPI, I²C, CAN
STMICROELECTR
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