STP16DP05B1R [STMICROELECTRONICS]
Low-voltage 16-bit constant current LED sink driver with outputs error detection;
| 型号： | STP16DP05B1R |
| 厂家： | 
ST |
| 描述： | Low-voltage 16-bit constant current LED sink driver with outputs error detection 驱动 光电二极管 接口集成电路 |
| 文件： | 总33页 (文件大小：567K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
STP16DP05
Low voltage 16-bit constant current LED sink driver with outputs
error detection
Datasheet
-
production data
Description
The STP16DP05 is a monolithic, low voltage, low
current power 16-bit shift register designed for
LED panel displays. The device contains a 16-bit
serial-in, parallel-out shift register that feeds a 16-
bit D-type storage register. In the output stage,
sixteen regulated current sources were designed
to provide 5-100 mA constant current to drive the
LEDs. The STP16DP05 features open and short
LED detections on the outputs.The STP16DP05
is backward compatible with STP16C/L596.The
detection circuit checks 3 different conditions that
can occur on the output line: short to GND, short
to VO or open line. The data detection results are
loaded in the shift register and shifted out via the
serial line output. The detection functionality is
implemented without increasing the pin count
number, through a secondary function of the
output enable and latch pin (DM1 and DM2
respectively), a dedicated logic sequence allows
the device to enter or leave from detection mode.
Through an external resistor, users can adjust the
STP16DP05 output current, controlling in this way
the light intensity of LEDs, in addition, user can
adjust LED’s brightness intensity from 0% to
100% via OE/DM2 pin. The STP16DP05
SO-24
QSOP-24
TSSOP24
TSSOP24
(exposed pad)
Features
• Low voltage power supply down to 3 V
• 16 constant current output channels
• Adjustable output current through external
resistor
• Short and open output error detection
• Serial data IN/Parallel data OUT
• 3.3 V micro driver-able
• Output current: 5-100 mA
• 30 MHz clock frequency
guarantees a 20 V output driving capability,
allowing users to connect more LEDs in series.
The high clock frequency, 30 MHz, makes the
device suitable for high data rate transmission.
The 3.3 V voltage supply is well useful for
• Available in high thermal efficiency TSSOP
exposed pad
• ESD protection 2.5 kV HBM, 200 V MM
applications that interface any 3.3 V micro
Compared with a standard TSSOP package, the
TSSOP exposed pad increases heat dissipation
capability by a 2.5 factor.
Table 1. Device summary
Order codes
Package
Packaging
STP16DP05MTR
STP16DP05TTR
SO-24 (tape and reel)
1000 parts per reel
2500 parts per reel
TSSOP24 (tape and reel)
TSSOP24 exposed pad
(tape and reel)
STP16DP05XTTR
STP16DP05PTR
2500 parts per reel
2500 parts per reel
QSOP-24
June 2014
DocID13093 Rev 7
1/33
This is information on a product in full production.
www.st.com
Contents
STP16DP05
Contents
1
2
Summary description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.1
Pin connection and description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.1
2.2
2.3
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3
4
5
6
7
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Equivalent circuit and outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Typical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Detection mode functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
7.1
7.2
7.3
7.4
Phase one: “entering in detection mode“ . . . . . . . . . . . . . . . . . . . . . . . . . 17
Phase two: “error detection” . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Phase three: “resuming to normal mode” . . . . . . . . . . . . . . . . . . . . . . . . . 20
Error detection conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
8
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Packaging mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
9
10
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STP16DP05
Summary description
1
Summary description
Table 2. Typical current accuracy
Current accuracy
Output voltage
Output current
VDD
Temperature
Between bits Between ICs
≥ 1.3 V
±1.5%
±5%
20 to 100 mA
3.3 V to 5 V
25 °C
1.1
Pin connection and description
Figure 1. Pin connection
Note:
The exposed pad should be electrically connected to a metal land electrically isolated or
connected to ground
Table 3. Pin description
Pin n°
Symbol
Name and function
1
2
GND
SDI
Ground terminal
Serial data input terminal
Clock input terminal
3
CLK
4
LE-DM1
OUT 0-15
Latch input terminal - detect mode 1 (see operation principle)
Output terminal
5-20
Input terminal of output enable (active low) - detect mode 1
(see operation principle)
21
22
OE-DM2
SDO
Serial data out terminal
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33
Summary description
Pin n°
STP16DP05
Table 3. Pin description (continued)
Name and function
Symbol
23
24
R-EXT
VDD
Input terminal of an external resistor for constant current programing
Supply voltage terminal
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STP16DP05
Electrical ratings
2
Electrical ratings
2.1
Absolute maximum ratings
Stressing the device above the rating listed in the “absolute maximum ratings” table may
cause permanent damage to the device. These are stress ratings only and operation of the
device at these or any other conditions above those indicated in the operating sections of
this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
Table 4. Absolute maximum ratings
Symbol
Parameter
Value
Unit
VDD
VO
Supply voltage
Output voltage
Output current
Input voltage
0 to 7
-0.5 to 20
100
V
V
IO
mA
V
VI
-0.4 to VDD
1600
IGND
fCLK
GND terminal current
Clock frequency
mA
MHz
50
2.2
Thermal data
Table 5. Thermal data
Parameter
Symbol
Value
Unit
TOPR
TSTG
Operating temperature range
Storage temperature range
-40 to +125
-55 to +150
42.7
°C
°C
SO-24
°C/W
°C/W
TSSOP24
55
TSSOP24(1)
exposed pad
RthJC
Thermal resistance junction-case
37.5
55
°C/W
°C/W
QSOP-24
1. The exposed pad should be soldered directly to the PCB to realize the thermal benefits.
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Electrical ratings
STP16DP05
2.3
Recommended operating conditions
Table 6. Recommended operating conditions
Symbol
Parameter
Test conditions
Min.
Typ.
Max.
Unit
VDD
VO
Supply voltage
Output voltage
Output current
Output current
Output current
Input voltage
3.0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
5.5
20
V
V
IO
OUTn
5
100
mA
mA
mA
V
IOH
SERIAL-OUT
SERIAL-OUT
+1
IOL
-1
VIH
0.7VDD
-0.3
6
VDD+0.3
0.3VDD
VIL
Input voltage
V
twLAT
twCLK
twEN
LE\DM1 pulse width
CLK pulse width
OE\DM2 pulse width
ns
ns
ns
ns
ns
ns
MHz
8
100
10
VDD = 3.0 V to 5.0 V
Cascade operation (1)
tSETUP(D) Setup time for DATA
tHOLD(D) Hold time for DATA
tSETUP(L) Setup time for LATCH
5
10
fCLK
Clock frequency
30
1. If the device is connected in cascade, it may not be possible achieve the maximum data transfer.
Please consider the timings carefully.
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STP16DP05
Electrical characteristics
3
Electrical characteristics
VDD = 3.3 V to 5 V, T = 25 °C, unless otherwise specified
Table 7. Electrical characteristics
Symbol
Parameter
Test conditions
Min.
Typ.
Max.
Unit
VIH
VIL
IOH
Input voltage high level
Input voltage low level
Output leakage current
0.7VDD
GND
VDD
0.3VDD
1
V
V
VOH = 20 V
μA
Output voltage
(Serial-OUT)
VOL
VOH
IOL = 1 mA
IOH = -1 mA
0.4
V
V
Output voltage
(Serial-OUT)
VOH -VDD = -0.4 V
IOL1
IOL2
VO = 0.3 V, Rext = 3.9 kΩ
VO = 0.3 V, Rext = 970 Ω
VO = 1.3 V, Rext = 190 Ω
4.25
19
5
5.75
21
Output current
20
mA
%
IOL3
96
100
± 5
104
± 8
ΔIOL1
ΔIOL2
ΔIOL3
VO = 0.3 VREXT = 3.9 kΩ
Output current error
between bit
(all output ON)
VO = 0.3 VREXT = 970 Ω
VO = 1.3 VREXT =190 Ω
± 1.5
± 1.2
300
200
± 3
± 3
RSIN(up) Pull-up resistor
150
100
600
400
KΩ
KΩ
RSIN(down) Pull-down resistor
REXT = 970
OUT 0 to 15 = OFF
IDD(OFF1)
5
13
6
6
14
7
Supply current (OFF)
IDD(OFF2)
REXT = 240
OUT 0 to 15 = OFF
mA
°C
REXT = 970
OUT 0 to 15 = ON
IDD(ON1)
Supply current (ON)
IDD(ON2)
REXT = 240
OUT 0 to 15 = ON
13.5
170
14.5
Thermal Thermal protection (1)
1. Guaranteed by design (not tested)
The thermal protection switches OFF only the outputs current
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33
Electrical characteristics
STP16DP05
VDD = 5 V, T = 25 °C, unless otherwise specified
Table 8. Switching characteristics
Symbol
Parameter
Test conditions
Min. Typ. Max. Unit
Propagation delay time,
tPLH1 CLK-OUTn, LE\DM1 = H,
OE\DM2 = L
VDD = 3.3 V
VDD = 5 V
VDD = 3.3 V
VDD = 5 V
-
-
-
-
-
-
40
20
51
32
49
27
65
30
77
47
77
41
ns
ns
Propagation delay time,
tPLH2 LE\DM1 -OUTn,
OE\DM2 = L
Propagation delay time,
tPLH3 OE\DM2-OUTn,
LE\DM1 = H
VDD = 3.3 V
ns
ns
ns
VDD = 5 V
VDD = 3.3 V
VDD = 5 V
-
-
-
21.5
14.5
15
32
21.5
25
Propagation delay time,
CLK-SDO
tPLH
Propagation delay time,
tPHL1 CLK-OUTn, LE\DM1 = H,
OE\DM2 = L
VDD = 3.3 V
VIH = VDD
VIL = GND
VDD = 5 V
VDD = 3.3 V
VDD = 5 V
VDD = 3.3 V
VDD = 5 V
-
-
-
-
-
11
13
14.5
20
CL = 10 pF
VL = 3.0 V
RL = 60 Ω
IO = 20 mA
Propagation delay time,
tPHL2 LE\DM1 -OUTn,
OE\DM2 = L
REXT = 1 KΩ
ns
9
12.5
18
Propagation delay time,
tPHL3 OE\DM2-OUTn,
LE\DM1 = H
11.5
8.5
ns
ns
ns
12
VDD = 3.3 V
VDD = 5 V
-
-
-
25.5
17.5
34
38
25
Propagation delay time,
CLK-SDO
tPHL
Output rise time
10~90% of voltage
waveform
VDD = 3.3 V
53.5
tON
VDD = 5 V
VDD = 3.3 V
VDD = 5 V
-
-
-
12.5
5.5
18.5
8.5
Output fall time
90~10% of voltage
waveform
tOFF
ns
4.5
6.5
tr
tf
CLK rise time (1)
CLK fall time (1)
-
-
5000
5000
ns
ns
1. In order to achieve high cascade data transfer, please consider tr/tf timings carefully.
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STP16DP05
Equivalent circuit and outputs
4
Equivalent circuit and outputs
Figure 2. OE\DM2 terminal
Figure 3. LE\DM1 terminal
Figure 4. CLK, SDI terminal
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33
Equivalent circuit and outputs
STP16DP05
Figure 5. SDO terminal
Figure 6. Block diagram
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STP16DP05
Timing diagrams
5
Timing diagrams
Table 9. Truth table
CLOCK LE\DM1 OE\DM2 SERIAL-IN OUT0 ............. OUT7 ................ OUT15
SDO
H
L
L
L
L
L
H
Dn
Dn ..... Dn - 7 ..... Dn -15
No change
Dn - 15
Dn - 14
Dn - 13
Dn - 13
Dn - 13
Dn + 1
Dn + 2
Dn + 3
Dn + 3
H
X
X
Dn + 2 ..... Dn - 5 ..... Dn -13
Dn + 2 ..... Dn - 5 ..... Dn -13
OFF
Note:
OUTn = ON when Dn = H OUTn = OFF when Dn = L
Figure 7. Timing diagram
Note:
1
Latch and output enable are level sensitive and ARE NOT synchronized with rising-or-falling
edge of CALK signal.
2
3
4
When LE terminal is low level, the latch circuits hold previous set of data
When LE terminal is at high level, the latch circuits refresh new set of data from SDI chain.
When OE terminal is at low level, the output terminals - Out0 to Out15 respond to data in the
latch circuits, either '1' for ON or '0' for OFF
5
When OE terminal is at high level, all output terminals will be switched OFF.
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Timing diagrams
STP16DP05
Figure 8. Clock, serial-in, serial-out
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STP16DP05
Timing diagrams
Figure 9. Clock, serial-in, latch, enable, outputs
LE\DM1
OE\DM2
Figure 10. Outputs
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33
Typical characteristics
STP16DP05
6
Typical characteristics
Figure 11. Output current-REXT resistor
Table 10. Output current-REXT resistor
Rext (Ω)
Output current (mA)
976
780
652
560
488
433
389
354
325
300
278
259
241
229
215
20
25
30
35
40
45
50
55
60
65
70
75
80
85
90
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STP16DP05
Typical characteristics
Conditions:
Temperature = 25 °C, VDD = 3.3 V; 5.0 V, ISET = 3 mA; 5 mA; 10 mA; 20 mA; 50 mA; 80 mA.
Figure 12. ISET vs drop out voltage (Vdrop
)
800
700
600
500
400
300
200
100
0
Avg @ 3.0V
Avg @ 5.0V
0
20
40
60
80
Iset mA)
Table 11. ISET vs drop out voltage (Vdrop
Avg @ 3.0 V
)
Iout (mA)
Avg @ 5.0 V
3
19.33
36.67
77.33
158.67
406
22.66
40.33
80
5
10
20
50
80
157.33
406
692
668
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33
Typical characteristics
STP16DP05
Figure 13. IDD ON\OFF
14
12
10
8
IddON Avg @ 5.5V
IddON Avg @ 3.6V
IddOFF Avg @ 5.5V
IddOFF Avg @ 3.6V
6
4
2
0
0
10 20 30 40 50 60 70 80 90
Iset (mA)
Figure 14. Power dissipation vs temperature package
Note:
The exposed pad should be soldered to the PBC to realize the thermal benefits.
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STP16DP05
Detection mode functionality
7
Detection mode functionality
7.1
Phase one: “entering in detection mode“
From the “normal mode” condition the device can switch to the “error mode” by a logic
sequence on the OE\DM2 and LE/DM1 pins as showed in the following table and diagram:
Table 12. Entering in detection truth table
CLK
1°
H
L
2°
L
3°
H
L
4°
H
5°
H
L
OE/DM2
LE/DM1
L
H
Figure 15. Entering in detection timing diagram
After these five CLK cycles the device goes into the “error detection mode” and at the 6th
rise front of CLK the SDI data are ready for the sampling.
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33
Detection mode functionality
STP16DP05
7.2
Phase two: “error detection”
The 16 data bits must be set “1” in order to set ON all the outputs during the detection. The
data are latched by LE/DM1 and after that the outputs are ready for the detection process.
When the micro controller switches the OE\DM2 to LOW, the device drives the LEDs in
order to analyze if an OPEN or SHORT condition has occurred.
Figure 16. Detection diagram
The LEDs status will be detected at least in 1 microsecond and after this time the
microcontroller sets OE\DM2 in HIGH state and the output data detection result will go to the
microprocessor via SDO.
Detection mode and normal mode use both the same format data. As soon as all the
detection data bits are available on the serial line, the device may go back to normal mode
of operation. To re-detect the status the device must go back in normal mode and re-
entering in error detection mode.
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STP16DP05
Detection mode functionality
Figure 17. Timing example for open and/or short detection
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Detection mode functionality
STP16DP05
7.3
Phase three: “resuming to normal mode”
The sequence for re-entering in normal mode is showed in the following table and diagram:
Figure 18. Resuming to normal mode timing diagram
CLK
1°
H
L
2°
L
3°
H
L
4°
H
L
5°
H
L
OE/DM2
LE/DM1
L
Note:
For proper device operation the “Entering in detection” sequence must be follow by a
“resume mode” sequence, it is not possible to insert consecutive equal sequence.
7.4
Error detection conditions
VDD = 3.3 to 5 V temperature range -40 to 125 °C
Table 13. Detection conditions
SW-1 or Open line or output
==> IODEC ≤ 0.5 x IO No error detected ==> IODEC ≥ 0.5 x IO
SW-3b short to GND detected
SW-2 or Short on LED or short
SW-3a to V-LED detected
==> VO ≥ 2.4 V
No error detected ==> VO ≤ 2.2 V
Note:
Where: IO = the output current programmed by the REXT, IODEC = the detected output
current in detection mode
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STP16DP05
Detection mode functionality
Figure 19. Detection circuit
STP16DP05
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33
Detection mode functionality
STP16DP05
Figure 20. Error detection sequence
During the error
detection are
necessary at least
2 CLK signal plus
oneat the end
16 CLK pulse are required to
load the data setting 1 into
shift register
Every CLK pulse shows the results of
single Output results:Out15;14; 13 etc. etc
The OE Pulse put
the device from
EDM to Normal
Mode
The LE pulse
latch the data
loaded during the
previous state
LE and OE Key
Sequence
necessary to Enter
in EDM
After OE signal turn High the
SDO pin show the results of
Error Detection (Open or
Short in this case)
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STP16DP05
Package mechanical data
8
Package mechanical data
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
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Package mechanical data
STP16DP05
Figure 21. QSOP-24 package dimensions
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STP16DP05
Package mechanical data
Table 14. QSOP-24 mechanical data
mm.
Dim.
Min
Typ
Max
A
A1
A2
b
1.54
0.1
1.62
0.15
1.47
0.2
1.73
0.25
0.31
0.254
8.56
5.8
c
0.17
8.66
6
D
E
8.76
6.2
E1
e
3.8
3.91
0.635
0.635
0.33
0°
4.01
L
0.4
0.25
8°
0.89
0.41
h
<
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33
Package mechanical data
STP16DP05
Figure 22. TSSOP24 package dimensions
Table 15. TSSOP24 mechanical data
mm
Dim.
Min.
Typ.
Max.
A
A1
A2
b
1.1
0.05
0.15
0.9
0.19
0.09
7.7
0.30
0.20
7.9
c
D
E
4.3
4.5
e
0.65 BSC
H
K
6.25
0°
6.5
8°
L
0.50
0.70
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STP16DP05
Package mechanical data
Figure 23. SO-24 package dimensions
Table 16. SO-24 mechanical data
mm.
Dim.
Min
Typ
Max
A
a1
a2
b
2.65
0.2
0.1
2.45
0.49
0.32
0.35
0.23
b1
C
0.5
c1
45°(typ.)
D
E
15.20
10.00
15.60
10.65
e
1.27
e3
F
13.97
7.40
0.50
7.60
1.27
L
S
°(max.) 8
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Package mechanical data
STP16DP05
Figure 24. TSSOP24 exposed pad dimensions
7100778_D
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STP16DP05
Package mechanical data
Table 17. TSSOP24 exposed pad mechanical data
mm
Dim.
Min.
Typ.
Max.
A
A1
A2
b
1.20
0.15
1.05
0.30
0.20
7.90
5.2
0.80
0.19
0.09
7.70
4.80
6.20
4.30
3.00
1.00
c
D
7.80
5.00
6.40
4.40
3.20
0.65
0.60
1.00
D1
E
6.60
4.50
3.40
E1
E2
e
L
0.45
0
0.75
L1
k
8
aaa
0.10
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Packaging mechanical data
STP16DP05
9
Packaging mechanical data
Figure 25. TSSOP24, TSSOP24 exposed pad and SO-24 reel dimensions
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STP16DP05
Packaging mechanical data
Table 18. TSSOP24 and TSSOP24 exposed pad tape and reel mechanical data
mm
Dim.
Min.
Typ.
Max.
A
C
-
-
-
-
-
-
-
-
-
-
330
12.8
20.2
60
13.2
D
N
T
22.4
7
Ao
Bo
Ko
Po
P
6.8
8.2
8.4
1.9
4.1
12.1
1.7
3.9
11.9
Table 19. SO-24 tape and reel mechanical data
mm.
Dim.
Min
Typ
Max
A
C
-
-
-
-
-
-
-
-
-
-
330
12.8
20.2
60
13.2
D
N
T
30.4
11.0
15.9
3.1
Ao
Bo
Ko
Po
P
10.8
15.7
2.9
3.9
4.1
11.9
12.1
DocID13093 Rev 7
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Revision history
STP16DP05
10
Revision history
Table 20. Document revision history
Revision Changes
Date
9-Jan-2007
21-May-2007
10-Jul-2007
1
2
3
First release
Updated Table 7 on page 7
Updated Table 9: Truth table on page 11
Updated Table 15: TSSOP24 exposed-pad on page 23
28-Feb-2008
4
Added QSOP-24 package information Table 14 and Figure 21
on page 24
23-Oct-2009
20-Jan-2010
5
6
Updated Figure 7 on page 11, Chapter 3 on page 7
Updated Table 5 on page 5
Updated Section 8: Package mechanical data.
Added Section 9: Packaging mechanical data.
Minor text changes.
17-Jun-2014
7
32/33
DocID13093 Rev 7
STP16DP05
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