STP16DPP05 [STMICROELECTRONICS]

Short and open output error detection;


型号：	STP16DPP05
厂家：	ST
描述：	Short and open output error detection
文件：	总34页 (文件大小：1406K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

STP16DPP05

Low voltage 16-bit constant current LED sink driver with output

error detection

Datasheet - production data

feeds a 16- bit D-type storage register. In the

output stage, sixteen regulated current sources

are designed to provide 3 to 40 mA of constant

current to drive the LEDs. The STP16DPP05

features open and short LED detection on the

outputs. The detection circuit checks for 3

different conditions that can occur on the output

line: short to GND, short to V_Oor open line. The

data detection results are loaded in the shift

registers and shifted out via the serial line output.

The detection functionality is implemented

without increasing the pin count, through a

secondary function of the output enable and latch

pin (DM1 and DM2 respectively). A dedicated

Features

logic sequence allows the device to enter or exit

from detection mode. The STP16DPP05 output

current can be adjusted through an external

resistor to control the light intensity of the LEDs.

LED brightness is adjustable from 0% to 100%



Low voltage power supply down to 3 V

16 constant current output channels

Adjustable output current through external

resistor

via the OE/DM2 pin. The STP16DPP05



Short and open output error detection

Serial data IN/parallel data OUT

3.3 V MCU-driving capability

Output current: 3 to 40 mA

30 MHz clock frequency

Available in high thermal efficiency TSSOP

exposed pad

guarantees a 20 V output driving capability,

allowing users to connect more LEDs in series.

The high 30 MHz clock frequency makes the

device suitable for high data rate transmission.

The 3.3 V supply is well suited for applications

which interface a 3.3 V MCU. Compared to a

standard TSSOP package, the TSSOP with

exposed pad increases heat dissipation capability

by a factor of 2.5.



ESD protection: 2 kV HBM, 200 V MM

Description

The STP16DPP05 is a monolithic, low voltage,

low current power 16-bit shift register designed

for LED panel displays. The device features a

16-bit serial-in, parallel-out shift register that

Table 1: Device summary

Order code

Package

Packing

STP16DPP05MTR

STP16DPP05TTR

STP16DPP05XTTR

STP16DPP05PTR

SO-24 (tape and reel)

TSSOP24 (tape and reel)

TSSOP24 exposed pad (tape and reel)

QSOP-24

1000 parts per reel

2500 parts per reel

April 2017

DocID16518 Rev 4

1/34

www.st.com

This is information on a product in full production.

Contents

STP16DPP05

Contents

Summary description......................................................................3

1.1

Pin connection and description .........................................................3

Electrical ratings .............................................................................4

2.1

2.2

2.3

Absolute maximum ratings................................................................4

Thermal data.....................................................................................4

Recommended operating conditions.................................................5

Electrical characteristics ................................................................6

Equivalent circuit and outputs .......................................................8

Timing diagrams............................................................................11

Typical characteristics..................................................................14

Error detection mode functionality ..............................................18

7.1

7.2

7.3

7.4

Phase one: entering error detection mode......................................18

Phase two: error detection ..............................................................19

Phase three: resuming normal mode ..............................................21

Error detection conditions ...............................................................21

Package information .....................................................................23

8.1

8.2

8.3

8.4

8.5

QSOP-24 package information .......................................................24

SO-24 package information ............................................................26

TSSOP24 package information.......................................................27

TSSOP exposed pad package information .....................................29

TSSOP24, TSSOP24 exposed pad and .............................................

SO-24 packing information..............................................................31

Revision history ............................................................................33

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STP16DPP05

Summary description

Table 2: Typical current accuracy

Current accuracy

Between bits Between ICs

± 1% ± 2%

Temperature

Output voltage

Output current

V_DD

≥ 1.3 V

5 to 40 mA

3.3 V to 5 V

25 °C

1.1

Pin connection and description

Figure 1: Pin connection

The exposed pad should be electrically connected to a metal land electrically

isolated or connected to ground.

Table 3: Pin description

Pin n°

Symbol

GND

Name and function

Ground terminal

SDI

Serial data input terminal

Clock input terminal

CLK

LE/DM1

OUT 0-15

Latch input terminal - detect mode 1 (see operation principle)

Output terminal

5-20

Input terminal of output enable (active low) - detect mode 1

(see operation principle)

OE/DM2

SDO

R-EXT

V_DD

Serial data out terminal

Input terminal for an external resistor for constant current programming

Supply voltage terminal

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Electrical ratings

STP16DPP05

Electrical ratings

2.1

Absolute maximum ratings

Stressing the device above the ratings listed in the “absolute maximum ratings” table may

cause permanent damage to the device. These are stress ratings only and operation of the

device at these or any other condition above those indicated in the operating sections of

this specification is not implied. Exposure to absolute maximum rating conditions for

extended periods may affect device reliability.

Table 4: Absolute maximum ratings

Symbol

V_DD

V_O

Parameter

Value

0 to 7

Unit

Supply voltage

Output voltage

Output current

Input voltage

-0.5 to 20

I_O

V_I

-0.4 to V_DD

800

I_GND

f_CLK

T_J

GND terminal current

Clock frequency

MHz

°C

Junction temperature range ⁽¹⁾

-40 to +170

Notes:

⁽¹⁾Such absolute value is based on the thermal shutdown protection.

2.2

Thermal data

Table 5: Thermal data

Symbol

T_A

Parameter

Operating free-air temperature range

Operating thermal junction temperature range

Storage temperature range

Value

-40 to +125

-40 to +150

-55 to +150

42.7

Unit

°C

T_J-OPR

T_STG

°C

SO-24

°C/W

TSSOP24

R_thJA

Thermal resistance junction-ambient ⁽¹⁾

TSSOP24 ⁽²⁾

exposed pad

37.5

°C/W

QSOP-24

Notes:

⁽¹⁾According with JEDEC standard 51-7.

⁽²⁾The exposed pad should be soldered directly to the PCB to obtain the thermal benefits.

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STP16DPP05

Electrical ratings

2.3

Recommended operating conditions

Table 6: Recommended operating conditions

Symbol

V_DD

V_O

Parameter

Supply voltage

Test conditions

Min.

Typ.

Max.

5.5

Unit

Output voltage

Output current

Input voltage

I_O

OUTn

I_OH

SERIAL-OUT

I_OL

-1

V_IH

0.7 V_DD

-0.3

V_DD

0.3 V_DD

V_IL

Input voltage

t_wLAT

t_wCLK

LE/DM1 pulse width

CLK pulse width

OE/DM2 pulse width

t_wEN

100

V_DD= 3.0 V to 5.0 V

Cascade operation ⁽¹⁾

t_SETUP(D)

t_HOLD(D)

t_SETUP(L)

f_CLK

Setup time for DATA

Hold time for DATA

Setup time for LATCH

Clock frequency

MHz

Notes:

⁽¹⁾If the device is connected in cascade, it may not be possible achieve the maximum data transfer. Please

consider the timings carefully.

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Electrical characteristics

STP16DPP05

Electrical characteristics

V_DD= 3.3 V to 5 V, T_A= 25 °C, unless otherwise specified.

Table 7: Electrical characteristics

Symbol

V_IH

Parameter

Test conditions

Min.

0.7 V_DD

GND

Typ.

Max.

V_DD

Unit

Input voltage high level

Input voltage low level

Output leakage current

Output voltage (serial-OUT)

V_IL

0.3 V_DD

I_OH

V_OH= 20 V

μA

V_OL

V_OH

I_OL1

I_OL= 1 mA

0.4

I_OH= -1 mA

V_DD-0.4V

4.75

V_O= 0.3 V, R_ext= 4 kΩ

V_O= 0.3 V, R_ext= 1 kΩ

V_O= 1.3 V, R_ext= 497 Ω

5.25

Output current

I_OL2

I_OL3

V_O= 0.3 V, I_O= 5 mA

ΔI_OL1

ΔI_OL2

± 1

± 5

± 3

R_ext= 4 kΩ

V_O= 0.3 V, I_O= 20 mA

Output current error between

bit (all output ON)

± 0.5

R_ext= 980 Ω

V_O= 1.3 V, I_O= 40 mA

ΔI_OL3

R_ext= 490 Ω

R_SIN(up)

Pull-up resistor

150

100

300

200

600

400

kΩ

R_SIN(down)Pull-down resistor

R_ext= 1 kΩ, I_OUT= 20 mA,

OUT 0 to 15 = OFF

I_DD(OFF1)

5.4

7.5

9.5

7.5

9.5

Supply current (OFF)

I_DD(OFF2)

R_ext= 497 Ω, I_OUT= 40 mA

OUT 0 to 15 = OFF

R_ext= 1 kΩ, I_OUT= 20 mA,

OUT 0 to 15 = ON

I_DD(ON1)

5.5

Supply current (ON)

I_DD(ON2)

R_ext= 497 Ω, I_OUT= 40 mA

OUT 0 to 15 = ON

8.1

Thermal Thermal protection

170

°C

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STP16DPP05

V_DD= 3.3 V to 5 V, T_A= 25 °C, unless otherwise specified.

Electrical characteristics

Table 8: Switching characteristics

Test conditions

Symbol

Parameter

Min. Typ. Max. Unit

Propagation delay time,

V_DD= 3.3 V

V_DD= 5 V

V_DD= 3.3 V

V_DD= 5 V

35.5 44.5

CLK- OUTn , LE/DM1 = H,

t_PLH1

18.5

41.5

OE/DM2 = L

Propagation delay time,

LE/DM1 - OUTn ,

t_PLH2

OE/DM2 = L

Propagation delay time,

OE/DM2 - OUTn ,

V_DD= 3.3 V

V_DD= 5 V

t_PLH3

LE = H

V_DD= 3.3 V

V_DD= 5 V

Propagation delay time,

CLK-SDO

t_PLH

Propagation delay time,

V_DD= 3.3 V

13.7

V_IH= V_DD

CLK- OUTn , LE/DM1 = H,

V_IL= GND C_L= 10 pF

I_O= 20 mA V_L= 3.0 V

R_ext= 1 KΩ R_L= 60 Ω

t_PHL1

V_DD= 5 V

8.8

12.5

OE/DM2 = L

Propagation delay time,

LE/DM1 - OUTn

V_DD= 3.3 V

V_DD= 5 V

t_PHL2

OE/DM2 = L

Propagation delay time,

OE/DM2 - OUTn ,

LE/DM1 = H

V_DD= 3.3 V

V_DD= 5 V

12.7

9.5

t_PHL3

V_DD= 3.3 V

V_DD= 5 V

V_DD= 3.3 V

V_DD= 5 V

V_DD= 3.3 V

V_DD= 5 V

17.5

12.5

Propagation delay time,

CLK-SDO

t_PHL

Output rise time 10~90% of

voltage waveform

t_ON

4.5

3.5

Output fall time 90~10% of

voltage waveform

t_OFF

t_r

t_f

CLK rise time ⁽¹⁾

CLK fall time ⁽¹⁾

5000

Notes:

⁽¹⁾In order to achieve high cascade data transfer, please consider tr/tf timings carefully.

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Equivalent circuit and outputs

STP16DPP05

Equivalent circuit and outputs

Figure 2: OE/DM2 terminal

Figure 3: LE/DM1 terminal

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STP16DPP05

Equivalent circuit and outputs

Figure 4: CLK, SDI terminal

Figure 5: SDO terminal

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Equivalent circuit and outputs

STP16DPP05

Figure 6: Block diagram

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STP16DPP05

Timing diagrams

Table 9: Truth table

OE/DM2

OUT0 ............. OUT7 ................ OUT15

CLOCK

LE/DM1

SERIAL-IN

SDO

_|¯

¯|_

Dn ..... Dn - 7 ..... Dn -15

No change

Dn - 15

Dn - 14

Dn - 13

Dn + 1

Dn + 2

Dn + 3

Dn + 2 ..... Dn - 5 ..... Dn -13

OFF

OUTn = ON when Dn = H OUTn = OFF when Dn = L.

Figure 7: Timing diagram

1 Latch and output enable terminals are level-sensitive and are not synchronized

with rising or falling edge of CLK signal.

2 When LE/DM1 terminal is low level, the latch circuit holds previous set of data.

3 When LE/DM1 terminal is high level, the latch circuit refreshes new set of data

from SDI chain.

4 When OE/DM2 terminal is at low level, the output terminals Out 0 to Out 15

respond to data in the latch circuits, either ‘1’ for ON or ‘0’ for OFF.

5 When OE/DM2 terminal is at high level, all output terminals are switched

OFF.

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Timing diagrams

STP16DPP05

Table 10: Enable IO: shutdown truth table

CLOCK LE/DM1 SDI0 ...........SDI7............ SDI15

Auto power-up

OUTn

OFF

_|¯

All = L

Active

Not active ⁽¹⁾

No change

Active

No change

Not active

No change

X ⁽²⁾

One or more = H

Notes:

⁽¹⁾At power-up, the device starts in shutdown mode.

⁽²⁾Undefined.

Figure 8: Clock, serial-in, serial-out

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STP16DPP05

Timing diagrams

Figure 9: Clock, serial-in, latch, enable, outputs

Figure 10: Outputs

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Typical characteristics

STP16DPP05

Typical characteristics

Figure 11: Output current vs. R-_EXTresistor

Table 11: Output current vs. R-_EXTresistor

Output current (mA)

R-_EXT(Ω)

23700

11730

6930

4090

2025

1000

667

497

331

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STP16DPP05

Typical characteristics

Conditions: temperature = 25 °C, V_DD= 3.3 V; 5.0 V, I_SET= 3 mA; 5 mA; 10 mA; 20 mA;

50 mA; 60 mA.

Figure 12: I_SETvs. dropout voltage (V_drop

)

Table 12: I_SETvs. dropout voltage (V_drop

Avg (mV) @ 3.3 V

)

Iout (mA)

Avg (mV) @ 5.0 V

163

346

724

1080

163

347

726

1110

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Typical characteristics

T_A= 25 °C, V_dd= 3.3 V; 5 V

STP16DPP05

Figure 13: Output current vs. ± ΔI_OL(%)

Figure 14: I_ddON/OFF

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Typical characteristics

Figure 15: Power dissipation vs package temperature

The exposed pad should be soldered to the PCB to obtain the thermal benefits.

Figure 16: Turn ON output current

characteristics⁽¹⁾

Figure 17: Turn OFF output current

characteristics⁽²⁾

Notes:

⁽¹⁾The reference level for the TON characteristics is 50% of OE/DM2 signal and 90 % of output current.

⁽²⁾The reference level for the TOFF characteristics is 50% of OE/DM2 signal and 10 % of output current.

Electrical conditions: Vdd = 3.3 V, Vin = Vdd, Vled = 3.0 V, RL = 60 Ω, CL = 10 pF Ch1

(Yellow) = OE/DM2 , Ch2 (Blue) = SDI, Ch3 (Purple) = VOUT, Ch4 (Green) = OUT

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Error detection mode functionality

STP16DPP05

Error detection mode functionality

7.1

Phase one: entering error detection mode

From the “normal mode” condition the device can switch to “error mode” by a logic

sequence on the OE/DM2 and LE/DM1 pins, as shown in the following table and

diagram:

Table 13: Entering error detection mode - truth table

CLK

1°

2°

3°

4°

5°

OE/DM2

LE/DM1

Figure 18: Entering error detection mode - timing diagram

After these five CLK cycles, the device goes into “error detection mode” and at the rising

edge of the 6th CLK cycle, the SDI data are ready for sampling.

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Error detection mode functionality

7.2

Phase two: error detection

The 16 data bits must be set to “1” in order for all the outputs to be ON during error

detection. The data are latched by LE/DM1, after which the outputs are ready for the

detection process. When the microcontroller switches the OE/DM2 to LOW, the device

drives the LEDs to analyze if an OPEN or SHORT condition has occurred.

Figure 19: Detection diagram

The status of the LEDs is detected in at least 1 microsecond, and after this period the

microcontroller sets OE/DM2 to HIGH state and the output data detection result is sent

to the microcontroller via SDO. Error detection mode and normal mode both use the same

data format. As soon as all the detection data bits are available on the serial line, the

device may return to normal mode of operation. To re-detect the status, the device must

first return to normal mode and reenter error detection mode.

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Error detection mode functionality

Figure 20: Timing example for open and/or short-circuit detection

STP16DPP05

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STP16DPP05

Error detection mode functionality

7.3

Phase three: resuming normal mode

The sequence for reentering normal mode is shown in the following table:

Table 14: Resuming normal mode - timing diagram

CLK

1°

2°

3°

4°

5°

OE/DM2

LE/DM1

For proper device operation, the “entering error detection” sequence must be

followed by a “resume mode” sequence, it is not possible to insert consecutive

equal sequences.

7.4

Error detection conditions

Table 15: Detection conditions (VDD = 3.3 to 5 V, temperature range -40 to 125 °C)

Configuration

Detect mode

Detection results

Open line or output

short to GND detected

No error

detected

SW-1 or SW-3b

==> I_ODEC≤ 0.5 x I_O

==> V_O≥ 2.6 V

==> I_ODEC≥ 0.5 x I_O

==> V_O≤ 2.3 V

Short on LED or short

to V-LED detected

No error

detected

SW-2 or SW-3a

Where: I_O= the output current programmed by the R-EXT, I_ODEC= the detected

output current in detection mode

Figure 21: Detection circuit

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Error detection mode functionality

STP16DPP05

Figure 22: Error detection sequence

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STP16DPP05

Package information

In order to meet environmental requirements, ST offers these devices in different grades of

ECOPACK^®packages, depending on their level of environmental compliance. ECOPACK^®

specifications, grade definitions and product status are available at: www.st.com.

ECOPACK^®is an ST trademark.

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Package information

STP16DPP05

8.1

QSOP-24 package information

Figure 23: QSOP-24 package outline

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STP16DPP05

Package information

Table 16: QSOP-24 mechanical data

Dim.

Min.

1.54

0.10

Typ.

1.62

0.15

1.47

Max.

1.73

0.25

0.20

0.17

8.56

5.80

3.80

0.31

0.254

8.76

6.20

4.01

8.66

6.00

3.91

0.635

0.33

0.40

0.25

0°

0.89

0.41

8°

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Package information

STP16DPP05

8.2

SO-24 package information

Figure 24: SO-24 package outline

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Package information

Table 17: SO-24 mechanical data

Dim.

Min.

2.35

0.10

0.33

0.23

15.20

7.40

Typ.

Max.

2.65

0.30

0.51

0.32

15.60

7.60

1.27

10.00

0.25

0.40

10.65

0.75

1.27

ddd

0.10

8.3

TSSOP24 package information

Figure 25: TSSOP24 package outline

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Package information

STP16DPP05

Table 18: TSSOP24 mechanical data

Dim.

Min.

Typ.

Max.

1.1

0.05

0.15

0.9

0.19

0.09

7.7

0.30

0.20

7.9

4.3

4.5

0.65 BSC

6.25

0°

6.5

8°

0.50

0.70

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STP16DPP05

Package information

8.4

TSSOP exposed pad package information

Figure 26: TSSOP24 exposed pad package outline

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Package information

STP16DPP05

Table 19: TSSOP24 exposed pad mechanical data

Dim.

Min.

Typ.

Max.

1.20

0.15

1.05

0.30

0.20

7.90

5.2

0.80

0.19

0.09

7.70

4.80

6.20

4.30

3.00

1.00

7.80

5.00

6.40

4.40

3.20

0.65

060

6.60

4.50

3.40

0.45

0°

075

1.00

8°

aaa

0.10

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Package information

8.5

TSSOP24, TSSOP24 exposed pad and SO-24 packing

information

Figure 27: TSSOP24, TSSOP24 exposed pad and SO-24 reel outline

Table 20: TSSOP24 and TSSOP24 exposed pad tape and reel mechanical data

Dim.

Min.

Typ.

Max.

330

12.8

20.2

13.2

22.4

6.8

8.2

8.4

1.9

4.1

12.1

1.7

3.9

11.9

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Package information

STP16DPP05

Table 21: SO-24 tape and reel mechanical data

Dim.

Min.

Typ.

Max.

330

12.8

20.2

13.2

30.4

11.0

15.9

3.1

10.8

15.7

2.9

3.9

4.1

11.9

12.1

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Revision history

Table 22: Document revision history

Changes

Date

Revision

22-Oct-2009

First release.

Updated Section 8: Package mechanical data.

Added Section 9: Packaging mechanical data.

Minor text changes.

19-Jun-2014

04-Apr-2016

04-Apr-2017

Updated Table 16: "QSOP-24 mechanical data".

Minor text changes.

Updated Figure 5: "SDO terminal", Figure 8: "Clock, serial-in,

serial-out" and Figure 9: "Clock, serial-in, latch, enable, outputs".

Minor text changes.

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STP16DPP05

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Information in this document supersedes and replaces information previously supplied in any prior versions of this document.

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STP16DPP05 [STMICROELECTRONICS]

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