STP24DP05BTR [STMICROELECTRONICS]
24-bit constant current LED sink driver with output error detection; 24位恒流LED散热器与输出错误检测的驱动程序
| 型号： | STP24DP05BTR |
| 厂家： | 
ST |
| 描述： | 24-bit constant current LED sink driver with output error detection |
| 文件： | 总26页 (文件大小：471K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
STP24DP05
24-bit constant current
LED sink driver with output error detection
Features
■ Low voltage power supply down to 3 V
■ 8 x 3 constant current output channels
■ Adjustable output current through external
resistors
■ Short and open output error detection
■ Serial data IN/Parallel data OUT
■ Shift register data flow registers control
■ Accepts 3.3 V and 5 V micro driver
■ Output current: 5-80 mA
TQFP48
The data detection results are loaded in the shift
registers and shifted out via the serial line output.
The detection functionality is activated with a
dedicated pin or as alternative, through a logic
sequence that allows the user to enter or exit from
detection mode.
■ 25 MHz clock frequency
■ High thermal efficiency package
Through three external resistors, users can adjust
the output current for each 8-channel group,
controlling in this way the light intensity of LEDs.
Description
The STP24DP05 is a monolithic, low voltage, low
current power 24-bit shift register designed for
LED panel displays. The device contains a
8 x 3-bit serial-in, parallel-out shift register that
feeds a 8 x 3-bit D-type storage register. In the
output stage, twenty-four regulated current
sources were designed to provide 5-80 mA
constant current to drive the LEDs.
The STP24DP05 guarantees a 20 V output
driving capability, allowing users to connect more
LEDs in series.
The high clock frequency, 25 MHz, makes the
device suitable for high data rate transmission.
The 3.3 V of voltage supply is useful for
applications that interface any micro from 3.3 V.
The 8x3 shift registers data flow sequence order
can be managed with two dedicated pins.
The STP24DP05 has a dedicated pin to activate
the outputs with a sequential delay, that will
prevent inrush current during outputs turn-ON.
The device detection circuit checks 3 different
conditions that can occur on the output line: short
to GND, short to V or open line.
O
Table 1.
Device summary
Order code
Package
Packaging
STP24DP05BTR
TQFP48
Tape and reel
May 2008
Rev 1
1/26
www.st.com
26
Contents
STP24DP05
Contents
1
Summary description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.1
Pin connection and description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2
Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.1
2.2
2.3
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3
4
5
6
7
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Equivalent circuit and outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Feature description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
7.1
7.2
7.3
7.4
7.5
7.6
7.7
DG: gradual outputs delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Error detection condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Phase one: “entering in detection mode” . . . . . . . . . . . . . . . . . . . . . . . . . 16
Phase two: “error detection” . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Phase three: “resuming to normal mode” . . . . . . . . . . . . . . . . . . . . . . . . . 18
Shift registers data flow control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
EFLAG/TFLAG - output detection and overtemperature monitoring . . . . 19
8
Typical application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Typical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
9
10
11
2/26
STP24DP05
Summary description
1
Summary description
Table 2.
Current accuracy
Typical current accuracy
VDD
Output voltage
Output current
Temperature
Between bits Between ICs
≥ 1.0 V
≥ 0.2 V
3 %
6 %
6 %
6 %
≥ 15 to 80 mA
3.3 V to 5 V
25 °C
5 to 15 mA
1.1
Pin connection and description
Figure 1. Pin connection
TQFP48 exposed pad
3/26
Summary description
Table 3.
STP24DP05
Pin description
Pin N°
1, 7, 12, 25, 30, 36
Symbol
Name and function
GND
SDI
Ground terminal
Serial data input
Serial data output
Clock for serial data
2
35
4
SDO
CLK
3
LE\DM
DM
Data latch in both SH register
Detection mode pin
5
13, 16, 19, 22,
39, 42, 45, 48
R1 - 8
8 channel LED driver outputs
8
29
9
TF
EF
DG
Thermal flag (open drain)
Error detection flag (open drain)
Gradual delay
15, 17, 20, 23,
37, 40, 43, 46
B1 - 8
8 channel LED driver outputs
32
33
34
28
27
26
OE-B
OE-G
Output enable for B1 - 8
Output enable for G1 - 8
Output enable for R1 - 8
Control outputs R1 - 8
Control outputs G1 - 8
Control outputs B1 - 8
OE-R\DM
REXTR
REXTG
REXTB
14, 18, 21, 24,
38, 41, 44, 48
G1 - 8
8 channel LED driver outputs
10
11
31
DF0
DF1
VDD
Data banks flow bit 0
Data banks flow bit 1
Supply voltage terminal
4/26
STP24DP05
Electrical ratings
2
Electrical ratings
2.1
Absolute maximum ratings
Stressing the device above the rating listed in the “absolute maximum ratings” table may
cause permanent damage to the device. These are stress ratings only and operation of the
device at these or any other conditions above those indicated in the operating sections of
this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability. Refer also to the STMicroelectronics SURE
program and other relevant quality documents.
Table 4.
Symbol
Absolute maximum ratings
Parameter
Value
Unit
VDD
VO
Supply voltage - digital
0 to 7
V
V
Output voltage - LED driver
-0.5 to 20
V
TF and
VER
Open drain absolute voltage
0 to 7
V
IO
VI
Output current - LED driver
Input voltage - digital
GND terminal current
Clock frequency
80
-0.4 to VDD+0.4
2000
mA
V
IGND
fCLK
mA
MHz
30
2.2
Thermal data
Table 5.
Symbol
Thermal data
Parameter
Value
Unit
TOPR
TSTG
RthJC
Operating temperature range
Storage temperature range
-40 to 125
-40 to 150
25
°C
°C
Thermal resistance junction-case
°C/W
5/26
Electrical ratings
STP24DP05
2.3
Recommended operating conditions
Table 6.
Symbol
Recommended operating conditions
Parameter
Test conditions
Min
Typ
Max
Unit
VDD
VO
Supply voltage
Output voltage
Output current
Output current
Output current
Input voltage
3.0
5.5
20
80
V
V
IO
OUTn
5
mA
mA
mA
V
IOH
SERIAL-OUT
SERIAL-OUT
+10
-10
IOL
VIH
0.7VDD
-0.3
15
VDD+0.3
0.3VDD
VIL
Input voltage
V
twLAT
twCLK
twEN
LE pulse width
CLK pulse width
OE pulse width
ns
15
ns
ns
150
15
VDD = 3.0 V to 5.0 V
Cascade operation (1)
tSETUP(D) Setup time for DATA
tHOLD(D) Hold time for DATA
tSETUP(L) Setup time for LATCH
ns
ns
5
10
ns
fCLK
Clock frequency
25
MHz
1. If the device is connected in cascade, it may not be possible achieve the maximum data transfer. Please
consider the timings carefully.
6/26
STP24DP05
Electrical characteristics
3
Electrical characteristics
Table 7.
Symbol
Electrical characteristics
(V = 3.3 V to 5 V, T = 25 °C, unless otherwise specified.)
DD
Parameter
Test conditions
Min
Typ
Max
Unit
VIH
VIL
IOH
Input voltage high level
Input voltage low level
Output leakage current
0.7VDD
GND
VDD
0.3VDD
10
V
V
VOH = 20 V
OL = 1 mA
µA
Output voltage
(Serial-OUT)
VOL
VOH
IOL1
I
0.4
V
V
Output voltage
(Serial-OUT)
IOH = -1 mA
VDD-0.4V
VO = 0.3 V, REXT = 2 kΩ,
IO = 10 mA
20
80
80
2
mA
mA
mA
%
VO = 0.3 V, REXT = 1 kΩ,
IO = 20 mA
IOL2
Output current
VO = 0.3V, REXT = 250 Ω,
IO = 80 mA
IOL3
VO = 0.3 V, REXT = 2 kΩ,
IO = 10 mA
∆IOL1
∆IOL2
3
3
3
Output current error among
the channels
(All outputs ON)
VO = 0.3 V, REXT = 1 kΩ,
IO = 20 mA
2
%
VO = 0.3V, REXT = 250 Ω,
IO = 80 mA
∆IOL3
2
%
RSIN(up)
Pull-up resistor
300
300
600
400
800
500
kΩ
kΩ
RSIN(down) Pull-down resistor
LE(up)
DG(up)
OE-R\
DM (up)
Pull-up resistor
OE-G (up)
300
400
500
kΩ
OE-B (up)
DF0
DF1
R
EXT = 1 kΩ
IDD(OFF1)
9
12
40
18
40
OUT 0 to 15 = OFF
Supply current (OFF)
IDD(OFF2)
REXT = 250 Ω
OUT 0 to 15 = OFF
32
13
35
mA
REXT = 1 kΩ
IDD(ON1)
OUT 0 to 15 = ON
Supply current (ON)
IDD(ON2)
REXT = 250 Ω
OUT 0 to 15 = ON
7/26
Electrical characteristics
STP24DP05
Table 7.
Symbol
Electrical characteristics
(V = 3.3 V to 5 V, T = 25 °C, unless otherwise specified.)
DD
Parameter
Test conditions
Min
Typ
Max
Unit
Thermal
VTF
Thermal protection
Output voltage
Output current
Output voltage
Output current
170
°C
V
5
5
ITF
VTF @ 1 V
20
20
mA
V
VEF
IEF
VEF @ 1 V
mA
Table 8.
Symbol
Switching characteristics (V = 5 V, T = 25 °C, unless otherwise specified.)
DD
Parameter
Test conditions
Min
Typ
Max Unit
V
DD = 3.3 V
62
38
67
44
65
38
22
14
46
100
ns
Propagation delay time,
CLK-OUTn, LE = H, OE = L
tPLH1
tPLH2
tPLH3
tPLH
VDD = 5 V
VDD = 3.3 V
VDD = 5 V
VDD = 3.3 V
VDD = 5 V
VDD = 3.3 V
VDD = 5 V
60
107
ns
60
Propagation delay time,
LE-OUTn, OE = L
83
ns
45
Propagation delay time,
OE-OUTn, LE = H
14
9
36
ns
23
Propagation delay time,
CLK-SDO
Propagation delay time,
VDD = 3.3 V
70
tPHL1 CLK-OUTn, LE = H,
OE = L
ns
V
DD = 3.3 V
VIH = VDD
CL = 10 pF
VL = 3.0 V
RL = 60 Ω
VDD = 5 V
39
50
VIL = GND
IO = 20 mA
REXT = 1 kΩ
VDD = 3.3 V
VDD = 5 V
51
46
41
33
24
15
33
76
ns
55
Propagation delay time,
tPHL2
LE-OUTn, OE = L
VDD = 3.3 V
VDD = 5 V
45
ns
39
Propagation delay time,
tPHL3
OE-OUTn, LE = H
VDD = 3.3 V
VDD = 5 V
15
9
38
ns
24
Propagation delay time,
CLK-SDO
tPHL
Output rise time
VDD = 3.3 V
57
tON
10~90% of voltage
waveform
ns
VDD = 5 V
VDD = 3.3 V
VDD = 5 V
17
24
25
27
Output fall time
90~10% of voltage
waveform
34
tOFF
ns
37
tr
tf
CLK rise time (1)
CLK fall time (1)
5000
5000
ns
ns
1. In order to achieve high cascade data transfer, please consider tr/tf timings carefully.
8/26
STP24DP05
Block diagram
4
Block diagram
Figure 2. Block diagram
9/26
Equivalent circuit and outputs
STP24DP05
5
Equivalent circuit and outputs
Figure 3. OExx terminal
Figure 4. LE\DM terminal
Figure 5. CLK, SDI terminal
10/26
STP24DP05
Equivalent circuit and outputs
Figure 6. SDO terminal
Figure 7. TF and EF
11/26
Timing diagrams
STP24DP05
6
Timing diagrams
Figure 8. Timing diagram
Note:
The latches circuit holds data when the LE terminal is low.
1
2
3
When LE\DML terminal is at high level, latch circuit hold the data it passes from the input to
the output.
When either OE-R\DM, OE-G, OE-B terminals are at low level, output terminals R\G\B1 to
R\G\B8 respond to the data, either ON or OFF.
When either OE-R\DM, OE-G, OE-B terminals are at high level, it switches off all the data on
the output terminal R\G\B1 to R\G\B8.
12/26
STP24DP05
Timing diagrams
Figure 9. Clock, serial-in, serial-out
13/26
Timing diagrams
Figure 10. Clock, serial-in, latch, enable, outputs
STP24DP05
Figure 11. Outputs
14/26
STP24DP05
Feature description
7
Feature description
7.1
DG: gradual outputs delay
This feature prevents large inrush current and reduces the bypass capacitors.
The fixed delay time can be activated with DG = LOW and the typical output delay is 20 ns
for each group of 8 outputs R, G, B. Eg: R1, G1, B1 has no delay, R2, G2, B2 has 20 ns
delay and R3, G3, B3, has 40 ns delay, etc.
Table 9.
Typical gradual delay time table
R1 R2
R3
R4
R5
R6
R7
R8
Delay time (ns) from ↓OExx
G1 G2 G3 G4 G5 G6 G7 G8
B1 B2
B3
B4
B5
B6
B7
B8
DG = 0
DG = 1
0
30
0
60
0
90 120 150 180 200
0
0
0
0
0
7.2
Error detection condition
Table 10. Detection conditions (V = 3.3 to 5 V, I = 20 mA, t = 25 °C)
DD
O
A
SW-1 Open Open line or output short
or SW-3b to GND detected
No error
detected
=> IODEC ≤ 0.4 x IO
=> IODEC ≥ 0.35 x IO
SW-2
Short on LED or short to
Closed or
No error
detected
=> VO ≥ 2.6 V
=> VO ≤ 2.4 V
V-LED detected
SW-3a
Note:
I = the output current programmed by the R
O EXT
I
= the detected output current in detection mode
ODEC
Table 11. Typical current threshold values to detect LED open line
Iset (mA)
Rext (Ω)
Typ. out current detection (mA)
5
3920
1960
980
1.28
2.45
7.4
17
10
20
50
80
386
241
27
15/26
Feature description
Figure 12. Detection circuit
STP24DP05
23
24
STP24DP05
7.3
Phase one: “entering in detection mode”
From the “normal mode” condition the device can switch to the “error detection mode“ by a
DM PIN set to LOW or a logic sequence on the OE-R/DM and LE/DM pins as showed in the
following table and diagram:
Figure 13. EDM timing diagram using DM pin
Table 12. SPI sequence to enter in detection mode - truth table
CLK
1°
H
L
2°
L
3°
H
L
4°
H
5°
H
L
OE-R/DM
LE/DM
L
H
16/26
STP24DP05
Feature description
Figure 14. SPI sequence to enter in detection mode - time diagram
OE-R/DM
LE/DM
th
After these five CLK cycles the device goes into the “error detection mode“ and at the 6
rise front of CLK the SDI data are ready for the sampling.
7.4
Phase two: “error detection”
The eight data bits must be set “1“ in order to set ON all the outputs during the detection.
The data are latched by LE/DM and after that the outputs are ready for the detection
process. When the micro controller switches the OE-R/DM to LOW, the device drives the
LEDs in order to analyze if an OPEN or SHORT condition has occurred.
Figure 15. Detection diagram
The LEDs status will be detected at least in 1 microsecond and after this time the
microcontroller sets OE-R/DM in HIGH state and the output data detection result will go to
the microprocessor via SDO.
Detection mode and normal mode use both the same format data. As soon as all the
detection data bits are available on the serial line, the device may go back to normal mode
of operation.
17/26
Feature description
STP24DP05
7.5
Phase three: “resuming to normal mode”
In order to re-enter in normal mode either the LE\DML pin or the sequence showed in the
following table and diagram can be used:
Table 13. SPI sequence to resume in normal mode - truth table
CLK
1°
H
L
2°
L
3°
H
L
4°
H
L
5°
H
L
OE-R/DM
LE/DM
L
Note:
For proper device operation the "entering in detection" sequence must be followed by a
"resume mode" sequence, it is not possible to insert consecutive equal sequence.
7.6
Shift registers data flow control
The 8x3 shift registers have a default RGB sequence serial data flow as showed on block
diagram Figure 2.
The data can be redirected by DF0 and DF1 pins, these pins change the order of the data
flow according to the following table:
Table 14. Shifter register data flow control
Sequence
DF0
DF1
BGR
BGR
RGB
GBR
1
0
1
0
1
1
0
0
18/26
STP24DP05
Feature description
7.7
EFLAG/TFLAG - output detection and overtemperature
monitoring
The open-drain output EFLAG and TFLAG are used to report the STP24DP05 error flags.
During normal operating conditions, the voltage on EFLAG/TFLAG is pulledup through an
external resistor. When an error is detected, the internal switch is turned on, to GND.
Figure 16. TF and EF test circuit
19/26
Typical application schematic
STP24DP05
8
Typical application schematic
Figure 17. Typical application schematic
20/26
STP24DP05
Typical characteristics
9
Typical characteristics
Figure 18. Typical external resistor values vs output current capabilities
4500
4000
3500
Temp. = 25°C
3000
2500
2000
1500
1000
500
Vdd = 5.0V
Iset = 5mA; 10mA; 20mA; 50mA; 80mA
0
0
10
20
30
40
50
60
70
80
90
Output Current (mA)
Table 15. Typical external resistor values vs output current capabilities
Iset
5 mA
10 mA
20 mA
50 mA
80 mA
249
Rext (Ω)
4210
2050
1000
400
Figure 19. Typical dropout voltage vs output current
Table 16. Typical dropout voltage vs output current
Iset
Rext (Ω)
Avg (mV) @ 3.3 V
Avg (mV) @ 5.0 V
5
4210
2050
1000
400
59
41
90
10
20
50
80
130
201
500
810
180
480
790
249
21/26
Package mechanical data
STP24DP05
10
Package mechanical data
In order to meet environmental requirements, ST offers these devices in ECOPACK®
packages. These packages have a lead-free second level interconnect. The category of
second level interconnect is marked on the package and on the inner box label, in
compliance with JEDEC Standard JESD97. The maximum ratings related to soldering
conditions are also marked on the inner box label. ECOPACK is an ST trademark.
ECOPACK specifications are available at: www.st.com
22/26
STP24DP05
Package mechanical data
Figure 20. TQFP48 mechanical data
TQFP48 MECHANICAL DATA
mm.
TYP
inch
DIM.
MIN.
MAX.
1.6
MIN.
TYP.
MAX.
0.063
0.006
0.057
0.011
0.0079
A
A1
A2
B
0.05
1.35
0.17
0.09
0.15
1.45
0.27
0.20
0.002
0.053
0.007
0.0035
1.40
0.22
0.055
0.009
C
D
9.00
7.00
5.50
0.50
9.00
7.00
5.50
0.60
1.00
3.5˚
0.354
0.276
0.216
0.020
0.354
0.276
0.216
0.024
0.039
3.5˚
D1
D3
e
E
E1
E3
L
0.45
0˚
0.75
7˚
0.018
0˚
0.030
7˚
L1
K
0110596/C
23/26
Package mechanical data
Figure 21. TQFP48 tape and reel
Tape & Reel TQFP48 MECHANICAL DATA
STP24DP05
mm.
TYP
inch
TYP.
DIM.
MIN.
MAX.
330
MIN.
MAX.
12.992
0.519
A
C
12.8
20.2
60
13.2
0.504
0.795
2.362
D
N
T
22.4
9.7
0.882
0.382
0.382
0.091
0.161
0.476
Ao
Bo
Ko
Po
P
9.5
9.5
0.374
0.374
0.083
0.153
0.468
9.7
2.1
2.3
3.9
4.1
11.9
12.1
24/26
STP24DP05
Revision history
11
Revision history
Table 17. Document revision history
Date
Revision
Changes
19-Apr-2008
1
First release
25/26
STP24DP05
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