STR710FR2H1_技术文档

STR71xF

ARM7TDMI™ 32-bit MCU with Flash, USB, CAN

5 timers, ADC, 10 communications interfaces

Features

■ Core

– ARM7TDMI 32-bit RISC CPU

– 59 MIPS @ 66 MHz from SRAM

– 45 MIPS @ 50 MHz from Flash

LQFP64

10 x 10

LQFP144

20 x 20

■ Memories

– Up to 256 Kbytes Flash program memory

(10 kcycles endurance, 20 years retention

@ 85° C)

– 16 Kbytes Flash data memory

(100 kcycles endurance, 20 years

retention@ 85° C)

– Up to 64 Kbytes RAM

– External Memory Interface (EMI) for up to 4

banks of SRAM, Flash, ROM

L^LF^FB^BG^GAA⁶6⁴4⁸8^xx⁸8^xx^1.1⁷.7

LFBGA144 10 x 10 x 1.7

■ 5 Timers

– 16-bit watchdog timer

– 3 16-bit timers with 2 input captures, 2

output compares, PWM and pulse counter

– 16-bit timer for timebase functions

– Multi-boot capability

■ 10 communications interfaces

■ Clock, reset and supply management

– 3.0 to 3.6V application supply and I/Os

– Internal 1.8V regulator for core supply

– Clock input from 0 to 16.5 MHz

2

– 2 I C interfaces (1 multiplexed with SPI)

– 4 UART asynchronous serial interfaces

– Smartcard ISO7816-3 interface on UART1

– 2 BSPI synchronous serial interfaces

– CAN interface (2.0B Active)

– USB Full Speed (12 Mbit/s) Device

Function with Suspend and Resume

– Embedded RTC osc. running from external

32 kHz crystal

– Embedded PLL for CPU clock

– Realtime Clock for clock-calendar function

– 5 power saving modes: SLOW, WAIT,

LPWAIT, STOP and STANDBY modes

– HDLC synchronous communications

■ 4-channel 12-bit A/D converter

– Sampling frequency up to 1 kHz

– Conversion range: 0 to 2.5 V

■ Nested interrupt controller

– Fast interrupt handling with multiple vectors

– 32 vectors with 16 IRQ priority levels

– 2 maskable FIQ sources

■ Development tools support

– Atomic bit SET and RES operations

■ Up to 48 I/O ports

Table 1.

Device summary

Root part number

– 30/32/48 multifunctional bidirectional I/Os

Up to 14 ports with interrupt capability

Reference

STR710FZ1, STR710FZ2,

STR711FR0, STR711FR1, STR711FR2,

STR712FR0, STR712FR1, STR712FR2,

STR715FR0

STR71xF

February 2008

Rev 12

1/78

www.st.com

78

Contents

STR71xF

Contents

1

2

3

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

System architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

3.1

3.2

3.3

3.4

3.5

3.6

3.7

On-chip peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Related documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Pin description for 144-pin packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Pin description for 64-pin packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

External connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

I/O port configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

4

Electrical parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

4.1

Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

4.1.1

4.1.2

4.1.3

4.1.4

4.1.5

Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

4.2

4.3

Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

4.3.1

4.3.2

4.3.3

4.3.4

4.3.5

4.3.6

4.3.7

4.3.8

4.3.9

Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Clock and timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

I/O port pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

TIM timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

EMI - external memory interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

I2C - inter IC control interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

BSPI - buffered serial peripheral interface . . . . . . . . . . . . . . . . . . . . . . . 63

4.3.10 USB characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

4.3.11 ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

2/78

STR71xF

Contents

5

Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

5.1

5.2

Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

6

7

Product history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

8

Note:

For detailed information on the STR71x Microcontroller memory, registers and peripherals,

please refer to the STR71x Reference Manual.

3/78

Introduction

STR71xF

1

Introduction

This datasheet provides the STR71x pinout, ordering information, mechanical and electrical

device characteristics.

For complete information on the STR71x microcontroller memory, registers and peripherals.

please refer to the STR71x reference manual.

For information on programming, erasing and protection of the internal Flash memory

please refer to the STR7 Flash programming reference manual.

For information on the ARM7TDMI core please refer to the ARM7TDMI technical reference

manual.

Table 2.

Features

Device overview

STR710

FZ1

STR710

FZ2

STR710

RZ

STR711

FR0

STR711

FR1

STR711

FR2

STR712

FR0

STR712

FR1

STR712

FR2

STR715

FRx

Flash - Kbytes 128+16 256+16

0

64+16 128+16 256+16 64+16 128+16 256+16 64+16

RAM - Kbytes

32

64

16

32

64

16

32

64

16

Peripheral

Functions

CAN, EMI, USB, 48 I/Os

USB, 30 I/Os

CAN, 32 I/Os

32 I/Os

Operating

Voltage

3.0 to 3.6 V

Operating

Temperature

-40 to +85°C or 0 to 70° C

T=LQFP144 20 x 20

H=LFBGA144 10 x10

Packages

.

T=LQFP64 10 x10 / H=LFBGA64 8 x 8 x 1.7

4/78

STR71xF

Description

2

Description

®

ARM core with embedded Flash and RAM

The STR71x series is a family of ARM-powered 32-bit microcontrollers with embedded

Flash and RAM. It combines the high performance ARM7TDMI CPU with an extensive

range of peripheral functions and enhanced I/O capabilities. STR71xF devices have on-chip

high-speed single voltage FLASH memory and high-speed RAM. STR710R devices have

high-speed RAM but no internal Flash. The STR71x family has an embedded ARM core and

is therefore compatible with all ARM tools and software.

Extensive tools support

STMicroelectronics’ 32-bit, ARM core-based microcontrollers are supported by a complete

range of high-end and low-cost development tools to meet the needs of application

developers. This extensive line of hardware/software tools includes starter kits and complete

development packages all tailored for ST’s ARM core-based MCUs. The range of

development packages includes third-party solutions that come complete with a graphical

development environment and an in-circuit emulator/programmer featuring a JTAG

application interface. These support a range of embedded operating systems (OS), while

several royalty-free OSs are also available.

For more information, please refer to ST MCU site http://www.st.com/mcu

5/78

System architecture

STR71xF

3

System architecture

Package choice: low pin-count 64-pin or feature-rich 144-pin LQFP or BGA

The STR71x family is available in 5 main versions.

The 144-pin versions have the full set of all features including CAN, USB and External

Memory Interface (EMI).

●

STR710F: 144-pin BGA or LQFP with CAN, USB and EMI

●

STR710R: Flashless 144-pin BGA or LQFP with CAN, USB and EMI (no internal Flash

memory)

The three 64-pin versions (BGA or LQFP) do not include External Memory Interface.

●

STR715F: 64-pin BGA or LQFP without CAN or USB

STR711F: 64-pin BGA or LQFP with USB

STR712F: 64-pin BGA or LQFP with CAN

High speed Flash memory (STR71xF)

The Flash program memory is organized in two banks of 32-bit wide Burst Flash memories

enabling true read-while-write (RWW) operation. Device Bank 0 is up to 256 Kbytes in size,

typically for the application program code. Bank 1 is 16 Kbytes, typically used for storing

data constants. Both banks are accessed by the CPU with zero wait states @ 33 MHz

Bank 0 memory endurance is 10K write/erase cycles and Bank 1 endurance is 100K

write/erase cycles. Data retention is 20 years at 85°C on both banks. The two banks can be

accessed independently in read or write. Flash memory can be accessed in two modes:

●

Burst mode: 64-bit wide memory access at up to 50 MHz.

●

Direct 32-bit wide memory access for deterministic operation at up to 33 MHz.

The STR7 embedded Flash memory can be programmed using In-Circuit Programming or

In-Application programming.

IAP (in-application programming): The IAP is the ability to re-program the Flash memory

of a microcontroller while the user program is running.

ICP (in-circuit programming): The ICP is the ability to program the Flash memory of a

microcontroller using JTAG protocol while the device is mounted on the user application

board.

The Flash memory can be protected against different types of unwanted access

(read/write/erase). There are two types of protection:

●

Sector Write Protection

●

Flash Debug Protection (locks JTAG access)

Refer to the STR7 Flash Programming Reference manual for details.

Optional external memory (STR710)

The non-multiplexed 16-bit data/24-bit address bus available on the STR710 (144-pin)

supports four 16-Mbyte banks of external memory. Wait states are programmable

individually for each bank allowing different memory types (Flash, EPROM, ROM, SRAM

etc.) to be used to store programs or data.

Figure 1 shows the general block diagram of the device family.

6/78

STR71xF

System architecture

Flexible power management

To minimize power consumption, you can program the STR71x to switch to SLOW, WAIT,

LPWAIT (low power wait), STOP or STANDBY mode depending on the current system

activity in the application.

Flexible clock control

Two external clock sources can be used, a main clock and a 32 kHz backup clock. The

embedded PLL allows the internal system clock (up to 66 MHz) to be generated from a main

clock frequency of 16 MHz or less. The PLL output frequency can be programmed using a

wide selection of multipliers and dividers. The microcontroller core, APB1 and APB2

peripherals are in separate clock domains and can be programmed to run at different

frequencies during application runtime. The clock to each peripheral is gated with an

individual control bit to optimize power usage by turning off peripherals any time they are not

required.

Voltage regulators

The STR71x requires an external 3.0-3.6V power supply. There are two internal Voltage

Regulators for generating the 1.8V power supply for the core and peripherals. The main VR

is switched off during low power operation.

Low voltage detectors

Both the Main Voltage Regulator and the Low Power Voltage Regulator contain each a low

voltage detection circuitry which keep the device under reset when the corresponding

controlled voltage value (V or V

) falls below 1.35V (+/- 10%). This enhances the

18

18BKP

security of the system by preventing the MCU from going into an unpredictable state.

An external reset circuit must be used to provide the RESET at V power-up. It is not

33

sufficient to rely on the RESET generated by the LVD in this case. This is because LVD

operation is guaranteed only when V is within the specification.

33

3.1

On-chip peripherals

CAN interface (STR710 and STR712)

The CAN module is compliant with the CAN specification V2.0 part B (active). The bit rate

can be programmed up to 1 MBaud.

USB interface (STR710 and STR711)

The full-speed USB interface is USB V2.0 compliant and provides up to 16 bidirectional/32

unidirectional endpoints, up to 12 Mb/s (full-speed), support for bulk transfer, isochronous

transfers and USB Suspend/Resume functions.

Standard timers

Each of the four timers have a 16-bit free-running counter with 7-bit prescaler

Three timers each provide up to two input capture/output compare functions, a pulse

counter function, and a PWM channel with selectable frequency.

The fourth timer is not connected to the I/O ports. It can be used by the application software

for general timing functions.

7/78

System architecture

Realtime clock (RTC)

STR71xF

The RTC provides a set of continuously running counters driven by the 32 kHz external

crystal. The RTC can be used as a general timebase or clock/calendar/alarm function.

When the STR71x is in Standby mode the RTC can be kept running, powered by the low

power voltage regulator and driven by the 32 kHz external crystal.

UARTs

The 4 UARTs allow full duplex, asynchronous, communications with external devices with

independently programmable TX and RX baud rates up to 1.25 Mb/s.

Smartcard interface

UART1 is configurable to function either as a general purpose UART or as an asynchronous

Smartcard interface as defined by ISO 7816-3. It includes Smartcard clock generation and

provides support features for synchronous cards.

Buffered serial peripheral interfaces (BSPI)

Each of the two SPIs allow full duplex, synchronous communications with external devices,

master or slave communication at up to 5.5 Mb/s in Master mode and 4 Mb/s in Slave mode.

2

I C interfaces

2

The two I C Interfaces provide multi-master and slave functions, support normal and fast

2

I C mode (400 kHz) and 7 or 10-bit addressing modes.

2

One I C Interface is multiplexed with one SPI, so either 2xSPI+1x I C or 1xSPI+2x I C may

be used at a time.

HDLC interface

The High Level Data Link Controller (HDLC) unit supports full duplex operation and NRZ,

NRZI, FM0 or MANCHESTER protocols. It has an internal 8-bit baud rate generator.

A/D converter

The Analog to Digital Converter, converts in single channel or up to 4 channels in single-

shot or round robin mode. Resolution is 12-bit with a sampling frequency of up to 1 kHz. The

input voltage range is 0-2.5V.

Watchdog

The 16-bit Watchdog Timer protects the application against hardware or software failures

and ensures recovery by generating a reset.

I/O ports

The 48 I/O ports are programmable as Inputs or Outputs.

External interrupts

Up to 14 external interrupts are available for application use or to wake up the application

from STOP mode.

8/78

STR71xF

System architecture

Figure 1.

STR71x block diagram

A[19:0]

D[15:0]

RDN

A[23:20] (AF)

CS[3:0)

WEN[1:0]

CK

CKOUT

RSTIN

PRCCU/PLL

EXT. MEM.

INTERFACE (EMI)

FLASH*

ARM7TDMI

CPU

Program Memory

64/128/256K

JTDI

JTCK

JTMS

16K Data FLASH*

JTRST

JTDO

JTAG

RAM

DBGRQS

16/32/64K

BOOTEN

APB

BRIDGE 1

V18[1:0]

V33[6:0]

VSS[9:0]

V18BKP

AVDD

POWER SUPPLY

VREG

APB

BRIDGE 2

AVSS

2 AF

4 AF

2 AF

I2C0

I2C1

INTERRUPT CTL(EIC)

A/D

BSPI0

BSPI1

UART0

4 AF

TIMER0

4 AF

2 AF

4 AF

TIMER1

UART1 /

SMARTCARD

3 AF

2 AF

3 AF

TIMER2

UART2

UART3

HDLC

TIMER3

STDBY

RTCXTO

RTCXTI

OSC

RTC

WAKEUP

14 AF

EXT INT (XTI)

WATCHDOG

USBDP

USBDN

USB

CAN

1 AF

P0[15:0]

P1[15:0]

P2[15:0]

I/O PORT 0

I/O PORT 1

I/O PORT 2

2 AF

AF: alternate function on I/O port pin

*Flash present in STR710F, not in STR710R

9/78

System architecture

STR71xF

3.2

Related documentation

Available from www.arm.com:

ARM7TDMI Technical reference manual

Available from http://www.st.com:

STR71x Reference manual

STR7 Flash programming manual

AN1774 - STR71x Software development getting started

AN1775 - STR71x Hardware development getting started

AN1776 - STR71x Enhanced interrupt controller

AN1777 - STR71x memory mapping

AN1780 - Real time clock with STR71x

AN1781 - Four 7 segment display drive using the STR71x

The above is a selected list only, a full list STR71x application notes can be viewed at

http://www.st.com.

10/78

STR71xF

System architecture

3.3

Pin description for 144-pin packages

Figure 2.

STR710 LQFP pinout

P0.10/U1.RX/U1.TX/SCDATA

1

108

107

106

105

104

103

102

101

100

99

P1.14/HRXD/I0.SDA

RDn

P0.11/U1.TX/BOOT.1

P0.12/SCCLK

VSS

2

P1.13/HCLK/I0.SCL

3

P1.10/USBCLK

4

P1.9

5

V33

6

VSS

P2.0/CSn.0

P2.1/CSn.1

7

A.4

8

A.3

P0.13/U2.RX/T2.OCMPA

P0.14/U2.TX/T2.ICAPA

P2.2/CSn.2

P2.3/CSn.3

P2.4/A.20

P2.5/A.21

P2.6/A.22

BOOTEN

P2.7/A.23

P2.8

9

A.2

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

A.1

98

A.0

97

D.15

96

D.14

LQFP144

95

D.13

94

D.12

93

D.11

92

D.10

91

USBDN

N.C.

90

USBDP

N.C.

89

P1.12/CANTX

P1.11/CANRX

N.C.

VSS

88

V33

87

P2.9

86

P1.8

P2.10

85

P1.7/T1.OCMPA

VSSIO-PLL

V33IO-PLL

D.9

P2.11

84

P2.12

83

P2.13

82

P2.14

81

D.8

P2.15

80

D.7

JTDI

79

D.6

JTMS

78

D.5

JTCK

77

P1.6/T1.OCMPB

P1.5/T1.ICAPB

P1.4/T1.ICAPA

P1.3/T3.ICAPB/AIN.3

P1.2/T3.OCMPA/AIN.2

JTDO

76

JTRSTn

NU

75

74

TEST

73

11/78

System architecture

Table 3.

STR71xF

STR710 BGA ball connections

A

B

C

D

E

F

G

H

J

K

L

M

BOOT

EN

1

2

3

4

5

P0.10

VSS

V33

P2.0

P2.1

VSS

P2.2

P2.6

P2.12

P2.13

P2.15

JTDI

TEST

N.C.

JTRST

n

RDn

P0.9

P0.11

P0.12

P0.8

V33

P0.13

P0.14

P0.5

P2.3

P2.4

P2.5

P2.7

P2.8

N.C.

VSS

P2.9

P2.10

P2.11

P2.14

JTMS

JTCK

JTDO

N.C.

TEST

V33

DBG

RQS

NU

CK

VSSIO-

PLL

P0.6

A.19

P0.7

CKOUT

RTCXTI

N.C.

P0.15

STDBY

RTCX-

TO

WEn.1

WEn.0

N.C.

V18BK

P

VSS

BKP

6

7

8

P0.3

P0.2

A.9

A.15

P0.1

A.10

A.16

P0.4

A.11

A.17

VSS18

A.13

A.18

V18

V33

A.14

A.0

V18

D.12

D.11

N.C.

D.1

N.C.

D.0

nc

VSS18 RSTIN

P1.12/

CANTX

P0.0

N.C.

AVSS

D.3

D.2

9

VSS

A.8

V33

N.C.

A.5

A.6

V33

VSS

A.2

D.15

D.14

D.13

D.10

P1.8

P1.7

VSS

D.9

D.8

D.5

P1.0

P1.5

P1.4

N.C.

P1.1

P1.3

N.C.

D.4

10

11

P1.15

P1.14

P1.13

P1.10

USBDN

USBDP

A.7

AVDD

P1.11/

CANRX

V33IO-

PLL

12

A.12

A.4

A.3

P1.9

A.1

N.C.

P1.6

D.7

D.6

P1.2

Legend / abbreviations for Table 4:

Type: I = input, O = output, S = supply, HiZ= high impedance,

In/Output level: C = CMOS 0.3V /0.7V

DD

C = CMOS 0.3V /0.7V with input trigger

T

DD

T = TTL 0.8 V/2 V with input trigger

T

C/T = Programmable levels: CMOS 0.3V /0.7V or TTL 0.8 V / 2 V

DD

Port and control configuration:

Input:

pu/pd= software enabled internal pull-up or pull down

pu= in reset state, the internal 100kΩ weak pull-up is enabled.

pd = in reset state, the internal 100kΩ weak pull-down is enabled.

Output:

OD = open drain (logic level)

PP = push-pull

T = true OD, (P-Buffer and protection diode to V not implemented),

DD

5 V tolerant.

12/78

STR71xF

System architecture

Table 4.

Pin n°

STR710 pin description

Input

Output

Main

function

(after

Pin name

Alternate function

reset)

UART1:

Receive Data

input

UART1: Transmit

data output.

Note: This pin may be used for

Smartcard DataIn/DataOut or single

wire UART (half duplex) if

P0.10/U1.RX/

SC.DATA

1

A1 U1.TX/

I/O pd C_TX 4mA

T

Port 0.10

programmed as Alternate Function

Output. The pin will be tri-stated

except when UART transmission is in

progress

External Memory Interface: Active low read signal

for external memory. It maps to the OE_N input of

the external components.

5)

2

3

B2 RD

O

X

Select Boot

UART1: Transmit

Port 0.11 Configuration

data output.

P0.11/BOOT.1

/U1.TX

C2

I/O pd C_T

4mA

X

input

4

5

6

C3 P0.12/SC.CLK I/O pd C_T

Port 0.12 Smartcard reference clock output

Ground voltage for digital I/Os⁴⁾

D1 V_SS

D2 V₃₃

S

Supply voltage for digital I/Os⁴⁾

External Memory Interface: Select

Memory Bank 0 output

8)

7

B1 P2.0/CS.0

C1 P2.1/CS.1

I/O

C_T

8mA

X

Port 2.0

Port 2.1

Note: This pin is forced to output

push-pull 1 mode at reset to allow

boot from external memory

pu

External Memory Interface: Select

Memory Bank 1 output

8

9

X

2)

UART2:

Port 0.13 Receive Data

input

P0.13/U2.RX/

Timer2: Output

Compare A output

D3

I/O pu C_TX 4mA

T2.OCMPA

UART2:

Port 0.14 Transmit data

output

P0.14/U2.TX/

T2.ICAPA

Timer2: Input

Capture A input

10 D4

I/O pu C_T

pu

4mA

X

External Memory Interface: Select

Memory Bank 2 output

11 E1 P2.2/CS.2

12 E2 P2.3/CS.3

I/O

C_T

8mA

X

Port 2.2

Port 2.3

2)

pu

External Memory Interface: Select

Memory Bank 3 output

I/O

C_T

2)

13/78

System architecture

STR71xF

Table 4.

Pin n°

STR710 pin description

Input

Output

Main

function

(after

Pin name

Alternate function

reset)

pd

13 E3 P2.4/A.20

14 E4 P2.5/A.21

15 F1 P2.6/A.22

16 G1 BOOTEN

17 E5 P2.7/A.23

I/O

I

C_T

8mA

X

Port 2.4

Port 2.5

Port 2.6

3)

pd

External Memory Interface: address

bus

8mA

3)

pd

3)

Boot control input. Enables sampling of

BOOT[1:0] pins

pd

External Memory Interface: address

I/O

8mA

X

Port 2.7

bus

3)

18 F2 P2.8

19 F3 N.C.

20 F4 N.C.

21 F5 V_SS

22 F6 V₃₃

23 G2 P2.9

24 G3 P2.10

25 G4 P2.11

26 H1 P2.12

I/O pu C_TX 4mA

Port 2.8 External interrupt INT2

Not connected (not bonded)

Ground voltage for digital I/Os⁴⁾

Supply voltage for digital I/Os⁴⁾

Port 2.9 External interrupt INT3

Port 2.10 External interrupt INT4

Port 2.11 External interrupt INT5

Port 2.12

S

I/O pu C_TX 4mA

X

I/O pu C_T

4mA

27

J1 P2.13

Port 2.13

28 G5 P2.14

29 K1 P2.15

30 L1 JTDI

Port 2.14

Port 2.15

I

T_T

JTAG Data input. External pull-up required.

JTAG Mode Selection Input. External pull-up

required.

31 H2 JTMS

JTAG Clock Input. External pull-up or pull-down

required.

32 H3 JTCK

33 H4 JTDO

I

C

O

I

8mA

X

JTAG Data output. Note: Reset state = HiZ.

JTAG Reset Input. External pull-up required.

Reserved, must be forced to ground.

Not connected (not bonded)

34

35

J2 JTRST

J3 NU

T_T

36 K2 TEST

37 M1 N.C.

38 L2 TEST

39 L3 N.C.

Reserved, must be forced to ground.

Not connected (not bonded)

14/78

STR71xF

System architecture

Table 4.

Pin n°

STR710 pin description

Input

Output

Main

function

(after

Pin name

Alternate function

reset)

Supply voltage for digital I/O circuitry and for PLL

reference

40 K3 V_33IO-PLL

41 M4 N.C.

S

Not connected (not bonded)

Ground voltage for digital I/O circuitry and for PLL

reference⁴⁾

42 L4 V_SSIO-PLL

43 M2 N.C.

Not connected (not bonded)

44 M3 DBGRQS

I

O

I

C_T

Debug Mode request input (active high)

Clock output (f_PCLK2) Note: Enabled by CKDIS

register in APB Bridge 2

45 K4 CKOUT

8mA

X

46

J4 CK

C

Reference clock input

Port 0.15 Wakeup from Standby mode input.

Note: This port is input only.

Not connected (not bonded)

P0.15/

WAKEUP

47 M5

I

T_T

X

48 L5 N.C.

Realtime Clock input and input of 32 kHz

oscillator amplifier circuit

49 K5 RTCXTI

50

J5 RTCXTO

Output of 32 kHz oscillator amplifier circuit

Input: Hardware Standby mode entry input active

low. Caution: External pull-up to V₃₃required to

select normal mode.

51 M6 STDBY

I/O

I

C_T

4mA

X

Output: Standby mode active low output following

Software Standby mode entry.

Note: In Standby mode all pins are in high

impedance except those marked Active in Stdby

52 M7 RSTIN

53 H5 N.C.

C_T

S

X

Reset input

Not connected (not bonded)

Stabilization for low power voltage regulator.

54 L6 V_SSBKP

Stabilization for low power voltage regulator.

Requires external capacitors of at least 1µF

between V_18BKPand V_SS18BKP. See Figure 5.

Note: If the low power voltage regulator is

bypassed, this pin can be connected to an

external 1.8V supply.

55 K6 V_18BKP

S

X

56

J6 N.C.

Not connected (not bonded)

57 H6 N.C.

Stabilization for main voltage regulator. Requires

external capacitors of at least 10µF + 33nF

between V₁₈and V_SS18. See Figure 5.

58 G6 V₁₈

S

15/78

System architecture

STR71xF

Table 4.

Pin n°

STR710 pin description

Input

Output

Main

function

(after

Pin name

Alternate function

reset)

59 L7 V_SS18

60 K7 N.C.

S

Stabilization for main voltage regulator.

Not connected (not bonded)

6)

61

J7 D.0

I/O

S

8mA

62 H7 D.1

63 M8 D.2

64 L8 D.3

65 M10 D.4

66 M11 V_DDA

67 K8 V_SSA

8mA

External Memory Interface: data bus

Supply voltage for A/D Converter

Ground voltage for A/D Converter

Not connected (not bonded)

Timer 3:

S

68

J8 N.C.

69 M9 N.C.

70 L9 N.C.

P1.0/T3.OCM

PB/AIN.0

71 K9

I/O pu C_T

4mA

X

Port 1.0 Output

Compare B

ADC: Analog input 0

Timer 3: Input

Capture A or

External Clock

input

P1.1/T3.ICAP

72 L10 A/T3.EXTCLK/ I/O pu C_T

AIN.1

Port 1.1

ADC: Analog input 1

Timer 3:

P1.2/T3.OCM

PA/AIN.2

73 M12

I/O pu C_T

Port 1.2 Output

Compare A

ADC: Analog input 2

ADC: Analog input 3

P1.3/T3.ICAP

B/AIN.3

Timer 3: Input

Capture B

74 L11

75 K11

76 K10

I/O pu C_T

4mA

X

Port 1.3

Port 1.4

Port 1.5

P1.4/T1.ICAP

A/T1.EXTCLK

Timer 1: Input Timer 1: External

Capture A

Clock input

P1.5/T1.ICAP

B

Timer 1: Input

Capture B

Timer 1:

Port 1.6 Output

Compare B

P1.6/T1.OCM

PB

77 J12

I/O pu C_T

4mA

X

6)

78 J11 D.5

79 L12 D.6

80 K12 D.7

81 J10 D.8

I/O

8mA

6)

I/O

6)

I/O

External Memory Interface: data bus

6)

I/O

6)

82

J9 D.9

I/O

16/78

STR71xF

System architecture

Table 4.

Pin n°

STR710 pin description

Input

Output

Main

function

(after

Pin name

Alternate function

reset)

Supply voltage for digital I/O circuitry and for PLL

reference⁴⁾

83 H12 V_33IO-PLL

84 H11 V_SSIO-PLL

S

Ground voltage for digital I/O circuitry and for PLL

reference⁴⁾

Timer 1:

Port 1.7 Output

Compare A

P1.7/T1.OCM

PA

85 H10

I/O pu C_T

I/O pd C_T

4mA

X

86 H9 P1.8

87 G12 N.C.

Port 1.8

Not connected (not bonded)

CAN: receive data input

Port 1.11

88 F12 P1.11/CANRX I/O pu C_TX 4mA

X

Note: On STR710 and STR712 only

CAN: Transmit data output

Port 1.12

89 H8 P1.12/CANTX I/O pu C_T

4mA

Note: On STR710 and STR712 only

USB bidirectional data (data +). Reset state = HiZ

Note: On STR710 and STR711 only

90 G11 USBDP

I/O

C_T

This pin requires an external pull-up to V₃₃to

maintain a high level.

USB bidirectional data (data -). Reset state = HiZ

91 G10 USBDN

I/O

Note: On STR710 and STR711 only.

6)

7)

92 G9 D.10

93 G8 D.11

94 G7 D.12

95 F11 D.13

96 F10 D.14

97 F9 D.15

98 F8 A.0

99 E12 A.1

100 E11 A.2

101 C12 A.3

102 B12 A.4

103 E10 V_SS

104 E9 V₃₃

105 D12 P1.9

I/O

O

8mA

External Memory Interface: data bus

X

O

External Memory Interface: address bus

O

S

Ground voltage for digital I/O circuitry⁴⁾

Supply voltage for digital I/O circuitry⁴⁾

Port 1.9

S

I/O pd C_T

4mA

X

P1.10/

106 D11

C/

I/O pd

T

USB: 48 MHZ

Port 1.10

USBCLK

clock input

17/78

System architecture

STR71xF

Table 4.

Pin n°

STR710 pin description

Input

Output

Main

function

(after

Pin name

Alternate function

reset)

HDLC:

Port 1.13 reference

clock input

P1.13/HCLK/

I0.SCL

107 D10

108 C11

I/O pd C_TX 4mA

I/O pu C_TX 4mA

X

I2C clock

HDLC:

P1.14/HRXD/

I0.SDA

Port 1.14 Receive data I2C serial data

input

109 B11 N.C.

110 B10 N.C.

111 C10 P1.15/HTXD

112 A9 V_SS

113 B9 V₃₃

114 C9 A.5

115 D9 A.6

116 A11 A.7

117 A10 A.8

118 A8 A.9

119 B8 A.10

120 C8 A.11

121 A12 A.12

122 D8 A.13

Not connected (not bonded)

I/O pu C_T

4mA

X

Port 1.15 HDLC: Transmit data output

Ground voltage for digital I/O circuitry⁴⁾

Supply voltage for digital I/O circuitry⁴⁾

S

7)

O

8mA

X

7)

O

7)

O

7)

O

7)

O

External Memory Interface: address bus

7)

O

7)

O

7)

O

7)

O

SPI0 Master

in/Slave out

data

UART3Transmit data

output

P0.0/S0.MISO

123 E8

I/O pu C_T

4mA

X

Port 0.0

Note: Programming AF function

selects UART by default. BSPI must

be enabled by SPI_EN bit in the

BOOTCR register.

/U3.TX

BSPI0: Master

UART3: Receive

out/Slave in

Data input

data

P0.1/S0.MOSI

124 B7

I/O pu C_TX 4mA

Port 0.1

Note: Programming AF function

selects UART by default. BSPI must

be enabled by SPI_EN bit in the

BOOTCR register.

/U3.RX

18/78

STR71xF

System architecture

Table 4.

Pin n°

STR710 pin description

Input

Output

Main

function

(after

Pin name

Alternate function

reset)

BSPI0: Serial

Clock

I2C1: Serial clock

P0.2/S0.SCLK

/I1.SCL

Note: Programming AF function

selects I2C by default. BSPI must be

enabled by SPI_EN bit in the

BOOTCR register.

125 A7

I/O pu C_TX 4mA

X

Port 0.2

Port 0.3

SPI0: Slave

Select input

active low.

I2C1: Serial Data

P0.3/S0.SS/

I1.SDA

126 A6

I/O pu C_T

4mA

X

Note: Programming AF function

selects I2C by default. BSPI must be

enabled by SPI_EN bit in the

BOOTCR register.

127 C7 P0.4/S1.MISO I/O pu C_T

Port 0.4 SPI1: Master in/Slave out data

Stabilization for main voltage regulator.

128 D7 V_SS18

S

Stabilization for main voltage regulator. Requires

external capacitors of at least 10µF + 33nF

between V₁₈and V_SS18. See Figure 5.

129 E7 V₁₈

S

7)

130 F7 A.14

131 B6 A.15

132 C6 A.16

133 D6 A.17

134 E6 A.18

135 A5 A.19

O

8mA

X

External Memory Interface: address bus

External Memory Interface: active low MSB write

enable output

5)

136 B5 WE.1

137 C5 WE.0

O

8mA

X

External Memory Interface: active low LSB write

enable output

138 A3 V₃₃

139 A2 V_SS

S

Supply voltage for digital I/Os⁴⁾

Ground voltage for digital I/Os⁴⁾

140 D5 P0.5/S1.MOSI I/O pu C_T

4mA

X

Port 0.5 SPI1: Master out/Slave In data

Port 0.6 SPI1: Serial Clock

141 A4 P0.6/S1.SCLK I/O pu C_TX 4mA

142 B4 P0.7/S1.SS I/O pu C_T4mA

Port 0.7 SPI1: Slave Select input active low

19/78

System architecture

STR71xF

Table 4.

Pin n°

STR710 pin description

Input

Output

Main

function

(after

Pin name

Alternate function

reset)

UART0:

Port 0.8 Receive Data

input

UART0: Transmit

data output.

P0.8/U0.RX/

U0.TX

143 C4

144 B3

I/O pd C_TX 4mA

T

X

Note: This pin may be used for single wire UART

(half duplex) if programmed as Alternate Function

Output. The pin will be tri-stated except when

UART transmission is in progress

Select Boot

UART0: Transmit

Port 0.9 Configuration

data output

P0.9/U0.TX/

BOOT.0

I/O pd C_T

4mA

X

input

1. The Reset configuration of the I/O Ports is IPUPD (input pull-up/pull down). Refer to Table 8 on page 29.

The Port bit configuration at reset is PC0=1, PC1=1, PC2=0. The port data register bit (PD) value depends

on the pu/pd column which specifies whether the pull-up or pull-down is enabled at reset

2. In reset state, these pins configured as Input PU/PD with weak pull-up enabled. They must be configured

by software as Alternate Function (see Table 8: Port bit configuration table on page 29) to be used by the

External Memory Interface.

3. In reset state, these pins configured as Input PU/PD with weak pull-down enabled to output Address

0x0000 0000 using the External Memory Interface. To access memory banks greater than 1Mbyte, they

need to be configured by software as Alternate Function (see Table 8: Port bit configuration table on

page 29).

4. V_33IO-PLLand V₃₃are internally connected. V_SSIO-PLLand V_SSare internally connected.

5. During the reset phase, these pins are in input pull-up state. When reset is released, they are configured as

Output Push-Pull.

6. During the reset phase, these pins are in input pull-up state. When reset is released, they are configured as

Hi-Z.

7. During the reset phase, these pins are in input pull-down state. When reset is released, they are configured

as Output Push-Pull.

8. During the reset phase, this pin is in input floating state. When reset is released, it is configured as Output

Push-Pull.

20/78

STR71xF

System architecture

3.4

Pin description for 64-pin packages

Figure 3.

STR712/STR715 LQFP64 pinout

P0.10/U1.RX/U1.TX/SCDATA

1

2

3

4

5

6

7

8

9

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

P1.14/HRXD/I0.SDA

P1.13/HCLK/I0.SCL

P0.11/U1.TX/BOOT.1

P0.12/SCCLK

VSS

P1.10

P1.9

VSS

P1.12/CANTX

P1.11/CANRX

P0.13/U2.RX/T2.OCMPA

P0.14/U2.TX/T2.ICAPA

1)

BOOTEN

VSS

LQFP64

P1.8

P1.7/T1.OCMPA

VSSIO-PLL

V33

JTDI 10

JTMS 11

JTCK 12

JTDO 13

nJTRST 14

NU 15

V33IO-PLL

P1.6/T1.OCMPB

P1.5/T1.ICAPB

P1.4/T1.ICAPA

P1.3/T3.ICAPB/AIN.3

P1.2/T3.OCMPA/AIN.2

TEST 16

1)

CANTX and CANRX in STR712F only, in STR715F they are general purpose I/Os.

21/78

System architecture

Figure 4.

STR71xF

STR711 LQFP64 pinout

P0.10/U1.RX/U1.TX/SCDATA

1

2

3

4

5

6

7

8

9

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

P1.14/HRXD/I0.SDA

P1.13/HCLK/I0.SCL

P1.10/USBCLK

P1.9

VSS

USBDN

USBDP

P1.8

P1.7/T1.OCMPA

VSSIO-PLL

V33IO-PLL

P1.6/T1.OCMPB

P1.5/T1.ICAPB

P1.4/T1.ICAPA

P1.3/T3.ICAPB/AIN.3

P1.2/T3.OCMPA/AIN.2

P0.11/U1.TX/BOOT.1

P0.12/SCCLK

VSS

P0.13/U2.RX/T2.OCMPA

P0.14/U2.TX/T2.ICAPA

BOOTEN

LQFP64

VSS

V33

JTDI 10

JTMS 11

JTCK 12

JTDO 13

nJTRST 14

NU 15

TEST 16

Table 5.

STR711 BGA ball connections

A

B

C

D

E

F

G

H

V33IO-

PLL

1

2

P0.10

P0.9

P0.11

P0.12

P0.14

V33

JTCK

TEST

P0.15

VSSIO-

PLL

VSS

P0.13

VSS

JTMS

JTRSTn

3

4

5

P0.5

VSS18

P0.2

P0.7

VSS

P0.4

BOOTEN

P0.8

JTDI

JTDO

P0.6

NU

AVDD

P1.9

STDBY

V18BKP

P1.0

RTCXTI

RSTIN

V18

CK

RTCXTO

VSSBKP

V18

VSSIO-

PLL

6

7

8

V33

VSS

P0.1

P0.0

P0.3

P1.10

VSS

P1.13

USBDN

P1.8

USBDP

P1.7

AVSS

P1.5

P1.3

VSS18

P1.1

P1.6

P1.4

V33IO-

PLL

P1.15

P1.14

P1.2

22/78

STR71xF

System architecture

Table 6.

STR712/715 BGA Ball Connections

A

B

C

D

E

F

G

H

V33IO-

PLL

1

2

P0.10

P0.9

P0.11

P0.12

P0.14

V33

JTCK

TEST

VSSIO-

PLL

VSS

P0.13

VSS

JTMS

JTRSTn

P0.15

3

4

5

P0.5

VSS18

P0.2

P0.7

VSS

P0.4

BOOTEN

P0.8

JTDI

JTDO

P0.6

NU

AVDD

P1.9

STDBY

V18BKP

P1.0

RTCXTI

RSTIN

V18

CK

RTCXTO

VSSBKP

V18

P1.11/

VSSIO-

PLL

6

7

8

V33

VSS

P0.1

P0.0

P0.3

P1.10

VSS

P1.13

AVSS

P1.5

P1.3

VSS18

P1.1

CANRX¹⁾

P1.12/

P1.7

P1.6

P1.4

CANTX¹⁾

V33IO-

PLL

P1.15

P1.14

P1.8

P1.2

¹⁾CANTX and CANRX in STR712F only, in STR715F they are general purpose I/Os.

Legend / abbreviations for Table 7:

Type:

I = input, O = output, S = supply, HiZ= high impedance,

In/Output level: C = CMOS 0.3V /0.7V

DD

C = CMOS 0.3V /0.7V with input trigger

T

DD

T = TTL 0.8V / 2V with input trigger

T

C/T = Programmable levels: CMOS 0.3V /0.7V or TTL 0.8V / 2V

DD

Port and control configuration:

Input:

pu/pd= software enabled internal pull-up or pull down

pu= in reset state, the internal 100kΩ weak pull-up is enabled.

pd = in reset state, the internal 100kΩ weak pull-down is enabled.

Output:

OD = open drain (logic level)

PP = push-pull

T = true OD, (P-Buffer and protection diode to V not implemented),

DD

5V tolerant.

23/78

System architecture

STR71xF

Table 7.

Pin n°

STR711/STR712/STR715 pin description

Input Output

Main

function

(after

Pin name

Alternate function

reset)

UART1:

Receive Data

input

UART1: Transmit data

output.

P0.10/U1.RX/

SC.DATA

Note: This pin may be used for

1

2

A1 U1.TX/

I/O pd C_T

X

4mA

T

Port 0.10

Smartcard DataIn/DataOut or single

wire UART (half duplex) if programmed

as Alternate Function Output. The pin

will be tri-stated except when UART

transmission is in progress

Select Boot

Port 0.11 Configuration

input

P0.11/BOOT.1

/U1.TX

UART1: Transmit data

output.

B1

I/O pd C_T

4mA

X

3

4

C1 P0.12/SC.CLK I/O pd C_T

Port 0.12 Smartcard reference clock output

Ground voltage for digital I/Os²⁾

B2 V_SS

S

UART2:

Timer2: Output

Port 0.13 Receive Data

Compare A output

input

P0.13/U2.RX/

T2.OCMPA

5

C2

D1

I/O pu C_T

X

4mA

X

UART2:

Timer2: Input Capture

Port 0.14 Transmit data

A input

P0.14/U2.TX/

T2.ICAPA

6

7

I/O pu C_T

output

Boot control input. Enables sampling of BOOT[1:0]

pins

C3 BOOTEN

I

C_T

8

9

D2 V_SS

E1 V₃₃

S

I

Ground voltage for digital I/Os²⁾

Supply voltage for digital I/Os²⁾

10 D3 JTDI

11 E2 JTMS

T_T

JTAG Data input. External pull-up required.

JTAG Mode Selection Input. External pull-up

required.

I

JTAG Clock Input. External pull-up or pull-down

required.

12 F1 JTCK

C

13 D4 JTDO

14 F2 JTRST

15 E3 NU

O

I

8mA

X

JTAG Data output. Note: Reset state = HiZ.

JTAG Reset Input. External pull-up required.

Reserved, must be forced to ground.

T_T

16 G1 TEST

Reserved, must be forced to ground.

Supply voltage for digital I/O circuitry and for PLL

reference²⁾

17 H1 V_33IO-PLL

S

Ground voltage for digital I/O circuitry and for PLL

reference²⁾

18 H2 V_SSIO-PLL

19 H3 CK

S

I

C

Reference clock input

24/78

STR71xF

System architecture

Table 7.

Pin n°

STR711/STR712/STR715 pin description

Input Output

Main

function

(after

Pin name

Alternate function

reset)

Port 0.15 Wakeup from Standby mode input.

P0.15/

20 G2

I

T_T

X

WAKEUP

Note: This port is input only.

Realtime Clock input and input of 32 kHz oscillator

amplifier circuit

21 G3 RTCXTI

22 H4 RTCXTO

Output of 32 kHz oscillator amplifier circuit

Input: Hardware Standby mode entry input active

low.

Caution: External pull-up to V₃₃required to select

normal mode.

23 F3 STDBY

I/O

C_T

4mA

X

Output: Standby mode active low output following

Software Standby mode entry.

Note: In Standby mode all pins are in high

impedance except those marked Active in Stdby.

24 G4 RSTIN

25 H5 V_SSBKP

I

C_T

S

X

Reset input

Stabilization for low power voltage regulator.

Requires external capacitors of at least 1µF

between V_18BKPand V_SS18BKP. See Figure 5.

Note: If the low power voltage regulator is

bypassed, this pin can be connected to an external

1.8V supply.

26 F4 V_18BKP

S

X

Stabilization for main voltage regulator. Requires

external capacitors of at least 10µF + 33nF

between V₁₈and V_SS18. See Figure 5.

27 G5 V₁₈

S

28 H6 V_SS18

29 E4 V_DDA

30 G6 V_SSA

S

Stabilization for main voltage regulator.

Supply voltage for A/D Converter

Ground voltage for A/D Converter

Timer 3: Output

P1.0/T3.OCM

PB/AIN.0

31 F5

I/O pu C_T

4mA

X

Port 1.0

ADC: Analog input 0

Compare B

Timer 3: Input

Capture A or

External Clock

input

P1.1/T3.ICAP

32 H7 A/T3.EXTCLK I/O pu C_T

/AIN.1

Port 1.1

ADC: Analog input 1

P1.2/T3.OCM

PA/AIN.2

Timer 3: Output

Compare A

33 H8

34 G8

35 F8

I/O pu C_T

4mA

X

Port 1.2

Port 1.3

Port 1.4

ADC: Analog input 2

ADC: Analog input 3

P1.3/T3.ICAP

B/AIN.3

Timer 3: Input

Capture B

P1.4/T1.ICAP

A/T1.EXTCLK

Timer 1: Input Timer 1: External

Capture A Clock input

25/78

System architecture

STR71xF

Table 7.

Pin n°

STR711/STR712/STR715 pin description

Input Output

Main

function

(after

Pin name

Alternate function

reset)

P1.5/T1.ICAP

B

Timer 1: Input

Capture B

36 G7

37 F7

I/O pu C_T

4mA

X

Port 1.5

Port 1.6

P1.6/T1.OCM

PB

Timer 1: Output

Compare B

I/O pu C_T

4mA

Supply voltage for digital I/O circuitry and for PLL

reference²⁾

38 E8 V_33IO-PLL

39 F6 V_SSIO-PLL

P1.7/T1.OCM

S

Ground voltage for digital I/O circuitry and for PLL

reference²⁾

Timer 1: Output

Port 1.7

40 E7

I/O pu C_T

I/O pd C_T

4mA

X

PA

Compare A

41 D8 P1.8

Port 1.8

CAN: receive data input

Port 1.11

42 E6 P1.11/CANRX I/O pu C_T

43 D7 P1.12/CANTX I/O pu C_T

X

Note: On STR710 and STR712 only

CAN: Transmit data output

Port 1.12

4mA

X

Note: On STR710 and STR712 only

USB bidirectional data (data +). Reset state = HiZ

Note: On STR710 and STR711 only

42 E6 USBDP

I/O

C_T

This pin requires an external pull-up to V₃₃to

maintain a high level.

USB bidirectional data (data -). Reset state = HiZ

43 D7 USBDN

I/O

S

Note: On STR710 and STR711 only.

44 C8 V_SS

45 E5 P1.9

Ground voltage for digital I/O circuitry²⁾

I/O pd C_T

4mA

X

Port 1.9

P1.10/USBCL

K

C/

I/O pd

T

USB: 48 MHZ

Port 1.10

46 C7

47 D6

48 B8

clock input

HDLC:

P1.13/HCLK/I

0.SCL

I/O pd C_T

I/O pu C_T

X

4mA

X

Port 1.13 reference clock I2C clock

input

P1.14/HRXD/I

0.SDA

HDLC: Receive

data input

4mA

X

Port 1.14

I2C serial data

49 A8 P1.15/HTXD

50 A7 V_SS

I/O pu C_T

Port 1.15 HDLC: Transmit data output

Ground voltage for digital I/O circuitry²⁾

Supply voltage for digital I/O circuitry²⁾

S

51 A6 V₃₃

26/78

STR71xF

System architecture

Table 7.

Pin n°

STR711/STR712/STR715 pin description

Input Output

Main

function

(after

Pin name

Alternate function

reset)

SPI0 Master

in/Slave out

data

UART3 Transmit data

output

P0.0/S0.MISO

/U3.TX

52 B7

I/O pu C_T

4mA

X

Port 0.0

Note: Programming AF function selects

UART by default. BSPI must be

enabled by SPI_EN bit in the BOOTCR

register.

BSPI0: Master

UART3: Receive Data

out/Slave in

input

data

P0.1/S0.MOSI

/U3.RX

53 B6

I/O pu C_T

X

4mA

X

Port 0.1

Note: Programming AF function selects

UART by default. BSPI must be

enabled by SPI_EN bit in the BOOTCR

register.

BSPI0: Serial

I2C1: Serial clock

Clock

P0.2/S0.SCLK

/I1.SCL

54 A5

I/O pu C_T

Port 0.2

Port 0.3

Note: Programming AF function selects

I2C by default. BSPI must be enabled

by SPI_EN bit in the BOOTCR register.

SPI0: Slave

Select input

active low.

I2C1: Serial Data

P0.3/S0.SS/I1

.SDA

55 C6

I/O pu C_T

4mA

X

Note: Programming AF function selects

I2C by default. BSPI must be enabled

by SPI_EN bit in the BOOTCR register.

56 B5 P0.4/S1.MISO I/O pu C_T

Port 0.4 SPI1: Master in/Slave out data

Stabilization for main voltage regulator.

57 A4 V_SS18

58 C5 V₁₈

59 B4 V_SS

S

Stabilization for main voltage regulator. Requires

external capacitors of at least 10µF + 33nF

between V₁₈and V_SS18. See Figure 5.

Ground voltage for digital I/Os

60 A3 P0.5/S1.MOSI I/O pu C_T

61 D5 P0.6/S1.SCLK I/O pu C_T

4mA

X

Port 0.5 SPI1: Master out/Slave In data

Port 0.6 SPI1: Serial Clock

X

62 B3 P0.7/S1.SS

I/O pu C_T

Port 0.7 SPI1: Slave Select input active low

27/78

System architecture

STR71xF

Table 7.

Pin n°

STR711/STR712/STR715 pin description

Input Output

Main

function

(after

Pin name

Alternate function

reset)

UART0:

Port 0.8 Receive Data

input

UART0: Transmit data

output.

P0.8/U0.RX/U

0.TX

63 C4

64 A2

I/O pd C_T

X

4mA

T

X

Note: This pin may be used for single wire UART

(half duplex) if programmed as Alternate Function

Output. The pin will be tri-stated except when

UART transmission is in progress

Select Boot

UART0: Transmit data

Port 0.9 Configuration

output

P0.9/U0.TX/B

OOT.0

I/O pd C_T

4mA

X

input

1. The Reset configuration of the I/O Ports is IPUPD (input pull-up/pull down). Refer to Table 8 on page 29.

The Port bit configuration at reset is PC0=1, PC1=1, PC2=0. The port data register bit (PD) value depends

on the pu/pd column which specifies whether the pull-up or pull-down is enabled at reset

2. V_33IO-PLLand V₃₃are internally connected. V_SSIO-PLLand V_SSare internally connected.

3.5

External connections

Figure 5.

Recommended external connection of V

V

pins

18 and 18BKP

33 nF

129 128

58

57

18

V

18

LQFP144

LQFP64

V

58

V

18BKP

18

18BKP

25 26 27¹⁸28

54

55

59

10 µF

1µF

10 µF

1µF

28/78

STR71xF

System architecture

3.6

I/O port configuration

Table 8.

Port bit configuration table

PxD

register

Input

PxC2

PxC1

PxC0

Configuration Mode

buffer

register register register

Read

access

Write

access

TTL Input Floating

TTL floating

I/O pin don’t care

0

1

0

CMOS Input Floating

CMOS floating I/O pin don’t care

CMOS Pull-

CMOS Input Pull-Down

(IPUPD)

I/O pin

0

1

Down

INPUT

CMOS

Pull-Up

CMOS Input Pull-Up (IPUPD)

I/O pin

1

Analog input

AIN

N.A.

0

don’t care

0 or 1

0

1

0

1

Output Open-Drain

Output Push-Pull

I/O pin

last value

written

0 or 1

OUTPUT

Alternate Function Open-Drain CMOS floating I/O pin don’t care

1

0

1

Alternate Function Push-Pull

CMOS floating I/O pin don’t care

Legend:

AIN: Analog Input

CMOS: CMOS Input levels

IPUPD: Input Pull Up /Pull Down

TTL: TTL Input levels

N.A.: not applicable. In Output mode, a read access to the port gets the output latch value.

29/78

System architecture

STR71xF

3.7

Memory mapping

Figure 6.

Memory map

APB Memory Space

0xFFFF FFFF

0xFFFF F800

EIC

WDG

4K

Addressable Memory Space

4 Gbytes

0xE000 E000

0xE000 D000

0xE000 C000

0xE000 B000

0xE000 A000

0xE000 9000

0xE000 8000

0xE000 7000

0xE000 6000

0xE000 5000

0xE000 4000

0xE000 3000

0xE000 2000

0xE000 1000

0xE000 0000

0xFFFF FFFF

RTC

EIC

4K

0xFFFF F800

TIMER 3

TIMER 2

TIMER 1

TIMER 0

7

64K

APB2

0xE000 0000

CLKOUT

ADC

6

reserved

IOPORT 2

IOPORT 1

IOPORT 0

reserved

64K

APB1

0xC000 0000

FLASH Memory Space

272 Kbytes + regs

0x4010 DFBF

FLASH Registers

36b

5

0x4010 0000

reserved

PRCCU

1K

0xA000 0000

0x400C 4000

0x400C 2000

0x400C 0000

XTI

B1F1

B1F0

8K

APB BRIDGE 2 REGS 4K

4

reserved

Reserved

4K

0x8000 0000

0xC001 0000

0xC000 F000

reserved

HDLC + RAM

reserved

BSPI 1

4K

reserved

B0F7

0x4004 0000

0xC000 E000

0xC000 D000

0xC000 C000

0xC000 B000

3

EXTMEM

64MB

See Figure 8

64K

0x6000 0000

0x4003 0000

BSPI 0

0xC000 A000

0xC000 9000

0xC000 8000

0xC000 7000

0xC000 6000

0xC000 5000

0xC000 4000

0xC000 3000

0xC000 2000

0xC000 1000

0xC000 0000

2

CAN

B0F6

USB + RAM

UART 3

FLASH

256K+16K+36b

0x4000 0000

0x4002 0000

UART 2

1

UART 1

B0F5

B0F4

64K

32K

UART 0

RAM

64K

0x2000 0000

0x4001 0000

reserved

I2C 1

2

0x4000 8000

0x4000 6000

0

8K

B0F3

B0F2

B0F1

B0F0

I

C 0

0x4000 4000

0x4000 2000

0x4000 0000

APB BRIDGE 1 REGS

FLASH/RAM/EMI

0x0000 0000

(*) FLASH aliased at 0x0000 0000h

by system decoder for booting with

valid instruction upon RESET

from Block B0 (8 Kbytes)

Reserved

30/78

STR71xF

System architecture

Figure 7.

Mapping of Flash memory versions

FLASH Memory Space

64 Kbytes + 16K RWW + regs

128 Kbytes + 16K RWW + regs

256 Kbytes + 16K RWW + regs

0x4010 DFBF

FLASH Registers

36b

FLASH Registers

36b

FLASH Registers

36b

0x4010 0000

reserved

0x400C 4000

B1F1

B1F0

8K

B1F1

B1F0

8K

B1F1

B1F0

8K

0x400C 2000

0x400C 0000

0x400C 2000

0x400C 0000

0x400C 2000

0x400C 0000

reserved

B0F7

0x4004 0000

64K

0x4003 0000

reserved

B0F6

0x4002 0000

reserved

B0F4

B0F5

B0F4

B0F5

B0F4

64K

32K

64K

32K

64K

32K

0x4001 0000

0x4000 8000

0x4000 6000

0x4000 8000

0x4000 6000

0x4000 8000

0x4000 6000

8K

B0F3

B0F2

B0F1

B0F0

B0F3

B0F2

B0F1

B0F0

B0F3

B0F2

B0F1

B0F0

0x4000 4000

0x4000 2000

0x4000 0000

0x4000 4000

0x4000 2000

0x4000 0000

0x4000 4000

0x4000 2000

0x4000 0000

STR715FR0xx

STR711FR0xx

STR712FR0xx

STR710FZ1xx

STR711FR1xx

STR712FR1xx

STR710F72xx

STR711FR2xx

STR712FR2xx

Table 9.

RAM memory mapping

Part number

RAM size

Start address

End address

STR715FR0xx

STR711FR0xx

STR712FR0xx

16 Kbytes

0x2000 0000

0x2000 3FFF

STR710FZ1xx

STR711FR1xx

STR712FR1xx

32 Kbytes

64 Kbytes

0x2000 0000

0x2000 7FFF

0x2000 FFFF

STR710FR2xx

STR710Rxx

STR711FR2xx

STR712FR2xx

31/78

System architecture

Figure 8.

STR71xF

External memory map

Addressable Memory Space

4 Gbytes

0xFFFF FFFF

EIC

0xFFFF F800

7

APB2

0xE000 0000

6

APB1

0xC000 0000

External Memory Space

64 MBytes

5

BCON3

BCON2

BCON1

BCON0

0x6C00 000C

0x6C00 0008

0x6C00 0004

0x6C00 0000

register

PRCCU

0xA000 0000

4

0x66FF FFFF

Reserved

EXTMEM

FLASH

0x8000 0000

Bank3

Bank2

16M

CSn.3

0x6600 0000

0x64FF FFFF

3

0x6000 0000

CSn.2

0x6400 0000

0x62FF FFFF

2

Bank1

Bank0

16M

CSn.1

0x4000 0000

0x6200 0000

0x60FF FFFF

1

CSn.0

RAM

0x2000 0000

0x6000 0000

0

FLASH/RAM/EMI

0x0000 0000

Reserved

Drawing not in scale

32/78

STR71xF

Electrical parameters

4

Electrical parameters

4.1

Parameter conditions

Unless otherwise specified, all voltages are referred to V

.

SS

4.1.1

Minimum and maximum values

Unless otherwise specified the minimum and maximum values are guaranteed in the worst

conditions of ambient temperature, supply voltage and frequencies by tests in production on

100% of the devices with an ambient temperature at T =25°C and T =T max (given by the

A

selected temperature range).

Data based on characterization results, design simulation and/or technology characteristics

are indicated in the table footnotes and are not tested in production. Based on

characterization, the minimum and maximum values refer to sample tests and represent the

mean value plus or minus three times the standard deviation (mean 3Σ).

4.1.2

4.1.3

Typical values

Unless otherwise specified, typical data are based on T =25°C, V =3.3V (for the

A

33

3.0V≤V ≤3.6V voltage range) and V =1.8V. They are given only as design guidelines and

33

18

are not tested.

Typical ADC accuracy values are determined by characterization of a batch of samples from

a standard diffusion lot over the full temperature range, where 95% of the devices have an

error less than or equal to the value indicated (mean 2Σ).

Typical curves

Unless otherwise specified, all typical curves are given only as design guidelines and are

not tested.

4.1.4

4.1.5

Loading capacitor

The loading conditions used for pin parameter measurement are shown in Figure 9.

Pin input voltage

The input voltage measurement on a pin of the device is described in Figure 10.

Figure 9.

Pin loading conditions

Figure 10. Pin input voltage

STR7 PIN

V

IN

=50pF

L

33/78

Electrical parameters

STR71xF

4.2

Absolute maximum ratings

Stresses above those listed as “absolute maximum ratings” may cause permanent damage

to the device. This is a stress rating only and functional operation of the device under these

conditions is not implied. Exposure to maximum rating conditions for extended periods may

affect device reliability.

Table 10. Voltage characteristics

Symbol

Ratings

Min

Max

Unit

External 3.3V Supply voltage

(including AV_DDand V_33IO-

2)

V₃₃- V_SS

-0.3

4.0

)

PLL

Digital 1.8V Supply voltage

on V_18BKPbackup supply ²⁾

V_18BKP- V_SSBKP

-0.3

2.0

V

Input voltage on true open

drain pin (P0.10) ¹⁾

V_SS-0.3

50

+5.5

V₃₃+0.3

50

V_IN

Input voltage on any other

pin ¹⁾

Variations between different

3.3V power pins

|∆V_33x

|

Variations between different

1.8V power pins ⁵⁾

|∆V_18x

25

mV

Variations between all the

different ground pins

|V_SSX- V_SS

V_ESD(HBM)

V_ESD(MM)

|

50

Electro-static discharge

voltage (Human Body Model)

see : Absolute maximum ratings

(electrical sensitivity) on page 48

Electro-static discharge

voltage (Machine Model)

34/78

STR71xF

Electrical parameters

Table 11. Current characteristics

Symbol

Ratings

Max.

150

Unit

Total current into V₃₃/V_33IO-PLLpower lines (source) ²⁾

Total current out of V_SS/V_SSIO-PLLground lines (sink) ²⁾

I_V33

I_VSS

I_IO

150

Output current sunk by any I/O and control pin

Output current source by any I/Os and control pin

Injected current on RSTIN pin

25

- 25

5

mA

1) 3)

1)

Injected current on CK pin

5

I_INJ(PIN)

Injected current on any other pin ⁴⁾

5

Total injected current (sum of all I/O and control pins) ⁴⁾

25

ΣI_INJ(PIN)

Notes:

1. I_INJ(PIN)must never be exceeded. This is implicitly insured if V_INmaximum is respected. If V_INmaximum

cannot be respected, the injection current must be limited externally to the I_INJ(PIN)value. A positive

injection is induced by V_IN>V₃₃while a negative injection is induced by V_IN<V_SS. For true open-drain pads,

there is no positive injection current, and the corresponding V_INmaximum must always be respected. Data

based on T_A= 25 °C.

2. All 3.3V power (V₃₃, AV_DD, V_33IO-PLL) and ground (V_SS, AV_SS, V_SSIO-PLL) pins must always be connected

to the external 3.3V supply.

3. Negative injection disturbs the analog performance of the device. See note in Section 4.3.11: ADC

characteristics on page 66.

4. When several inputs are submitted to a current injection, the maximum ΣI_INJ(PIN)is the absolute sum of the

positive and negative injected currents (instantaneous values). These results are based on

characterization with ΣI_INJ(PIN)maximum current injection on four I/O port pins of the device.

5. Only when using external 1.8V power supply. All the power (V₁₈, V_18BKP) and ground (V_SS18, V_SSBKP) pins

must always be connected to the external 1.8V supply.

Table 12. Thermal characteristics

Symbol

Ratings

Value

Unit

T_STG

Storage temperature range

-65 to +150

°C

Maximum junction temperature (see Section 5.2: Thermal characteristics on

page 72)

T_J

35/78

Electrical parameters

STR71xF

4.3

Operating conditions

Subject to general operating conditions for V , and T .

33

A

Table 13. General operating conditions

Symbol

Parameter

Conditions

Min

Max

Unit

Accessing SRAM or external

memory with 0 wait states

0

66

Accessing FLASH in burst

mode

0

50

Internal CPU Clock

frequency

f_MCLK

MHz

Executing from FLASH with

RWW

45¹⁾

33

Accessing FLASH with 0 wait

states

0

Internal APB Clock

frequency

f_PCLK

0

33

MHz

V

Standard Operating

Voltage (includes V_{33I0_PLL)}

V₃₃

3.0

3.6

V_18BKP

T_A

Backup Operating Voltage

1.4

-40

1.8

85

V

Ambient temperature range 6 Partnumber Suffix

°C

1. Data guaranteed by characterization, not tested in production

Table 14. Operating conditions at power-up / power-down

Symbol

Parameter

Conditions

Min

Max

Unit

µs/V

ms/V

Typ

Subject to general

operating conditions for

T_A.

20

V₃₃rise time rate

t_V33

20

36/78

STR71xF

Electrical parameters

4.3.1

Supply current characteristics

The current consumption is measured as described in Figure 9 on page 33 and Figure 10

on page 33.

Total current consumption

The MCU is placed under the following conditions:

●

All I/O pins in input mode with a static value at V or V (no load)

33 SS

●

All peripherals are disabled except if explicitly mentioned.

Embedded Regulators are used to provide 1.8V (except if explicitly

mentioned)

Subject to general operating conditions for V , and T .

33

A

Table 15. Total current consumption

1)

Max ²⁾

Symbol

Parameter

Conditions

Unit

Typ

f_MCLK=66 MHz, RAM execution

73.6

49.3

100

Supply current in RUN

mode

mA

f

_MCLK=32 MHz, Flash non-burst

execution

4)

I_DD

Supply current in STOP

mode

50³⁾

30

T_A=25°C

10

12

µA

Supply current in

STANDBY mode

OSC32K bypassed

Notes:

1. Typical data are based on T_A=25°C, V₃₃=3.3V.

2. Data based on characterization results, tested in production at V₃₃, f_MCLKmax. and T_Amax.

3. Based on device characterisation, device power consumption in STOP mode at T_A25°C is predicted to be

30µA or less in 99.730020% of parts.

4. The conditions for these consumption measurements are described in application note AN2100.

37/78

Electrical parameters

STR71xF

Unit

Table 16. Typical power consumption data

Typical

current

on V33

Symbol

Parameter

Conditions

MCLK = 16 MHz, PCLK1 = PCLK2 = 16

MHz

23

40

50

63

MCLK = 32 MHz, PCLK1 = PCLK2 = 32

MHz

All periphs ON

MCLK = 48 MHz, PCLK1 = PCLK2 = 24

MHz

RUN mode

current from

RAM

MCLK = 64 MHz, PCLK1 = PCLK2 = 32

MHz

MCLK = 16 MHz

MCLK = 32 MHz

MCLK = 48 MHz

MCLK = 64 MHz

16

26

39

48

All periphs OFF

All periphs ON

I_DDRUN

mA

MCLK = 16 MHz, PCLK1 = PCLK2 = 16

MHz

27

47

62

MCLK = 32 MHz, PCLK1 = PCLK2 = 32

MHz

RUN mode

current from

FLASH

MCLK = 48 MHz, PCLK1 = PCLK2 = 24

MHz

MCLK = 16 MHz

21

36

53

1.7

All periphs OFF MCLK = 32 MHz

MCLK = 48 MHz

I_DDSLOW

I_DDWAIT

I_DDLPWAIT

SLOW mode current

MCLK = CK_AF (32 kHz), MVR off

PCLK1 = PCLK2 = 1 MHz

WAIT mode current

(all periphs ON)

13

37

18

CK_AF (32 kHz), Main VReg off, FLASH in

power-down

LPWAIT mode current

Main VReg off, FLASH in power down, RTC

on

I_DDSTOP

STOP mode current

Main VReg off, FLASH in power down, RTC

off

10

9

LP VReg on, LVD on, RTC on

µA

LP VReg off (ext 1.8V on V18BKP), LVD on,

RTC on

I_DDSB

STANDBY mode current

LP VReg off (ext1.8V on V18BKP), LVD off,

RTC on

5

1

LP VReg off (ext 1.8V on V18BKP), LVD off,

RTC off

38/78

STR71xF

Electrical parameters

Figure 11. STOP I vs. V

Figure 12. STANDBY I vs. V

DD 33

DD

33

25

20

15

10

5

100

90

80

70

60

50

40

30

20

10

0

TA=-45°C

TA=0°C

TA=+25°C

TA=+90°C

TA=-45 to +25°C

TA=+90°C

0

3

3.1

3.2

3.3

V33 (V)

3.4

3.5

3.6

3

3.1

3.2

3.3

3.4

3.5

3.6

V33 (V)

Figure 13. WFI I vs. V

DD

33

100

90

80

70

60

50

TA=-40 to +90°C

3

3.1

3.2

3.3

V33 (V)

3.4

3.5

3.6

39/78

Electrical parameters

STR71xF

On-chip peripherals

Table 17. Peripheral current consumption

Symbol

I_DD(PLL1)

I_DD(PLL2)

I_DD(TIM)

Parameter

PLL1 supply current

Conditions

T = 25°C

Typ

3.42

5.81

0.88

1.1

Unit

A

PLL2 supply current

TIM Timer supply current ¹⁾

BSPI supply current ²⁾

UART supply current ²⁾

I2C supply current ²⁾

I_DD(BSPI)

I_DD(UART)

I_DD(I2C)

1.05

0.45

1.89

1.82

2.08

1.11

mA

T = 25°C,

A

f

=33 MHz

ADC supply current when converting ⁵⁾

HDLC supply current ²⁾

USB supply current ²⁾

PCLK1= PCLK2

I_DD(ADC)

I_DD(HDLC)

I_DD(USB)

I_DD(CAN)

CAN supply current ²⁾

Notes:

1. Data based on a differential I_DDmeasurement between reset configuration and timer counter running at

16MHz. No IC/OC programmed (no I/O pads toggling).

2. Data based on a differential I_DDmeasurement between the on-chip peripheral when kept under reset and

not clocked and the on-chip peripheral when clocked and not kept under reset. No I/O pads toggling.

3. Data based on a differential I_DDmeasurement between reset configuration and continuous A/D

conversions.

40/78

STR71xF

Electrical parameters

4.3.2

Clock and timing characteristics

External clock sources

Subject to general operating conditions for V , and T .

33

A

Table 18. CK external clock characteristics

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

External clock source

frequency

f_CK

0

16.5

MHz

CK input pin high level

voltage

V_CKH

V_CKL

t_w(CK)

0.7xV₃₃

V_SS

V₃₃

V

CK input pin low level

voltage

0.3xV₃₃

CK high or low time ¹⁾

CK rise or fall time ¹⁾

25

t_w(CK)

ns

t_r(CK)

t_f(CK)

20

CK input capacitance¹⁾

Duty cycle

C_IN(CK)

5

pF

%

DuCy(XT1)

40

60

1

I_L

V_SS≤V_IN≤V₃₃

CK Input leakage current

µA

Notes:

1. Data based on design simulation and/or technology characteristics, not tested in production.

Figure 14. CK external clock source

90%

V

CKH

CKL

10%

t

w(CKH)

t

w(CKL)

f(CK)

r(CK)

T

CK

f

CLK

EXTERNAL

CLOCK SOURCE

I

L

CK

STR710

41/78

Electrical parameters

STR71xF

Table 19. RTCXT1 external clock characteristics

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

External clock source

frequency

f_RTCXT1

0

500

kHz

RTCXT1 input pin high level

voltage

V_RTCXT1H

V_RTCXT1L

t_w(RTCXT1)

0.7xV₃₃

V_SS

V₃₃

V

RTCXT1 input pin low level

voltage

0.3xV₃₃

RTCXT1 high or low time ¹⁾

RTCXT1 rise or fall time ¹⁾

100

t_w(RTCXT1)

ns

t_r(RTCXT1)

t_f(RTCXT1)

5

RTCXT1 input

capacitance¹⁾

C_IN(RTCXT1)

5

pF

%

DuCy(RTCXT1)

Duty cycle

30

70

1

RTCXT1 Input leakage

current

I_L

V_SS≤V_IN≤V₃₃

µA

Notes:

1. Data based on design simulation and/or technology characteristics, not tested in production.

42/78

STR71xF

Electrical parameters

OSC32K crystal / ceramic resonator oscillator

The STR7 RTC clock can be supplied with a 32 kHz Crystal/Ceramic resonator oscillators.

All the information given in this paragraph are based on characterization results with

specified typical external components. In the application, the resonator and the load

capacitors have to be placed as close as possible to the oscillator pins in order to minimize

output distortion and start-up stabilization time. Refer to the crystal resonator manufacturer

for more details (frequency, package, accuracy...).

Table 20. 32K oscillator characteristics (f_OSC32K=32.768 kHz)

Symbol

Parameter

Feedback resistor

Conditions

Typ

Unit

R_F

2.7

MΩ

Recommended load capacitance

versus equivalent serial resistance

of the crystal (R_S)¹⁾

C_L1

C_L2

R_S=40K Ω

12.5

3.2

pF

V₃₃=3.3 V

V_IN=V_SS

i₂

RTCXT2 driving current

µA

g_m

Oscillator Transconductance

startup time

8

5

µA/V

2)

V₃₃is stabilized

t_SU(OSC32KHZ)

s

Notes:

1. The oscillator selection can be optimized in terms of supply current using an high quality resonator with

small R_Svalue for example MSIV-TIN32.768kHz. Refer to crystal manufacturer for more details

2. t_SU(OSC32KHZ)is the start-up time measured from the moment it is enabled (by software) to a stabilized

32 kHz oscillation is reached. This value is measured for a standard crystal resonator and it can vary

significantly with the crystal manufacturer

Figure 15. Typical application with a 32 kHz crystal

WHEN RESONATOR WITH

INTEGRATED CAPACITORS

FEEDBACK

LOOP

i

2

C

f

L1

RTCXT1

RTCXT2

OSC32K

32 kHz

RESONATOR

R

F

C

L2

STR710

43/78

Electrical parameters

Figure 16. RTC crystal oscillator and resonator

STR71xF

DEVICE

R_S

C_L

PLL electrical characteristics

V

= 3.0 to 3.6V, V

= 3.0 to 3.6V, T = -40 / 85 °C unless otherwise specified.

33

33IOPLL A

Table 21. PLL1 characteristics

Symbol Parameter

Value

Typ

Test conditions

Unit

Min

Max

f_PLLCLK1PLL multiplier output clock

165

3.0

MHz

FREF_RANGE = 0

1.5

3.0

FREF_RANGE = 1

MX[1:0]=’00’ or ‘01’

8.25

MHz

PLL input clock

f_PLL1

FREF_RANGE = 1

MX[1:0]=’10’ or ‘11’

3.0

25

6

MHz

%

PLL input clock duty cycle

75

FREF_RANGE = 0

MX[1:0]=’01’ or ‘11’

125

250

500

kHz

FREF_RANGE = 0

MX[1:0]=’00’ or ‘10’

kHz

f_FREE1PLL free running frequency

FREF_RANGE = 1

MX[1:0]=’01’ or ‘11’

FREF_RANGE = 1

MX[1:0]=’00’ or ‘10’

FREF_RANGE = 0

Stable Input Clock

300

µs

Stable V

, V

18

33IOPLL

t_LOCK1PLL lock time

FREF_RANGE = 1

Stable Input Clock

600

2

µs

Stable V

, V

18

33IOPLL

t

= 4 MHz, MX[1:0]=’11’

PLL

Global Output division = 32

∆t_JITTER1PLL jitter (peak to peak)

0.7

ns

(Output Clock = 2 MHz)

44/78

STR71xF

Electrical parameters

Table 22. PLL2 characteristics

Value

Symbol

Parameter

Test conditions

Unit

Min

Typ Max

PLL multiplier output

clock

f_PLLCLK2

140

MHz

FREF_RANGE = 0

1.5

3.0

5

MHz

f_PLL2

PLL input clock

FREF_RANGE = 1

FREF_RANGE = 0

Stable Input Clock

Stable V_33IOPLL, V₁₈

300

600

2

µs

ns

t_LOCK2

PLL lock time

FREF_RANGE = 1

Stable Input Clock

Stable V_33IOPLL, V₁₈

t

_PLL= 4 MHz, MX[1:0]=’11’

∆t_JITTER2

PLL jitter (peak to peak) Global Output division = 32

(Output Clock = 2 MHz)

0.7

Table 23. Low-power mode wakeup timing

Symbol

Parameter

Wakeup from LPWFI mode

Typ

Unit

26⁽¹⁾

t_WULPWFI

µs

CLK

t_WUSTOP

Wakeup from STOP mode

2048

Cycles

(2)

2048 CLK Cycles

+ 8 CLK2 Cycles⁽³⁾

t_WUSTBY

Wakeup from STANDBY mode

Cycles

1. Clock selected is CK2_16, Main VReg OFF and Flash in power-down

2. The CLK clock is derived from the external oscillator.

3. Refer to Figure 7. Reset General Timing in the STR71xF Reference Manual (UM0084)

45/78

Electrical parameters

STR71xF

4.3.3

Memory characteristics

Flash memory

V

= 3.0 to 3.6V, T = -40 to 85 °C unless otherwise specified.

A

33

Table 24. Flash memory characteristics

Value

Typ

Symbol

Parameter

Test conditions

Unit

Max¹⁾

Min.

t_PW

t_PDW

t_PB0

t_PB1

Word Program

40

60

µs

s

Double Word Program

Bank 0 Program (256K)

Bank 1 Program (16K)

Double Word Program

1.6

130

2.1

170

ms

Not preprogrammed

Preprogrammed

4.0

3.3

2.3

1.9

t_ES

Sector Erase (64K)

Sector Erase (8K)

Bank 0 Erase (256K)

Bank 1 Erase (16K)

s

0.7

0.6

1.1

1.0

Not preprogrammed

Preprogrammed

t_ES

8.0

6.6

13.7

11.2

Not preprogrammed

Preprogrammed

t_ES

0.9

0.8

1.5

1.3

Not preprogrammed

Preprogrammed

t_ES

2)

Recovery when disabled

Program Suspend Latency

Erase Suspend Latency

20

10

µs

t_RPD

2)

t_PSL

2)

300

t_ESL

Endurance (Bank 0

sectors)

N_{END_B0}

N_{END_B1}

t_RET

10

100

20

kcycles

Years

Endurance (Bank 1

sectors)

Data Retention (Bank 0

and Bank 1)

T_A=85°

Min time from Erase

Resume to next Erase

Suspend

t_ESR

Erase Suspend Rate

20

ms

Notes:

1. T_A=45°C after 0 cycles. Guaranteed by characterization, not tested in production.

2. Guaranteed by design, not tested in production

46/78

STR71xF

Electrical parameters

4.3.4

EMC characteristics

Susceptibility tests are performed on a sample basis during product characterization.

Functional EMS (electro magnetic susceptibility)

Based on a simple running application on the product (toggling 2 LEDs through I/O ports),

the product is stressed by two electro magnetic events until a failure occurs (indicated by the

LEDs).

●

ESD: Electro-Static Discharge (positive and negative) is applied on all pins of the

device until a functional disturbance occurs. This test conforms with the IEC 1000-4-2

standard.

●

FTB: A Burst of Fast Transient voltage (positive and negative) is applied to V and

DD

V

through a 100pF capacitor, until a functional disturbance occurs. This test

SS

conforms with the IEC 1000-4-4 standard.

A device reset allows normal operations to be resumed. The test results are given in the

table below based on the EMS levels and classes defined in application note AN1709.

Designing hardened software to avoid noise problems

EMC characterization and optimization are performed at component level with a typical

application environment and simplified MCU software. It should be noted that good EMC

performance is highly dependent on the user application and the software in particular.

Therefore it is recommended that the user applies EMC software optimization and

prequalification tests in relation with the EMC level requested for his application.

Software recommendations:

The software flowchart must include the management of runaway conditions such as:

●

Corrupted program counter

Unexpected reset

Critical Data corruption (control registers...)

Prequalification trials:

Most of the common failures (unexpected reset and program counter corruption) can be

reproduced by manually forcing a low state on the RESET pin or the Oscillator pins for 1

second.

To complete these trials, ESD stress can be applied directly on the device, over the range of

specification values. When unexpected behavior is detected, the software can be hardened

to prevent unrecoverable errors occurring (see application note AN1015).

In the case of an ARM7 CPU, in order to write robust code that can withstand all kinds of

stress, such as very strong electromagnetic disturbance, it is mandatory that the Data Abort,

Prefetch Abort and Undefined Instruction exceptions are managed by the application

software. This will prevent the code going into an undefined state or performing any

unexpected operation.

47/78

Electrical parameters

STR71xF

Table 25. EMS data

Level/

Class

Symbol

Parameter

Conditions

V₃₃=3.3 V, T_A=+25°C, f_MCLK=32 MHz

conforms to IEC 1000-4-2

Voltage limits to be applied on any I/O pin

to induce a functional disturbance

V_FESD

2B

4A

Fast transient voltage burst limits to be

V_EFTBapplied through 100pF on V_DDand V_SS

V₃₃=3.3 V, T_A=+25°C, f_MCLK=32 MHz

conforms to IEC 1000-4-4

pins to induce a functional disturbance

Electro magnetic interference (EMI)

Based on a simple application running on the product (toggling 2 LEDs through the I/O

ports), the product is monitored in terms of emission. This emission test is in line with the

norm SAE J 1752/3 which specifies the board and the loading of each pin.

Table 26. EMI data

Max vs.

[f_OSC4M/f_HCLK

]

Monitored

Symbol

Parameter

Conditions

Unit

frequency band

16/ 48

MHz

16/8

MHz

0.1 MHz to 30 MHz

30 MHz to 130 MHz

130 MHz to 1 GHz

SAE EMI Level

17

11

4

19

16

11

3

V₃₃=3.3 V, T_A=+25°C,

dBµV

LQFP64 package

conforming to SAE J

1752/3

S_EMI

Peak level

-

Notes:

1. Not tested in production.

2. BGA and LQFP devices have similar EMI characteristics.

Absolute maximum ratings (electrical sensitivity)

Based on three different tests (ESD, LU and DLU) using specific measurement methods, the

product is stressed in order to determine its performance in terms of electrical sensitivity.

For more details, refer to the application note AN1181.

Electro-static discharge (ESD)

Electro-Static Discharges (a positive then a negative pulse separated by 1 second) are

applied to the pins of each sample according to each pin combination. The sample size

depends on the number of supply pins in the device (3 parts*(n+1) supply pin). Two models

can be simulated: Human Body Model and Machine Model. This test conforms to the

JESD22-A114A/A115A standard.

48/78

STR71xF

Electrical parameters

Table 27. ESD absolute maximum ratings

Maximum

Unit

Symbol

Ratings

Conditions

value ¹⁾

Electro-static discharge voltage

(Human Body Model)

V_ESD(HBM)

2000

Electro-static discharge voltage

(Machine Model)

V_ESD(MM)

200

V

T_A=+25°C

750 on corner

pins, 500 on

others

Electro-static discharge voltage

(Charge Device Model)

V_ESD(CDM)

Notes:

1. Data based on characterization results, not tested in production.

Static and dynamic latch-up

●

LU: 3 complementary static tests are required on 10 parts to assess the latch-up

performance. A supply overvoltage (applied to each power supply pin) and a current

injection (applied to each input, output and configurable I/O pin) are performed on each

sample. This test conforms to the EIA/JESD 78 IC latch-up standard. For more details,

refer to the application note AN1181.

●

DLU: Electro-Static Discharges (one positive then one negative test) are applied to

each pin of 3 samples when the micro is running to assess the latch-up performance in

dynamic mode. Power supplies are set to the typical values, the oscillator is connected

as near as possible to the pins of the micro and the component is put in reset mode.

This test conforms to the IEC1000-4-2 and SAEJ1752/3 standards. For more details,

refer to the application note AN1181.

Electrical sensitivities

Table 28. Static and dynamic latch-up

Class ⁽¹⁾

Symbol

Parameter

Conditions

T_A=+25°C

T_A=+85°C

T_A=+105°C

A

LU

Static latch-up class

V_DD=3.3 V, f_OSC4M=4 MHz, f_MCLK=32 MHz,

T_A=+25°C

DLU

Dynamic latch-up class

A

1. Class description: A Class is an STMicroelectronics internal specification. All its limits are higher than the

JEDEC specifications, that means when a device belongs to Class A it exceeds the JEDEC standard. B

Class strictly covers all the JEDEC criteria (international standard).

49/78

Electrical parameters

STR71xF

4.3.5

I/O port pin characteristics

General characteristics

Subject to general operating conditions for V and T unless otherwise specified. All

33

A

unused pins must be kept at a fixed voltage: using the output mode of the I/O for example or

an external pull-up or pull-down resistor.

Table 29. I/O static characteristics

Symbol

V_IL

Parameter

Conditions

Min

Max

Unit

Typ

Input low level voltage ¹⁾

Input high level voltage ¹⁾

0.3V₃₃

V

V_IH

0.7V₃₃

CMOS ports

Schmitt trigger voltage hysteresis

V_hys

0.8

V

2)

Input low level voltage ¹⁾

Input high level voltage ¹⁾

V_IL

V_IH

0.9

0.8

2

1.35

P0.15 WAKEUP

TTL ports

Schmitt trigger voltage hysteresis

2)

V_hys

0.4

Input low level voltage ¹⁾

V_IL

V_IH

Input high level voltage ¹⁾

2.0

I_INJ(PIN)

Injected Current on any I/O pin

4

25

1

mA

ΣI_INJ(PIN)Total injected current (sum of all

I/O and control pins)

3)

Input leakage current ⁴⁾

I_lkg

V_SS≤V_IN≤V₃₃

V_IN=V_SS

µA

kΩ

Weak pull-up equivalent

resistor⁵⁾

R_PU

110

150

700

Weak pull-down equivalent

resistor⁵⁾

R_PD

C_IO

V_IN=V₃₃

150

5

kΩ

I/O pin capacitance

pF

Notes:

1. Data based on characterization results, not tested in production.

2. Hysteresis voltage between Schmitt trigger switching levels. Based on characterization results, not tested.

3. When the current limitation is not possible, the V_INabsolute maximum rating must be respected, otherwise

refer to I_INJ(PIN)specification. A positive injection is induced by V_IN>V₃₃while a negative injection is

induced by V_IN<V_SS. Refer to Section 4.2 on page 34 for more details.

4. Leakage could be higher than max. if negative current is injected on adjacent pins.

5. The R_PUpull-up and R_PDpull-down equivalent resistor are based on a resistive transistor (corresponding

I_PUand I_PDcurrent characteristics described in Figure 18 to Figure 19).

50/78

STR71xF

Electrical parameters

Figure 17. R vs. V with V =V

Figure 18. I vs. V with V =V

PU

33

IN

SS

PU

33

IN

SS

0.0

0

TA=-45°C

TA=0°C

TA=+25°C

TA=+90°C

TA=-45°C

TA=0°C

TA=+25°C

TA=+90°C

-5

-50.0

-10

-15

-20

-25

-30

-100.0

-150.0

-200.0

-250.0

3

3.1

3.2

3.3

3.4

3.5

3.6

3

3.1

3.2

3.3

3.4

3.5

3.6

V33 (V)

Figure 19. R vs. V with V =V

Figure 20. I vs. V with V =V

PD

33

IN

33

PD

33

IN

33

300.0

250.0

200.0

150.0

100.0

50.0

TA=-45°C

TA=0°C

TA=+25°C

TA=+90°C

30

25

20

15

10

5

TA=-45°C

TA=0°C

TA=+25°C

TA=+90°C

0.0

0

3

3.1

3.2

3.3

3.4

3.5

3.6

3

3.1

3.2

3.3

3.4

3.5

3.6

V33 (V)

51/78

Electrical parameters

STR71xF

Output driving current

Subject to general operating conditions for V and T unless otherwise specified.

33

A

Table 30. Output driving current

I/O

Symbol

Parameter

Conditions

I_IO=+4mA

I_IO=-4mA

I_IO=+8mA

I_IO=-8mA

Min

Max

Unit

Type

Output low level voltage for an I/O pin

when 8 pins are sunk at same time

1)

0.4

V_OL

Output high level voltage for an I/O pin

when 4 pins are sourced at same time

2)

V₃₃-0.8

V_OH

V

Output low level voltage for an I/O pin

when 8 pins are sunk at same time

1)

0.4

V_OL

Output high level voltage for an I/O pin

when 4 pins are sourced at same time

2)

V_OH

Notes:

1. The I_IOcurrent sunk must always respect the absolute maximum rating specified in Table 11 and the sum

of I_IO(I/O ports and control pins) must not exceed I_VSS

.

2. The I_IOcurrent sourced must always respect the absolute maximum rating specified in Table 11 and the

sum of I_IO(I/O ports and control pins) must not exceed I_V33

.

52/78

STR71xF

Electrical parameters

Figure 21. Typical V and V at V =3.3V (high current ports)

OL

OH

33

3.09

3.08

3.07

3.06

3.05

3.04

3.03

3.02

3.01

0.16

0.14

0.12

0.10

0.08

0.06

0.04

0.02

0.00

TA=-45°C

TA=0°C

TA=+25°C

TA=+90°C

TA=-45°C

TA=0°C

TA=+25°C

TA=+90°C

-4

-8

-4

-8

Ioh (mA)

Iol (mA)

53/78

Electrical parameters

STR71xF

Figure 22. Typical V vs. V

OL

33

0.18

0.16

0.14

0.12

0.10

0.08

0.06

0.04

0.02

0.00

0.16

0.14

0.12

0.10

0.08

TA=-45°C

TA=0°C

TA=+25°C

TA=+90°C

TA=-45°C

TA=0°C

0.06

TA=+25°C

TA=+90°C

0.04

0.02

0.00

3

3.1

3.2

3.3

3.4

3.5

3.6

3

3.1

3.2

3.3

3.4

3.5

3.6

V33 (V)

Figure 23. Typical V vs. V

OH

33

3.60

3.40

3.20

3.00

2.80

2.60

2.40

2.20

2.00

3.60

3.40

3.20

3.00

2.80

TA=-45°C

TA=0°C

TA=+25°C

TA=+90°C

2.60

2.40

2.20

2.00

TA=-45°C

TA=0°C

TA=+25°C

TA=+90°C

3

3.1

3.2

3.3

3.4

3.5

3.6

3

3.1

3.2

3.3

3.4

3.5

3.6

V33 (V)

54/78

STR71xF

Electrical parameters

RSTIN pin

The RSTIN pin input driver is CMOS. A permanent pull-up is present which is the same as

as R (seeTable 29 on page 50)

PU

Subject to general operating conditions for V and T unless otherwise specified.

33

A

Table 31. RESET pin characteristics

Typ ¹⁾

Symbol

V_IL(RSTINn)

V_IH(RSTINn)

V_F(RSTINn)

V_NF(RSTINn)

Parameter

Conditions

Min

Max Unit

RSTIN Input low level voltage ¹⁾

RSTIN Input high level voltage ¹⁾

RSTIN Input filtered pulse²⁾

0.8

V

2

500

ns

µs

RSTIN Input not filtered pulse²⁾

1.2

Notes:

1. Data based on characterization results, not tested in production.

2) Data guaranteed by design, not tested in production.

1)

Figure 24. Recommended RSTIN pin protection.

Recommended

V

33

V

33

V

33

R_PU

0.01µF

4.7kΩ

RSTIN

EXTERNAL

RESET

INTERNAL RESET

Filter

CIRCUIT

STR7X

Required

Notes:

1. The R_PUpull-up equivalent resistor is based on a resistive transistor (corresponding I_PUcurrent

characteristics described in Figure 18).

2. The reset network protects the device against parasitic resets.

3. The user must ensure that the level on the RSTIN pin can go below the V_IL(RSTINn)max. level specified in

Table 31. Otherwise the reset will not be taken into account internally.

55/78

Electrical parameters

STR71xF

4.3.6

TIM timer characteristics

Subject to general operating conditions for V , f

, and T unless otherwise

A

33 MCLK

specified.

Refer to Section 4.3.5: I/O port pin characteristics on page 50 for more details on

the input/output alternate function characteristics (output compare, input capture,

external clock, PWM output...).

Table 32. TIM characteristics

Symbol

Parameter

Conditions

Min

2

Typ

Max

Unit

t_{CK_TIM}

t_PCLK2

ns

t_w(ICAP)in

Input capture pulse time

1

t_res(TIM)

Timer resolution time

f_PCLK2= 30 MHz

33.3

f_{CK_TIM(MAX)}

f_MCLK

=

f_{CK_TIM}/4

0

MHz

Timer external clock

frequency

f_EXT

f_{CK_TIM}= f_MCLK

60 MHz

=

15

Res_TIM

Timer resolution

16

bit

16-bit Counter clock period

when internal clock is

selected

t_PCLK2

1

65536

2184

t_COUNTER

f_PCLK2= 30 MHz

0.033

µs

t_PCLK

s

65536x

65536

T_{MAX_COUNT}

Maximum Possible Count

f_PCLK2= 30 MHz

143.1

4.3.7

EMI - external memory interface

Subject to general operating conditions for V , f

, and T unless otherwise specified.

A

DD HCLK

The tables below use a variable which is derived from the EMI_BCONn registers (described

in the STR71x Reference Manual) and represents the special characteristics of the

programmed memory cycle.

Table 33.

Symbol

EMI general characteristics

Parameter

Value

t_MCLKCPU clock period

t_CMemory cycle time wait states

1 / f_MCLK

t_MCLKx (1 + [C_LENGTH])

56/78

STR71xF

Electrical parameters

Table 34. EMI read operation

Value

Symbol

Parameter

Test Conditions

Unit

Min¹⁾

19

Max¹⁾

21

Typ

t_RCR

t_RP

t_RDS

t_RDH

t_MCLK

t_C

Read to CSn Removal Time

Read Pulse Time

ns

98

100

Read Data Setup Time

Read Data Hold Time

22

0

MCLK=50 MHz

4 wait states

1.5*t_M

CLK

t_RAS

t_RAH

t_RAT

t_RRT

Read Address Setup Time

Read Address Hold Time

27

0.65

1.9

20

33

2

ns

50 pf load on all pins

Read Address Turnaround

Time

3.25

21

t_MCLK

RDn Turnaround Time

See Figure 25, Figure 26, Figure 27 and Figure 28 for related timing diagrams.

1. Data based on characterisation results, not tested in production.

Table 35. EMI write operation

Value

Symbol

Parameter

Test conditions

Unit

Min¹⁾

20

Max¹⁾

22.5

80

Typ

t_WCR

t_WP

t_MCLK

t_C

WEn to CSn Removal Time

Write Pulse Time

ns

77.5

t_C+

t_MCLK

t_WDS1

Write Data Setup Time 1

97

100

ns

t_WDS2

t_WDH

t_WAS

t_WAH

t_C

Write Data Setup Time 2

Write Data Hold Time

77

20

27

0.6

80

23

33

3

ns

MCLK=50 MHz

3 wait states

t_MCLK

50 pf load on all pins

1.5*t_MCLK

Write Address Setup Time

Write Address Hold Time

Write Address Turnaround

Time

t_WAT

1.75

20

4.1

23

ns

t_WWT

t_MCLK

WEn Turnaround Time

See Figure 29, Figure 30, Figure 31 and Figure 32 for related timing diagrams.

1. Data based on characterisation results, not tested in production.

57/78

Electrical parameters

Figure 25. Read cycle timing: 16-bit read on 16-bit memory

STR71xF

t_RAH

Address

t_RP

A[23:0]

RDn

t_RCR

CSn.x

WEn.x

t_RDS

t_RDH

t_RAS

Data Input

D[15:0]

(Input)

Figure 26. Read cycle timing: 32-bit read on 16-bit memory

t_RAT

t_RAH

Address

t_RP

Address

t_RP

A[23:0]

t_RRT

RDn

t_RCR

CSn.x

WEn.x

t_RAS

t_RDS

t_RDH

t_RDS

t_RDH

Data Input

D[15:0]

(Input)

See Table 34 for read timing data.

Figure 27. Read cycle timing: 16-bit read on 8-bit memory

t_RAT

t_RAH

Address

t_RP

Address

t_RP

A[23:0]

t_RRT

RDn

t_RCR

CSn.x

WEn.x

t_RAS

t_RDS

t_RDH

t_RDS

t_RDH

Data Input

D[7:0]

(Input)

58/78

STR71xF

Electrical parameters

Figure 28. Read cycle timing: 32-bit read on 8-bit memory

t_RAT

t_RAH

Address

t_RP

Address

t_RP

Address

t_RP

Address

t_RP

A[23:0]

t_RRT

RDn

t_RCR

CSn.x

WEn.x

t_RAS

t_RDS

t_RDH

t_RDS

t_RDH

t_RDS

t_RDH

t_RDS

t_RDH

Data Input

D[7:0]

(Input)

See Table 34 for read timing data.

Figure 29. Write cycle timing: 16-bit write on 16-bit memory

t_WAH

Address

A[23:0]

t_WCR

RDn

CSn.x

t_WAS

t_WP

WEn.x

t_WDH

t_WDS1

Data Output

D[15:0]

(Output)

Figure 30. Write cycle timing: 32-bit write on 16-bit memory

t_WAT

t_WAH

address

A[23:0]

t_WCR

RDn

CSn.x

t_WP

t_WWT

t_WP

WEn.x

t_WAS

t_WDS1

t_WDH

t_WDS2

t_WDH

Data Output

D[15:0]

(Output)

See Table 46 for write timing data.

59/78

Electrical parameters

Figure 31. Write cycle timing: 16-bit write on 8-bit memory

STR71xF

t_WAT

t_WAH

address

A[23:0]

t_WCR

RDn

CSn.x

t_WP

t_WWT

t_WP

WEn.x

t_WAS

t_WDS1

t_WDH

t_WDS2

t_WDH

Data Output

D[7:0]

(Output)

Figure 32. Write cycle timing: 32-bit write on 8-bit memory

t_WAT

t_WAH

address

A[23:0]

t_WCR

RDn

CSn.x

t_WP

t_WWT

t_WP

t_WWT

t_WP

t_WWT

t_WP

WEn.x

t_WAS

t_WDS1

t_WDH

t_WDS2

t_WDH

t_WDS2

t_WDH

t_WDS2

t_WDH

Data Output

D[7:0]

(Output)

See Table 35 for write timing data.

2

I C - inter IC control interface

4.3.8

Subject to general operating conditions for V ,

, and T unless otherwise specified.

f

33

A

PCLK1

2

The STR7 I C interface meets the requirements of the Standard I C communications

protocol described in the following table with the restriction mentioned below:

Restriction: The I/O pins which SDA and SCL are mapped to are not “True” Open-Drain:

Note:

when configured as open-drain, the PMOS connected between the I/O pin and V

is

33

the I/O pin and V

disabled, but it is still present. Also, there is a protection diode between

.

33

2

Consequently, when using this I C in a multi-master network, it is not possible to power off

the STR7X while some another I C master node remains powered on: otherwise, the

2

STR7X will be powered by the protection diode.

Refer to I/O port characteristics for more details on the input/output alternate function

characteristics (SDA and SCL).

60/78

STR71xF

Electrical parameters

Table 36. I2C characteristics

Standard mode

I²C

Fast mode I²C⁵⁾

Unit

Symbol

Parameter

Min ¹⁾

4.7

Max ¹⁾

Min ¹⁾

Max ¹⁾

t_w(SCLL)

t_w(SCLH)

t_su(SDA)

t_h(SDA)

SCL clock low time

1.3

µs

SCL clock high time

SDA setup time

4.0

0.6

250

100

0 ³⁾

0 ²⁾

900 ³⁾

300

SDA data hold time

t_r(SDA)

t_r(SCL)

ns

20+0.1C_b

SDA and SCL rise time

1000

300

t_f(SDA)

t_f(SCL)

20+0.1C_b

SDA and SCL fall time

300

t_h(STA)

t_su(STA)

t_su(STO)

t_w(STO:STA)

C_b

START condition hold time

4.0

4.7

4.0

4.7

0.6

1.3

µs

Repeated START condition setup

time

STOP condition setup time

µs

pF

STOP to START condition time (bus

free)

Capacitive load for each bus line

400

Notes:

1. Data based on standard I²C protocol requirement, not tested in production.

2. The device must internally provide a hold time of at least 300 ns for the SDA signal in order to bridge the

undefined region of the falling edge of SCL.

3. The maximum hold time t_h(SDA)is not applicable.

4. Measurement points are done at CMOS levels: 0.3xV_DDand 0.7xV_DD

.

5. f_PCLK1, must be at least 8 MHz to achieve max fast I²C speed (400 kHz).

6. The following table gives the values to be written in the I2CCCR register to obtain the required I²C SCL line

frequency.

61/78

Electrical parameters

Figure 33.

STR71xF

2

Typical application with I C bus and timing diagram

V

DD

4.7kΩ

100Ω

SDA

SCL

2

I C BUS

STR7

REPEATED START

START

t

su(STA)

w(STO:STA)

START

SDA

t

r(SDA)

f(SDA)

STOP

t

h(SDA)

su(SDA)

SCL

t

su(STO)

t

h(STA)

w(SCKH)

w(SCKL)

r(SCK)

f(SCK)

Table 37. SCL Frequency Table (f_PCLK1=8 MHz.,V₃₃= 3.3 V)

I2CCCR Value

f_SCL

(kHz)

R_P=4.7kΩ

400

300

200

100

50

83

85h

8Ah

24h

4Ch

C4h

20

Legend:

R_P= External pull-up resistance

f_SCL= I²C speed

NA = Not achievable

Note:

For speeds around 200 kHz, achieved speed can have ± ±5% tolerance

For other speed ranges, achieved speed can have ± ±2% tolerance

The above variations depend on the accuracy of the external components used.

62/78

STR71xF

Electrical parameters

4.3.9

BSPI - buffered serial peripheral interface

Subject to general operating conditions for V , T and f ,unless otherwise specified.

PCLK1

DD

A

Refer to I/O port pin characteristics on page 50 for more details on the input/output alternate

function characteristics (SS, SCK, MOSI, MISO).

Table 38. BSPI characteristics

Symbol

Parameter

Conditions

Min

Max

Unit

f_PCLK1/6

5.5

Master

f_PCLK1/254

f_SCK

1/t_c(SCK)

SPI clock frequency

MHz

f_PCLK1/8

3.3

Slave

0

capacitive charge

C=50 pF

t_r(SCK)

t_f(SCK)

SPI clock rise and fall time

14

(1)

t_su(SS)

SS setup time

SS hold time

Slave

0

(1)

t_h(SS)

(1)

t_w(SCKH)

t_w(SCKL)

Master f_PCLK1=33 MHz,

presc = 6

SCK high and low time

Data input setup time

Data input hold time

73

(1)

t_su(MI)

t_su(SI)

Master

Slave

7

0

(1)

1)(2)

t_h(MI)

t_h(SI)

Master

Slave

1xt_PCLK1

2xt_PCLK1

(1)

t_h(MI)

t_h(SI)

Master f_PCLK1=33 MHz

Slave f_PCLK1=33 MHz

30

60

(1)

ns

Slave

0

1.5xt_PCLK1+42

1)(3)

(1)(4)

t_a(SO)

Data output access time

Data output disable time

Data output valid time

Data output hold time

Data output valid time

Data output hold time

Slave f_PCLK1=33 MHz

Slave

87

42

t_dis(SO)

Slave (after enable edge)

3xt_PCLK1+45

135

(1)(2)

t_v(SO)

f

_PCLK1=33 MHz

(1)

t_h(SO)

Slave (after enable edge)

Master (after enable edge)

0

2xt_PCLK1+12

72

(1)(2)

t_v(MO)

f

_PCLK1=33 MHz

(1)

t_h(MO)

Master (after enable edge)

1. Data based on design simulation and/or characterisation results, not tested in production.

2. Depends on f_PCLK1. For example, if f_PCLK1=8 MHz, then t_PCLK1= 1/f_PCLK1=125 ns and t_v(MO)= 255 ns.

3. Min. time is the minimum time to drive the output and the max. time is the maximum time to validate the data.

4. Min time is the minimun time to invalidate the output and the max time is the maximum time to put the data in Hi-Z.

63/78

Electrical parameters

Figure 34. SPI slave timing diagram with CPHA=0

STR71xF

1)

SS

INPUT

t

su(SS)

c(SCK)

t

h(SS)

CPHA=0

CPOL=0

CPHA=0

CPOL=1

t

w(SCKH)

w(SCKL)

t

dis(SO)

a(SO)

v(SO)

h(SO)

t

r(SCK)

f(SCK)

MISO

OUTPUT

INPUT

MSB OUT

BIT6 OUT

LSB OUT

t

h(SI)

su(SI)

MSB IN

BIT1 IN

LSB IN

MOSI

1)

Figure 35. SPI slave timing diagram with CPHA=1

SS

INPUT

t

su(SS)

c(SCK)

t

h(SS)

CPHA=1

CPOL=0

CPHA=1

CPOL=1

t

w(SCKH)

w(SCKL)

t

dis(SO)

a(SO)

t

h(SO)

v(SO)

t

r(SCK)

f(SCK)

MISO

OUTPUT

INPUT

MSB OUT

BIT6 OUT

LSB OUT

t

h(SI)

su(SI)

MSB IN

BIT1 IN

LSB IN

MOSI

1)

Figure 36. SPI master timing diagram

SS

INPUT

t

c(SCK)

CPHA = 0

CPOL = 0

CPHA = 0

CPOL = 1

CPHA = 1

CPOL = 0

CPHA = 1

CPOL = 1

t

w(SCKH)

w(SCKL)

t

r(SCK)

f(SCK)

t

h(MI)

su(MI)

MISO

INPUT

MSB IN

BIT6 IN

LSB IN

t

v(MO)

h(MO)

MSB OUT

BIT6 OUT

LSB OUT

MOSI

OUTPUT

1. Measurement points are done at CMOS levels: 0.3xV₃₃and 0.7xV₃₃

64/78

STR71xF

Electrical parameters

4.3.10

USB characteristics

The USB interface is USB-IF certified (Full Speed).

Table 39. USB startup time

Symbol

Parameter

Conditions

Max

Unit

t_STARTUP

USB transceiver startup time

1

µs

Table 40. USB DC characteristics

Symbol

Parameter

Conditions

Input Levels

Min.⁽¹⁾⁽²⁾Max.⁽¹⁾⁽²⁾Unit

V_DI

Differential Input Sensitivity

I(DP, DM)

0.2

Differential Common Mode

Range

V_CM

Includes V_DIrange

0.8

1.3

2.5

2.0

V

Single Ended Receiver

Threshold

V_SE

Output Levels

V_OL

V_OH

Static Output Level Low

Static Output Level High

R_Lof 1.5 kΩ to 3.6V⁽³⁾

0.3

3.6

(3)

R_Lof 15 kΩ to V_SS

2.8

1. All the voltages are measured from the local ground potential.

2. It is important to be aware that the DP/DM pins are not 5 V tolerant. As a consequence, in case of a a

shortcut with Vbus (typ: 5.0V), the protection diodes of the DP/DM pins will be direct biased . This will not

damage the device if not more than 50 mA is sunk for longer than 24 hours but the reliability may be

affected.

R_Lis the load connected on the USB drivers

3.

Figure 37. USB: data signal rise and fall time

Differential

Data Lines

Crossover

points

V_CRS

V

SS

t

r

f

Table 41.

Symbol

USB: Full speed driver electrical characteristics

Parameter

Conditions

Min

Max

Unit

t_r

t_f

Rise time⁽¹⁾

Fall Time¹⁾

C_L=50 pF

t_r/t_f

4

20

ns

%

V

t_rfm

V_CRS

Rise/ Fall Time matching

Output signal Crossover Voltage

90

1.3

110

2.0

Measured from 10% to 90% of the data signal. For more detailed information, please refer to USB

Specification - Chapter 7 (version 2.0).

1.

65/78

Electrical parameters

STR71xF

4.3.11

ADC characteristics

Subject to general operating conditions for AV , f

, and T unless otherwise specified.

A

DD PCLK2

Table 42. ADC characteristics

Typ ¹⁾

Symbol

Parameter

Conditions

Min

Max

Unit

Modulator Oversampling

frequency

f_MOD

2.1

2.5

MHz

V

Conversion voltage range ²⁾³⁾

V_AIN

0

V_IN<V_SS,| I_IN|<

400µA on adjacent

analog pin

Negative input leakage current on

analog pins

I_lkg

5

6

µA

PBR

Passband Ripple

0.1

dB

MΩ

pF

SINAD S/N and Distortion

56

60

1

63

74

THD

Z_IN

Total Harmonic Distortion

Input Impedance

f_MOD= 2 MHz

C_ADC

Internal sample and hold capacitor

3.2

2048/

Total Conversion time (including

sampling time)

t_CONV

f_MOD

(max)

T_A= 27 °C

Normal mode

Standby mode

2.5

3.0

1

mA

I_ADC

µA

Notes:

1. Unless otherwise specified, typical data are based on T_A=25°C and AV_DD-AV_SS=3.3V. They are given only

as design guidelines and are not tested.

2. Any added external serial resistor will downgrade the ADC accuracy (especially for resistance greater than

10kΩ). Data based on characterization results, not tested in production.

3. Calibration is needed once after each power-up.

66/78

STR71xF

Electrical parameters

Table 43. ADC accuracy with f

= 20 MHz, f

=10 MHz, AV =3.3 V

ADC DD

PCLK2

Symbol

Parameter

Conditions

Min

2370

1480

Typ

Max

2565

1680

Unit

Converted code when AIN=0V ¹⁾

Converted code when AIN=2.5V ¹⁾

Dec-

imal

code

ADC_DATA(0V)

ADC_DATA(2.5V)

Center voltage of Sigma-Delta

Modulator¹⁾

VCM

TUE

1.23

1.25

1.30

V

In this type of ADC, calibration is necessary to correct

gain error and offset errors. Once calibrated, the TUE is

limited to the ILE.

Total unadjusted error

Differential linearity error¹⁾

Integral linearity error ¹⁾

|E_D|

|E_L|

1.96

2.36

2.19

3.95

LSB

1. Data based on characterisation, not tested in production.

ADC Accuracy vs. Negative Injection Current: Injecting negative current on any of the standard (non-

robust) analog input pins should be avoided as this significantly reduces the accuracy of the conversion

being performed on another analog input. It is recommended to add a Schottky diode (pin to ground) to

standard analog pins which may potentially inject negative current. The effect of negative injection current

on robust pins is specified in Section 4.3.5.

Any positive injection current within the limits specified for I_INJ(PIN)and ΣI_INJ(PIN)in Section 4.3.5 does not

affect the ADC accuracy.

Figure 38. ADC accuracy characteristics

4095

4094

4093

(2)

(3)

(1)

ADC_DATA(0V)

ADC_DATA(2.5V)

5

4

3

2

1

E

L

Out of range

E

D

1 LSB

IDEAL

0

1

2

3

4093 4094 4095

AV

1633

VCM

3100 3101 3102 3103

AV

SS

DD

V

(LSB

)

IDEAL

AIN

(1) Example of an actual transfer curve

(2) The ideal transfer curve

AVDD – AVSS

(3) End point correlation line

1LSB

= -----------------------------------------------

IDEAL

4095

E =Differential Linearity Error: maximum deviation between actual steps and the

D

ideal one.

E =Integral Linearity Error: maximum deviation between any actual transition and

L

the end point correlation line.

67/78

Electrical parameters

STR71xF

Analog power supply and reference pins

The AV and AV pins are the analog power supply of the A/D converter cell. They act as

DD

SS

the high and low reference voltages for the conversion.

Separation of the digital and analog power pins allow board designers to improve A/D

performance. Conversion accuracy can be impacted by voltage drops and noise in the event

of heavily loaded or badly decoupled power supply lines (see: General PCB design

guidelines).

General PCB design guidelines

To obtain best results, some general design and layout rules should be followed when

designing the application PCB to shield the noise-sensitive, analog physical interface from

noise-generating CMOS logic signals.

●

Use separate digital and analog planes. The analog ground plane should be connected

to the digital ground plane via a single point on the PCB.

●

Filter power to the analog power planes. It is recommended to connect capacitors, with

good high frequency characteristics, between the power and ground lines, placing

0.1 µF and optionally, if needed 10 pF capacitors as close as possible to the STR7

power supply pins and a 1 to 10 µF capacitor close to the power source (see

Figure 39).

●

The analog and digital power supplies should be connected in a star network. Do not

use a resistor, as AV is used as a reference voltage by the A/D converter and any

DD

resistance would cause a voltage drop and a loss of accuracy.

Properly place components and route the signal traces on the PCB to shield the analog

inputs. Analog signals paths should run over the analog ground plane and be as short

as possible. Isolate analog signals from digital signals that may switch while the analog

inputs are being sampled by the A/D converter. Do not toggle digital outputs near the

A/D input being converted.

Software filtering of spurious conversion results

For EMC performance reasons, it is recommended to filter A/D conversion outliers using

software filtering techniques.

Figure 39. Power supply filtering

STR710

1 to 10µF

0.1µF

V

SS

33

STR7

DIGITAL NOISE

FILTERING

V

33

POWER

SUPPLY

SOURCE

(3.3V)

AV

0.1µF

DD

EXTERNAL

NOISE

FILTERING

SS

68/78

STR71xF

Package characteristics

5

Package characteristics

5.1

Package mechanical data

Figure 40. 64-Pin low profile quad flat package (10x10)

mm

inches

Dim.

Min Typ Max Min Typ Max

D

A

1.60

0.063

0.006

D1

A2

A1 0.05

0.15 0.002

A1

A2 1.35 1.40 1.45 0.053 0.055 0.057

b

c

0.17 0.22 0.27 0.007 0.009 0.011

0.09 0.20 0.004 0.008

b

e

D

12.00

10.00

12.00

10.00

0.50

0.472

0.394

0.472

0.394

0.020

3.5°

E1

E

D1

E

E1

e

θ

0°

3.5°

7°

0°

7°

c

L1

L

0.45 0.60 0.75 0.018 0.024 0.030

1.00 0.039

Number of Pins

64

h

L1

L

N

Recommended footprint (dimensions in mm)

1

69/78

Package characteristics

Figure 41. 144-Pin low profile quad flat package

STR71xF

(1)

mm

inches

Dim.

Min Typ Max Min Typ Max

D

A

1.60

0.063

0.006

0.057

0.011

0.008

D1

D3

A1 0.05

0.15 0.002

A

A2

A2 1.35 1.40 1.45 0.053

A1

b

c

0.17 0.22 0.27 0.007

0.09 0.20 0.004

108

109

73

72

0.08 mm

.003 in.

Seating Plane

b

D

21.80 22.00 22.20 0.858 0.867 0.874

b

D1 19.80 20.00 20.20 0.780 0.787 0.795

E

E1

E3

D3

E

17.50

0.689

21.80 22.00 22.20 0.858 0.867 0.874

E1 19.80 20.00 20.20 0.780 0.787 0.795

37

144

E3

e

17.50

0.50

3.5°

0.689

0.020

3.5°

1

36

c

e

K

0°

7°

0°

7°

L1

L

0.45 0.60 0.75 0.018 0.024 0.030

1.00 0.039

Number of Pins

144

h

L1

N

Jedec Ref. MS-026-BFB

1.Values in inches are converted from mm and

rounded to 3 decimal digits.

Recommended footprint (dimensions in mm)

70/78

STR71xF

Package characteristics

Figure 42. 64-Low profile fine pitch ball grid array package

mm

inches

Dim.

Min Typ Max Min Typ Max

A

1.210

1.700 0.048

0.011

0.067

A1 0.270

A2

1.120

0.044

b

D

0.450 0.500 0.550 0.018 0.020 0.022

7.750 8.000 8.150 0.305 0.315 0.321

D1

E

5.600

7.750 8.000 8.150 0.305 0.315 0.321

5.600 0.220

0.220

E1

e

0.720 0.800 0.880 0.028 0.031 0.035

1.050 1.200 1.350 0.041 0.047 0.053

f

ddd

0.120

0.005

Number of Pins

64

N

Figure 43. 144-low profile fine pitch ball grid array package

1)

mm

Min Typ Max

inches

Dim.

A

Min

Typ

Ma

1.21

1.70 0.0476

0.0083

0.06

A1 0.21

A2

1.085

0.0427

b

D

0.35 0.40 0.45 0.0138 0.0157 0.01

9.85 10.00 10.15 0.3878 0.3937 0.39

D1

E

8.80

0.3465

9.85 10.00 10.15 0.3878 0.3937 0.39

E1

e

8.80

0.80

0.60

0.3465

0.0315

0.0236

F

ddd

eee

fff

0.10

0.15

0.08

0.00

Number of Pins

N

144

1

Values in inches are converted from mm and

rounded to 4 decimal digits.

Figure 44. Recommended PCB design rules (0.80/0.75mm pitch BGA)

Dpad

Dsm

0.37 mm

0.52 mm typ. (depends on solder

mask registration tolerance

Solder paste 0.37 mm aperture diameter

– Non solder mask defined pads are recommended

– 4 to 6 mils screen print

Dpad

Dsm

71/78

Package characteristics

STR71xF

5.2

Thermal characteristics

The average chip-junction temperature, T , in degrees Celsius, may be calculated using the

J

following equation:

T = T + (P x Θ )

(1)

J

A

D

JA

Where:

●

T is the Ambient Temperature in °C,

A

Θ

is the Package Junction-to-Ambient Thermal Resistance, in °C/W,

JA

P is the sum of P

and P (P = P

+ P ),

INT I/O

D

INT

I/O

D

P

is the product of I and V , expressed in Watts. This is the Chip Internal Power.

DD DD

INT

P

represents the Power Dissipation on Input and Output Pins;

I/O

Most of the time for the application P < P and can be neglected. On the other hand, P

I/O

INT

may be significant if the device is configured to drive continuously external modules and/or

memories.

An approximate relationship between P and T (if P is neglected) is given by:

D

J

I/O

P = K / (T + 273°C)

(2)

D

J

Therefore (solving equations 1 and 2):

2

K = P x (T + 273°C) + Θ x P

D

(3)

D

A

JA

where:

K is a constant for the particular part, which may be determined from equation (3) by

measuring P (at equilibrium) for a known T Using this value of K, the values of P and T

J

D

A.

D

may be obtained by solving equations (1) and (2) iteratively for any value of T .

A

Table 44. Thermal characteristics

Symbol

Parameter

Value

Unit

Thermal Resistance Junction-Ambient

LQFP 144 - 20 x 20 mm / 0.5 mm pitch

Θ_JA

42

°C/W

Thermal Resistance Junction-Ambient

LQFP 64 - 10 x 10 mm / 0.5 mm pitch

Θ_JA

45

58

50

°C/W

Thermal Resistance Junction-Ambient

LFBGA 64 - 8 x 8 x 1.7mm

Thermal Resistance Junction-Ambient

LFBGA 144 - 10 x 10 x 1.7mm

72/78

STR71xF

Product history

6

Product history

There are three versions of the STR710F series products. All versions are functionally

identical and differ only with the points listed below.

Version "A" was the first version produced and delivered. Version "Z" was the second in

production replacing version "A". Version "Z" has lower power consumption in STOP mode.

Version "X" is the latest introduced.

Marking

The difference between versions is visible on the marking of the product as shown in the

four examples in Figure 45 through Figure 48.

Figure 45. LQFP144 STR710 version “A”

Figure 46. LQFP64 STR712 version “Z”

A

Z

STR712FR2

T6

2208JVG

MLT225571

STR710FZ2T6

2208JVG

MLT225571

73/78

Product history

STR71xF

Figure 47. BGA144 STR710 version “Z”

Figure 48. BGA64 STR711 version “X”

R711R1H6

2208JVG

R710Z2H6

MLT225571

X

2208JVG Z

MLT 22 551

Table 45. A, Z and X version differences

Feature

A version

Z version

X version

ARM7TDMI core device

Identification (ID) code register

(see ARM7TDMI Technical

Reference Manual)

Version bits [31:28] =

0001

Version bits [31:28] =

0010

Version bits [31:28] = 0010

50 µA maximum at 25°C.

Not guaranteed

Typical 49 µA

Low power mode consumption in

STOP mode at 25 °C

Same as Z.

Less than 30 µA at 25 °C

for 99.730020% of parts

P0.10/U1.RX/U1.TX/SC.

DATA has been modified

to offer TRUE OPEN

DRAIN functionality

when in Smartcard

mode. When addressing

5V cards, the SCDATA

Not TRUE open drain

SC.DATA pin

When addressing 5V cards, the SCDATA

line can now be

Line must be connected to an open drain buffer.

connected directly to the

card I/O. This

modification is backward

compatible with previous

designs, and no board

modification is required.

74/78

STR71xF

Ordering information

7

Ordering information

Figure 49. STR71xF ordering information scheme

Example:

STR71

0

F

Z

1

T

6

Product class

STR71x microcontroller

Peripheral set

0 = full peripheral set

1 = No EMI, no CAN

2 = No EMI, no USB

5 = No EMI, no USB, no CAN

Program memory type

F = Flash

Pin count

R = 64 pins

Z = 144 pins

Program memory size

0 = 64+16K

1 = 128+16K

2 = 256+16K

no character = 0K

Package type

H = LFBGA

T = LQFP

Temperature range

1 = 0 °C to 70 °C

3 = -40 °C to 125 °C

6 = -40 °C to 85 °C

Packing

no character = tray or tube

TR = tape and reel

For a list of available options (e.g. memory size, package) and orderable part numbers or for

further information on any aspect of this device, please go to www.st.com or contact the ST Sales

Office nearest to you.

75/78

Revision history

STR71xF

8

Revision history

Table 46. Document revision history

Date

Revision

Changes

17-Mar-2004

05-Apr-2004

08-Apr-2004

15-Apr-2004

1

First Release

2

Updated “Electrical parameters” on page 33

Corrected STR712F Pinout. Pins 43/42 swapped.

PDF hyperlinks corrected.

2.1

2.2

Corrected description of STDBY, V18, VSS18 V18BKP

VSSBKP pins

Added IDDrun typical data

7-Jul-2004

3

4

Updated BSPI max. baudrate.

Updated “EMI - external memory interface” on page 56

Corrected Flash sector B1F0/F1 address in Figure 6: Memory

map on page 30

Corrected Table 7 on page 24 LQFP64 TEST pin is 16 instead

of 17. Added to TQPFP64 column: pin 7 BOOTEN, pin 17

V_33IO-PLL

29-Oct-2004

Changed description of JTCK from ‘External pull-down

required’ to ‘External pull-up or pull down required’.

Changed “Product Preview” to “Preliminary Data” on page 1

and 3

Renamed ‘PU/PD’ column to ‘Reset state’ in Table 7 on

page 24

25-Jan-2005

19-Apr-2005

5

6

Added reference to STR7 Flash Programming Reference

Manual

Added STR715F devices and modified RAM size of STR71xF1

devices

Added BGA package in Section 5

Updated ordering information in Section 7.

Added PLL duty cycle min and max. in PLL electrical

characteristics on page 44

Updated feature description on page 1

Update overview Section 1.1

Added OD/PP to P0.12 in Table 7

Changed name of WFI mode to WAIT mode

13-Oct-2005

7

Changed Memory Map Table 6: Ext. Memory changed to 64 MB

and flash register changed to 36 bytes.

Added Power Consumption Table 15

Modified BGA144 F3, F5, F12 and G12 in Table 3 and Table 4

Update EMI Timing Table 26 and Figure 29

76/78

STR71xF

Revision history

Table 46. Document revision history (continued)

Date

Revision

Changes

Added Flashless device.

Changed reset state of pins P1.10 and P1.13 from pu to pd,

P0.15 from pu to floating and removed x in interrupt column for

P1.15 and P1.12 in Table 4 and Table 7

22-May-2006

8

Added notes under Table 4 on EMI pin reset state.

Corrected inch value for d3 in Figure 40

Added footprint diagrams in Figure 40 and Figure 43

Updated Section 4: Electrical parameters

Flash data retention changed to 20 years at 85° C.

Changed note 8 on page 19

01-Aug-2006

06-Nov-2006

20-Mar-2007

9

Changed note 1 on page 45

Added STR715FR0T1 in Table 42: Order codes

P0.12 corrected in Table 7 on page 24

10

11

Added characteristics of BSPI - buffered serial peripheral

interface on page 63

Updated Table 23: Low-power mode wakeup timing on page 45

Updated ordering information

Updated USB characteristics

13-Feb-2008

12

Updated external clock characteristics

77/78

STR71xF

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78/78


型号：	STR710FR2H1
厂家：	ST
描述：	32-BIT, FLASH, 66MHz, RISC MICROCONTROLLER, PBGA64, 8 X 8 MM, 1.70 MM HEIGHT, LFBGA-64
文件：	总78页 (文件大小：2014K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

STR710FR2H1 [STMICROELECTRONICS]

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