STR731FV2T6 [STMICROELECTRONICS]
ARM7TDMI 32-bit MCU with Flash, 3x CAN, 4 UARTs, 20 timers, ADC, 12 comm. interfaces; ARM7TDMI的32位MCU配备闪光灯, 3倍CAN , 4个UART , 20定时器, ADC , 12 COMM 。 INTERFACES型号: | STR731FV2T6 |
厂家: | ST |
描述: | ARM7TDMI 32-bit MCU with Flash, 3x CAN, 4 UARTs, 20 timers, ADC, 12 comm. interfaces |
文件: | 总53页 (文件大小:1519K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
STR73xF
ARM7TDMI™ 32-bit MCU with Flash, 3x CAN,
4 UARTs, 20 timers, ADC, 12 comm. interfaces
■ Core
– ARM7TDMI 32-bit RISC CPU
– 32 MIPS @ 36 MHz
■ Memories
TQFP100 14 x 14
– Up to 256 Kbytes FLASH program memory
(10,000 cycles endurance, data retention
20 years @ 85° C)
TQFP144
20 x 20
LFBGA144 10 x 10 x 1.7
– 16 Kbytes RAM
■ Clock, reset and supply management
– 4.5 - 5.5V application supply and I/Os
– Embedded 1.8V regulator for core supply
■ DMA
– 4 DMA controllers with 4 channels each
■ Timers
– Embedded oscillator running from external
4-8MHz crystal or ceramic resonator
– 16-bit watchdog timer (WDG)
– 6/10 16-bit timers (TIM) each with: 2 input
captures, 2 output compares, PWM and
pulse counter modes
– 6 16-bit PWM modules (PWM)
– 3 16-bit timebase timers with 8-bit
prescalers
– Up to 36 MHz CPU freq. with internal PLL
– Internal RC oscillator 32kHz or 2MHz
software configurable for fast startup and
backup clock
– Realtime Clock for clock-calendar function
– Wakeup Timer driven by internal RC for
wakeup from STOP mode
■ 12 communications interfaces
2
– 5 power saving modes: SLOW, WFI,
LPWFI, STOP and HALT modes
– 2 I C interfaces
– 4 UART asynchronous serial interfaces
– 3 BSPI synchronous serial interfaces
– Up to 3 CAN interfaces (2.0B Active)
■ Nested interrupt controller
– Fast interrupt handling with multiple vectors
– 64 maskable IRQs with 64 vectors and 16
priority levels
– 2 maskable FIQ sources
■ 10-bit A/D converter
– 12/16 channels
– Conversion time: min. 3 µs, range: 0 to 5V
– 16 ext. interrupts, up to 32 wake-up lines
■ Development tools support
■ Up to 112 I/O ports
– JTAG interface
– 72/112 multifunctional bidirectional I/Os
Table 1.
Device summary
Features
STR730FZx
128K 256K
16K
STR735FZx
128K 256K
STR731FVx
STR736FVx
FLASH memory - bytes
64K
128K
256K
16K
64K
128K
256K
RAM - bytes
10 TIM Timers, 112 I/Os, 32 Wake-Up
lines, 16 ADC channels
6 TIM Timers, 72 I/Os, 18 Wake-Up lines,
12 ADC channels
Peripheral Functions
CAN Peripherals
Operating Voltage
3
0
3
0
4.5 to 5.5V
Operating Temperature
-40 to +85°C/-40 to +105°C
T=TQFP144 20 x 20
H=LFBGA144 10 x10
Packages
T=TQFP100 14x14
September 2006
Rev 6
1/53
www.st.com
53
Contents
STR73xF
Contents
1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.1
1.2
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
On-Chip Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.1
2.2
Related Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.2.1
2.2.2
2.2.3
STR730F/STR735F (TQFP144) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
STR730F/STR735F (LFBGA144) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
STR731F/STR736F (TQFP100) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.3
Memory Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3
Electrical parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.1
Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.1.1
3.1.2
3.1.3
3.1.4
3.1.5
Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.2
3.3
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.3.1
3.3.2
3.3.3
3.3.4
3.3.5
3.3.6
Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Clock and timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
I/O port pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
10-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
4
Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
4.1
4.2
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
5
Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
2/53
STR73xF
Contents
6
Known limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
6.1
6.2
Low Power Wait For Interrupt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
PLL free running mode at high temperature . . . . . . . . . . . . . . . . . . . . . . 51
7
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
3/53
Introduction
STR73xF
1
Introduction
This datasheet provides the STR73x Ordering Information, Mechanical and Electrical
Device Characteristics.
For complete information on the STR73xF Microcontroller memory, registers and
peripherals. please refer to the STR73x Reference Manual.
For information on programming, erasing and protection of the internal Flash memory
please refer to the STR7 Flash Programming Reference Manual
For information on the ARM7TDMI core please refer to the ARM7TDMI Technical Reference
Manual.
1.1
Overview
‚
ARM core with embedded Flash & RAM
™
STR73xF family combines the high performance ARM7TDMI CPU with an extensive range
of peripheral functions and enhanced I/O capabilities. All devices have on-chip high-speed
single voltage FLASH memory and high-speed RAM. The STR73xF family has an
embedded ARM core and is therefore compatible with all ARM tools and software.
Extensive tools support
STMicroelectronics’ 32-bit, ARM core-based microcontrollers are supported by a complete
range of high-end and low-cost development tools to meet the needs of application
developers. This extensive line of hardware/software tools includes starter kits and complete
development packages all tailored for ST’s ARM core-based MCUs.
The range of development packages includes third-party solutions that come complete with
a graphical development environment and an in-circuit emulator/programmer featuring a
JTAG application interface. These support a range of embedded operating systems (OS),
while several royalty-free OSs are also available.
For more information, please refer to ST MCU site http://www.st.com/mcu
Figure 1 shows the general block diagram of the device family.
Package Choice: Reduced Pin-Count TQFP100 or Feature-Rich 144-pin TQFP or
LFBGA
The STR73xF family is available in 3 packages. The TQFP144 and LFBGA144 versions
have the full set of all features. The 100-pin version has fewer timers, I/Os and ADC
channels. Refer to the Device Summary on Page 1 for a comparison of the I/Os available on
each package.
The family includes versions with and without CAN.
4/53
STR73xF
Introduction
High Speed Flash Memory
The Flash program memory is organized in 32-bit wide memory cells which can be used for
storing both code and data constants. It is accessed by CPU with zero wait states @ 36
MHz.
The STR7 embedded Flash memory can be programmed using In-Circuit Programming or
In-Application programming.
The Flash memory endurance is 10K write/erase cycles and the data retention is 20 years
@ 85° C.
IAP (In-Application Programming): The IAP is the ability to re-program the Flash memory
of a microcontroller while the user program is running.
ICP (In-Circuit Programming): The ICP is the ability to program the Flash memory of a
microcontroller using JTAG protocol while the device is mounted on the user application
board.
The Flash memory can be protected against different types of unwanted access
(read/write/erase). There are two types of protection:
●
Sector Write Protection
●
Flash Debug Protection (locks JTAG access)
Flexible Power Management
To minimize power consumption, you can program the STR73xF to switch to SLOW, WFI
LPWFI, STOP or HALT modes depending on the current system activity in the application.
Flexible Clock Control
Two clock sources are used to drive the microcontroller, a main clock driven by an external
crystal or ceramic resonator and an internal backup RC oscillator that operates at 2MHz or
32 kHz. The embedded PLL can be configured to generate an internal system clock of up to
36 MHz. The PLL output frequency can be programmed using a wide selection of multipliers
and dividers.
Voltage Regulators
The STR73xF requires an external 4.5 to 5.5V power supply. There are two internal Voltage
Regulators for generating the 1.8V power supply needed by the core and peripherals. The
main VR is switched off and the Low Power VR switched on when the application puts the
STR73xF in Low Power Wait for Interrupt (LPWFI) mode.
Low Voltage Detectors
The voltage regulator and Flash modules each have an embedded LVD that monitors the
internal 1.8V supply. If the voltage drops below a certain threshold, the LVD will reset the
STR73xF.
Note: An external power-on reset must be provided ensure the microcontroller starts-up
correctly.
5/53
Introduction
STR73xF
1.2
On-Chip Peripherals
CAN Interfaces
The three CAN modules are compliant with the CAN specification V2.0 part B (active). The
bit rate can be programmed up to 1 MBaud. These are not available in the STR735 and
STR736.
DMA
4 DMA controllers, each with 4 data streams manage memory to memory, peripheral to
peripheral, peripheral to memory and memory to peripheral transfers. The DMA requests
are connected to TIM timers, BSPI0, BSPI1, BSPI2 and ADC. One of the streams can be
configured to be triggered by a software request, independently from any peripheral activity.
16-bit Timers (TIM)
Each of the ten timers (six in 100-pin devices) have a 16-bit free-running counter with 7-bit
prescaler, up to two input capture/output compare functions, a pulse counter function, and a
PWM channel with selectable frequency. This provides a total of 16 independent PWMs (12
in 100-pin devices) when added with the PWM modules (see next paragraph).
PWM Modules (PWM)
The six 16-bit PWM modules have independently programmable periods and duty-cycles,
with 5+3 bit prescaler factor.
Timebase Timers (TB)
The three 16-bit Timebase Timers with 8-bit prescaler for general purpose time triggering
operations.
Realtime Clock (RTC)
The RTC provides a set of continuously running counters driven by separate clock signal
derived from the main oscillator. The RTC can be used as a general timebase or
clock/calendar/alarm function. When the STR73xF is in LPWFI mode the RTC keeps
running, powered by the low power voltage regulator.
UARTs
The 4 UARTs allow full duplex, asynchronous, communications with external devices with
independently programmable TX and RX baud rates up to 625K baud.
Buffered Serial Peripheral Interfaces (BSPI)
Each of the three BSPIs allow full duplex, synchronous communications with external
devices, master or slave communication at up 6 Mb/s (@36 MHz System Clock).
2
I C Interfaces
2
The two I C Interfaces provide multi-master and slave functions, support normal and fast
2
I C mode (400 kHz) and 7 or 10-bit addressing modes.
A/D Converter
The 10-bit Analog to Digital Converter, converts up to 16 channels in single-shot or
continuous conversion modes (12 channels in 100-pin devices). The minimum conversion
time is 3us.
6/53
STR73xF
Introduction
Watchdog
The 16-bit Watchdog Timer protects the application against hardware or software failures
and ensures recovery by generating a reset.
I/O Ports
Up to 112 I/O ports (72 in 100-pin devices) are programmable as general purpose
input/output or Alternate Function.
External Interrupts and Wake-Up Lines
16 external interrupts lines are available for application use. In addition, up to 32 external
Wakeup lines (18 in 100-pin devices) can be used as general purpose interrupts or to wake-
up the application from STOP mode.
7/53
Block Diagram
STR73xF
2
Block Diagram
Figure 1.
STR730F/STR735F block diagram
RSTIN
PRCCU/PLL
FLASH
M0
M1
TEST
Program Memory
64/128/256K
ARM7TDMI
CPU
RAM
16K
JTDI
JTCK
JTMS
JTRST
JTDO
JTAG
APB
BRIDGE 0
V18
VDD
POWER SUPPLY
VREG
APB
BRIDGE 1
VSS
VDDA
VSSA
AHB
BRIDGE
AHB BUS
DMA0-3
WATCHDOG
CLOCK MGT (CMU)
XTAL1
XTAL2
4 AF
32 AF
8 AF
I2C0-1
OSC
RTC
WAKEUP/INT (WIU)
UART0, 1, 2, 3
INTERRUPT CTL (EIC)
A/D CONVERTER (ADC)
16 AF
12 AF
TIMEBASE TIMER
(TB) 0-2
TIMER (TIM) 2-4
WAKEUP TIMER
(WUT)
12 AF
6 AF
BSPI 0-2
CAN 0-2*
PWM 0-5
8 AF
TIMER (TIM) 0-1
TIMER (TIM) 5-9
20 AF
6 AF
122 ports
GPIO PORTS 0-6
AF: alternate function on I/O port pin
*CAN peripherals not available on STR735F.
8/53
STR73xF
Block Diagram
Figure 2.
STR731F/STR736 block diagram
RSTIN
PRCCU/PLL
FLASH
M0
M1
TEST
Program Memory
64/128/256K
ARM7TDMI
CPU
RAM
16K
JTDI
JTCK
JTMS
JTRST
JTDO
JTAG
APB
BRIDGE 0
V18
VDD
VSS
POWER SUPPLY
VREG
APB
BRIDGE 1
VDDA
VSSA
AHB
BRIDGE
AHB BUS
DMA0-3
WATCHDOG
CLOCK MGT (CMU)
XTAL1
XTAL2
4 AF
I2C0-1
OSC
RTC
18 AF
8 AF
WAKEUP/INT (WIU)
UART0, 1, 2, 3
INTERRUPT CTL (EIC)
A/D CONVERTER (ADC)
12 AF
12 AF
TIMEBASE TIMER
(TB) 0-2
TIMER (TIM) 2-4
WAKEUP TIMER
(WUT)
12 AF
6 AF
BSPI 0-2
CAN 0-2*
PWM 0-5
8 AF
4 AF
TIMER (TIM) 0-1
TIMER (TIM) 5
6 AF
72 ports
GPIO PORTS 0-6
AF: alternate function on I/O port pin
*CAN peripherals not available on STR736F.
9/53
Block Diagram
STR73xF
2.1
Related Documentation
Available from www.arm.com:
ARM7TDMI Technical Reference Manual
Available from http://www.st.com:
STR73x Reference Manual
STR7 Flash Programming Reference Manual
STR73x Software Library User Manual
For a list of related application notes refer to http://www.st.com.
10/53
STR73xF
Block Diagram
2.2
Pin description
2.2.1
STR730F/STR735F (TQFP144)
Figure 3.
STR730F/STR735F pin configuration (top view)
1
2
3
4
5
6
7
8
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
OCMPB2 / P0.0
OCMPA2 / P0.1
ICAPA2 / P0.2
ICAPB2 / P0.3
VSS
P4.14 / SS1
P4.13 / ICAPB9
P4.12 / ICAPA9 / WUP21
P4.11 / OCMPB8
P4.10 / ICAPA6 / WUP20
P4.9 / ICAPB6
P4.8 / OCMPA8
P4.7 / SDA1
P4.6 / SCL1 / WUP19
P4.5 / CAN2RX / WUP18
P4.4 / CAN2TX
P4.3 / ICAPB8 / WUP27
P4.2 / ICAPA8 / WUP26
P4.1 / ICAPB7 / WUP25
P4.0 / ICAPA7 / WUP24
VDD
VSS
JTDO
JTCK
JTMS
JTDI
JTRST
VSS
VDD
P3.15 / AIN15 / INT5
P3.14 / AIN14 / INT4
P3.13 / AIN13 / INT3
P3.12 / AIN12 / INT2
P3.11 / AIN11
P3.10 / AIN10
P3.9 / AIN9
P3.8 / AIN8
VDDA
VSSA
P3.7 / AIN7
VDD
OCMPA5 / P0.4
OCMPB5 / P0.5
ICAPA5 / P0.6
ICAPB5 / P0.7
OCMPA6 / P0.8
OCMPB6 / P0.9
OCMPA7 / P0.10
OCMPB7 / P0.11
VDD
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
VSS
ICAPA3 / P0.12
ICAPB3 / P0.13
OCMPB3 / P0.14
OCMPA3 / P0.15
OCMPA4 / P1.0
OCMPB4 / P1.1
ICAPB4 / P1.2
ICAPA4 / P1.3
VSS
STR730F/STR735F
VDD
P1.4
P1.5
OCMPB1 / P1.6
OCMPA1 / P1.7
INT0 / OCMPA0 / P1.8
INT1 / OCMPB0 / P1.9
ICAPB0 / WUP28 / P1.10
ICAPA0 / WUP29 / P1.11
ICAPA1 / WUP30 / P1.12
ICAPB1 / WUP31 / P1.13
74
73
P3.6 / AIN6
Note 1: CAN alternate functions not available on STR735F.
11/53
Block Diagram
STR73xF
2.2.2
STR730F/STR735F (LFBGA144)
Table 2.
Ball
STR730F/STR735F LFBGA ball connections
Name
Ball
Name
Ball
Name
Ball
Name
A1
A2
P0.0 / OCMPB2
P6.10 / WUP8
P6.9 / TDO0
P6.12 / MOSI0
P6.6 / WUP6
V18
B1
B2
B3
P0.4 / OCMPA5
P0.1 / OCMPA2
P6.15 / WUP9
C1
C2
C3
P0.5 / OCMPB5
P0.2 / ICAPA2
P0.3 / ICAPB2
P6.14 / SSO
P6.8 / RDI0 / WUP10
P6.3 / WUP3
VSS
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
VSS
VDD
A3
P0.6 / ICAPA5
P0.7 /ICAPB5
P6.11 / MISO0
P6.4 / WUP4 /TDO3
VDD
A4
B4 P6.13 / SCKO / WUP11 C4
A5
B5
B6
P6.7 / WUP7
P6.2 / WUP2 / RDI3
P5.14 / INT12
P5.9 / INT7
C5
C6
A6
A7
P5.15 / INT13
P5.8 / INT6
B7
C7
A8
B8
C8
P5.10 / INT8 / RDI2
P5.4 / SS2
P5.12 / INT10
P5.5 / SCK2 / WUP23
P4.13 / ICAPB9
A9
P5.2 / OCMPA9
P5.7 / MISO2
P5.6 / MOSI2
B9
P5.3 / OCMPB9
P5.0 / MOSI1
C9
A10
A11
B10
C10
P5.1 / MISO1
P4.14 / SS1
P4.7 / SDA1
VSS
B11 P4.15 / SCK1 / WUP22 C11
D11 P4.12 / ICAPA9 / WUP21
A12
E1
E2
E3
E4
E5
E6
P5.11 / TDO2 / INT9
P0.8 / OCMPA6
P0.9 / OCMPB6
P0.10 / OCMPA7
P0.11 / OCMPB7
P0.12 / ICAPA3
P6.5 / WUP5
B12
F1
F2
F3
F4
F5
F6
P4.8 / OCMPA8
VDD
C12
G1
G2
G3
G4
G5
G6
D12
H1
H2
H3
H4
H5
H6
P4.11 / OCMPB8
VDD
P0.13 / ICAPB3
P0.14 / OCMPB3
P0.15 / OCMPA3
P1.0 / OCMPA4
P1.1 / OCMPB4
P1.2 / ICAPB4
P1.3 / ICAPA4
VSS
P1.8 / OCMPA0 / INT0
P1.9 / OCMPB0 / INT1
P1.10 / ICAPB0 / WUP28
XTAL2
P1.5
P2.11 / WUP17
P2.10 / WUP16
P4.0 / ICAPA7 /
WUP24
E7
E8
E9
P6.0 / WUP0
P5.13 / INT11
F7
F8
F9
P6.1 / WUP1
G7
G8
G9
H7
H8
H9
P2.15 / SDA 0
JTMS
P4.4 / CAN2TX1)
VDD
P4.10 / ICAPA6 /
WUP20
P4.3 / ICAPB8 /
WUP27
VSS
VSS
P4.2 / ICAPA8 /
WUP26
E10
P4.9 / ICAPB6
F10
G10
G11
G12
L1
JTDO
JTCK
H10
H11
H12
M1
VDD
P4.1 / ICAPB7 /
WUP25
E11 P4.6 / SCL1 / WUP19 F11
P4.5 / WUP18 /
P3.15 / AIN15 / INT5
P3.14 / AIN14 / INT4
E12
F12
JTDI
nJTRST
CAN2RX1)
P1.14 / CAN0RX1)
WUP12
/
J1
P1.4
K1
P1.6 / OCMPB1
P1.7 / OCMPA1
P1.15 / CAN0TX1)
P2.0 / PWM0
P1.11 / ICAPA0 /
WUP29
P1.13 / ICAPB1 /
WUP31
P2.1 / CAN1RX1)
WUP13
J2
K2
L2
M2
P2.4 / PWM2
P1.12 / ICAPA1 /
WUP30
/
J3
K3
L3
M3
P2.5 / PWM3
J4
J5
J6
P2.7 / PWM5
VDD
K4
K5
K6
P2.6 / PWM4
M1
L4
L5
P2.3 / PWM1
RSTIN
M4
M5
P2.2 / CAN1TX1)
M0
P2.9 / RDI1 / WUP14
P2.8 / TDO1
P2.13 / INT15
P3.0 / AIN0
P3.4 / AIN4
VDDA
L6
VSS
M6
VSS
J7 P2.14 / SCL 0 / WUP15 K7
L7
P2.12 / INT14
VBIAS
M7
XTAL1
J8
J9
P3.1 / AIN1
P3.13 / AIN13 / INT3
P3.12 / AIN12 / INT2
P3.9 / AIN9
K8
K9
L8
M8
TST
L9
P3.3 / AIN3
P3.5 / AIN5
P3.7 / AIN7
P3.10 / AIN10
M9
P3.2 / AIN2
VSS
J10
J11
J12
K10
K11
K12
L10
L11
L12
M10
M11
M12
VSSA
VDD
P3.8 / AIN8
P3.11 / AIN11
P3.6 / AIN6
Note 1: CAN alternate functions not available on STR735F.
12/53
STR73xF
Block Diagram
2.2.3
STR731F/STR736F (TQFP100)
Figure 4.
STR731F/STR736F pin configuration (top view)
P4.14 / SS1
P4.10 / ICAPB5 / WUP20
P4.7 / SDA1
OCMPB2 / P0.0
OCMPA2 / P0.1
ICAPA2 / P0.2
ICAPB2 / P0.3
OCMPA5 / P0.4
OCMPB5 / P0.5
ICAPA5 / P0.6
1
2
3
4
5
6
7
8
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
P4.6 / SCL1 / WUP19
V
DD
V
SS
JTDO
JTCK
JTMS
JTDI
V
DD
V
9
SS
ICAPA3 / P0.12
ICAPB3 / P0.13
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
JTRST
V
OCMPB3 / P0.14
OCMPA3 / P0.15
OCMPA4 / P1.0
OCMPB4 / P1.1
ICAPB4 / P1.2
ICAPA4 / P1.3
OCMPB1 / P1.6
OCMPA1 / P1.7
SS
STR731F/STR736F
V
DD
P3.15 / AIN11 / INT5
P3.14 / AIN10 / INT4
P3.13 / AIN9 / INT3
P3.12 / AIN8 / INT2
P3.11 / AIN7
P3.10 / AIN6
P3.9 / AIN5
P3.8 / AIN4
INT0 / OCMPA0 / P1.8
INT1 / OCMPB0 / P1.9
ICAPB0 / WUP28 / P1.10
ICAPA0 / WUP29 / P1.11
ICAPA1 / WUP30 / P1.12
ICAPB1 / WUP31 / P1.13
V
DDA
V
SSA
P3.7 / AIN3
P3.6 / AIN2
Note 1: CAN alternate functions not available on STR736F.
13/53
Block Diagram
Legend / Abbreviations for Table 3:
STR73xF
Type:
I = input, O = output, S = supply, HiZ= high impedance,
In/Output level:
T = TTL 0.8V / 2V with input trigger
T
C = CMOS 0.3V /0.7V with input trigger
T
DD
DD
Port and control configuration:
Input:
pu/pd = with internal 100kΩ weak pull-up or pull down
Output:
OD = open drain (logic level)
PP = push-pull
Interrupts:
INTx =external interrupt line
WUPx =Wake-Up interrupt line
The reset state (during and just after the reset) of the I/O ports is input floating (Input Tristate
TTL mode). To avoid excess power consumption, unused I/O ports must be tied to ground.
Table 3.
Pin n°
STR73xF pin description
Input
Output
Main
functio
n
Pin Name
Alternate function
(after
reset)
1
2
3
4
5
6
7
8
9
A1
1
2
3
4
P0.0/OCMPB2 I/O TT
P0.1/OCMPA2 I/O TT
2mA
X
X
X
X
X Port 0.0 TIM2: Output Compare B output
X Port 0.1 TIM2: Output Compare A output
X Port 0.2 TIM2: Input Capture A input
X Port 0.3 TIM2: Input Capture B input
Ground
B2
C2
C3
D1
D2
B1
C1
D3
2mA
2mA
2mA
P0.2/ICAPA2
P0.3/ICAPB2
VSS
I/O TT
I/O TT
S
S
VDD
Supply voltage (5V)
5
6
7
P0.4/OCMPA5 I/O TT
P0.5/OCMPB5 I/O TT
2mA
2mA
2mA
2mA
2mA
2mA
X
X
X
X
X
X
X Port 0.4 TIM5: Output Compare A output
X Port 0.5 TIM5: Output Compare B output
X Port 0.6 TIM5: Input Capture A input
X Port 0.7 TIM5: Input Capture B input
X Port 0.8 TIM6: Output Compare A output
X Port 0.9 TIM6: Output Compare B output
Port
P0.6/ICAPA5
P0.7/ICAPB5
I/O TT
I/O TT
10 D4
11 E1
12 E2
P0.8/OCMPA6 I/O TT
P0.9/OCMPB6 I/O TT
13 E3
14 E4
P0.10/OCMPA7 I/O TT
2mA
2mA
X
X
X
TIM7: Output Compare A output
0.10
P0.11/OCMPB
7
Port
0.11
I/O TT
X
TIM7: Output Compare B output
15 F1
16 G1
8
9
VDD
VSS
S
S
Supply voltage (5V)
Ground
Port
0.12
17 E5 10 P0.12/ICAPA3
I/O TT
2mA
X
X
TIM3: Input Capture A input
14/53
STR73xF
Block Diagram
Table 3.
Pin n°
STR73xF pin description
Pin Name
Input
Output
Main
functio
n
Alternate function
(after
reset)
Port
0.13
18 F2 11 P0.13/ICAPB3 I/O TT
P0.14/OCMPB
2mA
X
X
X
X
X
X
TIM3: Input Capture B input
Port
0.14
19 F3 12
I/O TT
2mA
2mA
TIM3: Output Compare B output
TIM3: Output Compare A output
3
Port
0.15
20 F4 13 P0.15/OCMPA3 I/O TT
21 F5 14 P1.0/OCMPA4 I/O TT
22 F6 15 P1.1/OCMPB4 I/O TT
2mA
2mA
2mA
2mA
X
X
X
X
X Port 1.0 TIM4: Output Compare A output
X Port 1.1 TIM4: Output Compare B output
X Port 1.2 TIM4: Input Capture B input
X Port 1.3 TIM4: Input Capture A input
Ground
23 G2 16 P1.2/ICAPB4
24 G3 17 P1.3/ICAPA4
I/O TT
I/O TT
S
25 G4
26 H1
27 J1
28 G5
VSS
VDD
P1.4
P1.5
S
Supply voltage (5V)
I/O TT
I/O TT
2mA
2mA
2mA
2mA
2mA
2mA
X
X
X
X
X
X
X Port 1.4
X Port 1.5
29 K1 18 P1.6/OCMPB1 I/O TT
30 L1 19 P1.7/OCMPA1 I/O TT
31 H2 20 P1.8/OCMPA0 I/O TT
32 H3 21 P1.9/OCMPB0 I/O TT
X Port 1.6 TIM1: Output Compare B output
X Port 1.7 TIM1: Output Compare A output
X Port 1.8 TIM0: Output Compare A output
X Port 1.9 TIM0: Output Compare B output
Port
INT0
INT1
33 H4 22 P1.10/ICAPB0 I/O TT
WUP28 2mA
WUP29 2mA
WUP30 2mA
WUP31 2mA
WUP12 2mA
2mA
X
X
X
X
X
X
X
X
X
X
X
X
TIM0: Input Capture B input
TIM0: Input Capture A input
TIM1: Input Capture A input
TIM1: Input Capture B input
CAN0: Receive Data input
CAN0: Transmit Data output
1.10
Port
1.11
34 J2 23 P1.11/ICAPA0
35 J3 24 P1.12/ICAPA1
I/O TT
I/O TT
Port
1.12
Port
1.13
36 K2 25 P1.13/ICAPB1 I/O TT
37 M1 26 P1.14/CAN0RX I/O TT
38 L2 27 P1.15/CAN0TX I/O TT
Port
1.14
Port
1.15
39 L3 28 P2.0/PWM0
I/O TT
2mA
WUP13 2mA
2mA
X
X
X
X
X
X Port 2.0 PWM0: PWM output
X Port 2.1 CAN1: Receive Data input
X Port 2.2 CAN1: Transmit Data output
X Port 2.3 PWM1: PWM output
X Port 2.4 PWM2: PWM output
40 K3 29 P2.1/CAN1RX I/O TT
41 M4 30 P2.2/CAN1TX
42 L4 31 P2.3/PWM1
43 M2 32 P2.4/PWM2
I/O TT
I/O TT
I/O TT
2mA
2mA
15/53
Block Diagram
STR73xF
Table 3.
Pin n°
STR73xF pin description
Input
Output
Main
functio
n
Pin Name
Alternate function
(after
reset)
44 M3
45 K4
46 J4
P2.5/PWM3
P2.6/PWM4
P2.7/PWM5
I/O TT
I/O TT
I/O TT
2mA
X
X
X
X Port 2.5 PWM3: PWM output
X Port 2.6 PWM4: PWM output
X Port 2.7 PWM5: PWM output
BOOT: Mode selection 0 input
Reset input
2mA
2mA
47 M5 33 M0
48 L5 34 RSTIN
49 K5 35 M1
50 J5 36 VDD
51 M6 37 VSS
I
I
TT pd
CT pu
TT pd
I
BOOT: Mode selection 1 input
Supply voltage (5V)
S
S
Ground
Oscillator amplifier circuit input and
internal clock generator input.
52 M7 38 XTAL1
I
53 H5 39 XTAL2
54 L6 40 VSS
O
S
Oscillator amplifier circuit output.
Ground
CAN2:Receive
Data input
UART1:
X Port 2.8 Transmit Data
output
P2.8/TDO1/CA
N2RX
55 K6 41
I/O TT
2mA
X
X
(TQFP100
only)
CAN2:
UART1:
X Port 2.9 Receive Data
input
Transmit Data
output
(TQFP100
only)
P2.9/RDI1/CAN
2TX
56 J6 42
I/O TT
WUP14 2mA
Port
X
57 H6
58 G6
59 L7
60 K7
P2.10
P2.11
P2.12
P2.13
I/O TT
I/O TT
I/O TT
I/O TT
I/O TT
WUP16 2mA
WUP17 2mA
INT14 2mA
INT15 2mA
WUP15 2mA
2mA
X
X
X
X
X
X
2.10
Port
X
2.11
Port
X
2.12
Port
X
2.13
Port
2.14
61 J7 43 P2.14/SCL0
X
X
I2C0:Serial Clock
I2C0:Serial Data
Port
2.15
62 H7 44 P2.15/SDA0
63 M8 45 Test
I/O TT
I
pd
Reserved pin. Must be tied to ground
16/53
STR73xF
Block Diagram
Table 3.
Pin n°
STR73xF pin description
Pin Name
Input
Output
Main
functio
n
Alternate function
(after
reset)
Internal RC Oscillator bias. A 1.3MΩ
external resistor has to be connected to
this pin when a 32kHZ RC oscillator
frequency is used.
64 L8 46 VBIAS
S
65 M10 47 VSS
66 M11 48 VDD
S
Ground
S
Supply voltage (5V)
67 K8
68 J8
69 M9
70 L9
P3.0/AIN0
I/O TT
I/O TT
I/O TT
I/O TT
2mA
X
X
X
X
X Port 3.0 ADC: Analog input 0
X Port 3.1 ADC: Analog input 1
X Port 3.2 ADC: Analog input 2
X Port 3.3 ADC: Analog input 3
P3.1/AIN1
P3.2/AIN2
P3.3/AIN3
2mA
2mA
2mA
ADC: Analog input 4
X Port 3.4
71 K9 49 P3.4/AIN4
72 L10 50 P3.5/AIN5
73 M12 51 P3.6/AIN6
74 L11 52 P3.7/AIN7
I/O TT
I/O TT
I/O TT
I/O TT
2mA
2mA
2mA
2mA
X
X
X
X
(AIN0 in TQFP100)
ADC: Analog input 5
X Port 3.5
(AIN1 in TQFP100)
ADC: Analog input 6
X Port 3.6
(AIN2 in TQFP100)
ADC: Analog input 7
X Port 3.7
(AIN3 in TQFP100)
75 K11 53 VSSA
76 K10 54 VDDA
S
S
Reference ground for A/D converter
Reference voltage for A/D converter
ADC: Analog input 8
X Port 3.8
77 J12 55 P3.8/AIN8
78 J11 56 P3.9/AIN9
79 L12 57 P3.10/AIN10
80 K12 58 P3.11/AIN11
81 J10 59 P3.12/AIN12
82 J9 60 P3.13/AIN13
83 H12 61 P3.14/AIN14
I/O TT
I/O TT
I/O TT
I/O TT
I/O TT
I/O TT
I/O TT
2mA
2mA
2mA
2mA
2mA
2mA
2mA
2mA
X
X
X
X
X
X
X
X
(AIN4 in TQFP100)
ADC: Analog input 9
X Port 3.9
(AIN5 in TQFP100)
Port
3.10
ADC: Analog input 10
(AIN6 in TQFP100)
X
X
X
X
X
X
Port
3.11
ADC: Analog input 11
(AIN7 in TQFP100)
Port
3.12
ADC: Analog input 12
(AIN8 in TQFP100)
INT2
INT3
INT4
INT5
Port
3.13
ADC: Analog input 13
(AIN9 in TQFP100)
Port
3.14
ADC: Analog input 14
(AIN10 in TQFP100)
Port
3.15
ADC: Analog input 15
(AIN11 in TQFP100)
84 H11 62 P3.15/AIN15
85 H10 63 VDD
I/O TT
S
Supply voltage (5V)
17/53
Block Diagram
STR73xF
Table 3.
Pin n°
STR73xF pin description
Input
Output
Main
functio
n
Pin Name
Alternate function
(after
reset)
86 H9 64 VSS
87 G12 65 JTRST
88 F12 66 JTDI
89 H8 67 JTMS
90 G11 68 JTCK
S
I
Ground
TT pu
JTAG Reset Input
JTAG Data input
I
TT pu
TT pu
TT pd
I
JTAG Mode Selection Input
JTAG Clock Input
I
JTAG data output.
Note: Reset state = HiZ
91 G10 69 JTDO
O
4mA
92 G9 70 VSS
93 G8 71 VDD
S
S
Ground
Supply voltage (5V)
94 G7
95 F11
96 F10
97 F9
98 F8
99 E12
P4.0/ICAPA7
I/O TT
I/O TT
I/O TT
I/O TT
WUP24 2mA
WUP25 2mA
WUP26 2mA
WUP27 2mA
2mA
X
X
X
X
X
X
X
X
X
X
X Port 4.0 TIM7: Input Capture A input
X Port 4.1 TIM7: Input Capture B input
X Port 4.2 TIM8: Input Capture A input
X Port 4.3 TIM8: Input Capture B input
X Port 4.4 CAN2: Transmit Data output
X Port 4.5 CAN2: Receive Data input
X Port 4.6 I2C1:Serial Clock
P4.1/ICAPB7
P4.2/ICAPA8
P4.3/ICAPB8
P4.4/CAN2TX I/O TT
P4.5/CAN2RX I/O TT
WUP18 2mA
WUP19 2mA
2mA
100 E11 72 P4.6/SCL1
101 C12 73 P4.7/SDA1
I/O TT
I/O TT
X Port 4.7 I2C1:Serial Data
102 B12
103 E10
P4.8/OCMPA8 I/O TT
2mA
X Port 4.8 TIM8: Output Compare A output
X Port 4.9 TIM6: Input Capture B input
P4.9/ICAPB6
I/O TT
I/O TT
2mA
TIM5: Input
TIM6: Input
Capture B
input
(TQFP100
only)
P4.10/ICAPA6/I
CAPB5
Port
4.10
Capture A input
(144-pin pkg
only)
104 E9 74
WUP20 2mA
X
X
P4.11/OCMPB
8
Port
4.11
105 D12
106 D11
107 D10
I/O TT
2mA
WUP21 2mA
2mA
X
X
X
X
X
X
X
X
X
X
TIM8: Output Compare B output
TIM9: Input Capture A input
TIM9: Input Capture B input
BSPI1: Slave Select
Port
4.12
P4.12/ICAPA9 I/O TT
P4.13/ICAPB9 I/O TT
Port
4.13
Port
4.14
108 C11 75 P4.14/SS1
109 B11 76 P4.15/SCK1
I/O TT
I/O TT
2mA
Port
4.15
WUP22 2mA
BSPI1: Serial Clock
18/53
STR73xF
Block Diagram
Table 3.
Pin n°
STR73xF pin description
Pin Name
Input
Output
Main
functio
n
Alternate function
(after
reset)
BSPI1: Master Output/Slave
input
110 B10 77 P5.0/MOSI1
111 C10 78 P5.1/MISO1
I/O TT
I/O TT
2mA
X
X
X Port 5.0
X Port 5.1
BSPI1: Master input/Slave
output
2mA
112 A9
113 B9
P5.2/OCMPA9 I/O TT
P5.3/OCMPB9 I/O TT
2mA
2mA
X
X
X Port 5.2 TIM9: Output Compare A output
X Port 5.3 TIM9: Output Compare B output
PWM3: PWM
P5.4/SS2/PWM
3
BSPI2: Slave
Select
output
(TQFP100
only)
114 C9 79
I/O TT
2mA
X
X Port 5.4
115 D9 80 P5.5/SCK2
116 A11 81 P5.6/MOSI2
I/O TT
I/O TT
WUP23 2mA
2mA
X
X
X Port 5.5 BSPI2: Serial Clock
BSPI2: Master Output/Slave
input
X Port 5.6
X Port 5.7
X Port 5.8
X Port 5.9
BSPI2: Master input/Slave
output
117 A10 82 P5.7/MISO2
118 A8 83 P5.8/PWM4
119 B8 84 P5.9/PWM5
120 C8 85 P5.10/RDI2
121 A12 86 P5.11/TDO2
122 D8 87 P5.12
I/O TT
I/O TT
I/O TT
I/O TT
I/O TT
I/O TT
I/O TT
I/O TT
I/O TT
2mA
X
X
X
X
X
X
X
X
X
PWM4: PWM output (TQFP100
only)
INT6
INT7
INT8
INT9
2mA
2mA
2mA
2mA
PWM5: PWM output (TQFP100
only)
Port
X
UART2: Receive Data input
UART2: Transmit Data output
5.10
Port
X
5.11
Port
X
INT10 2mA
INT11 2mA
INT12 2mA
INT13 2mA
5.12
Port
X
123 E8
124 B7
125 A7
P5.13
P5.14
P5.15
5.13
Port
X
5.14
Port
X
5.15
1.8V decoupling pin: a
decoupling capacitor
126 A6 88 V18
S
(recommended value: 100nF)
must be connected between this
pin and nearest VSS pin.
127 C7 89 VSS
128 D7 90 VDD
S
S
Ground
Supply voltage (5V)
19/53
Block Diagram
STR73xF
Table 3.
Pin n°
STR73xF pin description
Input
Output
Main
functio
n
Pin Name
Alternate function
(after
reset)
129 E7 91 P6.0
130 F7 P6.1
131 B6 92 P6.2/RDI3
132 C6 P6.3
133 D6 93 P6.4/TDO3
134 E6 P6.5
135 A5 94 P6.6
136 B5 P6.7
I/O TT
I/O TT
I/O TT
I/O TT
I/O TT
I/O TT
I/O TT
I/O TT
I/O TT
I/O TT
WUP0 8mA
WUP1 2mA
X
X
X
X
X
X
X
X
X
X
X Port 6.0
X Port 6.1
WUP2 2mA
WUP3 2mA
WUP4 2mA
WUP5 2mA
WUP6 2mA
WUP7 2mA
WUP10 2mA
2mA
X Port 6.2 UART3: Receive Data input
X Port 6.3
X Port 6.4 UART3: Transmit Data output
X Port 6.5
X Port 6.6
X Port 6.7
137 C5 95 P6.8/RDI0
138 A3 96 P6.9/TDO0
X Port 6.8 UART0: Receive Data input
X Port 6.9 UART0: Transmit Data output
Port
X
139 A2
P6.10
I/O TT
I/O TT
I/O TT
I/O TT
I/O TT
I/O TT
WUP8 2mA
2mA
X
X
X
X
X
X
6.10
Port
6.11
BSPI0: Master input/Slave
output
140 D5 97 P6.11/MISO0
141 A4 98 P6.12/MOSI0
X
X
X
X
X
Port
6.12
BSPI0: Master Output/Slave
input
2mA
Port
6.13
142 B4 99 P6.13/SCK0
10
WUP11 2mA
2mA
BSPI0: Serial Clock
BSPI0: Slave Select
Port
6.14
143 C4
P6.14/SS0
0
Port
6.15
144 B3
P6.15
WUP9 2mA
20/53
STR73xF
Block Diagram
2.3
Memory Mapping
Figure 5 shows the various memory configurations of the STR73xF system. The system
memory map (from 0x0000_0000 to 0xFFFF_FFFF) is shown on the left part of the figure,
the right part shows maps of the Flash and APB areas. For flexibility the Flash or RAM
addresses can be aliased to Block 0 addresses using the remapping feature
Most reserved memory spaces (gray shaded areas in Figure 5) are protected from access
by the user code. When an access this memory space is attempted, an ABORT signal is
generated. Depending on the type of access, the ARM processor will enter “prefetch abort”
state (Exception vector 0x0000_000C) or “data abort” state (Exception vector
0x0000_0010). It is up to the application software to manage these abort exceptions.
Figure 5.
Memory map
Addressable Memory Space
4 Gbytes
APB Memory Space
32 Kbytes
0xFFFF FFFF
0xFFFF FFFF
APB TO ARM7
BRIDGE
32K
EIC
1K
1K
1K
1K
1K
1K
1K
1K
1K
1K
1K
1K
1K
1K
1K
1K
1K
1K
1K
1K
1K
1K
1K
0xFFFF 8000
0xFFFF FC00
0xFFFF FBFF
ADC
0xFFFF F800
0xFFFF F7FF
0xFFFF F600
0xFFFF F400
0xFFFF F3FF
7
CMU
RTC
DMA 0-3
TIM 4
FLASH Memory Space
64K/128/256 Kbytes
0xE000 0000
0xDFFF FFFF
0xFFFF F000
0xFFFF EFFF
0xFFFF EC00
0xFFFF EBFF
0x8010 DFFF
TIM 3
System Memory
Flash registers
8K
0xFFFF E800
0xFFFF E7FF
0x8010 C000
0x8010 0017
0x8010 0000
6
TIM 2
20B
0xFFFF E400
0xFFFF E3FF
BSPI 2
BSPI 1
0xFFFF E000
0xFFFF DFFF
0xC000 0000
0xBFFF FFFF
0xFFFF DC00
0xFFFF DBFF
BSPI 0
0xFFFF D800
0xFFFF D7FF
5
GP I/O 0-6
PWM 0-5
CAN 2(4)
0xFFFF D400
0xFFFF D3FF
0xA000 3FFF
0xA000 0000
0x9FFF FFFF
RAM
16K
0xFFFF D000
0xFFFF CFFF
0xFFFF CC00
0xFFFF CBFF
CAN 1(4)
0xFFFF C800
0xFFFF C7FF
4
CAN 0(4)
0xFFFF C400
0xFFFF C3FF
0x8010 0017
APB BRIDGE 1 REGS
reserved
WAKEUP
reserved
TIM 5-9
FLASH
64K/128K/256K
0xFFFF C000
0xFFFF BFFF
0x8000 0000
0x7FFF FFFF
0xFFFF BC00
0xFFFF BBFF
0xFFFF B800
0xFFFF B7FF
3
0xFFFF B400
0xFFFF B3FF
0x6000 03FF
PRCCU
1K
0x8003 FFFF
0xFFFF B000
0xFFFF AFFF
0x6000 0000
0x5FFF FFFF
TIM 1
B0F7(2)
B0F6(2)
0xFFFF AC00
0xFFFF ABFF
64K
64K
TIM 0
0xFFFF A800
0xFFFF A7FF
0xFFFF A600
0x8003 0000
0x8002 FFFF
2
WAKEUPTIM
WDG
0xFFFF A400
0xFFFF A3FF
UART 3
UART 1
UART 2
UART 0
0x4000 003F
0x4000 0000
0x3FFF FFFF
0xFFFF A200
1K
1K
CONFIG. REGS
64B
16B
0xFFFF A000
0xFFFF 9FFF
0xFFFF 9E00
0x8002 0000
0x8001 FFFF
0xFFFF 9C00
0xFFFF 9BFF
TB 0-2
1K
1K
1K
1K
1K
1K
1K
0xFFFF 9800
0xFFFF 97FF
B0F5(3)
B0F4
1
64K
32K
reserved
reserved
0xFFFF 9400
0xFFFF 93FF
0x2000 000F
0x2000 0000
0x1FFF FFFF
0x8001 0000
0x8000 FFFF
NATIVE ARBITER
0xFFFF 9000
0xFFFF 8FFF
reserved
2
0xFFFF 8C00
0xFFFF 8BFF
0x8000 8000
0x8000 7FFF
I
C 1
B0F3
B0F2
B0F1
B0TF
8K
8K
8K
0xFFFF 8800
0xFFFF 87FF
0x8000 6000
0
0x8000 5FFF
2
0x8000 4000
0x8000 3FFF
I
C 0
0xFFFF 8400
0xFFFF 83FF
0x8000 2000
0x0010 0017
0x0000 0000
0x8000 1FFF
APB BRIDGE 0 REGS
(1)
FLASH
64K/128K/256K
8K
0x8000 0000
0xFFFF 8000
(1) FLASH aliased at 0x0000 0000h by system decoder for booting with valid instruction upon RESET from Block B0 (8 Kbytes)
(2) Only available in STR73xZ2/V2
access to gray shaded area will return an ABORT
(3) Only available in STR73xZ2/V2 and STR73xZ1/V1
(4) Only available in STR730/STR731
Drawing not to scale
21/53
Electrical parameters
STR73xF
3
Electrical parameters
3.1
Parameter conditions
Unless otherwise specified, all voltages are referred to V
.
SS
3.1.1
Minimum and maximum values
Unless otherwise specified the minimum and maximum values are guaranteed in the worst
conditions of ambient temperature, supply voltage and frequencies by tests in production on
100% of the devices with an ambient temperature at T =25°C and T =T (given by the
A
A
Amax
selected temperature range).
Data based on characterization results, design simulation and/or technology characteristics
are indicated in the table footnotes and are not tested in production. Based on
characterization, the minimum and maximum values refer to sample tests and represent the
mean value plus or minus three times the standard deviation (mean 3Σ).
3.1.2
3.1.3
Typical values
Unless otherwise specified, typical data are based on T =25°C and V =5V. They are given
only as design guidelines and are not tested.
A
DD
Typical ADC accuracy values are determined by characterization of a batch of samples from
a standard diffusion lot over the full temperature range, where 95% of the devices have an
error less than or equal to the value indicated (mean 2Σ).
Typical curves
Unless otherwise specified, all typical curves are given only as design guidelines and are
not tested.
3.1.4
3.1.5
Loading capacitor
The loading conditions used for pin parameter measurement are shown in Figure 6.
Pin input voltage
The input voltage measurement on a pin of the device is described in Figure 7.
Figure 6. Pin loading conditions
Figure 7. Pin input voltage
STR7 PIN
STR7 PIN
V
IN
=50pF
L
22/53
STR73xF
Electrical parameters
3.2
Absolute maximum ratings
Stresses above those listed as “absolute maximum ratings” may cause permanent damage
to the device. This is a stress rating only and functional operation of the device under these
conditions is not implied. Exposure to maximum rating conditions for extended periods may
affect device reliability
Table 4.
Symbol
DD - VSS
VSSA
VDDA- VSSA
VIN
Voltage characteristics
Ratings
Min
Max
Unit
V
External 5V Supply voltage
-0.3
VSS
-0.3
6.0
VSS
V
V
Reference ground for A/D converter
Reference voltage for A/D converter
VDD+0.3
V
VDD+0.3
0.3
Input voltage on any pin
-0.3
-
Variations between different 5V
power pins
|∆VDDx
|
mV
Variations between all the different
ground pins
|VSSX - VSS
VESD(HBM)
VESD(MM)
|
-
0.3
Electro-static discharge voltage
(Human Body Model)
see : Absolute Maximum Ratings
(Electrical Sensitivity) on
page 37
Electro-static discharge voltage
(Machine Model)
Table 5.
Symbol
Current characteristics
Ratings
Max.
Unit
Total current into VDD power lines (source) 1)
Total current out of VSS ground lines (sink) 1)
IVDD
IVSS
100
100
Output current sunk by any I/O and control pin
Output current source by any I/O and control pin
10
10
IIO
mA
2) & 3)
Injected current on any other pin 4) &5)
10
75
IINJ(PIN)
2)
Total injected current (sum of all I/O and control pins) 4)
ΣIINJ(PIN)
1. All 5V power (VDD, VDDA) and ground (VSS, VSSA) pins must always be connected to the external 5V
supply
2.
I
INJ(PIN) must never be exceeded. This is implicitly insured if VIN maximum is respected. If VIN maximum
cannot be respected, the injection current must be limited externally to the IINJ(PIN) value. A positive
injection is induced by VIN>VDD while a negative injection is induced by VIN<VSS
.
3. Negative injection disturbs the analog performance of the device. See note in Section 3.3.6: 10-bit ADC
characteristics on page 44.
4. When several inputs are submitted to a current injection, the maximum ΣIINJ(PIN) is the absolute sum of the
positive and negative injected currents (instantaneous values). These results are based on
characterization with ΣIINJ(PIN) maximum current injection on four I/O port pins of the device.
5.) In 144-pin devices, only +10mA on P0.3, P1.13, P3.6 and P4.13 pins (negative injection not allowed).
23/53
Electrical parameters
Table 6.
STR73xF
Thermal characteristics
Symbol
TSTG
Ratings
Value
Unit
Storage temperature range
-55 to +150
°C
Maximum junction temperature (see Section 4.2: Thermal characteristics on
page 49)
TJ
24/53
STR73xF
Electrical parameters
3.3
Operating conditions
Subject to general operating conditions for V , and T .
DD
A
Table 7.
Symbol
General Operating Conditions
Parameter
Conditions
Min
Max
Unit
Accessing SRAM or Flash
(zero wait state Flash access
up to 36 MHz)
Internal CPU and system
Clock frequency
fMCLK
0
36
MHz
Standard Operating
Voltage
4.5
4.5
5.5
V
V
VDD
VDDA
TA
Operating Analog Refer-
ence Voltage with respect
to ground
V
DD+0.1
6 Partnumber Suffix
7 Partnumber Suffix
-40
-40
85
105
Ambient temperature range
°C
Table 8.
Symbol
Operating Conditions at power-up / power-down
Parameter
Conditions
Min
Max
Unit
Typ
Subject to general
operating conditions for
TA.
tVDD
VDD rise time rate
-
20
-
ms/V
25/53
Electrical parameters
STR73xF
3.3.1
Supply current characteristics
The current consumption is measured as described in Figure 6 and Figure 7.
Total current consumption
The MCU is placed under the following conditions:
●
All I/O pins in input mode with a static value at V or V (no load)
DD SS
●
All peripherals are disabled except if explicitly mentioned.
Subject to general operating conditions for V , and T .
DD
A
Table 9.
Symbol
Total Current consumption
1)
Typ
Max 2)
Unit
Parameter
Conditions
Formula, fMCLK in MHz, RAM execution
7 + 1.9 fMCLK
mA
mA
mA
RUN mode3)
f
f
f
MCLK=36 MHz, RAM execution
76
86
MCLK=36 MHz, Flash execution
OSC = 4 MHz, fMCLK= fOSC/16 = 250KHz
Main Voltage Regulator ON,
WFI mode
6.7
8
mA
µA
LP Voltage Regulator = 2mA,
RTC and WDG ON, Other modules off.
f
RC = High Frequency (CMU_RCCTL= 0x8),
LPWFI mode fMCLK= fRC /16, LP Voltage Regulator = 2mA,
Other modules off.
220
350
IDD
fOSC = 4 MHz, RC oscillator ON
fRC = High Frequency (CMU_RCCTL= 0x0)
LP Voltage Regulator = 6mA,
500
150
700
220
RTC and WUT ON, Other modules off.
Internal wake-up possible.
STOP mode
HALT mode
µA
µA
fRC = High Frequency (CMU_RCCTL= 0xF),
LP Voltage Regulator = 2mA.
WUT ON. Other modules off.
Internal wake-up possible.
LP Voltage Regulator = 2mA, WIU ON, Other
modules off, External wake-up.
50
50
140
140
LP Voltage Regulator = 2mA.
Notes:
1. Typical data are based on TA=25°C, VDD=5V
2. Data based on characterization results, tested in production at VDD max. and TA = 25°C.
3. I/O in static configuration (not toggling). RUN mode is almost independent of temperature. On the
contrary RUN mode current is highly dependent on the application. The IDDRUN value can be
significantly reduced by the application in the following ways: switch-off unused peripherals (default),
reduce peripheral frequency through internal prescaler, fetch the most frequently-used functions from RAM
and use low power mode when possible.
26/53
STR73xF
Figure 8.
Electrical parameters
STOP I vs. VDD
Figure 9.
HALT I vs. V
DD DD
DD
300
250
200
150
100
50
300
250
200
150
100
50
TA=-45°C
TA=25°C
TA=85°C
TA=105°C
TA=-45°C
TA=25°C
TA=85°C
TA=105°C
0
0
3.5
4
4.5
5
5.5
6
6.5
3.5
4
4.5
5
5.5
6
6.5
Vdd (V)
Vdd (V)
Figure 10. WFI I vs. V
Figure 11. LPWFI I vs. V
DD
DD
DD
DD
8.0
7.5
7.0
6.5
6.0
5.5
500
450
400
350
300
250
200
150
100
50
TA=-45°C
TA=25°C
TA=85°C
TA=105°C
TA=-45°C
TA=25°C
TA=85°C
TA=105°C
0
3.5
4
4.5
5
5.5
6
6.5
3.5
4
4.5
5
5.5
6
6.5
Vdd (V)
Vdd (V)
27/53
Electrical parameters
STR73xF
Typical application current consumption
Table 10. Typical consumption in Run mode at 25°C and 85°C
Conditions fMCLK (MHz) fADC (MHz) Typical IDD (mA)
10
20
36
10
20
36
20
29
42
22
32
48
10
9
Code executing in
RAM
VDD= 5.5 V, RC Oscillator off,
PLL on, RTC enabled, 1 Timer
(TIM) running, and ADC
running in scan mode.
10
9
Code executing in
Flash
Table 11. Typical consumption in Run and low power modes at 25°C
Mode
Conditions
fMCLK
Typical IDD
36MHz
24MHz
36MHz
24MHz
4MHz
76 mA
56 mA
33 mA
31 mA
11 mA
8 mA
RUN
All peripherals on, RAM execution
Main Voltage Regulator on, Flash on, EIC on, WIU
on, GPIOs on.
WFI
PLL off, Main Voltage Regulator on
CLOCK2/16, Main Voltage Regulator on,
CLOCK2/16, Main Voltage Regulator off,
250kHz
250kHz
SLOW
LPWFI
3 mA
RC oscillator running in Low Frequency, Main crystal
oscillator off, Main Voltage Regulator off
29kHz
2.5 mA
528 µA
378 µA
83 µA
CLOCK2/16, Main Voltage Regulator off, LP Voltage
Regulator = 2mA, Flash in power down mode.
250kHz
Main Voltage Regulator off, RTC on, RC oscillator
off, LP Voltage Regulator = 6 mA
-
-
-
Main Voltage Regulator off, RTC off, RC oscillator
off, LP Voltage Regulator = 6 mA
STOP
HALT
Main Voltage Regulator off, RTC off, RC oscillator
off, LP Voltage Regulator = 4 mA
64 µA
Main Voltage Regulator off, RTC off, RC oscillator
off, LP Voltage Regulator = 2 mA
-
-
44 µA
44 µA
RTC off, LP Voltage Regulator = 2 mA
28/53
STR73xF
Electrical parameters
On-Chip Peripherals
Table 12. Peripheral current consumption at T = 25°C
A
Symbol
Parameter
Conditions
Typ
Unit
High Frequency
Low Frequency
120
60
µA
µA
µA
IDD(RC)
RC (Backup oscillator) supply current
TIM Timer supply current 1)
BSPI supply current 1)
UART supply current 1)
I2C supply current 1)
IDD(TIM)
IDD(BSPI)
IDD(UART)
IDD(I2C)
350
1.1
850
430
5
mA
µA
µA
mA
mA
mA
µA
µA
µA
µA
mA
µA
µA
µA
µA
ADC supply current when converting 2)
EIC supply current
IDD(ADC)
IDD(EIC)
2.88
2.95
150
250
240
370
2.5
CAN supply current 1)
GPIO supply current
TB supply current
IDD(CAN)
IDD(GPIO)
IDD(TB)
fMCLK=36 MHz
IDD(PWM)
IDD(RTC)
IDD(DMA)
IDD(ARB)
IDD(AHB)
IDD(WUT)
IDD(WIU)
PWM supply current
RTC supply current
DMA supply current
Native Arbiter supply current
AHB Arbiter supply current
WUT supply current
WIU supply current
180
570
300
460
Notes:
1. Data based on a differential IDD measurement between the on-chip peripheral when kept under reset, not
clocked and the on-chip peripheral when clocked and not kept under reset. This measurement does not
include the pad toggling consumption.
3. Data based on a differential IDD measurement between reset configuration and continuous A/D
conversions.
29/53
Electrical parameters
STR73xF
3.3.2
Clock and timing characteristics
Crystal / Ceramic Resonator Oscillator
The STR73xF can operate with a crystal oscillator or resonator clock source. Figure 12 describes a
simple model of the internal oscillator driver as well as example of connection for an oscillator or a
resonator.
Figure 12. Crystal Oscillator and Resonator
VDD
STR73x
I
RF
STR73x
STR73x
Resonator
Crystal
RS
CL
CL
Notes
1) XTAL2 must not be used to directly drive external circuits.
2) For test or boot purpose, XTAL2 can be used as an high impedance input pin to provide an external
clock to the device. XTAL1 should be grounded, and XTAL2 connected to a wave signal generator
providing a 0 to VDD signal. Directly driving XTAL2 may results in deteriorated jitter and duty cycle.
30/53
STR73xF
Electrical parameters
V
= 5V 10%, T = -40°C to T
, unless otherwise specified.
DD
A
Amax
Table 13. Main Oscillator characteristics
Value
Unit
Symbol
Parameter
Conditions
Min Typ Max
fOSC
gm
Oscillator frequency
4
1.5
-
8
MHz
Oscillator
Transconductance
4.2 mA/V
f
OSC = 4 MHz, TA= 25oC
2.4
1.-
-
1)
VOSC
Oscillation amplitude
V
fOSC = 8 MHz, TA= 25oC
1)
V
VAV
Oscillator operating point
Sine wave middle, TA= 25oC
-
-
0.77
-
External crystal, VDD = 5.5V,
fOSC = 4 MHz, TA=-40oC
-
12
-
ms
ms
ms
ms
ms
ms
External crystal, VDD = 5.0V,
fOSC = 4 MHz, TA=25oC
-
-
-
-
-
5.5
-
External crystal, VDD = 5.5V,
fOSC = 6 MHz, TA=-40oC
8
-
1)
tSTUP
Oscillator Start-up Time
External crystal, VDD = 5.0V,
fOSC = 6 MHz, TA=25oC
3.3
-
External crystal, VDD = 5.5V,
fOSC = 8 MHz, TA=-40oC
7
-
External crystal, VDD = 5.0V,
fOSC = 8 MHz, TA= 25oC
2.7
31/53
Electrical parameters
Symbol
STR73xF
Unit
Value
Parameter
Conditions
Min Typ Max
C13) = C2
10pF
=
4)
150 555
-
fOSC = 4 MHz
Cp2) = 10pF
C1 = C2 = 20pF 490 1035
C1 = C2 = 30pF 490 1030
C1 = C2 = 40pF 380 850
C1 = C2 = 10pF 160 470
C1 = C2 = 20pF 415 800
C1 = C2 = 30pF 340 735
C1 = C2 = 40pF 260 580
C1 = C2 = 10pF 160 415
C1 = C2 = 20pF 325 640
C1 = C2 = 30pF 250 550
C1 = C2 = 40pF 180 420
C1 = C2 = 10pF 160 375
C1 = C2 = 20pF 260 525
C1 = C2 = 30pF 185 420
C1 = C2 = 40pF 135 315
C1 = C2 = 10pF 155 340
C1 = C2 = 20pF 210 435
C1 = C2 = 30pF 145 335
C1 = C2 = 40pF 100 245
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
fOSC = 5 MHz
Cp = 10pF
1)
fOSC = 6 MHz
Cp = 10pF
RF
Feedback resistor
Ω
fOSC = 7 MHz
Cp = 10pF
fOSC = 8MHz
Cp = 10pF
1. Min and Max values are guaranteed by characterization, not tested in production.
2. CP represents the total capacitance between XTAL1 and XTAL2, including the shunt capacitance of the
external quartz crystal as well as the total board parasitic cross-capacitance between XTAL1 track and
XTAL2 track.
3. C1 represents the total capacitance between XTAL1 and ground, including the external capacitance tied to
XTAL1 pin (CL) as well as the total parasitic capacitance between XTAL1 track and ground (this includes
application board track capacitance to ground and device pin capacitance).
4. C2 represents the total capacitance between XTAL2 and ground, including the external capacitance tied to
XTAL1 pin (CL) as well as the total parasitic capacitance between XTAL2 track and ground (this includes
application board track capacitance to ground and device pin capacitance).
32/53
STR73xF
Electrical parameters
RC/Backup Oscillator characteristics
VDD = 5V 10%, TA = -40°C to TAmax, unless otherwise specified.
Table 14. RC Oscillator Characteristics
Value
Unit
Symbol
fRC
Parameter
RC Frequency
Conditions
Min Typ Max
High Frequency mode 1)
Low Frequency mode1)
CMU_RCCTL = 0x0
CMU_RCCTL = 0xF
CMU_RCCTL = 0x0
CMU_RCCTL = 0xF
Fixed CMU_RCCTL
Fixed CMU_RCCTL
2.35
29
MHz
kHz
3
MHz
fRCHF
RC High Frequency
RC Low Frequency
2.3 MHz
kHz
35
fRCLF
30
10
23
kHz
%
2)
fRCHFS
RC High Frequency stability
RC Low Frequency stability
2)
fRCLFS
%
Stable VDD, fRC = 2.35
MHz, TA = 25oC
µs
tRCSTUP RC Start-up Time
2.35
1) CMU_RCCTL = 0x8
2) RC frequency shift versus average value (%)
PLL Electrical Characteristics
VDD = 5V 10%, TA = -40°C to TAmax, unless otherwise specified
Table 15.
Symbol
PLL characteristics.
Parameter
Value
Typ
Conditions
Unit
Min
Max
FREF_RANGE = ‘0’
FREF_RANGE = ‘1’
1.5
3.0
3.0
5.0
(1)
fPLLIN
PLL reference clock
MHz
MX = ”00”
MX = ”01”
MX = ”10”
MX = ”11”
20 x fPLLIN
12 x fPLLIN
28 x fPLLIN
16 x fPLLIN
fPLLOUT
PLL output clock
System clock
MHz
MHz
kHz
fMCLK
DX = 1..7
fPLLOUT/DX
36
FREF_RANGE = ‘0’, MX0 = ’1’
FREF_RANGE = ‘0’, MX0 = ’0’
FREF_RANGE = ‘1’, MX0 = ’1’
FREF_RANGE = ‘1’, MX0 = ’0’
120
240
240
480
PLL free running
frequency
(2)
fFREE
stable oscillator
(fPLLIN = 4 MHz), stable VDD
(3)
tLOCK
PLL lock time
100
300
1.5
µs
f
PLLIN = 4 MHz (pulse
generator)
∆tPKJIT
PLL jitter (pk to pk)
ns
1. fPLLIN is obtained from fOSC directly or through an optional divider by 2.
2. Typical data are based on TA=25°C, VDD=5V
3. Max value is guaranteed by characterization, not tested in production.
33/53
Electrical parameters
STR73xF
Unit
Table 16. Low-power Mode Wake-up Timing
Symbol
Parameter
Conditions
Typ
tWUHALT
Wake-up from HALT mode
200
180
234
µs
µs
µs
RC High Frequency in STOP mode
RC Low Frequency in STOP mode
tWUSTOP
Wake-up from STOP mode
Main Voltage Regulator ON
RC oscillator off
27
µs
fOSC = 4 MHz, fMCLK= fOSC/16
RAM or FLASH execution
Main Voltage Regulator ON
RC oscillator = High frequency
FLASH execution
1)
Wake-up from LPWFI mode
tWULPWFI
46
µs
Main Voltage Regulator ON
RC oscillator = Low frequency
FLASH execution
3.6
ms
1) FLASH memory has been programmed to enter Power Down mode during LPWFI.
34/53
STR73xF
Electrical parameters
3.3.3
Memory characteristics
Flash Memory
Table 17. Flash memory characteristics
Value
Unit
Min Typ
Symbol
Parameter
Test Conditions
Max1)
tWP
Word Program (32-bit)
Double Word Program(64-bit)
Bank Program (64K)
35
64
0.5
1
80
150
1.25
2.5
µs
µs
s
tDWP
tBP64
tBP128
tBP256
Double Word Program
Double Word Program
Double Word Program
Not preprogrammed
Preprogrammed 2)
Bank Program (128K)
Bank Program (256K)
s
2
4.9
s
0.6
0.5
0.9
0.8
tSE8
tSE32
tSE64
Sector Erase (8K)
Sector Erase (32K)
s
s
Not preprogrammed
Preprogrammed2)
1.1
0.8
2
1.8
1.7
1.3
3.7
3.3
not preprogrammed
preprogrammed 2)
Sector Erase (64K)
s
3)
Recovery from Power-Down
20
10
30
µs
tRPD
3)
tPSL
Program Suspend Latency
Erase Suspend Latency
µs
µs
3)
tESL
Min time from Erase
Resume to next Erase
Suspend
3)
tESR
Erase Suspend Rate
Set Protection
20
20
ms
µs
3)
tSP
40
1
170
3)
tFPW
First Word Program
Endurance
ms
NEND
tRET
10
20
kcycles
Years
Data Retention
TA=85°
1. TA=-45°C after 0 cycles, Guaranteed by characterization, not tested in production
2. All bits programmed to 0.
3. Guaranteed by design, not tested in production.
35/53
Electrical parameters
STR73xF
3.3.4
EMC characteristics
Susceptibility tests are performed on a sample basis during product characterization.
Functional EMS (Electro Magnetic Susceptibility)
Based on a simple running application on the product (toggling 2 LEDs through I/O ports),
the product is stressed by two electro magnetic events until a failure occurs (indicated by the
LEDs).
●
ESD: Electro-Static Discharge (positive and negative) is applied on all pins of the
device until a functional disturbance occurs. This test conforms with the IEC 1000-4-2
standard.
●
FTB: A Burst of Fast Transient voltage (positive and negative) is applied to V and
DD
V
through a 100pF capacitor, until a functional disturbance occurs. This test
SS
conforms with the IEC 1000-4-4 standard.
A device reset allows normal operations to be resumed. The test results are given in the
table below based on the EMS levels and classes defined in application note AN1709.
Designing hardened software to avoid noise problems
EMC characterization and optimization are performed at component level with a typical
application environment and simplified MCU software. It should be noted that good EMC
performance is highly dependent on the user application and the software in particular.
Therefore it is recommended that the user applies EMC software optimization and
prequalification tests in relation with the EMC level requested for his application.
Software recommendations:
The software flowchart must include the management of runaway conditions such as:
●
●
●
Corrupted program counter
Unexpected reset
Critical Data corruption (control registers...)
Prequalification trials:
Most of the common failures (unexpected reset and program counter corruption) can be
reproduced by manually forcing a low state on the RESET pin or the Oscillator pins for 1
second.
To complete these trials, ESD stress can be applied directly on the device, over the range of
specification values. When unexpected behavior is detected, the software can be hardened
to prevent unrecoverable errors occurring (see application note AN1015).
Table 18. EMS data
Level/
Class
Symbol
Parameter
Conditions
VDD=5V, TA=+25°C, fMCLK=36MHz
conforms to IEC 1000-4-2
Voltage limits to be applied on any I/O pin to
induce a functional disturbance
VFESD
4A
Fast transient voltage burst limits to be
VEFTB applied through 100pF on VDD and VSS pins
VDD=5V, TA=+25°C, fMCLK=36MHz
conforms to IEC 1000-4-4
4A
to induce a functional disturbance
36/53
STR73xF
Electrical parameters
Electro Magnetic Interference (EMI)
Based on a simple application running on the product (toggling 2 LEDs through the I/O
ports), the product is monitored in terms of emission. This emission test is in line with the
norm SAE J 1752/3 which specifies the board and the loading of each pin.
Table 19. EMI data
Max vs.
Unit
[fOSC4M/fMCLK
]
Monitored
Frequency Band
Symbol
Parameter
Conditions
6/36MHz 8/8MHz
0.1MHz to 30MHz
30MHz to 130MHz
130MHz to 1GHz
SAE EMI Level
23
37
20
4
30
34
7
VDD=5.0V,
TA=+25°C,
All packages
dBµV
-
SEMI
Peak level
3.5
Absolute Maximum Ratings (Electrical Sensitivity)
Based on three different tests (ESD, LU and DLU) using specific measurement methods, the
product is stressed in order to determine its performance in terms of electrical sensitivity.
For more details, refer to the application note AN1181.
Electro-Static Discharge (ESD)
Electro-Static Discharges (a positive then a negative pulse separated by 1 second) are
applied to the pins of each sample according to each pin combination. The sample size
depends on the number of supply pins in the device (3 parts*(n+1) supply pin). Two models
can be simulated: Human Body Model and Machine Model. This test conforms to the
JESD22-A114A/A115A standard.
Table 20. ESD Absolute Maximum ratings
Maximum
Symbol
Ratings
Conditions
Unit
value 1)
Electro-static discharge voltage
(Human Body Model)
VESD(HBM)
2000
Electro-static discharge voltage
(Machine Model)
VESD(MM)
200
TA=+25°C
V
750 on corner
pins, 500 on
others
Electro-static discharge voltage
(Charge Device Model)
VESD(CDM)
Notes:
1. Data based on characterization results, not tested in production.
Static and Dynamic Latch-Up
●
LU: 3 complementary static tests are required on 10 parts to assess the latch-up
performance. A supply overvoltage (applied to each power supply pin) and a current
injection (applied to each input, output and configurable I/O pin) are performed on each
37/53
Electrical parameters
STR73xF
sample. This test conforms to the EIA/JESD 78 IC latch-up standard. For more details,
refer to the application note AN1181.
●
DLU: Electro-Static Discharges (one positive then one negative test) are applied to
each pin of 3 samples when the micro is running to assess the latch-up performance in
dynamic mode. Power supplies are set to the typical values, the oscillator is connected
as near as possible to the pins of the micro and the component is put in reset mode.
This test conforms to the IEC1000-4-2 and SAEJ1752/3 standards. For more details,
refer to the application note AN1181.
Electrical Sensitivities
Class 1)
Symbol
Parameter
Conditions
TA=+25°C
TA=+85°C
TA=+105°C
A
A
A
LU
Static latch-up class
V
=5.5V, f
=4MHz, f
=32MHz, T =+25°C
DLU
Dynamic latch-up class
A
DD
OSC4M
MCLK A
Notes:
1. Class description: A Class is an STMicroelectronics internal specification. All its limits are higher than the
JEDEC specifications, that means when a device belongs to Class A it exceeds the JEDEC standard. B
Class strictly covers all the JEDEC criteria (international standard).
38/53
STR73xF
Electrical parameters
3.3.5
I/O port pin characteristics
General Characteristics
Subject to general operating conditions for V and T unless otherwise specified.
DD
A
Table 21. I/O static characteristics
Symbol
Parameter
Conditions
Min
Max
Unit
Typ
Input low level voltage 1)
VIL
VIH
0.8
TTL ports
V
Input high level voltage 1)
2.0
IINJ(PIN)
Injected Current on any I/O pin
10
75
1
mA
mA
µA
Total injected current (sum of all
I/O and control pins)
ΣIINJ(PIN)
2)
Input leakage current 3)
Ilkg
IS
VSS≤VIN≤VDD
Floating input
mode
Static current consumption 4)
200
120
µA
Weak pull-up equivalent
resistor5)
RPU
VIN=VSS
VIN=VDD
55
55
220
220
kΩ
Weak pull-down equivalent
resistor5)
RPD
CIO
120
5
kΩ
I/O pin capacitance
pF
Notes:
1. Data based on characterization results, not tested in production.
2. When the current limitation is not possible, the VIN absolute maximum rating must be respected, otherwise
refer to IINJ(PIN) specification. A positive injection is induced by VIN>V33 while a negative injection is
induced by VIN<VSS. Refer to Section 3.2 on page 23 for more details.
3. Leakage could be higher than max. if negative current is injected on adjacent pins.
4. Configuration not recommended, all unused pins must be kept at a fixed voltage: using the output mode of
the I/O for example or an external pull-up or pull-down resistor. Data based on design simulation and/or
technology characteristics, not tested in production.
6. The RPU pull-up and RPD pull-down equivalent resistor are based on a resistive transistor (corresponding
IPU and IPD current characteristics described in Figure 19).
39/53
Electrical parameters
STR73xF
Output Driving Current
Subject to general operating conditions for VDD and T unless otherwise specified.
A
Table 22. Output driving current
I/O Type Symbol
Parameter
Conditions
Min
Max
Unit
Output low level voltage for an I/O pin
when 8 pins are sunk at same time
1)
IIO=+2mA
0.4
VOL
Standard
Output high level voltage for an I/O pin
when 4 pins are sourced at same time
2)
IIO=-2mA
VDD-0.8
VOH
1)
Med.
VOL
IIO=+6mA
IIO=-6mA
IIO=+8mA
IIO=-8mA
Output low level voltage for an I/O pin
Output high level voltage for an I/O pin
Output low level voltage for an I/O pin
Output high level voltage for an I/O pin
0.4
0.4
V
Current
2)
VDD-0.8
VDD-0.8
VOH
VOL
VOH
(JTDO)
1)
2)
High
Current
P6.0
Notes:
1. The IIO current sunk must always respect the absolute maximum rating specified in Table 5 and the sum of
IIO (I/O ports and control pins) must not exceed IVSS
.
2. The IIO current sourced must always respect the absolute maximum rating specified in Table 5 and the
sum of IIO (I/O ports and control pins) must not exceed IVDD
.
Figure 13. V standard ports vs I @ V 5V Figure 14. V standard ports vs I @ V 5V
OH
OH
DD
OL
OL
DD
TA -45°c
5.10
5.00
4.90
4.80
4.70
4.60
4.50
0.25
0.20
0.15
0.10
0.05
0.00
Ta -45°C
Ta 25°C
Ta 90°C
Ta 110°C
Ta -45°C
Ta 25°C
Ta 90°C
Ta 110°C
0
1
2
3
4
0
1
2
3
4
Ioh (mA)
Iol (mA)
40/53
STR73xF
Electrical parameters
Figure 15. V JTDO pin vs I @ VDD 5V
Figure 16. V JTDO pin vs I @ VDD 5V
OL OL
OH
OL
5.10
5.00
4.90
4.80
4.70
4.60
4.50
0.14
0.12
0.10
0.08
0.06
0.04
0.02
0.00
Ta -45°C
Ta -45°C
Ta 25°C
Ta 90°C
Ta 110°C
Ta 25°C
Ta 90°C
Ta 110°C
0
1
2
3
4
5
6
0
1.2
2.4
3.6
4.8
6
Ioh (mA)
Iol (mA)
Figure 17. V P6.0 pin vs I @ VDD 5V
Figure 18. V P6.0 pin vs I @ V 5V
OL OL DD
OH
OL
5.10
5.00
4.90
4.80
4.70
4.60
4.50
0.18
0.16
0.14
0.12
0.10
0.08
0.06
0.04
0.02
0.00
Ta -45°C
Ta -45°C
Ta 25°C
Ta 90°C
Ta 110°C
Ta 25°C
Ta 90°C
Ta 110°C
0
1
2
3
4
5
6
7
8
0
1
2
3
4
5
6
7
8
Ioh (mA)
Iol (mA)
41/53
Electrical parameters
STR73xF
NRSTIN Pin
NRSTIN Pin Input Driver is CMOS. A permanent pull-up is present which is the same as
(see : General Characteristics on page 39)
R
PU
Subject to general operating conditions for VDD and T unless otherwise specified.
A
Table 23. Reset pin characteristics
Typ 1)
Symbol
VIL(NRSTIN)
VIH(NRSTIN)
Parameter
Conditions
Min
Max
Unit
RSTIN Input low level voltage 1)
RSTIN Input high level voltage 1)
0.3 VDD
V
0.7 VDD
RSTIN Schmitt trigger voltage
hysteresis 2)
Vhys(NRSTIN)
800
mV
RSTIN Input filtered pulse3)
VF(RSTINn)
VNF(RSTINn)
VRP(RSTINn)
500
ns
µs
µs
RSTIN Input not filtered pulse3)
RSTIN removal after Power-up3)
2
100
Notes:
1. Data based on characterization results, not tested in production.
2. Hysteresis voltage between Schmitt trigger switching levels.
3. Data guaranteed by design, not tested in production.
1)
Figure 19. Recommended NRSTIN pin protection
VDD
RPU
EXTERNAL
RESET
INTERNAL RESET
Filter
CIRCUIT
STR7X
0.01µF
Required
Notes:
1. The RPU pull-up equivalent resistor is based on a resistive transistor.
2. The reset network protects the device against parasitic resets.
3. The user must ensure that the level on the NRSTIN pin can go below the VIL(NRSTIN) max. level specified in
Table 23. Otherwise the reset will not be taken into account internally.
42/53
STR73xF
Electrical parameters
Figure 20. NRSTIN R vs. V
PU
DD
250
200
150
100
50
25C
-45C
110C
0
3
3.5
4
4.5
5
5.5
Vdd (v)
43/53
Electrical parameters
STR73xF
3.3.6
10-bit ADC characteristics
Subject to general operating conditions for V
, f
, and T unless otherwise specified.
DDA MCLK A
Table 24. ADC characteristics
Typ 1)
Symbol
Parameter
Conditions
Min
0.4
Max
Unit
fADC
VAIN
10
MHz
V
Conversion voltage range 2)
VSSA
VDDA
VIN<VSS, | IIN |<
400µA on adjacent
analog pin
Negative input leakage current on
analog pins
Ilkg
5
6
µA
Internal sample and hold
capacitor
CADC
3.5
pF
580.2
5802
µs
2)
fADC = 10MHz
Calibration Time
Sampling time
tCAL
1/fADC
3)
f
ADC = 10MHz
1
3
14
µs
µs
tS
Total Conversion time (including
sampling time)
30 (10 for sampling
+20 for successive
approximation)
tCONV
fADC = 10MHz
Normal Mode
1/fADC
Running mode
5
mA
IADC
Power-down mode
1
µA
Notes:
1. Unless otherwise specified, typical data are based on TA=25°C and VDDA-VSS=5.0V. They are given only
as design guidelines and are not tested.
2. Calibration is recommended once after each power-up.
3. During the sample time the input capacitance CAIN (6.8 max) can be charged/discharged by the external
source. The internal resistance of the analog source must allow the capacitance to reach its final voltage
level within tS. After the end of the sample time tS, changes of the analog input voltage have no effect on
the conversion result. Values for the sample clock tS depend on programming.
Table 25. ADC Accuracy with f
= 20MHz, f
=10MHz, R
< 10kΩRAIN,
MCLK
ADC
AIN
2)
V
=5V. This assumes that the ADC is calibrated
DDA
Symbol
|ET|
Parameter
Conditions
Typ
1.0
Max
2.0
1.0
1.1
1.0
1.5
Unit
Total unadjusted error 1)
Offset error 1)
|EO|
0.15
0.97
0.7
Gain Error 1)
|EG|
LSB
Differential linearity error1)
Integral linearity error 1)
|ED|
|EL|
0.76
1. ADC Accuracy vs. Negative Injection Current: Injecting negative current on any of the standard (non-
robust) analog input pins should be avoided as this significantly reduces the accuracy of the conversion
being performed on another analog input. It is recommended to add a Schottky diode (pin to ground) to
standard analog pins which may potentially inject negative current. The effect of negative injection current
44/53
STR73xF
Electrical parameters
on robust pins is specified in Section 3.3.5.
Any positive injection current within the limits specified for IINJ(PIN) and ΣIINJ(PIN) in Section 3.3.5 does not
affect the ADC accuracy.
2. Calibration is needed once after each power-up.
Figure 21. ADC Accuracy Characteristics
E
G
(1) Example of an actual transfer curve
(2) The ideal transfer curve
1023
1022
1021
V
– V
(3) End point correlation line
DDA
SSA
1LSB
= ----------------------------------------
IDEAL
1024
(2)
E =Total Unadjusted Error: maximum deviation
T
E
between the actual and the ideal transfer curves.
T
(3)
7
6
5
4
3
2
1
E
=Offset Error: deviation between the first actual
O
transition and the first ideal one.
=Gain Error: deviation between the last ideal
(1)
E
G
transition and the last actual one.
E
O
E
L
E =Differential Linearity Error: maximum deviation
D
between actual steps and the ideal one.
E =Integral Linearity Error: maximum deviation
L
E
between any actual transition and the end point
correlation line.
D
1 LSB
IDEAL
V
0
1
2
3
4
5
6
7
1021 1022 1023 1024
V
V
DDA
SSA
Figure 22. Typical Application with ADC
V
DD
STR73X
V
T
0.6V
2.3kΩ(max)
R
AIN
AINx
10-Bit A/D
Conversion
V
AIN
C
V
T
0.6V
AIN
I
C
ADC
3.5pF
L
1µA
45/53
Electrical parameters
STR73xF
Analog Power Supply and Reference Pins
The V
and V
pins are the analog power supply of the A/D converter cell. They act as
SSA
DDA
the high and low reference voltages for the conversion.
Separation of the digital and analog power pins allow board designers to improve A/D
performance. Conversion accuracy can be impacted by voltage drops and noise in the event
of heavily loaded or badly decoupled power supply lines (see: General PCB Design
Guidelines).
General PCB Design Guidelines
To obtain best results, some general design and layout rules should be followed when
designing the application PCB to shield the noise-sensitive, analog physical interface from
noise-generating CMOS logic signals.
●
Use separate digital and analog planes. The analog ground plane should be connected
to the digital ground plane via a single point on the PCB.
●
Filter power to the analog power planes. It is recommended to connect capacitors, with
good high frequency characteristics, between the power and ground lines, placing
0.1µF and optionally, if needed 10pF capacitors as close as possible to the STR7
power supply pins and a 1 to 10µF capacitor close to the power source (see Figure 23).
●
●
The analog and digital power supplies should be connected in a star network. Do not
use a resistor, as V
is used as a reference voltage by the A/D converter and any
DDA
resistance would cause a voltage drop and a loss of accuracy.
Properly place components and route the signal traces on the PCB to shield the analog
inputs. Analog signals paths should run over the analog ground plane and be as short
as possible. Isolate analog signals from digital signals that may switch while the analog
inputs are being sampled by the A/D converter. Do not toggle digital outputs near the
A/D input being converted.
Software Filtering of Spurious Conversion Results
For EMC performance reasons, it is recommended to filter A/D conversion outliers using
software filtering techniques.
Figure 23. Power Supply Filtering
STR73x
1 to 10µF
0.1µF
V
V
SS
DD
STR7
DIGITAL NOISE
FILTERING
5V
POWER
SUPPLY
SOURCE
V
V
0.1µF
DDA
SSA
EXTERNAL
NOISE
FILTERING
46/53
STR73xF
Package characteristics
4
Package characteristics
4.1
Package mechanical data
Figure 24. 100-pin thin quad flat package
mm
inches
A
D
Dim.
Min Typ Max Min Typ Max
D1
A2
A
1.60
0.063
0.006
A1
A1 0.05
0.15 0.002
A2 1.35 1.40 1.45 0.053 0.055 0.057
b
C
0.17 0.22 0.27 0.007 0.009 0.011
0.09 0.20 0.004 0.008
b
e
D
16.00
14.00
16.00
14.00
0.50
0.630
0.551
0.630
0.551
0.020
3.5°
D1
E
E1
E
E1
e
θ
0°
3.5°
7°
0°
7°
L
0.45 0.60 0.75 0.018 0.024 0.030
1.00 0.039
Number of Pins
100
c
L1
L
1
L
h
N
Figure 25. 144-pin thin quad flat package
mm
inches
Dim.
Min Typ Max Min Typ Max
D
A
1.60
0.063
0.006
0.057
0.011
0.008
D1
D3
A
A1 0.05
0.15 0.002
A2
A1
A2 1.35 1.40 1.45 0.053
108
109
73
b
c
0.17 0.22 0.27 0.007
0.09 0.20 0.004
72
0.10mm
.004 in.
Seating Plane
b
D
21.80 22.00 22.20 0.858 0.867 0.874
b
D1 19.80 20.00 20.20 0.780 0.787 0.795
E
E1
E3
D3
E
17.50
0.699
21.80 22.00 22.20 0.858 0.867 0.874
E1 19.80 20.00 20.20 0.780 0.787 0.795
37
144
1
36
E3
e
17.50
0.50
3.5°
0.699
0.020
3.5°
c
e
L1
K
0°
7°
0°
7°
L
L
0.45 0.60 0.75 0.018 0.024 0.030
1.00 0.039
Number of Pins
144
h
L1
N
47/53
Package characteristics
Figure 26. 144-ball low profile fine pitch ball grid array package
STR73xF
mm
inches
Dim.
A
Min Typ Max Min Typ Max
1.21
1.70 0.048
0.008
0.067
A1 0.21
A2
1.085
0.043
b
D
0.35 0.40 0.45 0.014 0.016 0.018
9.85 10.00 10.15 0.388 0.394 0.400
D1
E
8.80
0.346
9.85 10.00 10.15 0.388 0.394 0.400
E1
e
8.80
0.80
0.60
0.346
0.031
0.024
F
ddd
eee
fff
0.10
0.15
0.08
0.004
0.006
0.003
Number of Pins
N
144
Figure 27. Recommended PCB Design rules (0.80/0.75mm pitch BGA)
Dpad
Dsm
0.37 mm
0.52 mm typ. (depends on solder
mask registration tolerance
Solder paste 0.37 mm aperture diameter
– Non solder mask defined pads are recommended
– 4 to 6 mils screen print
Dpad
Dsm
48/53
STR73xF
Package characteristics
4.2
Thermal characteristics
The average chip-junction temperature, T , in degrees Celsius, may be calculated using the
J
following equation:
T = T + (P x Θ )
(1)
J
A
D
JA
Where:
–
–
–
–
T is the Ambient Temperature in °C,
A
Θ
is the Package Junction-to-Ambient Thermal Resistance, in °C/W,
JA
P is the sum of P
and P (P = P
+ P ),
INT I/O
D
INT
I/O
D
P
is the product of I and V , expressed in Watt. This is the Chip Internal
DD DD
INT
Power,
P represents the Power Dissipation on Input and Output Pins; User Determined.
I/O
–
Most of the time for the applications P < P
and may be neglected. On the other hand,
INT
I/O
P
may be significant if the device is configured to drive continuously external modules
I/O
and/or memories.
An approximate relationship between P and T (if P is neglected) is given by:
D
J
I/O
P = K / (T + 273°C)
(2)
(3)
D
J
Therefore (solving equations 1 and 2):
K = P x (T + 273°C) + Θ x P
D
2
D
A
JA
Where:
–
K is a constant for the particular part, which may be determined from equation (3)
by measuring P (at equilibrium) for a known T Using this value of K, the values
D
A.
of P and T may be obtained by solving equations (1) and (2) iteratively for any
D
J
value of T
A
Table 26. Thermal Characteristics
Symbol
Description
Package
Value (typical)
Unit
LFBGA144
50
40
40
ΘJA
Thermal Resistance Junction-Ambient TQFP144
TQFP100
°C/W
49/53
Order codes
STR73xF
5
Order codes
Table 27. Order Codes
TIM
6x PWM CAN
A/D
FLASH
Partnumber
RAM
Kbytes
Wake-up
Lines
I/O
Temp.
Package
Kbytes
Ports Range
Timers Module Periph Chan.
STR730FZ1T6
STR730FZ2T6
STR730FZ1H6
STR730FZ2H6
STR735FZ1T6
STR735FZ2T6
STR735FZ1H6
STR735FZ2H6
STR731FV0T6
STR731FV1T6
STR731FV2T6
STR736FV0T6
STR736FV1T6
STR736FV2T6
STR730FZ1T7
STR730FZ2T7
STR730FZ1H7
STR730FZ2H7
STR735FZ1T7
STR735FZ2T7
STR735FZ1H7
STR735FZ2H7
STR731FV0T7
STR731FV1T7
STR731FV2T7
STR736FV0T7
STR736FV1T7
STR736FV2T7
128
256
128
256
128
256
128
256
64
TQFP144
20x20
3
LFBGA144
10x10
10
16
12
16
12
32
18
32
18
112
TQFP144
20x20
0
LFBGA144
10x10
-40 to
+85°C
16
1
TQFP100
14x14
128
256
64
3
0
6
72
TQFP100
14x14
128
256
128
256
128
256
128
256
128
256
64
TQFP144
20x20
3
0
LFBGA144
10x10
10
112
TQFP144
20x20
LFBGA144
10x10
-40 to
+105°C
16
1
TQFP100
14x14
128
256
64
3
0
6
72
TQFP100
14x14
128
256
50/53
STR73xF
Known limitations
6
Known limitations
6.1
Low Power Wait For Interrupt mode
When the STR73x device is put in Low Power Wait For Interrupt mode (LPWFI), the Flash
goes into Low Power mode or Power Down mode, depending on the setting of the PWD bit
in the Flash Control Register 0 (default is ‘0’, Low Power mode). This default mode can
create excessive voltage conditions on the transistor gates and may affect the long term
behavior of the Low Power mode circuitry.
Workaround
There is no workaround. If Low Power Wait For Interrupt mode is used, it is strongly
suggested to configure the Flash to enter Power Down mode (bit PWD = ‘1’).
6.2
PLL free running mode at high temperature
When the STR73x device is operated and an ambient temperature (T ) of more than 55°C
A
and the main system clock (f
may not work properly.
) is sourced by the PLL in free running mode, the device
MCLK
Workaround
At high temperature (more than 55°C), it is recommended to use the internal RC oscillator
as a backup clock source rather than the PLL free running mode.
51/53
Revision history
STR73xF
7
Revision history
Table 28. Revision history
Date
Revision
Description of Changes
19-Sep-2005
1
First release
Removed Table 8 power consumption in LP modes
2-Nov-2005
8-Mar-2006
2
3
Updated PLL frequency in Section 1.1 and Table 12
Section 3.4: Preliminary power consumption data updated
Section 3.5: DC electrical characteristics updated
Section 6: Known limitations added.
Section 3: Electrical parameters updated
Section 6: Known limitations updated
4-Jun-2006
19-Jun-2006
08-Sep-2006
4
5
6
Added temperature range -40°C to 85°C in Section 5: Order
codes
Changed Flash data retention to 20 years at 85°C in Table 17 on
page 35.
Changed Table 22: Output driving current on page 40
Added Figure 14: VOL standard ports vs IOL @ VDD 5V thru
Figure 18: VOL P6.0 pin vs IOL @ VDD 5V on page 41.
Added Figure 20: NRSTIN RPU vs. VDD
52/53
STR73xF
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53/53
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