STR755FR2T6 [STMICROELECTRONICS]
ARM7TDMI-S, 32-bit MCU with Flash, SMI, 3 std 16-bit timers PWM timer, fast 10-bit ADC, I2C, UART, SSP, USB and CAN; ARM7TDMI -S ， 32位MCU和Flash ， SMI ， 3性病16位定时器PWM计时器，快速10位ADC ， I2C ， UART ， SSP ， USB和CAN
| 型号： | STR755FR2T6 |
| 厂家： | 
ST |
| 描述： | ARM7TDMI-S, 32-bit MCU with Flash, SMI, 3 std 16-bit timers PWM timer, fast 10-bit ADC, I2C, UART, SSP, USB and CAN |
| 文件： | 总73页 (文件大小：1734K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
STR750F
ARM7TDMI-S™ 32-bit MCU with Flash, SMI, 3 std 16-bit timers,
PWM timer, fast 10-bit ADC, I2C, UART, SSP, USB and CAN
■ Core
– ARM7TDMI-S 32-bit RISC CPU
– 54 DMIPS @ 60 MHz
■ Memories
– Up to 256 KB Flash program memory (10k
erase/write cycles, retention 20 yrs at
85°C)
LQFP64 10x10 mm LQFP100 14 x 14 mm
– 16KB Read-While-Write Flash for data
(100k erase/write cycles, retention 20 yrs@
85°C)
LFBGA64
8 x 8 x 1.7 mm
LFBGA100
10 x 10 x 1.7 mm
– Flash Data Readout and Write Protection
– 16KBytes embedded high speed SRAM
– Memory mapped interface (SMI) to ext.
Serial Flash (64 MB) w. boot capability
– 16-bit timer for system timebase functions
– 3 synchronizable timers each with up to 2
input captures and 2 output
compare/PWMs.
■ Clock, Reset and Supply Management
– Single supply 3.3V 10% or 5V 10%
– 16-bit 6-channel synchronizable PWM
timer
– Embedded 1.8V Voltage Regulators with
Low Power features
– Dead time generation, edge/center-aligned
waveforms and emergency stop
– Smart Clock Controller with flexible clock
generation capability:
– Ideal for induction/brushless DC motors
– Internal RC for fast start-up and backup
clock mechanism
– Up to 60 MHz operation using internal PLL
with 4 or 8 MHz crystal/ceramic osc.
– Smart Low Power Modes: SLOW, WFI,
STOP and STANDBY with backup registers
■ 8 Communications Interfaces
2
– 1 I C interface
– 3 HiSpeed UARTs w. Modem/LIN capability
– 2 SSP interfaces (SPI or SSI) up to 16 Mb/s
– 1 CAN interface (2.0B Active)
– 1 USB full-speed 12 Mb/s interface with 8
configurable endpoint sizes
– Real Time Clock, driven by low power
internal RC or 32.768 kHz dedicated osc,
for clock-calendar and Auto Wake-up
■ 10-bit A/D Converter
■ Nested interrupt controller
– 16/11 chan. with prog. Scan Mode & FIFO
– Programmable Analog Watchdog feature
– Conversion: min. 3.75 µs, range: 0 to
– Fast interrupt handling with 32 vectors
– 16 IRQ priorities, 2 maskable FIQ sources
– 16 external interrupt / wake-up Lines
V
DD_IO
■ DMA
– Start conversion can be triggered by timers
– 4-channel DMA controller
– Circular buffer management
– Support for UART, SSP, Timers, ADC
■ Up to 72/38 I/O ports
– 72/38 GPIO lines with High Sink
capabilities
■ 6 Timers
– Atomic bit SET and RES operations
– 16-bit watchdog timer (WDG)
October 2006
Rev 2
1/71
www.st.com
1
Contents
STR750F
Contents
1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.1
1.2
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2
3
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.0.1
Pin Description Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.1
Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Electrical parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.1
Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.1.1
3.1.2
3.1.3
3.1.4
3.1.5
3.1.6
3.1.7
3.1.8
Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Power Supply Schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
I/O characteristics versus the various power schemes (3.3V or 5.0V) . 28
Current Consumption Measurements . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.2
3.3
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
3.2.1
3.2.2
3.2.3
Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
3.3.1
3.3.2
3.3.3
3.3.4
3.3.5
3.3.6
3.3.7
3.3.8
3.3.9
General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . 33
Embedded voltage regulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Clock and timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
I/O port pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
TB and TIM timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
3.3.10 Communication interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . 58
3.3.11 USB characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
2/76
STR750F
Contents
3.3.12 10-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
4
4.1
4.2
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
5
6
Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
3/76
Introduction
STR750F
1
Introduction
This Datasheet contains the description of the STR750 family features, pinout, Electrical
Characteristics, Mechanical Data and Ordering information.
For complete information on the Microcontroller memory, registers and peripherals. Please
refer to the STR750 Reference Manual.
For information on the ARM7TDMI-S core please refer to the ARM7TDMI-S Technical
Reference Manual available from Arm Ltd.
For information on programming, erasing and protection of the internal Flash memory
please refer to the STR7 Flash Programming Reference Manual
For information on third-party development tools, please refer to the http://www.st.com/mcu
website.
Table 1.
Device summary
STR755FRx
Features
STR751FRx
STR752FRx STR755FVx STR750FVx
Flash - Bank 0
(bytes)
64K/128K/256K
Flash - Bank 1
(bytes)
16K RWW
16K
RAM (bytes)
Operating Temp.
-40 to +85°C / -40 to +105°C (see Table 44)
3 UARTs, 2 SSPs, 1 I2C,
3 UARTs, 2 SSPs, 1 I2C, 3 timers 1 PWM timer, 3 timers 1 PWM timer, 72
Common Peripherals
38 I/Os 13 Wake-up lines, 11 A/D Channels
I/Os 15 Wake-up lines, 16
A/D Channels
USB/CAN
peripherals
None
USB
3.3V
CAN
None
USB+CAN
Operating Voltage
3.3V or 5V
3.3V or 5V
T=LQFP100 14x14,
H=LFBGA100
Packages (x)
T=LQFP64 10x10, H=LFBGA64
4/71
STR750F
Introduction
1.1
Overview
The STR750 family includes devices in 2 package sizes: 64-pin and 100-pin. Both types
have the following common features:
TM
ARM7TDMI-S core with embedded Flash & RAM
STR750 family has an embedded ARM core and is therefore compatible with all ARM tools
TM
and software. It combines the high performance ARM7TDMI-S CPU with an extensive
range of peripheral functions and enhanced I/O capabilities. All devices have on-chip high-
speed single voltage FLASH memory and high-speed RAM.
Figure 1 shows the general block diagram of the device family.
Embedded Flash Memory
Up to 256 KBytes of embedded Flash is available in Bank 0 for storing programs and data.
An additional Bank 1 provides 16 Kbytes of RWW (Read While Write) memory allowing it to
be erased/programmed on-the-fly. This partitioning feature is ideal for storing application
parameters.
●
When configured in burst mode, access to Flash memory is performed at CPU clock
speed with 0 wait states for sequential accesses and 1 wait state for random access
(maximum 60 MHz).
●
When not configured in burst mode, access to Flash memory is performed at CPU
clock speed with 0 wait states (maximum 32 MHz)
Embedded SRAM
16 Kbytes of embedded SRAM accessed (read/write) at CPU clock speed with 0 wait states.
Enhanced Interrupt Controller (EIC)
In addition to the standard ARM interrupt controller, the STR750F embeds a nested interrupt
controller able to handle up to 32 vectors and 16 priority levels. This additional hardware
block provides flexible interrupt management features with minimal interrupt latency.
Serial Memory Interface (SMI)
The Serial Memory interface is directly able to access up to 4 serial FLASH devices. It
communicates at a speed of up to 48 MHz. It can be used to access data, execute code
directly or boot the application from external memory. The memory is addressed as 4 banks
of up to 16 Mbytes each.
Clocks and start-up
After RESET or when exiting from Low Power Mode, the CPU is clocked immediately by an
internal RC oscillator (FREEOSC) at a frequency centered around 5 MHz, so the application
code can start executing without delay. In parallel, the 4/8 MHz Oscillator is enabled and its
stabilization time is monitored using a dedicated counter.
An oscillator failure detection is implemented: when the clock disappears on the XT1 pin, the
circuit automatically switches to the FREEOSC oscillator and an interrupt is generated.
In Run mode, the AHB and APB clock speeds can be set at a large number of different
frequencies thanks to the PLL and various prescalers: up to 60 MHz for AHB and up to 32
MHz for APB when fetching from Flash (64 MHz and 32 MHz when fetching from SRAM).
5/71
Introduction
STR750F
In SLOW mode, the AHB clock can be significantly decreased to reduce power
consumption.
The built-in Clock Controller also provides the 48 MHz USB clock directly without any extra
oscillators or PLL. For instance, starting from the 4 MHz crystal source, it is possible to
obtain in parallel 60 MHz for the AHB clock, 48 MHz for the USB clock and 30 MHz for the
APB peripherals.
Boot modes
At start-up, boot pins are used to select one of five boot options:
●
Boot from internal flash
●
●
●
Boot from external serial Flash memory
Boot from internal boot loader
Boot from internal SRAM
Booting from SMI memory allows booting from a serial flash. This way, a specific boot
monitor can be implemented. Alternatively, the STR750F can boot from the internal boot
loader that implements a boot from UART.
Power Supply Schemes
You can connect the device in any of the following ways depending on your application.
●
Power Scheme 1: Single external 3.3V power source. In this configuration the
supply required for the internal logic is generated internally by the main voltage
V
CORE
regulator and the V
supply is generated internally by the low power voltage
BACKUP
regulator. This scheme has the advantage of requiring only one 3.3V power source.
●
Power Scheme 2: Dual external 3.3V and 1.8V power sources. In this configuration,
the internal voltage regulators are switched off by forcing the VREG_DIS pin to high
level. V
is provided externally through the V and V
power pins and
CORE
18
18REG
V
through the V
pin. This scheme is intended to save power consumption
BACKUP
18_BKP
for applications which already provide an 1.8V power supply.
●
●
Power Scheme 3: Single external 5.0V power source. In this configuration the
V
supply required for the internal logic is generated internally by the main voltage
CORE
regulator and the V
supply is generated internally by the low power voltage
BACKUP
regulator. This scheme has the advantage of requiring only one 5.0V power source.
Power Scheme 4: Dual external 5.0V and 1.8V power sources. In this configuration,
the internal voltage regulators are switched off, by forcing the VREG_DIS pin to high
level. V
is provided externally through the V and V
power pins and
CORE
18
18REG
V
through the V
pin. This scheme is intended to provide 5V I/O capability.
BACKUP
18_BKP
Caution: When powered by 5.0V, the USB peripheral cannot operate.
6/71
STR750F
Introduction
Low Power modes
The STR750F supports 5 low power modes, SLOW, PCG, WFI, STOP and STANDBY.
●
SLOW MODE: the system clock speed is reduced. Alternatively, the PLL and the main
oscillator can be stopped and the device is driven by a low power clock (f ). The
RTC
clock is either an external 32.768 kHz oscillator or the internal low power RC oscillator.
●
●
●
PCG MODE (Peripheral Clock Gating MODE): When the peripherals are not used, their
APB clocks are gated to optimize the power consumption.
WFI MODE (Wait For Interrupts): only the CPU clock is stopped, all peripherals
continue to work and can wake-up the CPU when IRQs occur.
STOP MODE: all clocks/peripherals are disabled. It is also possible to disable the
oscillators and the Main Voltage Regulator (In this case the V
is entirely powered
CORE
by V
). This mode is intended to achieve the lowest power consumption with
18_BKP
SRAM and registers contents retained. The system can be woken up by any of the
external interrupts / wake-up lines or by the RTC timer which can optionally be kept
running. The RTC can be clocked either by the 32.768 kHz Crystal or the Low Power
RC Oscillator.
Alternatively, STOP mode gives flexibility to keep the either main oscillator, or the Flash
or the Main Voltage Regulator enabled when a fast start after wake-up is preferred (at
the cost of some extra power consumption).
●
STANDBY MODE: This mode (only available in single supply power schemes) is
intended to achieve the lowest power consumption even when the temperature is
increasing. The digital power supply (V
) is completely removed (no leakage even
CORE
at high ambient temperature). SRAM and all register contents are lost. Only the RTC
remains powered by V . The STR750F can be switched back from STANDBY to
18_BKP
RUN mode by a trigger event on the WKP_STDBY pin or an alarm timeout on the RTC
counter.
Caution:
It is important to bear in mind that it is forbidden to remove power from the V
supply in any of the Low Power Modes (even in STANDBY MODE).
power
DD_IO
DMA
The flexible 4-channel general-purpose DMA is able to manage memory to memory,
peripheral to memory and memory to peripheral transfers. The DMA controller supports
circular buffer management avoiding the generation of interrupts when the controller
reaches the end of the buffer.
The DMA can be used with the main peripherals: UART0, SSP0, Motor control PWM timer
(PWM), standard timer TIM0 and ADC.
RTC (Real Time Clock)
The real time clock provides a set of continuously running counters which can be used with
suitable software to provide a clock calendar function, and provides an alarm interrupt and a
periodic interrupt. It is clocked by an external 32.768 kHz oscillator or the internal low power
RC oscillator. The RC has a typical frequency of 300 kHz and can be calibrated.
WDG (Watchdog Timer)
The watchdog timer is based on a 16-bit downcounter and 8-bit prescaler. It can be used as
watchdog to reset the device when a problem occurs, or as free running timer for application
time out management.
7/71
Introduction
STR750F
Timebase Timer (TB)
The timebase timer is based on a 16-bit auto-reload counter and not connected to the I/O
pins. It can be used for software triggering, or to implement the scheduler of a real time
operating system.
Synchronizable Standard Timers (TIM2:0)
The three standard timers are based on a 16-bit auto-reload counter and feature up to 2
input captures and 2 output compares (for external triggering or time base / time out
management). They can work together with the PWM timer via the Timer Link feature for
synchronization or event chaining. In reset state, timer Alternate Function I/Os are
connected to the same
I/O ports in both 64-pin and 100-pin devices. To optimize timer functions in 64-pin devices,
timer Alternate Function I/Os can be connected, or “remapped”, to other I/O ports as
summarized in Table 2 and detailed in Table 5. This remapping is done by the application via
a control register.
Table 2. Standard timer alternate function I/Os
Number of Alternate Function I/Os
Standard Timer Functions
64-pin package
100-pin
package
Default mapping
Remapped
Input Capture
2
2
2
2
2
2
1
1
1
1
2
1
2
2
1
1
2
2
TIM 0
Output Compare/PWM
Input Capture
TIM 1
TIM 2
Output Compare/PWM
Input Capture
Output Compare/PWM
Any of the standard timers can be used to generate PWM outputs. One timer (TIM0) is
mapped to a DMA channel.
Motor Control PWM timer (PWM)
The Motor Control PWM Timer (PWM) can be seen as a three-phase PWM multiplexed on 6
channels. The 16-bit PWM generator has full modulation capability (0...100%), edge or
centre-aligned patterns and supports dead-time insertion. It has many features in common
with the standard TIM timers which has the same architecture and it can work together with
the TIM timers via the Timer Link feature for synchronization or event chaining.The PWM
timer is mapped to a DMA channel.
I²C bus
The I²C bus interface can operate in multi-master and slave mode. It can support standard
and fast modes (up to 400KHz).
8/71
STR750F
Introduction
High Speed Universal Asynch. Receiver Transmitter (UART)
The three UART interfaces are able to communicate at speeds of up to 2 Mbit/s. They
provide hardware management of the CTS and RTS signals and have LIN Master capability.
To optimize the data transfer between the processor and the peripheral, two FIFOs
(receive/transmit) of 16 bytes each have been implemented.
One UART can be served by the DMA controller (UART0).
Synchronous Serial Peripheral (SSP)
The two SSPs are able to communicate up to 8 Mbit/s (SSP1) or up to 16 Mbit/s (SSP0) in
standard full duplex 4-pin interface mode as a master device or up to 2.66 Mbit/s as a slave
device. To optimize the data transfer between the processor and the peripheral, two FIFOs
(receive/transmit) of 8 x 16 bit words have been implemented. The SSPs support the
Motorola SPI or TI SSI protocols.
One SSP can be served by the DMA controller (SSP0).
Controller Area Network (CAN)
The CAN is compliant with the specification 2.0 part B (active) with a bit rate up to 1Mbit/s. It
can receive and transmit standard frames with 11-bit identifiers as well as extended frames
with 29-bit identifiers. Up to 32 message objects are handled through an internal RAM
buffer. In LQFP64 devices, CAN and USB cannot be connected simultaneously.
Universal Serial Bus (USB)
The STR750F embeds a USB device peripheral compatible with the USB Full speed 12Mbs.
The USB interface implements a full speed (12 Mbit/s) function interface. It has software
configurable endpoint setting and suspend/resume support. The dedicated 48 MHz clock
source is generated from the internal main PLL. V must be in the range 3.3V 10% for
DD
USB operation.
ADC (Analog to Digital Converter)
The 10-bit Analog to Digital Converter, converts up to 16 external channels (11 channels in
64-pin devices) in single-shot or scan modes. In scan mode, continuous conversion is
performed on a selected group of analog inputs. The minimum conversion time is 3.75 µs
(including the sampling time).
The ADC can be served by the DMA controller.
An analog watchdog feature allows you to very precisely monitor the converted voltage of up
to four channels. An IRQ is generated when the converted voltage is outside the
programmed thresholds.
The events generated by TIM0, TIM2 and PWM timers can be internally connected to the
ADC start trigger, injection trigger, and DMA trigger respectively, to allow the application to
synchronize A/D conversion and timers.
GPIOs (General Purpose Input/Output)
Each of the 72 GPIO pins (38 GPIOs in 64-pin devices) can be configured by software as
output (push-pull or open-drain), as input (with or without pull-up or pull-down) or as
Peripheral Alternate Function. Port 1.15 is an exception, it can be used as general-purpose
input only or wake-up from STANDBY mode (WKP_STDBY). Most of the GPIO pins are
shared with digital or analog alternate functions.
9/71
Introduction
STR750F
1.2
Block Diagram
Figure 1.
STR750 block diagram
BOOT1,
BOOT0
ARM7TDMI-S
CPU
as AF
HRESETN
PRESETN
NRSTIN
NRSTOUT
RESET &
POWER
TEST
NJTRST
60MHz
AHB
AHB
VDD_IO
VCORE
VBACKUP
VDDA_PLL
VDDA_ADC
SRAM 16KB
DC-DC
JTAG & ICE-RT
VDD_IO
V18
V18BKP
VSS
JTDI
JTCK
JTMS
JTDO
as AF
3.3V TO 1.8V
GP DMA
4 streams
MAIN
FLASH 256KB
+16KB (RWW)
LOW POWER
32xIRQ
2xFIQ
NESTED
INTERRUPT CTL
Arbiter
LP
OSC
SCLK, MOSI
MISO as AF
4 CS as AF
SERIAL MEMORY
INTERFACE
CK_RTC
RTC_XT1
RTC_XT2
OSC
32K
CK_SYS
HCLK
CLOCK
MANAGE-
MENT
FREE
OSC
PCLK
XT1
XT2
OSC
4M
APB
BRIDGE
PLL
VDDA_PLL
VSSA_PLL
CK_USB
USBDP
USBDM
EXT.IT
WAKEUP
15AF
USB Full Speed
P0[31:0]
P1[19:0]
P2[19:0]
GPIO PORT 0
GPIO PORT 1
GPIO PORT 2
RX,TX
as AF
CAN 2.0B
FIFO
RX,TX,CTS,
RTS as AF
UART0
UART1
UART2
2x(16x8bit)
16AF
VDDA_ADC
VSSA_ADC
FIFO
RX,TX,CTS,
RTS as AF
10-bit ADC
2x(16x8bit)
FIFO
RX,TX,CTS,
RTS as AF
WATCHDOG
RTC
2x(16x8bit)
FIFO
MOSI,MISO,
SSP0
SSP1
2x(8x16bit)
SCK,NSS
as AF
TB TIMER
FIFO
MOSI,MISO,
SCK,NSS
as AF
2x(8x16bit)
2xICAP, 2xOCMP
as AF
TIM0 TIMER
TIM1 TIMER
TIM2 TIMER
2xICAP, 2xOCMP
as AF
SCL,SDA
as AF
I2C
2xICAP, 2xOCMP
as AF
PWM1, PWM1N
PWM2, PWM2N
PWM3, PWM3N
PWM TIMER
APB (up to 32 MHz)
PWM_EMERGENCY
as AF
AF: alternate function on I/O port pin
Note: I/Os shown for 100 pin devices. 64-pin devices have the I/O set shown in Figure 3.
10/71
STR750F
Pin Description
2
Pin Description
Figure 2.
LQFP100 Pinout
ADC_IN13 / P1.12
ADC_IN0 / TIM2_OC1/ P0.02
MCO / TIM0_TI1 / P0.01
BOOT0 / TIM0_OC1 / P0.00
TIM1_TI2 / P0.31
1
2
3
4
5
6
7
8
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
VREG_DIS
V
SS_IO
V
SSA_ADC
P2.10
P2.11
TIM1_OC2 / P0.30
ADC_IN8 / TIM1_TI1 / P0.29
V
V
DDA_ADC
DD_IO
TIM1_OC1 / P0.28
P1.02 / TIM2_OC2
P1.03 / TIM2_TI2
USB_DP
TEST
9
10
11
V
SS_IO
ADC_IN6 / UART1_RTS / P0.23
USB_DN
TIM2_OC1/ P2.04 12
UART1_RTS / P2.03
P2.02
LQFP100
P0.14 / CAN_RX
P0.15 / CAN_TX
P2.12
P2.13
P1.15 / WKP_STDBY
NRSTIN
NRSTOUT
XRTC2
XRTC1
13
14
ADC_IN5 / UART1_CTS / P0.22 15
UART1_TX / P0.21
UART1_RX / P0.20
16
17
JTMS / P1.19 18
JTCK / P1.18
JTDO / P1.17
19
20
V18BKP I/Os
JTDI / P1.16 21
V
V
V
V
18BKP
SSBKP
SS18
NJTRST
P2.01
P2.00 24
UART0_RTS / RTCK / P0.13
22
23
18REG
25
P2.14
= 16 A/D input channels
= 15 External interrupts / Wake-up Lines
11/71
Pin Description
STR750F
Figure 3.
LQFP64 Pinout
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
48
V
V
V
V
V
ADC_IN13 / P1.12
1
REG_DIS
SS_IO_2
SSA_ADC
DDA_ADC
DD_IO_2
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
ADC_IN0 / TIM2_OC1 / P0.02
MCO / TIM0_TI1 / P0.01
BOOT0 / TIM0_OC1 / P0.00
ADC_IN8 / TIM1_TI1 / P0.29
TIM1_OC1 / P0.28
2
3
4
5
P1.03 / TIM2_TI2
6
P0.14 / CAN_RX or USB_DP
P0.15 / CAN_TX or USB_DN
NRSTIN
NRSTOUT
XRTC2
TEST
7
V
8
SS_IO_4
LQFP64
UART1_TX / P0.21
UART1_RX / P0.20
JTMS / P1.19
9
10
11
12
13
14
15
16
V18BKP I/Os
XRTC1
JTCK / P1.18
JTDO / P1.17
JTDI / P1.16
V
18BKP
V
SSBKP
V
NJTRST
UART0_RTS / RTCK / P0.13
SS18
V
18REG
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
= 11 A/D input channels
= 13 External interrupts / Wake-up Lines
12/71
STR750F
Pin Description
Table 3.
LFBGA100 ball connections
1
2
3
4
5
6
7
8
9
10
A
B
C
D
E
F
P0.03 P1.13 P1.14 P1.04 P1.06 P1.08
P1.12 P0.02 P0.01 P1.05 P1.07 P1.09
P0.31 P0.00 VDD_IO V18 P1.10 P2.09
P0.29 P0.30 VSS_IO VSS18 P1.01 P1.15
P0.05
P0.04
VSS_IO
VDD_IO
P0.06
P0.07
P1.03
P1.02
P2.10
P2.13
VSSA_ADC
VDDA_ADC
P2.11 USB_DP
P2.12 USB_DN
P0.28 P0.23 P0.22 VSS_IO TEST P1.00 NRSTOUT VREG_DIS NRSTIN
P0.14
P0.15
P2.03 P0.21 P0.20 P2.02 P2.04 P2.05
NJTRST P1.18 P1.19 P2.01 P2.00 P2.07
P0.13 P1.16 P1.17 P2.19 P2.18 P2.17
P0.11 P0.12 P1.11 P0.27 P0.19 P0.26
P0.10 P0.09 P0.08 P0.18 P0.17 P0.16
P2.06
2.08
VSS18
V18REG
P2.14
P2.15
XT2
VSSBKP
V18BKP
P2.16
G
H
J
XRTC2
XRTC1
VSS_IO
P0.24
P0.25
XT1
VDD_IO
K
VDDA_PLL VSSA_PLL
Table 4.
LFBGA64 ball connections
1
2
3
4
5
6
7
8
A
B
C
D
E
F
P0.03
P1.12
P0.01
P0.29
P1.18
P0.13
P0.11
P0.10
VSS_IO
VDD_IO
P0.02
P0.28
P1.19
NJTRST
P0.12
P0.09
P1.04
P1.05
P0.00
TEST
P0.20
P1.16
P1.11
P0.08
P1.06
P1.07
V18
P1.08
P1.09
VSS18
P0.05
P0.04
VDD_IO
P0.06
P1.10
VSS_IO
P0.07
P1.03
P0.14
VSS_IO VREG_DIS VDDA_ADC VSSA_ADC P0.15
P0.21
P1.17
P0.19
P0.17
NRSTOUT NRSTIN
V18BKP
VSSBKP
XRTC2
XRTC1
V18REG
VDD_IO
P0.18
VSS18
G
H
VSS_IO VDDA_PLL VSSA_PLL
P0.16 XT2 XT1
13/71
Pin Description
STR750F
2.0.1
Pin Description Table
Legend / Abbreviations for Table 5:
Type:
I = input, O = output, S = supply,
Input Levels:
All Inputs are LVTTL at V
= 3.3V+/-0.3V or TTL
DD_IO
at V
= 5V± ±0.5V. In both cases, T means
DD_IO
T
V
=0.8V V
=2.0V
IHmin
ILmax
Inputs:
All inputs can be configured as floating or with
internal weak pull-up or pull down (pu/pd)
Outputs:
All Outputs can be configured as Open Drain (OD) or
Push-Pull (PP) (see also note 6 below Table 5).
There are 3 different types of Output with different
drives and speed characteristics:
– O8: f
= 40 MHz on C =50pF and 8 mA static
max
L
drive capability for V =0.4V and up to 20 mA for
OL
V
=1.3V (seeOutput driving current on page 54)
OL
– O4: f
= 20 MHz on C =50pF and 4 mA static
max
L
drive capability for V =0.4V (seeOutput driving
OL
current on page 54)
– O2: f
= 10 MHz on C =50pF and 2 mA static
max
L
drive capability of for V =0.4V (seeOutput driving
OL
current on page 54)
External Interrupts/wake-up lines: EITx
14/71
STR750F
Pin Description
Port Reset State
The reset state of the I/O ports is GPIO input floating. Exceptions are P1[19:16] and P0.13
which are configured as JTAG alternate functions:
●
●
●
The JTAG inputs (JTDI, JTMS and JTDI) are configured as input floating and are ready
to accept JTAG sequences.
The JTAG output JTDO is configured as floating when idle (no JTAG operation) and is
configured in output push-pull only when serial JTAG data must be output.
The JTAG output RTCK is always configured as output push-pull. It outputs '0' level
during the reset phase and then outputs the JTCK input signal resynchronized 3 times
by the internal AHB clock.
●
The GPIO_PCx registers do not control JTAG AF selection, so the reset values of
GPIO_PCx for P1[19:16] and P0. 13 are the same as other ports. Refer to the GPIO
section of the STR750 Reference Manual for the register description and reset values.
●
●
P0.11 and P0.00 are sampled by the boot logic after reset, prior to fetching the first
word of user code at address 0000 0000h.
When booting from SMI (and only in this case), the reset state of the following GPIOs is
"SMI alternate function output enabled":
–
–
–
–
P0.07 (SMI_DOUT)
P0.05 (SMI_CLK)
P0.04 (SMI_CS0)
P0.06 (SMI_DIN)
Note that the other SMI pins: SMI_CS1,2,3 (P0.12, P0.11, P0.10) are not affected.
To avoid excess power consumption, unused I/O ports must be tied to ground.
Table 5.
Pin n°
STR750F pin description
Input
Output
Main
function
(after
Pin Name
Alternate function
OD
PP
(1)
reset)
P1.12 /
ADC_IN13
ADC: Analog
input 13
1
2
B1
B2
1
2
B1
I/O
I/O
T
T
X
X
X
EIT12 O8
X
X
X
X
Port 1.12
Port 0.02
T
T
P0.02 /
C2 TIM2_OC1 /
ADC_IN0
TIM2: Output
ADC: Analog
input 0
X
X
EIT0
O8
O8
(2)
Compare 1
TIM0: Input
Capture / trigger
/ external clock 1
P0.01 / TIM0_TI1
/ MCO
Main Clock
Output
3
4
B3
C2
3
4
C1
I/O
I/O
T
T
X
X
X
X
X
X
Port 0.01
T
T
Port 0.00 /
Boot mode
selection
input 0
P0.00 /
C3 TIM0_OC1 /
BOOT0
X
O8
TIM0: Output Compare 1
TIM1: Input Capture / trigger /
external clock 2
5
6
C1
D2
P0.31 / TIM1_TI2 I/O
T
T
X
X
X
X
O2
O2
X
X
X
X
Port 0.31
Port 0.30
T
T
P0.30 /
I/O
TIM1: Output Compare 2
TIM1_OC2
15/71
Pin Description
STR750F
Table 5.
Pin n°
STR750F pin description (continued)
Input
Output
Main
function
(after
Pin Name
Alternate function
OD
PP
(1)
reset)
P0.29 / TIM1_TI1
/ ADC_IN8
TIM1: Input
Capture 1
ADC: Analog
input 8
7
8
D1
E1
5
6
D1
D2
I/O
I/O
T
T
X
X
X
O2
O2
X
X
X
X
Port 0.29
Port 0.28
T
T
P0.28 /
TIM1_OC1
X
TIM1: Output Compare 1
9
E5
E4
7
8
D3 TEST
D4 VSS_IO
P0.23 /
I
Reserved, must be tied to ground
Ground Voltage for digital I/Os
UART1: Ready
10
S
ADC analog input
6
11
12
E2
F5
UART1_RTS /
ADC_IN6
I/O
I/O
T
T
X
X
X
X
O2
O2
X
X
X
X
Port 0.23
To Send
output
T
T
(2)
P2.04 /
TIM2_OC1
TIM2: Output
Compare 1
Port 2.04
(2)
UART1: Ready
To Send
output
P2.03 /
UART1_RTS
13
14
15
F1
F4
E3
I/O
I/O
I/O
T
T
T
X
X
X
X
X
X
O2
O2
O2
X
X
X
X
X
X
Port 2.03
Port 2.02
Port 0.22
T
T
T
(2)
P2.02
P0.22 /
UART1_CTS /
ADC_IN5
UART1: Clear To ADC: Analog
Send input input 5
P0.21 /
UART1_TX
UART1: Transmit data output
(remappable to P0.15)
16
17
F2
9
E4
I/O
I/O
T
T
X
X
X
X
O2
O2
X
X
X
X
Port 0.21
Port 0.20
(2)
T
T
P0.20 /
UART1_RX
UART1: Receive data input
F3 10 E3
(2)
(remappable to P0.14)
JTAG mode
selection
input
18
G3 11 E2 P1.19 / JTMS
I/O
T
X
X
O2
X
X
Port 1.19
T
(4)
JTAG clock
input
19
20
21
G2 12 E1 P1.18 / JTCK
H3 13 F4 P1.17 / JTDO
I/O
I/O
I/O
T
T
T
X
X
X
X
X
X
O2
O8
O2
X
X
X
X
X
X
Port 1.18
Port 1.17
(4)
T
T
T
JTAG data
(4)
output
JTAG data
H2 14 F3 P1.16 / JTDI
G1 15 F2 NJTRST
Port 1.16
(3)
(4)
input
22
23
24
I
T
T
T
JTAG reset input
Port 2.01
T
T
T
G4
G5
P2.01
P2.00
I/O
I/O
X
X
X
X
O2
O2
X
X
X
X
Port 2.00
JTAG
return
clock
output
Port 0.13
UART0: Ready To Send output
P0.13 / RTCK /
UART0_RTS
25
26
H1 16 F1
I/O
I/O
T
T
X
X
X
O8
O4
X
X
X
X
T
T
(2)
(4)
UART0: Clear To ADC: Analog
Send input input 2
P0.12 /
UART0_CTS /
ADC_IN2 /
SMI_CS1
J2 17 G2
X
Port 0.12
Serial Memory Interface: chip select
output 1
16/71
STR750F
Pin Description
Table 5.
Pin n°
STR750F pin description (continued)
Input
Output
Main
function
(after
Pin Name
Alternate function
OD
PP
(1)
reset)
Port
0.11/Boot
mode
selection
input 1
P0.11 /
UART0_TX /
BOOT1 /
SMI_CS2
Serial Memory
Interface: chip
select output 2
UART0:Transmit
data output
27
28
J1 18 G1
I/O
I/O
T
T
X
X
X
X
O4
O2
X
X
X
X
T
T
P0.10 /
K1 19 H1 UART0_RX /
SMI_CS3
Serial Memory
Interface: chip
select output 3
UART0: Receive
Data input
EIT4
EIT3
Port 0.10
29
30
31
32
K2 20 H2 P0.09 / I2C_SDA I/O
T
T
T
T
X
X
X
X
X
X
X
X
O4
O4
O2
O2
X
X
X
X
X
X
X
X
Port 0.09
Port 0.08
Port 2.19
Port 2.18
I2C: Serial Data
I2C: Serial clock
T
T
T
T
K3 21 H3 P0.08 / I2C_SCL
I/O
I/O
I/O
H4
H5
P2.19
P2.18
P2.17 /
UART2_RTS
(2)
33
34
H6
I/O
I/O
T
T
X
X
X
X
O2
X
X
X
X
Port 2.17
Port 1.11
UART2: Ready To Send output
T
T
P1.11
UART0: Ready
ADC: Analog
To Send
J3 22 G3 /UART0_RTS
ADC_IN12
EIT11 O8
O2
input 12
(2)
output
P0.27 /
UART2_RTS /
ADC_IN7
UART2: Ready
To Send
ADC: Analog
input 7
35
J4
I/O
T
X
X
X
X
Port 0.27
T
(6)
output
P0.26 /
UART2_CTS
36
37
38
J6
J7
I/O
I/O
I/O
T
T
T
X
X
X
X
X
X
O2
O2
O2
X
X
X
X
X
X
Port 0.26
Port 0.25
Port 0.24
UART2: Clear To Send input
UART2: Transmit data output
T
T
T
P0.25 /
UART2_TX
(6)
(remappable to P0.13)
P0.24 /
UART2_RX
UART2: Receive data input
H7
(6)
(remappable to P0.12)
SSP1: Slave
select input
ADC: Analog
input 4
(remappable to
P0.19 / USB_CK /
J5 23 G4 SSP1_NSS /
ADC_IN4
(6)
P0.11)
39
I/O
T
X
X
EIT6
O2
X
X
Port 0.19
T
USB:
48 MHz Clock
input
P0.18 /
K4 24 H5
SSP1: Master out/slave in data
(remappable to P0.10)
40
41
42
I/O
I/O
I/O
T
T
X
X
X
X
O2
O2
X
X
X
X
Port 0.18
Port 0.17
(6)
T
T
SSP1_MOSI
SSP1: Master
in/slave out data ADC: Analog
P0.17 /
K5 25 H4 SSP1_MISO /
ADC_IN3
(remappable to
P0.09)
input 3
(6)
P0.16 /
K6 26 H6
SSP1: serial clock (remappable to
T
T
X
X
X
X
O2
O2
X
X
X
X
Port 0.16
Port 2.16
(6)
T
T
SSP1_SCLK
P0.08)
43
44
45
H9
P2.16
I/O
S
J9 27 G5 VDD_IO
Supply voltage for digital I/Os
Supply voltage for PLL
K9 28 G7 VDDA_PLL
S
17/71
Pin Description
STR750F
Table 5.
Pin n°
STR750F pin description (continued)
Input
Output
Main
function
(after
Pin Name
Alternate function
OD
PP
(1)
reset)
46
47
K8 29 H7 XT2
K7 30 H8 XT1
4 MHz main oscillator
48 J10 31 G6 VSS_IO
S
S
Ground voltage for digital I/Os
Ground voltage for PLL
Port 2.15
49 K10 32 G8 VSSA_PLL
50
51
J8
P2.15
P2.14
I/O
I/O
T
T
X
X
X
O2
O2
X
X
X
X
T
T
H8
X
Port 2.14
Stabilization for main voltage regulator. Requires
external capacitors of at least 10µF between
V18REG and VSS18. See Figure 4.
52
G8 33 F5 V18REG
S
To be connected to the 1.8V external power supply
when embedded regulators are not used,
53
54
F8 34 F6 VSS18
F9 35 F7 VSSBKP
S
S
Ground Voltage for the main voltage regulator
Stabilization for low power voltage regulator.
Ground Voltage for the low power voltage regulator.
Requires external capacitors of at least 1µF
between V18BKP and VSSBKP. See Figure 4.
To be connected to the 1.8V external power supply
when embedded regulators are not used,
55
G9 36 E7 V18BKP
S
56 H10 37 F8 XRTC1
57 G10 38 E8 XRTC2
X
X
X
X
32 kHz oscillator for Realtime Clock
58
59
E7 39 E5 NRSTOUT
E9 40 E6 NRSTIN
O
I
Reset output
Reset input
T
T
T
T
P1.15 /
D6
60
I
X
EIT15
X
Port 1.15
Wake-up from STANDBY input pin
WKP_STDBY
61
62
B8
D9
P2.13
P2.12
I/O
I/O
T
T
X
X
X
X
O2
O2
X
X
X
X
Port 2.13
Port 2.12
T
T
41 D8
63 F10
64 E10
65 D10
66 C10
P0.15 / CAN_TX
P0.14 / CAN_RX
USB_DN
I/O
I/O
I/O
I/O
T
T
X
X
X
X
O2
O2
X
X
X
X
Port 0.15
Port 0.14
CAN: Transmit data output
CAN: Receive data input
(5)
(5)
T
T
42 C8
EIT5
(5)
(5)
41 D8
USB: bidirectional data (data -)
USB: bidirectional data (data +)
(5)
(5)
42 C8
USB_DP
(5)
(5)
TIM2: Input Capture / trigger /
67
B9 43 B8 P1.03 / TIM2_TI2 I/O
P1.02 /
T
T
X
X
X
X
O2
O2
X
X
X
X
Port 1.03
Port 1.02
external clock 2 (remappable to
T
T
(6)
P0.07)
TIM2: Output compare 2
68 A10
I/O
(6)
TIM2_OC2
(remappable to P0.06)
69
70
D7 44 C6 VDD_IO
S
S
Supply Voltage for digital I/Os
D8 45 D6 VDDA_ADC
Supply Voltage for A/D converter
18/71
STR750F
Pin Description
Table 5.
Pin n°
STR750F pin description (continued)
Input
Output
Main
function
(after
Pin Name
Alternate function
OD
PP
(1)
reset)
71
C9
P2.11
P2.10
I/O
I/O
S
T
T
X
X
X
X
O2
O2
X
X
X
X
Port 2.11
Port 2.10
T
T
72 B10
73
74
75
C8 46 D7 VSSA_ADC
C7 47 C7 VSS_IO
E8 48 D5 VREG_DIS
Ground Voltage for A/D converter
Ground Voltage for digital I/Os
Voltage Regulator Disable input
Serial Memory
Port 0.07
Port 0.06
Port 0.05
Port 0.04
Port 1.10
S
I
T
T
T
T
P0.07 /
A9 49 A8 SMI_DOUT /
SSP0_MOSI
SSP0: Master out
Slave in data
76
77
78
79
80
I/O
I/O
I/O
I/O
I/O
X
X
X
X
X
X
X
X
X
X
EIT2
EIT1
O4
O4
O4
O4
X
X
X
X
X
X
X
X
X
X
Interface: data
output
Serial Memory
Interface: data
input
P0.06 / SMI_DIN
A8 50 A7
SSP0: Master in
Slave out data
T
T
T
T
T
T
T
T
/ SSP0_MISO
P0.05 /
A7 51 A6 SSP0_SCLK /
SMI_CK
Serial Memory
Interface: Serial
clock output
SSP0: Serial
clock
Serial Memory
Interface: chip
select output 0
P0.04 / SMI_CS0
B7 52 B6
SSP0: Slave
select input
/ SSP0_NSS
P1.10
C5 53 B7 PWM_EMERGE
NCY
EIT10 O2
PWM: Emergency input
81
82
83
84
85
86
B6 54 B5 P1.09 / PWM1
I/O
I/O
I/O
I/O
I/O
I/O
T
T
T
T
T
T
X
X
X
X
X
X
X
X
X
X
X
X
EIT9
O4
O2
O2
O2
O2
O2
X
X
X
X
X
X
X
X
X
X
X
X
Port 1.09
Port 2.09
Port 2.08
Port 2.07
Port 2.06
Port 2.05
PWM: PWM1 output
T
T
T
T
T
T
PWM: PWM1 complementary
C6
G7
G6
F7
F6
P2.09 / PWM1N
P2.08 / PWM2
P2.07 / PWM2N
P2.06 / PWM3
P2.05 / PWM3N
(2)
output
(2)
PWM: PWM2 output
PWM: PWM2 complementary
(2)
output
(2)
PWM: PWM3 output
PWM: PWM3 complementary
(2)
output
PWM: PWM1
ADC: analog
complementary
output
P1.08 / PWM1N /
ADC_IN11
87
88
89
90
91
A6 55 A5
I/O
I/O
I/O
I/O
I/O
T
T
T
T
T
X
X
X
X
X
X
X
X
X
X
O4
O4
O4
O4
O4
X
X
X
X
X
X
X
X
X
X
Port 1.08
Port 1.07
Port 1.06
Port 1.05
Port 1.04
T
T
T
T
T
input 11
(6)
(2)
B5 56 B4 P1.07 / PWM2
EIT8
EIT7
PWM: PWM2 output
PWM: PWM2
P1.06 / PWM2N /
A5 57 A4
ADC: analog
input 10
complementary
ADC_IN10
(2)
output
(2)
B4 58 B3 P1.05 / PWM3
PWM: PWM3 output
PWM: PWM3
P1.04 / PWM3N /
A4 59 A3
ADC: analog
input 9
complementary
ADC_IN9
(2)
output
P1.14 /
ADC_IN15
92
93
A3
I/O
I/O
T
T
X
X
X
X
O8
X
X
X
X
Port 1.14
Port 1.13
ADC: analog input 15
ADC: analog input 14
T
T
P1.13 /
ADC_IN14
A2
EIT13 O8
19/71
Pin Description
STR750F
Table 5.
Pin n°
STR750F pin description (continued)
Input
Output
Main
function
(after
Pin Name
Alternate function
OD
PP
(1)
reset)
TIM0: Input Capture / trigger /
external clock 2 (remappable to
P0.05)
94
95
D5
P1.01 / TIM0_TI2 I/O
T
T
X
X
X
O2
O2
X
X
X
X
Port 1.01
Port 1.00
T
T
(6)
P1.00 /
I/O
TIM0: Output compare 2
E6
X
(6)
TIM0_OC2
(remappable to P0.04)
Stabilization for main voltage regulator. Requires
external capacitors 33nF between V18 and VSS18.
See Figure 4.
96
C4 60 C4 V18
S
To be connected to the 1.8V external power supply
when embedded regulators are not used.
97
98
99
D4 61 C5 VSS18
D3 62 A2 VSS_IO
C3 63 B2 VDD_IO
S
S
S
Ground Voltage for the main voltage regulator.
Ground Voltage for digital I/Os
Supply Voltage for digital I/Os
TIM2: Input
Capture / trigger
/ external clock 1
P0.03 / TIM2_TI1
/ ADC_IN1
ADC: analog
input 1
100 A1 64 A1
I/O
T
X
X
O2
X
X
Port 0.03
T
1. None of the I/Os are True Open Drain: when configured as Open Drain, there is always a protection diode between the I/O
pin and VDD_IO.
2. In the 100-pin package, this Alternate Function is duplicated on two ports. You can configure one port to use this AF, the
other port is then free for general purpose I/O (GPIO), external interrupt/wake-up lines, or analog input (ADC_IN) where
these functions are listed in the table.
3. It is mandatory that the NJTRST pin is reset to ground during the power-up phase. It is recommended to connect this pin to
NRSTOUT pin (if available) or NRSTIN.
4. After reset, these pins are enabled as JTAG alternate function see (Port Reset State on page 15). To use these ports as
general purpose I/O (GPIO), the DBGOFF control bit in the GPIO_REMAP0R register must be set by software (in this case,
debugging these I/Os via JTAG is not possible).
5. There are two different TQFP and BGA 64-pin packages: in the first one, pins 41 and 42 are mapped to USB DN/DP while
for the second one, they are mapped to P0.15/CAN_TX and P0.14/RX.
6. For details on remapping these alternate functions, refer to the GPIO_REMAP0R register description.
20/71
STR750F
Pin Description
Figure 4.
Required external capacitors when regulators are used
33 nF
33 nF
97 96
V
V
V
V
18BKP
SSBKP
55
54
SS18
18
61
SS18
60
V
V
V
18BKP
1µF
36
35
V
18
1µF
SSBKP
LQFP100
V
LQFP64
SS18
53
52
V
SS18
10 µF
34
33
V
18REG
10 µF
V
18REG
V
DD_IO
27
V
DD_IO
44
1 µF
1 µF
33 nF
33 nF
C5
SS18
C4
18
V
V
D4 C4
V
18BKP
SSBKP
E7
V
V
V
V
18BKP
SSBKP
G9
SS18
18
1µF
1µF
F7
V
F9
LFBGA64
V
LFBGA100V
SS18
F6
F5
SS18
F8
10 µF
V
10 µF
18REG
V
18REG
G8
V
DD_IO
G5
V
DD_IO
1 µF
J9
1 µF
21/71
Pin Description
STR750F
2.1
Memory map
Figure 5.
Memory map
Addressable Memory Space
4 Gbytes
Peripheral Memory Space
32 Kbytes
0xFFFF FFFF
0xFFFF FFFF
APB TO ARM7
BRIDGE
32K
Reserved
EIC
1K
1K
1K
1K
1K
1K
1K
1K
1K
1K
1K
1K
1K
1K
1K
1K
1K
1K
1K
1K
1K
1K
1K
0xFFFF 8000
0xFFFF FC00
0xFFFF FBFF
0xFFFF F800
0xFFFF F7FF
7
EXTIT
0xFFFF F400
0xFFFF F3FF
RTC
FLASH Memory Space
128/256 Kbytes
0xE000 0000
0xDFFF FFFF
0xFFFF F000
0xFFFF EFFF
DMA
0xFFFF EC00
0xFFFF EBFF
0x2010 DFFF
0x2010 C000
Reserved
GPIO I/O Ports
SystemMemory
8K
0xFFFF E800
0xFFFF E7FF
6
0x2010 0017
0x2010 0000
Flash registers
24B
0xFFFF E400
0xFFFF E3FF
Reserved
UART2
0xFFFF E000
0xFFFF DFFF
0xC000 0000
0xBFFF FFFF
0xFFFF DC00
0xFFFF DBFF
UART1
0xFFFF D800
0xFFFF D7FF
5
UART0
0xFFFF D400
0xFFFF D3FF
0x200C 4000
Reserved
I2C
0x200C 3FFF
0x200C 2000
0x200C 1FFF
8K
8K
B1F1
0xA000 0000
0x9FFF FFFF
0xFFFF D000
0xFFFF CFFF
B1F0
0x200C 0000
0xFFFF CC00
0xFFFF CBFF
Reserved
CAN
0xFFFF C800
0xFFFF C7FF
0x9000 0013
0x9000 0000
SMI Registers
20B
4
0xFFFF C400
0xFFFF C3FF
0x83FF FFFF
Reserved
SSP1
SMI Ext. Memory
4 x 16M
0xFFFF C000
0xFFFF BFFF
0x8000 0000
0x7FFF FFFF
0xFFFF BC00
0xFFFF BBFF
SSP0
0xFFFF B800
0xFFFF B7FF
3
Reserved
WDG
0xFFFF B400
0xFFFF B3FF
0x6000 0047
CONF + MRCC
Internal SRAM
Internal Flash
1K
0x2003 FFFF
0xFFFF B000
0xFFFF AFFF
0x6000 0000
0x5FFF FFFF
Reserved
USB Registers
Reserved
USB RAM 256 x16-bit
Reserved
B0F7(2)
0xFFFF AC00
0xFFFF ABFF
64K
64K
0xFFFF A800
0xFFFF A7FF
0x2003 0000
0x2002 FFFF
2
0xFFFF A400
0xFFFF A3FF
0x4000 3FFF
0x4000 0000
0x3FFF FFFF
B0F6(2)
0xFFFF A200
1K
1K
16K
0xFFFF A000
0xFFFF 9FFF
0x2002 0000
0x2001 FFFF
0xFFFF 9C00
0xFFFF 9BFF
PWM
TIM2
TIM1
TIM0
1K
1K
1K
1K
1K
1K
1K
0xFFFF 9800
0xFFFF 97FF
1
64K
32K
B0F5
0xFFFF 9400
0xFFFF 93FF
0x2010 0017
0x2000 0000
0x1FFF FFFF
0x2001 0000
0x2000 FFFF
128K/256K+16K+32B
0xFFFF 9000
0xFFFF 8FFF
B0F4
0xFFFF 8C00
0xFFFF 8BFF
0x2000 8000
TB Timer
0x2000 7FFF
B0F3
8K
8K
8K
0xFFFF 8800
0xFFFF 87FF
0x2000 6000
0
0x2000 5FFF
B0F2
0x2000 4000
ADC
0x2000 3FFF
0xFFFF 8400
0xFFFF 83FF
B0F1
0x2000 2000
0x2000 1FFF
B0F0
Reserved
Boot Memory(1)
128K/256K
8K
0x2000 0000
0xFFFF 8000
0x0000 0000
(1) In internal Flash Boot Mode, internal FLASH is aliased at 0x0000 0000h
(2) Only available in STR750Fx2
Reserved
22/71
STR750F
Electrical parameters
3
Electrical parameters
3.1
Parameter conditions
Unless otherwise specified, all voltages are referred to V
.
SS
3.1.1
Minimum and maximum values
Unless otherwise specified the minimum and maximum values are guaranteed in the worst
conditions of ambient temperature, supply voltage and frequencies by tests in production on
100% of the devices with an ambient temperature at T =25° C and T =T max (given by the
A
A
A
selected temperature range).
Data based on product characterisation, design simulation and/or technology characteristics
are indicated in the table footnotes and are not tested in production. Based on
characterization, the minimum and maximum values refer to sample tests and represent the
mean value plus or minus three times the standard deviation (mean 3Σ).
3.1.2
3.1.3
Typical values
Unless otherwise specified, typical data are based on T =25° C, V
=3.3 V (for the
DD_IO
A
3.0 V≤V
≤3.6 V voltage range) and V =1.8 V. They are given only as design guidelines
DD_IO
and are not tested.
18
Typical ADC accuracy values are determined by characterization of a batch of samples from
a standard diffusion lot over the full temperature range, where 95% of the devices have an
error less than or equal to the value indicated (mean 2Σ).
Typical curves
Unless otherwise specified, all typical curves are given only as design guidelines and are
not tested.
23/71
Electrical parameters
STR750F
3.1.4
Loading capacitor
The loading conditions used for pin parameter measurement are shown in Figure 6.
Figure 6.
Pin loading conditions
STR7 PIN
C =50pF
L
3.1.5
Pin input voltage
The input voltage measurement on a pin of the device is described in Figure 7.
Figure 7. Pin input voltage
STR7 PIN
V
IN
24/71
STR750F
Electrical parameters
3.1.6
Power Supply Schemes
When mentioned, some electrical parameters can refer to a dedicated power scheme
among the four possibilities. The four different power schemes are described below.
Power supply scheme 1: Single external 3.3 V power source
Figure 8.
Power supply scheme 1
IN STANDBY MODE THIS BLOCK IS KEPT POWERED ON
V18_BKP
1µF
BACKUP
VSS_BKP
VREG_DIS
V18
NORMAL
MODE
VBACKUP
CIRCUITRY
OSC32K, RTC
WAKEUP LOGIC,
BACKUP REGISTERS)
LOW POWER
VOLTAGE
REGULATOR
VLPVREG ~1.4V
POWER
SWITCH
33nF
VSS18
V18REG
V18
10µF
VSS18
VDD_IO
KERNEL LOGIC
(CPU &
1µF
MAIN
VOLTAGE
REGULATOR
3.3V
VMVREG = 1.8V
VCORE
+/-0.3V
DIGITAL &
VSS_IO
MEMORIES)
VIO=3.3V
OUT
IN
I/O LOGIC
GP I/Os
VDD_PLL
VSS_PLL
3.3V
3.3V
PLL
VDD_ADC
ADC
VSS_ADC
ADCIN
25/71
Electrical parameters
STR750F
Power supply scheme 2: Dual external 1.8V and 3.3V supply
Figure 9.
Power supply scheme 2
V
18_BKP
VSS_BKP
DD_IO
BACKUP
V
V
BACKUP
CIRCUITRY
(OSC32K, RTC
OFF
LOW POWER
VOLTAGE
REGULATOR
WAKEUP LOGIC,
BACKUP REGISTERS)
VREG_DIS
V
LPVREG
V
18
V
18REG
POWER
SWITCH
1.8V
V
SS18
OFF
V
DD_IO
MAIN
VOLTAGE
REGULATOR
KERNEL
(CORE &
DIGITAL &
MEMORIES)
V
CORE
V
MVREG
3.3V
+/-0.3V
V
SS_IO
V
=3.3V
IO
OUT
IN
GP I/Os
I/O LOGIC
V
3.3V
3.3V
DD_PLL
V
PLL
SS_PLL
V
DD_ADC
ADC
V
SS_ADC
ADC
IN
NOTE : THE EXTERNAL 3.3 V POWER SUPPLY MUST ALWAYS BE KEPT ON
26/71
STR750F
Electrical parameters
Power supply scheme 3: Single external 5 V power source
Figure 10. Power supply scheme 3
IN STANDBY MODE THIS BLOCK IS KEPT POWERED ON
V
18_BKP
1µF
BACKUP
V
SS_BKP
NORMAL
MODE
V
CIRCUITRY
BACKUP
OSC32K, RTC
WAKEUP LOGIC,
BACKUP REGISTERS)
VREG_DIS
LOW POWER
VOLTAGE
V
~1.4V
LPVREG
REGULATOR
V
18
33nF
POWER
SWITCH
V
SS18
V
V
18
18REG
10µF
V
SS18
V
DD_IO
KERNEL LOGIC
(CPU &
1µF
V
MAIN
VOLTAGE
REGULATOR
5.0V
V
= 1.8V
V
MVREG
+/-0.5V
CORE
DIGITAL &
SS_IO
MEMORIES)
V
=5.0V
IO
OUT
IN
GP I/Os
I/O LOGIC
V
DD_PLL
5.0V
5.0V
PLL
V
SS_PLL
V
DD_ADC
SS_ADC
ADC
V
ADC
IN
27/71
Electrical parameters
STR750F
Power supply scheme 4: Dual external 1.8 V and 5.0 V supply
Figure 11. Power supply scheme 4
V
18_BKP
VSS_BKP
DD_IO
V
V
BACKUP
BACKUP
OFF
CIRCUITRY
(OSC32K, RTC
LOW POWER
VOLTAGE
REGULATOR
VREG_DIS
V
WAKEUP LOGIC,
BACKUP REGISTERS)
LPVREG
V
18
V
18REG
POWER
SWITCH
1.8V
V
SS18
OFF
V
DD_IO
KERNEL
(CORE &
DIGITAL &
MEMORIES)
MAIN
VOLTAGE
REGULATOR
V
CORE
V
MVREG
5.0V
+/-0.5V
V
SS_IO
V
=5.0V
IO
OUT
IN
GP I/Os
I/O LOGIC
V
5.0V
5.0V
DD_PLL
PLL
V
SS_PLL
V
DD_ADC
SS_ADC
ADC
V
ADC
IN
NOTE : THE EXTERNAL 5.0V POWER SUPPLY MUST ALWAYS BE KEPT ON
3.1.7
3.1.8
I/O characteristics versus the various power schemes (3.3V or 5.0V)
Unless otherwise mentioned, all the I/O characteristics are valid for both
●
V
V
=3.0 V to 3.6 V with bit EN33=1
=4.5 V to 5.5 V with bit EN33=0
DD_IO
DD_IO
●
When V
=3.0 V to 3.6 V, I/Os are not 5V tolerant.
DD_IO
Current Consumption Measurements
All the current consumption measurements mentioned below refer to Power scheme 1 and 2
as described in Figure 12 and Figure 13
28/71
STR750F
Electrical parameters
Figure 12. Power consumption measurements in power scheme 1 (regulators
enabled)
V
pins
DDA_ADC
ADC
load
V
pins
I
DDA_PLL
DDA_ADC
PLL
load
I
DDA_PLL
V
pins
DD_IO
I
DD
ballast
regulator
transistor
3.3V
internal
load
3.3V
Supply
I
33
V
pins (including V
)
18
18BKP
1.8V
internal
load
I
18
I
I
is measured, which corresponds to the total current consumption :
DD
DD
= I
+ I
+ I + I
DDA_PLL
DDA_ADC 33 18
Figure 13. Power consumption measurements in power scheme 2 (regulators
disabled)
V
pins
DDA_ADC
DDA_PLL
ADC
load
V
pins
I
DDA_ADC
PLL
load
I
DDA_PLL
V
pins
DD_IO
I
DD_v33
3.3V
internal
load
3.3V
Supply
I
I
33
V
pins (including V
)
18BKP
18
I
DD_v18
1.8V
Supply
1.8V
internal
load
18
I
and I
are measured which correspond to:
DD_v18
DD_v33
I
I
= I
+ I
+ I
DD_v33
DD_v18
DDA_PLL
18
DDA_ADC 33
= I
29/71
Electrical parameters
STR750F
Figure 14. Power consumption measurements in power scheme 3 (regulators
enabled)
V
pins
DDA_ADC
ADC
load
V
pins
I
DDA_PLL
DDA_ADC
PLL
load
I
DDA_PLL
V
pins
DD_IO
I
DD
ballast
regulator
transistor
5.0V
internal
load
5.0V
Supply
I
50
V
pins (including V
)
18
18BKP
1.8V
internal
load
I
18
I
I
is measured, which corresponds to the total current consumption :
DD
DD
= I
+ I
+ I + I
DDA_PLL
DDA_ADC 50 18
Figure 15. Power consumption measurements in power scheme 4 (regulators
disabled)
V
pins
DDA_ADC
DDA_PLL
ADC
load
V
pins
I
DDA_ADC
PLL
load
I
DDA_PLL
V
pins
DD_IO
I
DD_v50
5.0V
internal
load
5.0V
Supply
I
I
50
V
pins (including V
)
18BKP
18
I
DD_v18
1.8V
Supply
1.8V
internal
load
18
I
and I
= I
are measured which correspond to:
DD_v50
DD_v18
I
I
+ I
+ I
DDA_ADC 50
DD_v50 DDA_PLL
= I
DD_v18
18
30/71
STR750F
Electrical parameters
3.2
Absolute maximum ratings
Stresses above those listed as “absolute maximum ratings” may cause permanent damage
to the device. This is a stress rating only and functional operation of the device under these
conditions is not implied. Exposure to maximum rating conditions for extended periods may
affect device reliability.
3.2.1
Voltage characteristics
Table 6.
Symbol
Voltage characteristics
Ratings
Min
Max
Unit
(1)
VDD_x - VSS_X
Including VDDA_ADC and VDDA_PLL
-0.3
6.5
V
Digital 1.8 V Supply voltage on all V18
power pins (when 1.8 V is provided
externally)
V18 - VSS18
-0.3
2.0
VSS-0.3 to
VDD_IO+0.3
VSS-0.3 to
VDD_IO+0.3
VIN
|∆VDDx
|∆V18x
|VSSX - VSS
VESD(HBM)
Input voltage on any pin (2)
Variations between different 3.3 V or
5.0 V power pins
|
50
25
50
Variations between different 1.8 V power
pins(3)
|
mV
Variations between all the different
ground pins
|
Electro-static discharge voltage (Human see : Absolute see : Absolute
Body Model)
Maximum
Ratings
Maximum
Ratings
(Electrical
Sensitivity) on Sensitivity) on
page 51 page 51
(Electrical
Electro-static discharge voltage (Machine
Model)
VESD(MM)
1. All 3.3 V or 5.0 V power (VDD_IO, VDDA_ADC, VDDA_PLL) and ground (VSS_IO, VSSA_ADC, VDDA_ADC) pins
must always be connected to the external 3.3V or 5.0V supply. When powered by 3.3V, I/Os are not 5V
tolerant.
2. IINJ(PIN) must never be exceeded. This is implicitly insured if VIN maximum is respected. If VIN maximum
cannot be respected, the injection current must be limited externally to the IINJ(PIN) value. A positive
injection is induced by VIN>VDD while a negative injection is induced by VIN<VSS. For true open-drain pads,
there is no positive injection current, and the corresponding VIN maximum must always be respected
3. Only when using external 1.8 V power supply. All the power (V18, V18REG, V18BKP) and ground (VSS18
VSSBKP) pins must always be connected to the external 1.8 V supply.
,
31/71
Electrical parameters
STR750F
3.2.2
Current characteristics
Table 7.
Symbol
Current characteristics
Maximum
value
Ratings
Unit
(1)
IVDD_IO
Total current into VDD_IO power lines (source) (2)
Total current out of VSS ground lines (sink) (2)
Output current sunk by any I/O and control pin
Output current source by any I/Os and control pin
Injected current on NRSTIN pin
150
150
25
- 25
5
(1)
IVSS_IO
IIO
mA
(3) & (4)
IINJ(PIN)
Injected current on XT1 and XT2 pins
5
Injected current on any other pin (5)
5
(3)
ΣIINJ(PIN)
Total injected current (sum of all I/O and control pins) (5)
25
1. The user can use GPIOs to source or sink high current (up to 20 mA for O8 type High Sink I/Os). In this
case, the user must ensure that these absolute max. values are not exceeded (taking into account the
RUN power consumption) and must follow the rules described in Section 3.3.8: I/O port pin characteristics
on page 53.
2. All 3.3 V or 5.0 V power (VDD_IO, VDDA_ADC, VDDA_PLL) and ground (VSS_IO, VSSA_ADC, VDDA_ADC) pins
must always be connected to the external 3.3V or 5.0V supply.
3. IINJ(PIN) must never be exceeded. This is implicitly insured if VIN maximum is respected. If VIN maximum
cannot be respected, the injection current must be limited externally to the IINJ(PIN) value. A positive
injection is induced by VIN>VDD while a negative injection is induced by VIN<VSS
.
4. Negative injection disturbs the analog performance of the device. See note in Section 3.3.12: 10-bit ADC
characteristics on page 64.
5. When several inputs are submitted to a current injection, the maximum ΣIINJ(PIN) is the absolute sum of the
positive and negative injected currents (instantaneous values). These results are based on
characterization with ΣIINJ(PIN) maximum current injection on four I/O port pins of the device.
3.2.3
Thermal characteristics
Table 8.
Symbol
TSTG
Thermal characteristics
Ratings
Storage temperature range
Value
Unit
-65 to +150
°C
Maximum junction temperature (see Section 4.2: Thermal characteristics on
page 70)
TJ
32/71
STR750F
Electrical parameters
3.3
Operating conditions
3.3.1
General operating conditions
Subject to general operating conditions for V
, and T unless otherwise specified.
A
DD_IO
Table 9.
Symbol
General operating conditions
Parameter
Conditions
Min
Max
Unit
Accessing SRAM with 0 wait
states
0
64
Accessing Flash in burst mode,
TA≤85° C
0
60
56
32
Accessing Flash in burst mode
fHCLK
Internal AHB Clock frequency
Internal APB Clock frequency
MHz
TA>85° C
Accessing Flash with 0 wait
states
0
Accessing Flash in RWW mode
0
0
16
32
fPCLK
MHz
V
Standard Operating Voltage
Power Scheme 1 & 2
3.0
4.5
3.6
5.5
VDD_IO
Standard Operating Voltage
Power Scheme 3 & 4
Standard Operating Voltage
Power Scheme 2 & 4
V18
TA
1.65
1.95
6 Suffix Version
7 Suffix Version
-40
-40
85
°C
°C
Ambient temperature range
105
3.3.2
Operating conditions at power-up / power-down
Subject to general operating conditions for T .
A
Table 10. Operating conditions at power-up / power-down
Symbol
Parameter
Conditions
Min(1) Typ Max(1) Unit
20
20
µs/V
ms/V
µs/V
ms/V
tVDD_IO VDD_IO rise time rate
20
20
When 1.8 V power is supplied
externally
tV18
V18 rise time rate (1)
1. Data guaranteed by characterization, not tested in production.
33/71
Electrical parameters
STR750F
3.3.3
Embedded voltage regulators
Subject to general operating conditions for V
, and T
A
DD_IO
Table 11. Embedded voltage regulators
Symbol
VMVREG
Parameter
Conditions
Min
Typ
Max
Unit
V
MVREG power supply(1)
LPVREG power supply(2)
load <150 mA
load <10 mA
1.65 1.80
1.30 1.40
1.95
1.50
VLPVREG
V
VDD_IO rise
slope = 20 µs/V
80
35
µs
Voltage Regulators start-up
time (to reach 90% of final V18
value) at VDD_IO power-up(3)
(1)
tVREG_PWRUP
VDD_IO rise
slope = 20 ms/V
ms
1. VMVREG is observed on the V18, V18REG and V18BKP pins except in the following case:
- In STOP mode with MVREG OFF (LP_PARAM13 bit). See note 2.
- In STANDBY mode. See note 2.
2. In STANDBY mode, VLPVREG is observed on the V18BKP pin
In STOP mode, VLPVREG is observed on the V18, V18REG and V18BKP pins.
3. Once VDD_IO has reached 3.0 V, the RSM (Regulator Startup Monitor) generates an internal RESET
during this start-up time.
34/71
STR750F
Electrical parameters
3.3.4
Supply current characteristics
The current consumption is measured as described in Figure 12 on page 29 and Figure 13
on page 29.
Subject to general operating conditions for V
, and T
A
DD_IO
Maximum power consumption
For the measurements in Table 12 and Table 13, the MCU is placed under the following
conditions:
●
●
●
All I/O pins are configured in output push-pull 0
All peripherals are disabled except if explicitly mentioned.
Embedded Regulators are used to provide 1.8 V (except if explicitly mentioned).
Table 12. Maximum power consumption in RUN and WFI modes
Symbol
Parameter
Conditions(1)
Typ(2) Max (3) Unit
External Clock with PLL
multiplication, code running from
RAM, all peripherals enabled in the
MRCC_PLCKEN register: fHCLK=60
MHz, fPCLK=30 MHz
3.3V
and 5V
range
Supply current in
RUN mode
80
62
90
67
mA
mA
Single supply scheme see Figure 12
/ Figure 14
IDD
External Clock, code running from
RAM: fHCLK=60 MHz, fPCLK=30 MHz
3.3V
and 5V
range
Supply current in Single supply scheme see
WFI mode
Figure 12./ Figure 14
Parameter setting BURST=1,
WFI_FLASHEN=1
1. The conditions for these consumption measurements are described at the beginning of Section 3.3.4.
2. Typical data are based on TA=25°C, VDD_IO=3.3V or 5.0V and V18=1.8V unless otherwise specified.
3. Data based on product characterisation, tested in production at VDD_IO max and V18 max (1.95V in dual
supply mode or regulator output value in single supply mode) and TA max.
35/71
Electrical parameters
STR750F
Unit
Table 13. Maximum power consumption in STOP and STANDBY modes
Max(3)
TA
Symbol
Parameter
Conditions(1)
Typ(2)
TA
TA
25°C 85°C 105°C
LP_PARAM bits: ALL OFF(4)
3.3V
range
12
16
117
250
µA
µA
µA
Single supply scheme see Figure 12.
LP_PARAM bits: ALL OFF
IDD_V18
IDD_V33
5
<1
8
3
60
TBD
110
TBD
Supply
current in
STOP mode
Dual supply scheme see Figure 13.
LP_PARAM bits: ALL OFF(4)
5V
range
15
22
160
310
Single supply scheme see Figure 10
IDD
LP_PARAM bits: ALL OFF
IDD_V18
IDD_V50
5
3
8
5
60
TBD
110
TBD
Dual supply scheme see Figure 11
3.3 V
range
Supply
µA
10
15
20
25
25
30
28
33
current in
STANDBY
mode
RTC OFF
5V
range
1. The conditions for these consumption measurements are described at the beginning of Section 3.3.4.
2. Typical data are based on TA=25°C, VDD_IO=3.3V or 5.0V and V18=1.8V unless otherwise specified.
3. Data based on product characterisation, tested in production at VDD_IO max and V18 max (1.95V in dual supply mode or
regulator output value in single supply mode).
4. In this mode, the whole digital circuitry is powered internally by the LPVREG at approximately 1.4V, which significantly
reduces the leakage currents.
36/71
STR750F
Electrical parameters
Figure 16. Power consumption in STOP mode Figure 17. Power consumption in STOP mode
in Single supply scheme (3.3 V
range)
Single supply scheme (5 V range)
350
300
250
200
150
100
50
300
250
200
150
100
50
TYP (3.3V)
MAX (3.6V)
TYP (5.0V)
MAX (5.5V)
0
0
-40
25
45
55
75
95
105
-40
25
45
55
75
95
105
Temp (°C)
Temp (°C)
Figure 18. Power consumption in STANDBY
mode (3.3 V range)
Figure 19. Power consumption in STANDBY
mode (5 V range)
30
35
TYP (5.0V)
30
TYP (3.3V)
25
MAX (5.5V)
25
MAX (3.6V)
20
20
15
10
5
15
10
5
0
0
-40
25
105
-40
25
105
Temp (°C)
Temp (°C)
37/71
Electrical parameters
STR750F
Typical power consumption
The following measurement conditions apply to Table 14, Table 15 and Table 16.
In RUN mode:
●
Program is executed from Flash (except if especially mentioned). The program consists
of an infinite loop. When f > 32 MHz, burst mode is activated.
HCLK
●
●
●
A standard 4 MHz crystal source is used.
In all cases the PLL is used to multiply the frequency.
All measurements are done in the single supply scheme with internal regulators used
(see Figure 12)
In WFI Mode:
In WFI Mode the measurement conditions are similar to RUN mode (OSC4M and PLL
enabled). In addition, the Flash can be disabled depending on burst mode activation:
●
–
For AHB frequencies greater than 32 MHz, burst mode is activated and the Flash
is kept enabled by setting the WFI_FLASH_EN bit (this bit cannot be reset when
burst mode is activated).
–
For AHB frequencies less than or equal to 32 MHz, burst mode is deactivated,
WFI_FLASH_EN is reset and the LP_PARAM14 bit is set (Flash is disabled in WFI
mode).
In SLOW mode:
The same program as in RUN mode is executed from Flash. The CPU is clocked by the
●
FREEOSC, OSC4M, LPOSC or OSC32K. Only EXTIT peripheral is enabled in the
MRCC_PCLKEN register.
In SLOW-WFI mode:
●
In SLOW-WFI, the measurement conditions are similar to SLOW mode (CPU clocked
by a low frequency clock). In addition, the LP_PARAM14 bit is set (FLASH is OFF). The
WFI routine itself is executed from SRAM (it is not allowed to execute a WFI from the
internal FLASH)
In STOP mode:
Several measurements are given: in the single supply scheme with internal regulators
used (see Figure 12): and in the dual supply scheme (see Figure 13).
In STANDBY mode:
Three measurements are given:
●
●
–
The RTC is disabled, only the consumption of the LPVREG and RSM remain
(almost no leakage currents)
–
–
The RTC is running, clocked by a standard 32.768 kHz crystal.
The RTC is running, clocked by the internal Low Power RC oscillator (LPOSC)
●
STANDBY mode is only supported in the single supply scheme (see Figure 12)
38/71
STR750F
Electrical parameters
Subject to general operating conditions for V
, and T
A
DD_IO
Table 14. Single supply typical power consumption in Run, WFI, Slow and Slow-WFI modes
3.3V
5V
Symbol
Para meter
Conditions
Unit
typ(1) typ(2)
Clocked by OSC4M with PLL multiplication, all peripherals
enabled in the MRCC_PLCKEN register:
fHCLK=60 MHz, fPCLK=30 MHz
fHCLK=56 MHz, fPCLK=28 MHz
fHCLK=48 MHz, fPCLK=24 MHz
fHCLK=32 MHz, fPCLK=32 MHz
fHCLK=16 MHz, fPCLK=16 MHz
fHCLK=8 MHz, fPCLK=8 MHz
80
75
65
59
34
20
82
77
67
61
37
22
mA
Supply current in
RUN mode(4)
Clocked by OSC4M with PLL multiplication, only EXTIT
peripheral enabled in the MRCC_PLCKEN register:
fHCLK=60 MHz, fPCLK=30 MHz
65
60
54
42
22
16
67
62
55
44
24
18
fHCLK=56 MHz, fPCLK=28 MHz
fHCLK=48 MHz, fPCLK=24 MHz
fHCLK=32 MHz, fPCLK=32 MHz
fHCLK=16 MHz, fPCLK=16 MHz
mA
fHCLK=8 MHz, fPCLK=8 MHz
(3)
IDD
Clocked by OSC4M with PLL multiplication, only EXTIT
peripheral enabled in the MRCC_PLCKEN register:
fHCLK=60 MHz, fPCLK=30 MHz(5)
62
59
53
22
13
10
63
60
54
23
15
11
Supply current in fHCLK=56 MHz, fPCLK=28 MHz(5)
mA
WFI mode(4)
fHCLK=48 MHz, fPCLK=24 MHz(5)
fHCLK=32 MHz, fPCLK=32 MHz(6)
fHCLK=16 MHz, fPCLK= 16 MHz (6)
fHCLK= 8 MHz, fPCLK= 8 MHz(6)
Clocked by FREEOSC: fHCLK=fPCLK=~5 MHz,
Clocked by OSC4M: fHCLK=fPCLK=4 MHz
Clocked by LPOSC: fHCLK=fPCLK=~300 kHz
Clocked by OSC32K: fHCLK=fPCLK=32.768 kHz
9
8
3.65
3.5
10
9
3.9
4.2
Supply current in
SLOW mode(4)
mA
mA
(7)
Clocked by FREEOSC: fHCLK=fPCLK=~5 MHz
Clocked by OSC4M: fHCLK=fPCLK=4 MHz
Clocked by LPOSC: fHCLK=fPCLK=~300 kHz
Clocked by OSC32K: fHCLK=fPCLK=32.768 kHz
3.5
3.1
1.15 1.65
0.98 1.5
4.0
3.75
Supply current in
SLOW-WFI
mode(4) (7)
1. Typical data based on TA=25° C and VDD_IO=3.3V.
2. Typical data based on TA=25° C and VDD_IO=5.0V.
3. The conditions for these consumption measurements are described at the beginning of Section 3.3.4 on page 35.
4. Single supply scheme see Figure 14.
5. Parameter setting BURST=1, WFI_FLASHEN=1
6. Parameter setting BURST=0, WFI_FLASHEN=0
7. Parameter setting WFI_FLASHEN=0, OSC4MOFF=1
39/71
Electrical parameters
STR750F
Table 15. Dual supply supply typical power consumption in Run, WFI, Slow and
Slow-WFI modes
To calculate the power consumption in Dual supply mode, refer to the values given in Table 14. and
consider that this consumption is split as follows:
IDD(single supply)~IDD(dual supply)= IDD_V18 + IDD(VDD_IO)
For 3.3V range: IDD(VDD_IO) ~ 1 to 2 mA
For 5V range: IDD(VDD_IO) ~ 2 to 3 mA
Therefore most of the consumption is sunk on the V18 power supply
This formula does not apply in STOP and STANDBY modes, refer to Table 16.
Subject to general operating conditions for V
, and T
A
DD_IO
Table 16. Typical power consumption in STOP and STANDBY modes
3.3V
5V
Symbol
Parameter
Conditions
LP_PARAM bits: ALL OFF(5)
Unit
Typ(1)
Typ(2)
12
15
LP_PARAM bits : MVREG ON, OSC4M OFF, FLASH
OFF(6)
130
135
Supply current
in STOP
LP_PARAM bits: MVREG ON, OSC4M ON , FLASH
OFF(6)
µA
1950
1930
mode(4)
LP_PARAM bits: MVREG ON, OSC4M OFF, FLASH ON (6)
LP_PARAM bits: MVREG ON, OSC4M ON, FLASH ON (6)
630
635
2435
2425
IDD_V18
LPPARAM bits: ALL OFF, with V18=1.8 V
IDD_V33
5
<1
5
<1
(3)
IDD
IDD_V18
LP_PARAM bits: OSC4M ON, FLASH OFF
IDD_V33
410
1475
410
1435
Supply current
in STOP
µA
µA
mode(7)
IDD_V18
LP_PARAM bits: OSC4M OFF, FLASH ON
IDD_V33
550
<1
550
1
IDD_V18
LP_PARAM bits: OSC4M ON, FLASH ON
IDD_V33
910
1475
910
1445
Supply current
in STANDBY
mode(4)
RTC OFF
11
14
14
18
RTC ON clocked by OSC32K
1. Typical data are based on TA=25°C, VDD_IO=3.3 V and V18=1.8 V unless otherwise indicated in the table.
2. Typical data are based on TA=25°C, VDD_IO=5.0 V and V18=1.8 V unless otherwise indicated in the table.
3. The conditions for these consumption measurements are described at the beginning of Section 3.3.4 on page 35.
4. Single supply scheme see Figure 12.
5. In this mode, the whole digital circuitry is powered internally by the LPVREG at approximately 1.4 V, which significantly
reduces the leakage currents.
6. In this mode, the whole digital circuitry is powered internally by the MVREG at 1.8 V.
7. Dual supply scheme see Figure 13.
40/71
STR750F
Electrical parameters
Supply and Clock manager power consumption
Table 17. Supply and Clock manager power consumption
3.3V
Typ
5V
Typ
Symbol
Parameter
Conditions(1)
Unit
External components specified in:
4/8 MHz Crystal / Ceramic
Resonator Oscillator (XT1/XT2) on
page 45
Supply current of resonator oscillator
IDD(OSC4M) in STOP or WFI mode (LP_PARAM
bit: OSC4M ON)
1815
515
1795
515
FLASH static current consumption in
IDD(FLASH) STOP or WFI mode (LP_PARAM bit
FLASH ON)
Main Voltage Regulator static current
IDD(MVREG) consumption in STOP mode
(LP_PARAM bit: MVREG ON)
µA
130
12
135
15
STOP mode includes leakage
where V18 is internally set to 1.4 V
Low Power Voltage Regulator + RSM
IDD(LPVREG)
STANDBY mode where
V18BKP and V18 are internally set to
1.4 V and 0 V respectively
current static current consumption
11
14
1. Measurements performed in 3.3V single supply mode see Figure 12
41/71
Electrical parameters
STR750F
On-Chip peripheral power consumption
Conditions:
–
–
–
V
=V
=V
=3.3 V or 5 V 10% unless otherwise specified.
DDA_PLL
DD_IO
DDA_ADC
T = 25° C
A
Clocked by OSC4M with PLL multiplication, f
=64 MHz, f
=32 MHz,
HCLK
CK_SYS
f
=32 MHz
PCLK
.
Table 18. On-Chip peripherals
Symbol
Typ
Parameter
Unit
(3.3V and 5.0V)
IDD(TIM)
IDD(PWM)
IDD(SSP)
IDD(UART)
IDD(I2C)
TIM Timer supply current (1)
0.7
1
PWM Timer supply current(2)
SSP supply current (3)
1.3
1.6
0.3
1.2
UART supply current (4)
I2C supply current (5)
mA
IDD(ADC)
ADC supply current when converting (6)
USB supply current (7)
IDD(USB)
IDD(CAN)
0.90
2.8
Note: VDD_IO must be 3.3 V 10%
CAN supply current (8)
1. Data based on a differential IDD measurement between reset configuration and timer counter running at 32
MHz. No IC/OC programmed (no I/O pads toggling)
2. Data based on a differential IDD measurement between reset configuration and PWM running at 32 MHz.
This measurement does not include PWM pads toggling consumption.
3. Data based on a differential IDD measurement between reset configuration and permanent SPI master
communication at maximum speed 16 MHz. The data sent is 55h. This measurement does not include the
pad toggling consumption.
4. Data based on a differential IDD measurement between reset configuration and a permanent UART data
transmit sequence at 1Mbauds. This measurement does not include the pad toggling consumption.
5. Data based on a differential IDD measurement between reset configuration (I2C disabled) and a permanent
I2C master communication at 100kHz (data sent equal to 55h). This measurement includes the pad
toggling consumption but not the external 10kOhm external pull-up on clock and data lines.
6. Data based on a differential IDD measurement between reset configuration and continuous A/D
conversions at 8 MHz in scan mode on 16 inputs configured as AIN.
7. Data based on a differential IDD measurement between reset configuration and a running generic HID
application.
8. Data based on a differential IDD measurement between reset configuration (CAN disabled) and a
permanent CAN data transmit sequence in loopback mode at 1MHz. This measurement does not include
the pad toggling consumption.
42/71
STR750F
Electrical parameters
3.3.5
Clock and timing characteristics
XT1 external Clock source
Subject to general operating conditions for V
, and T .
A
DD_IO
Table 19. XT1 external Clock source
Symbol
Parameter
Conditions(1) (2)
Min
Typ
Max
Unit
External clock source
frequency
fXT1
4
60
MHz
XT1 input pin high level
voltage
VXT1H
VXT1L
tw(XT1H)
0.7xVDD_IO
VDD_IO
V
XT1 input pin low level
voltage
see Figure 20
VSS
6
0.3xVDD_IO
XT1 high or low time (3)
XT1 rise or fall time (3)
XTx Input leakage current
tw(XT1L)
ns
tr(XT1)
tf(XT1)
5
1
VSS ≤±VIN ≤±
VDD_IO
IL
µA
1. Data based on typical application software.
2. Time measured between interrupt event and interrupt vector fetch. ∆tc(INST) is the number of tCPU cycles
needed to finish the current instruction execution.
3. Data based on design simulation and/or technology characteristics, not tested in production.
43/71
Electrical parameters
STR750F
XRTC1 external Clock source
Subject to general operating conditions for V
, and T .
DD_IO
A
Table 20. XRTC1 external Clock source
Symbol
Parameter
Conditions(1)
Min
Typ
Max
Unit
External clock source
frequency
fXRTC1
32.768
500
kHz
XRTC1 input pin high
level voltage
VXRTC1H
VXRTC1L
tw(XRTC1H)
0.7xVDD_IO
VDD_IO
V
XRTC1 input pin low level
voltage
see Figure 20
VSS
990
0.3xVDD_IO
XRTC1 high or low time(2)
XRTC1 rise or fall time(2)
tw(XRTC1L)
ns
tr(XRTC1)
tf(XRTC1)
5
1
XRTCx Input leakage
current
VSS≤VIN≤VDD_I
O
IL
µA
1. Data based on typical application software.
2. Data based on design simulation and/or technology characteristics, not tested in production.
Figure 20. Typical application with an external Clock source
90%
V
XT1H
10%
V
XT1L
t
t
w(XT1H)
t
t
w(XT1L)
f(XT1)
r(XT1)
T
XT1
XT2
XT1
f
OSC4M
hi-Z
EXTERNAL
CLOCK SOURCE
I
L
STR750
44/71
STR750F
Electrical parameters
4/8 MHz Crystal / Ceramic Resonator Oscillator (XT1/XT2)
The STR750 system clock or the input of the PLL can be supplied by a OSC4M which is a 4
MHz clock generated from a 4 MHz or 8 MHz crystal or ceramic resonator. If using an 8 MHz
oscillator, software set the XTDIV bit to enable a divider by 2 and generate a 4 MHz OSC4M
clock. All the information given in this paragraph are based on product characterisation with
specified typical external components. In the application, the resonator and the load
capacitors have to be placed as close as possible to the oscillator pins in order to minimize
output distortion and start-up stabilization time. Refer to the crystal/ceramic resonator
manufacturer for more details (frequency, package, accuracy...).
(1)
Table 21. 4/8 MHz crystal / ceramic resonator oscillator (XT1/XT2)
Symbol
Parameter
Conditions
Min Typ Max Unit
4 MHz Crystal/Resonator Oscillator
connected on XT1/XT2 XTDIV=0
fOSC4M
Oscillator frequency
Feedback resistor
or
4
MHz
8 MHz Crystal/Resonator Oscillator
connected on XT1/XT2 XTDIV=1
RF
200 240 270
kΩ
Recommended load
(2)
CL1
CL2
capacitance versus equivalent
serial resistance of the crystal or
ceramic resonator (RS)(3)
RS=200Ω
60
pF
i2
XT2 driving current
VDD_IO=3.3 V or 5.0 V
425
1
µA
(4)
tSU(OSC4M)
Startup time at VDD_IO power-up
ms
1. Resonator characteristics given by the crystal/ceramic resonator manufacturer.
2. For CL1 and CL2 it is recommended to use high-quality ceramic capacitors in the 5-pF to 25-pF range (typ.) designed for
high-frequency applications and selected to match the requirements of the crystal or resonator. CL1 and CL2, are usually the
same size. The crystal manufacturer typically specifies a load capacitance which is the series combination of CL1 and CL2
PCB and MCU pin capacitance must be included when sizing CL1 and CL2 (10 pF can be used as a rough estimate of the
combined pin and board capacitance).
.
3. The relatively low value of the RF resistor offers a good protection against issues resulting from use in a humid
environment, due to the induced leakage and the bias condition change. However, it is recommended to take this point into
account if the MCU is used in tough humidity conditions.
4. tSU(OSC4M) is the typical start-up time measured from the moment VDD_IO is powered (with a quick VDD_IO ramp-up from 0
to 3.3V (<50µs) to a stabilized 4MHz oscillation is reached. This value is measured for a standard crystal resonator and it
can vary significantly with the crystal/ceramic resonator manufacturer.
Figure 21. Typical application with a 4 or 8 MHz crystal or ceramic resonator
XTDIV
WHEN RESONATOR WITH
INTEGRATED CAPACITORS
f
OSC4M
/2
C
L1
XT1
LINEAR
AMPLIFIER
FEEDBACK
LOOP
i
VDD/2
Ref
2
RESONATOR
XT2
R
F
C
L2
STR75X
45/71
Electrical parameters
STR750F
OSC32K crystal / ceramic resonator oscillator
The STR7 RTC clock can be supplied with a 32.768 kHz Crystal/Ceramic resonator
oscillator. All the information given in this paragraph are based on product characterisation
with specified typical external components. In the application, the resonator and the load
capacitors have to be placed as close as possible to the oscillator pins in order to minimize
output distortion and start-up stabilization time. Refer to the crystal/ceramic resonator
manufacturer for more details (frequency, package, accuracy...).
Table 22. OSC32K crystal / ceramic resonator oscillator
Symbol
fOSC32K
Parameter
Oscillator Frequency
Conditions
Min
Typ
Max Unit
32.768
310
kHz
V
DD_IO=3.3 V
270
370
kΩ
RF
Feedback resistor
VDD_IO=5.0 V
TBD TBD
TBD
Recommended load capacitance
CL1
CL2
versus equivalent serial resistance of
RS=TBD
TBD
TBD
250
pF
the crystal or ceramic resonator (RS)(1)
VDD_IO=3.3 V or 5.0 V
VIN=VSS
i2
XT2 driving current
startup time
160
µA
(2)
tSU(OSC32K)
VDD_IO is stabilized
2.5
s
1. The oscillator selection can be optimized in terms of supply current using an high quality resonator with small RS value.
Refer to crystal/ceramic resonator manufacturer for more details
2. tSU(OSC32K) is the start-up time measured from the moment it is enabled (by software) to a stabilized 32 kHz oscillation is
reached. This value is measured for a standard crystal resonator and it can vary significantly with the crystal/ceramic
resonator manufacturer
Figure 22. Typical application with a 32.768 kHz crystal or ceramic resonator
WHEN RESONATOR WITH
INTEGRATED CAPACITORS
FEEDBACK
LOOP
i
2
C
f
L1
XRTC1
XRTC2
OSC32K
32 kHz
RESONATOR
R
F
C
L2
STR750
PLL Characteristics
PLL Jitter Terminology
●
Self-referred single period jitter (period jitter)
Period Jitter is defined as the difference of the maximum period (T ) and minimum
max
period (T ) at the output of the PLL where T
is the maximum time difference
min
max
between 2 consecutive clock rising edges and T
between 2 consecutive clock rising edges.
is the minimum time difference
min
See Figure 23
●
Self-referred long term jitter (N period jitter)
Self-referred long term Jitter is defined as the difference of the maximum period (T
)
max
and minimum period (T ) at the output of the PLL where T
is the maximum time
min
max
46/71
STR750F
Electrical parameters
is the minimum time
difference between N+1 consecutive clock rising edges and T
difference between N+1 consecutive clock rising edges.
min
N should be kept sufficiently large to have a long term jitter (ex: thousands).
For N=1, this becomes the single period jitter.
See Figure 23
●
Cycle-to-cycle jitter (N period jitter)
This corresponds to the time variation between adjacent cycles over a random sample
of adjacent clock cycles pairs. Jitter(cycle-to-cycle) = Max(Tcycle n- Tcycle n-1) for n=1
to N.
See Figure 24
Figure 23. Self-referred jitter (single and long term)
---
n
n+1
n+N
IDEAL
CK_PLL
T
ACTUAL
CK_PLL
single period
jitter
long term
jitter
trigger point
Figure 24. Cycle-to-cycle jitter
n
n+1
n+2
---
n+N
IDEAL
CK_PLL
T
ACTUAL
CK_PLL
Tcycle 1
Tcycle 2
Tcycle N-1
47/71
Electrical parameters
STR750F
PLL characteristics
Subject to general operating conditions for V
, and T .
A
DD_IO
Table 23. PLL characteristics
Value
Symbol
Parameter
Test Conditions
Unit
Min
Typ
Max(1)
PLL input clock
4.0
MHz
%
fPLL_IN
PLL input clock duty cycle
PLL multiplier output clock
40
60
fPLL_OUT
fVCO
fPLL_INx 24
165
MHz
When PLL
operates (locked)
VCO frequency range
336
960
300
MHz
µs
tLOCK
PLL lock time
Single period jitter (+/-3Σ±peak fPLL_IN = 4 MHz(4)
(2)(3)
∆tJITTER1
∆tJITTER2
∆tJITTER3
+/-250
ps
to peak)
VDD_IO is stable
Long term jitter (+/-3Σ±peak to fPLL_IN = 4 MHz(4)
(2)(3)
(2)(3)
+/-2.5
ns
ps
peak)
VDD_IO is stable
Cycle to cycle jitter (+/-3Σ±peak fPLL_IN = 4 MHz(4)
to peak) VDD_IO is stable
+/-500
1. Data based on product characterisation, not tested in production.
2. Refer to jitter terminology in : PLL Characteristics on page 46 for details on how jitter is specified.
3. The jitter specification holds true only up to 50mV (peak-to-peak) noise on VDDA_PLL and V18 supplies.
Jitter will increase if the noise is more than 50mV. In addition, it assumes that the input clock has no jitter.
4. The PLL parameters (MX1, MX0, PRESC1, PRESC2) must respect the constraints described in: PLL
Characteristics on page 46.
Internal RC Oscillators (FREEOSC & LPOSC)
Subject to general operating conditions for V
, and T .
A
DD_IO
Table 24. Internal RC Oscillators (FREEOSC & LPOSC)
Symbol
fCK_FREEOSC FREEOSC Oscillator Frequency
fCK_LPOSC LPOSC Oscillator Frequency
Parameter
Conditions
Min
Typ
Max
Unit
3
5
8
MHz
kHz
150
300
500
48/71
STR750F
Electrical parameters
3.3.6
Memory characteristics
Flash memory
Subject to general operating conditions for V
otherwise specified.
and V , T = -40 to 105 °C unless
18 A
DD_IO
Table 25. Flash memory characteristics
Value
Unit
Typ
Symbol
Parameter
Test Conditions
Max(1)
tPW
Word Program
35
60
µs
µs
tPDW
Double Word Program
Bank 0 Program (256K)
Single Word programming of
a checker-board pattern
tPB0
tPB1
tES
2
4.9(2)
s
ms
s
Single Word programming of
a checker-board pattern
Bank 1 Program (16K)
Sector Erase (64K)
Sector Erase (8K)
125
224(2)
Not preprogrammed (all 1)
Preprogrammed (all 0)
2.94(2)
1.54
1.176 2.38(2)
Not preprogrammed (all 1)
Preprogrammed (all 0)
392
343
560(2)
532(2)
tES
tES
tES
ms
s
Not preprogrammed (all 1)
Preprogrammed (all 0)
8.0
6.6
13.7
11.2
Bank 0 Erase (256K)
Bank 1 Erase (16K)
Not preprogrammed (all 1)
Preprogrammed (all 0)
0.9
0.8
1.5
1.3
s
tRPD
tPSL
tESL
Recovery when disabled
Program Suspend Latency
Erase Suspend Latency
20
10
µs
µs
µs
300
1. Data based on characterisation not tested in production
2. 10K program/erase cycles.
Table 26. Flash memory endurance and data retention
Value
Typ
Symbol
Parameter
Conditions
Unit
Min(1)
Max
NEND_B0 Endurance (Bank 0 sectors)
NEND_B1 Endurance (Bank 1 sectors)
YRET Data Retention
kcycles
kcycles
Years
10
100
20
TA=85° C
Min time from Erase
Resume to next Erase
Suspend
tESR
Erase Suspend Rate
ms
20
1. Data based on characterisation not tested in production.
49/71
Electrical parameters
STR750F
3.3.7
EMC characteristics
Susceptibilitytests are performed on a sample basis during product characterization.
Functional EMS (Electro Magnetic Susceptibility)
Based on a simple running application on the product (toggling 2 LEDs through I/O ports),
the product is stressed by two electro magnetic events until a failure occurs (indicated by the
LEDs).
●
ESD: Electro-Static Discharge (positive and negative) is applied on all pins of the
device until a functional disturbance occurs. This test conforms with the IEC 1000-4-2
standard.
●
FTB: A Burst of Fast Transient voltage (positive and negative) is applied to V and
DD
V
through a 100pF capacitor, until a functional disturbance occurs. This test
SS
conforms with the IEC 1000-4-4 standard.
A device reset allows normal operations to be resumed. The test results are given in the
table below based on the EMS levels and classes defined in application note AN1709.
Designing hardened software to avoid noise problems
EMC characterization and optimization are performed at component level with a typical
application environment and simplified MCU software. It should be noted that good EMC
performance is highly dependent on the user application and the software in particular.
Therefore it is recommended that the user applies EMC software optimization and
prequalification tests in relation with the EMC level requested for his application.
Software recommendations:
The software flowchart must include the management of runaway conditions such as:
●
●
●
Corrupted program counter
Unexpected reset
Critical Data corruption (control registers...)
Prequalification trials:
Most of the common failures (unexpected reset and program counter corruption) can be
reproduced by manually forcing a low state on the RESET pin or the Oscillator pins for 1
second.
To complete these trials, ESD stress can be applied directly on the device, over the range of
specification values. When unexpected behaviour is detected, the software can be
hardened to prevent unrecoverable errors occurring (see application note AN1015).
Table 27. EMC characteristics
Level/
Class
Symbol
Parameter
Conditions
VDD_IO=3.3 V or 5 V,
TA=+25° C, fCK_SYS=32 MHz
conforms to IEC 1000-4-2
Voltage limits to be applied on any I/O pin to
induce a functional disturbance
VFESD
Class A
Fast transient voltage burst limits to be applied VDD_IO=3.3 V or 5 V,
VEFTB through 100pF on VDD and VSS pins to induce TA=+25° C, fCK_SYS=32 MHz
a functional disturbance conforms to IEC 1000-4-4
Class A
50/71
STR750F
Electrical parameters
Electro Magnetic Interference (EMI)
Based on a simple application running on the product (toggling 2 LEDs through the I/O
ports), the product is monitored in terms of emission. This emission test is in line with the
norm SAE J 1752/3 which specifies the board and the loading of each pin.
Table 28. EMI characteristics
Max vs. [fOSC4M/fHCLK
]
Symbo
l
Monitored
Frequency Band
Parameter
Conditions
Unit
4/32MHz
4/60MHz
Flash devices:
VDD_IO=3.3 V or 5 V,
TA=+25° C,
LQFP64 package
conforming to SAE J
1752/3
0.1 MHz to 30 MHz
30 MHz to 130 MHz
130 MHz to 1 GHz
22
31
19
26
26
23
dBµV
SEMI Peak level
SAE EMI Level
>4
>4
-
Absolute Maximum Ratings (Electrical Sensitivity)
Based on three different tests (ESD, LU and DLU) using specific measurement methods, the
product is stressed in order to determine its performance in terms of electrical sensitivity.
For more details, refer to the application note AN1181.
Electro-Static Discharge (ESD)
Electro-Static Discharges (a positive then a negative pulse separated by 1 second) are
applied to the pins of each sample according to each pin combination. The sample size
depends on the number of supply pins in the device (3 parts*(n+1) supply pin). Two models
can be simulated: Human Body Model and Machine Model. This test conforms to the
JESD22-A114A/A115A standard.
Table 29. Absolute maximum ratings
Maximum
Symbol
Ratings
Conditions
Unit
value(1)
Electro-static discharge voltage
(Human Body Model)
VESD(HBM)
VESD(MM)
VESD(CDM)
2000
Electro-static discharge voltage
(Machine Model)
TA=+25° C
200
750
V
Electro-static discharge voltage
(Charge Device Model)
1. Data based on product characterisation, not tested in production.
51/71
Electrical parameters
STR750F
Static and dynamic latch-up
●
LU: 3 complementary static tests are required on 10 parts to assess the latch-up
performance. A supply overvoltage (applied to each power supply pin) and a current
injection (applied to each input, output and configurable I/O pin) are performed on each
sample. This test conforms to the EIA/JESD 78 IC latch-up standard. For more details,
refer to the application note AN1181.
●
DLU: Electro-Static Discharges (one positive then one negative test) are applied to
each pin of 3 samples when the micro is running to assess the latch-up performance in
dynamic mode. Power supplies are set to the typical values, the oscillator is connected
as near as possible to the pins of the micro and the component is put in reset mode.
This test conforms to the IEC1000-4-2 and SAEJ1752/3 standards. For more details,
refer to the application note AN1181.
Table 30. Electrical sensitivities
Symbol
Parameter
Conditions
Class(1)
TA=+25° C
TA=+85° C
TA=+105° C
LU
Static latch-up class
Class A
VDD=±5.5 V, fOSC4M=4 MHz,
fCK_SYS=32 MHz, TA=+25° C
DLU
Dynamic latch-up class
Class A
1. Class description: A Class is an STMicroelectronics internal specification. All its limits are higher than the
JEDEC specifications, that means when a device belongs to Class A it exceeds the JEDEC standard. B
Class strictly covers all the JEDEC criteria (international standard).
52/71
STR750F
Electrical parameters
3.3.8
I/O port pin characteristics
General characteristics
Subject to general operating conditions for V
and T unless otherwise specified.
A
DD_IO
Table 31. General characteristics
I/O static characteristics
Conditions
Symbol
Parameter
Min Typ Max Unit
VIL
Input low level voltage
Input high level voltage
0.8
V
VIH
2
TTL ports
Schmitt trigger voltage
hysteresis(1)
Vhys
400
mV
mA
IINJ(PIN) Injected Current on any I/O pin
4
ΣIIN(2J)(PIN Total injected current (sum of all
25
I/O and control pins)
Input leakage current on robust
pins
See Section 3.3.12 on page 64
Ilkg
Input leakage current(3)
VSS≤VIN≤VDD_IO
1
µA
IS
Static current consumption(4)
Floating input mode
200
95
58
80
50
5
VDD_IO=3.3 V 50
200 kΩ
150 kΩ
180 kΩ
120 kΩ
pF
Weak pull-up equivalent
resistor(5)
RPU
VIN=VSS
VDD_IO=5 V
20
VDD_IO=3.3 V 30
Weak pull-down equivalent
resistor(5)
RPD
VIN=VDD_IO
VDD_IO=5 V
20
2
CIO
I/O pin capacitance
External interrupt/wake-up lines
pulse time(6)
TAP
tw(IT)in
B
1. Hysteresis voltage between Schmitt trigger switching levels.
2. When the current limitation is not possible, the VIN absolute maximum rating must be respected, otherwise
refer to IINJ(PIN) specification. A positive injection is induced by VIN>VDD_IO while a negative injection is
induced by VIN<VSS. Refer to Section 3.2 on page 31 for more details.
3. Leakage could be higher than max. if negative current is injected on adjacent pins.
4. Configuration not recommended, all unused pins must be kept at a fixed voltage: using the output mode of
the I/O for example or an external pull-up or pull-down resistor (see Figure 25). Data based on design
simulation and/or technology characteristics, not tested in production.
5. The RPU pull-up and RPD pull-down equivalent resistor are based on a resistive transistor.
6. To generate an external interrupt, a minimum pulse width has to be applied on an I/O port pin configured
as an external interrupt source.
53/71
Electrical parameters
Figure 25. Connecting unused I/O pins
STR750F
V
STR7XXX
DD
10kΩ
UNUSED I/O PORT
UNUSED I/O PORT
10kΩ
STR7XXX
Output driving current
The GP I/Os have different drive capabilities:
●
●
●
O2 outputs can sink or source up to +/-2 mA.
O4 outputs can sink or source up to +/-4 mA.
outputs can sink or source up to +/-8 mA or can sink +20 mA (with a relaxed V ).
OL
In the application, the user must limit the number of I/O pins which can drive current to
respect the absolute maximum rating specified in Section 3.2.2 :
●
The sum of the current sourced by all the I/Os on V
plus the maximum RUN
DD_IO,
consumption of the MCU sourced on V
can not exceed the absolute maximum
DD_IO,
rating IV
.
DD_IO
●
The sum of the current sunk by all the I/Os on V
plus the maximum RUN
SS_IO
consumption of the MCU sunk on V
can not exceed the absolute maximum rating
SS_IO
IV
.
SS_IO
Subject to general operating conditions for V
and T unless otherwise specified.
A
DD_IO
54/71
STR750F
Electrical parameters
Table 32. Output driving current
I/O Output Drive characteristics for
VDD_IO = 3.0 to 3.6 V and EN33 bit =1
or VDD_IO = 4.5 to 5.5 V and EN33 bit =0
I/O
Type
Symbol
Parameter
Conditions
Min
Max Unit
Output low level voltage for a standard
I/O pin when 8 pins are sunk at same IIO=+2 mA
time
(1)
VOL
0.4
O2
O4
Output high level voltage for an I/O pin
IIO=-2 mA
(2)
VOH
VDD_IO-0.8
when 4 pins are sourced at same time
Output low level voltage for a standard
I/O pin when 8 pins are sunk at same IIO=+4 mA
time
(1)
VOL
0.4
Output high level voltage for an I/O pin
IIO=-4 mA
(2)
VOH
VDD_IO-0.8
when 4 pins are sourced at same time
V
Output low level voltage for a standard
I/O pin when 8 pins are sunk at same IIO=+8 mA
time
0.4
(1)
VOL
IIO=+20 mA,
TA≤85°C
TA≥85°C
1.3
1.5
Output low level voltage for a high sink
I/O pin when 4 pins are sunk at same
time
O8
IIO=+8 mA
0.4
Output high level voltage for an I/O pin
IIO=-8 mA
(2)
VOH
VDD_IO-0.8
when 4 pins are sourced at same time
1. The IIO current sunk must always respect the absolute maximum rating specified in Section 3.2.2 and the
sum of IIO (I/O ports and control pins) must not exceed IVSS_IO
.
2. The IIO current sourced must always respect the absolute maximum rating specified in Section 3.2.2 and
the sum of IIO (I/O ports and control pins) must not exceed IVDD_IO
.
55/71
Electrical parameters
STR750F
Output speed
Subject to general operating conditions for V
and T unless otherwise specified.
A
DD_IO
Table 33. Output speed
I/O dynamic characteristics for
VDD_IO = 3.0 to 3.6V and EN33 bit =1
or VDD_IO = 4.5 to 5.5V and EN33 bit =0
I/O
Type
Symbol
Parameter
Conditions
CL=50 pF
Min Typ Max Unit
Fmax(IO)out Maximum Frequency(1)
10 MHz
Output high to low level fall
tf(IO)out
30
ns
30
O2
O4
O8
time(2)
CL=50 pF
Between 10% and 90%
Output low to high level rise
tr(IO)out
time(2)
Fmax(IO)out Maximum Frequency(1)
CL=50 pF
25 MHz
Output high to low level fall
tf(IO)out
12
ns
12
time(2)
CL=50 pF
Between 10% and 90%
Output low to high level rise
tr(IO)out
time(2)
Fmax(IO)out Maximum Frequency(1)
CL=50pF
40 MHz
Output high to low level fall
tf(IO)out
tr(IO)out
6
time(2)
CL=50 pF
Between 10% and 90%
ns
Output low to high level rise
6
time(2)
1. The maximum frequency is defined as described in Figure 26.
2. Data based on product characterisation, not tested in production.
Figure 26. I/O output speed definition
10%
90%
50%
50%
90%
10%
t
t
r(IO)out
r(IO)out
EXTERNAL
OUTPUT
ON 50pF
T
Maximum frequency is achieved if (t + t ) ≤ (2/3)T and if the duty cycle is (45-55%)
r
f
when loaded by 50pF
56/71
STR750F
Electrical parameters
NRSTIN and NRSTOUT pins
NRSTIN Pin Input Driver is TTL/LVTTL as for all GP I/Os. A permanent pull-up is present
which is the same as R (see : General characteristics on page 53)
PU
NRSTOUT Pin Output Driver is equivalent to the O2 type driver except that it works only as
an open-drain (the P-MOS is de-activated). A permanent pull-up is present which is the
same as R (see : General characteristics on page 53)
PU
Subject to general operating conditions for V
and T unless otherwise specified.
A
DD_IO
Table 34. NRSTIN and NRSTOUT pins
Symbol
Parameter
Conditions
Min Typ 1) Max Unit
NRSTIN Input low level
voltage(1)
VIL(NRSTIN)
0.8
V
NRSTIN Input high level
voltage(1)
VIH(NRSTIN)
Vhys(NRSTIN)
VOL(NRSTIN)
2
NRSTIN Schmitt trigger
voltage hysteresis(2)
400
mV
V
NRSTOUT Output low level
voltage(3)
IIO=+2 mA
0.4
VDD_IO=3.3 V 25
50
31
100 kΩ
100 kΩ
NRSTIN Weak pull-up
equivalent resistor(4)
RPU(NRSTIN)
VIN=VSS
VDD_IO=5 V
20
Generated reset pulse
tw(RSTL)out duration (visible at NRSTOUT Internal reset source
15
20
µs
pin)(5)
At VDD_IO power-up(5)
20
1
µs
µs
External reset pulse hold time
th(RSTL)in
at NRSTIN pin(6)
When VDD_IO is
established(5)
The time between two
spikes must be higher
than 1/2 of the spike
duration.
maximum negative spike
duration filtered at NRSTIN
pin(7)
tg(RSTL)in
150
ns
1. Data based on product characterisation, not tested in production.
2. Hysteresis voltage between Schmitt trigger switching levels.
3. The IIO current sunk must always respect the absolute maximum rating specified in Section 3.2.2 and the
sum of IIO (I/O ports and control pins) must not exceed IVSS
.
4. The RPU pull-up equivalent resistor are based on a resistive transistor
5. To guarantee the reset of the device, a minimum pulse of 15 µs has to be applied to the internal reset. At
V
DD_IO power-up, the built-in reset stretcher may not generate the 15 µs pulse duration while once VDD_IO
is established, an external reset pulse will be internally stretched up to 15 µs thanks to the reset pulse
stretcher.
6. The reset network (the resistor and two capacitors) protects the device against parasitic resets, especially
in noisy environments.
7. In fact the filter is made to ignore all incoming pulses with short duration:
- all negative spikes with a duration less than 150 ns are filtered
- all trains of negative spikes with a ratio of 1/2 are filtered. This means that all spikes with a maximum
duration of 150 ns with minimum interval between spikes of 75 ns are filtered.
Data guaranteed by design, not tested in production.
57/71
Electrical parameters
Figure 27. Recommended NRSTIN pin protection
STR750F
V
DD_IO
RPU
Filter
INTERNAL RESET
NRSTOUT
TO RESET
OTHER CHIPS
WATCHDOG RESET
SOFTWARE RESET
RSM RESET
PULSE
GENERATOR
V
DD_IO
STR7X
RPU
EXTERNAL
RESET
NRSTIN
Filter
CIRCUIT
0.01µF
1. The user must ensure that the level on the NRSTIN pin can go below the VIL(NRSTIN) max. level specified in
NRSTIN and NRSTOUT pins on page 57. Otherwise the reset will not be taken into account internally.
58/71
STR750F
Electrical parameters
3.3.9
TB and TIM timer characteristics
Subject to general operating conditions for V
, f
, and T unless otherwise
DD_IO CK_SYS A
specified.
Refer to Section 3.3.8: I/O port pin characteristics on page 53 for more details on the
input/output alternate function characteristics (output compare, input capture, external clock,
PWM output...).
Table 35. TB and TIM timers
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Input capture
pulse time
tw(ICAP)in
TIM0,1,2
TB
2
tCK_TIM
tCK_TIM
ns
fCK_TIM(MAX) = fCK_SYS
1
16.6(1)
1
fCK_TIM = fCK_SYS
60 MHz
=
Timer
tres(TIM) resolution
time(1)
fCK_TIM(MAX) = fCK_SYS
tCK_TIM
ns
TIM0,1,2
TIM0,1,2
fCK_TIM = fCK_SYS
60MHz
=
16.6(1)
0
Timer
external clock
frequency on
TI1 or TI2
fCK_TIM(MAX) = fCK_SYS
fCK_TIM/4
15
MHz
fEXT
fCK_TIM = fCK_SYS
60 MHz
=
0
MHz
Timer
resolution
ResTIM
16
bit
tCK_TIM
µs
1
65536
1092
65536
1092
16-bit
Counter clock
period when
TB
fCK_TIM = fCK_SYS
60 MHz
=
=
=
=
0.0166
1
tCOUNTER internal clock
is selected
tCK_TIM
µs
(16-bit
Prescaler)
TIM0,1,2
TB
fCK_TIM = fCK_SYS
60 MHz
0.0166
65536x65536 tCK_TIM
71.58
65536x65536 tCK_TIM
71.58
fCK_TIM = fCK_SYS
60 MHz
s
Maximum
tMAX_COUNT Possible
Count
TIM0,1,2
fCK_TIM = fCK_SYS
60 MHz
s
1. Take into account the frequency limitation due to the I/O speed capability when outputting the PWM to I/O
pin, described in : Output speed on page 56.
59/71
Electrical parameters
STR750F
Table 36. PWM Timer (PWM)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
fCK_TIM(MAX) = fCK_SYS
1
tCK_TIM
tres(PWM) PWM resolution time
ResPWM PWM resolution
fCK_TIM = fCK_SYS
60 MHz
=
16.6(1)
ns
16
bit
µV
µV
VDD_IO=3.3 V, Res=16-bits
VDD_IO=5.0 V, Res=16-bits
50(1)
76(1)
PWM/DAC output step
voltage
(1)
VOS
Timer clock period
1
65536 tCK_TIM
tCOUNTER when internal clock is
selected
fCK_TIM=60 MHz
0.0166
1087
µs
65536x
65536
tCK_TIM
Maximum Possible
tMAX_COUNT
Count
fCK_TIM = fCK_SYS
60 MHz
=
71.58
s
1. Take into account the frequency limitation due to the I/O speed capability when outputting the PWM to an
I/O pin, as described in : Output speed on page 56.
60/71
STR750F
Electrical parameters
3.3.10
Communication interface characteristics
I2C - Inter IC control interface
Subject to general operating conditions for V
,
, and T unless otherwise specified.
f
DD_IO
A
PCLK
2
2
The ST7 I C interface meets the requirements of the Standard I C communication protocol
described in the following table with the restriction mentioned below:
Restriction: The I/O pins which SDA and SCL are mapped to are not “True” Open-
Drain: when configured as open-drain, the PMOS connected between the I/O pin and
V
the
is disabled, but it is still present. Also, there is a protection diode between
DD_IO
2
I/O pin and V
. Consequently, when using this I C in a multi-master network, it is
DD_IO
2
not possible to power off the STR7x while some another I C master node remains
powered on: otherwise, the STR7x will be powered by the protection diode.
Refer to I/O port characteristics for more details on the input/output alternate function
characteristics (SDA and SCL).
Table 37. SDA and SCL characteristics
Standard mode
Fast mode I2C(1)
I2C
Symbol
Parameter
Unit
Min(2) Max(2)
Min(2)
Max(2)
tw(SCLL) SCL clock low time
tw(SCLH) SCL clock high time
4.7
4.0
1.3
0.6
µs
tsu(SDA)
th(SDA)
tr(SDA)
SDA setup time
250
0(3)
100
0(4)
SDA data hold time
900(3)
300
ns
SDA and SCL rise time
SDA and SCL fall time
1000 20+0.1Cb
tr(SCL)
tf(SDA)
tf(SCL)
300
20+0.1Cb
300
th(STA)
tsu(STA)
tsu(STO)
START condition hold time
4.0
4.7
4.0
4.7
0.6
0.6
0.6
1.3
µs
Repeated START condition setup time
STOP condition setup time
µs
µs
pF
tw(STO:STA) STOP to START condition time (bus free)
Cb Capacitive load for each bus line
400
400
1. fPCLK, must be at least 8 MHz to achieve max fast I2C speed (400 kHz).
Data based on standard I2C protocol requirement, not tested in production.
2.
3.
The maximum hold time of the START condition has only to be met if the interface does not stretch the low
period of SCL signal.
The device must internally provide a hold time of at least 300 ns for the SDA signal in order to bridge the
undefined region of the falling edge of SCL.
4.
61/71
Electrical parameters
Figure 28.
STR750F
2
Typical application with I C bus and timing diagram
V
V
DD
DD
4.7kΩ
4.7kΩ
100Ω
100Ω
SDA
SCL
2
I C BUS
STRT75X
REPEATED START
START
t
t
w(STO:STA)
su(STA)
START
SDA
t
t
r(SDA)
f(SDA)
STOP
t
t
h(SDA)
su(SDA)
SCL
t
t
t
t
t
su(STO)
t
h(STA)
w(SCKH)
w(SCKL)
r(SCK)
f(SCK)
Measurement points are done at CMOS levels: 0.3xVDD and 0.7xVDD
.
1.
62/71
STR750F
Electrical parameters
3.3.11
USB characteristics
The USB interface is USB-IF certified (Low Speed and High Speed).
Table 38. USB characteristics
USB DC Electrical Characteristics
Symbol
Parameter
Conditions
Input Levels
Min.(1)(2) Max.(1)(2) Unit
VDI
Differential Input Sensitivity
I(DP, DM)
0.2
Differential Common Mode
Range
VCM
Includes VDI range
0.8
1.3
2.5
2.0
V
V
Single Ended Receiver
Threshold
VSE
Output Levels
VOL
VOH
Static Output Level Low
Static Output Level High
RL of 1.5 kΩ to 3.6V(3)
0.3
3.6
(3)
RL of 15 kΩ to VSS
2.8
1. All the voltages are measured from the local ground potential.
2. It is important to be aware that the DP/DM pins are not 5 V tolerant. As a consequence, in case of a a
shortcut with Vbus (typ: 5.0V), the protection diodes of the DP/DM pins will be direct biased . This will not
damage the device if not more than 50 mA is sunk for longer than 24 hours but the reliability may be
affected.
RL is the load connected on the USB drivers
3.
Figure 29. USB: data signal rise and fall time
Differential
Data Lines
Crossover
points
VCRS
V
SS
t
t
r
f
Table 39.
Symbol
USB: Full speed electrical characteristics
Parameter
Conditions
Min
Max
Unit
Driver characteristics:
CL=50 pF
tr
tf
Rise time(1)
Fall Time1)
4
4
20
20
ns
ns
%
V
CL=50 pF
trfm
VCRS
Rise/ Fall Time matching
tr/tf
90
1.3
110
2.0
Output signal Crossover Voltage
Measured from 10% to 90% of the data signal. For more detailed informations, please refer to USB
Specification - Chapter 7 (version 2.0).
1.
63/71
Electrical parameters
STR750F
3.3.12
10-bit ADC characteristics
Subject to general operating conditions for V
specified.
, f
, and T unless otherwise
DDA_ADC PCLK
A
Table 40. 10-bit ADC characteristics
Symbol
Parameter
Conditions
Min
Typ(1)
Max
Unit
fADC
VAIN
ADC clock frequency
0.4
8
MHz
Conversion voltage range
VSSA_ADC
VDDA_ADC
V
RAIN External input impedance
kΩ
TBD(2)(3)(4)
External capacitor on analog
CAIN
input
pF
+400 µA injected
on any pin
1
1
µA
-400 µA injected
on any pin
except specific
µA
Ilkg
Induced input leakage current adjacent pins in
Table 41
-400µA injected
on specific
adjacent pins in
Table 41
40
µA
Internal sample and hold
capacitor
CADC
3.5
pF
f
f
CK_ADC=8 MHz
CK_ADC=8 MHz
725.25
5802
3.75
µs
1/fADC
µs
tCAL
Calibration Time
Total Conversion time
(including sampling time)
tCONV
30 (11 for sampling + 19 for
Successive Approximation)
1/fADC
mA
Sunk on
VDDA_ADC
IADC
3.7
1. Unless otherwise specified, typical data are based on TA=25°C. They are given only as design guidelines
and are not tested.
2. CPARASITIC represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus
the pad capacitance (3 pF). A high CPARASITIC value will downgrade conversion accuracy. To remedy this,
f
ADC should be reduced.
3. Depending on the input signal variation (fAIN), CAIN can be increased for stabilization time and reduced to
allow the use of a larger serial resistor (RAIN). It is valid for all fADC frequencies ≤ 8 MHz.
4. Calibration is needed once after each power-up.
64/71
STR750F
Electrical parameters
ADC Accuracy vs. Negative Injection Current
Injecting negative current on specific pins listed in Table 41 (generally adjacent to the analog
input pin being converted) should be avoided as this significantly reduces the accuracy of
the conversion being performed. It is recommended to add a Schottky diode (pin to ground)
to pins which may potentially inject negative current.
Table 41. List of adjacent pins
Analog input
Related adjacent pins
a
None
AIN1/P0.03
AIN2/P0.12
AIN3/P0.17
AIN4/P0.19
AIN5/P0.22
AIN6/P0.23
AIN7/P0.27
AIN8/P0.29
AIN9/P1.04
AIN10/P1.06
AIN11/P1.08
AIN12/P1.11
AIN13/P1.12
AIN14/P1.13
AIN15/P1.14
None
P0.11
P0.18 and P0.16
P0.24
None
P2.04
P1.11 and P0.26
P0.30 and P0.28
None
P1.05
P1.04 and P1.13
P2.17 and P0.27
None
P1.14 and P1.01
None
Figure 30. Typical application with ADC
V
DD
STR75XX
V
T
0.6V
R
2kΩ(max)
AIN
AINx
10-Bit A/D
Conversion
V
AIN
C
V
T
0.6V
AIN
I
C
ADC
3.2pF
L
1µA
Analog Power Supply and Reference Pins
The V
and V
pins are the analog power supply of the A/D converter cell.
SSA_ADC
DDA_ADC
Separation of the digital and analog power pins allow board designers to improve A/D
performance. Conversion accuracy can be impacted by voltage drops and noise in the event
of heavily loaded or badly decoupled power supply lines (see : General PCB Design
Guidelines on page 66).
65/71
Electrical parameters
STR750F
General PCB Design Guidelines
To obtain best results, some general design and layout rules should be followed when
designing the application PCB to shield the noise-sensitive, analog physical interface from
noise-generating CMOS logic signals.
●
Use separate digital and analog planes. The analog ground plane should be connected
to the digital ground plane via a single point on the PCB.
●
Filter power to the analog power planes. It is recommended to connect capacitors, with
good high frequency characteristics, between the power and ground lines, placing
0.1 µF and optionally, if needed 10 pF capacitors as close as possible to the STR7
power supply pins and a 1 to 10 µF capacitor close to the power source (see
Figure 31).
●
●
The analog and digital power supplies should be connected in a star network. Do not
use a resistor, as V
is used as a reference voltage by the A/D converter and
DDA_ADC
any resistance would cause a voltage drop and a loss of accuracy.
Properly place components and route the signal traces on the PCB to shield the analog
inputs. Analog signals paths should run over the analog ground plane and be as short
as possible. Isolate analog signals from digital signals that may switch while the analog
inputs are being sampled by the A/D converter. Do not toggle digital outputs near the
A/D input being converted.
Software Filtering of Spurious Conversion Results
For EMC performance reasons, it is recommended to filter A/D conversion outliers using
software filtering techniques.
Figure 31. Power supply filtering
STR75XX
1 to 10µF
0.1µF
V
V
SS
STR7
DIGITAL NOISE
FILTERING
DD_IO
V
DD
POWER
SUPPLY
SOURCE
V
V
0.1µF
DDA_ADC
SSA_ADC
(3.3V or 5.0V)
EXTERNAL
NOISE
FILTERING
66/71
STR750F
Electrical parameters
Table 42. ADC accuracy
ADC Accuracy with fCK_SYS = 20 MHz, fADC=8 MHz, RAIN < 10 kΩ
This assumes that the ADC is calibrated(1)
Symbol
Parameter
Conditions
Typ
Max
Unit
VDDA_ADC=3.3 V
VDDA_ADC=5.0 V
VDDA_ADC=3.3 V
VDDA_ADC=5.0 V
VDDA_ADC=3.3 V
1
1.2
1.2
0.5
0.5
-0.2
-0.2
0.9
0.9
0.8
0.8
|ET|
Total unadjusted error (2) (3)
1
0.15
0.15
-0.8
-0.8
0.7
0.7
0.6
0.6
|EO|
EG
Offset error(2) (3)
Gain Error (2) (3)
LSB
VDDA_ADC=5.0 V
VDDA_ADC=3.3 V
VDDA_ADC=5.0 V
VDDA_ADC=3.3 V
VDDA_ADC=5.0 V
|ED|
|EL|
Differential linearity error(2) (3)
Integral linearity error (2) (3)
1. Calibration is needed once after each power-up.
2. Refer to ADC Accuracy vs. Negative Injection Current on page 65
3. ADC Accuracy vs. MCO (Main Clock Output): the ADC accuracy can be significantly degraded when
activating the MCO on pin P0.01 while converting an analog channel (especially those which are close to
the MCO pin). To avoid this, when an ADC conversion is launched, it is strongly recommended to disable
the MCO.
Figure 32. ADC accuracy characteristics
Digital Result ADCDR
E
G
(1) Example of an actual transfer curve
(2) The ideal transfer curve
(3) End point correlation line
1023
1022
1021
V
– V
DDA
SSA
1LSB
= ----------------------------------------
IDEAL
1024
(2)
E =Total Unadjusted Error: maximum deviation
T
E
between the actual and the ideal transfer curves.
T
(3)
7
6
5
4
3
2
1
E
=Offset Error: deviation between the first actual
O
transition and the first ideal one.
=Gain Error: deviation between the last ideal
(1)
E
G
transition and the last actual one.
E
O
E
L
E =Differential Linearity Error: maximum deviation
D
between actual steps and the ideal one.
E =Integral Linearity Error: maximum deviation
L
E
between any actual transition and the end point
correlation line.
D
1 LSB
IDEAL
7
Vin
0
1
2
3
4
5
6
1021 1022 1023 1024
V
V
DDA
SSA
67/71
Package characteristics
STR750F
4
Package characteristics
4.1
Package mechanical data
Figure 33. 64-Pin Low Profile Quad Flat Package (10x10)
mm
inches
Dim.
Min Typ Max Min Typ Max
D
A
A
1.60
0.063
0.006
D1
A2
A1 0.05
0.15 0.002
A1
A2 1.35 1.40 1.45 0.053 0.055 0.057
b
c
0.17 0.22 0.27 0.007 0.009 0.011
0.09 0.20 0.004 0.008
b
e
D
12.00
10.00
12.00
10.00
0.50
0.472
0.394
0.472
0.394
0.020
3.5°
E1
E
D1
E
E1
e
θ
0°
3.5°
7°
0°
7°
c
L1
L
0.45 0.60 0.75 0.018 0.024 0.030
1.00 0.039
Number of Pins
64
θ
L1
L
N
Figure 34. 100-Pin Low Profile Flat Package (14x14)
mm
inches
A
D
Dim.
Min Typ Max Min Typ Max
D1
A2
A
1.60
0.063
0.006
A1
A1 0.05
0.15 0.002
A2 1.35 1.40 1.45 0.053 0.055 0.057
b
C
0.17 0.22 0.27 0.007 0.009 0.011
0.09 0.20 0.004 0.008
b
e
D
16.00
14.00
16.00
14.00
0.50
0.630
0.551
0.630
0.551
0.020
3.5°
D1
E
E1
E
E1
e
θ
0°
3.5°
7°
0°
7°
L
0.45 0.60 0.75 0.018 0.024 0.030
1.00 0.039
Number of Pins
100
c
L1
L
1
L
h
N
68/71
STR750F
Package characteristics
Figure 35. 64-Low Profile Fine Pitch Ball Grid Array Package
mm
inches
Dim.
Min Typ Max Min Typ Max
A
1.210
1.700 0.048
0.011
0.067
A1 0.270
A2
1.120
0.044
b
D
0.450 0.500 0.550 0.018 0.020 0.022
7.750 8.000 8.150 0.305 0.315 0.321
D1
E
5.600
7.750 8.000 8.150 0.305 0.315 0.321
5.600 0.220
0.220
E1
e
0.720 0.800 0.880 0.028 0.031 0.035
1.050 1.200 1.350 0.041 0.047 0.053
f
ddd
0.120
0.005
Number of Pins
N
64
Figure 36. 100-Low Profile Fine Pitch Ball Grid Array Package
mm
inches
Dim.
Min Typ Max Min Typ Max
A
1.700
0.80
0.067
0.031
A1 0.270
0.011
A2
A3
A4
1.085
0.30
0.043
0.012
b
D
0.45 0.50 0.55 0.018 0.020 0.022
9.85 10.00 10.15 0.388 0.394 0.40
D1
E
7.20
0.283
9.85 10.00 10.15 0.388 0.394 0.40
E1
e
7.20
0.80
1.40
0.283
0.031
0.055
F
ddd
eee
fff
0.12
0.15
0.08
0.005
0.006
0.003
Number of Balls
N
100
Figure 37. Recommended PCB design rules (0.80/0.75mm pitch BGA)
Dpad
Dsm
0.37 mm
0.52 mm typ. (depends on solder
mask registration tolerance
Solder paste 0.37 mm aperture diameter
– Non solder mask defined pads are recommended
– 4 to 6 mils screen print
Dpad
Dsm
69/71
Package characteristics
STR750F
4.2
Thermal characteristics
The average chip-junction temperature, T must never exceed 125° C.
J
The average chip-junction temperature, T , in degrees Celsius, may be calculated using the
J
following equation:
T = T + (P x Θ )(1)
J
A
D
JA
Where:
–
–
–
–
T is the Ambient Temperature in °C,
A
Θ
is the Package Junction-to-Ambient Thermal Resistance, in °±C/W,
JA
P is the sum of P
and P (P = P
+ P ),
INT I/O
D
INT
I/O
D
P
is the product of I and V , expressed in Watts. This is the Chip Internal
DD DD
INT
Power.
P represents the Power Dissipation on Input and Output Pins;
I/O
–
Most of the time for the applications P < P
and may be neglected. On the other hand,
INT
I/O
P
may be significant if the device is configured to drive continuously external modules
I/O
and/or memories.
An approximate relationship between P and T (if P is neglected) is given by:
D
J
I/O
P = K / (T + 273°C) (2)
D
J
Therefore (solving equations 1 and 2):
2
K = P x (T + 273°C) + Θ x P (3)
D
where:
–
A
JA
D
K is a constant for the particular part, which may be determined from equation (3)
by measuring P (at equilibrium) for a known T Using this value of K, the values
D
A.
of P and T may be obtained by solving equations (1) and (2) iteratively for any
D
J
value of T .
A
Table 43. Thermal characteristics
Symbol
Parameter
Value
Unit
Thermal Resistance Junction-Ambient
LQFP 100 - 14 x 14 mm / 0.5 mm pitch
ΘJA
46
°C/W
Thermal Resistance Junction-Ambient
LQFP 64 - 10 x 10 mm / 0.5 mm pitch
ΘJA
ΘJA
ΘJA
45
58
41
°C/W
°C/W
°C/W
Thermal Resistance Junction-Ambient
LFBGA 64 - 8 x 8 x 1.7mm
Thermal Resistance Junction-Ambient
LFBGA 100 - 10 x 10 x 1.7mm
70/71
STR750F
Order codes
5
Order codes
Table 44. Order codes
Flash Prog.
Memory
(Bank 0)
Kbytes
CAN
USB
Partnumber
Package
Temp. Range
Periph
Periph
STR750FV0T6
STR750FV1T6
STR750FV2T6
STR750FV2H6(1)
STR751FR0T6
STR751FR1T6
STR751FR2T6
STR751FR2H6(1)
STR752FR0T6
STR752FR1T6
STR752FR2T6
STR752FR2H6(1)
STR752FR0T7
STR752FR1T7
STR752FR2T7
STR752FR2H7(1)
STR755FR0T6
STR755FR1T6
STR755FR2T6
STR755FR2H6(1)
STR755FV0T6
STR755FV1T6
STR755FV2T6
STR755FV2H6(1)
64
128
256
256
64
LQFP100 14x14
LFBGA100 10x10
LQFP64 10x10
LFBGA64 8x8
LQFP64 10x10
LFBGA64 8x8
LQFP64 10x10
LFBGA64 8x8
LQFP64 10x10
LFBGA64 8x8
LQFP100 14x14
LFBGA100 10x10
Yes
Yes
-40 to +85°C
128
256
256
64
-
Yes
-40 to +85°C
-40 to +85°C
-40 to +105°C
128
256
256
64
Yes
Yes
-
-
128
256
256
64
128
256
256
64
-
-
-40 to +85°C
128
256
256
1. For other memory sizes, contact sales office.
71/71
Revision history
STR750F
6
Revision history
Table 45. Revision history
Date
Revision
Description of Changes
25-Sep-2006
30-Oct-2006
1
2
Initial release
Added power consumption data for 5V operation in Section 3
72/71
STR750F
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Resale of ST products with provisions different from the statements and/or technical features set forth in this document shall immediately void
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Information in this document supersedes and replaces all information previously supplied.
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71/71
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