STSPIN32F0252 [STMICROELECTRONICS]
Advanced 250 V three-phase BLDC controller with embedded STM32 MCU;
| 型号： | STSPIN32F0252 |
| 厂家： | 
ST |
| 描述： | Advanced 250 V three-phase BLDC controller with embedded STM32 MCU |
| 文件： | 总32页 (文件大小：1267K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
STSPIN32F0251, STSPIN32F0252
Datasheet
Advanced 250 V three-phase BLDC controller with embedded STM32 MCU
Features
•
Three-phase gate drivers
–
–
–
High voltage rail up to 250 V
dV/dt transient immunity ±50 V/ns
Gate driving voltage range from 9V to 20V
•
•
Driver current capability:
–
–
STSPIN32F0251/Q: 200/350 mA source/sink current
STSPIN32F0252/Q: 1/0.85 A source/sink current
32-bit ARM® Cortex®-M0 core:
TQFP 10x10 64L pitch 0.5
–
–
–
–
Up to 48 MHz clock frequency
4-kByte SRAM with HW parity
32-kByte Flash memory with option bytes
used for write/readout protection
•
•
•
21 general-purpose I/O ports (GPIO)
6 general-purpose timers
12-bit ADC converter (up to 10 channels)
•
•
•
•
•
•
•
•
•
•
I2C, USART and SPI interfaces
Matched propagation delay for all channels
Integrated bootstrap diodes
Comparator for fast over current protection
UVLO, Interlocking and deadtime functions
Smart shutdown (smartSD) function
Standby mode for low power consumption
On-chip debug support via SWD
Extended temperature range: -40 to +125 °C
Package:
Product status link
STSPIN32F0251
STSPIN32F0252
STSPIN32F0251Q
STSPIN32F0252Q
–
–
TQFP 10x10 64L pitch 0.5 Creepage 1.2 mm
QFN 10x10 72L pitch 0.5 Creepage 1.8 mm
Product label
Applications
•
•
•
•
•
•
Home and Industrial refrigerators compressors
Industrial drives, pumps, fans
Air conditioning compressors & fans
Corded power tools, garden tools
Home appliances
Industrial automation
Description
The STSPIN32F025x is a system in package providing an extremely integrated
solution suitable for driving three-phase applications.
DS13048 - Rev 4 - February 2021
www.st.com
For further information contact your local STMicroelectronics sales office.
STSPIN32F0251, STSPIN32F0252
It embeds an MCU (STM32F031x6x7) featuring an ARM® 32-bit Cortex®-M0 CPU
and a 250V triple half bridge gate driver, able to drive N-channel power MOSFETs or
IGBTs.
A comparator featuring advanced smartSD function is integrated in the device,
ensuring fast and effective protection against overload and overcurrent.
The high-voltage bootstrap diodes are also integrated, as well as anti cross-
conduction (interlocking), deadtime and UVLO protection on both the lower and
upper driving sections, which prevents the power switches from operating in low
efficiency or dangerous conditions. Matched delays between low and high-side
sections guarantee no cycle distortion.
The integrated MCU allows performing FOC, 6-step sensorless and other advanced
driving algorithm including the speed control loop.
It has WR and RD protection for embedded flash memory to prevent unwanted
writing and reading, and it can be put in standby mode to reduce the power
consumption.
The MCU provides 21 general-purpose I/O ports (GPIO) with 5 V tolerant capability,
one 12-bit analog-to-digital converter with up to 10 channels performing conversions
in a single-shot or scan modes, 6 synchronizable general-purpose timers and
supports an easy to use debugging serial interface (SWD).
All of the integrated features of STSPIN32F025x make design of the application PCB
easier, and result in reduced PCB area consumption, bill of material and overall
application cost.
DS13048 - Rev 4
page 2/32
STSPIN32F0251, STSPIN32F0252
Block diagram
1
Block diagram
Figure 1. STSPIN32F025x SiP block diagram
VCC
EN
UVLO
DETECTION
UVLO
D1
D2
D3
VCC
BOOT3
HVG3
OUT3
UV&
Level Shifter
Floating structure
VCC
+5V
+5V
HIN3
HIN2
BOOT2
HVG2
UV&
Level Shifter
Floating structure
VCC
OUT2
+5V
BOOT1
HVG1
HlN1
UV&
Level Shifter
+5V
+5V
+5V
LOGIC
PC13
PC14
PC15
PF0
PF1
NRST
VSSA
BYPASSREG1
PF7
PF6
PC13
Floating structure
OUT1
PC14
V
SHOOT
THROUGH
PREVENTION
CC
PA13
PA12
PA11
PA10
PA9
LIN3
LIN2
PC15
PF0
LVG3
DEADTIME
PF1
NRST
V
CC
VSSA
STM32F031
PA8
LVG2
LVG1
PB15
PB14
PB13
PB12
VDD18
VDDA
PA0
PA1
PA2
VDDA
LlN1
V
CC
PA0
PA1
PA2
PA3
PA3
FAULT
IOD
SMART
SD
OD
CIN
PGND
SGND
+5V
+
-
+
UVLO
V
REF
DS13048 - Rev 4
page 3/32
STSPIN32F0251, STSPIN32F0252
Pin description and connection diagram
2
Pin description and connection diagram
Figure 2. STSPIN32F025x pin connection (TQFP top view)
Figure 3. STSPIN32F025x pin connection (QFN top view)
DS13048 - Rev 4
page 4/32
STSPIN32F0251, STSPIN32F0252
Pin description and connection diagram
Table 1. Legend/abbreviations used in the pin description table
Name
Abbreviation
Unless otherwise specified in brackets below the pin name, the pin function during and after
reset is the same as the actual pin name
Pin name
AO
P
Gate Driver Analog Output
Gate Driver Supply\GND pin
Supply pin
Pin type
S
I
Input-only pin
I/O
FT
FTf
TTa
TC
B
Input / output pin
5 V-tolerant I/O
5 V-tolerant I/O, FM+ capable
3.3 V-tolerant I/O directly connected to ADC
Standard 3.3V I/O
I/O structure
Dedicated BOOT0 pin
Bidirectional reset pin with embedded weak pull-up
resistor
RST
Notes
Unless otherwise specified by a note, all I/Os are set as floating inputs during and after reset
Alternate Functions
Additional functions
Functions selected through GPIOx_AFR registers
Pin functions
Functions directly selected/enabled through peripheral
registers
Table 2. STSPIN32F025x MCU-Driver internal connections
MCU pad
PB12
Type
I/O - FT
controller pad
FAULT
Function
Gate Driver Fault output
PB13
PB14
PB15
PA8
PA9
PA10
PA11
-
I/O - FT
I/O - FT
I/O - FT
I/O - FT
I/O - FTf
I/O - FTf
I/O - FT
Power
LIN1
LIN2
LIN3
HIN1
HIN2
HIN3
EN
Gate Driver Low Side input driver 1
Gate Driver Low Side input driver 2
Gate Driver Low Side input driver 3
Gate Driver High Side input driver 1
Gate Driver High Side input driver 2
Gate Driver High Side input driver 3
Gate Driver shut down input
EPAD
Note:
Each unused GPIO inside the SiP should be configured in OUTPUT mode low level after startup by software
DS13048 - Rev 4
page 5/32
STSPIN32F0251, STSPIN32F0252
Pin description table
3
Pin description table
Table 3. Pin description
TQFP N.
QFN N.
Name
Type
Function
Pin must be left floating
-
1
RES6
PB8
Reserved
I/O - FTf
Supply
1
2
MCU PB8
2
3
VSS
MCU digital ground
MCU digital power supply
MCU PC13
3
4
VDD
PC13
PC14
PC15
PF0
Supply
4
5
I/O - TC
I/O - TC
I/O - TC
I/O - FT
I/O - FT
I/O - RST
Supply
5
6
MCU PC14
6
7
MCU PC15
7
8
MCU PF0
8
9
PF1
MCU PF1
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
NRST
VSSA
VDDA
PA0
MCU Reset pin
10
11
12
13
14
15
16
-
MCU analog ground
MCU analog power supply
MCU PA0
Supply
I/O - TTa
I/O - TTa
I/O - TTa
I/O - TTa
I/O - TTa
Reserved
I/O - TTa
I/O - TTa
I/O - TTa
I/O - TTa
I/O - TTa
Supply
PA1
MCU PA1
PA2
MCU PA2
PA3
MCU PA3
PA4
MCU PA4
RES7
PA5
Pin must be left floating
MCU PA5
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
PA6
MCU PA6
PA7
MCU PA7
PB0
MCU PB0
PB1
MCU PB1
VDD
VSS
MCU digital power supply
MCU digital ground
Open Drain comparator output
Comparator positive input
Driver signal ground
Driver power ground
Phase 1 low-side driver output
Phase 2 low-side driver output
Phase 3 low-side driver output
Pin must be left floating
Supply
OD
Analog OD Output
Analog Input
Power
CIN
SGND
PGND
LVG1(1)
LVG2(1)
LVG3(1)
RES4
Power
Analog Out
Analog Out
Analog Out
Reserved
Phase 1 high-side (floating) common
voltage
33
38
OUT1
Power
HVG1(1)
BOOT1
34
35
39
40
Analog Out
Power
Phase 1 high-side driver output
Phase 1 bootstrap supply voltage
DS13048 - Rev 4
page 6/32
STSPIN32F0251, STSPIN32F0252
Pin description table
TQFP N.
QFN N.
Name
Type
Function
Phase 2 high-side (floating) common
voltage
40
45
OUT2
Power
HVG2(1)
BOOT2
41
42
46
47
Analog Out
Power
Phase 2 high-side driver output
Phase 2 bootstrap supply voltage
Phase 3 high-side (floating) common
voltage
46
51
OUT3
Power
HVG3(1)
BOOT3
RES5
VCC
47
48
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
52
53
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
Analog Out
Power
Phase 3 high-side driver output
Phase 3 bootstrap supply voltage
Pin must be left floating
Driver low side and logic supply voltage
Pin must be left floating
Pin must be left floating
Pin must be left floating
MCU PA12
Reserved
Power
RES1
RES2
RES3
PA12
PA13
PA14
PA15
PB3
Reserved
Reserved
Reserved
I/O - FT
I/O - FT
I/O - FT
I/O - FT
I/O - FT
I/O - FT
I/O - FT
I/O - FTf
I/O - FTf
I - B
MCU PA13/SWDIO (System debug data)
MCU PA14/SWDCLK (System debug clock)
MCU PA15
MCU PB3
PB4
MCU PB4
PB5
MCU PB5
PB6
MCU PB6
PB7
MCU PB7
BOOT0
Boot memory selection
32, 36, 37,
38, 39, 43,
44, 45, 49
44
-
NC
Not Connected
Exposed pad, internally connected to
SGND
-
EPAD
Power
1. The circuit guarantees less than 1 V on the LVG and HVG pins (at I
= 10 mA), with VCC > 3 V. This allows omitting the
sink
“bleeder” resistor connected between the gate and the source of the external MOSFETs normally used to hold the pin low.
When the EN is set low, gate driver outputs are forced low and assure low impedance.
DS13048 - Rev 4
page 7/32
STSPIN32F0251, STSPIN32F0252
Electrical data
4
Electrical data
4.1
Absolute maximum ratings
(Each voltage referred to SGND unless otherwise specified)
Table 4. Absolute maximum ratings
Symbol
VCC
Parameter
Power supply voltage
Low-side driver ground
Test Condition
Min
Max
Unit
-0.3
21
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
VCC – 21
-21
VCC + 0.3
21
PGND
(1)
Low-side driver ground
Output voltage
PS
V
– 21
V
+ 0.3
BOOT
OUT
BOOT
HVG
LVG
CIN
BOOT
Bootstrap voltage
-0.3
V
270
V
– 0.3
+ 0.3
High side gate output voltage
Low side gate output voltage
Comparator input voltage
Open-drain voltage (OD, FAULT)
OUT
BOOT
V
– 0.3
VCC + 0.3
PGND
-0.3
-0.3
20
21
OD
Common mode transient
Immunity
dV
/dt
50
V/ns
OUT
MCU logic input voltage
Logic input voltage
TTa type2
FT, FTf type2
2
-0.3
-0.3
-25
4
V
V
I
IO
VDD + 4 (3)
25
V
MCU I/O output current
mA
IO
ΣI
MCU I/O total output current
MCU digital supply voltage
MCU analog supply voltage
Storage temperature
2
2
2
-80
-0.3
-0.3
-50
80
4
mA
V
IO
VDD
VDDA
4
V
T
150
°C
stg
T
Junction temperature
Total power dissipation
-40
150
4.5
°C
W
J
P
TOT
TQFP 10x10 64L
package
2(4)
ESD
Human Body Model
kV
QFN 10x10 72L
package
2
1.
V
= V
- V
PGND SGND
PS
2. For details see Table 15 and 16 in the STM32F031x6x7 datasheet www.st.com
3. Valid only if the internal pull-up/pull-down resistors are disabled. If the internal pull-up or pull-down resistor is enabled, the
maximum limit is 4 V.
4. Pins 33 to 48 have HBM ESD rating 1C conforming to ANSI/ESDA/JEDEC JS-001-2014.
DS13048 - Rev 4
page 8/32
STSPIN32F0251, STSPIN32F0252
Thermal data
4.2
Thermal data
Table 5. Thermal data
Symbol
Parameter
Value
Unit
Thermal resistance junction to ambient(1)
TQFP 10x10 64L package
27.6
R
th(JA)
°C/W
Thermal resistance junction to ambient (1)
QFN 10x10 72L package
22.4
1. JEDEC 2s2p PCB in still air.
4.3
Recommended operating conditions
Table 6. Recommended operating conditions
Symbol
Parameter
Power supply voltage
Low-side driver supply voltage
Low-side driver ground
Floating supply voltage
Comparator input voltage
DC Output voltage
Test Condition
Min
Typ
Max
20
Unit
(V
4
)
VCC
V
V
V
V
V
V
CCthON MAX
(1)
V
20
LS
(2)
V
-5
(V
0
5
PS
(3)
V
)
20
BOthON MAX
BO
V
15
CIN
-10(4)
V
OUT
230
Maximum switching frequency
F
800
3.6
3.6
kHz
V
SW
(5)
Standard MCU operating
voltage
VDD
3.0
3.3
MCU analog operating voltage
(ADC not used)
VDD
V
Must have a potential equal to
or higher than VDD
VDDA
MCU analog operating voltage
(ADC used)
VDD
-40
3.6
V
T
Operating junction temperature
125
°C
J
1.
2.
3.
V
LS
V
PS
V
BO
= VCC - V
PGND
= V
- V
SGND
PGND
= V
- V
OUT
BOOT
4. LVG off. VCC = 9 V. Logic is operational if V
> 5 V
BOOT
5. Actual maximum F
depends on power dissipation.
SW
DS13048 - Rev 4
page 9/32
STSPIN32F0251, STSPIN32F0252
Electrical characteristics
5
Electrical characteristics
(VCC=15 V; VDD=3.3 V; PGND = SGND; TJ = +25 °C, unless otherwise specified)
Table 7. Electrical characteristics
Symbol
Parameter
Test condition
Min
Typ
Max
Unit
Power supply and standby mode
VCC under-voltage
quiescent supply
current
VCC = 7 V;
I
430
950
744
µA
µA
QCCU
QCC
EN = 5 V; CIN = SGND
EN = 5 V;
VCC quiescent
supply current
I
CIN = SGND
LVG & HVG: OFF
1450
VCC UVLO turn-on
threshold
VCC
VCC
VCC
8
8.5
8
9
V
V
V
thON
thOFF
hys
VCC UVLO turn-off
threshold
7.5
0.4
8.5
0.6
VCC UVLO
threshold hysteresis
0.5
VDD = 3.6 V
VDD current
consumption
HSE bypass, PLL off
0.8
18.9
2.0
f
= 1 MHz
HCLK
(1)
I
mA
(Supply current
in Run mode,
code executing from
Flash memory)
DD
VDD = 3.6 V
HSI clock, PLL on
f
= 48 MHz
HCLK
VDD = 3.6 V
HSE bypass, PLL off
f
= 1 MHz
HCLK
VDDA current
consumption
(1)
I
µA
DDA
VDD = 3.6 V
HSI clock, PLL on
220
f
= 48 MHz
HCLK
VDD Power on reset
threshold
1.84(2)
1.80
V
V
V
Rising edge
1.92
1.88
40
2.00
V
V
POR
VDD Power down
reset threshold
1.96(2)
Falling edge
PDR
VDD PDR
hysteresis
mV
PDRhyst
High-side floating section supply3
VBO under-voltage
quiescent supply
current
VCC = VBO = 6.5 V;
I
I
25
62
µA
QBOU
EN = 5 V; CIN = SGND
VBO = 15 V
VBO quiescent
supply current
EN = 5 V; CIN = SGND
LVG OFF; HVG = ON
84
8
150
8.5
µA
V
QBO
VBO UVLO turn on
threshold
V
7.5
BOthON
DS13048 - Rev 4
page 10/32
STSPIN32F0251, STSPIN32F0252
Electrical characteristics
Symbol
Parameter
Test condition
Min
Typ
Max
Unit
VBO UVLO turn-off
threshold
V
V
I
7
7.5
8
V
BOthOff
VBO UVLO
threshold hysteresis
0.4
0.5
0.6
15
V
BOhys
High voltage
leakage current
BOOT = HVG = OUT = 620 V
µA
LK
LVG
ON
215
215
240
250
Bootstrap diode on
resistance
R
Dboot
TJ = 25 °C
Ω
LVG
OFF
Output driving buffers
Source peak current
TJ = 25 °C
160
130
200
1.0
300
350
mA
mA
A
STSPIN32F0251/Q
I
Full temperature range3
TJ = 25 °C
SO
0.88
0.72
1.33
1.48
STSPIN32F0252/Q
Sink peak current
STSPIN32F0251/Q
Full temperature range3
A
TJ = 25 °C
230
200
350
430
500
mA
mA
A
I
Full temperature range3
TJ = 25 °C
SI
0.71
0.51
0.85
1.02
1.15
STSPIN32F0252/Q
Full temperature range3
I = 10mA
A
Source R
DSon
TJ = 25 °C
24
20
5
35
46
56
Ω
Ω
Ω
Ω
STSPIN32F0251/Q
STSPIN32F0252/Q
R
Full temperature range3
TJ = 25 °C
DSonON
6.4
7.6
10.3
Full temperature range3
I = 10mA
4.2
Sink R
DSon
TJ = 25 °C
11
8
16
21
27
Ω
Ω
Ω
Ω
STSPIN32F0251/Q
STSPIN32F0252/Q
R
Full temperature range3
TJ = 25 °C
DSonOFF
5.5
4.5
6.7
8
Full temperature range3
11.2
Logic Inputs
0.3·VDD+
0.07
TTa type (4)
V
V
V
Low level logic
threshold voltage
V
il
0.475 ·VDD
–0.2
FT, FTf type (4)
TTa type (4)
0.45 ·VDDIOx
+ 0.398
High level logic
threshold voltage
V
ih
0.5 ·VDDIOx
+0.2
FT, FTf type (4)
V
TTa type (4)
200
100
mV
mV
Schmitt trigger
hysteresis
V
I
hyst
FT, FTf type (4)
Input leakage
current
TC, FT and FTf I/O TTa in digital
mode
± 0.1
µA
lkg
DS13048 - Rev 4
page 11/32
STSPIN32F0251, STSPIN32F0252
Electrical characteristics
Symbol
Parameter
Test condition
Min
Typ
Max
Unit
VSS ≤ VIN ≤ VDDIOx
TTa in digital mode
1
VDDIOx ≤ VIN ≤ VDDA
Input leakage
current
I
µA
TTa in analog mode
VSS ≤ VIN ≤ VDDA
lkg
± 0.1
10
FT and FTf I/O
VDDIOx ≤ VIN ≤ 5 V
SmartSD restart
threshold
V
V
3.5
4
4.3
SSDh
SmartSD unlatch
threshold
0.56
0.75
V
SSDl
Sense Comparator and FAULT
Internal voltage
reference
V
410
40
7
460
70
510
mV
mV
µA
REF
Comparator input
hysteresis
CIN
hyst
Comparator input
pull-down current
CIN
VCIN = 1 V
10
13
PD
OD internal current
source
I
2.5
19
5
7.5
36
µA
W
OD
R
I
OD On resistance
IOD = 16 mA
25
95
ON_OD
OD saturation
current
V
= 5 V
OD
mA
SAT_OD
OD floating voltage
level
OD connected only to an external
capacitance
V
4.4
11
4.8
16
50
8
5.2
21
V
FLOAT_OD
OL_OD
OD low level sink
current
I
V
= 400 mV
mA
Ω
OD
FAULT On
resistance
R
I
= 8 mA
100
12
ON_F
FAULT
FAULT low level sink
current
I
V
= 400mV
FAULT
4
mA
OL_F
OD
Rpu = 100 kΩ to 5 V;
Comparator
propagation delay
t
t
0 to 3.3 V voltage step on CIN
50% CIN to 90% OD
350
350
360
500
500
510
ns
ns
ns
0 to 3.3 V voltage step on CIN;
50% CIN to 90% FAULT
Comparator
triggering to FAULT
CIN-F
Comparator
triggering to
0 to 3.3 V voltage step on CIN
t
t
CINoff
high/low side driver 50% CIN to 90% LVG/HVG
propagation delay
Comparator input
filter time
200
4
300
7.7
400
ns
FCIN
CL = 1 nF; Rpu = 1 kΩ to 5 V;
SR
Slew rate
10.3
V/µs
90% to 10% OD
Driver dynamic characteristics
OUT = 0 V
BOOT = VCC
CL = 1 nF
High/Low-side driver
turn-on propagation
delay
t
45
85
120
ns
on
DS13048 - Rev 4
page 12/32
STSPIN32F0251, STSPIN32F0252
Electrical characteristics
Symbol
Parameter
Test condition
Min
Typ
Max
Unit
High/Low-side driver
turn-off propagation
delay
t
t
45
85
120
ns
off
Vin = 0 to 3.3 Vsee Figure 4
Enable to high/low
side driver
propagation delay
245
345
520
ns
ns
EN
Rise time
CL= 1 nF
CL= 1 nF
t
STSPIN32F0251/Q
STSPIN32F0252/Q
Fall time
120
19
r
f
t
STSPIN32F0251/Q
STSPIN32F0252/Q
50
17
ns
ns
Delay matching
high/low
MT
0
30
side turn-on/off
(6)
DT
Deadtime
CL= 1 nF
CL= 1 nF
200
300
0
400
50
ns
ns
Matching deadtime
(7)
MDT
1. The current consumption depends on the firmware loaded in the microcontroller. See STM32F031x6x7
datasheet.www.st.com
2. Data based on characterization results, not tested in production.
3. Values provided by characterization, not tested
4. Data based on design simulation only. Not tested in production.
5. Comparator is disabled when VCC is in UVLO condition.
6. MT = max. (|t (LVG) - t (LVG)|, |t (HVG) - t HVG)|, |t LVG) - t (HVG)|, |t (HVG) - t (LVG)|)
on
off
on
off(
off(
on
off
on
7. MDT = | DTLH - DTHL |, refer to Figure 4.
DS13048 - Rev 4
page 13/32
STSPIN32F0251, STSPIN32F0252
Electrical characteristics
Figure 4. Propagation delay timing definition
50%
50%
50%
LIN
t > DT
t > DT
50%
50%
HIN
tr
tf
90%
90%
LVG
10%
10%
ton
toff
tr
tf
90%
90%
HVG
10%
10%
ton
toff
EN
50%
50%
90%
10%
LVG/HVG
tEN
tEN
Figure 5. Deadtime timing definitions
t > DT
LIN
50%
50%
HIN
50%
50%
tr
tf
90%
90%
HVG
LVG
10%
10%
toff
tf
90%
10%
10%
toff
DTLH
DTHL
DS13048 - Rev 4
page 14/32
STSPIN32F0251, STSPIN32F0252
Electrical characteristics
Figure 6. Deadtime and interlocking waveforms definition
LIN
HIN
INTERLOCKING
INTERLOCKING
CONTROL SIGNAL EDGES
OVERLAPPED FOR
MORE THAN DEAD TIME:
INTERLOCKING
LVG
HVG
DTHL
DTLH
gate driver outputs OFF
gate driver outputs OFF
(HALF-BRIDGE TRI-STATE)
(HALF-BRIDGE TRI-STATE)
LIN
HIN
CONTROL SIGNAL EDGES
OVERLAPPED:
INTERLOCKING + DEAD TIME
LVG
HVG
HL
LH
gate driver outputs OFF
gate driver outputs OFF
(HALF-BRIDGE TRI-STATE)
(HALF-BRIDGE TRI-STATE)
LIN
HIN
CONTROL SIGNALS EDGES
SYNCHRONOUS (*):
DEAD TIME
LVG
HVG
DTLH
DTHL
gate driver outputs OFF
gate driver outputs OFF
(HALF-BRIDGE TRI-STATE)
(HALF-BRIDGE TRI-STATE)
LIN
HIN
LVG
CONTROL SIGNALS EDGES
NOT OVERLAPPED,
BUT INSIDE THE DEAD TIME:
DEAD TIME
DTLH
DTHL
HVG
gate driver outputs OFF
gate driver outputs OFF
(HALF-BRIDGE TRI-STATE)
(HALF-BRIDGE TRI-STATE)
LIN
HIN
CONTROL SIGNALS EDGES
NOT OVERLAPPED,
OUTSIDE THE DEAD TIME:
DIRECT DRIVING
LVG
HVG
DTLH
DTHL
gate driver outputs OFF
gate driver outputs OFF
(HALF-BRIDGE TRI-STATE)
(HALF-BRIDGE TRI-STATE)
DS13048 - Rev 4
page 15/32
STSPIN32F0251, STSPIN32F0252
Device description
6
Device description
The STSPIN32F025x is a system-in-package providing an integrated solution suitable for driving high-voltage
3-phase applications.
6.1
Gate driver
The STSPIN32F025x integrates a triple half-bridge gate driver able to drive N-channel power MOSFETs or IGBTs.
The high-side section is supplied by a bootstrapped voltage technique with integrated bootstrap diode.
All the inputs lines are connected to a pull-down resistor with typical value of 60 kΩ.
The high- and low-side outputs of same half-bridge cannot be simultaneously driven high thanks to an integrated
interlocking function.
6.1.1
Inputs and outputs
The device is controlled through the following logic inputs:
•
•
•
EN: enable input, active high;
LIN: low-side driver inputs, active low;
HIN: high-side driver inputs, active low.
Table 8. Inputs truth table (applicable when device is not in UVLO or SmartSD protection)
Input pins
Output pins
HVG
EN
L
LIN
X
HIN
X
LVG
Low
Low
HIGH
Low
Low
Low
H
H
H
Low
H
L
H
Low
H
H
L
HIGH
Low
Interlocking
H
L
L
Note:
X : Don’t care
The FAULT and OD pins are open-drain outputs. The FAULT signal is set low in case VCC UVLO is detected, or
in case the SmartShutDown comparator triggers an event. It is only used to signal a UVLO or SmartSD activation
to external circuits, and its state does not affect the behavior of other functions or circuits inside the driver. The
OD behavior is explained in Comparator and Smart shutdown.
6.1.2
Deadtime
The deadtime feature, in companion with the interlocking feature, guarantees that driver outputs of the same
channel are not high simultaneously and at least a DT time passes between the turn-off of one driver's output and
the turn-on of the companion output of the same channel. If a deadtime longer than the internal DT is applied
to LIN and HIN inputs by the external controller, the internal DT is ignored and the outputs follow the deadtime
determined by the inputs. Refer to Figure 1 for the deadtime and interlocking waveforms.
6.1.3
VCC UVLO protection
Undervoltage protection is available on VCC and BOOT supply pins. In order to avoid intermittent operation, a
hysteresis sets the turn-off threshold with respect to the turn-on threshold.
When VCC voltage goes below the VCCthOFF threshold all the outputs are switched off, both LVG and HVG. When
VCC voltage reaches the VCCthON threshold the driver returns to normal operation and sets the LVG outputs
according to actual input pins status; HVG is also set according to input pin status if the corresponding VBO
section is not in UVLO condition. The FAULT output is kept low when VCC is in UVLO condition. The following
figures show some examples of typical operation conditions.
DS13048 - Rev 4
page 16/32
STSPIN32F0251, STSPIN32F0252
Gate driver
Figure 7. VCC power ON and UVLO, LVG timing
VCCthON
VCCthOFF
VCC
0 V
FAULT
0 V
UVLO VCC
LIN
0 V
0 V
LVG
Figure 8. VCC power ON and UVLO, HVG timing
VCCthON
VCCthOFF
VCC
0 V
FAULT
HIN
0 V
UVLO VCC
0 V
V
BOthON
V
BOthOFF
VBO
0 V
HVG-OUT
6.1.4
V
UVLO protection
BO
Dedicated undervoltage protection is available on each bootstrap section between BOOTx and OUTx supply
pins. In order to avoid intermittent operation, a hysteresis sets the turn-off threshold with respect to the turn-on
threshold.
When VBO voltage goes below the VBOthOFF threshold, the HVG output of the corresponding bootstrap section is
switched off. When VBO voltage reaches the VBOthON threshold the device returns to normal operation and the
output remains off up to the next input pins transition that requests HVG to turn on.
DS13048 - Rev 4
page 17/32
STSPIN32F0251, STSPIN32F0252
Gate driver
Figure 9. VBO Power-ON and UVLO timing
VCCthON
VCCthOFF
VCC
0 V
0 V
FAULT
HIN
0 V
VBOthON
VBOthOFF
0 V
0 V
V
BO
HVG-OUT
6.1.5
Comparator and Smart shutdown
The STSPIN32F025x integrates a comparator committed to the fault protection function, thanks to the
SmartShutDown (SmartSD) circuit.
The SmartSD architecture allows immediate turn-off of the gate driver outputs in the case of overload or
overcurrent condition, by minimizing the propagation delay between the fault detection event and the actual
output switch-off. In fact, the time delay between the fault detection and the output turn-off is not dependent on the
value of the external components connected to the OD pin, which are only used to set the duration of disable time
after the fault.
This provides the possibility to increase the duration of the output disable time after the fault event up to very
large values without increasing the delay time of the protection. The duration of the disable time is determined by
the values of the external capacitor COD and of the optional pull-up resistor connected to the OD pin.
The comparator has an internal voltage reference VREF connected to the inverting input, while the non-inverting
input is available on the CIN pin. The comparator's CIN input can be connected to an external shunt resistor
in order to implement a fast and simple overcurrent protection function. The output signal of the comparator is
filtered from glitches shorter than tFCIN and then fed to the SmartSD logic.
If the impulse on the CIN pin is higher than VREF and wider than tFCIN, the SmartSD logic is triggered and
immediately sets all of the driver outputs to low-level (OFF).
At the same time, FAULT is forced low to signal the event (for example to a MCU input) and OD starts to
discharge the external COD capacitor used to set the duration of the output disable time of the fault event.
The FAULT pin is released and driver outputs restart following the input pins as soon as the output disable time
expires.
The overall disable time is composed of two phases:
•
The OD unlatch time (t1 in Figure 10), which is the time required to discharge the COD capacitor down to the
VSSDl threshold. The discharge starts as soon as the SSD comparator is triggered.
•
The OD Restart time (t2 in Figure 10), which is the time required to recharge the COD capacitor up to the
VSSDh threshold. The recharge of COD starts when the OD internal MOSFET is turned-off, which happens
when the fault condition has been removed (CIN < VREF - CINhyst) and the voltage on OD reaches the VSSDl
threshold. This time normally covers most of the overall output disable time.
If no external pull-up is connected to OD, the external COD capacitor is discharged with a time constant defined
by COD and the internal MOSFET's characteristic (Equation 1), and the Restart time is determined by the internal
current source IOD and by COD (Equation 2 ).
DS13048 - Rev 4
page 18/32
STSPIN32F0251, STSPIN32F0252
Gate driver
Equation 1
(1)
(2)
V
OD
t ≅ R
∙ C
∙ ln
OD
V
1
ON_OD
SSDꢀ
Equation 2
C
∙ V
SSDh
V
V
OD
SSDꢀ − OD
V
SSDh − OD
t ≅
∙ ln
2
I
V
OD
Where VOD = VFLOAT_OD In case the OD pin is connected to VCC by an external pull-up resistor ROD_ext, the
OD discharge time is determined by the external network ROD_ext COD and by the internal MOSFET's RON_OD
(Equation 3), while the Restart time is determined by current in ROD_ext (Equation 4)
Equation 3
(3)
(4)
V
V
OD − oꢁ
− V
t ≅ C
∙ R
//R
∙ ln
ON_OD
V
1
OD
OD_ext
SSDꢀ
oꢁ
Equation 4
V
V
SSDꢀ − OD
V
t ≅ C ∙ R
∙ ln
2
OD
OD_ext
V
SSDh − OD
where
R
ON_OD
+ R
V
=
∙ V
;
V
= V
ꢂꢃ
cc
ꢄꢅ cc
R
OD_ext
ON_OD
Figure 10. Smart shutdown timing waveforms
VREF
CIN
tFCIN
tFCIN
Fast shut down
immediately after the comparator triggering
the driver outputs are switched off
tCINoff
LVG/HVG
OD
VOD
VSSDh
VSSDl
1
2
OD gate
(internal)
t1
t2
disable time
FAULT
SMART SHUTDOWN CIRCUIT
external pull-up
VCC
5
V
5
V
IOD
IOD
R
OD_ext
OD
OD
SMART
SD
LOGIC
SMART
SD
LOGIC
C
OD
COD
RON_OD
RON_OD
DS13048 - Rev 4
page 19/32
STSPIN32F0251, STSPIN32F0252
Microcontroller unit
6.2
Microcontroller unit
The integrated MCU is the STM32F031x6 with the following main characteristics:
•
•
•
•
•
•
•
Core: ARM® 32-bit Cortex® -M0 CPU, frequency up to 48 MHz
Memories: 4kB of SRAM, 32 kB of Flash Memory
CRC calculation unit
Up to 21 fast I/Os
Advanced-control timer dedicated for PWM generation
Up to 6 general purpose timers
12-bit ADC (up to 10 channels)
•
•
•
Communication interfaces: I2C, USART, SPI
Serial Wire Debug (SWD)
Extended temperature range: -40 to 125°C
Note:
For more details refer to the STM32F031x6 datasheet on www.st.com
6.2.1
Memories and boot mode
The device has the following features:
•
4 Kbytes of embedded SRAM accessed (read/write) at CPU clock speed with 0 wait states and featuring
embedded parity checking with exception generation for fail-critical applications.
•
The non-volatile memory is divided into two arrays:
–
–
32 Kbytes of embedded Flash memory for programs and data
Option bytes
The option bytes are used to write-protect the memory (with 4 KB granularity) and/or readout-protect the whole
memory with the following options:
•
•
Level 0: no readout protection
Level 1: memory readout protection, the Flash memory cannot be read from or written to if either debug
features are connected or boot in RAM is selected
•
Level 2: chip readout protection, debug features (Cortex®-M0 serial wire) and boot in RAM selection
disabled.
At startup, the boot pin and boot selector option bit are used to select one of the three boot
options:
•
•
•
boot from User Flash memory
boot from System Memory
boot from embedded SRAM
The boot loader is located in System Memory, programmed by ST during production. It is used to reprogram the
Flash memory by using USART on pins PA14/PA15.
6.2.2
Power management
The VDD pin is the power supply for I/Os and the internal regulator.
The VDDA pin is power supply for ADC, Reset blocks, RCs and PLL. The VDDA voltage is provided externally
through VDDA pin
Note:
The VDDA voltage level must be always greater or equal to the VDD voltage level and must be established first.
The MCU has integrated power-on reset (POR) and power-down reset (PDR) circuits. They are always active,
and ensure proper operation above a threshold of 2 V. The device remains in reset mode when the monitored
supply voltage is below a specified threshold, VPOR/PDR, without the need for an external reset circuit.
•
The POR monitors only the VDD supply voltage. During the startup phase it is required that VDDA should
arrive first and be greater than or equal to VDD.
•
The PDR monitors both the VDD and VDDA supply voltages, however the VDDA power supply supervisor
can be disabled (by programming a dedicated Option bit) to reduce the power consumption if the application
design ensures that VDDA is higher than or equal to VDD.
DS13048 - Rev 4
page 20/32
STSPIN32F0251, STSPIN32F0252
Microcontroller unit
The device features an embedded programmable voltage detector (PVD) that monitors the VDD power supply
and compares it to the VPVD threshold. An interrupt can be generated when VDD drops below the VPVD
threshold and/or when VDD is higher than the VPVD threshold. The interrupt service routine can then generate a
warning message and/or put the MCU into a safe state. The PVD is enabled by software.
The MCU supports three low-power modes to achieve the best compromise between low power consumption,
short startup time and available wakeup sources:
•
•
Sleep mode
In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can wake up the CPU
when an interrupt/event occurs.
Stop mode
Stop mode achieves very low power consumption while retaining the content of SRAM and registers.
All clocks in the 1.8 V domain are stopped, the PLL, the HSI RC and the HSE crystal oscillators are
disabled. The voltage regulator can also be put either in normal or in low power mode.
The device can be woken up from Stop mode by any of the EXTI lines (one of the 16 external lines, the
PVD output, RTC, I2C1 or USART1).
•
Standby mode
The Standby mode is used to achieve the lowest power consumption. The internal voltage regulator is
switched off so that the entire 1.8 V domain is powered off. The PLL, the HIS RC and the HSE crystal
oscillators are also switched off. After entering Standby mode, SRAM and register contents are lost
except for registers in the RTC domain and Standby circuitry.
The device exits Standby mode when an external reset (NRST pin), an IWDG reset, a rising edge on
the WKUP pins, or an RTC event occurs.
6.2.3
High-speed external clock source
The high-speed external (HSE) clock can be generated from external clock signal or supplied with a 4 to 32
MHz crystal/ceramic resonator oscillator (see Figure 11). In the application, the resonator and the load capacitors
have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup
stabilization time.
Figure 11. Typical application with 8 MHz crystal
1.
2.
The REXT value depends on the crystal characteristics (refer to the crystal resonator manufacturer for more
details on them).
The external clock signal has to respect the I/O characteristics and follows recommended clock input
waveform (refer to Figure 12).
Figure 12. HSE clock source timing diagram
DS13048 - Rev 4
page 21/32
STSPIN32F0251, STSPIN32F0252
Advanced-control timer (TIM1)
6.3
Advanced-control timer (TIM1)
The advanced-control timer (TIM1) can be seen as a three-phase PWM multiplexed on six channels. It has
complementary PWM outputs with programmable inserted deadtimes.
This timer is used to generate the PWM signal for the three half-bridge gate drivers as shown in Table 9.
Table 9. TIM1 channel configuration
MCU I/O
PB13
PB14
PB15
PA8
ASIC input
LIN1
TIM1 channel
TIM1_CH1N
TIM1_CH2N
TIM1_CH3N
TIM1_CH1
LIN2
LIN3
HIN1
PA9
HIN2
TIM1_CH2
PA10
HIN3
TIM1_CH3
DS13048 - Rev 4
page 22/32
STSPIN32F0251, STSPIN32F0252
Package information
7
Package information
In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK®
packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions
and product status are available at:www.st.com www.st.com.
ECOPACK® is an ST trademark.
7.1
TQFP 10x10 64L package information
Figure 13. TQFP mechanical data
BOTTOM VIEW
EXPOSED PAD
DS13048 - Rev 4
page 23/32
STSPIN32F0251, STSPIN32F0252
TQFP 10x10 64L package information
Table 10. TQFP package dimensions
Symbol
A
Min
-
Nom
-
Max
1.2
0.15
1.05
0.27
0.23
0.2
0.16
-
TOTAL THICKNESS
STAND OFF
A1
A2
b
0.05
0.95
0.17
0.17
0.09
0.09
-
-
MOLD THICKNESS
LEAD WIDTH(PLATING)
LEAD WIDTH
-
0.22
0.2
-
b1
c
L/F THICKNESS(PLATING)
L/F THICKNESS
c1
D
-
X
Y
X
Y
12
12
10
10
0.5
0.6
3.5°
-
E
-
-
D1
E1
e
-
-
BODY SIZE
-
-
LEAD PITCH
-
-
L
0.45
0°
0.75
7°
θ
θ1
θ2
θ3
R1
R2
S
0°
-
11°
11°
0.08
0.08
0.2
5.85
5.85
12°
12°
-
13°
13°
-
-
0.2
-
-
X
Y
M
5.95
5.95
6.05
6.05
EP SIZE
N
PACKAGE LEAD TOLERANCE
LEAD EDGE TOLERANCE
COPLANARITY
aaa
bbb
ccc
ddd
eee
0.2
0.2
0.08
0.08
0.05
LEAD OFFSET
MOLD FLATNESS
Note:
All dimensions are mm unless otherwise specified
DS13048 - Rev 4
page 24/32
STSPIN32F0251, STSPIN32F0252
TQFP 10x10 64L package information
Figure 14. QFN mechanical data
TOP VIEW
BOTTOM VIEW
EXPOSED PAD
SIDE VIEW
Table 11. QFN package dimensions
Symbol
Min
0.90
0
Non
Max
1.00
0.05
TOTAL THICKNESS
STAND OFF
A
A1
A3
b
0.95
L/F THICKNESS
LEAD WIDTH
0.20 Ref.
0.20
0.15
9.90
5.40
0.25
10.10
5.60
BODY LENGTH X
EP LENGTH X
LEAD PITCH
D
10.00
5.50
D2
e
0.50 BSC
10.00
5.50
BODY WIDTH Y
EP WIDTH Y
E
9.90
5.40
0.30
10.10
5.60
0.50
E2
L
LEAD LENGTH
0.40
DS13048 - Rev 4
page 25/32
STSPIN32F0251, STSPIN32F0252
Suggested land pattern
Symbol
Min
Non
Max
K
1.85 Ref.
Note:
All dimensions are mm unless otherwise specified
7.2
Suggested land pattern
Figure 15. TQFP 10x10 64L suggested land pattern
11.45
6.00
.25
Note:
All dimensions are mm unless otherwise specified
Figure 16. QFN 10x10 72L suggested land pattern
DS13048 - Rev 4
page 26/32
STSPIN32F0251, STSPIN32F0252
Ordering information
8
Ordering information
Table 12. Order codes
Order code
Package
TQFP 10x10 64L
TQFP 10x10 64L
Package marking
STSPIN32F0 251
Packaging
STSPIN32F0251
Tray
STSPIN32F0251TR
STSPIN32F0252
STSPIN32F0 251
STSPIN32F0 252
STSPIN32F0 252
SPINF251Q
Tape and Reel
Tray
TQFP 10x10 64L
TQFP 10x10 64L
QFN 10 x 10 72L
QFN 10 x 10 72L
QFN 10 x 10 72L
QFN 10 x 10 72L
STSPIN32F0252TR
STSPIN32F0251Q
STSPIN32F0251QTR
STSPIN32F0252Q
STSPIN32F0252QTR
Tape and Reel
Tray
SPINF251Q
Tape and Reel
Tray
SPINF252Q
SPINF252Q
Tape and Reel
DS13048 - Rev 4
page 27/32
STSPIN32F0251, STSPIN32F0252
Revision history
Table 13. Document revision history
Date
Version
Changes
29-Aug-2019
4-sep-2019
27-Oct-2020
1
2
3
Initial release.
Changed Figure 2 and 11
Added QFN package version
Change to Title. Cover image updated.
Table 3, Table 4 and Table 5 updated.
Figure 6 and Figure 10 changed.
10-Feb-2021
4
DS13048 - Rev 4
page 28/32
STSPIN32F0251, STSPIN32F0252
Contents
Contents
1
2
3
4
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
Pin description and connection diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
Pin description table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
4.1
4.2
4.3
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
5
6
Electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Device description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
6.1
Gate driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
6.1.1
6.1.2
6.1.3
6.1.4
6.1.5
Inputs and outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Deadtime . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
VCC UVLO protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
V
UVLO protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
BO
Comparator and Smart shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6.2
6.3
Microcontroller unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
6.2.1
6.2.2
6.2.3
Memories and boot mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
High-speed external clock source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Advanced-control timer (TIM1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
7
8
Package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
7.1
7.2
TQFP 10x10 64L package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Suggested land pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
List of tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
List of figures. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
DS13048 - Rev 4
page 29/32
STSPIN32F0251, STSPIN32F0252
List of tables
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Legend/abbreviations used in the pin description table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
STSPIN32F025x MCU-Driver internal connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Pin description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Recommended operating conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Inputs truth table (applicable when device is not in UVLO or SmartSD protection) . . . . . . . . . . . . . . . . . . . . . . 16
TIM1 channel configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 10. TQFP package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 11. QFN package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 12. Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 13. Document revision history. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
DS13048 - Rev 4
page 30/32
STSPIN32F0251, STSPIN32F0252
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
STSPIN32F025x SiP block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
STSPIN32F025x pin connection (TQFP top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
STSPIN32F025x pin connection (QFN top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Propagation delay timing definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Deadtime timing definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Deadtime and interlocking waveforms definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
VCC power ON and UVLO, LVG timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
VCC power ON and UVLO, HVG timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
VBO Power-ON and UVLO timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Smart shutdown timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Typical application with 8 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
HSE clock source timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
TQFP mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
QFN mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
TQFP 10x10 64L suggested land pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
QFN 10x10 72L suggested land pattern. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
DS13048 - Rev 4
page 31/32
STSPIN32F0251, STSPIN32F0252
IMPORTANT NOTICE – PLEASE READ CAREFULLY
STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST
products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST
products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement.
Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of
Purchasers’ products.
No license, express or implied, to any intellectual property right is granted by ST herein.
Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product.
ST and the ST logo are trademarks of ST. For additional information about ST trademarks, please refer to www.st.com/trademarks. All other product or service
names are the property of their respective owners.
Information in this document supersedes and replaces information previously supplied in any prior versions of this document.
© 2021 STMicroelectronics – All rights reserved
DS13048 - Rev 4
page 32/32
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