STV0118_技术文档

STV0118

PAL/NTSC HIGH PERFORMANCE DIGITAL ENCODER

PRELIMINARY DATA

.

NTSC-M, PAL-B, D, G, H, I, N, M, PLUS

NTSC-4.43 ENCODING (OPTIONAL PEDES-

TAL IN ALL STANDARDS)

SMALL AND ECONOMICAL SO28 PACKAGE

LINE SKIP/INSERT CAPABILITY SUPPRES-

SING THE NEED FOR AN EXTERNAL VCXO,

THUS REDUCING APPLICATION COST

4 SIMULTANEOUS ANALOG OUTPUTS : RGB +

CVBS, or S-VHS (Y/C) + CVBS1 + CVBS2

54MHz INPUT MULTIPLEX INTERFACE FOR

24-BIT DIRECT DIGITAL FREQUENCY SYN-

THESIZERFOR COLORSUBCARRIER

PROGRAMMABLE RESET OF COLOR SUB-

CARRIER PHASE (4 MODES)

.

2

.

EASY CONTROL VIAFAST I C BUS

2

TWO I C ADDRESSES

AUTOTEST OPERATION MODE (ON-CHIP

COLOR BAR PATTERN 100/0/75/0)

CMOS TECHNOLOGY WITH 3.3V POWER

SUPPLY

APPLICATIONS : SATELLITE, CABLE & TER-

RESTRIAL DIGITAL TV DECODERS, MULTIME-

DIATERMINALS,DVDPLAYERS

.

DOUBLE

ENCODING

APPLICATIONS

(TO BE ABLE TO ENCODE OR NOT THE OSD

CONTENT OF THE VIDEO INPUT STREAM)

CROSS-COLOR REDUCTION BY SPECIFIC

TRAP FILTERING ON LUMA WITHIN CVBS

FLOW

CLOSED CAPTIONING, CGMS ENCODING

AND TELETEXT ENCODING

.

ITU-R/CCIR601 ENCODING WITH EASILY

PROGRAMMABLE COLOR SUB-CARRIER

FREQUENCIES

DIGITAL FRAME SYNC INPUT/OUTPUT

(ODDEV/VSYNC), PROGRAMMABLE PO-

LARITY AND RELATIVE POSITION

DIGITAL HORIZONTAL SYNC INPUT/OUPUT

(HSYNC), PROGRAMMABLE POLARITY AND

RELATIVE POSITION

DIGITAL LINE OR FRAME SYNC EXTRAC-

TION FROM ITU-R/CCIR656 / D1 DATA

.

SO28

(Plastic Micropackage)

MASTER

OPERATION

MODE,

PLUS

ORDER CODE : STV0118

6 SLAVE MODES

INTERLACED/NON-INTERLACED OPERA-

TION MODES

FULL OR PARTIAL VERTICAL BLANKING

LUMAFILTERING WITH 2X OVERSAMPLING&

SINY/Y CORRECTION

CHROMINANCE FILTERING WITH 4X OVER-

SAMPLING TO EITHER 1.1MHz, 1.3MHz,

1.6MHz or 1.9MHz

.

WIDE CHROMINANCE BANDWIDTH FOR

RGB ENCODING (2.45MHz)

1/42

May 1997

This is advance information on a new product now in development or undergoing evaluation. Details are subject to change without notice.

STV0118

CONTENTS

Page

I

GENERAL DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3

II

PIN INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3

II.1

II.2

PIN CONNECTIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

PIN DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3

4

III

BLOCK DIAGRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

FUNCTIONAL DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5

6

IV

IV.1

IV.2

IV.3

IV.4

DATA INPUT FORMAT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

VIDEO TIMING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

RESET PROCEDURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

MASTER MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6

10

11

IV.5

SLAVE MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

12

IV.5.1

IV.5.2

IV.5.3

Synchronizationonto a Line Sync Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Synchronizationonto a Frame Sync Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Synchronizationonto Data-embeddedSync Words . . . . . . . . . . . . . . . . . . . . . . . . . . . .

12

13

14

IV.6

IV.7

IV.8

IV.9

IV.10

IV.11

IV.12

IV.13

IV.14

INPUT DEMULTIPLEXER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

SUB-CARRIER GENERATION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

BURST INSERTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

LUMINANCE ENCODING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

CHROMINANCE ENCODING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

COMPOSITE VIDEO SIGNAL GENERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

RGB ENCODING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

CLOSED CAPTIONING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

CGMS ENCODING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

15

16

17

18

19

IV.15

TELETEXT ENCODING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

19

IV.15.1 Signals Exchanged . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

IV.15.2 Transmission Protocol. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

IV.15.3 Programming. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

IV.15.4 Teletext Pulse Shape . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

19

20

IV.16

IV.17

IV.18

IV.19

I²C BUS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

DUAL ENCODING APPLICATION WITH 54MBIT/S YCRCB INTERFACE . . . . . . . . . .

LINE SKIP / LINE INSERT CAPABILITY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

CVBS, S-VHS AND RGB ANALOG OUTPUTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

21

22

24

V

CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

25

V.1

V.2

V.3

V.4

ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

THERMAL DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

DC ELECTRICAL CHARACTERISTICS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

AC ELECTRICAL CHARARCTERISTICS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

25

26

VI

REGISTERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

27

VI.1

VI.2

REGISTER MAPPING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

REGISTER CONTENTS AND DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

27

28

VII

APPLICATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

PACKAGE MECHANICAL DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

41

42

VIII

2/42

STV0118

I - GENERAL DESCRIPTION

The STV0118 is a high performance PAL/NTSC

digital encoder in a low cost pakage. It converts a

4:2:2 digital video stream into a standard analog

baseband PAL/NTSC signal and into RGB analog

components. The STV0118 can handle interlaced

mode (with 525/625 line standards) and non-inter-

laced mode. It can perform Closed-Captions,

CGMS or Teletext encoding.

Four analog output pins are available, on which it

is possible to output either S-VHS(Y/C) + CVBS1

+ CVBS2 or RGB + CVBS. Moreover, it is possible

to use two STV0118 in parallel to interface with

SGS-THOMSON’s MPEG decoder ICs that are

able to deliver a 54Mbit/s “double” YCrCb stream

(e.g. the STi3520M). This allows for example to

encode OSD in one of the streams only.

II - PIN INFORMATION

II.1 - Pin Connections

HSYNC

YCRCB7

YCRCB6

YCRCB5

YCRCB4

YCRCB3

YCRCB2

YCRCB1

YCRCB0

V_SS

1

28

27

26

25

24

23

22

21

20

19

18

17

16

15

VSYNC/ODDEVEN

SDA

2

3

SCL

4

RESET

CKREF

TTXD

5

6

7

TTXS/CSI2C

V_DD

8

9

G/Y

10

11

12

13

14

R/C

CVBS

B/CVBS

VR_RGB

I_REF(RGB)

V_DDA

VR_CVBS

I_REF(CVBS)

V_SSA

3/42

STV0118

II - PIN INFORMATION (continued)

II.2 - Pin Description

Name

Type

Function

1

HSYNC

I/O

Line Synchronization Signal :

- Input in ODDEV+HSYNC or VSYNC + HSYNC or VSYNC slave modes

- Output in all other modes (master/slave)

- Synchronous to rising edge of CKREF

- Default polarity : negative pulse

2

3

4

5

6

7

8

9

YCrCb7

YCrCb6

YCrCb5

YCrCb4

YCrCb3

YCrCb2

YCrCb1

YCrCb0

I/O

Input : time multiplexed 4:2:2 luminance and chrominance data as defined in ITU-R

Rec601-2 and Rec656 (except for TTL input levels). This bus interfaceswith MPEG video

decoder output port and typically carries a stream of Cb,Y,Cr,Y digital video at CKREF

frequency, clocked on the rising edge (by default) of CKREF. A 54-Mbit/s ‘double’ Cb, Y,

Cr, Y input multiplex is supported for double encoding application (rising and falling edge

of CKREF are operating). Output: for test purpose only.

10

11

V_SS

Supply Digital Ground

CVBS

Output Analog Composite Video Output (current-driven).

CVBS must be connected to analog ground over a load resistor (R_LOAD).

Following the load resistor, a simple analog low pass filter is recommended CVBS

amplitude is proportional to I_REF(CVBS)(V_OUT(N)= N x R_LOADx I_REF(CVBS)/96) with N = [0-

511] V_OUT(Max.)= 1V_PPand I_OUT(Max.)= 5mA

12

13

VR_CVBS

I_REF(CVBS)

I/O

Internal Reference Voltage for the 9-bit DAC CVBS.

VR_CVBS must be connected to analog ground over a capacitor (6.8nF typ.),

VR_CVBS = 1.9V

Reference current source for the 9-bit DAC CVBS.

- I_REF(CVBS)must be biased to analog ground over a reference resistor R_REF(CVBS)

- R_{REF(CVBS)(Min.)}= 5.95 x R_LOAD/V_OUT(Max.)with V_OUT(Max.)= 1V_PPand I_OUT(Max.)= 5mA

(I_REF(CVBS)= V_REF(CVBS)/R_REF(CVBS)), V_{REF(CVBS)(Typ.)}= 1.12V.

14

15

16

V_SSA

V_DDA

Supply Analog ground for DACs

Supply Analog positive power supply for DACs (+3.3V nom.)

I_REF(RGB)

I/O

Reference current source for Tri-DAC R/Y,G/C,B/CVBS.

-I_REF(RGB)must be connected to analog ground over a reference resistor R_REF(RGB)

-R_{REF(RGB)(Min.)}= 5.95 x R_LOAD/V_OUT(Max.), with V_OUT(Max.)= 1V_PPand I_OUT(Max.)= 5mA

(I_REF(RGB)= V_REF(RGB)/R_REF(RGB)), V_{REF(RGB) (Typ.)}= 1.12V.

17

18

VR_RGB

B/CVBS

I/O

O

Internal reference voltage for the 9bit Tri-DAC R/Y,G/C,B/CVBS.

VR_RGB must be biased toanalog ground overa typical 6.8nF capacitor, VR_RGB = 1.9V.

Analog ‘Blue’ or CVBS output (current-driven).

This output must be connected to analog ground over a load resistor (R_LOAD).

Following the load resistor, a simple analog low pass filter is recommended.

V_OUT(Max.)= 1V_PPand I_OUT(Max.)= 5mA (V_OUT(N)= N x R_LOADx I_REF(RGB)/96)

with N = [0-511].

19

20

21

R/C

G/Y

V_DD

O

Analog ‘Red’ or S-VHS Chrominance output (current-driven).

This output must be connected to analog ground over a load resistor (R_LOAD).

Following the load resistor, a simple analog low pass filter is recommended.

V_OUT(Max.)= 1V_PPand I_OUT(Max.)= 5mA (V_OUT(N)= N x R_LOADx I_REF(RGB)/96)

with N = [0-511].

Analog ‘Green’ or S-VHS Luminance output (current-driven).

This output must be connected to analog ground over a load resistor (R_LOAD).

Following the load resistor, a simple analog low pass filter is recommended.

V_OUT(Max.)= 1V_PPand I_OUT(Max.)= 5mA (V_OUT(N)= N x R_LOADx I_REF(RGB)/96)

with N = [0-511].

Supply Digital positive supply voltage (+3.3V nom.)

22 TTXS/CSI2C

I/O

Output : positive sync pulse for control of Teletext buffer in external demultiplexer or

Transport IC.

23

TTXD

I/O

Teletext data stream from external demultiplexer or Transport IC synchronous to rising

edge of CKREF signal average rate of 6.9375Mbit/s.

Output in test mode only.

4/42

STV0118

II - PIN INFORMATION (continued)

II.2 - Pin Description (continued)

Name

Type

Function

24

CKREF

I

Master clock reference signal.

Its rising edge is the default reference for set-up and hold times of all inputs, and for

propagation delay of all outputs (except for SDA output).

CKREF nominal frequency is 27MHz (CCIR601) : input pad with pull down (50kΩ Typ.)

25

RESET

I

Hardware reset, active LOW.

It has priorityoversoftware reset.NRESET imposesdefault states (seeRegister Contents).

Minimum Low level required duration is 5 CKREF periods : input pad with pull down

(50kΩ Typ.)

26

27

SCL

SDA

I

I²C bus clock line (internal 5-bit majority logic with CKREF for reference) : input pad with

pull down (50k Typ.)

Ω

I/O

I²C bus serial data line.

Input : internal 5-bit majority logic with CKREF for reference

Output : open drain

28

VSYNC/

ODDEVEN

I/O

Frame sync signal :

- input in slave modes, except when sync is extracted from YCrCb data

- output in master mode and when sync is extracted from YCrCb data

- synchronous to rising edge of CKREF

- ODDEVEN default polarity :

odd (not-top) field : LOW level

even (bottom) field : HIGH level

III - BLOCK DIAGRAM

TTXS/

TTXD CSI2C

23

22

STV0118

CSI2C

AUTOTEST

COLOR BAR

PATTERN

TTXS

TELETEXT

V_DDA

V_DD

YCRCB7

YCRCB6

21

2

G/Y

20

19

18

17

16

CB-CR

RGB ENCODING

R/C

3

B/CVBS

VR_RGB

I_REF(RGB)

YCRCB5

YCRCB4

4

LUMA

PROCESSING

Y

5

YCRCB3

YCRCB2

YCRCB1

YCRCB0

6

TRAP

7

CLOSED

CAPTIONS

CGMS

8

V_SSA

9

V_DDA

V_SSA

V_DDA

14

15

V_SS10

CHROMA

PROCESSOR

VSYNC/ODDEVEN 28

CVBS

11

12

13

SYNC CONTROL

& VIDEO TIMING

GENERATOR

HSYNC

RESET

1

VR_CVBS

I_REF(CVBS)

9-BIT

DAC

CTRL + CFG

REGISTER

CSI2C

25

CKREF 24

V_SSA

27

26

SDA

SCL

I²C BUS

5/42

STV0118

IV - FUNCTIONAL DESCRIPTION

The STV0118 can operate either in master mode,

where it supplies all sync signals, or in 6 slave

modes, where it locks onto incoming sync signals.

The main functions are controlled by a micro-con-

troller via an I²C 2-wire bus. Refer to the “User’s

Register Description” for an exhaustive list of the

control possibilities available.

allows to keep in the encoded waveform any VBI

data present in digitized form in the incoming

YCrCb stream (e.g. WSS data, VPS, supplemen-

tary Closed-Captions line or StarSight data, etc.).

Alternatively,the complete VBI maybe blanked(no

incoming YCrCb data encoded on these lines, “full

blanking”).

The completeVBI comprisesof the followinglines:

- for 525/60systems (SMPTE line numbering con-

vention): lines 1 to 19 and second half of line 263

to line 282.

- for 625/50 systems (CCIR line numbering con-

vention) : second half of line 623 to line 22 and

lines 311 to 335.

IV.1 - Data Input Format

The digital input is a time-multiplexed ITU-R656

/D1-type [Cb, Y, Cr, Y] 8-bit stream. Note that

“ITU-R” was formerly knownas “CCIR”. Inputsam-

ples are latched in on the rising edge (by default)

of the clock signal CKREF, whose nominal fre-

quencyis 27MHz. Figure 1 illustratesthe expected

data input format. Alternatively,a 54-Mbit/sstream

can be fed to the STV0118, refer to Section IV.17

(“dual encoding”) for details.

The ‘partial’ VBI consists of :

- for 525/60systems (SMPTE line numbering con-

vention) : lines 1 to 9 and second half of line 263

to line 272.

- for 625/50 systems (CCIR line numbering con-

vention): secondhalf of line623to line 5and lines

311 to 318.

The STV0118 is able to encode interlaced and

non-interlaced video. One bit is sufficient to auto-

matically direct the STV0118to process non-inter-

laced video. Update is performed internallyon the

first frame sync active edgefollowing the program-

ing of this bit. The non-interlaced mode is a

624/2 = 312 line mode or a 524/2= 262 line mode,

where all fields are identical.

Full or partialblankingis controlledby configuration

bit ‘blkli in configurationregister1’.

Note that :

- line 282 in 525/60/SMPTEsystems is either fully

blanked or fullyactive.

An ‘autotest’ mode is available by setting 3 bits

(sync[2:0]) within the configurations register0.

In this mode, a color bar patternis produced,inde-

pendentlyfrom video input, in the adequatestand-

ard. As this mode sets the STV0118 in master

mode, VSYNC/ODDEV and HSYNC pins are then

in output mode.

- line 23 in 625/60/CCIR systems is always fully

active.

In anITU-R656-compliant digitalTV line, the active

portion of the digital line is the portion included

between the SAV (Start of Active Video) and EAV

(End of Active Video) words. However, this digital

active line starts somewhat earlier and may end

slightly later than the active line usually defined by

analog standards. The STV0118 allows two ap-

proaches :

- It is possible to encode the full digital line (720

pixels/ 1440clock cycles).In this case,theoutput

waveform will reflect the full YCrCb stream in-

cluded between SAV and EAV.

IV.2 - Video Timing

The STV0118 outputs interlaced or non-interlaced

video in PAL-B, D, G, H, I, PAL-N, PAL-M or

NTSC-M standards and ‘NTSC- 4.43’ is also pos-

sible.

The 4-frame (for PAL) or 2 frame (for NTSC) burst

sequences are internally generated, subcarrier

generation being performed numerically with

CKREF as reference. Rise and fall times of syn-

chronizationtips andburst enveloppeareinternally

controlled according to the relevant ITU-R and

SMPTE recommendations.

- Alternatively, it is possible to drop some YCrCb

samples at the extremities of the digital line so

that the encoded analog line fits within the ‘ana-

log’ ITU-R/SMPTE specifications.

Selection between these two modes of operation

is performed with bit ‘aline’ in configuration regis-

ter 4.

Figures 2 to 7 depict typical VBI waveforms.

It is possible to allow encoding of incoming YCrCb

data on those lines of the VBI that do not bear line

sync pulses or pre/post-equalisation pulses (see

Figures 2 to 7). This mode of operation is refered

to as “partial blanking” and is the default set-up. It

In all cases, the transitions between horizontal

blanking and active video are shaped to avoid too

steep edges within theactive video. Figure 8 gives

timings concerning the horizontal blanking interval

and the active video interval.

6/42

STV0118

IV - FUNCTIONAL DESCRIPTION (continued)

Figure 1 : Input Data Format

4T

E

A

V

S

A

V

E

A

V

276T

1440T

NTSC, PAL M

(525 Line / 60Hz)

Digital Standing Interval

Digital Active Line

1716T

Line Duration

288T

1440T

PAL B, D, G, H, I, N

(625 Line / 50Hz)

1728T

Figure 2 : PAL-BDGHI, PAL-N Typical VBI Waveform, Interlaced Mode (CCIR-625 Line Numbering)

0_V

A

B

IV

308

309

310

311

312

313

314

315

316

317

318

319

A

320

Full VBI1

Partial VBI1

I

621

622

623

624

625

1

2

3

4

5

6

7

22

23

Full VBI2

Partial VBI2

A

II

308

309

310

311

312

313

314

315

316

317

318

317 335

B

336

A

III

621

622

623

624

625

1

2

3

4

5

6

7

8

I

II

C

III

IV

0_V

:

Frame synchronizationreference

th

I, II, III, IV : 1^stand 5^th, 2^ndand 6^th, 3^rdand 7 , 4^thand 8 fields

A :

B :

C :

Burst phase : nominal value +135°

Burst phase : nominal value -135°

Burst suppression internal

Figure 3 : PAL-BDGHI, PAL-N Typical VBI Waveform, Non-interlaced Mode (“CCIR-like” Line Numbering)

Full VBI

Partial VBI

A

B

0_V

308

309

310

311

312

1

2

3

4

5

6

7

8

22

Burst phase toggles every line

7/42

STV0118

IV - FUNCTIONAL DESCRIPTION (continued)

Figure 4 : NTSC-M Typical VBI Waveforms, Interlaced Mode (SMPTE-525 Line Numbering)

Full VBI1

Partial VBI1

1

2

3

4

5

6

7

8

9

10

18

H

19

H

0.5H

Full VBI2

270

Partial VBI2

262

263

264

265

266

267

268

269

271

H

272

273

282

0.5H

H

VBI3

7

525

1

2

3

4

5

6

8

9

10

18

19

VBI4

270

263

264

265

266

267

268

269

271

272

273

282

Figure 5 : NTSC-M Typical VBI Waveforms, Non-interlaced Mode (“SMPTE-like” Line Numbering)

Full VBI

Partial VBI

3H

2

3H

5

3H

8

262

H

1

3

4

6

7

9

10

18

H

19

H

0.5H

8/42

STV0118

IV - FUNCTIONAL DESCRIPTION (continued)

Figure 6 : PAL-M Typical VBI Waveforms, Interlaced Mode (CCIR-525 Line Numbering)

Full VBI1

F’

F

F’

F

PartialVBI1

A

B

I

0_V

519

520

521

522

523

524

525

1

2

3

4

5

6

7

8

9

16

17

Full VBI2

F

F’

F

PartialVBI2

A

B

II

257

258

259

260

261

262

263

264

265

266

267

268

269

270

A

271 279

B

280

F

F’

F

III

519

520

521

522

523

524

525

1

2

3

4

5

6

7

8

9

F’

F

A

B

IV

257

258

259

260

261

262

263

264

265

266

267

268

269

270

271

272

I

II

C

III

IV

0_V

:

Framesynchronizationreference

st th nd th rd th th

th

I, II, III, IV :

1

and5 , 2 and 6 , 3 and 7 , 4 and8 fields

A :

B :

C :

Burst phase : nominalvalue +135°

Burst phase : nominalvalue -135°

Burst suppressioninternal

Figure 7 : PAL-M Typical VBI Waveforms, Non-interlaced Mode (“CCIR-like” Line Numbering)

Full VBI

Partial VBI

A

B

0_V

256

257

258

259

260

261

262

1

2

3

4

5

6

7

8

9

10

16

17

Burst phase togglesevery line

9/42

STV0118

IV - FUNCTIONAL DESCRIPTION (continued)

Figure 8 : Horizontal Blanking Intervaland Active Video Timings

d

Full Digital Line Encoding

(720 Pixels - 1440T)

0_H

”Analog” Line Encoding

(710 Pixels - 1420T)

b

a

c1 (bit ”aline” = 0)

c2 (bit ”aline” = 1)

NTSC-M

PAL-BDGHI

PAL-N

PAL-M

5.38µs(even lines)

5.52µs(odd lines)

5.54µs (A-type)

5.66µs (B-type)

5.54µs (A-type)

5.66µs (B-type)

5.73µs (A-type)

5.87µs (B-type)

a

These are typical values.

Actual values will depend on the static offset programmed for subcarrier generation.

1.56µs

1.28µs

b

c1

c2

8.8µs

9.3µs

10.1µs

9 Cycles of 3.58MHz 10 Cycles of 4.43MHz 9 Cycles of 3.58MHz 9 Cycles of 3.58MHz

d

IV.3 - Reset Procedure

Ahardwarereset is performedby groundingthe pin

NRESET. The master clock must be running and

pin NRESET kept low for a minimum of 5 clock

cycles. This sets the STV0118 in HSYNC+ODDEV

(line-locked) slave mode, for NTSC-M, interlaced

ITU-R601 encoding. Closed-captioning and

Teletext encoding are all disabled.

are never reset, their contentsis unknown until the

first loading (refer to the Register Contents and

Description).

It is also possible to perform a software reset by

setting bit’softreset’ in Reg 6. The IC’s response in

that caseis similar to itsresponseafter a hardware

reset, except that Configuration Registers

(Reg 0 to6) anda few otherregisters (see descrip-

tion of bit ‘softreset’) are not altered .

Then the configuration can be customized by wri-

ting into the appropriate registers. A few registers

10/42

STV0118

IV - FUNCTIONAL DESCRIPTION (continued)

IV.4 - Master Mode

In this mode, the STV0118 supplies HSYNC and

ODDEVsync signals(with independentlyprogram-

mable polarities) to drive other blocks. Refer to

Figure 9 and 10 for timings and waveforms.

cycles as soon as the master mode has been

loaded into the control register (Reg.0).

Configurationbits“Syncout_ad[1:0]”(Reg4)allowto

shift the relative position of the sync signals by up

to 3 clock cycles to cope with any YCrCb phasing.

The STV0118 starts encoding and counting clock

Figure 9 : ODDEVEN, VSYNC and HSYNC Waveforms

Active edge (programmable polarity)

128 T_ckref= 4.74µs

ODDEVEN

(see Note 1)

VSYNC

HSYNC

(see Note 2)

Line Numbers :

SMPTE-525

CCIR-625

4

1

5

2

6

3

266

313

267

314

268

315

269

316

Notes : 1. When ODDEVEN is a sync input, only one edge (“the active edge”) of the incoming ODDEVEN is taken into account for

synchronization. The “non-active” edge (2nd edge on thisdrawing) is not critical and its position may differ by H/2 from the location

shown.

2. The HSYNC pulse width indicated is valid when the STV0118 supplies HSYNC. In those slave modes where it receives HSYNC,

only the edge defined as active is relevant, and the width of the HSYNC pulse it receives is not critical.

Figure 10 : Master Mode Sync Signals

CKREF

Active Edge

(programmable polarity)

ODDEVEN

(out)

1T_CKREF

HSYNC

Active Edge

(programmable polarity)

(out)

Duration of HSYNC Pulse : 128 T_CKREF

Cr Y’

YCRCB

Cr

Y’

Cb

Y

Note : 1. This figure is valid for bits “syncout_ad[1:0]” = default.

11/42

STV0118

IV - FUNCTIONAL DESCRIPTION (continued)

IV.5 - Slave Modes

The STV0118 is thus fully slaved to the HSYNC

signal, which means that lines may contain more

or less samples than typical 525/625 system re-

quirement.

Six slave modes are available : ODDEV+HSYNC

based (line-based sync), VSYNC+HSYNC based

(another type of line-based sync), ODDEV-only

based (frame-based sync), VSYNC-only based

(another type of frame-based sync), or sync-in-

data based (line locked or frame locked).

If the digital line is shorter than its nominal value:

the sample counter is re-initialized when the ‘early’

HSYNC arrives and all internal synchronization

signals are re-initialized.

ODDEV refers to an odd/even (also known as

not-top/bottom) field flag, HSYNC is a line sync

signal,VSYNCis a verticalsync signal.Theirwave-

forms are depicted in Figure 9. The polarities of

HSYNC and VSYNC/ODDEV are independently

programmable in all slave modes.

If the digital line is longer than its nominal value :

the sample counter is stopped when it reaches its

nominal end-of-line value and waits for the ‘late’

HSYNC before reinitializing.

The field counter is incremented on each ODDEV

transition. The line counter is reset on the HSYNC

following each active edge of ODDEV.

IV.5.1- Synchronizationontoa Line Sync Signal

IV.5.1.1- HSYNC+ODDEV Based Synchronization

Synchronization is performed on a line-by-line ba-

sis by locking onto incoming ODDEV and HSYNC

signals. Refer to Figure 11 for waveforms and

timings. The polarities of the active edges of

HSYNC and ODDEV are programmable and inde-

pendent.

IV.5.1.2- HSYNC+VSYNC Based Synchronization

Synchronization is performed on a line-by-line ba-

sis by locking onto incoming VSYNC and HSYNC

signals. Refer to Figure 12 for waveforms and

timings. The polarities of HSYNC and VSYNC are

programmable and independent.

The first active edge of ODDEV initializes the inter-

nal line counter but encoding of the first line does

not start until an HSYNC active edge is detected

(at the earliest, HSYNC may transition at the same

time as ODDEV). At thatpoint, the internal sample

counter is initialized and encoding of the first line

starts. Then, encoding of each subsequent line is

individuallytriggeredby HSYNCactive edges.The

phase relationship between HSYNC and the in-

coming YCrCB data is normally such that the first

clockrising edge following the HSYNCactive edge

samples “Cb” (i.e. a ‘blue’ chroma sample within

the YCrCb stream). It is however possible to inter-

nally delay the incoming sync signals

(HSYNC+ODDEV) by up to 3 clock cycles to cope

with different data/sync phasings, using configura-

tion bits “Syncin_ad” (Reg. 4).

The incoming VSYNC signal is immediately trans-

formed into a waveform identical to the odd/even

waveform of an ODDEV signal, therefore the be-

havior of the core is identical to that described

above for ODDEV+HSYNC based synchroniza-

tion. Again, the phase relationship between

HSYNC and the incoming YCrCb data is normally

such that the first clock rising edge following the

HSYNC active edge samples “Cb” (i.e. a ‘blue’

chroma sample within the YCrCb stream). It is

however possible to internally delay the incoming

sync signals (HSYNC+VSYNC) by up to 3 clock

cycles to cope with different data/sync phasings,

using configuration bits “Syncin_ad” (Reg. 4).

The field counter is incremented on each active

edge of VSYNC.

Figure 11 : HSYNC + ODDEVEN Based Slave Mode Sync Signals

CKREF

Active Edge (programmable polarity)

ODDEVEN

(in)

Active Edge (programmable polarity)

HSYNC

(in)

YCRCB

Cb

Y

Cr

Y’

Cb

Note : 1. This figure is valid for bits “syncin_ad[1:0]” = default.

12/42

STV0118

IV - FUNCTIONAL DESCRIPTION (continued)

Figure 12 : HSYNC + VSYNC Based Slave Mode Sync Signals

CKREF

Active Edge (programmable polarity)

VSYNC

(in)

Active Edge (programmable polarity)

HSYNC

(in)

YCRCB

Cb

Y

Cr

Y’

Cb

Notes : 1. This figure is valid for bits “syncin_ad[1:0]” = default.

2. The active edges of HSYNC and VSYNC should normally be simultaneous. It is permissible that HSYNC transitions before

VSYNC, but VSYNC must not transition before HSYNC.

Figure 13 : ODDEVEN Based Slave Mode Sync Signals

CKREF

Active Edge (programmable polarity)

ODDEVEN

(in)

YCRCB

Cb

Y

Cr

Y’

Cb

Note : 1. This figure is valid for bits “syncin_ad[1:0]” = default.

IV.5.2- Synchronization onto a FrameSync Signal

IV.5.2.1 - ODDEV-only Based Synchronization

Encoding and analog sync generation carry on un-

less three successive fails of these checks occur.

Synchronizationis performed on a frame-by-frame

basis by locking onto an incoming ODDEV signal.

A line sync signal is derived internally and is also

output as HSYNC. Refer to Figure 13 for wave-

forms andtimings. Thephaserelationshipbetween

ODDEV and the incoming YCrCB data is normally

such that the first clock rising edge following the

ODDEV active edge samples “Cb” (i.e. a ‘blue’

chroma sample within the YCrCb stream). It is

however possible to internally delay the incoming

ODDEV signal by up to 3 clock cycles to cope with

different data/sync phasings, using configuration

bits “Syncin_ad” (Reg. 4).

In that case, three behaviors are possible, accord-

ing to the configuration programmed (Reg. 1-2) :

- if ‘free-run’ is enabled, the STV0118 carries on

outputtingthe digital line sync HSYNC and gene-

rating analog video just as though the expected

ODDEV edge had been present. However, it will

re-synchronize onto the next ODDEV active edge

detected, whateverits location.

- if ‘free-run’ is disabled but bit ‘sync_ok’ is set in

configuration register1, the STV0118 sets the

active portion of the TV line to black level but

carries on outputting the analog sync tips (on Ys

and CVBS) and the digital line sync signal

HSYNC.

Thefirst active edge of ODDEV triggersgeneration

of the analog sync signals and encoding of the

incomingvideo data.Frames beingsupposedto be

of constant duration, the next ODDEV active tran-

sition is expected at a precise time after the last

ODDEV detected.

- if ‘free-run’is disabled and the bit ‘sync_ok’is not

set, all analog video is at black level and neither

analog sync tips nor digital line sync are output.

Note that this mode is a frame-based sync mode,

as opposedtoa field-basedsyncmode, that is, only

one type of edge (rising or falling, according to bit

‘polv’in Reg 0) is of interest to the STV0118, the

other one is ignored.

So, once an active ODDEV edge has been de-

tected, checks that the following ODDEV are pre-

sent at the expected instants are performed.

13/42

STV0118

IV - FUNCTIONAL DESCRIPTION (continued)

IV.5.2.2 - VSYNC only Based Synchronization

time after the latest detection.

So, once an active ‘F’ flag has been detected,

checks that the following flags are present within

the incoming video stream at the expected times

are performed.

Encoding and analog sync generation carry on un-

less three successive fails of these checks occur.

Synchronization is performed on a frame-by-frame

basis by locking onto an incoming VSYNC signal.

An auxiliary line sync signal HSYNC must also be

fedto theSTV0118,whichusesittoreconstructfrom

VSYNC and HSYNC information an internal

odd/even waveform identical to that of an ODD-

EVEN signal. Thereforethe behaviorof the core is

identicaltothatdescribedaboveforODDEVENonly

basedsynchronization(exceptthatnothingis output

onHSYNCpin since it isan inputportin thatmode).

Note that HSYNC is an input but has no other use

than allowing the STV0118 to decide whether an

incoming VSYNC pulse flags an odd or an even

field. In other words, the STV0118 does not lock

onto HSYNC in this mode since this is NOT a

line-locked mode.

The phase relationship between VSYNC and the

incomingYCrCb data is normallysuch that the first

clockrising edge following the VSYNC activeedge

samples “Cb” (i.e. a ‘blue’ chroma sample within

the YCrCb stream). It is however possible to inter-

nally delay the incoming sync signals

(VSYNC+HSYNC) by up to 3 clock cycles to cope

with different data/sync phasings, using configura-

tion bits “Syncin_ad” (Reg. 4).

In that case, three behaviors are possible, accor-

ding to the configuration programmed :

- if ‘free-run’ is enabled, the STV0118 carries on

generatingthedigital frameand line syncs(ODD-

EVEN and HSYNC) and generatinganalog video

just as though the expected ‘F’ flag had been

present. However, it will re-synchronize onto the

next ‘F’ flag detected within the incoming

CCIR656/D1 video stream.

- if ‘free-run’ is disabled but the bit ‘sync_ok’ is set in

the configuration registers, the STV0118 sets the

activeportion of theTVline toblacklevel butcarries

onoutputtingtheanalogsynctips(on YsandCVBS)

andthedigitalframeandlinesyncsignalsODDEVEN

andHSYNC.

- if ‘free-run’is disabledandthebit‘sync_ok’is notset,

all analogvideo is at black level and neitheranalog

synctipsnordigital frame/linesync are output.

The SAV and EAV words are Hamming-decoded.

After detectionof two successiveerrors, a bit is set

in the status register to inform the micro-controller

of the poor transmission quality.

IV.5.3 - Synchronization onto Data-embedded

Sync Words

IV.5.3.1 - ‘End-of-frame’ Word Based

Synchronization

IV.5.3.2 - ‘End-of-line’ Word Based

Synchronization

Synchronization is performed by extracting the 1-

to-0 transitions of the ‘F’ flag (end-of-frame) from

the ‘EAV’ (End-of-Active Video) sequence embed-

ded within ITU-R656 / D1 compliant digital video

streams. Both a frame sync signal and a line sync

signal are derived and are made available exter-

nally as ODDEVEN and HSYNC (see Figure 14).

The first successfuldetectionof the ‘F’ flag triggers

generationof theanalogsyncsignalsandencoding

of the incoming video data. Frames being sup-

posed to be of constant duration, the next EAV

wordcontainingthe ‘F’flag is expectedat a precise

Synchronization is performed by extracting the ‘F’

and ‘H’ flags from the ‘SAV’ (Start of Active Video)

and ‘EAV’ (End of Active Video) words embedded

withinITU-R656/D1compliantdigitalvideostreams.

Alinesyncsignalanda framesyncsignalarederived

internally from these flags and are output on the

HSYNC and ODDEVEN/VSYNC pins in output

mode. These signals are also exploited by the core

of thecircuit which treatsthem like it treatsincoming

ODDEVENandHSYNC signalsinHSYNC+ODDEV

based synchronization(see SectionIV.5.1.1).

Figure 14 : Data (EAV) Based Slave Mode Sync Signals

CKREF

YCRCB

FF

00

B6

Cb

Y

EAV

46T_CKREF

1T_CKREFHSYNC Duration : 128T_CKREF

ODDEVEN

(out)

HSYNC

(out)

14/42

STV0118

IV - FUNCTIONAL DESCRIPTION (continued)

IV.6 - Input Demultiplexer

YCrCbstreams for dual encodingapplications.Re-

fer to Section IV.17, “Dual Encoding Application -

54Mbit/s YCrCB interface”.

The incoming 27Mbit/s YCrCb data is demulti-

plexed into a ‘blue-difference’ chroma information

stream, a ‘red-difference’ chroma information

stream and a luma information stream. Incoming

data bits are treated as blue, red or luma samples

according to their relative position with respect to

the sync signals in use and to the content of con-

figuration bits “Syncin_ad” (slave modes) or “Syn-

cout_ad”(master mode).

IV.7 - Sub-carrier Generation

A Direct Digital Frequency Synthesizer (DDFS)

using a 24-bit phase accumulator, generates the

requiredcolor sub-carrierfrequency.This oscillator

feeds a quadraturemodulatorwhich modulatesthe

baseband chrominance components.

The ITU-R601 recommendation defines the black

luma level as Y = 16dec and the maximum white

luma level as Y = 235dec. Similarly it defines 225

quantizationlevels for the color difference compo-

nents (Cr, Cb), centered around 128.

Accordingly, incoming YCrCB samples can be

saturatedin the input multiplexer with the following

rules :

The sub-carrier frequency is obtained from the

following equation :

Fsc = (24-bit Increment Word / 2²⁴) x CKREF

Hard-wired Increment Word values are available

for eachstandard(exceptfor ‘NTSC-4.43’)and can

be automaticallyselected. Alternatively(according

to bit ‘selrst’ in Reg. 2.), the frequency can be fully

customized by programming other values into a

dedicated Increment Word Register (Reg. 10-11-

12). This allows for instance to encode “NTSC-

4.43” or ”PAL-M-4.43”.

- for Cr or Cb samples :

Cr, Cb > 240 Cr, Cb saturated at 240

Cr,Cb < 16

Cr, Cb saturated at 16

- for Y samples :

Y > 235

Y < 16

Y saturated at 235

Y saturated at 16

This is done with the following procedure :

- Program the required increment in Registers 10

to 12

- Set bit ‘selrst’ to ‘1’ in Configuration Register 2

- Perform a software reset (Reg. 6).

Caution : this sets back all bits from Reg. 7

onwards to their default value, when they can be

reset.

This avoids having to heavily saturate the com-

posite video codes before digital-to-analog con-

version in case erroneous or unrealistic YCrCb

samples are input to the encoder (there may

otherwise be overflow errors in the codes driving

the DACs), and therefore avoids genera-ting a

distorded output waveform.

Warning :

if a standard change occurs after the

However, in someapplications, it maybe desirable

to let ‘extreme’ YCrCb codes pass through the

demultiplexer. This is also possible, provided that

bit “maxdyn” is set in configuationregister 6.

softwarereset,theincrement valueis automatically

re-initialized with the hardwired or loaded value

according to bit selrst.

The reset phase of the color sub-carrier can also

be software-controlled (Reg. 13-14).

In this case, only codes 00hex and FFhex are

overridden: if such codes are found in the active

video samples, they are forced to 01hex and FE-

hex.

The sub-carrier phase can be periodically reset to

its nominal value to compensatefor any drift intro-

duced by the finite accuracy of the calculations.

Sub-carrier phase adjustment can be performed

every line, every eight field, every four field, or

every two field (Register 2 bits valrst[1:0]).

In any case, the YCrCb codes are not overridden

for EAV/SAV decoding

The demultiplexer is also able to handle 54Mbit/s

15/42

STV0118

IV - FUNCTIONAL DESCRIPTION (continued)

IV.8 - Burst Insertion

The interpolationfilter compensatesfor thesin(x)/ x

attenuationinherent to D/A conversion and greatly

simplifies the output stage filter (refer to Figures 15

to 17 for characteristic curves).

The color reference burst is inserted so as to

always start with a positive zero crossing of the

subcarrier sine wave. The first and last half-cycles

have a reduced amplitude so that the burst enve-

lope starts and ends smoothly.

The burst contains 9 or 10 sine cycles of

4.43361875MHzor3.579545MHzaccordingto the

standard programmed in the Control Register

(Reg. 0, bits std[1:0]), as follows :

Figure 15 : Luma Filtering Including DAC

Attenuation

0

-5

-10

-15

-20

-25

-30

-35

-40

- NTSC-M

9 cycles of

3.579542MHz

- PAL-BDGHI 10 cycles of 4.43361875MHz

- PAL-M

- PAL-N

9 cycles of

3.57561149MHz

3.5820558MHz

It is possibleto turn theburst off(no burstinsertion)

bysetting configurationbit ‘bursten’to 0 (register2).

Notes : - Two strategies exist for burst insertion: one is to merely

gateand shapethe subcarrier forburstinsertion, the other

is more elaborated and is to always start the burst with a

positive-going zero crossing. In the first case the phase

of the subcarrier when the burst starts is not controlled,

with the consequence that some of its first and last cycles

are more heavily distorded. The second solution

guarantees smoothstartand endof burst witha maximum

of undistorded burst cycles and can only be beneficial to

chroma decoders, it is the solution implemented in the

STV0118.

0

1

2

3

4

5

6

7

8

9

10 11 12 13

Frequency (x10⁶) (Hz)

Figure 16 : Luma Filtering with 3.58MHz Trap,

Including DAC Attenuation

0

-5

- While the first option gave constant burst start time but

uncontrolled initial burst phase, the second solution

guarantees start on a positive-going zero crossing with

the consequence that two burst start locations are visible

over successive lines, according to the line parity. This is

normal and explained below.

- In NTSC, the relation between subcarrier frequency and

line length creates a 180o subcarrier phase difference

(with respect to the horizontal sync) from one line to the

next according to the line parity. So if the burst always

startswith thesame phase (positive-goingzero crossing),

this means the burst will be inserted at time X or at time

X+T_NTSC/2 after the horizontal sync tip according to the

line parity, where T_NTSCis the duration of one cycle of the

NTSC burst.

-10

-15

-20

-25

-30

-35

-40

- With PAL, a similar rationale holds, and again there will

be two possible burst start locations. The subcarrier

phase difference (withrespect tothehorizontal sync) from

one line to the next in that case is either 0 or 180o with

the following series: A-A-B-B-A-A-...-etc. where A

denotes ‘A-type’ bursts and B denotes ‘B-type’ bursts,

A-type and B-type being 180° out of phase with respect

to the horizontal sync. So 2 locations are possible, one

for A-type, the other for B-type (see Figure 8).

- This assumes a periodic reset of the subcarrier is

automatically performed (see bits valrst[1:0] in Reg 2).

Otherwise, over severalframes, the start of burst will drift

within an interval of one a subcarrier’s cycle. THIS IS

NORMAL and means the burst is correctly locked to the

colors encoded. The equivalent effect with a gated burst

approach would be the following : the start location would

be fixed but the phase with which the burst starts (with

respect to the horizontal sync) would be drifting.

0

1

2

3

4

5

6

7

8

9

10 11 12 13

Frequency (x10⁶) (Hz)

Figure 17 : Luma Filtering with 4.43MHz Trap,

Including DAC Attenuation

0

-5

-10

-15

-20

-25

-30

-35

-40

IV.9 - Luminance Encoding

The demultiplexed Y samples are band-limited

and interpolated at CKREF clock rate. The result-

ing luminance signal is properly scaled before

insertion of any Closed-captions, CGMS or

Teletext data and synchronization pulses.

0

1

2

3

4

5

6

7

8

9

10 11 12 13

Frequency (x10⁶) (Hz)

16/42

STV0118

IV - FUNCTIONAL DESCRIPTION (continued)

In addition, the luminance that is added to the

chrominanceto create the compositeCVBS signal

can be trap-filtered at 3.58MHz (NTSC) or

4.43MHz (PAL). This allows to cope with applica-

tion oriented towards low-end TV sets which are

subject to cross-color if the digital source has a

wide luminance bandwidth (e.g. some DVD

sources).Notethat the trapfilterdoes notaffect the

S-VHS luminance output nor the RGB outputs.

A 7.5 IRE pedestal can be programmed if needed

withall standards(seeReg1,bit setup).Thisallows

in particular to encode Argentinian and non-Ar-

gentinian PAL-N, or Japanese NTSC (NTSC with

no set-up).

Note that this function does not suppress the

chrominance on the S-VHS outputs (nevertheless

suppressing the S-VHS chrominance is possible

using bit “bkg_c” in Reg 5).

Figure 18 : Various Chroma Filters Available

+ RGB Filter

1

0

-1

-2

RGB

-3

-4

f₃=2.45

f₃=1.9

-5

A programmable delay can be inserted on the

luminance path to compensate any chroma/luma

delay introduced by off-chip filtering (chroma and

lumatransitionsbeingcoincidentat theDACoutput

with default delay) (Reg3, bits del[2:0]).

f₃=1.6

-6

f₃=1.3

-7

f₃=1.1

-8

-9

0

0.5

1

1.5

2

2.5

3

3.5

Frequency (x10⁶) (Hz)

IV.10 - Chrominance Encoding

U and V chroma components are computed from

demultiplexed Cb, Cr samples. Before modulating

the subcarrier, these are band-limited and interpo-

lated at CKREF clock rate. This processing eases

the filtering following D/A conversion and allows a

more accurate encoding. A set of 4 different filters

is available for chroma filtering to fit a wide variety

of applications in the different standards and in-

cludefilters recommendedby ITU-RRec624-4 and

SMPTE170-M. The available 3dB bandwidths are

1.1, 1.3, 1.6 or 1.9MHz, refer to Figures 18 to 22

for the various frequency responses (Reg1, bits

flt[1:0]).

Figure 19 : 1.1MHz Chroma Filter (flt = 00)

0

-5

-10

-15

-20

-25

-30

-35

-40

The narrowerbandwidthsare usefulagainstcross-

luminanceartefacts,the widerbandwidthsallow to

keep higher chroma contents and then an im-

proved image quality.

0

2

4

6

8

10

12

14

Frequency (x10⁶) (Hz)

Figure 20 : 1.3MHz Chroma Filter (flt = 01)

0

-5

IV.11 - Composite Video Signal Generation

The composite video signal is created by adding

the luminance (after optional trap filtering, Reg 3

bits entrap and trap_pal) and the chrominance

components.Asaturationfunctionis includedin the

adder to avoid overflow errors should extreme

luminance levels be modulated with highly satu-

rated colors (this does not correspond to natural

colors but may be generated by computers or

graphic engines).

-10

-15

-20

-25

-30

-35

-40

A‘color killing’function is available (Reg 1, bit coki)

whereby the composite signal contains no chromi-

nance, i.e. replicates the trap-filtered luminance.

0

2

4

6

8

10

12

14

Frequency (x10⁶) (Hz)

17/42

STV0118

IV - FUNCTIONAL DESCRIPTION (continued)

Figure 21 : 1.6MHz Chroma Filter (flt = 10)

IV.13 - Closed Captioning

Closed-captions (or data from an Extended Data

Service as defined by the Closed-Captions speci-

fication) can be encoded by the circuit. The closed

caption data is delivered to the circuit through the

I²C interface. Two dedicated pairs of bytes (two

bytes per field), each pair preceded by a clock

run-in and a start bit can be encodedand inserted

on the luminance path on a selected TV line. The

Clock Run-In and Start code are generatedby the

STV0118.

0

-5

-10

-15

-20

-25

-30

-35

-40

Closed-caption data registers are double-buffered

so that loading can be performed anytime, even

during line 21/284 or any other selected line.

0

2

4

6

8

10

12

14

Frequency (x10⁶) (Hz)

User register 39 (resp. 41) containsthe firstbyte to

send(LSBfirst)after thestartbit on the appropriate

TVline in field1 (resp.field 2), and user register 40

(resp. 42) contains the second byte to send. The

TV line number where data is to be encoded is

programmble (Reg. 37, 38). Lines that may be

selected include those used by the StarSight data

broadcastsystem. Closed-captionsdata has prior-

ity over CGMS programmed for the same line.

Figure 22 : 1.9MHz Chroma Filter (flt = 11)

0

-5

-10

-15

-20

-25

-30

-35

-40

The internal Clock Run-In generator is based on a

Direct Digital Frequency Synthesizer. The nominal

instantaneousdata rate is 503.5kbit/s(i.e. 32 times

the NTSC line rate). Data LOW correspondsnomi-

nally to 0 IRE, data HIGH correspondsto 50 IRE at

the DAC outputs. Refer to Figure 24.

0

2

4

6

8

10

12

14

Frequency (x10⁶) (Hz)

When closed-captioning is on (bits cc1/cc2 in

Reg.1), the CPU should load the relevant registers

(reg. 39 and 40, or 41 and 42) once everyframe at

most (although there is in fact some margin due to

the double-buffering).Two bits are set in thestatus

register in case of attemptsto loadthe closed-cap-

tion data registers too frequently, these can be

used to regulate loading rate.

IV.12 - RGB Encoding

After demultiplexing, the Cr and Cb samples feed

a 4 times interpolation filter. The resulting base-

band chroma signal has a 2.45MHz bandwidth

(Figure 23) and is combined with the filtered luma

componentto generateR, G, B samplesat 27MHz.

Figure 23 : RGB Chroma Filtering

Figure 24 : Example Closed-caption Waveform

0

-5

300

27.35µs

250

-10

-15

-20

-25

-30

-35

-40

Transition

Time : 220ns

200

10µs

150

100

50

0

13.9µs

7 cycles

of 504kHz

61µs

0

2

4

6

8

10

12

14

Frequency (x10⁶) (Hz)

t

18/42

STV0118

IV - FUNCTIONAL DESCRIPTION (continued)

The closed caption encoder considers that closed

caption data has been loaded and is valid on

completion of the write operation into register 40

forfield1, intoregister42for field2.If closedcaption

encodinghas been enabledandno new databytes

have been written into the closed caption data

registerswhen the closedcaptionwindow startson

theappropriateTV line,then the circuit outputstwo

US-ASCII NULL characterswith oddparityafter the

start bit.

IV.15 - TeletextEncoding

The STV0118is able to encodeTeletext according

to the “CCIR/ITU-R Broadcast Teletext System B”

specification, also known as “World System

Teletext”.

In DVB applications, Teletext data is embedded

withinDVB streams asMPEGdata packets.It isthe

responsibility of a “Transport Layer Processing” IC

(or demultiplexer), like SGS-Thomson’s ST20-

based“TP2”, to sort out incomingdata packetsand

inparticulartostoreTeletextpacketinabuffer,which

then passes them to the STV0118 on request.

IV.14 - CGMS Encoding

IV.15.1 - Signals Exchanged

CGMS (Copy Generation Management System -

also known as VBID and described by standard

CPX-1204 of EIAJ) data can be encoded by the

circuit. Three bytes (20 significant bits) are deliv-

eredtothe chipviatheI2C interface.Two reference

bits (‘1’ then ‘0’) are encoded first, followed by 20

bits of CGMSdata (including a CyclicRedundancy

Check sequence, not computed by the device and

supplied to it as part of the 20 data bits). The

reference bits are generated locally by the

STV0118. Refer to Figure 25 for a typical CGMS

waveform.

The STV0118 and the Teletext buffer exchange 2

signals: TTXS (Teletext Synchronization) going

from the STV0118to theTeletext Buffer and TTXD

(TeletextData) goingfrom the TeletextBufferto the

STV0118.

The TTXS signal is a request signal generated on

selected lines. In response to this signal, the

Teletextbufferis expectedto send360 Teletextbits

to the STV0118 for insertion of a Teletext line into

the analog video signal.

Thedurationof theTTXSwindowis 1402reference

clockperiods(51.926µs), which correspondsto the

duration of 360 Teletext bits (see Transmission

Protocol below).

Following the TTXS rising edge the encoder ex-

pectsdata from the Teletextbuffer aftera program-

mable number (2 to 9) of 27MHz master clock

periods.Datais transmittedsynchronouslywiththe

master clock at an average rate of 6.9375Mbit/s

according to the protocol described below. It con-

sists, in order of transmission, of 16 Clock Run-In

bits, 8 Framing Code bits and the 336 bits (42

bytes) that represent one Teletext packet.

When CGMS encodingis enabled,the CGMS(see

bit encgms in Reg 3) waveform is continously

present once in each field, on lines 20 and 283

(SMPTE-525 line numbering).

The CGMS data register is double-buffered,which

means that it can be loaded anytime (even during

line 20/283) without any risk of corrupting CGMS

data that could be in the process of being en-

coded.The CGMS encoder considers that new

CGMS data has been loaded and is valid on com-

pletion of the write operation into register 33

IV.15.2 - Transmission Protocol

Figure 25 : Example CGMS Waveform

In order to transmit the Teletext data bits at an

average rate of 6.9375Mbit/s, which is about

1/3.89 times the master clock frequency, the follo-

wing scheme is adopted :

300

250

The 360-bit packet is regarded as nine 37-bit se-

quences plus one 27-bit sequence. In every se-

quence, each Teletext data bit is transmitted as a

successionof 4 identicalsamplesat27 Msample/s,

except for the 10th, 19th, 28th and 37th bits of the

sequence which are transmitted as a succession

of 3 identical samples. This protocol is compatible

with SGS-Thomson’s ST-20 based Tranport Layer

IC (“TP2”).

200

11µs

150

48.7µs

100

Word 0

6 bits

Word 2

CRCC

6 bits

Word 1

4 bits 4 bits

50

0

Bit 1

Bit 20

t

19/42

STV0118

IV - FUNCTIONAL DESCRIPTION (continued)

Figure 26 : “TTXS Rising” to “First Valid Sample” Delay for txdl[2:0] = 0

CKREF

TTXS

(txdl[2:0] + 2) T_CKREF

TTXD

Not Valid

Bit 1

Bit 2

IV.15.3 - Programming

quired by the World System Teletext specification.

IV.15.3.1 - ’TTXS Rising’ to ’First Valid

Sample’Delay Programming

Figure 27 : Shape and Amplitude of a Single

Teletext Symbol

TheencoderexpectstheTeletextbufferto clockout

the first Teletext data sample on the (2+N)th rising

edge of the master clock following the rising edge

of TTXS (Figure 26 depicts this graphically for

N=0). ’N’ is programmable from 0 to 7 (i.e. overall

delay is programmable from TWO to NINE 27MHz

cycles) via 3 dedicatedbits located in the Configu-

ration Register4 : “txdl[2:0]”.

70

60

50

40

30

20

IV.15.3.2 - Teletext Line Selection

Five dedicated registers allow to program Teletext

encoding in various areas of the Vertical Blanking

Interval (VBI) of each field. A total of 4 such areas

(i.e. blocks of contiguous Teletext lines) can inde-

pendently be defined within the two VBIs of one

frame(e.g. 2 blocksineachVBI,or3 blocksinfield1

VBI and one in field2 VBI, etc.). Further, under

certain circumstances, it is possible to define up to

4 areas in each VBI.

Programming is performed using 4 “Teletext Block

Definition” registers (TTXBD1, TTXBD2,

TTXBD3,TTXBD4) and a “TeletextBlock Mapping”

register (TTXBM). Refer to the description of user

registers 34 to 38 for details.

10

0

-150

-100

-50

0

(ns)

50

100

150

-144ns

+144ns

Figure 28 : Linear PSD Scale

1

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0

IV.15.4 - TeletextPulse Shape

The shape and amplitude of a singleTeletext pulse

aredepictedin Figure27, itsrelativepowerspectral

density is given in Figures 28 and 29 and is sub-

stantially zero at frequencies above 5MHz, as re-

0

1

2

3

4

5

6

7

8

(x10⁶) (Hz)

20/42

STV0118

IV - FUNCTIONAL DESCRIPTION (continued)

Figure 29 : LogarithmicPSD Scale

After a hardware reset, it is these addresses that

the STV0118 recognizes.

It is possible to modify the default I²C address by

tiing the TTXS/CSI2C pin to logic ‘1’ and validat-

ing the change by writing into a dedicated bit in

Register 6.

In that case, the STV0118 has a new I²C address:

- in write mode : “01000010”(42 hex)

- in read mode : “01000011”(43hex)

Once theI²C addresshas been changed, it cannot

be modifed anymoreuntil thenext hardware reset.

0

-10

-20

-30

-40

-50

-60

-70

-80

Note that these I²C addresses are the same as

those used by the STV0117/STV0117A/STV0119

(others SGS-THOMSON PAL/NTSC Digital En-

coder).

0

1

2

3

4

5

6

7

8

(x10⁶) (Hz)

IV.16 - I²C Bus

It is expected that I²C address changes will nor-

mally be needed for dual encoding applications.

The exact procedure to change the I²C addresses

is detailed below,in the sectionthat dealswith dual

encoding applications.

An external micro-controller controls the STV0118

via anI²C busby writing intoor readingfrom internal

registers. The I²C interface supports the “fast

I²C protocol”(up to 400kHz- andpotentiallymore).

The default I²C addresses of the STV0118 are :

- in write mode : “01000000”(40 hex)

- in read mode : “01000001”(41 hex)

2

Write and read operations are described in Fig-

ures 30 and 31.

≠

Figure 30 : I C Write Operation (default address at power-on, CSI2C ’1’)

SCL

R/W

A7

A6

A5

A4

A3

A2

A1

A0

D7

D6

D5

D4

D3

D2

D1

D0

SDA

I2C Slave Address40h

ACK by

STV0119

Start

LSB Address

Data Byte 1

STV0119

SCL

SDA

D7

D6

D5

D4

D3

D2

D1

D0

D7

D6

D5

D4

D3

D2

D1

D0

D7

D6

D5

D4

D3

D2

D1

D0

ACK by

STV0119

ACK by

Data Byte 2

Data Byte 3

Data Byte n

Stop

STV0119

2

≠

Figure 31 : I C Read Operation (default address at power-on, CSI2C ’1’)

SCL

R/W

A7 A6 A5 A4 A3 A2 A1 A0

SDA

I²C SlaveAddress 40h

ACK by

STV0119

Stop

Start

LSB Address

STV0119

SCL

R/W

D7 D6 D5 D4 D3 D2 D1 D0

SDA

I²C SlaveAddress 41h

ACK by

micro

ACK by

micro

Start

Data Byte 1

Data Byte n

Stop

STV0119

21/42

STV0118

IV - FUNCTIONAL DESCRIPTION (continued)

IV.17 - Dual Encoding Application with 54Mbit/s YCrCb Interface

The STV0118 is able to interface with SGS-

THOMSON’s MPEG decoders capable of supply-

ing a 54-Mbit/s YCrCB multiplex, like the

STi3520M. This multiplex embeds two 27Mbit/s

YCrCb video streams, one with OSD contents and

the other without OSD content (see Figure 32).

Note that the frequency of the reference clock

supplied to the encoder is still 27MHz, only both

edges are used in the interface.

the 1st encoder to ‘0’.

- If Teletext encoding is needed, connect the

TTXS/CSI2C pin of the first encoder to both the

TTXS input pin of the Teletext Buffer / Transport

IC (e.g. SGS-Thomson’s TP2) and a pull-down

resistor (needed for power-on configuration).

- Connect TTXS/CSI2C of the second encoder to

logic ‘1’.

- Before performing any Teletext-related program-

ming, set to ‘1’ bit “chgi2c” in configurationregis-

ter 6.

The MPEG decoder being usually slaved to the

encoder,if two encodersare to be usedin parallel,

one of them must be master and the other must be

slave. Figure 33 shows a typical dual encoding

application (although other applications where two

STV0118’sare slave are possible).

On hardware reset, both encoders have the same

default I²C address (40-41hex). When bit “chgi2c”

toggles to ‘1’, the I²C address of the first encoder

(withTTXS/CSI2C pulledlow) keepsunchangedat

40-41hex, whilst the I²C address of the second

encoder (with TTXS/CSI2C = ‘1’) switches to 42-

43hex and can no more be changed until the next

hardware reset.

It is also necessary to be able to control inde-

pendently the encoders. One solution is to have

two separate I²C busses (one for each encoder)

runningfrom the microcontroller(this is possibleon

SGS-THOMSON’s ST20, which features two I²C

busses),another solution is to change the I²C chip

address of one of the STV0118.

After I²C address change, the second encoder

mustbe programmedto choosetheYCRCbincom-

ing data stream on thefalling edge of CKREF (see

bit ’nosd’ in configurationregister 3).

This can be done with the following procedure :

- If no Teletext is required, tie pin TTXS/ CSI2C of

Figure 32 : 54Mbit/sDual YCRCB Stream

CKREF

(27MHz)

54Mbit/s

YCRCB Stream

Cb_nosdCb_osdY_nosd

Y_osd

Cr_nosdCr_osdY’_nosd

Y’_osdCb_nosdCb_nosd

22/42

STV0118

IV - FUNCTIONAL DESCRIPTION (continued)

Figure 33 : Typical Dual Encoding Application

27MHz

STV0118

(Master)

V_DD

3.3V

ODDEVEN

HSYNC

27MHz

3.3V

V_DD

G/Y

R/C

With OSD

For TV Set

B/CVBS

CVBS

8

54MHz

Interface

Frame Sync

Line Sync

ODDEVEN

HSYNC

SCL

Bit nosd = 0

V_SS

SDA

TTXS/CSI2C

8

3.3V

V

27MHz

YCrCb[7:0]

3.3V 3.3V

MPEG Decoder

(e.g. STi3520M)

54MHz

Digital Video

Data

R_pull-down= 47kΩ

Transport IC

(ST20TP2)

^DDTTXS

V_SS

(Demultiplexer +

CPU + Teletext

Buffer)

SDA

SCL

V_SS

3.3V

STV0118

(Slave)

TTXS/CSI2C

(See Bit chgi2c)

V_SS

SCL

SDA

ODDEVEN

HSYNC

G/Y

R/C

8

54MHz

Interface

Without OSD

For VCR

B/CVBS

CVBS

27MHz

Bit nosd = 1

23/42

STV0118

IV - FUNCTIONAL DESCRIPTION (continued)

IV.18 - Line Skip / Line Insert Capability

These operationscan be repeated until the MPEG

data buffer is inside its fixed limits.

This patented feature of the STV0118 offers the

possibility to cut the cost of the application by

suppressing the need for a VCXO.

It is also possible to use the line skip/repeat capa-

bility in non-interlacedmode.

Ideally, the master clock used on the application

board and fed to the MPEG decoding IC would

haveexactly same frequencyas theclock that was

used when the MPEG data was encoded. Obvi-

ously this is not realistic; up to now a solution

commonlychosenis to dynamicallyadjusttheclock

onthe boardas closeto the‘ideal’clockas possible

with the help of time stamps embedded within the

MPEG stream. Such a kind of tracking often in-

volves the use of a VCXO : when the MPEG data

bufferfills up tomorethan somethresholdthe clock

frequency is increased, when it empties down to

some other threshold the clock frequency is low-

ered.

This functionalityof the STV0118 is also available

in slave mode, in this case the sync signals sup-

plied to the STV0118 must be in accordance with

the modified frame lengthes programmed.

IV.19 - CVBS, S-VHS and RGB Analog Outputs

Four out of six video signals (composite CVBS,

S-VHS(Y/C) and RGB) can bedirected to 4 analog

output pins through 9-bit D/A converters operating

at the reference clock frequency.

The available combinations (see bit ‘rgb_nyc’ in

Reg5) are :

S-VHS (Y/C) + CVBS + CVBS1

or : R, G, B + CVBS1.

The STV0118 offers an alternative, cost-saving

solution: by programming the two bits jump and

dec_ninc in configuration Reg6, the STV0118 is

able to reduce or increase the length of some

frames in a way that will not introduce visible arte-

facts (even if comb-filtering is used). These bits

should be set according to the level of the MPEG

data buffer. Refer to Section VI.2 Register 6,

Register 9 and Registers 21-22-23 for complete

bit description.

A single external analog power supply pair is used

for all DACs, but two independentpairs of current

and voltage references are needed. Each current

referencepin is normally connectedexternallyto a

resistor tied to the analogue ground, whilst each

voltage reference pin is normally connected to a

capacitance tied to the analogue ground.

The internal current sources are independentfrom

the positive supply, thanks to a bangap, and the

consumptionof theDACs is constantwhateverthe

codes converted.

Operation with the STV0118 as sync master is as

follows :

- If the MPEG data buffers fills up too much: set bit

“jump” to ‘1’and bit “dec_ninc”to ‘1’.The STV0118

will reduce the length of the current frame (Bit

“jump” will then automaticallybe reset to ‘0’).

- If the MPEGdata buffersemptiestoomuch:set bit

“jump” to ‘1’ and bit “dec_ninc”to ‘0’.The STV0118

will increase the length of the current frame (Bit

“jump” will then automaticallybe reset to ‘0’).

Any unused DAC may be independentlydisabled

by software, in which case its output is at ‘neutral’

level (blanking for luma and composite outputs,no

color for chroma output, black for RGB outputs).

For applications where a single CVBS output is

required, the RGB/CVBS+S-VHS Triple DAC

should be disabled and Pins I_REF(RGB), VR_RGB

tied to analog power supply.

24/42

STV0118

V - CHARACTERISTICS

V.1 - Absolute Maximum Ratings

Symbol

Parameter

Value

-0.3, 4.0

-0.3, V_DD+ 0.3

2

Unit

V

V_DDx

V_IN

DC Supply Voltage

Digital Input Voltage

Digital Output Voltage

V

V_OUT

I_REF

T_oper

T_stg

V

Analog Input Reference Current

Operating Temperature

Storage Temperature

mA

^oC

mW

0, +70

-40, +150

500

P_tot

Total Power Dissipation

V.2 - Thermal Data

Symbol

Parameter

Value

Unit

R_th(j-a)

DC Junction-Ambient Thermal Resistance

with sample soldered on a PCB

Typ.

76

°C/W

V.3 - DC Electrical Characteristics

T_amb= 25°C/70°C, V_DDA= V_DD= 3.3V, unless otherwise specified

Symbol

Parameter

Test Conditions

Min. Typ. Max. Unit

SUPPLY

V_DDA

V_DD

I_DDA

I_DD

Analog Positive Supply Voltage

Digital Supply Voltage

Analog Current Consumption

Digital Current Consumption

3.0

20

3.3

3.6

50

V

mA

RI_REF=1.2k , R = 200 ,

Ω

L

C_L= 50pF, CKREF = 27MHz,

V_DD= 3.6V autotest mode,

static input signals

20

35

50

DIGITAL INPUTS

V_IL

V_IH

Input Voltage

SCL and SDA

Low level (any other pins)

High level (any other pins)

0.8

V

2.0

4.5

V_DD

Except SCL and SDA

I_L

Input Leakage Current

Input Pins (see note 2)

Bi-directional Pins

V_ILmin or V_IHmax

-10

80

10

µA

C_IN

Input Capacitance

Input Pins

Bi-directional Pins

0.1

5

pF

SDA OUTPUT

V_L

Output Voltage

Low level, I_O= 2mA

0.4

0.6

V

DIGITAL OUTPUT

V_OH

V_OL

Output Voltage

High level (I_OH= -4mA)

Low level (I_OL= 4mA)

2

V

D/A CONVERTER

RI_REF

Resistance for reference Current

Source for 3 D/A Converters

I_REF= V_REF/RI_REF, V_REF= 1.12V typ.

1.2

k

Ω

V_O

Output Voltage Dyn

RI_REF= 1.2kΩ, R_L= 200Ω

(Max. code - Min. Code)

0.95

1.10 V_PP

DAC to DAC V_Omax code (tri-DAC only) RI_REF= 1.2kΩ, R_L= 200Ω

3

%

ILE

DLE

LF Integral Non-linearity

LF Differential Non-linearity

RI_REF= 1.2k , R = 200

1

±

0.5

±

LSB

Ω

L

RI_REF= 1.2k , R = 200

Ω

L

Notes : 1. This product withstands 1.4kV (The MIL883C Norm requires 2.0kV).

This product withstands 150V (The EIAJ Norm requires 200V).

2. The high value for input Pins is due to internal pull-down resistance.

25/42

STV0118

V - CHARACTERISTICS (continued)

V.4 - AC Electrical Characteristics

T_amb= 25°C/70°C, V_DDA= V_DD= 3.3V, unless otherwise specified

Symbol

Parameter

Test Conditions

Min. Typ. Max. Unit

DIGITAL INPUT (YCRCB[7:0], HSYNC, VSYNC/ODDEVEN)

tsu

tho

Input Data Set-up Time

Input Data Hold Time

CKREF rising edge, CKREF = 27MHz

6

3

ns

ACTIVE PERIOD FOR NRESET

tRSTL Input Low Time

REFERENCE CLOCK : CKREF

200

35*

ns

1/tC_REF

tD_REF

tR_REF

tF_REF

Clock Frequency

27

50

MHz

%

Clock Duty Cycle

Clock Rise Time

Clock Fall Time

65*

5

ns

5

ns

I²C CLOCK : SCL

tC_SCL

tD_SCL

tL_SCL

Clock Cycle Time

Clock Duty Cycle

LOW Level Cycle

Rpull_up = 4.7kΩ

2

MHz

%

Rpull_up = 4.7k

250

ns

Ω

DIGITAL OUTPUTS

td_HSYNC

Delay Time

CKREF rising edge

10

ns

CKREF = 27MHz, C_L= 50pF

td_ODDEVEN

CKREF rising edge

CKREF = 27MHz, C_L= 50pF

* In case of double encoding these values must be compatible with the ycrcb transmitter.

26/42

STV0118

VI - REGISTERS

VI.1 - Register Mapping

configuration0

configuration1

configuration2

configuration3

configuration4

R/W 00

R/W 01

R/W 02

R/W 03

R/W 04

std1

blkli

std0

flt1

sync2

flt0

sync1

sync_ok

xxx

sync0

coki

polh

setup

rstosc

del1

polv

cc2

freerun

cc1

nintrl

entrap

enrst

bursten

selrst

del2

valrst1

del0

valrst0

xxx

trap_pal encgms

nosd

syncin

_ad1

syncin

_ad0

syncout

_ad1

syncout

_ad0

aline

txdl2

txdl1

txdl0

configuration5

configuration6

reserved

R/W 05 rgb_nyc bkcvbs1 reserved reserved

bk_ys

xxx

fieldct2

d19

d11

d3

bk_c

xxx

fieldct1

d18

d10

d2

bk_cvbs

chgi2c

xxx

dacinv

maxdyn

xxx

R/W 06 softreset

jump

xxx

atfr

d22

d14

d6

dec_ninc free_jump

xxx 07

xxx 08

xxx

hok

d23

d15

d7

xxx

b2_free

d21

d13

d5

xxx

b1_free

d20

d12

d4

reserved

xxx

status

R

09

fieldct0

d17

d9

jumping

d16

d8

increment_dfs

phase_dfs

reserved

R/W 10

R/W 11

R/W 12

R/W 13

R/W 14

xxx 15

xxx 16

d1

d0

-

o23

o15

xxx

o22

o14

xxx

o21

xxx

0

o20

xxx

1

o19

xxx

1

o18

xxx

1

o17

xxx

0

o16

xxx

1

reserved

S

xxx

chipid

R

17

18

1

revid

0

1

reserved

R/W 19

R/W 20

R/W 21

R/W 22

R/W 23

R/W 31

R/W 32

xxx

ltarg8

ltarg0

lref1

-

xxx

ltarg7

lref8

lref0

-

xxx

ltarg6

lref7

-

xxx

ltarg5

lref6

-

xxx

ltarg4

lref5

-

xxx

ltarg3

lref4

-

xxx

reserved

xxx

line_reg

ltarg2

lref3

-

ltarg1

lref2

-

line_reg

cgms_bit_1-4

cgms_bit_5-12

-

bit1

bit9

bit17

bit2

bit10

bit18

bit3

bit11

bit19

bit4

bit12

bit20

bit5

bit13

bit6

bit14

bit7

bit15

bit8

bit16

cgms_bit_13-20 R/W 33

ttx_block_1_def. R/W 34 ttxbs1.3 ttxbs1.2 ttxbs1.1

ttx_block_2_def. R/W 35 ttxbs2.3 ttxbs2.2 ttxbs2.1

ttx_block_3_def. R/W 36 ttxbs3.3 ttxbs3.2 ttxbs3.1

ttx_block_4_def. R/W 37 ttxbs4.3 ttxbs4.2 ttxbs4.1

ttxbs1.0 ttxbe1.3 ttxbe1.2 ttxbe1.1 ttxbe1.0

ttxbs2.0 ttxbe2.3 ttxbe2.2 ttxbe2.1 ttxbe2.0

ttxbs3.0 ttxbe3.3 ttxbe3.2 ttxbe3.1 ttxbe3.0

ttxbs4.0 ttxbe4.3 ttxbe4.2 ttxbe4.1 ttxbe4.0

ttx_block_map

c.c.c.F1

c.c.c.F2

cclif1

R/W 38 ttxbmf1.1 ttxbmf1.2 ttxbmf1.3 ttxbmf1.4 ttxbmf2.1 ttxbmf2.2 ttxbmf2.3 ttxbmf2.4

R/W 39

R/W 40

R/W 41

R/W 42

R/W 43

R/W 44

xxx 45

opc11

opc12

opc21

opc22

xxx

c117

c127

c217

c227

xxx

c116

c126

c216

c226

xxx

c115

c125

c215

c225

l1_4

l2_4

xxx

c114

c124

c214

c224

l1_3

l2_3

xxx

c113

c123

c213

c223

l1_2

l2_2

xxx

c112

c122

c212

c222

l1_1

l2_1

xxx

c111

c121

c211

c221

l1_0

l2_0

xxx

cclif2

xxx

reserved

...

xxx

...

reserved

xxx 63

xxx

27/42

STV0118

VI - REGISTERS (continued)

VI.2 - Register Contents and Description

(*) = DEFAULT mode when NRESET pin is active (LOW level)

REGISTER_0 - Configuration0

MSB

LSB

freerun

0

Content

Default

std1

1

std0

0

sync2

0

sync1

1

sync0

0

polh

0

polv

1

std[1:0] std1 std0 Standard Selected

0

1

0

1

0

1

PAL BDGHI

PAL N (see bit set-up)

NTSC M

(*)

PAL M

Note 1 : Standard on hardware reset is NTSC; any standard modification selects automatically the right parameters for

correct subcarrier generation.

sync[2:0] sync2 sync1 sync0 Configuration

(referto Functional Description, Sections IV.4 and IV.5)

0

1

0

1

0

1

0

1

0

1

0

1

0

1

ODDEVEN based SLAVE mode (frame locked)

F only based SLAVEmode (frame locked)

ODDEV+HSYNC based SLAVE mode (line locked)

‘F’+’H’ based SLAVE mode (line locked)

VSYNC-only based SLAVE mode (frame locked) (see Note)

VSYNC+HSYNC based SLAVE mode (line locked)

MASTER mode

AUTOTEST mode (color bar pattern)

Caution : In VSYNC-only based slave mode (sync[2:0]=”100”), HSYNC is nevertheless needed as an input.

Refer to Functional Description, Section IV.5.2.2.

polh

polv

Synchro : active edge of HSYNC selection (when input)

or polarity of HSYNC (when output)

(*)

0

1

HSYNC is a negativepulse (128 T_CKREFwide) or falling edge is active

HSYNC is a positive pulse (128 T_CKREFwide) or rising edge is active

Synchro : active edge of ODDEVEN/VSYNC selection (when input)

or polarity of ODDEV (when output) - See Note 2

0

1

Falling edge of ODDEVEN flags start of field1 (odd field) or VSYNC is active low

Rising edge of ODDEVEN flags start of field1 (odd field) or VSYNC is active high

(*)

Note 2 : In master mode : polarity of ODDEVEN output.

In slave by F (from EAV) : polv = 0 (cf D1 encoding) and ODDEVEN polarity is the image of F extracted

from EAV words.

freerun Refer to Functional Description, Section IV.5

0

1

disabled

Enabled

Caution : This bit is taken into account in ODDEV-only, VSYNC-only or ‘F’ based slave modes and is irrelevant to other

synchronization modes.

28/42

STV0118

VI - REGISTERS (continued)

VI.2 - Register Contents and Description (continued)

(*) = DEFAULT mode when NRESET pin is active (LOW level)

REGISTER_1 - Configuration1

MSB

LSB

cc1

0

Content

Default

blkli

0

flt1

1

flt0

0

sync_ok

0

coki

0

setup

1

cc2

0

blkli

VerticalBlankingIntervalselectionfor activevideo linesarea (referto FunctionalDescription,

Section IV.2 and Figures 2 to 7).

(*)

0

1

(‘partial blanking’) Only following lines inside Vertical Interval are blanked

NTSC-M : lines [1..9], [263(half)..272] (525-SMPTE)

PAL-M : lines [523..6], [260(half)..269](525-CCIR)

other PAL: lines [623(half)..5], [311..318](625-CCIR)

This mode allows preservation of VBI data embedded within incoming YCrCb, e.g.

Teletext (lines [7..22] and [320..335]), Wide Screen signalling (full line 23), Video

Programing Service (line16), etc.).

(‘full blanking’) All lines inside VBI are blanked

NTSC-M : lines [1..19], [263(half)..282](525-SMPTE)

PAL-M : lines [523..16],[260(half)..279](525-CCIR)

other PAL: lines [623(half)..22],[311..335](625-CCIR)

Note : blkli must be set to ’0’ when closed captions and are to be encoded on following lines :

- in 525/60 system: before line 20(SMPTE) or before line 283(SMPTE)

- in 625/50 system: before line 23(CCIR) or before line 336(CCIR)

For CGMS and Teletext encodings, blkli value is not taken into account.

flt[1:0]

U/V Chroma filter bandwidth selection

(Refer to Functional Description, Section IV.10 and Figures 4 and 5)

flt1 flt0 3dB Bandwidth Typical Application

0

1

0

1

0

f-3 = 1.1MHz

f-3 = 1.3MHz

f-3 = 1.6MHz

Low definition NTSC filter

Low definition PAL filter

High definition NTSC filter (ATSC compliant)

& PAL M/N (ITU-R 624.4 compliant)

High definitionPALfilter: Rec 624 - 4 for PALBDG/Icompliant

(*)

1

f-3 = 1.9MHz

sync_ok Availability of sync signals (analog and digital) in case of input synchronizationloss with no

free-run active (i.e. freerun=0) (Refer to Functional Description, Section IV.5)

0

1

No synchro output signals

Output synchros available on YS, CVBS and, when applicable, HSYNC (if output port),

ODDEVEN (if output port), i.e same behavior as free-run except that video outputs are

blanked in the active portion of the line

Caution : This bit is taken into account in ODDEV-only, VSYNC-only or‘F’ based slave modes and is irrelevant to other

synchronization modes.

coki

Color killer (Refer to FunctionalDescription, Section IV.11)

(*)

0

1

Color ON

Color suppressedon CVBS(and CVBS1)outputsignal(CVBS=YS) but colorstill present

on C andRGB outputs.ForcolorsuppressiononchromaDAC ‘C’,seeregister5 bitbkg_c.

setup

Pedestal enable (Refer to Functional Description, Section IV.9)

0

Blanking level and black level are identical on all lines

(ex : ArgentinianPAL-N, Japan NTSC-M, PAL-BDGHI)

Black level is 7.5 IRE above blanking level on all lines outside VBI

(ex :Paraguayanand Uruguayan PAL-N)

(*)

1

In all standards, gain factor is adjusted to obtain the required levels for chrominance.

cc2, cc1 Closed caption encoding mode (Refer to Functional Description, Section IV.13)

cc2 cc1 Encoding Mode

0

1

0

1

0

1

No closed caption/extendeddata encoding

Closed caption/extendeddata encoding enabled in field 1 (odd)

Closed caption/extendeddata encoding enabled in field 2 (even)

Closed caption/extendeddata encoding enabled in both fields

29/42

STV0118

VI - REGISTERS (continued)

VI.2 - Register Contents and Description (continued)

(*) = DEFAULT mode when NRESET pin is active (LOW level)

REGISTER_2 - Configuration2

MSB

LSB

valrst0

0

Content

Default

nintrl

0

enrst

0

bursten

1

xxxx

0

selrst

0

rstosc

0

valrst1

0

Refer to Functional Description, Section IV.7.

nintrl

Non-interlaced mode select (Refer to Figures 3, 5 and 7)

(*)

0

1

Interlaced mode (625/50 or 525/60 system)

Non-interlaced mode(2x312/50or 2x262/60 system)

Note : ‘nintrl’ update is internallytaken into account on beginning of next frame.

enrst

Cyclic update of DDFS phase

0

1

No cyclic subcarrier phase reset

Cyclic subcarrier phase reset dependingof valrst1 and valrst0 (see below)

bursten

selrst

Chrominance burst control

0

1

Burst is turned off on CVBS (and CVBS1), C and RGB outputs are not affected

Burst is enabled

(*)

Selects set of reset values for Direct Digital Frequency Synthesizer

0

Hardware reset values for phase and increment of subcarrier oscillator

(see description of registers 10 to 14 for values)

1

I²C loaded reset values selected (see contents of Registers 10 to 14)

rstosc

Software phase reset of DDFS (Direct Digital FrequencySynthesizer)

(*)

0

1

inactive

a 0-to-1 transition resets the phase of the subcarrier to either the hard-wired default

phase value or the value loaded in Register 13-14 (according to bit ‘selrst’)

Note : Bit ‘rstosc’ is automatically set back to ‘0’ after the oscillator reset has been performed.

valrst[1:0] Note : valrst[1:0] is taken into account only if bit ‘enrst’ is set

valrst1 valrst0 Selection

0

1

0

1

0

1

Automatic reset of the oscillator every line

Automatic reset of the oscillator every 2nd field

Automatic reset of the oscillator every 4th field

Automatic reset of the oscillator every 8th field

Resettingthe oscillatormeans here forcingthe valueof theaccumulatorphaseto its nominal valueto avoid

accumulating errors due to the finite number of bits used internally. The value to which the accumulatoris

reset is either the hard-wired default phase value or the value loaded in Register 13-14 (according to bit

‘selrst’), to which a 0°, 90°, 180°, or 270°correction is applied according to the field and line on which the

reset is performed.

30/42

STV0118

VI - REGISTERS (continued)

VI.2 - Register Contents and Description (continued)

(*) = DEFAULT mode when NRESET pin is active (LOW level)

REGISTER_3 - Configuration3

MSB

LSB

xxx

0

Content

Default

entrap

0

trap_pal

0

encgms

0

nosd

0

del2

0

del1

0

del0

0

entrap

Enable trap filter

(*)

0

1

Trap filter disabled

Trap filter enabled

trap_pal Refer to Functional Description, Section IV.9

Note : ‘trap_pal’is taken into account only if bit ‘entrap’is set.

(*)

0

1

To select the NTSC trap filter (centered around 3.58MHz)(see Figure 16)

To select the PAL trap filter (centered around 4.43MHz) (see Figure 17)

encgms CGMS encoding enable (Refer to FunctionalDescription, Section IV.14)

0

1

Disabled

Enabled

Note : When encgms is set to 1 Closed-Captions/Extended Data Services should not be programmed on lines 20 and

283 (525/60, SMPTE line number convention).

nosd

Choice of active edge of ‘ckref’ (master clock) that samples incoming YCrCb data (Refer to

Functional Description, Section IV.17).

(*)

0

1

‘ckref’ rising edge (e.g. data with OSD coming from STi3520M)

‘ckref’ falling edge (e.g. data without OSD coming from STi3520M)

Note : Typically, this bit is used when two STV0118’s are used in a ‘dual encoding’configuration.

del[2:0] Delay on luma path with reference to chroma path

(Refer to Functional Description, Section IV.9)

del2 del1 del0 Delay on luma path with reference to chroma path

(one pixel corresponds to 1/13.5MHz(74.04ns))

0

1

0

1

0

1

0

1

0

+ 2 pixel delay on luma

+ 1 pixel delay on luma

+ 0 pixel delay on luma

- 1 pixel delay on luma

- 2 pixel delay on luma

+ 0 pixel delay on luma

(*)

1

Other

31/42

STV0118

VI - REGISTERS (continued)

VI.2 - Register Contents and Description (continued)

(*) = DEFAULT mode when NRESET pin is active (LOW level)

REGISTER_4 - Configuration4

MSB

LSB

txdl0

0

Content

Default

syncin_ad1

0

syncin_ad0 syncout_ad1 syncout_ad0

aline

0

txdl2

0

txdl1

0

syncin_ad Adjustmentof incoming sync signals (Refer to Functional Description, Section IV.5).

Used to insure correct interpretation of incoming video samples as Y, Cr or Cb when the

encoderis slavedto incomingsyncsignals(incl. ‘F/H’flagsstrippedoffITU-R656/D1data).

syncin_ad1

syncin_ad0

Internal delay undergone by incoming sync

(*)

0

1

0

1

0

1

Nominal

+1 ckref

+2 ckref

+3 ckref

syncout_ad Adjustmentof outgoing sync signals (Refer to FunctionalDescription, SectionIV.4).

Used to insure correct interpretationof incoming video samples as Y, Cr or Cb whenthe

encoder is master and supplies sync signals.

syncout_ad1 syncout_ad0 Delay added to sync signals before they are output

(*)

0

1

0

1

0

1

Nominal

+1 ckref

+2 ckref

+3 ckref

aline

Video active line duration control(Refer to FunctionalDescription, Section IV.2)

0

1

Full digital video line encoding (720 pixels - 1440 clock cycles)

Active line duration follows ITU-R/SMPTE ‘analog’ standard requirements

txdl[2:0]

Teletext data latency (* “000” default) (Refer to Functional Description, Section IV.15)

The encoder will clock in the first Teletext data sample on the (2+txdl[2:0]) rising edge

th

of the master clock following the rising edge of TTXS (Teletext Synchro signal, supplied

by the encoder).

32/42

STV0118

VI - REGISTERS (continued)

VI.2 - Register Contents and Description (continued)

(*) = DEFAULT mode when NRESET pin is active (LOW level)

REGISTER_5 - Configuration5

MSB

LSB

dacinv

0

Content

Default

rgb_nyc

0

bkcvbs1

0

reserved

1

reserved

1

bk_ys

0

bk_c

0

bk_cvbs

0

rgb_nyc Selection between RGB or S-VHS/CVBS outputs present on DACs

(refer to Functional Description, Section IV.12)

(*)

0

1

Y - C - CVBS - CVBS1 on DACs

R - G - B - CVBS1 on DACs

bkcvbs1 Blanking of DAC CVBS

0

1

DAC CVBS in normal operation

DAC input code forced to blanking level

bk_ys

bk_c

Blanking of DAC G/Y’

0

1

DAC G/Y in normal operation

DAC input code forced to black level (if G) or blanking level (if Y)

Blanking of DAC ‘R/C’

0

1

DAC R/C in normal operation

DAC input code forced to black level (if R) or neutrallevel [no color] (if C)

bk_cvbs Blanking of DAC ‘B/CVBS’

0

1

DAC B/CVBS in normal operation

DAC input code forced to black level (if B) or blanking level (if CVBS)

dacinv

‘Inverts’ DAC codes to compensatefor an inverting output stage in the application

0

1

DAC non inverted inputs

DAC inverted inputs

33/42

STV0118

VI - REGISTERS (continued)

VI.2 - Register Contents and Description (continued)

(*) = DEFAULT mode when NRESET pin is active (LOW level)

REGISTER_6 - Configuration6

MSB

LSB

maxdyn

0

Content

Default

softreset

0

jump

0

dec_ninc

0

free_jump

1

xxxx

0

xxxx

0

chgi2c

0

softreset Software reset

(*)

0

1

No reset

Software reset

Note : Bit ‘softreset’ is automatically reset after internal reset generation.

Software reset is active during 4 CKREF periods. When softreset is activated, all the device is reset as with

hardware reset except for the first six user registers (configurations) and for registers 10 up to 14

(increment and phase of oscillator), 31-33, 34-37 and 39-42.

jump, dec_ninc, free_jump

jump dec_ninc free_jump

0

Normal mode (no line skip/insert capability)

CCIR : 313/312 or 263/262

non-interlaced : 312/312 or 262/262

0

x

1

Manual mode for line insert (“dec_ninc” = 0) or skip

(“dec_ninc” = 1) capability.

Both fields of all the frames following the I²C writing are

modifiedaccordingto “lref”and “ltarg”bits of registers21-22-23

(bydefault, “lref”= 0 and“ltarg”= 1 whichleads to normalmode

above).

1

0

1

x

0

1

Automatic line insert mode.

The 2^ndfield of the frame following the I²C writing is increased.

Lineinsertionis done afterline 245 in 525/60 and afterline 330

in 625/50. “lref” and “ltarg” bits are ignored.

Automatic line skip mode.

The2^ndfieldof the framefollowingthe I²C writtingis decreased.

Line suppression is done after line 245 in 525/60 and after

line 330 in 625/50. “lref” and “ltarg” bits are ignored.

Not be used

1

Notes :

- Refer to Functional Description (Section IV.18)

- bit “jump” is automatically reset after use.

chgi2c

Chip address selection

(*)

0

1

Chip address : write = 40hex ; read = 41hex

Chip address : write = 42hex; read = 43hex

Note : Setting this bit to 1 changes the chip address provided that pin ttxs/csi2c is tied to Vdd when the 0-to-1

transition occurs. Refer to sections IV.16 and IV.17. The new address is valid until the next hardware reset.

maxdyn Max dynamic magnitude allowed on YCrCb inputs for encoding

(Refer to Functional Description, Section IV.6).

0

1

10hex to EBhex for Y, 10hex to E0hex for chrominance (Cr,Cb)

01hex to FEhex for Y, Cr and Cb

Note : In any case, EAV and SAV words are replaced by blanking values before being fed to the luminance and

chrominace processings

REGISTER_7 and 8 : Reserved

34/42

STV0118

VI - REGISTERS (continued)

VI.2 - Register Contents and Description (continued)

(*) = DEFAULT mode when NRESET pin is active (LOW level)

REGISTER_9 - Status (read only)

MSB

LSB

Content

hok

atfr

buf2_free

buf1_free

fieldct2

fieldct1

fieldct0

jumping

hok

Hamming decoding of frame sync flag embedded within ITU-R656/D1 compliant YCrCb

streams.

0

1

Consecutive errors

A single or no error

(*)

Note : signal quality detector is issued from Hamming decoding of EAV,SAVfrom YCrCb

atfr

Frame synchronization flag (slave mode only)

(*)

0

1

Encoder not synchronized

Encoder synchronized

buf2_free Closed caption registers access condition for field 2

(refer to Functional Description, Section IV.13)

Closed caption data for field 2 is buffered before being output on the relevant TV line;

buf2_free is reset if the buffer is temporarily unavailable. If the microcontroller can

guaranteethat registers41 and 42 (cccf2) are never written more than once betweentwo

frame reference signals, then bit ‘buf2_free’ will always be true (set). Otherwise, closed

caption field2 registers access might be temporarilyforbidden by resetting bit ‘buf2_free’

until the next field2 closed caption line occurs.

Note that this bit is false (reset) when 2 pairs of data bytes are awaiting to be encoded,

and is set back immediately after one of these pairs has been encoded (so at that

time,encoding of the last pair of bytes is still pending)

(*)

Reset value = 1 (access authorized)

buf1_free Closed caption registers access condition for field 1

Same as buf2_free but concerns field 1.

Reset value = 1 (access authorized)

fieldct[2:0] Digital field identification number

000 Indicates field 1

...

111 Indicates field 8

fieldct[0] also representsthe odd/even information (odd=’0’, even=’1’)

jumping

Indicates whether a frame length modification has been programmed at ‘1’ from

programming of bit ‘jump’ to end of frame(s) concerned.

Default = 0

(*)

Refer to register 6 and registers 21-22-23.

35/42

STV0118

VI - REGISTERS (continued)

VI.2 - Register Contents and Description (continued)

(*) = DEFAULT mode when NRESET pin is active (LOW level)

REGISTERS_10_11_12- Increment_dfs: Increment for digital frequency synthesizer

MSB

LSB

d16

d8

register_10

register_11

register_12

d23

d15

d7

d22

d14

d6

d21

d13

d5

d20

d12

d4

d19

d11

d3

d18

d10

d2

d17

d9

d1

d0

These registers contain the 24-bit increment used by the DDFS if bit ‘selrst’ equals ‘1’ to generate the

frequencyof thesubcarrieri.e. theaddressthat is suppliedtothe sineROM. It thereforeallowsto customize

the subcarrier frequencysynthesized. Refer to Functional Description, Section IV.7.

1 LSB ~ 1.6 Hz

The procedure to validate usage of these registers instead of the hard-wired values is the following :

- Load the registers with the required value

- Set bit ‘selrst’ to 1 (Reg 2)

- Perform a softwarereset (Reg 6)

Notes : The values loaded in Reg10-11-12 are taken into account after a software reset, and ONLY IF bit

‘selrst’=’1’ (Reg. 2)

These registers are never reset and must be explicitly written into to contain sensible information.

On hardware reset (=> ‘selrst’=0) or on soft reset with selrst=’0’, the DDFS is initalized with a

hardwired increment, independent of Registers 10-12. These hardwired values being out of any

user register these cannot be read out of the STV0118.

These values are :

Value

Frequency Synthesized

f = 3.5795452MHz

f = 4.43361875MHz

f = 3.5820558MHz

f = 3.57561149MHz

Ref.Clock

27MHz

d[23:0] : 21F07C hexa for NTSC M (*)

d[23:0] : 2A098B hexa for PAL BGHIN

d[23:0] : 21F694 hexa for PAL N

d[23:0] : 21E6F0 hexa for PAL M

‘NTSC-4.43’can be obtained with d[23:0]value likefor PALBGHI but with standardfixed as NTSC.

REGISTERS_13_14 - Phase_dfs : Static phase offset for digital frequencysynthesizer(10 bits only)

MSB

-

LSB

o22

o14

register_13

register_14

-

o23

o15

o21

o20

o19

o18

o17

o16

Under certaincircumstances (detailed below), these registerscontain the 10 MSBsof the value with which

the phase accumulator of the DDFS is initialized after a 0-to-1 transition of bit ‘rstosc’ (Reg 2), or after a

standardchange, or when cyclic phase readjustment has been programmed(see bits valrst[1:0]of Reg 2).

The 14 remaining LSBs loaded into the accumulator in these cases are all ‘0’s (this allows to define the

phase reset value with a 0.35°accuracy).

The procedure to validate usage of these registers instead of the hard-wired values is the following :

- Load the registers with the required value

- Set bit ‘selrst’ to 1 (Reg 2)

- Perform a softwarereset (Reg 6)

Notes : Registers 13-14 are never reset and must be explicitly written into to contain sensible information.

If bit ‘selrst’=0 (e.g. after a hardware reset) the phase offset used to reinitialize the DDFS is the

hard-wired value. The hard-wired values being out of any register, they cannot be read out of the

STV0118.

These are :

- D9C000hexfor PAL BDGHI, N, M

- 1FC000hexfor NTSC-M

36/42

STV0118

VI - REGISTERS (continued)

VI.2 - Register Contents and Description (continued)

(*) = DEFAULT mode when NRESET pin is active (LOW level)

REGISTER_15 : Reserved

REGISTER_16 : Reserved

REGISTER_17 : chipID

(read only) : STV0118 Identification Number

0 1 1 1 0 1 1 0 (codes 118 in binary format)

REGISTER_18 : revID

(read only) : STV0118Revision Number

0 0 0 0 0 0 0 1 (for first revision)

REGISTER_19 : Reserved

REGISTER_20 : Reserved

REGISTERS_21_22_23: line_reg= ltarg[8:0] and lref[8:0]

MSB

LSB

ltarg1

lref2

-

register_21

register_22

register_23

ltarg8

ltarg0

lref1

ltarg7

lref8

lref0

ltarg6

lref7

-

ltarg5

lref6

-

ltarg4

lref5

-

ltarg3

lref4

-

ltarg2

lref3

-

These registers may be used to jump from a reference line (end of that line) to the beginning of a target

line of the SAME FIELD.

However, not all lines can be skipped or repeated with no problem and, if needed,this functionality has to

BE USED WITH CAUTION.

lref[8:0] contains in binary format the reference line from which a jump is required. ltarg[8:0] contains the

target line binary number.

Default values: lref[8:0] = 000000000and ltarg[8:0] = 000000001

REGISTER_31-32-33- cgms_bit[1:20]: CGMS Data registers (20 bits only)

MSB

-

LSB

b4

register_31

register_32

register_33

-

b1

b9

b2

b3

b5

b6

b7

b8

b10

b18

b11

b19

b12

b20

b13

b14

b15

b16

b17

These registers are never reset.

Word0A=> bit1....bit3

Word0B => bit4....bit6

Word1 => bit7....bit10

Word2 => bit11....bit14

CRC => bit15...bit20(not internally computed)

Refer to Functional Description, Section IV.14

37/42

STV0118

VI - REGISTERS (continued)

VI.2 - Register Contents and Description (continued)

(*) = DEFAULT mode when NRESET pin is active (LOW level)

REGISTER_34-35-36-37- ttx_block_[1:4]_def. : TeletextBlock Definition

(Refer to Functional Description, Section IV.15)

MSB

LSB

register_34 txbd1

register_35 txbd2

register_36 txbd3

register_37 txbd4

txbs1.3

txbs2.3

txbs3.3

txbs4.3

txbs1.2

txbs2.2

txbs3.2

txbs4.2

txbs1.1

txbs2.1

txbs3.1

txbs4.1

txbs1.0

txbs2.0

txbs3.0

txbs4.0

txbe1.3

txbe2.3

txbe3.3

txbe4.3

txbe1.2

txbe2.2

txbe3.2

txbe4.2

txbe1.1

txbe2.1

txbe3.1

txbe4.1

txbe1.0

txbe2.0

txbe3.0

txbe4.0

Theseare four TeletextBlockDefinitionregisters, usedin conjunctionwithReg38 (TeletextBlock Mapping).

Each of these registers defines a start line (TXBSx[3:0]) and an end line (TXBEx[3:0]). [TXBSx = Teletext

Block Start for block x, TXBEx = Teletext Block End for block x]

When applying to field1:

When applying to field2:

(ITU-R601/625 line numbering)

TXBSx[3:0]=0 codes line 7,

...

TXBSx[3:0]=i codes line 7+i,

...

TXBSx[3:0]=15dec(‘1111’bin) codes line 7+15=22

TXBSx[3:0]=0 codes line 320,

...

TXBSx[3:0]=i codes line 320+i,

...

TXBSx[3:0]=15dec(‘1111’bin) codes line 320+15=335

DEFAULT value: none, registers 34-37 are never reset.

REGISTER_38 - ttx_block_map : Teletext Block Mapping

MSB

LSB

register_38

txmf1.1

txmf1.2

txmf1.3

txmf1.4

txmf2.1

txmf2.2

txmf2.3

txmf2.4

(txmf1 stands for ’Teletext Block Mapping to field1, txmf2 stands for ’Teletext Block Mapping to field2)

This register allows to map the blocks of Teletext lines defined by registers 34 to 37 to either field1, field2

or both :

Its default value is “00000000”

txmf1.N defines whether txbdN (Nth teletext block, see reg34-37 above) applies to field 1,

txmf2.N defines whether txbdN (Nth teletext block, see reg34-37 above) applies to field 2.

In other words, if txmf1.N=1 then Teletext will be encoded in field 1 from the line defined by txbsN.[3:0]

(see above) to the line defined by txbeN.[3:0].

Similarly, if txmf2.N=1 then Teletext will be encoded in field 2 from the line definedtxbsN.[3:0] (see above)

to the line defined by txbeN.[3:0].

38/42

STV0118

VI - REGISTERS (continued)

VI.2 - Register Contents and Description (continued)

(*) = DEFAULT mode when NRESET pin is active (LOW level)

REGISTER_39-40 - cccf1 : Closed caption characters/extendeddata for field 1

First byte to encode in field1 :

MSB

LSB

register_39

opc11

c117

c116

c115

c114

c113

c112

c122

c111

opc11

Odd-parity bit of US-ASCII 7-bit character c11[7:1]

Second byte to encode in field1:

MSB

LSB

register_40

opc12

c127

c126

c125

c124

c123

c121

opc12

Odd-parity bit of US-ASCII 7-bit character c12[7:1]

Default value : none, but closed captions enabling without loading these registers will

issue character NULL. Registers 39-40 are never reset.

REGISTER_41-42 : cccf2 : Closed caption characters/extendeddata for field 2

First byte to encode in filed2 :

MSB

LSB

register_41

opc21

c217

c216

c215

c214

c213

c223

c212

c211

opc21

Odd-parity bit of US-ASCII 7-bit character c21[7:1]

Second byte to encode in field2 :

MSB

LSB

register_42

opc22

c227

c226

c225

c224

c222

c221

opc22

Odd-parity bit of US-ASCII 7-bit character c22[7:1]

Default value : none but closed captions enabling without loading these registers will

issue character NULL. Registers 41-42 are never reset.

REGISTER_43 - cclif1 : Closed caption/extended data line insertion for field 1

TV line number where closed caption/extendeddata is to be encoded in field 1 is programmable through

the following register :

MSB

xxxx

0

LSB

l1_0

1

register_43

Default

xxxx

0

xxxx

0

l1_4

0

l1_3

1

l1_2

1

l1_1

1

- 525/60 system : (525-SMPTE line number convention)

Only lines 10 through 22 should be used for closed caption or extendeddata services (line 1 through 9

contain the vertical sync pulses with equalizing pulses).

l1[4:0] = 00000 no line selected for closed caption encoding

l1[4:0] = 000xx do not use these codes

...

l1[4:0] = i code line (i+6) (SMPTE) selected for encoding

...

l1[4:0] = 11111 line 37 (SMPTE) selected

- 625/50 system: (625-CCIR/ITU-R line number convention)

Only lines 7 through 23 should be used for closed caption or extended data services.

l1[4:0] = 00000 no line selected for closed caption encoding

...

l1[4:0] = i code line (i+6) (CCIR) selected for encoding (i > 0)

...

l1[4:0] = 11111 line 37 (CCIR) selected

(*) Default value = 01111line 21 (525/60, 525-SMPTE line number convention).

This value also corresponds to line 21 in 625/50 system,(625-CCIR line number convention).

39/42

STV0118

VI - REGISTERS (continued)

VI.2 - Register Contents and Description (continued)

(*) = DEFAULT mode when NRESET pin is active (LOW level)

REGISTER_44 - cclif2 : Closed caption/extended data line insertion for field 2

TV line number where closed caption/extendeddata is to be encoded in field 2 is programmable through

the following register :

MSB

xxxx

0

LSB

I2_0

1

register_44

Default

xxxx

0

xxxx

0

I2_4

0

I2_3

1

I2_2

1

I2_1

1

- 525/60 system : (525-SMPTE line number convention)

Only lines 273 through284 should be used for closed caption or extendeddata services (preceding lines

contain the vertical sync pulses with equalizing pulses), although it is possible to program over a wider

range.

l2[4:0] = 00000 no line selected for closed caption encoding

l2[4:0] = 000xx do not use these codes

l2[4:0] = i line (269 +i) (SMPTE) selected for encoding

...

l2[4:0] = 01111 line 284 (SMPTE) selected for encoding

l2[4:0] = 11111 line 300 (SMPTE)

Note : if cgms is allowed on lines 20 and 283 (525/60, 525-SMPTE line number convention), closed

captions should not be programmed on these lines.

- 625/50 system : (625-CCIR line number convention)

Only lines 319 through336 should be used for closed caption or extendeddata services (preceding lines

contain the vertical sync pulses with equalizing pulses), although it is possible to program over a wider

range.

l2[4:0] = 00000 no line selected for closed caption encoding (i > 0)

l2[4:0] = i line (318 +i) (CCIR) selected for encoding

...

l2[4:0] = 10010 line 336 (CCIR) selected for encoding

l2[4:0] = 11111 line 349 (CCIR)

(*) Default value = 01111line 284 (525/60, 525-SMPTE line number convention).

This value also corresponds to line 333 in 625/50 system, (625-CCIR line number convention).

REGISTERS_45 up to 63 :

Reserved

40/42

STV0118

VII - APPLICATION

Figure 34 : Typical Application

Ω 2 0

Ω 7 5

Ω

8 2 0

Ω

2 . 2 k

Ω

4 . 7 k

Ω 0 2 0

T E L E T E X T

I D A T C R 9 - B I T

C H S W I T

P L E X E R D E M U L T I

D E C O D M E P R E G

41/42

STV0118

VIII - PACKAGE MECHANICAL DATA

28 PINS - PLASTICMICROPACKAGE (SO)

Millimeters

Dimensions

Inches

Typ.

Min.

Typ.

Max.

2.65

0.2

Min.

Max.

0.104

0.0078

0.019

0.013

A

a1

b

0.1

0.004

0.014

0.009

0.35

0.23

0.49

0.32

b1

C

c1

D

E

0.5

0.020

45^o(Typ.)

17.7

10

18.1

0.697

0.394

0.713

0.419

10.65

e

1.27

0.050

0.65

e3

F

16.51

7.4

0.4

7.6

0.291

0.016

0.299

0.050

L

1.27

S

8^o(Max.)

Information furnishedis believed to be accurate and reliable.However, SGS-THOMSON Microelectronics assumes no responsibility

for the consequences of use of such information nor for any infringement of patentsor other rights of third parties which may result

from itsuse. No licence is grantedby implication orotherwise underany patent or patent rights of SGS-THOMSON Microelectronics.

Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all

information previouslysupplied. SGS-THOMSON Microelectronics products are not authorized for use as criticalcomponents in life

support devices or systems without express written approval of SGS-THOMSON Microelectronics.

Purchase of I²C Components of SGS-THOMSON Microelectronics, conveys a license under the Philips

I²C Patent. Rights to use these components in a I²C system, is granted provided that the system conforms to

the I²C Standard Specifications as defined by Philips.

SGS-THOMSON Microelectronics GROUP OF COMPANIES

Australia - Brazil - Canada - China - France - Germany - Hong Kong - Italy - Japan - Korea - Malaysia - Malta - Morocco

The Netherlands - Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A.

42/42


型号：	STV0118
厂家：	ST
描述：	PAL/NTSC HIGH PERFORMANCE DIGITAL ENCODER PAL / NTSC制式高性能数字编码器转换器色度信号转换器消费电路商用集成电路光电二极管编码器
文件：	总42页 (文件大小：387K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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