STV0684_技术文档

STV0684

Digital Camera Processor

PRODUCT PREVIEW

■ Versatile mass storage interface

Features

● Support Compact-flash, Nand-on-board,

Smartmedia, Secure Digital and Multi-Media

■ Supports the VC6700 CMOS sensor (UXGA,

1600 x 1200 pixels) from STMicroelectronics

■ USB 2.0 full speed device

■ High quality video processor

● RAM based firmware

● USB audio and video class compliant

● USB mass storage class compliant, Bulk only

transfer protocol

● Pixel defect correction

● NORA (Noise Reduction Algorithm

● Anti-vignetting algorithm

■ JPEG and MJPEG CODEC

● Advanced statistics processor

● Two general purpose scalers

Description

The STV0684 processor is targeted for use in

CMOS digital still cameras. ST supplies complete

camera reference designs which include sensor,

co-processor, firmware and software drivers. The

STV0684 uses a small BGA package (12 mm x 12

mm) ideal for the design of very small digital

cameras. The STV0684 incorporates ST’s unique

and highly performing video processor algorithms

including newly improved and patented algorithms

(e.g. NORA and Anti-vignetting).

● Dual video interface for concurrent viewfinder

and movie capture

■ ST20 32-bit core

● Instruction, data cache and embedded

memory for fast code execution

● Embedded ROM bootloader for code storage

in cost effective NAND flash memory

● Code executed in SDRAM, no code-size

limitation

The CMOS sensors from STMicroelectronics use

pinned photodiodes manufactured in a high

performance process resulting in improved low light

performance, reducing the gap with CCD sensors.

■ AVI (Audio Video Interleave) clips directly

recorded into the mass storage media

● Long clip length

● Low power consumption

Applications

■ Flexible TFT, D-TFD digital interface for

●

Digital still cameras

preview (while recording) and review

Solid state video camera recorders

Embedded cameras

● Direct support for Casio, Epson and AU

optronics displays

● Flexible digital interface designed to support

future digital panels

Ordering Information

■ PAL and NTSC encoder with on-chip digital

Part Number

Temperature

Package

to analog converter

STV0684

[0; +70 ] °C

BGA196

● TV display of pictures and movie clips

■ On-chip 16-bit Sigma-Delta analog to digital

converter for audio record

■ Audio digital to analog converter for audio

playback

Rev. 1

March 2005

1/49

This is preliminary information on a new product now in development. Details are subject to change without notice.

STV0684

Technical Specifications

Resolution

UXGA - VC6700V048

Sample rate

Power supply

Power requirements

Package

up to 48 M sample/s (MSPS)

3.3V and 1.8V

mA typical

BGA196, 12x12 mm

System Overview

Figure 1: STV0684 system overview

SCALER 1

SCALER 2

USB

Interface

VP

CODEC

ST20

CORE

Audio

Interface

STV0684

TV

Boot

interface

HW ECC

NAND

interface

LCD

controller

DRAM

Interface

NAND

SDRAM

2/49

STV0684

Table of Contents

Chapter 1

Chapter 2

Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5

Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6

Chapter 3

Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14

Video processor (VP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

ST20-C103 core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

SFP module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

USB interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Memory interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

3.1

3.2

3.3

3.4

3.5

3.6

Audio interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Audio record . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Audio playback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

3.6.1

3.6.2

3.7

3.8

3.9

3.10

TV interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

LCD controller - Display interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

JPEG CODEC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Other interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

3.10.1 SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

3.10.2 I2C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

3.10.3 Comparator for low battery detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Chapter 4

Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

4.1

4.2

4.3

4.4

4.5

AC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

SFP AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Audio ADC electrical parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

AC electrical characteristics of USB transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

SDRAM timing description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

I2C timing description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

SPI timing description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

NAND timing description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

4.5.1

4.5.2

4.5.3

4.5.4

4.5.5

4.5.6

4.5.7

3/49

STV0684

4.5.8

4.5.9

AC characteristics for NAND flash operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Compact flash timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

4.5.10 TFT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

4.5.11 TV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

4.5.12 Sensor interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

4.6

ESD handling characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

4.7

External circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Crystal oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Audio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Recommended power supply decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

4.7.1

4.7.2

4.7.3

Chapter 5

Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45

STV0684 pin assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

STV0684 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

5.1

5.2

4/49

STV0684

Functional Block Diagram

1

Functional Block Diagram

Figure 2: STV0684 functional block diagram

DMA

FIFO

DMA

RAM

I2C

CF

SPI

FLASH

ILC

VP

JPEG

ENCODE

T1

sensor

ST20

core

VDFIF

T2

JPEG

DECODE

LCD

TV

LCDC

TVC

Boot

ROM

Dot

selector

Audio

fifo

AUDIO

ADC

DMA

RAM

DMA

FIFO

PWM

fifo

AUDIO

USBIFO

ISO

usb

BLKOUT

BLKIN

NAND

CF

I2C

SPI

5/49

Signal Description

STV0684

2

Signal Description

Figure 3: Signals identified by functional group

STV0684

XTLI

XTLO

PLL and

Clock:

Power Inputs:

Core

5

VDDC

10

VDDI

VDDP

I/O

VC

AP

AN

CBS

Audio

Master PLL

Audio

VDDA

VDDAP

TV_VDDA

Audio PLL

TV

RESET

WAKEUP

Interrupt/

Control

DP

Grounds:

USB

Interface

15

DN

VSS

VSSP

VSSA

VSSAP

Common

USB_DET

Master PLL

Audio

CVBS

TV

Interface

Audio PLL

TV

TV_REXT

TV_GNDA_REXT

TV_VSSA

VREF

LOW_BATT

Low

Battery

Sensor interface

SCLK

SPCLK

SSDA

5

ST Micro connect

ST Micro

connect

Debug

SSCL

133

Special Function Pins (SFP)

2

ST Micro connect

SDRAM

ST Micro

connect

Debug

Sensor interface

HSYNC

VSYNC

SDATA[9:0]

10

38

4

SDRAM

Graphics

display

17

28

Graphics display

E-Warp

debugger

E-Warp

debug

CF/

NAND/

SMC

CF/NAND/SMC

interface

5

SPI

Audio

output/

PIEZO

PWM output

User interface/Power

Management

20

Other

6/49

STV0684

Signal Description

1

Table 1: STV0684 signal description

SFP

number

Pin name Location Type

Description

Power supplies: total 38 pins

VDDI1 L12

S

VDD IO Supply 3.3V

VDDI2

VDDI3

VDDI4

VDDI5

VDDI6

VDDI7

VDDI8

VDDI9

VDDI10

VDDC1

VDDC2

VDDC3

VDDC4

VDDC5

VSS

G13

F10

F7

VDD IO Supply 3.3V

VDD CORE supply 1.8V

GROUND

F4

K3

N3

P5

N6

K8

G8

C7

F2

M5

M11

L13

H8

F14

E13

B7

VSS

GROUND

VSS

GROUND

VSS

GROUND

VSS

S

GROUND

VSS

A7

GROUND

VSS

F6

GROUND

VSS

G6

K4

GROUND

VSS

GROUND

VSS

P2

GROUND

VSS

P4

GROUND

VSS

M6

M7

P8

GROUND

VSS

GROUND

VSS

GROUND

VSS

N11

D8

E8

GROUND

VDDP

VSSP

TV_VDDA

PLL core supply 3.3V

PLL core GND

TV core supply 3.3V

A12

7/49

Signal Description

STV0684

1

Table 1: STV0684 signal description

SFP

number

Pin name

TV_VSSA

Location Type

Description

B12

C10

B11

B14

C13

S

TV core GND

VDDA

Audio analog power supply 3.3V

Audio analog ground

VSSA

VDDAP

VSSAP

Audio PLL supply 1.8V

Audio PLL ground

Sensor interface: total 16 pins of which 12 are SFPs

SDATA0

SDATA1

SDATA2

SDATA3

SDATA4

SDATA5

SDATA6

SDATA7

SDATA8

SDATA9

HSYNC

VSYNC

SCLK

N8

M9

I

SFP80

SFP81

SFP82

SFP83

SFP84

SPF85

SFP86

SFP87

SFP88

SFP89

SFP90

SFP91

Sensor interface Bit0

I

Sensor interface Bit1

J8

I

Sensor interface Bit2

L9

I

Sensor interface Bit3

P9

I

Sensor interface Bit4

N9

I

Sensor interface Bit5

K9

I

Sensor interface Bit6

P10

L10

N10

M10

P11

N12

P14

P12

I

Sensor interface Bit7

I

Sensor interface Bit8

I

Sensor interface Bit9

Horizontal synchronization

Vertical Synchronization

Clock supplied to the sensor

Data qualifying clock from the sensor

I

O

I

SPCLK

SSDA

I²C Data line

I²C clock line

I/O

SSCL

P13

I/O

SDRAM interface: total 38 pins all of which are SFPs

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

DQ8

DQ9

DQ10

L14

N13

J9

I/O

SFP101

SFP92

SFP102

SFP93

SFP103

SFP94

SFP104

SFP95

SFP96

SFP105

SFP97

SDRAM

N14

J10

M12

K13

L11

K10

J11

M13

8/49

STV0684

Signal Description

1

Table 1: STV0684 signal description

SFP

number

Pin name Location Type

Description

DQ11

J12

M14

J13

K11

K14

K12

H10

J14

H11

H12

H9

I/O

SFP106

SFP98

SDRAM

DQ12

DQ13

DQ14

DQ15

DQML

A0

SFP107

SFP99

SFP108

SFP100

SFP109

SFP110

SFP111

SFP112

SFP113

SFP114

SFP115

SFP116

SFP117

SFP118

SFP119

SFP120

SFP121

SFP122

SFP123

SFP124

SFP125

SFP126

SFP127

SFP128

SFP129

A1

A2

A3

A4

A5

H14

H13

G10

G14

G11

G12

G9

A6

A7

A8

A9

A10

A11

A12

BA0

BA1

CLK

CKE

F13

E14

F12

F11

D14

E12

D13

E11

D12

DQMH

RAS

CAS

WE

9/49

Signal Description

STV0684

1

Table 1: STV0684 signal description

SFP

number

Pin name

Location Type

Description

Graphics LCD interface: total 18 pins of which all are SFPs

L_LP

L5

M4

N4

P3

N5

L6

K6

J6

I/O

SFP63

SFP64

SFP65

SFP66

SFP67

SFP68

SFP69

SFP70

SFP71

SFP72

SFP73

SFP74

SFP75

SFP76

SFP77

SFP78

SFP79

SFP13

LCD interface

L_RES

L_XINH

L_XSCL

L_FRYP

L_FRYS

L_DY / PNL_CLK

L_YSCL / HSYNC

L_YSCLD / VSYNC

L_DOUT0

P6

H7

P7

K7

J7

L_DOUT1

L_DOUT2

L_DOUT3

L_DOUT4

L7

N7

M8

L8

B6

L_DOUT5

L_FRX / Data6

L_GCP / Data7

BACKLIGHT

TV interface: total 3 pins

CVBS

LCD interface / GPIO

C12

B13

A13

ANA

CVBS out

TV_REXT

TV Reference voltage

TV_GNDA_REXT

SPI (used for MMC, SD): total 5 pins all of which are SFPs

SPI_MISO

SPI_MOSI

SPI_SLK

SPI_SS

B10

F9

I/O

SFP1

SFP2

SFP3

SFP4

SFP5

Master In Slave Out

Master Out Slave In

SPI clock

D9

B9

E9

SPI slave/host selection

SPI Chip select

SPI CS

10/49

STV0684

Signal Description

1

Table 1: STV0684 signal description

Pin name Location Type

Audio interface: total 6 pins of which 2 are sfps

SFP

number

Description

CBS

C11

A11

D10

C14

E10

C6

ANA

I/O

Audio Vbias

AP

Audio ADC Differential input

Audio ADC differential input

Audio PLL filter

AN

VC

PWM OUT

ENABLE

SFP0

DAC: Pulse Width Modulator output

ENABLE external audio amplifier

I/O

SFP17

NAND (Smartmedia) & Compact-flash interface: total 29 pins all of which are SFPs

IO0

E4

E3

D1

E2

E1

F5

F3

G3

F1

G7

G2

J1

I/O

SFP35

SFP36

SFP37

SFP38

SFP39

SFP40

SFP41

SFP42

SFP43

SFP44

SFP45

SFP46

SFP47

SFP48

SFP49

SFP50

SMC D0 - CF D00

SMC D1 - CF D01

SMC D2 - CF D02

SMC D3 - CF D03

SMC D4 - CF D04

SMC D5 - CF DO5

SMC D6 - CF DO6

SMC D7 - CF DO7

Nand Chip select

IO1

IO2

IO3

IO4

IO5

IO6

IO7

NAND CS

WE

SMC WE - CF WE

SMC ALE - CF OE

SMC CLE - CF READY

SMC R/-B - CF WAIT

SMC RE - CF REG

SMC CS - CF CE1

SMC WP - CF WP

ALE OE

CLE RDY

RB WAIT

RE REG

CS CARD EN

J4

J2

J5

WRIT_PROT

CARD DET1

K1

CARD_DET

CARD DET2

K5

I/O

SFP51

SMC CD - CF CD1

CFA0

CFA1

CFA2

CFA3

CFA4

CFA5

CFA6

CFA7

K2

L1

I/O

SFP52

SFP53

SFP54

SFP55

SFP56

SFP57

SFP58

SFP59

CF A00

CF A01

CF A02

CF A03

CF AO4

CF A05

CF A06

CF A07

L2

L3

M1

M2

N1

N2

11/49

Signal Description

STV0684

1

Table 1: STV0684 signal description

SFP

number

Pin name

Location Type

Description

CFA8

CFA9

M3

P1

L4

I/O

SFP60

SFP61

SFP62

CF A08

CF AO9

CF A10

CFA10

User Interface - (Application specific SFP): total 16 pins all of which are SFPs

MODE UP

F8

A10

C9

A9

D7

A5

B5

B8

E5

E7

A6

B4

D5

A4

C5

E6

I/O

SFP6

SFP7

see firmware manual

MODE DOWN

SELECT

see firmware manual

Sensor interface

SFP8

CANCEL

SFP9

SHUTTER

SFP12

SFP18

SFP19

SFP10

SFP20

SFP11

SFP14

SFP24

SFP21

SFP22

SFP23

SFP15

LED0

LED1

FLASH RDY

FLASH TRIGGER

POWER OFF

POWER DOWN

SNAP

SHUTTER_CNTL1

SHUTTER_CNTL2

SHUTTER_CNTL3

SUSPEND

mechanical shutter interface

Sensor suspend pin

General Purpose Input/Output: total 11 pins all of which are SFPs

GPIO0

GPIO1

GPIO2

GPIO3

GPIO4

GPIO5

GPIO6

GPIO7

GPIO8

GPIO9

GPIO10

B3

A2

C3

B2

A1

B1

C2

D3

C4

A3

D4

I/O

SFP28

SFP29

SFP30

SFP31

SFP32

SFP33

SFP34

SFP130

SFP25

SFP26

SFP27

General purpose IO

General purpose IO / JTAG TRIG EWARP

General purpose IO / JTAG TDI EWARP

General purpose IO / JTAG TDO EWARP

General purpose IO / JTAG TMS EWARP

General purpose IO / JTAG TCK EWARP

General purpose IO

12/49

STV0684

Signal Description

1

Table 1: STV0684 signal description

Pin name Location Type

USB interface: total 4 pins of which 1 is a SFP

SFP

number

Description

DP

G4

G5

G1

D6

I/O

USB DATAP

USB DATAN

DN

DETECT

USB TX_EN

High when USB VCC present

SFP16

Battery level detector: total 2 pins

LOW_BATT

VREF

A14

D11

ANA

Battery level input

Reference for the battery voltage

CLOCK, Reset, system signals: total 4 pins

Xtal in

C8

A8

C1

D2

ANA

I

27 Mhz Crystal input

27 MHz Crystal Output

RESET INPUT

Xtal out

RESET

WAKE_UP

I/O

Debug and test interface: total 7 pins of which 2 are SFPs

UP_TRIGI

UP_TRIGO

UP_TDI

H5

H4

H1

H2

J3

I/O

SFP131

SFP132

ST20 microconnect debug interface

I/O

I

O

I

UP_TDO

UP_TMS

UP_TCK

UP_RST

H6

H3

I

1. This is preliminary information that may be subject to change

13/49

Functional Description

STV0684

3

Functional Description

3.1

Video processor (VP)

The VP is the result of STMicroelectronics extensive know-how and hard work around the colour

science for CMOS sensor. The VP block fulfills many functions related to colour reconstruction from

a bayer filter, colour matrixing and sharpening, real-time and programmable defect pixel correction,

AGC, AWB, Anti flicker and Gamma correction, scaling from the sensor to the required video and

LCD panel resolution. This new video processor benefits from STMicroelectronics latest algorithms

development such as the patented Noise Reduction Algorithm and anti-vignetting that ensures the

highest quality standard.

The VP combines hardware and firmware. The main block controller is powered by a 8051 E WARP

microcontroller, with RAM based firmware for the highest level of flexibility.

Feature list

System features

●

RAM based firmware

Dual video interface for simultaneous ViewFinder and movie capture

Bayer or YCbCr input from supported memory

48Mpixel/s capable processing pipe

Flashgun and shutter support

RGB/YUV 4:2:2 output formats

Image reconstruction functions

●

x2, x2.5 Horizontal downscaling

Colour Channel Gains and Offsets

Anti-vignetting

Defect correction

NoRA - Active Noise Reduction

Demosaic (bayer->rgb conv)

YUV matrix (rgb -> YUV)

Image crop

General purpose RGB downscaler

RGB matrix

Peaking

Gamma correction

Statistics processor

●

4 Accumulators - programmable on the fly

Programmable zones

14/49

STV0684

Functional Description

Image control functions (Tasks handled by the EWARP processor)

●

Sensor detection, initialisation and configuration

VP mode management: stills, streaming etc.

Automatic Exposure Control, Automatic White balance

Flicker correction

Dampening/Promotion Tasks

Scaler Management

Dark Calibration

Flashgun control

Shutter control

3.2

ST20-C103 core

The ST20 core is the heart of the STV0684 system-on-chip. The processor can execute its code

from either the 64KB of private SRAM or directly from the external SDRAM. Instruction/Data cache

ensure a fast code execution.

A boot loader residing in a ROM of the device provides capability to boot the system by copying the

application firmware image from Non Volatile Memory (SPI Flash or Standard NAND Flash) to the

program SRAM or SDRAM memory. This mechanism ensures the lowest system cost by storing the

application firmware on a cheap mass storage memory and thus avoiding the extra cost of a NOR

type memory. The boot loader also provides the useful possibility to upgrade the Application

Firmware and therefore program cameras on the factory line.

The ST20-C103 core includes the following:

●

ST20C1 processor running at 48 MHz frequency

diagnostic control unit DCU3 (4 compare, 4 capture, trace) for debug and code development

PWM4 timer, INTC2 interrupt controller (16 inputs)

64K local RAM (SRAM)

4K D-cache & 4K I-cache instruction and data caches memory arbiter

15/49

Functional Description

STV0684

Core architecture and block diagram

Figure 4: ST20DC3 architecture and block diagram

ST20-C103

ICache

SDRAM

controller

Boot ROM

ST20-C103

DCache

Peripheral 1

Peripheral 2

Peripheral 10

ST20-C103

peripheral

port

Peripheral 11

Peripheral 10

ST20-C103

Peripheral 20

Interconnect

ST Bus Type 2 domain

ST Bus Type 1 domain

3.3

SFP module

The SFP module is based on reconfigurable device pins combined with some local logic to

maximize in-system flexibility of the device in any given application

An SFP can be configured either to be driven as a GPIO or by the local logic block within the

STV0684 (detailed in Figure 3). The functionality and configuration of each SFP is determined and

managed under control of the ST20. Control registers local to each module are mapped into the

processors address space, this leaves the processor to support more demanding, computational

intensive tasks.

16/49

STV0684

Functional Description

3.4

USB interface

The USB interface fulfills the three following functions:

●

The first function is to download from the camera to the PC all the various objects stored on the

mass storage media. The STV0684 uses mass storage class, Bulk Only Transfer to ensure

seamless connection with most of the Operating System on the market, including PC and Mac

platforms.

The second function is to stream concurrent audio and video through isochronous endpoints.

Once again, the STV0684 follow established and newly developed standards to ensure the

lowest burden of driver development. The STV0684 is USB Audio class and USB video class

Compliant.

The third function allows the download of the system program code, necessary to run the

application, to either serial Flash or NAND flash soldered on the main camera PCB. This

function is extremely convenient when programming the cameras on the manufacturing lines

and is not open to final users.

Features

●

USB 2.0 Compliant (Full speed device)

Full speed (12 Mbps) signalling bit rate

USB Audio Class Compliant

USB Video Class Compliant

USB Mass Storage Compliant, Bulk only Transfer protocol

Simultaneously accessible endpoints:

➢ Isochronous endpoint (IN) for video

➢ Isochronous endpoint (IN) for audio

➢ Bulk endpoint (IN) for download

➢ Bulk endpoint (OUT) for download

➢ Interrupt endpoint (IN)

➢ Control pipe

17/49

Functional Description

STV0684

3.5

Memory interface

Description

The memory control Block provides dedicated support for embedded SRAM, external SDRAM,

NAND, Smartmedia and Compact Flash (via SFP pins).

Embedded SRAM

●

Full-speed random read/write access from the ST20 to embedded SRAM

Full-speed embedded SRAM address generation for real-time data writes from the compression

engine, the Video Processor block, SPI, the audio block and the USB module

●

Full-speed embedded SRAM address generation for data reads to the DMA out FIFO

Selection of the source/destination modules is managed by firmware.

External SDRAM

●

ST20 memory mapped accesses to external SDRAM

Full-speed embedded SDRAM address generation for real-time data writes from VDFIF (for VC

and VP modules) or DMA out FIFO

●

Full-speed external SDRAM address generation/control to DMA out FIFO, TV FIFO, LCD FIFO

or VP FIFO’s

Operation with PC100 (or better e.g. PC133) and JEDEC Standard No. 21-C compliant devices

and supports 64MB, 128MB, 256MB and 512MB parts with a 16-bit bus width

Mass storage media support

●

Compact-flash support

SmartMedia Card support

NAND flash memory with a 512B+16 page organization, ECC done by hardware, 32Mbit to

1Gbit devices

●

Support for Multi-Media card and Secure Digital with the SPI interface

18/49

STV0684

Functional Description

3.6

Audio interface

The STV0684 includes every step of the processing chain required to record, compress,

decompress and playback audio. The STV0684 features a high quality 16 bit sigma delta analog to

digital converter including automatic level control and noise gating, as well as volume control. It also

features an ADPCM CODEC to maximize the length of audio and AVI clips on a given mass storage

media. Finally, the product features a digital to analog converter (PWM followed by RC filters) to

directly address a speaker or buzzer for audio playback.

3.6.1 Audio record

The audio record block consists two main blocks the analogue front end and a 16bit delta-sigma

ADC. The front end includes the functions of automatic level control and noise gate, and volume

control, the ADC uses sampling frequencies of 8kHz, 11.025kHz, 16kHz, 22.05kHz, 32kHz,

44.1kHz and 48kHz, with either differential or single ended inputs. The sampled output can be 8 or

16 bit. The output of the ACD is then available to the ADPCM module giving an audio compression

ratio of 4 to 1.

3.6.2 Audio playback

Audio playback is achieved by an internal Pulse Width Modulator with a sample rates of 8kHz,

11.025kHz, 16kHz, 22.05kHz, 32kHz or 44.1kHz, connected to either an external amplifier chip and

loudspeaker/ head phone socket, or to a simple piezo buzzer.

3.7

TV interface

The TV block is composed of a digital encoder that supports PAL and NTSC and a video digital to

analog converter (DAC). This interface supports still and video encoding for display on a TV set.

Features

●

Supports PAL/NTSC analog TV standards

Interlaced input data, YCrCb 4:2:2 format

16bits x 16words FIFO for buffering incoming display data

Interrupt generation

19/49

Functional Description

STV0684

3.8

LCD controller - Display interface

The STV0684 LCD controller has been specifically designed to ensure the two following important

characteristics:

●

Support of low cost panels with a direct interface to digital LCD panels removing the need for an

external timing controller IC

●

Flexibility with a high-level of programmability on all the signals shapes, polarities and

frequencies

The display interface fully supports LCD panel dot selection modes such as Delta, Delta

Transverse, Delta Longitudinal and Mosaic and many more by incorporating a dot selector which

converts 3dot/pixel input RGB frame data, to 1dot/pixel RGB data.

Basic functionality of the system includes still picture review, viewfinder mode as well as viewfinder

mode while recording a video clip.

Features

●

Support Thin Film Transistor (TFT) color displays

64 or 256 grey level, 256k(18bit)or 16.7Million(24bit) color TFT support

6 bit or 8 bit display interfaces

16-deep, 16bit deep FIFO for buffering incoming display data

Resolution programmable up to 1024x1024 pixels

Programmable timing for different display panels

Support CASIO, EPSON, and AU optronics panels

Horizontal, Vertical Sync and Pixel clock signals

Supports little-endian data formats

Interrupt generation

20/49

STV0684

Functional Description

3.9

JPEG CODEC

Description

The STV0684 features a compression and a decompression engine that is used for both Still

pictures and video clips. The hardware CODEC ensures a fast reaction time of the system to

encode and decode data. This is particularly important to minimize the shutter to shutter time and

the ability to rapidly display images on a local display or the TV set.

Compression engine The compression engine uses Baseline Sequential JPEG techniques to

compress a digital 656 video stream (at up to 12MPixels/s), down to bandwidth that can be

transmitted over the USB interface or to a mass storage media, typically 500-900Kbytes/s. It outputs

a JPEG data stream with the headers required by standard decoders.

Decompression engine The JPEG decoder block reads the compressed data from the DMA fifo,

parses the header and writes back decompressed data back to DMA fifo. This data is organized in

8x8 blocks of the different color components. This data can be converted to raster scan format to be

read by the display controller for display on a LCD or TV.

21/49

Functional Description

STV0684

3.10 Other interfaces

3.10.1 SPI

The SPI interface is a generic serial interface that can be used to perform the following functions:

●

Support for Multi-media and Secure Digital Cards

Support for serial flash where code can be located

●

The SPI supports:

●

Full duplex, three-wire synchronous transfers

Single, master/slave operation selectable either through firmware or hardware

Programmable clock polarity and phase

End of transfer interrupt flag

Write collision flag

Busy flag indication

3.10.2 I2C

The STV0684 features a hardware I2C master interface and supports the following features:

●

I2C protocol

Standard I2C mode (100 Khz)/Fast I2C mode (400 Khz)

Single master mode

Transmitter/Receiver performance

7/10 bit addressing

DMA mode data transfer

Clock stretching

3.10.3 Comparator for low battery detection

The comparator circuit was designed to compare the battery voltage (after an external resistor

divider) with an external reference voltage and generate a low_batt (high when battery voltage is

lower than the present threshold) signal for the CPU core.

22/49

STV0684

Electrical Characteristics

4

Electrical Characteristics

4.1

Absolute maximum ratings

Table 2: Absolute maximum ratings

Symbol

V_DDC

Parameter

Value

2.5

Unit

Supply voltage (core)

Supply voltage (IO)

V

V_DDI

4.0

V_DDP

Supply voltage (PLL)

Supply voltage (Audio)

Supply voltage (Audio_PLL)

Supply voltage (TV)

4.0

V

V_DDA

4.0

V_DDAP

V_{TV_VDDA}

2.5

Current on any signal pin

Storage temperature

2

mA

°C

T_STO

T_OP

-50 to 150

Operating temperature

0 to 70

+260

°C

T_LEAD

Lead temperature (soldering, 10 s)

Caution:

Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to

the device. This is a stress rating only and functional operation of the device at these or any other

conditions above those indicated in the operational sections of this specification is not implied.

Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

23/49

Electrical Characteristics

STV0684

4.2

Operating conditions

Table 3: Operating conditions

Symbol

Parameter

Typ.

1.8

3.3

1.8

3.3

25

Unit

V

V_DDC

V_DDI

Supply voltage (core)

Supply voltage (IO)

V

V_DDP

V_DDA

V_DDAP

V_{TV_VDDA}

T_A

Supply voltage (PLL)

Supply voltage (Audio)

Supply voltage (Audio_PLL)

Supply voltage (TV)

V

Ambient temperature

°C

4.3

Thermal data

Table 4: Thermal data

Symbol

Parameter

Value

Unit

Rth(j-a)

Junction-ambient thermal resistance - LFBGA196 (Note 1)

50

°C/W

Note: 1 Typical, measured with the component mounted on an evaluation PC board in free air.

24/49

STV0684

Electrical Characteristics

4.4

DC electrical characteristics

Over operating conditions unless otherwise specified. Values from Table 5 and Table 6 are

estimates.

Table 5: DC electrical characteristics

Symbol

V_Il

Parameter

Min

Typ

Max

0.631

Unit

Input low voltage (XTAL_IN)

Input high voltage (XTAL_IN)

Hysteresis (XTAL_IN)

0

V

V_Ih

1.123

V_DDC

V

µA

V_hys

V_IL

0.492

Input low voltage (SFP pin)¹

0

0.8

Input high voltage (SFP pin)¹

V_IH

V_HYS

V_T+

V_T-

2

V_DDI

Schmitt trigger hysteresis (SFP pin)¹

Schmitt input low to high threshold voltage (SFP pin)¹

Schmitt input high to low threshold voltage (SFP pin)¹

0.4

2.15

1.05

1.65

Threshold point (SFP pin)¹

Output low voltage(SFP pin)

V_T

V_OL

V_OH

I_IL

0.4

Output high voltage(SFP pin)

2.4

1

Input leakage current

Input pins

I/O pins

V_ILU

USB differential pad D+/D- input low

0.8

3.6

V

V_IHU

V_IHUZ

V_TDI

USB differential pad D+/D- input high (driven)

USB differential pad D+/D- input high (floating)

2.0

2.7

0.2

0.8

0.0

2.8

1.3

USB differential pad D+/D- input sensitivity ²

USB differential pad D+/D- common mode voltage ³

USB differential pad D+/D- output low voltage

V_CM

2.5

0.3

3.6

2.0

V_OLU

V_OHU

V_CRS

USB differential pad D+/D- output high voltage

USB differential pad D+/D- output signal cross over

voltage

Z_drv

Driver output resistance

28

44

Ω

1. These figures apply to SFP, SPCLK, SSCL, and SSDA, they do not apply to the XTAL_IN pad

2. V = |(D+)- (D-)|

DI

3. V includes V range

cm

DI

25/49

Electrical Characteristics

STV0684

Table 6: Power supply specifications

Symbol

V_DDC

Parameter

Min

1.65

Typ

1.8

Max

1.95

Unit

Supply voltage (core)

Supply voltage (IO)

Supply voltage (PLL)

V

V_DDI

3.0

1.65

3.0

3.3

1.8

3.3

3.6

1.95

3.6

V_DDP

V_DDA

Supply voltage (Audio)

Supply voltage (Audio_PLL)

Supply voltage (TV)

V_DDAP

V_{TV_VDDA}

I_Suspend

Core Suspend current

IO Suspend current

0.2

mA

µA

1.166

PLL Suspend current

1

Audio Suspend current

Audio_PLL Suspend current

TV Suspend current

µA

I_{Low power}

Core Low power Current

IO Low power Current

PLL Low power Current

Audio Low power Current

Audio_PLL Low power Current

TV Low power Current

Core High power Current

IO High power Current

PLL High power Current

Audio High power Current

Audio_PLL High power Current

TV High power Current

54.3

6.3

3.8

5.9

12

mA

µA

1

µA

I_Highpower

130

mA

17.8

7.74

5.3

0.23

11.63

26/49

STV0684

Electrical Characteristics

4.5

AC electrical characteristics

4.5.1 SFP AC parameters

Each SFP is a TTL schmitt trigger bidirectional pad Buffer, 3v3 capable with 2mA drive capability

and Slew-rate Control. The 3.3V IOs comply to the EIA/JEDEC standard JESD8-B.

4.5.2 Audio ADC electrical parameters

Table 7: Audio/ADC electrical characteristics

Symbol

Fclk

Parameter

Test conditions

Min.

Typ.

12

Max.

Unit

MHz

Clock frequency

Clk duty cycle

Dutymclk

Fs

40

60

%

Sample frequency

Bias reference voltage

8

48

kHz

V

Vbias

Vbias / V_DDA= 3V

1.5

Rbias

RIN

Vbias impedance

Input impedance

Input capacitance

Input dynamic range

Vbias

5

kΩ

pF

IN+ / IN-

50

10

1.5

Cin

Dyn In

ADC Out Full scale IN+ /

IN- Gain 0dB (AGC off)

Vpp

SNR*

Offset

Signal / Noise ratio

Offset error

Sinewave @FS - 3dB

Gain 0dB

82

dB

After automatic

calibration

100

LSB

dB

Harm¹

Signal to peak harmonics Sinewave @FS - 3dB

Gain 0dB

75

50

Sinewave @FS - 3dB

Gain 24dB

dB

1. Input sine wave 1kHz, Fmclk 11.289 MHz, BW = 10Hz-20 kHz, A-weighting filters, output 16 bits

RAW PCM

27/49

Electrical Characteristics

STV0684

4.5.3 AC electrical characteristics of USB transceiver

All measurements are fully electrically compliant to Chapter 7 (Electrical requirements) of revision 2

of the USB specification for full-speed devices (V1.1). The transceiver has been tested with external

impedance-matching series resistors (27 Ω +/-5%) between the pads and the USB cable.

The operation of the USB transceiver is guaranteed through design and application testing.

Table 8: AC characteristics of USB transceiver

Symbol

Description

Min.

Typ.

Max

Unit

Transmit /Output stage

tlr

Fall time

4.45

5.82

5.77

7.31

ns

tlf

Rise time

4.55

90

6.81

111

ns

%

tlrfm

System

Rpu

Rise and fall time matching

USB differential pad Dp,

Dn pullup Resistor

1.425

14.25

1.575

15.75

kΩ

Rpd

USB differential pad Dp,

Dn pulldown Resistor

28/49

STV0684

Electrical Characteristics

4.5.4 SDRAM timing description

4.5.4.1 Read/Write timing diagrams for external synchronous DRAM

Figure 5: SDRAM read timing

t_CK

t_CL

t_CH

DCLK

CKE

t_CMS

t_CMH

READ

Command

(RAS, CAS,

WE)

ACTIVE

NOP

PRECHARGE

NOP

A0-9, BA,

A11-12

ROW

COLUMN

A10

ROW

t_AS

t_AH

t_CMS

t_CMH

t

OH

AC

DQM

DQ

DOUT M

DOUT M + 1

DOUT M + 2 DOUT M + 3

t

RCD

CAS Latency

t

RC

t

RP

RAS

DQ sample

Figure 6: SDRAM write timing

t_CK

t_CL

t_CH

DCLK

CKE

t_CMS

t_CMH

WRITE

Command

(RAS, CAS,

WE)

ACTIVE

NOP

PRECHARGE

NOP

A0-9,

ROW

COLUMN

A11-12

A10

t_AS

t_AH

t_CMS

t_CMH

t

DH

DS

DQM

DQ

DIN M

DIN M + 1

DIN M + 2

DIN M + 3

t

RCD

t

RC

t

RP

RAS

SDRAM Write Timing

29/49

Electrical Characteristics

STV0684

Table 9: SDRAM timing

Symbol

Min

Typ

Max

Units

ns

t

41.67

CK

t

/2 - (t *0.0345)

t

/2

t

/2 + (t *0.0345)

ns

CH

CK

/2 - (t *0.0345)

/2 + (t *0.0345)

ns

CL

CK

24.8

ns

AC

0

ns

OH

CMS

CMH

AS

20.3

20

20.7

20.1

21.8

1

ns

DS

ns

DH

t

RCD

RAS

RC

CK

2

4

2

RP

1

2

t

RRD

tah

19.8

ns

1. t_RRD= Row active to row active delay

Note: 1 The SDRAM interface is designed to operate with SDRAM devices which are compliant with the

Intel SDRAM Specification Revision 1.7 November 1999. Speed grades 66, 100 and 133MHz are

compatible.

2 Above timing assumes 20pF load per pad.

30/49

STV0684

Electrical Characteristics

4.5.5 I²C timing description

Figure 7: START and STOP conditions

STOP

START

SDA

tSU;STA

tSU;STO

tHD;STA

SCL

Figure 8: SDA Data valid

tLOW

SCL

SDA

tHIGH

tHD;DAT

tSU;DAT

Data allowed to

change

Data allowed to

change

Data valid

2

Table 10: I C timing Spec

STD mode

FAST mode

Unit

Symbol

Parameter

Min

Max

Min

Max

f SCL

SCL clock frequency

Low period of SCL

10

100

10

400

kHz

µs

ns

µs

tLOW

4.8

-

1.4

0.9

1.4

0.9

-

tHIGH

High period of SCL

Hold time for a repeated start

Setup time for repeated start

Setup time for a stop

Data hold time

tHD;STA

tSU;STA

tSTU;STO

tHD;DAT

tSU;DAT

tBUF

350

2.4

4.8

350

045

1.4

Data setup time

Bus free time between stop and

start

31/49

Electrical Characteristics

STV0684

Figure 9: Message format

S

SR

R/w

A

(A)

7 BIT DEVICE ADD

A

8 BIT DATA

P

SCL

LSB

MSB

1

LSB

8

MSB

1

8

2

3

9

2

7

9

SDA

4.5.6 SPI timing description

It is able to support master and slave mode. The timing given is needed for slave mode and in

master mode is able to provide

t_R, t_F= 5ns with output load 30pF

Figure 10: SPI timing diagram

t

DSU

t

SCK

DH

SPI_SLK

SPI_MISO

SPI_MOSI

t

V

SPI_SLK

SPI_SS

SPI_SLK

SPI_SS

t

CS

t

CSS

t

CHSH

Table 11: SPI timing table

Symbol

Parameter

Min

Max

Units

f_SCK

t_DSU

t_DH

SCK frequency= 1/t_SCK

Data in Setup time

Data in Hold time

24 (master)

48 (slave)

MHz

18(master)

5(slave)

ns

0(master)

5(slave)

32/49

STV0684

Electrical Characteristics

Table 11: SPI timing table

Symbol

t_CSS

Parameter

Min

Max

Units

ns

SS active Setup time, relative to SCK

210(master/

slave)

t_CHSH

SS active hold time, relative to SCK

Clock low to output valid

50(master/

slave)

ns

t_V

20

(master/slave)

t_CS

t_idle

Minimum SS high time

120(slave)

ns

Idle phase between byte transfer in transmit mode for

resynchronisation

In slave mode for resynchronization purpose the need for idle phase between byte transfer is

needed for the transmit mode.

Figure 11: Idle phase timing in slave mode

t_idle

sck

33/49

Electrical Characteristics

STV0684

4.5.7 NAND timing description

Figure 12: Command latch cycle for NAND flash interface

CLE

t

CLH

CLS

CE_n

WE_n

ALE

t

WP

t

ALS

ALH

t

DS

DH

IO[7:0]

Command

Figure 13: Address latch cycle for NAND flash interface

CLE

t

WC

CLS

CE_n

WE_n

t

WH

WP

t

ALH

ALE

t

DS

DH

IO[0:7]

A9-A16

A17-A21

A0-A7

34/49

STV0684

Electrical Characteristics

Figure 14: Input data latch cycles for NAND flash interface

CLE

t

CLH

CE_n

t

WC

ALS

ALE

WE_n

IO[0:7]

t

WH

WP

t

DS

DH

DIN0

DIN1

DIN511

Figure 15: Sequential output cycle after read for NAND flash interface

t

RC

CE_n

RE_n

t

REH

RP

t

REA

IO[0:7]

RB_n

Dout

t

RR

Figure 16: Status read cycle for NAND flash interface

CLE

t

CLS

t

CLS

CLH

CE_n

WE_n

t

WP

t

WHR

RE_n

t

DS

DH

t

RSTO

IO[0:7]

Status

70h

35/49

Electrical Characteristics

STV0684

Figure 17: Read operation for NAND flash interface

CLE

CE_n

WE_n

t

WB

ALE

t

R

RE_n

t

RR

IO[0:7]

RB_n

00H A0-7 A9-16 A17-21

Dout0

Dout1

Dout2

Figure 18: Reset operation for NAND flash interface

CLE

CE_n

WE_n

FFh

IO[0:7]

RB_n

t

RST

36/49

STV0684

Electrical Characteristics

4.5.8 AC characteristics for NAND flash operation

Table 12: AC characteristics for NAND flash operation

Symbol

t_CLS

Parameter

Min

61.4

Typical

Max

Units

ns

CLE Set-up time

CLE Hold time

62.4

t_CLH

t_WP

t_ALS

t_ALH

t_DS

83.2

82.6

82.4

82.6

61.8

145.1

61.9

81

ns

µs

ns

µs

WE-n Pulse Width

ALE Set-up time

ALE Hold time

83.2

62.4

145.6

62.4

83

Data Set-up time

Data Hold time

Write Cycle time

t_DH

t_WC

t_WH

t_RR

WE_n High Hold time

Ready to RE_n Low

RE_n Pulse Width

t_RP

83.2

187.2

t_RC

Read Cycle time

t_REA

t_REH

t_WHR

t_R

RE_n Access time

35

43.2

RE_n High Hold time

WE_n High to RE_n Low

Data Transfer from Cell to Register

WE_n High to Busy

103.5

124.2

104

124.8

25.015

215.3

5.015

t_WB

t_RST

41.6

Device Resetting (Read)

Note: 1 All parameters relating to the CE_n signal are omitted as it is not enabled/disabled during execution

of any NAND flash operation i.e. it is permanently tied low.

2 All timings are worst case

3 Conforms to both Samsung and Toshiba specifications as outlined in datasheets.

4 The NAND flash timings detailed here are guaranteed by design.

5 The loading factor used for the characterization is equivalent to 40pF.

4.5.9 Compact flash timing

There are two types of bus cycles and timing sequences that occur in the PCMCIA type interface,

direct mapped I/O transfer and memory access. The STV0684 will only support the memory

mapped mode.

37/49

Electrical Characteristics

STV0684

4.5.9.1 Compact flash pin description

The following table lists the pins of the CF card which are connected to the STV0684.Output refers

to pins that are driven by STV0684. Input is those pins that are driven by the CF Card.

Table 13: Pin description

Symbol

CFA0 ~CFA10

Pin Description

Direction

SFP used

Address

Output

Input

52~62

50

CARD_DET

Card Detect

CARD_DET2

CS CARD EN

IO0~IO7

ALE OE

CLE RDY

RE REG

RST

Card Enable.

Output

Input

49

Data. Only 8 bits of the data bus D[7:0] are used.

35~42

45

Output Enable

Output

Input

Ready/Busy

46

Register(Attribute) Memory Select

Reset

Output

48

note ¹

47

RB WAIT

WE

Wait

Input

Write Enable

Output

44

1. The reset may come from the global reset of the system or be driven by a user definable SFP this

function is application specific.

4.5.9.2 Compact flash timings

The timings achieved for accessing the attribute and common memory are listed below.There are

registers in the CF Controller of the STV0684 in which all these timings can be programmed in

terms of number of clocks of 48MHz. All the timings below assume a 48MHz operating clock

frequency.

Table 14: CF attribute memory read timing

Symbol

Parameter

Min.

340

Typ.

Max.

Units

ns

tc(R)

Read Cycle Time

-

ta(A)

Address Access Time

300

ns

ta(CE)

ta(OE)

tdis(CE)

tdis(OE)

tsu (A)

ten(CE)

ten(OE)

tv(A)

Card Enable Access Time

Output Enable Access Time

Output Disable Time from CE

Output Disable Time from OE

Address Setup Time

300

100

40

5

Output Enable Time from CE

Output Enable Time from OE

Data Valid from Address Change

5

0

38/49

STV0684

Electrical Characteristics

Figure 19: Attribute memory read timing diagram

Table 15: Attribute memory write timing

Symbol Parameter

tc(W)

Min.

280

Max.

Units

ns

Write Cycle Time

tw(WE)

Write Pulse Width

Address Setup Time

Write Recovery Time

Data Setup Time for WE

Data Hold Time

200

40

ns

tsu(A)

trec(WE)

WE tsu(D-WEH)

th(D)

40

160

40

39/49

Electrical Characteristics

STV0684

Figure 20: Attribute memory write timing diagram

Table 16: Common memory read timing

Symbol

Item

Min.

Max.

140

Units

ta(OE)

tdis(OE)

tsu(A)

Output Enable Access Time

ns

Output Disable Time from OE

Address Setup Time

100

40

th(A)

Address Hold Time

40

0

tsu(CE)

th(CE)

tv(WT-OE)

tv(WT)

tw(WT)

CE Setup before OE

CE Hold following OE

Wait Delay Falling from OE

Data Setup for Wait Release

Wait Width Time

40

0

350

40/49

STV0684

Electrical Characteristics

Figure 21: Common memory read timing diagram

Table 17: Common memory write timing

Symbol

Parameter

Min.

80

Max.

Units

ns

tsu(D-WEH)

th(D)

Data Setup before WE

Data Hold following WE

WE Pulse Width

40

200

40

0

ns

tw(WE)

tsu(A)

Address Setup Time

CE Setup before WE

Write Recovery Time

Address Hold Time

tsu(CE)

trec(WE)

th(A)

40

20

th(CE)

CE Hold following WE

Wait Delay Falling from WE

WE High from Wait Release

Wait Width Time

tv(WT-WE)

tv(WT)

40

0

tw (WT)

350

41/49

Electrical Characteristics

STV0684

4.5.10 TFT

Table 18: TFT timing

Symbol

Parameter

Min.

1.56

Max.

27

Units

PNL_CLK

HSYNC¹

VSYNC¹

Panel clock

MHz

Horizontal Sync

2

1822

1598

PNL_CLK periods

Vertical sync

Horizontal sync

periods

1. HSYNC & VSYNC are active low (default, but programmable) and the falling edge of both HS & VS

are always synchronous.

4.5.11 TV

TV timing description

Table 19: TV timing description

Symbol

Parameter

Min.

Typ.

Max.

10

Unit

Bits

Resolution

Recommended load impedance

175

Ω

Analog output

1

6.64

8

9.36

1.6

mA

Dynamic current

1

V DC

Output voltage

Dynamic performance

SNR, BW=10MHz, Fclk=80MHz

THD, BW=10MHz, Fclk=80MHz

Voltage reference

50

dB

V_REXT - TV_GNDA_REXT

-7%

1.4

+7%

V

1. The output current of 8mA = typ: TV_REXT - TV_GNDA_REXT =1.4V, RREF=10000 Ω

TV External components

An external 10000 ohm precision resistor typical 1% placed between the TV_REXT pin and

GNDAS_REXT sets the full scale DAC current.

42/49

STV0684

Electrical Characteristics

4.5.12 Sensor interface

Figure 22: Timing for sensor input

T_CLK

T_SETUP

T_HOLD

SPCLK

SDATA[9:0]

SENSOR_VSYNC

SENSOR_HSYNC

T_RMAX

T_SKEW

Table 20: Timing for Sensor Input

Symbol

Parameter

Min

20

Max

1000

Unit

ns

T

SPCLK

CLK

(50MHz) (1MHz)

T

Data valid before clock rising

Data hold time

1.5

ns

SETUP

HOLD

RMAX

SKEW

T

/2

CLK

Max transition time (20% to 80%)

Data / clock skew

1

ns

ps

440

55

Clock duty cycle

45

4.6

ESD handling characteristics

Table 21: ESD handling characteristics

Test

Criteria

Unit

ESD Machine Model

ESD Human body

150

2

V

kV

43/49

Electrical Characteristics

STV0684

4.7

External circuits

4.7.1 Crystal oscillator

There are 2 crystal oscillator pins XTAL_IN, XTAL_OUT, as shown in Figure 23. The Oscillator cell

architecture is a single stage oscillator with an inverter working as an amplifier. The oscillator stage

is biased by an internal resistor (>1MΩ). It also requires an external PI network consisting of a

crystal and two capacitors.

Note: The TV standards requests that the clock accuracy of the oscillator circuit must be 30ppm or less to

achieve a 500Hz accuracy for 4.5MHz chroma.

Figure 23: Oscillator support circuit

XTALI

XTALO

22pF

Crystal

22pF

4.7.2 Audio

Figure 24: Audio PLL filter and CBS

VC

CBS

10K

+

_

10µF

680pF

10nF

If the record audio section of the STV0684 is not required, AP, CBS, VC and AN can be left

unconnected. Power must still be supplied to VDDA and VDDAP.

4.7.3 Recommended power supply decoupling

A 0.1µF bypass capacitor located as close as possible to the chip package connecting between all VDD pins

and GND and at least one bulk decoupling capacitor on each of the supply rails VDDA, VDDC, VDDI and

VDDP.

44/49

STV0684

Package Information

5

Package Information

5.1

STV0684 pin assignment

Figure 25: STV0684 pin assignment

14

13

12

11

10

9

8

7

6

5

4

3

2

1

TV_GNDA TV_VDDA

_REXT

LOW_

BAT

AP

SFP7

SFP1

VDDA

AN

SFP9

SFP4

SFP8

SFP3

SFP5

XTALO VSS_6 SFP14 SFP18 SFP22 SFP26 SFP29 SFP32

SFP10 VSS_5 SFP13 SFP19 SFP24 SFP28 SFP31 SFP33

A

B

C

D

E

F

VDDAP TV_

REXT

TV_

VSSA

CBS

VC

VSSA

P

CVBS

XTALI

VDDP

VSSP

SFP6

VDDC SFP17 SFP23 SFP25 SFP30 SFP34 RESET

_2

SFP125

SFP127 SFP129 VREF

SFP12 SFP16 SFP21 SFP27 SFP130 WAKEUP SFP37

SFP11 SFP15 SFP20 SFP35 SFP36 SFP38 SFP39

VDDI_4 VSS_7 SFP40 VDDI_5 SFP41 VDDC_3 SFP43

SFP122 VSS_4 SFP126 SFP128 SFP0

VSS_3 SFP121 SFP123 SFP124 VDDI_3 SFP2

SFP117 VDDI_2 SFP119 SFP118 SFP116 SFP120 VDDC_1 SFP44 VSS_8 DN

DP

SFP42 SFP45 USB_

DETECT

G

H

J

SFP114 SFP115 SFP112 SFP111 SFP109 SFP113 VSS_2 SFP72 UP_

TCK

SFP132 SFP131 UP_

RST

UP_

TDO

UP_

TDI

SFP110 SFP107 SFP106 SFP105 SFP103 SFP102 SFP82 SFP75 SFP70 SFP49 SFP47 UP_

TMS

SFP48 SFP46

SFP108 SFP104 SFP100 SFP99 SFP96 SFP86 VDDI_ SFP74 SFP69 SFP51 VSS_9 VDDI_6 SFP52 SFP50

10

K

L

SFP101 VSS_1 VDDI_1 SFP95 SFP88 SFP83 SFP79 SFP76 SFP68 SFP63 SFP62 SFP55 SFP54 SFP53

SFP98 SFP97 SFP94 VDDC_5 SFP90 SFP81 SFP78 SFP13 SFP12 VDDC_4 SFP64 SFP60 SFP57 SFP56

M

N

P

SFP93 SFP92 SCLK

VSS_

15

SFP89 SFP85 SFP80 SFP77 VDDI_9 SFP67 SFP65 VDDI_7 SFP59 SFP58

SPCLK SSCL

SSDA

SFP91 SFP87 SFP84 VSS_

14

SFP73 SFP71 VDDI_8 VSS_

11

SFP66 VSS_

10

SFP61

45/49

Package Information

STV0684

5.2

STV0684 package mechanical data

Dimensions (mm)

Typ.

Reference

Min.

Max.

A

1.210

0.270

1.700

A1

A2

b

1.120

0.500

0.450

0.550

D

11.850

12.000

10.400

12.000

10.400

0.800

12.150

D1

E

11.850

12.150

E1

e

0.720

0.650

0.880

0.950

0.120

f

0.800

ddd

Note: 1 The maximum mounted height is 1.57 mm based on a 0.37 mm ball pad diameter.

Solder paste is 0.15 mm thick with 0.37 mm ball pad diameter.

2 LFBGA stands for Low Profile Fine Pitch Ball Grid Array.

Low profile: The total profile height (Dim A) is measured from the seating plane to the top of the

component. A = [1.21 to 1.70] mm

FIne pitch: e<1.00 mm pitch.

3 The terminal A1 corner must be identified on the top surface by using a corner chamfer, ink or

metallized markings or other features of package body or integral heatslug.

A distinguishing feature can be added on the bottom surface of the package to identify the terminal

A1 corner.

Exact shape of each corner is optional.

46/49

STV0684

Package Information

Figure 26: LFBGA 12x12x1.70 196 (80% scale versus original drawing)

47/49

Revision history

STV0684

Revision history

Table 22: Revision history

Version

Date

Comments

1

22-Mar-05

First publication for this revision 1.

48/49

STV0684

Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of

such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication

or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice.

This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical

components in life support devices or systems without the express written approval of STMicroelectronics.

The ST logo is a registered trademark of STMicroelectronics.

All other names are the property of their respective owners

STMicroelectronics Group of Companies

Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan -

Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States

http://www.st.com

49/49


型号：	STV0684
厂家：	ST
描述：	Digital Camera Processor 数码相机处理器消费电路商用集成电路数码相机
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