STV5348D/T [STMICROELECTRONICS]
MONOCHIP TELETEXT AND VPS DECODER WITH 8 INTEGRATED PAGES; MONOCHIP图文电视和VPS解码器，集成8 PAGES
| 型号： | STV5348D/T |
| 厂家： | 
ST |
| 描述： | MONOCHIP TELETEXT AND VPS DECODER WITH 8 INTEGRATED PAGES |
| 文件： | 总30页 (文件大小：552K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
STV5348
STV5348/H - STV5348/T
MONOCHIP TELETEXT AND VPS DECODER
WITH 8 INTEGRATED PAGES
FEATURES SUMMARY
Figure 1. Package
■ COMPLETE TELETEXT AND VPS DECODER
INCLUDING AN 8 PAGE MEMORY ON A
SINGLE CHIP
■ UPWARD SOFTWARE COMPATIBLE WITH
PREVIOUS ST’s MULTICHIP SOLUTIONS
(SAA5231, SDA5243, STV5345)
■ PERFORM PDC SYSTEM A (VPS) AND PDC
SYSTEM B (8/30/2) DATA STORAGE
SEPARATELY
PDIP28 (Plastic Package)
■ DEDICATED "ERROR FREE" OUTPUT FOR
VALID PDC DATA
■ INDICATION OF LINE 23 FOR EXTERNAL
USE
■ SINGLE +5V SUPPLY VOLTAGE
■ SINGLE 13.875MHz CRYSTAL
■ REDUCED SET OF EXTERNAL
COMPONENTS, NO EXTERNAL
ADJUSTMENT
SO28 (Plastic Package)
■ OPTIMIZED NUMBER OF DIGITAL SIGNALS
Figure 2. Pin Connections
REDUCING EMC RADIATION
■ HIGH DENSITY CMOS TECHNOLOGY
1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
CVBS
MA/SL
VDDA
CBLK
TEST
■ DIGITAL DATA SLICER AND DISPLAY
2
CLOCK PHASE LOCK LOOP
3
VSSA
VSSO
■ 28 PIN DIP & SO PACKAGE
4
POL
DESCRIPTION
5
STTV/LFB
FFB
XTI
The STV5348 decoder is a computer-controlled
teletext device including an 8 page internal mem-
ory. Data slicing and capturing extracts the teletext
information embedded in the composite video sig-
nal. Control is accomplished via a two wire serial
6
XTO
7
VSSD
VDDD
8
R
VCR/TV
RESERVED
DV
2
9
I C bus ®. Chip address is 22h. Internal ROM pro-
G
vides a character set suitable to display text using
up to seven national languages. Hardware and
software features allow selectable master/slave
synchronization configurations. The STV5348
also supports facilities for reception and display of
current level protocol data.
10
11
12
13
14
B
RGB REF
BLAN
L23
SDA
COR
SCL
Y
ODD/EVEN
REV. 2
May 2004
1/30
STV5348 - STV5348/H - STV5348/T
Table 1. Pin Description
Pin No
Symbol
Function
Description
Composite Video Signal Input through Coupling Capacitor
Master/Slave Selection Mode
+5V
Figure
12
14
-
1
CVBS
Input
2
MA/SL
Input
3
V
A
DD
Analog Supply
Input
4
POL
STTV/LFB
FFB
STTV / LFB / FFB Polarity Selection
Composite Sync Output, Line Flyback Input
Field Flyback Input
15
18
15
-
5
Output / Input
Input
6
7
VSSD
R
Ground
Output
Digital Ground
8
Video Red Signal
16
16
16
16
18
18
18
18
19
20
18
18
18
18
-
9
G
Output
Video Green Signal
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
B
Output
Video Blue Signal
RGBREF
BLAN
COR
Supply
DC Voltage to define RGB High Level
Fast Blanking Output TTL Level
Open Drain Contrast Reduction Output
25Hz Output Field synchronized for non-interlaced display
Open Drain Foreground Information Output
Serial Clock Input
Output
Output
ODD/EVEN
Y
Output
Output
SCL
Input
SDA
Input/ Output
Output
Serial Data Input/Output
L23
Line 23 Identification
DV
Output
VPS Data Valid
RESERVED
VCR/TV
Test
To be connected to VSSD through a resistor
PLL Time Constant Selection
+5V
Input
V
D
Digital Supply
Crystal Output
Crystal Input
Ground
Ground
Test
DD
XTO
XTI
Oscillator Output 13.875MHz
Oscillator Input 13.875MHz
Oscillator Ground
17
17
-
VSSO
V
Analog Ground
-
SSA
TEST
CBLK
Grounded to V
14
13
SSA
Input / Output
To connect Black Level Storage Capacitor
2/30
STV5348 - STV5348/H - STV5348/T
Figure 3. Block Diagram
FFB MA/SL POL
VDDD VDDA
STTV/LFB
L23
18
5
6
2
4
22
3
Data
CVBS
CBLK
1
CLAMPING
SYNCHRONIZING
DATA EXTRACTION
DATA DECODING
DATA
PROCESSING
Clock
19
20
DV
28
21
VCR/TV
TEST
OSCILLATOR
FREQUENCY
SYNTHETIZER
TIME BASE
XTI
24
23
8 PAGES
MEMORY
XTO
VSSO 25
BLAN
12
13 COR
RED
GREEN
BLUE
Y
8
9
SCL
SDA
16
17
I2C BUS
INTERFACE
DISPLAY
INTERFACE
10
15
STV5348
27
TEST
7
26
11
14
VSSD
V
ODD/EVEN
RGB REF
SSA
Table 2. Absolute Maximum Ratings
Symbol
Parameter
Value
Unit
V
V
Positive Supply Voltage on V
Input Voltage (any input)
and V
DDA
–0.3, 6.0
–0.3, V + 0.5
DD
DDD
V
V
I
DD
V
O
Output Voltage (any output)
–0.3, V + 0.5
V
DD
∆V
Difference between V
, V
DDD DDA
0.25
0, +70
V
DD
T
oper
Operating Ambient Temperature
Storage Temperature
°C
°C
T
–40, +150
stg
3/30
STV5348 - STV5348/H - STV5348/T
ELECTRICAL CHARACTERISTICS
(V = 5V, V = 0V, T = 25°C)
DD
SS
A
Table 3. Supplies
Symbol
Parameter
Min.
Typ.
5.0
30
Max.
Unit
V
V
Supply Voltage
4.75
5.25
DD
I
V
V
Pin Supply Current
mA
mA
DDD
DDD
DDA
I
Pin Supply Current
5
DDA
Table 4. Inputs
Symbol
Parameter
Min.
Typ.
Max.
Unit
CBLK
I
Source Current (V
= 2V, V = 0V)
CVBS
4.75
5.0
30
5.25
V
BLKO
CBLK
I
Sink Current (V
= 2V, V = 1V))
CVBS
mA
BLKI
CBLK
CVBS
CVBSI
CVBSC
Video Input Amplitude (peak to peak)
Input Capacitance
1
V
10
pF
ns
t
Delay from CVBS to TCS Output from STTV Pin
Clamping Level at Synchro Pulse
200
0
SYNC
V
mV
µA
µA
CLAMP
I
High Level Clamp Current (CVBS = V
+ 1V)
5
CLPH
CLAMP
I
Low Level Clamp Current (CVBS = V
– 0.3V)
–400
CLPL
CLAMP
MA/SL, POL, LFB, FFB, VCR/TV
V
Input Voltage Low Level
Input Voltage High Level
–0.3
2
+0.8
V
V
IL
IH
IL
V
V
DD
I
Input Leakage Current (V = 0 to V
)
–10
+10
10
µA
pF
I
DDD
C
Input Capacitance
I
SCL, SDA
V
Input Voltage Low Level
Input Voltage High Level
–0.3
3
+1.5
V
V
IL
IH
IL
V
V
DD
I
Input Leakage Current (V = 0 to V
)
–10
+10
100
2
µA
kHz
µs
I
DD
f
Clock Frequency (SCL)
SCL
t , t
R
Input Rise and Fall Time (10 to 90%)
Input Capacitance
F
C
10
pF
I
RGB REF
V
Input Voltage
Input Current
V
–0.5V
DD
V
V +0.3V
DD
V
I
DD
I
50
mA
I
4/30
STV5348 - STV5348/H - STV5348/T
Table 5. Outputs
Symbol
Parameter
Min.
Typ.
Max.
Unit
RGB
V
Output Low Voltage (I = 2mA)
0.4
RGB REF
50
V
V
OL
OL
V
OH
Output High Voltage (I = –2mA, RGB REF = V /2) RGB REF – 0.5
OH DD
C
Load Capacitance
Rise and Fall Time (10 to 90%)
pF
ns
L
t , t
R
20
F
BLAN
V
Output Low Voltage (I = 2mA)
0
0.4
V
V
OL
OL
V
OH
Output High Voltage (I = –0.2mA)
V
V
– 0.5
DD
OH
C
Load Capacitance
50
20
pF
ns
L
t , t
R
Rise and Fall Time (10 to 90%)
F
ODD/EVEN, STTV, L23, DV
V
OL
Output Low Voltage (I = 2mA)
0
0.5
V
V
OL
V
OH
Output High Voltage (I = –0.2mA)
– 0.8
V
DD
OH
DD
C
Load Capacitance
50
pF
ns
L
t , t
R
Rise and Fall Time (10 to 90%)
20
F
COR AND COR AND Y (with Pull up to V
)
DDD
V
Output Low Voltage (I = 2mA)
0
0.5
25
V
V
OL
OL
C
Load Capacitance
L
t
Fall Time (R = 1.2kΩ, V
– 0.5V to 1.5V)
50
ns
µs
F
L
DDD
I
Output Leakage Current
–10
0
+10
OLL
SDA
V
Output Low Voltage (I = 3mA)
0.5
200
400
V
OL
OL
t
F
Fall Time (3.0 to 1.0V)
Load Capacitance
ns
pF
C
L
Table 6. Crystal Oscillator
Symbol
Parameter
Min.
Typ.
13.875
1
Max.
Unit
MHz
MΩ
pF
f
Crystal Frequency
XTAL
R
Internal Bias Resistance
Input Capacitance
0.4
3
7
BIAS
C
I
5/30
STV5348 - STV5348/H - STV5348/T
Table 7. Timing
Symbol
Parameter
Min.
Typ.
Max.
Unit
SERIAL BUS (referred to V = 3V, V = 1.5V)
IH
IL
Clock:
● Low Period
● High Period
t
4
4
µs
µs
LOW
t
HIGH
t
t
Data Set-up Time
Data Hold Time
250
170
4
ns
ns
µs
µs
µs
µs
SU, DAT
HD, DAT
SU, STO
t
Stop Set-up Time from Clock High
Start Set-up Time following a Stop
Start Hold Time
t
4
BUF
t
t
4
HD, STA
Start Set-up Time following Clock Low to High Transition
4
SU, STA
Figure 4. Display Output Timing
LSP
(TCS)
40µs
0 4.66
64
R.G.B.Y
(1)
0
16.67
56.67
all timings in µs
(a) LINE RATE
s
lines 42 to 291 inclusive
(and 355 to 604 inclusive interlaced)
R.G.B.Y
(1)
0
41
291 312
line numbers
(b) FIELD RATE
6/30
STV5348 - STV5348/H - STV5348/T
Figure 5. Serial Bus Timing
SDA
t BUF
t LOW
t F
SCL
t HD,STA
t R
t HD,DAT
t HIGH
t SU,DAT
SDA
t SU,STA
t SU,STO
VIH = 3V , VIL = 1.5V
Figure 6. Master Synchronization Mode - Hardware Configuration
Output signal on STTV Pin :
POL grounded
Synchro
Extractor
1
Line PLL
Line PLL
VCS when R1D2 = 0
TCS when R1D2 = 1
MA/SL
VCS
R1D2 = "0"
TCS
R1D2 = "1"
POL to VDD
2
4
VCS when R1D2 = 0
TCS when R1D2 = 1
I2C
Control
+5V
Bit R1D2
POL
STTV
7/30
STV5348 - STV5348/H - STV5348/T
Figure 7. Master Synchronization Mode - Delivered Composite Synchronization Signal
VCS, TCS
(interlaced)
621
622
623
(310)
624
(311)
625
(312)
1
2
3
4
5
6
(308) (309)
VCS, TCS
(interlaced)
309
308
310
309
311
312
313
312
314
(1)
315
(2)
316
(3)
317
(4)
318
(5)
319
(6)
TCS
(non-interlaced)
310
311
1
2
3
4
5
6
The number positions indicate the end of lines.
Internal signals :
- VCS composite synchro from CVBS signal,
- TCS Teletext composite synchro.
Figure 8. Slave Synchronization Mode
MA/SL
LFB
+5V
2
4
5
6
SCS
POL
+5V
FFB
POL to VDD, Inputs Signals :
POL grounded, Inputs Signals :
are LFB line flyback synchro on Pin 5
FFB field flyback synchro on Pin 6
are LFB line flyback synchro on Pin 5
FFB field flyback synchro on Pin 6
or SCS synchro composite signal on Pins 5 and 6 or SCS synchro composite signal on Pins 5 and 6
Figure 9. Data Valid Timing (DV)
Field 0
Field 1
Field 0
DV for
VPS Data
Line 16
8/30
STV5348 - STV5348/H - STV5348/T
FUNCTIONAL DESCRIPTION
Displayable Page Memory Map
The organization of a page memory is shown in
Figure 10.
The display area consists of 25 rows of 40 charac-
ters per row.
to the "search mode" and the header appears
green.
– The following twenty-four characters give the
header of the requested page when the
system is in search mode.
– The last eight characters display the time of
day.
– Row number twenty-four is used by the
microprocessor for the display of information, or
used to display X/24 colored key data according
to R0D7 bit.
– Row twenty-five comprises ten bytes of control
data concerning the received page (see Table
9) and fourteen free bytes which can be used by
the microprocessor.
The organization is as follows:
– Row zero contains the page header:
– The first seven characters (0 - 6) are used for
messages regarding the operational status.
– The eighth character is an alphanumeric
control character either "white" or "green"
defining the "search" status of the page.
When it is "white" the operational state is
normal and the header appears white; when
it is "green" the operational state corresponds
Figure 10. Page Memory Organization
Fixed characters
Alphanumerics white
for normal,
green on search
7 Status
Characters
24 characters from page header
rolling on page search
8 scrolling
time characters
ROW
7
1
24
8
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
MAIN PAGE DISPLAY AREA
row free for status (R0D7 = 0) or packet X/24 (R0D7 = 1)
14
10
10 bytes for received
page information
14 bytes free
for use by
C
µ
9/30
STV5348 - STV5348/H - STV5348/T
Table 8. Ghost Row Storage Organization
Row Address Designation Row (Packet)
Function
of Stored Data
Code
0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 0
0 1 0 1
0 1 1 0
0 1 1 1
1 0 0 0
1 0 0 1
1 0 1 0
1 0 1 1
1 1 0 0
1 1 0 1
1 1 1 0
0 0 1 0
0 0 0 0
0 0 0 1
0 1 0 0
0 1 0 1
Number
0
1
2
3
4
5
6
7
X / 26
Enhanced display facilities
8
Page related data
stored in chapter
9
corresponding
level 1 data,
to
10
11
12
13
14
15
16
17
18
19
20
21
22
23
i.e. For 0 goes in 4
" 1
" 2
" 3
"
"
"
" 5
" 6
" 7
X / 28
X / 27
Conditional access
Editorial
Linked pages
Composition
X / 24
X / 25
X / 28
Page extension stored here if R0D7 = 0
Page extension
0 0 0 0
Color definition
(1)
(1)
X X X X
8 / 30
Broadcasting service data packet
24
0 0 0 1
X/28
Character set designation
(2)
Not used
25
Note: 1. Packet 8/30 storage: 8/30/0,1:
8/30/2,3:
chapter 4, row23
chapter 5, row23
8/30/4 to 15: chapter 6, row23
2. See Table 10 for VPS data storage.
10/30
STV5348 - STV5348/H - STV5348/T
Table 9. Row 25 Received Page Control Data Format
D0
D1
PU0
PU1
PU2
PU3
HAM
0
PT0
PT1
PT2
PT3
HAM
0
MU0
MU1
MU2
MU3
HAM
0
MT0
MT1
MT2
C4
HAM
0
HU0
HU1
HU2
HU3
HAM
0
HT0
HT1
C5
C6
HAM
0
C7
C8
C9
C10
HAM
0
C11
C12
C13
C14
HAM
0
MAG0
0
MAG1
0
D2
MAG2
0
D3
0
0
D4
FOUND
0
D5
0
0
0
8
PBLF
D6
0
0
0
0
0
0
0
0
0
0
9
D7
0
0
0
0
0
0
0
0
COLUMN
0
1
2
3
4
5
6
7
Page number : - MAG = magazine, PU = page units, PT = page tens.
Page sub-code : - MU = minutes units, MT = minutes tens, HU = hours units, HT = hours tens.
PBLF = page being looked for, FOUND = low for page found, HAM = hamming error in byte, C4-14 = control bits.
VPS DATA (see Table 10)
The automatic succession on a byte by byte basis
is indicated by the arrows in Table 10.
In the normal operating mode TB should be set to
logic level 0.
After power-up the contents of the registers are as
follows: all bits in registers R0 to R11A are cleared
to zero with the exception of bits D0 and D1 in reg-
isters R5 and R6 which are set to logical one.
VPS data are stored in row 25 chapter 5 as shown
in Table 10 when VPS enable bit (D4 of R8 regis-
ter) is set. VPS data bits are decoded and stored
in a received area with biphase error bit.
8/30/2 data are stored as received (without ham-
ming decoding) in Row 23 chapter 5 according to
Table 10.
8/30 packet and VPS data decoding is the respon-
sibility of the control software. The decoder simply
stores transmitted data.
I C Bus Register Map (see Table 11)
Registers R0 to R10 are write only whilst R11A is
a read/write and R11B is read only.
After power-up all the memory bytes are preset to
hexadecimal value 20H (space) with the exception
of the byte corresponding to row 0 of column 7 of
chapter 0 which is set to the value corresponding
to "alpha white" hexadecimal value 07H.
2
Table 10. PDC Data Storage
Column
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19
b13 b14 b15 b16 b17 b18 b19 b20 b21 b22 b23 b24 b25
Received Page Information B11 B12 B13 B14 B15
8/30/2 (Row 23)
VPS (Row 25)
D
Initial Page
Column
20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39
Status Display
8/30/2 (Row 23)
VPS (Row 25)
B4
B5
11/30
STV5348 - STV5348/H - STV5348/T
Table 11. Register Specification
D7
D6
D5
D4
D3
D2
D1
(1)
D0
X24
FREE
0
DISABLE (1)
ROLLING
HEADER
EVEN
OFF
SEL 11B
R0 Mode 0
POSITION RUNNING
PLL
(1)
7 + P/
8 BIT
ACQ.
ON/OFF
GHOST
ROW
ENABLE
DEW/
TCS
ON
T1
T0
R1 Mode 1
FULL
FIELD
(1)
BANK
SELECT
A2
ACQ.
CCT
A1
ACQ.
CCT
A0
TB
START
START
START
R2 Page request address
COLUMN COLUMN COLUMN
SC2
PRD2
A2
SC1
PRD1
A1
SC0
PRD0
A0
R3 Page request data
R4 Display chapter
(1)
(1)
(1)
(1)
(1)
(1)
PRD4
(1)
PRD3
(1)
R5 Display control
(normal)
BKGND
OUT
BKGND
IN
COR
OUT
COR
IN
TEXT
OUT
TEXT
IN
PON
OUT
PON
IN
BKGND
OUT
BKGND
IN
COR
OUT
COR
IN
TEXT
OUT
TEXT
IN
PON
OUT
PON
IN
R6 Display control
(newsflash / subtitle)
STATUS
ROW
CURSOR CONCEAL/ TOP/
SINGLE/
BOX ON
BOX ON
1-23
BOX ON
0
R7 Display mode
R8 Active chapter
ON/OFF
REVEAL
BOTTOM DOUBLE 24
HEIGHT
BTM/TOP
(1)
(1)
(1)
VPS
ENABLE
CLEAR
MEM.
A2
A1
A0
(1)
(1)
(1)
(1)
(1)
C5
R4
C4
R3
C3
R2
C2
R1
C1
R0
C0
R9 Active row
R10 Active column
D7
(R/W)
D6
(R/W)
D5
(R/W)
D4
(R/W)
D3
(R/W)
D2
(R/W)
D1
(R/W)
D0
(R/W)
R11A Active data
R11B Status
60Hz
0
0
0
0
0
DATA
QUAL
V
CS
QUAL
Note (1). Reserved register bits: must be set to 0.
12/30
STV5348 - STV5348/H - STV5348/T
Table 12. Registers Functions
Register
Function
Bit(s)
Description
SEL 11B (D0)
EVEN OFF (D2)
Selection of register 11B (D0 = 1) or 11A (D0 = 0)
Control of ODD/EVEN pin: EVEN signal output
(D2 = 0) or grounded (D2 = 1)
R0
Address
00H
DISABLE ROLLING
HEADER
D4 = 1, Disable rolling header
D4 = 0, Normal operation
R11 addressing and
pin functions control
FREE RUNNING
PLL (D6)
D6 = 0, PLL locks on line frequency
D6 = 1, to force free running mode
X/24 POSITION (D7) D7 = 0, packet X/24 stored to chapter 4 to 7/row 20
D7 = 1, packet X/24 stored to chapter 0 to 3/row 24
T1 (D1) T0 (D0)
Character display line control:
0
0
1
1
0
1
0
1
312.5/312.5 line MIX - mode with interlace
312/313 line TEXT - mode without interlace
312/312 line Terminal mode without interlace
External synchronization. SCS mode (scan field
synchro)
TCS ON (D2)
Master Mode (MA/SL Pin 2 = 0)
case POL Pin 4 = 0
D2 = 0, Pin 5 = VCS
D2 = 1, Pin 5 = TCS
Slave Mode (MA/SL Pin 2 = V
No effect
R1
Address
01H
)
Operating mode
controls
DD
DEW / FULLFIELD
(D3)
Selection of field flyback mode or full channel mode
(D3 = 1) for recovering of Teletext data.
GHOST ROW
ENABLE (D4)
Selection of ghost row mode (D4 = 1)
ACQUISITION
ON / OFF (D5)
Control of acquisition operation (D5 = 0 enables
acquisition)
7 bits + parity or 8 bits Selection of received data format either 7 bits with
without parity (D6)
parity (D6 = 0) or 8 bits without parity (D6 = 1).
SC0, SC1, SC2
(D0, D1, D2)
Address the first column of the on chip page request
RAM to be written.
TB (D3)
Test bit equal to "0" in the normal working mode.
R2
Address
02H
Addressing
information for
a page request
A0, A1 (D4, D5)
Address a group of four consecutive pages currently
used for data acquisition.
A2 (D6)
Address of one of the two groups of four pages for
acquisition in normal mode.
R3
Address
03H
Data relative to the
requested page
(see Table 10)
PRD0 - PRD4
(D0 - D4)
Written data in the page request RAM, starting with
the columns addressed by SC0, SC1, SC2.
R4
Address
04H
Selection of one of
eight pages to
display
A0, A1, A2
(D0, D1, D2)
Chapter selection.
13/30
STV5348 - STV5348/H - STV5348/T
Register
Function
Bit(s)
Description
Picture on (IN: D0, OUT: D1)
PON (D0, D1)
TEXT (D2, D3)
COR (D4, D5)
BKGND (D6, D7)
IN / OUT
Text on (IN: D2, OUT: D3)
R5
Address
05H
Display control for
normal operation
Contrast reduction on (IN: D4, OUT: D5)
Background color on (IN: D6, OUT: D7)
Enable inside/outside the box
R6
Address
06H
Display control for
news-flash subtitle
generation
See R5
See R5
BOX ON 0, 1-23,24
(D0, D1, D2)
The "boxing" function is enabled on row 0,1-23 and
24 by D0, D1 and D2 set to one.
TOP / BOTTOM
X0 = Normal
Single / Double Height 01 = double height Rows 0 to 11
R7
Address
07H
(D4/D3) 11 = double height Rows 12 to 23
Display mode
Conceal / Reveal (D5) Conceal Reveal Function
Cursor ON/OFF (D6) Cursor position given by row/column value of R9/R10
STATUS ROW
BTM / TOP (D7)
The row 24 is displayed before the "Main text Area"
(lines 0-23) or after (D7 = 0).
VPS Enable (D4)
D4 = 1 Enable VPS acquisition and DV signal output.
Clear Memory (D3)
D4 = 1 Clear memory.
Chapter selected with A2A1A0 (D2, D1, D0) R4.
R8
Memory access
Chapter Address
(D2, D1, D0)
Chapter selection
R9 to R11A
Address
Active row address (R9), active column address (R10).
Data contained in R11A read (written) from (to) memory by microprocessor via I C.
2
(1)
08H to 0BH
VCS QUAL (D0)
DATA QUAL (D1)
50/60Hz (D7)
Good VCS quality signal detected (D0 = 1).
Bad VCS quality signal detected (D0 = 0).
R11B
Good TELETEXT signal (D1 = 1).
Bad TELETEXT signal (D1 = 0).
Address
Status
(1)
0BH
If D1 = 0 frame frequency is 50Hz
(only valid with good VCS)
Note: 1. Reading of R11A or R11B is determined by register 0, bit D0. However, write operation is always performed on R11A register.
14/30
STV5348 - STV5348/H - STV5348/T
Table 13. Register R3
START
COLUMN
PRD4
PRD3
PRD2
PRD1
PRD0
0
1
2
3
4
5
6
Do care magazine
Do care page tens
Do care page units
Do care hours tens
Do care hours units
Do care minutes tens
Do care minutes units
HOLD
PT3
PU3
X
MAG2
PT2
PU2
X
MAG1
PT1
MAG0
PT0
PU1
HT1
PU0
HT0
HU3
X
HU2
MT2
MU2
HU1
MT1
MU1
HU0
MT0
MU0
MU3
The abbreviations have the same significance as in Table 9 with the exception of the "DO CARE" entries. It is only when this bit is "1"
that the corresponding digit is taken into consideration on page request. For example, a page defined as "normal" or one defined as
"timed" may be selected.
If "HOLD" is low the page is held. The addressing of successive bytes via the I2C is automatic.
Character Sets
The complete character set with 8-bit decoding is
given in Table 12.
Characters in columns 0 and 1 are normally dis-
played as blanks. Black dots represent the charac-
ter shape whereas white dots represent the
background.
Each character can be identified by a pair of corre-
sponding row and column integers: for example
the character "3" may be indicated by 3/3.
A rectangle may be represented as follows
The characters 8/6, 8/7, 9/5, 9/7 are used as spe-
cial characters, always in conjunction with 8/5.
The 13 national characters are placed in columns
with bit 8 = 0.
15/30
STV5348 - STV5348/H - STV5348/T
Table 14. STV5348 Complete Character Set (with 8 bit codes) - West European Languages
Case using C12 C13 C14 = 001 (German Set)
*
**
These control characters are reserved for compatibility with other data codes.
These control characters are presumed before each row begins
16/30
STV5348 - STV5348/H - STV5348/T
Table 15. STV5348/H Complete Character Set (with 8 bit codes) - East European Languages
Case using C12 C13 C14 = 001 (Rumanian Set)
*
**
These control characters are reserved for compatibility with other data codes.
These control characters are presumed before each row begins
17/30
STV5348 - STV5348/H - STV5348/T
Table 16. STV5348/T Complete Character Set (with 8 bit codes) - Turkish European Languages
Case using C12 C13 C14 = 001 (German Set)
*
**
These control characters are reserved for compatibility with other data codes.
These control characters are presumed before each row begins
18/30
STV5348 - STV5348/H - STV5348/T
The basic set of the 96 characters is shown in Ta-
ble 17. The location of the 13 national characters
are shown in Table 17 whilst full national character
sets are depicted in Table 18, 19 and 20.
Table 17. Basic character set.
National
National
2/0
2/1
3/0
3/1
4/0
4/1
5/0
5/1
6/0
6/1
7/0
7/1
Character
Character
2/2
3/2
4/2
5/2
6/2
7/2
National
2/3
3/3
4/3
5/3
6/3
7/3
Character
National
2/4
3/4
4/4
5/4
6/4
7/4
Character
2/5
3/5
4/5
5/5
6/5
7/5
2/6
3/6
4/6
5/6
6/6
7/6
2/7
3/7
4/7
5/7
6/7
7/7
2/8
3/8
4/8
5/8
6/8
7/8
2/9
3/9
4/9
5/9
6/9
7/9
2/10
2/11
2/12
2/13
2/14
2/15
3/10
3/11
3/12
3/13
3/14
3/15
4/10
4/11
4/12
4/13
4/14
4/15
5/10
5/11
5/12
5/13
5/14
5/15
6/10
6/11
6/12
6/13
6/14
6/15
7/10
7/11
7/12
7/13
7/14
7/15
National
National
Character
Character
National
National
Character
Character
National
National
Character
Character
National
National
Character
Character
National
Character
19/30
STV5348 - STV5348/H - STV5348/T
Table 18. STV5348 Character Set - West European Languages
Note: 1. Where PHCB are the Page Header Control bits. Other Combinations default to English. Only the above characters change with the
PHCB. All others characters in the basic set are shown in Table 14.
20/30
STV5348 - STV5348/H - STV5348/T
Table 19. STV5348/H Character Set -
East European Languages
Table 20. STV5348/T Character Set -
Turkish European Languages
Note: 1. Where PHCB are the Page Header Control bits. Other
Combinations default to German. Only the above charac-
ters change with the PHCB. All others characters in the
basic set are shown in Table 16.
Note: 1. Where PHCB are the Page Header Control bits. Other
Combinations default to Turkish. Only the above charac-
ters change with the PHCB. All others characters in the
basic set are shown in Table 16.
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STV5348 - STV5348/H - STV5348/T
Figure 11. Character Format
Alphanumerics and
Graphics 'space'
character
Alphanumerics or
blast-through
alphanumerics
character 4/8
Alphanumerics
character
2/13
Alphanumerics
character
7/15
2/0
Separated
graphics character
7/6
Separated
graphics character
7/15
Contiguous
graphics character
7/15
Contiguous
graphics character
7/6
Background
Display
=
=
Color
Color
22/30
STV5348 - STV5348/H - STV5348/T
I/O PIN ELECTRICAL SCHEMATICS
Figure 12. Analog 1 (CVBS)
Figure 15. Input D
VDDA
VDDD
450
Ω
Pins 4, 6
CVBS
1
250Ω
POL, FFB
VSSD
VSSA
Figure 13. Analog 2 (CBLK)
Figure 16. PRGB
VDDA
VDDD
RGB REF
11
CBLK
28
250Ω
450Ω
Pins
8, 9, 10
R, G, B
VSSD
VSSA
Figure 14. Input A
Figure 17.
VDDD
VDDA
450
Ω
XTI
24
450
Ω
XTO
23
450
Ω
Pins 2, 27
MA/SL, TEST
VSSD
VSSA
23/30
STV5348 - STV5348/H - STV5348/T
Figure 18. INOUT
Figure 20. PSDA
VDDD
VDDD
Pins 5, 12, 13, 14,
SDA
17
450Ω
450
Ω
15, 18, 19, 20, 21
STTV/LFB, BLAN, COR,
ODD/EVEN, Y, L23,
DV, RESERVED, VCR/TV
VSSD
VSSD
Figure 19. PSCL
VDDD
SCL
450Ω
16
VSSD
24/30
STV5348 - STV5348/H - STV5348/T
Figure 21. Application Diagram
0.1µ
F
0.1µF
1
2
CVBS
MA/SL
VDDA
POL
STTV/LFB
FFB
CBLK 28
TEST 27
VSSA 26
+5V
+5V
SL
MA
1µ
F
+5V
3
4
VSSO
25
C1*
C2*
5
XTI 24
13.875MHz
23
S
T
V
5
3
4
8
6
XTO
+5V
7
VSSD
VDDD
22
TV
VCR
+5V
8
R
VCR/TV 21
20
1 F
µ
10nF
9
G
47kΩ**
10
B
19
18
+5V
0.1 F
µ
11 RGB REF
12
13
14
BLAN
SDA 17
SCL 16
COR
ODD/EVEN
Y
15
* Value according to used crystal, C1 = C2 = 2 * C
LOAD
Example : C1 = C2 = 56pF, CLOAD = 30pF.
** Depending on application. Please refer to our video application lab.
Remark: all the power supply inputs must be switched on at the same time (connected to the same source).
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STV5348 - STV5348/H - STV5348/T
PART NUMBERING
Table 21. Order Codes
Part Number
STV5438
Package
PDIP28
PDIP28
PDIP28
SO28
Temperature Range
0 to 70 °C
West European
East European
STV5438/H
STV5348/T
STV5348D
STV5348D/T
0 to 70 °C
Turkish and European
West European
0 to 70 °C
0 to 70 °C
SO28
Turkish and European
0 to 70 °C
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STV5348 - STV5348/H - STV5348/T
PACKAGE MECHANICAL
Table 22. PDIP28 - 28 Pins - Plastic Dip - Mechanical Data
millimeters
Symbol
inches
Min
0.23
15.2
Typ
0.63
0.45
Max
Min
Typ
Max
a1
b
0.025
0.018
b1
b2
D
E
0.31
0.009
0.598
0.012
1.27
0.050
37.4
1.470
0.657
16.68
e
2.54
0.100
1.300
e3
F
33.02
14.1
0.555
I
4.445
3.3
0.175
0.130
L
Figure 22. PDIP28 - 28 Pins - Plastic Dip - Package Dimensions
Note: Drawing is not to scale
27/30
STV5348 - STV5348/H - STV5348/T
Table 23. SO28 - 28 Pins, Plastic Micropackage - Mechanical Data
millimeters
Symbol
inches
Typ
Min
Typ
Max
2.65
0.3
Min
Max
0.104
0.012
0.019
0.013
A
a1
b
0.1
0.004
0.014
0.009
0.35
0.23
0.49
0.32
b1
C
0.5
0.020
c1
D
45° (Typ)
17.7
10
18.1
0.697
0.394
0.713
0.419
E
10.65
e
1.27
0.050
0.65
e3
F
16.51
7.4
0.4
7.6
0.291
0.016
0.299
0.050
L
1.27
S
8° (Max)
Figure 23. SO28 - 28 Pins, Plastic Micropackage - Package Dimensions
Note: Drawing is not to scale
28/30
STV5348 - STV5348/H - STV5348/T
REVISION HISTORY
Table 24. Revision History
Date
Revision
Description of Changes
September-1998
28-May-2004
1
2
First Issue
Stylesheet update. No content change.
29/30
STV5348 - STV5348/H - STV5348/T
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
The ST logo is a registered trademark of STMicroelectronics.
All other names are the property of their respective owners
© 2004 STMicroelectronics - All rights reserved
STMicroelectronics GROUP OF COMPANIES
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