STV7619 [STMICROELECTRONICS]
DC PLASMA DISPLAY DRIVER, PQFP100, 14 X 14 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100;
| 型号： | STV7619 |
| 厂家： | 
ST |
| 描述： | DC PLASMA DISPLAY DRIVER, PQFP100, 14 X 14 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100 驱动 CD 接口集成电路 |
| 文件： | 总21页 (文件大小：186K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
®
STV7619DU
Scan Driver for Plasma Display Panels
Main Features
■ 64-output Scan Driver
■ 120 V Absolute Maximum Supply
■ 5 V Logic Supply
■ Optional 12 V Supply for driving the output
stage
■ 150mA/1A Source/Sink Output
■ 1 A Source/Sink Output Diode
■ 64-bit Bi-directional Shift Register (8 MHz)
■ BCD Technology
TQFP100 (14 x 14 x 1.4 mm Slug-down)
(Thin Plastic Quad Flat Pack)
■ 100-pin TQFP package with integrated
heatsink
ORDER CODE: STV7619D
Description
The STV7619 is a scan driver for plasma display
panels (PDP) implemented in ST’s proprietary BCD
(Bi-polar CMOS DMOS) technology. Using a 64-bit
cascadable 8 MHz shift register, it drives 64 high-
current and high-voltage outputs.
By connecting several STV7619 devices in series,
any vertical pixel definition can be performed. The
STV7619 is supplied with separate 110V power
output and 5 V logic supplies. The logic section of
the output stage is supplied either externally by a
5V or 12V supply or internally by a charge pump
cell. The choice of the supply value is related to the
PDP size. All command inputs are CMOS
compatible.
TQFP100 (14 x 14 x 1.4 mm)
(Thin Plastic Quad Flat Pack)
ORDER CODE: STV7619
The STV7619 package is a 100-pin TQFP with
integrated heatsink located on the bottom
(STV7619D) of the package. It is also available
without heatsink (STV7619).
August 2003
1/21
STV7619DU
Table of Contents
Chapter 1
Pin Allocation and Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
1.1
Pinout Diagrams ...............................................................................................................3
Chapter 2
Circuit Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Chapter 3
Application Hints: Charge Pump Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Power Supply .......................................................................................................................9
Sink Current Characteristics ..............................................................................................10
Recommendations .............................................................................................................10
3.1
3.2
3.3
Chapter 4
4.1
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Absolute Maximum Ratings ..............................................................................................11
Thermal Data ....................................................................................................................12
Supply Characteristics ....................................................................................................... 12
Power Output Characteristics ...........................................................................................13
SOUT Characteristics .......................................................................................................14
Input (CLK, STB, BLK, POC, SIN, CLR, F/R and ENABLE) Characteristics ....................14
AC Timing Requirements ...................................................................................................14
AC Timing Characteristics .................................................................................................15
4.2
4.3
4.4
4.5
4.6
4.7
4.8
Chapter 5
Chapter 6
Chapter 7
Input/Output Schematic Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Package Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
2/21
Pin Allocation and Descriptions
STV7619DU
1
Pin Allocation and Descriptions
1.1
Pinout Diagrams
Figure 1: STV7619 and STV7619D (TQFP100)
OUT4
1
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
OUT61
OUT60
OUT59
OUT5
2
OUT6
3
OUT7
4
OUT58
OUT57
OUT56
OUT55
OUT54
OUT53
OUT8
5
OUT9
6
OUT10
OUT11
OUT12
OUT13
OUT14
OUT15
OUT16
OUT17
OUT18
OUT19
OUT20
OUT21
OUT22
OUT23
OUT24
OUT25
OUT26
OUT27
OUT28
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
OUT52
OUT51
OUT50
OUT49
OUT48
TQFP100
(Top View)
OUT47
OUT46
OUT45
OUT44
OUT43
OUT42
OUT41
OUT40
OUT39
OUT38
OUT37
*NC: Not Connected
3/21
STV7619DU
Pin Allocation and Descriptions
Table 1: Supply Pins
Pin Description
Pin No.
Pin Name
88
84
33
34
42
43
79
97
36
40
83
30
31
45
46
81
82
94
95
37
39
VCC
VDD
5V Logic Supply
5/12V Internal/External Logic Supply
High Voltage Supply for Power Outputs
High Voltage Supply for Power Outputs
High Voltage Supply for Power Outputs
High Voltage Supply for Power Outputs
High Voltage Supply for Power Outputs
High Voltage Supply for Power Outputs
Logic Ground
VPP
VPP
VPP
VPP
VPP
VPP
VSSLOG
VSSLOG
VSSLOG
VSSP
VSSP
VSSP
VSSP
VSSP
VSSP
VSSP
VSSP
VSSSUB
VSSSUB
Logic Ground
Logic Ground
Ground for Power Outputs
Ground for Power Outputs
Ground for Power Outputs
Ground for Power Outputs
Ground for Power Outputs
Ground for Power Outputs
Ground for Power Outputs
Ground for Power Outputs
Substrate Ground
Substrate Ground
Table 2: Shift Register and Input Pins
Pin Description
Pin No.
Pin Name
38
85
86
87
89
90
91
92
93
ENABLE
SOUT
CLK
Enable Charge Pump mode
Shift Register Data Output
Clock for Shift Register Data
STB
Latch for Shift Register Data (Strobe Input)
Blanking Control for Power Outputs
Polarity Output Control
BLK
POC
SIN
Shift Register Data Input
CLR
Clear for Shift Register Data
F/R
Foward/Reserve modes for selecting Shift Register
4/21
Pin Allocation and Descriptions
STV7619DU
Table 3: Power Output Pins
Pin No.
Pin Name
Pin Description
Pin No.
Pin Name
Pin Description
Power Output 33
98
99
100
1
OUT1
OUT2
Power Output 1
Power Output 2
Power Output 3
Power Output 4
Power Output 5
Power Output 6
Power Output 7
Power Output 8
Power Output 9
Power Output 10
Power Output 11
Power Output 12
Power Output 13
Power Output 14
Power Output 15
Power Output 16
Power Output 17
Power Output 18
Power Output 19
Power Output 20
Power Output 21
Power Output 22
Power Output 23
Power Output 24
Power Output 25
Power Output 26
Power Output 27
Power Output 28
Power Output 29
Power Output 30
Power Output 31
Power Output 32
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
OUT33
OUT34
OUT35
OUT36
OUT37
OUT38
OUT39
OUT40
OUT41
OUT42
OUT43
OUT44
OUT45
OUT46
OUT47
OUT48
OUT49
OUT50
OUT51
OUT52
OUT53
OUT54
OUT55
OUT56
OUT57
OUT58
OUT59
OUT60
OUT61
OUT62
OUT63
OUT64
Power Output 34
Power Output 35
Power Output 36
Power Output 37
Power Output 38
Power Output 39
Power Output 40
Power Output 41
Power Output 42
Power Output 43
Power Output 44
Power Output 45
Power Output 46
Power Output 47
Power Output 48
Power Output 49
Power Output 50
Power Output 51
Power Output 52
Power Output 53
Power Output 54
Power Output 55
Power Output 56
Power Output 57
Power Output 58
Power Output 59
Power Output 60
Power Output 61
Power Output 62
Power Output 63
Power Output 64
OUT3
OUT4
2
OUT5
3
OUT6
4
OUT7
5
OUT8
6
OUT9
7
OUT10
OUT11
OUT12
OUT13
OUT14
OUT15
OUT16
OUT17
OUT18
OUT19
OUT20
OUT21
OUT22
OUT23
OUT24
OUT25
OUT26
OUT27
OUT28
OUT29
OUT30
OUT31
OUT32
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
5/21
STV7619DU
Pin Allocation and Descriptions
Table 4: Miscellaneous Pins
Pin Description
Pin No.
Pin Name
32
35
41
44
80
96
NC
NC
NC
NC
NC
NC
Not connected
Not connected
Not connected
Not connected
Not connected
Not connected
6/21
Circuit Description
STV7619DU
2
Circuit Description
Figure 2: Block Diagram
CLR
F/R
CLK
64-bit Shift Register
SOUT (SIN)
P
64
P1
SIN (SOUT)
S64
S1
Latch
STB
BLK
POC
Q1 Q2
Q63 Q64
VCC
VSSSUB
VSSP
VSSLOG
VPP
Voltage
Generator
Vcc
VDD
V
V
SSP
SSP
V
V
PP
PP
ENABLE
STV7619
OUT64
OUT1
The STV7619 includes all the necessary logic and power circuits to drive the rows of electrodes of
a plasma display panel (PDP). Data is shifted at each low to high transition of the (CLK) shift clock.
After 64 shifts, the first bit presented at the serial input (SIN) is available at the serial output (SOUT).
This output is used to cascade several drivers to perform any vertical resolution (Table 5). CLK,
STB, SIN and SOUT inputs are Schmitt trigger inputs.
Table 5: Shift Register Truth Table
F/R
CLK
SIN
SOUT
Comments
H
H
L
Rise
L or H
Rise
In
In
Out
Out
In
Forward Shift
Steady
Out
Out
Reverse Shift
Steady
L
L or H
In
In reverse mode (F/R = low), data is input on the SOUT pin and output on the SIN pin.
The clear signal (CLR) sets the shift register data to low.
Shift register outputs (P1, ... P64) are transferred from the shift register to the latch stage when the
latch input (STB) is at low level.
All the data is kept memorized in the latch stage when the strobe input (STB) is pulled high.
7/21
STV7619DU
Circuit Description
Driver outputs can be simultaneously polarized at high or low level depending on the biasing of the
POC input signal (Table 6).
Table 6: Output State Configuration
STB
CLR
POC
BLK
Comments
*
*
*
*
L
*
H
L
L
L
All at low level
All at high level
All at high level
H
H
H
H
L
L
H
H
L
*
Inverted copy of input data
Inverted copy of latched data
The STV7619 integrates a charge pump cell to manage the current drive capabilities of the output
sink transistor, as explained in Table 7. More details are given in Chapter 3.
Table 7: Voltage Generator Table
ENABLE
VDD
Output Performances
Minimum Sink Current mode
External Power Supply (V = 5V)
DD
L
External Power Supply (V = 12V)
Maximum Sink Current mode
DD
Internal Power Supply (Charge Pump mode)
V
connected to an external capacitance
H
Medium Sink Current mode
DD
(C
= 100nF (20V))
VDD
8/21
Application Hints: Charge Pump Function
STV7619DU
3
Application Hints: Charge Pump Function
3.1
Power Supply
The STV7619 is designed to drive panels up to 42” with low voltage logic supplies (pins VCC and
VDD). In this case, pin VDD must be connected to pin VCC. The driving of large panels (50”, 60”)
requires a 100 nF capacitor connected between pin VDD and the ground. An internal charge pump
provides a higher driving voltage for the low stage. If requested, higher performances are obtained
when a 12V power supply is directly connected to pin VDD.
The logic supply management of the output stage mainly depends on the write current value of the
plasma cells. The write current is related to the size of the PDP. The following figures illustrate the
different possibilities to supply the STV7619 according to the current drive performances requested
by the plasma panel.
Figure 3: External Power Supply (Small-size PDP)
110V
V
PP
V
CC
5V
STV7619
V
DD
ENABLE
Figure 4: External Power Supply (Large-size PDP)
110V
V
PP
V
CC
5V
STV7619
ENABLE
V
DD
12V
Figure 5: Internal Power Supply, Charge Pump mode (Medium- or Large-size PDP)
110V
V
PP
V
CC
5V
STV7619
V
ENABLE
DD
100nF
(16V)
9/21
STV7619DU
Application Hints: Charge Pump Function
3.2
Sink Current Characteristics
Figure 6: Typical Sink Stage Characteristics (Peak current and T
= 25 °C)
AMB
1400
1200
1000
800
600
400
200
0
Vgs =5V
Vgs =chpum p
Vgs =12V
0
5
10
15
20
25
30
Vpoutl(V)
3.3
Recommendations
The Sustain current must not be sunk in the power outputs to VPP when the power supply is
applied. VSSSUB and VSSLOG must be connected close to the logical reference ground of the
logic control signal buffers.
10/21
Electrical Characteristics
STV7619DU
4
Electrical Characteristics
4.1
Absolute Maximum Ratings
Symbol
Parameter
Value
Units
V
V
Logic Supply
-0.3, +7
-0.3, +14
-0.3, +120
V
V
V
V
V
V
CC
DD
Logic supply of power part
Output Pins
OUTi
V
-0.3, V +0.3
Logic Input Voltage
Logic Output Voltage
IN
CC
V
-0.3, V + 0.3
OUT
CC
V
Driver Output Voltage (scanning mode)
-0.3, +120
POUT
ESD Susceptibility (Human Body model: 100 pF capacitor discharged through
1.5 kΩ serial resistor) (See Note 1)
V
±2200
V
ESD
I
Driver Output Current (See Note 2, Note 5 and Note 6)
Diode Output Current (See Note 3 and Note 5)
Diode Output Current (See Note 4 and Note 5)
Junction Temperature
-150 mA/+1.2
±1
A
A
POUT
I
I
DOUT1
DOUT2
±700
mA
°C
°C
°C
T
+150
JMAX
T
Operating Temperature
-20, +85
-20, +150
OPER
T
Storage Temperature
STG
Note:1. All pins in relation to VCC = -1500V
2. Through one power output.
3. Through one diode
4. Through all power outputs (see test diagram): with power dissipation lower than or equal to Ptot and
Junction temperature lower than or equal to Tjmax and VPP = VSSP.
5. These parameters are measured during ST’s internal qualification which includes temperature
characterisation on standard batches and on corners batches of the process. These parameters are
not tested on the parts.
6. For VDD = 9 V, IPOUT = 1.0 A, for VDD = 5 V, IPOUT = 0.5 A
11/21
STV7619DU
Electrical Characteristics
4.2
Thermal Data
Symbol
Parameter
Value
Units
T
Maximum Operating Junction
125
20
°C
JOPER
R
R
R
Junction-ambient Thermal Resistance (See Note 1)
Junction-ambient Thermal Resistance (See Note 2)
Junction-ambient Thermal Resistance (See Note 3)
°C/W
°C/W
°C/W
thJA
thJA
thJA
40
29
Note:1. For TQFP100 packaging with slug soldered on printed circuit board.
2. TQFP soldered on 4-layer printed circuit board.
3. For TQFP100 packaging with slug not soldered on printed circuit board.
4.3
Supply Characteristics
(VSSP = 0 V, VSSLOG = 0 V, VSSSUB = 0 V, TAMB = 25°C and fCLK = 8 MHz, unless otherwise
specified)
Symbol
Parameter
Logic Supply Voltage
Test Conditions
Min.
Typ.
Max. Units
V
V
4.5
5
5.5
13
V
V
V
CC
DD
V
Logic Supply Voltage for Output Stage
Power Output Supply Voltage
CC
V
20
110
PP
with V =5 or 12 V
DD
100
2
µA
(ENABLE=L)
with pump charge capacitor
(ENABLE=H)
I
Logic Supply Current
CCH
0.3
mA
mA
µA
I
f
= 8 MHz
Dynamic Logic Supply Current
TBD
CCL
CLK
I
Power Output Supply Current (steady outputs)
100
PPH
12/21
Electrical Characteristics
STV7619DU
4.4
Power Output Characteristics
Symbol
Parameter
Test Conditions
Min.
Typ.
Max. Units
Power Output High Level
(Voltage drop versus V
V
I
= - 60 mA
TBD
4.2
V
POUTH
POUTH
)
PP
V
V
=12V (ENABLE = L)
=5V (ENABLE = L)
2.5
3.4
TBD
TBD
V
V
DD
DD
Power Output Low Level voltage drop
= +400 mA
V
POUTL
I
POUTL
pump charge capacitor on
2.8
TBD
V
V
V
V
(ENABLE = H)
DD
DD
DD
=12 V (ENABLE = L)
= 5V (ENABLE= L)
TBD
TBD
1100
530
mA
mA
Power Output Low Level Peak current
=12 V (See Note 1)
I
V
POULP
POUTL
(Pulse ≤ 500ns)
pump charge capacitor on
TBD
1000
mA
V
(ENABLE = H)
DD
V
I
= +400 mA
Output Diode High Level (See Note 2 and Note 3)
Output Diode Low Level (See Note 2 and Note 3)
1.8
3.0
V
V
DOUTH
DOUTH
DOUTL
V
I
= - 400 mA
-1.25
-3.00
DOUTL
Note:1. Peak current - Pulse mode 720 Hz - 0.2%. Duty cycle.
2. Compatible with power dissipation and TJOPER ≤ 125°C.
3. See Figure 8: Test Configuration on page 17.
13/21
STV7619DU
Electrical Characteristics
4.5
SOUT Characteristics
Symbol
Parameter
Logic Output High Level
Logic Output Low Level
Test Conditions
= -1 mA
Min.
Typ.
Max. Units
V
I
I
4.2
4.6
0.1
V
OH
OH
V
= +1 mA
0.4
V
OL
OL
4.6
Input (CLK, STB, BLK, POC, SIN, CLR, F/R and ENABLE) Characteristics
Symbol
Parameter
Test Conditions
Min.
Typ.
Max. Units
V
0.8 V
Input High Level
Input Low Level
V
IH
CC
V
0.2V
CC
V
IL
I
V
V
V
= V
High Level Input Current
±10
±10
µA
IH
IH
IL
IL
CC
Low Level Input Current for pins CLK, SIN, STB,
CLR, BLK and POC
I
= 0 V
= 0 V
µA
µA
IL
I
Low Level Input Current for ENABLE pin
-25
IL
4.7
AC Timing Requirements
VCC = 4.5 V to 5.5 V, TAMB = -20 to +85°C, max. leading/trailing edge for input signals (tr, tf) = 10 ns
Symbol
Parameter
Duration of clock (CLK) pulse at high level
Min.
Typ.
Max. Units
t
40
40
10
20
25
10
20
100
ns
ns
ns
ns
ns
ns
ns
ns
WHCLK
t
Duration of clock (CLK) pulse at low level
WLCLK
t
Set-up Time of data input before clock (low to high) transition
Hold Time of data input after clock (low to high) transition
Minimum Delay to latch STB after clock (low to high) transition
Set-up Time STB before clock (low to high) transition
Latch STB Low Level Pulse Duration
SDAT
t
HDAT
t
DSTB
t
SSTB
t
STB
t
Blanking (BLK) Pulse Duration
BLK
14/21
Electrical Characteristics
STV7619DU
4.8
AC Timing Characteristics
Symbol
Parameter
Min.
Typ.
Max. Units
t
Data Clock Period
125
CLK
t
Logical Data Output Rise Time
Logical Data Output Fall Time
25
15
RDAT
t
FDAT
PHL1
Delay of logic data output (high to low transition) after clock (CLK) transition
(CL=10pF)
t
45
50
Delay of logic data output (low to high transition) after clock (CLK) transition
(CL=10 pF)
t
ns
PLH1
t
t
t
t
t
t
Delay of power output change (high to low transition) after clock (CLK) transition
Delay of power output change (low to high transition) after clock (CLK) transition
Delay of power output change (high to low transition) after Latch (STB) transition
Delay of power output change (low to high transition) after Latch (STB) transition
Delay of power output change (high to low transition) to POC transition
Delay of power output change (low to high transition) to POC transition
Power Output Rise Time (See Note 1)
TBD
TBD
TBD
TBD
105
100
100
30
180
180
165
165
160
160
ns
ns
ns
ns
ns
ns
ns
ns
PHL2
PLH2
PHL3
PLH3
PHL4
PLH4
t
ROUT
t
Power Output Fall Time (See Note 1)
FOUT
Note:1. One output among 64, loading capacitor COUT = 200 pF, other outputs at low or high level.
15/21
STV7619DU
Electrical Characteristics
Figure 7: AC Characteristics Waveform
tCLK
tWLCLK
tWHCLK
"1"
CLK
SIN
50%
50%
50%
"0"
tSDAT
tHDAT
"1"
50%
50%
"0"
tPHL1
tFDAT
"1"
"0"
10%
10%
90%
90%
SOUT
50%
tRDAT
tPLH1
tDSTB
STB
tSSTB
"1"
STB
50%
50%
"0"
tPHL2
90%
tPHL3
90%
"1"
"0"
OUTn
10%
10%
tPLH2
tPLH3
tBLK
"1"
POC
50%
tPLH4
50%
"0"
"1"
tPHL4
90%
90%
OUTn
10%
10%
"0"
tROUT
tFOUT
16/21
Electrical Characteristics
STV7619DU
Figure 8: Test Configuration
V
V
V
V
PP= SSP
PP= SSP
V
I
DOUTH
DOUTH
V
I
DOUTL
DOUTL
V
SSP
V
SSP
Output sinking current as positive value, sourcing current as negative value.
17/21
STV7619DU
Input/Output Schematic Diagrams
5
Input/Output Schematic Diagrams
Figure 9: ENABLE Input
Figure 11: SIN, SOUT Input
V
V
CC
CC
V
CC
V
CC
SIN, SOUT
V
CC
ENABLE
V
SSLOG
V
SSLOG
V
SSLOG
V
SSLOG
V
SSLOG
Figure 10: F/R, CLR, CLK, STB, BLK and POC Inputs
Figure 12: Power Outputs
V
CC
V
CC
V
PP
BLK, POC, F/R
CLK, STB, CLR
OUT1 to OUT64
V
SSLOG
V
V
SSLOG
SSP
18/21
Package Mechanical Data
STV7619DU
6
Package Mechanical Data
Figure 13: TQFP100 Package
D
A
D1
D3
Seating
Plane
A2
C
A1
75
51
50
76
ccc
C
e
H
S1
E3 E1 E
B
0.25mm
.010 inch
Gage Plane
Pin 1
Identification
26
100
25
1
C
K
TQFP100M
L
S
L1
Millimeters
Typ.
Inches
Dimensions
Min.
Max.
Min.
Typ.
Max.
A
A1
A2
B
1.60
0.15
1.45
0.27
0.20
0.063
0.006
0.057
0.011
0.008
0.05
1.35
0.17
0.09
0.002
0.053
0.007
0.004
1.40
0.22
0.055
0.009
C
D
16.00
14.00
12.00
0.50
0.630
0.551
0.472
0.20
D1
D3
e
E
16.00
14.00
12.00
0.60
0.630
0.551
0.472
0.024
0.039
E1
E3
L
L1
K
0.45
0.75
0.018
0.030
1.00
0° (Min.), 7° (Max.)
Slug Dimension For L/Frame Pad Size 10.00 x 10.00 mm
H
S
S1
9.85
0.388
8.80
8.80
0.346
0.346
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STV7619DU
Revision History
7
Revision History
Table 8: Summary of Modifications
Description
Version
Date
Target Specification
1.0
1.1
1.2
1.3
April 2001
First version issued
April 2001
May 2001
May 2001
Corrections from the design
Corrections in Table 1 and text added in Circuit description
Inversion of BLK and POC pinsin block diagram and Table 1.
Product Preview
Pin connections - pins 30 to 50 corrected, Pin assignements: completed, Block diagram: voltage
generator added, Circuit description: text modified, Application hints chapter added, Electrical
characteristics: few precisions, Input/output schematics: corrections
September
2.0
2.1
2001
Pin connections - pins 38 added to pin description, Electrical characteristics: I and I typical
IH
IL,
October
2001
value is ±10, AC timing characteristics: t
and t
: (BLK) replaced with (POC), Figure 5: AC
PHL4
PLH4
characteristics waveform: STB and OUTn waveforms replaced, BLK renamed with POC.
Page 10 - C value replaced with 100 nF (1 previously), Page 11 - figure 3 - C value
VDD
VDD
replaced with 100 nF, Page 12 - Figure 4 replaced. Sentence modified in subsection 7.3
recommendations: the logical reference ground “of the application” replaced with “of the logic
control signal buffers”. Page 13 - absolute maximum ratings - Ioutput value replaced with -150mA/
+1.2A. Note removed. Page 14- Electrical characteristics: values replaced. Page 15 - AC timing
charactersitics: values replaced
November
2001
2.2
2.3
January
2002
Electrical characteristics: First sentence: Vpp and Vdd removed, in the table: Vpp moved after Vdd.
Preliminary Data
Reformatted datasheet. Deletion of STV7619U (Slug-up) device and related information.
Modification of values in Note 6 on page 11. Addition of Note 3 on page 12. Update of typical
24 July
2002
2.4
values in Section 4
.
13 January
2003
Addition of V information in Section 4.1: Absolute Maximum Ratings on page 11
.
2.5
Datasheet
3.0
ESD
August
2003
Published on internet.
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STV7619DU
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such
information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication
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© 2003 STMicroelectronics - All Rights Reserved
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