STV8162 [STMICROELECTRONICS]
+5 V, +5 V and +8 V Triple-Voltage Regulator with Disable and Reset Functions; + 5V ， + 5V和+ 8V三重电压调节器禁用和复位功能
| 型号： | STV8162 |
| 厂家： | 
ST |
| 描述： | +5 V, +5 V and +8 V Triple-Voltage Regulator with Disable and Reset Functions |
| 文件： | 总12页 (文件大小：172K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
®
STV8162 - STV8162D
+5 V, +5 V and +8 V Triple-Voltage Regulator
with Disable and Reset Functions
DATASHEET
Key Features
■ Input Voltage range between 7 V and 18 V
■ Output Currents up to 600 mA
■ Fixed Precision Output 1 voltage of 5 V ± 2%
■ Fixed Precision Output 2 voltage of 5 V ± 2%
■ Fixed Precision Output 3 voltage of 8 V ± 2%
■ Output 1 with Reset facility
Clipwatt 11
Order Code: STV8162
■ Outputs 2 and 3 can be disabled by digital input
■ Short Circuit Protection on each output
■ Thermal Protection
■ Low Dropout Voltages
DESCRIPTION
The STV8162 and STV8162D are monolithic triple
positive voltage regulators designed to provide three
fixed precision output voltages of 5 V, 5 V and 8 V for
currents up to 0.6 A.
Power DIP 18 (9 + 9)
Order Code: STV8162D
An internal reset circuit generates a reset pulse
when the voltage of Output 1 drops below the
regulated voltage value.
Outputs 2 and 3 can be disabled by a digital input.
Short-circuit and thermal protections are included in
all versions.
GROUND
GROUND
GROUND
GROUND
GROUND
GROUND
GROUND
GROUND
GROUND
9
8
7
6
5
4
3
2
1
10
11
12
13
14
15
16
17
18
DISABLE
INPUT3
11
10
9
8
7
6
5
4
3
NC
DISABLE
INPUT3
OUTPUT3
INPUT2
GROUND
OUTPUT2
INPUT1
Top View
OUTPUT3
INPUT2
OUTPUT2
INPUT1
OUTPUT1
DELAY CAPACITOR
RESET
OUTPUT1
DELAY CAPACITOR
RESET
2
1
February 2004
1/12
GENERAL INFORMATION
STV8162 - STV8162D
1
GENERAL INFORMATION
Figure 1: STV8162 Block Diagram
DELAY CAPACITOR
2
RESET
1
3
Reference
4
7
OUTPUT1
OUTPUT2
INPUT1
INPUT2
Regulator 1
Protections
5
Regulator 2
Regulator 3
6
OUTPUT3
9
8
INPUT3
DISABLE
10
Not Connected
11
GROUND
Figure 2: STV8162D Block Diagram
DELAY CAPACITOR
2
RESET
1
3
Reference
4
6
OUTPUT1
INPUT1
INPUT2
Regulator 1
Protections
5
7
Regulator 2
Regulator 3
OUTPUT2
OUTPUT3
INPUT3
8
9
DISABLE
GROUND
Pins 10 to 18
2/12
STV8162 - STV8162D
Electrical Characteristics
2
Electrical Characteristics
2.1
Absolute Maximum Ratings
Symbol
Parameter
DC Input Voltage at pins INPUT1, INPUT2 and INPUT3
Disable Input Voltage at pin DISABLE
Output Voltage at pin RESET
Output Currents
Value
Unit
VIN
VDIS
VRST
IOUTPUT
Pt
20
20
V
V
V
20
Internally Limited
Internally Limited
-65 to +150
0 to +150
Power Dissipation
TSTG
TJ
Storage Temperature
°C
°C
Junction Temperature
2.2
Thermal Data
Symbol
Parameter
Value
Unit
Junction-to-Case Thermal
Resistance
STV8162
STV8162D
3
15
RthJC
°C/W
Junction-to-Ambient Thermal
Resistance 1
STV8162
STV8162D
O10
56
RthJA
°C/W
TJ
Maximum Recommended Junction Temperature
Operating Free Air Temperature Range
140
°C
°C
TOPER
0 to +70
1. Mounted on board. For more information, refer to Section 5.
2.3
Electrical Characteristics
T
= 25° C, V
= 7 V, V
= 7 V and V
= 10 V, unless otherwise specified.
IN3
AMB
IN1
IN2
Symbol
Parameter
Output Voltage
Test Conditions
IOUT1 = 10 mA
Min.
Typ.
Max.
Unit
VOUT1
VOUT2
VOUT3
4.90
4.90
7.84
5.00
5.00
8.00
5.10
5.10
8.16
V
V
V
IOUT2 = 10 mA
IOUT3 = 10 mA
Output Voltage
Output Voltage
7 V < VIN1 < 12 V
VOUT1
VOUT2
VOUT3
Output Voltage
Output Voltage
Output Voltage
4.80
4.80
7.68
5.20
5.20
8.32
V
V
V
5 mA < IOUT1 < 600 mA
7 V < VIN2 < 12 V
5 mA < IOUT2 < 600 mA
10 V < VIN3 < 15 V
5 mA < IOUT3 < 600 mA
3/12
Electrical Characteristics
STV8162 - STV8162D
Symbol
VIO1
Parameter
Dropout Voltage
Test Conditions
IOUT1 = 0.6 A
Min.
Typ.
Max.
Unit
1
1
1
1.4
1.4
1.4
V
V
V
VIO2
IOUT2 = 0.6 A
Dropout Voltage
Dropout Voltage
VIO3
IOUT3 = 0.6 A
7 V < VIN1 < 12 V,
VOUT1LI
VOUT2LI
VOUT3LI
Line Regulation
Line Regulation
Line Regulation
50
50
80
mV
mV
mV
IOUT1 = 200 mA
7 V < VIN2 < 12 V,
OUT2 = 200 mA
I
10 V < VIN3 < 15 V,
OUT3 = 200 mA
I
VOUT1LO
VOUT2LO
VOUT3LO
5 mA < IOUT1 < 600 mA
5 mA < IOUT2 < 600 mA
5 mA < IOUT3 < 600 mA
Load Regulation
Load Regulation
Load Regulation
100
100
160
mV
mV
mV
IOUT1 = 10 mA
IQ
Quiescent Current
2.2
3.0
mA
Outputs 2 and 3 disabled
VO1RST
VRTH
K = VOUT1
Reset Threshold Voltage
K-0.4
30
K-0.25
75
K-0.10
120
V
Reset Threshold Hysteresis
See circuit description.
mV
Ce = 100 nF
tRD
VRL
IRH
Reset Pulse Delay
25
ms
V
See circuit description.
Saturation Voltage in Reset
Condition
IRESET = 5 mA
0.4
10
Leakage Current in Normal
Condition, at RESET pin
VRESET = 10 V
ꢀA
TJ = 0 to 125°C
ꢁVOUT ꢂ 106
KOUT1
KOUT2
KOUT3
Output Voltage Thermal Drift
100
ppm/°C
--------------------------------
=
KOUT
ꢁT ꢂ VOUT
IOUT1SC
IOUT2SC
IOUT3SC
VDISH
VDISL
VIN1 = 7 V
VIN1 = 7 V
Short Circuit Output Current
Short Circuit Output Current
Short Circuit Output Current
0.8
0.8
0.8
2
1.3
1.3
1.3
1.8
1.8
1.8
A
A
VIN3 = 10 V
A
Voltage High Level at DISABLE pin (Outputs 2 and 3 active)
Voltage Low Level at DISABLE pin (Outputs 2 and 3 disabled)
V
0.8
2
V
IDIS
0 V < VDISABLE < 7 V
Bias Current at DISABLE pin
-100
ꢀA
°C
°C
TJSD
Junction Temperature for Thermal Shutdown
Thermal Shutdown Temperature Hysteresis
150
15
TSDH
4/12
STV8162 - STV8162D
Circuit Description
3
Circuit Description
The STV8162 and STV8162D are triple-voltage regulators with Reset and Disable functions.
The three regulation parts are supplied from a single voltage reference circuit trimmed by zener
zapping during EWS testing. Since the supply voltage of this voltage reference is connected to pin
INPUT1 (V ), the second and third regulators will not work if pin INPUT1 is not supplied.
IN1
The output stages are designed using a Darlington configuration with a typical dropout voltage of
1.0 V.
IMPORTANT: In all applications, all three inputs must be polarized. If Outputs 2 or 3 are not used, the
corresponding inputs must be connected to Input 1.
The Disable circuit will switch off pins OUTPUT2 and OUTPUT3 if a voltage less than 0.8 V is
applied to pin DISABLE.
The Reset circuit checks the voltage at pin OUTPUT1. If this voltage drops below V
-0.25 V
OUT1
(4.75 V Typ.), the "a" comparator (Figure 3) rapidly discharges the external capacitor (Ce) and the
reset output immediately switches to low. When the voltage at pin OUTPUT1 exceeds
V
-0.175 V (4.825 V Typ.), the V voltage increases linearly to the reference voltage (V
=
OUT1
Ce
REF
2.5 V) corresponding to a Reset Pulse Delay (t ) as shown in Figure 4.
RD
Ce P 2.5V
-------------------------
=
tRD
10ꢀA
Afterwards, the reset output returns to high. To avoid glitches in the reset output, the second
comparator "b" has a large hysteresis (1.9 V).
5/12
Application Diagrams
STV8162 - STV8162D
4 Application Diagrams
Figure 3: Reset Diagram
10 µA
RESET
b
VREF
a
-
+
+
-
OUTPUT1
3
REG
Ce
VREF
0.6V
VREF = 2.5 V
Figure 4: Internal Reset Voltage
VOUT1
K
VO1RST
VRTH
RESET
K = Actual Value of VOUT1
tRD
tRD
Power Off
Power On
6/12
STV8162 - STV8162D
Application Diagrams
Figure 5: STV8162 Typical Application
C1 to C6 = 10 µF
0.1 µF
Ce
1
2
DELAY
CAPACITOR
RESET
VOUT1
VOUT2
VIN1
VIN2
VIN3
INPUT1
OUTPUT1
3
4
7 INPUT2
OUTPUT2
OUTPUT3
5
8
VOUT3
9
INPUT3
C4
C5
C6
C2
C1
C3
GROUND
6
DISABLE
10
NC
11
Figure 6: STV8162D Typical Application
C1 to C6 = 10 µF
0.1 µF
Ce
1
2
DELAY
CAPACITOR
RESET
VOUT1
VOUT2
VIN1
4 INPUT1
6 INPUT2
OUTPUT1
3
VIN2
VIN3
OUTPUT2
OUTPUT3
5
7
VOUT3
8
INPUT3
C4
C5
C6
C2
C3
GROUND
Pins
DISABLE
C1
9
10 to 18
7/12
Power Dissipation and Layout Indications
STV8162 - STV8162D
5
Power Dissipation and Layout Indications
The power is mainly dissipated by the three device buffers. It can be calculated by the equation:
P = (V -V ) x I + (V -V ) x I + (V -V ) x I
IN1 OUT1
OUT1
IN2 OUT2
OUT2
IN3 OUT3
OUT3
The following table lists the different R
values of these packages with or without a heat sink and
thJA
the corresponding maximum power dissipation assuming:
■ Maximum Ambient Temperature = 70° C
■ Maximum Junction Temperature = 140° C
R
thJA in °C/W
PMAX in W
Device
Heat Sink
No
Yes
No
50
15
1.4
4.6
STV8162
56 to 40
32
1.25 to 1.75
2.2
STV8162D
Yes
Figure 7: Thermal Resistance (Junction-to-Ambient) of DIP18 Package without Heat Sink
To optimize the thermal conductivity of the copper
layer and the exchanges with the air, the solder
must cover the maximum amount of this area.
60
55
50
Test Board with
“On Board” square heat sink area.
45
40
6
0
2
4
8
10
12
Copper area (cm²) (35 µm plus solder) Board is face-down
Figure 8: Metal plate mounted near the STV8162D for heat sinking
Top View
Bottom View
8/12
STV8162 - STV8162D
Package Mechanical Data
6
Package Mechanical Data
Figure 9: 11-pin Plastic Clipwatt Package
H3
C
A
H1
B
E
G
F
G1
M1 M
mm
Inches
Dim.
Min.
Typ.
Max.
Min.
Typ.
Max.
A
B
3.20
1.05
0.126
0.041
C
0.15
1.50
0.55
0.006
0.059
0.002
D
E
0.49
0.80
1.57
0.019
0.031
0.062
F
0.91
1.83
0.036
0.072
G
1.70
12.00
18.60
0.067
0.480
0.732
H1
H2
H3
L
19.85
10.70
0.781
0.421
17.90
14.45
11.00
5.50
0.700
0.569
0.433
0.217
0.100
0.100
L1
L2
L3
M
11.20
0.441
2.54
M1
2.54
Number of Pins
11
N
9/12
Package Mechanical Data
STV8162 - STV8162D
Figure 10: 18-pin Plastic Dual In-line Power Package
E
A2
A1
A
L
c
b2
e
b
eB
D1
b3
D
18
1
10
9
E1
mm
Inches
Typ.
Dim.
Min.
Typ.
Max.
Min.
Max.
A
A1
A2
b
5.33
0.210
0.38
2.92
0.36
1.14
0.76
0.20
22.35
0.13
0.015
0.115
0.014
0.045
0.030
0.008
0.880
0.005
3.30
0.46
1.52
0.99
0.25
22.86
4.95
0.56
1.78
1.14
0.36
23.37
0.130
0.018
0.060
0.039
0.010
0.900
0.195
0.022
0.070
0.045
0.014
0.920
b2
b3
c
D
D1
e
2.54
0.100
eB
E
10.92
8.26
7.11
3.81
0.430
0.325
0.280
0.150
7.62
6.10
2.92
7.87
6.35
3.30
0.300
0.240
0.115
0.310
0.250
0.130
E1
L
10/12
STV8162 - STV8162D
Revision History
7
Revision History
Table 1: Summary of Modifications
Main Changes
Version
Date
0.2
0.3
January 2000
First Edition
November 2002
Addition of PDIP18 package.
11/12
Revision History
NOTES:
STV8162 - STV8162D
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the
consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its
use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications
mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously
supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without
express written approval of STMicroelectronics.
The ST logo is a registered trademark of STMicroelectronics
All other names are the property of their respective owners
© 2004 STMicroelectronics - All rights reserved
STMicroelectronics GROUP OF COMPANIES
Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy
- Japan - Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States
www.st.com
12/12
相关型号：
STV8162D
+5 V, +5 V and +8 V Triple-Voltage Regulator with Disable and Reset Functions
STMICROELECTR
STV8162_09
+5 V, +5 V and +8 V triple voltage regulator with disable and reset functions
STMICROELECTR
STV8163
+3.3 V, +5 V and Adjustable Triple-Voltage Regulator with Disable and Reset Functions
STMICROELECTR
STV8164
+5 V, +5 V and Adjustable Triple-Voltage Regulator with Disable and Reset Functions
STMICROELECTR
STV8172A
Vertical Deflection Booster for 3-APPTV/Monitor Applications with 70-V Flyback Generator
STMICROELECTR
©2020 ICPDF网 联系我们和版权申明