STW5098BBLR/LF [STMICROELECTRONICS]
Dual low power asynchronous stereo audio Codec with integrated power amplifiers; 双路低功耗异步立体声音频编解码器，集成功率放大器
| 型号： | STW5098BBLR/LF |
| 厂家： | 
ST |
| 描述： | Dual low power asynchronous stereo audio Codec with integrated power amplifiers |
| 文件： | 总86页 (文件大小：946K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
34ꢀ.80 7IRELESS
IMPORTANT NOTICE
Dear customer,
nd
As from August 2 2008, the wireless operations of STMicroelectronics have moved to a
new company, ST-NXP Wireless.
As a result, the following changes are applicable to the attached document.
●
●
Company name - STMicroelectronics NV is replaced with ST-NXP Wireless.
Copyright - the copyright notice at the bottom of the last page “© STMicroelectronics
200x - All rights reserved”, shall now read: “© ST-NXP Wireless 200x - All rights
reserved”.
●
●
Web site - http://www.st.com is replaced with http://www.stnwireless.com
Contact information - the list of sales offices is found at http://www.stnwireless.com
under Contacts.
If you have any questions related to the document, please contact our nearest sales office.
Thank you for your cooperation and understanding.
ST-NXP Wireless
34ꢀ.80 7IRELESS
www.stnwireless.com
STw5098
Dual low power asynchronous stereo audio Codec
with integrated power amplifiers
Features
■ Dual 20 bit audio resolution, 8kHz to 96kHz
independent rate ADC and DAC
■ Dual I2S or PCM digital interfaces for dual
STw5098
master
■ Sustain complex voice and audio flow with or
without mixing
■ I2C/SPI compatible control I/F
■ Asynchronous sampling ADC and DAC: they
do not require oversampled clock and
information on the audio data sampling
frequency (fs). Jitter tolerant fs
LFBGA 6x6x1.4 (112 pins)
VFBGA 5x5x1 (112 pins)
■ Wide master clock range: from 4MHz to 32MHz
■ Stereo headphones drivers, handsfree
Description
loudspeaker driver, line out drivers
■ Mixable analog line inputs
STw5098 is a dual low power asynchronous
stereo audio CODEC device with headphones
amplifiers for high quality audio listening and
recording.
■ Voice filters: 8/16kHz with voice channel filters
■ Automatic gain control for microphone and line-
in inputs
Two I2S/PCM digital interfaces are available, one
per master for example Bluetooth and Application
Processor, enabling concurrent audio and voice
flow between Network and user.
■ Frequency programmable clock outputs
■ Multibit Σ∆ modulators with data weighted
averaging ADC and DAC
■ DSP functions for bass-treble-volume control,
mute, mono/stereo selection, voice channel
filters, de-emphasis filter and dynamic
compression
The STw5098 control registers are accessible
through a selectable I2C-bus compatible or SPI
compatible interface.
■ 93 dB dynamic range ADC, 0.001% THD with
full scale output @ 2.7V
■ 95 dB dynamic range DAC, 0.02% THD
performance @ 2.7V over 16Ω load
Applications
■ Digital cellular telephones with application
processor such as mp3 or gaming and
Bluetooth concurrent application
April 2007
Rev 1
1/85
www.st.com
1
Contents
STw5098
Contents
1
2
3
4
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.1
4.2
4.3
4.4
4.5
4.6
4.7
4.8
4.9
Naming convention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Device programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Power up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Master clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Data rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Clock generators and master mode function . . . . . . . . . . . . . . . . . . . . . . 20
Audio digital interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Analog inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
4.10 Analog output drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
4.11 Analog mixers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
4.12 AD paths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
4.13 DA paths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
4.14 Analog-only operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
4.15 Automatic Gain Control (AGC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
4.16 Interrupt request: IRQ pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
4.17 Headset plug-in and push-button detection . . . . . . . . . . . . . . . . . . . . . . . 26
4.18 Microphone biasing circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
5
Control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
5.1
5.2
5.3
5.4
5.5
Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Supply and power control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Gains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
DSP control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Analog functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
2/85
STw5098
Contents
5.6
5.7
5.8
5.9
Digital audio interfaces master mode and clock generators . . . . . . . . . . . 41
Digital audio interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Digital filters, software reset and master clock control . . . . . . . . . . . . . . . 45
Interrupt control and control interface SPI out mode . . . . . . . . . . . . . . . . 46
5.10 AGC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
6
Control interface and master clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
6.1
6.2
6.3
Control interface I2C mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Control interface SPI mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Master clock timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
7
8
9
Audio interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Timing specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Operative ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
9.1
9.2
9.3
9.4
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Operative supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Typical power dissipation by entity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
10
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
10.1 Digital interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
10.2 AMCK with sinusoid input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
10.3 Analog interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
10.4 Headset plug-in and push-button detector . . . . . . . . . . . . . . . . . . . . . . . . 64
10.5 Microphone bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
10.6 Power supply rejection ratio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
10.7 LS and EAR gain limiter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
11
Analog input/output operative ranges . . . . . . . . . . . . . . . . . . . . . . . . . 66
11.1 Analog levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
11.2 Microphone input levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
11.3 Line output levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
11.4 Power output levels HP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
3/85
Contents
STw5098
11.5 Power output levels LS and EAR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Stereo audio ADC specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Stereo audio DAC specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
AD to DA mixing (sidetone) specifications . . . . . . . . . . . . . . . . . . . . . . 71
Stereo analog-only path specifications . . . . . . . . . . . . . . . . . . . . . . . . 72
ADC (TX) & DAC (RX) specifications with voice filters selected . . . . . 73
Typical performance plots . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
12
13
14
15
16
17
18
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
18.1 LFBGA 6x6x1.4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
18.2 VFBGA 5x5x1.0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
19
20
21
Application schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
4/85
STw5098
List of tables
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
STw5098 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Control register summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
CR0 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
CR1 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
CR2 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
CR3 and CR4 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
CR5 and CR6 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
CR7 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
CR8 and CR9 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
CR10 and CR11 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
CR12 and CR13 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
CR14 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
CR15 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
CR16 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
CR17 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
CR18 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
CR19 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
CR21-20 and CR24-23 description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
CR22 and CR25 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
CR26 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
CR27 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
CR28 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
CR29 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
CR30 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
CR31 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
CR32 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
CR33 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
CR 34 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
CR 35 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Control interface timing with I²C format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Control interface signal timing with SPI format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
AMCK timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Audio interface signal timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Operative supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Typical power dissipation, no master clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Typical power dissipation with master clock AMCK = 13 MHz . . . . . . . . . . . . . . . . . . . . . . 61
Digital interfaces specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
AMCK with sinusoid input specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Analog interface specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Headset plug-in and push-button detector specifications. . . . . . . . . . . . . . . . . . . . . . . . . . 64
Microphone bias specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Power supply rejection ratio specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
LS and EAR gain limiter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Reference full scale analog levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Microphone input levels, absolute levels at pins connected to preamplifiers . . . . . . . . . . . 66
Microphone input levels, absolute levels at pins connected to the line-in amplifiers . . . . . 66
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
Table 26.
Table 27.
Table 28.
Table 29.
Table 30.
Table 31.
Table 32.
Table 33.
Table 34.
Table 35.
Table 36.
Table 37.
Table 38.
Table 39.
Table 40.
Table 41.
Table 42.
Table 43.
Table 44.
Table 45.
Table 46.
Table 47.
Table 48.
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List of tables
STw5098
Table 49.
Table 50.
Table 51.
Table 52.
Table 53.
Table 54.
Table 55.
Table 56.
Table 57.
Table 58.
Table 59.
Table 60.
Absolute levels at OLP/OLN, ORP/ORN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Absolute levels at HPL - HPR. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Absolute levels at 1EARP-1EARN and 2LSP - 2LSN. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Stereo audio ADC specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Stereo audio DAC specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
AD to DA mixing (sidetone) specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Stereo analog-only path specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
ADC (TX) & DAC (RX) specifications with voice filters selected. . . . . . . . . . . . . . . . . . . . . 73
Dimensions of LFBGA 6x6x1.4 112 4R11x11. 0.5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Dimensions of VFBGA 5x5x1.0 112 balls 0.4 mm pitch . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
6/85
STw5098
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Pin assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
STw5098 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Power up block diagram: example shown for one entity . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Plug-in and push-button detection application note . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Control interface I2C format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Control interface: I2C format timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Control interface SPI format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Control interface: SPI format timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Audio interfaces formats: delayed, left and right justified . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Figure 10. Audio interfaces formats: DSP, SPI and PCM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Figure 11. Audio interface timings: master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Figure 12. Audio interface timing: slave mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Figure 13. A.C. testing input-output waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Figure 14. Bass treble control, de-emphasis filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Figure 15. Dynamic compressor transfer function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Figure 16. ADC audio path measured filter response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Figure 17. ADC in band audio path measured filter response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Figure 18. DAC digital audio filter characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Figure 19. DAC in band digital audio filter characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Figure 20. ADC 96 kHz audio path measured filter response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Figure 21. ADC 96 kHz audio in-band measured filter response. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Figure 22. ADC voice TX path measured filter response. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Figure 23. ADC voice TX path measured in-band filter response . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Figure 24. DAC voice (RX) digital filter characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Figure 25. DAC voice (RX) in-band digital filter characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Figure 26. ADC path FFT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Figure 27. ADC S/N versus input-level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Figure 28. DAC path FFT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Figure 29. DAC S/N versus input-level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Figure 30. Analog path FFT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Figure 31. Analog path S/N versus input-level. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Figure 32. LFBGA 6x6x1.4 112 4R11x11 0.5 drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Figure 33. VFBGA 5x5x1.0 112 0.4 drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Figure 34. STw5098 application schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
7/85
Overview
STw5098
1
Overview
●
●
●
●
●
Dual 20 bit audio resolution, 8kHz to 96kHz independent rate ADC and DAC
Dual I2S/PCM digital interfaces for dual master
Sustain complex voice and audio flow with or without mixing
Two I2C/SPI compatible independent control interfaces
Asynchronous sampling ADC and DAC that do not require oversampled clock and
information on the audio data sampling frequency (fs). Jitter tolerant fs
●
●
●
●
●
●
Wide master clock range from 4MHz to 32MHz
Two stereo headphones drivers, hand free loudspeaker driver, line out drivers
Mixable analog line inputs
Voice filters: 8/16kHz with voice channel filters
Automatic gain control for microphone and line-in inputs
Four programmable master/slave serial audio data interfaces: I2S, SPI, PCM
compatible and other formats
●
●
●
Frequency programmable clock outputs
Multibit Σ∆ modulators with data weighted averaging ADC and DAC
Four DSP functions for bass-treble-volume control, mute, mono/stereo selection, voice
channel filters, de-emphasis filter and dynamic compression
●
●
93 dB dynamic range ADC, 0.001% THD with full scale with full scale output @ 2.7V
95 dB dynamic range DAC, 0.02% THD performance @ 2.7V over 16Ω load
Analog inputs
●
Selectable stereo differential or single-ended microphone amplifier inputs with 51dB
range programmable gain
●
●
●
2 microphone biasing output
Microphone plug-in and push-button detection input
Selectable stereo differential or single-ended line inputs with 38dB range
programmable gain
Analog output drivers
●
2 Stereo headphones outputs. driving capability: 40mW (0.1% THD) over 16Ω with
40dB range programmable gain
●
●
Common mode voltage headphones driver (phantom ground)
1 Balanced loudspeaker output with driving capability up to 500mW (VCCLS>3.5V; 1%
THD) over 8Ω with 30dB range programmable gain
●
●
●
1 Balanced earphone output with driving capability up to 125mW
Transient suppression filter during power up and power down
Balanced/unbalanced stereo line outputs with 1 kΩ driving capability
8/85
STw5098
2
Pinout
Pinout
Figure 1.
Pin assignment
1
2
3
4
5
6
7
8
9
10
11
GND
1SCLK
1AD_OCK
2SDA/SDIN
1DA_OCK
1AD_CK
2AS/CSB
2AD_DATA
2AD_SYNC
1DA_SYNC
1DA_DATA
A
B
C
D
E
F
G
H
J
2HDET
VCCA
2SCLK
1HDET
2AD_OCK
VCCA
1CMOD
2CMOD
VCC
2DA_OCK
1SDA/SDIN
VCCIO
2DA_CK
2AD_CK
1DA_CK
AMCK
VCC
2DA_SYNC
2DA_DATA
2MBIAS
GND
1AD_DATA
1AS/CSB
1AD_SYNC
2IRQ
1MBIAS
2AUX1R
2MICRN
2MICRP
2AUX1L
2AUX3L
2CAPMIC
1AUX1L
1AUX3L
1CAPMIC
1MICLN
1MICLP
GNDA
1IRQ
VCCA
1AUX1R
2AUX3R
1AUX3R
2MICLN
2MICLP
2CAPLINEIN
1CAPLINEIN
1MICRN
1MICRP
1AUX2LN
1AUX2LP
1OLN
2AUX2LN
2AUX2LP
1OLP
1LINEINL
2OLN
2LINEINL
GNDCM
2HPL
GNDA
1HPR
1AUX2RP
2ORN
1AUX2RN
2LINEINR
1ORN
2AUX2RN
2AUX2RP
1LINEINR
1EARPS
1EARP
VCCP
2OLP
1VCMHP
1CAPEAR
1EARN
VCCLS
2ORP
GNDCM
VCCP
VCCP
GNDP
1HPL
2VCMHPS
2VCMHP
VCCLS
2LSPS
GNDP
2LSP
GNDP
1EARNS
VCCLS
2LSNS
1ORP
VCCP
GNDP
2HPR
K
L
1VCMHPS
2CAPLS
2LSN
9/85
Pinout
STw5098
Table 1.
STw5098 pin description
Type Pin name
GND
Position
Description
Ground pin for the digital section
A1
A2
A3
P
DI
DO
1SCLK
Control interface serial clock input
1AD_OCK
Oversampled clock out from AD clock generator
Control interface serial data input-output in I2C mode (SDA), control
interface serial data input in SPI mode (SDIN).
A4
DIOD
2SDA/SDIN
A5
A6
DO
1DA_OCK
1AD_CK
Oversampled clock out from DA clock generator
DIO
Serial data clock for stereo A/D converter
Control interface address select in I2C mode (AS).
Interface enable signal in SPI mode (CSB).
A7
DI
2AS/CSB
A8
DO
DIO
DIO
DI
2AD_DATA
2AD_SYNC
1DA_SYNC
1DA_DATA
Serial data out for stereo A/D converter
Frame sync for stereo A/D converter
Frame sync for stereo D/A converter
Serial data In for stereo D/A converter
A9
A10
A11
Headset detection input
(microphone plug-in and push-button detection)
B1
AI
2HDET
B2
B3
B4
B5
B6
DI
2SCLK
Control interface serial clock input
DO
DI
2AD_OCK
1CMOD
Oversampled clock out from AD clock generator
Control interface type selector I2C-bus mode or SPI mode
Oversampled clock out from DA clock generator
Serial data clock for stereo D/A converter
DO
DIO
2DA_OCK
2DA_CK
Master clock input. Accepted range 4 MHz to 32 MHz.
AMCK is a digital square wave
B7
B8
DI
AI
AMCK
VCC
AMCK is an analog sinewave (Section 10.2 on page 62)
Power supply pin for the digital section.
Operating range: from 1.71 V to 2.7 V
P
B9
DIO
DI
2DA_SYNC
2DA_DATA
GND
Frame sync for stereo D/A converter
Serial data in for stereo D/A converter
Ground pin for the digital section
B10
B11
P
Power supply pin for the analog section.
Standard operating range: from 2.7V to 3.3V
Low voltage (LV) range: from 2.4V to 2.7V
C1
C2
P
VCCA
Headset detection input
(microphone plug-in and push-button detection)
AI
1HDET
Power supply pin for the analog section.
Standard operating range: from 2.7V to 3.3V
Low voltage (LV) range: from 2.4V to 2.7V
C3
C4
P
VCCA
DI
2CMOD
Control interface type selector I2C-bus mode or SPI mode.
10/85
STw5098
Pinout
Table 1.
Position
STw5098 pin description
Type
Pin name
Description
Control interface serial data input-output in I2C mode (SDA). Control
interface serial data input in SPI mode (SDIN).
C5
DIOD
1SDA/SDIN
C6
C7
C8
C9
C10
C11
D1
D2
D3
DIO
DO
DIO
DO
AO
AO
AI
2AD_CK
1AD_DATA
1AD_SYNC
2IRQ
Serial data clock for stereo A/D converter
Serial data out for stereo A/D converter
Frame sync for stereo A/D converter
Programmable interrupt output. Active low signal.
Microphone biasing pin. Fixed voltage reference
Microphone biasing pin. Fixed voltage reference
Left and right channel single ended pins for microphone or line input
Left and right channel single ended pins for microphone or line input
Left and right channel differential pins for microphone input
2MBIAS
1MBIAS
2AUX1L
1AUX1L
1MICLN
AI
AI
Power supply pin for the digital section.
Operating range: from 1.71V to 2.7V
D4
P
VCC
Power supply pin for the digital I ⁄ O buffers.
Operating ranges: from 1.2V to 1.8V and from 1.71V to VCC
D5
D6
D7
D8
P
VCCIO
1DA_CK
1AS/CSB
1IRQ
DIO
DI
Serial data clock for stereo D/A converter
Control interface address select in I2C mode (AS)
Interface enable signal in SPI mode (CSB)
DO
Programmable interrupt output. Active low signal.
Power supply pin for the analog section.
Standard operating range: from 2.7V to 3.3V
Low voltage (LV) range: from 2.4V to 2.7V
D9
P
VCCA
D10
D11
E1
AI
AI
AI
AI
AI
AI
AI
AI
AI
AI
AI
AI
P
1AUX1R
2AUX1R
2AUX3L
1AUX3L
1MICLP
2MICLN
2CAPLINEIN
1MICRN
2AUX3R
2MICRN
2CAPMIC
1CAPMIC
GNDA
Left and right channel single ended pins for microphone or line input
Left and right channel single ended pins for microphone or line input
Left and right channel single ended pins for microphone or line input
Left and right channel single ended pins for microphone or line input
Left and right channel differential pins for microphone input
Left and right channel differential pins for microphone input
A capacitor must be connected between CAPLINEIN and ground
Left and right channel differential pins for microphone input
Left and right channel single ended pins for microphone or line input
Left and right channel differential pins for microphone input
A capacitor must be connected between CAPMIC and ground.
A capacitor must be connected between CAPMIC and ground
Ground pin for the analog section
E2
E3
E4
E8
E9
E10
E11
F1
F2
F3
F4
AI
2MICLP
Left and right channel differential pins for microphone input
11/85
Pinout
STw5098
Table 1.
STw5098 pin description
Position
Type
Pin name
Description
F8
AI
AI
AI
AI
AI
AI
AI
AI
P
1CAPLINEIN
1MICRP
A capacitor must be connected between CAPLINEIN and ground
Left and right channel differential pins for microphone input
Left and right channel single ended pins for microphone or line input
Left and right channel differential pins for microphone input
Left and right channel differential pins for microphone or line input
Left and right channel differential pins for microphone or line input
Left and right channel single ended pins for line input
F9
F10
F11
G1
G2
G3
G4
G8
G9
G10
G11
H1
1AUX3R
2MICRP
1AUX2LN
2AUX2LN
1LINEINL
2LINEINL
GNDA
Left and right channel single ended pins for line input
Ground pin for the analog section
AI
AI
AI
AI
AI
1AUX2RP
1AUX2RN
2AUX2RN
1AUX2LP
2AUX2LP
Left and right channel differential pins for microphone or line input.
Left and right channel differential pins for microphone or line input
Left and right channel differential pins for microphone or line input
Left and right channel differential pins for microphone or line input
Left and right channel differential pins for microphone or line input
H2
Audio differential line out amplifier for left and right channels. This
outputs can drive up to 1kΩresistive load. Can be used as single
ended output.
H3
H4
H5
AO
P
2OLN
Ground pin for analog reference.
GNDCM
1EARPS
GNDCM can be connected to GNDA
EARPS, EARNS (sense) pins must be connected on the application
board to EARP, EARN pins respectively. The connection must be as
close as possible to the pins.
AO
Analog differential loudspeaker amplifier output for left channel or
right channel or the sum of both. This output can drive 50nF (with
series resistor) or directly an earpiece transductor from 8Ω. to 32Ω.
Can deliver from 500mW to 125mW.
H6
AO
1EARP
Power supply pin for the left and right output drivers (headphones
and line-out). Operating range: from VCCA to 3.3V
H7
H8
P
VCCP
1HPR
Audio single ended headphones amplifier outputs for left and right
channels. The outputs can drive 50nF (with series resistor) or
directly an earpiece transductor of 16Ω.
AO
Audio differential line out amplifier for left and right channels. This
outputs can drive up to 1kΩresistive load. Can be used as single
ended output.
H9
AO
2ORN
H10
H11
AI
AI
2LINEINR
2AUX2RP
Left and right channel single ended pins for line input
Left and right channel differential pins for microphone or line input
Audio differential line out amplifier for left and right channels. This
outputs can drive up to 1kΩresistive load. Can be used as single
ended output.
J1
AO
1OLN
12/85
STw5098
Pinout
Table 1.
Position
STw5098 pin description
Type Pin name
Description
Audio differential line out amplifier for left and right channels. This
outputs can drive up to 1kΩresistive load. Can be used as single
ended output.
J2
J3
J4
AO
AO
AO
1OLP
Audio differential line out amplifier for left and right channels. This
outputs can drive up to 1kΩresistive load. Can be used as single
ended output.
2OLP
2HPL
Audio single ended headphones amplifier outputs for left and right
channels. The outputs can drive 50nF (with series resistor) or
directly an earpiece transductor of 16Ω.
Common mode voltage headphones output. The negative pins of
headphones left and right speakers can be connected to this pin to
avoid decoupling capacitors.
J5
J6
AO
AI
1VCMHP
1CAPEAR
A capacitor can be connected between this node and ground
Analog differential loudspeaker amplifier output for Left channel or
Right channel or the sum of both. This output can drive 50nF (with
series resistor) or directly an earpiece transductor from 8Ω to 32Ω.;
It can deliver from 500mW to 125mW.
J7
AO
1EARN
Power supply pin for the mono differential output driver. Operating
range: from VCCA to 5.5V
J8
J9
P
VCCLS
2ORP
Audio differential line out amplifier for left and right channels. This
outputs can drive up to 1kΩresistive load. Can be used as single
ended output.
AO
Audio differential line out amplifier for left and right channels. This
outputs can drive up to 1kΩresistive load. Can be used as single
ended output.
J10
AO
1ORN
J11
K1
AI
P
1LINEINR
GNDCM
Left and right channel single ended pins for line input
Ground pin for analog reference.
GNDCM can be connected to GNDA
Power supply pins for the left and right output drivers (headphones
and line-out).
K2
K3
K4
P
VCCP
Operating range: from VCCA to 3.3V
Audio single ended headphones amplifier outputs for left and right
channels. The outputs can drive 50nF (with series resistor) or
directly an earpiece transductor of 16Ω.
AO
AO
1HPL
VCMHPS (sense) pin must be connected on the application board to
VCMHP pin. The connection must be as close as possible to the
pins.
2VCMHPS
Power supply pin for the mono differential output driver. Operating
range: from VCCA to 5.5V
K5
K6
K7
P
P
P
VCCLS
GNDP
GNDP
Ground pin for the left, right and mono-differential output drivers.
GNDP and GNDA must be connected together.
Ground pin for the left, right and mono-differential output drivers.
GNDP and GNDA must be connected together.
13/85
Pinout
STw5098
Table 1.
STw5098 pin description
Type Pin name
Position
Description
EARPS, EARNS (sense) pins must be connected on the application
board to EARP, EARN pins respectively. The connection must be as
close as possible to the pins.
K8
AO
P
1EARNS
Power supply pins for the mono differential output driver. Operating
range: from VCCA to 5.5V
K9
VCCLS
1ORP
GNDP
Audio differential line out amplifier for left and right channels. This
outputs can drive up to 1kΩresistive load. Can be used as single
ended output.
K10
K11
AO
P
Ground pin for the left, right and mono-differential output drivers.
GNDP and GNDA must be connected together.
Power supply pin for the left and right output drivers (headphones
and line-out).
L1
L2
L3
P
VCCP
Operating range: from VCCA to 3.3V
Ground pin for the left, right and mono-differential output drivers.
GNDP and GNDA must be connected together.
P
GNDP
VCMHPS (sense) pin must be connected on the application board to
VCMHP pin. The connection must be as close as possible to the
pins.
AO
1VCMHPS
Common mode voltage headphones output. The negative pins of
headphones left and right speakers can be connected to this pin to
avoid decoupling capacitors.
L4
L5
AO
AO
2VCMHP
2LSPS
LSPS, LSNS (sense) pins must be connected on the application
board to LSP, LSN pins respectively. The connection must be as
close as possible to the pins.
Analog differential loudspeaker amplifier output for Left channel or
Right channel or the sum of both. This output can drive 50nF (with
series resistor) or directly an earpiece transductor of 8Ω.; It can
deliver up to 500mW.
L6
L7
L8
AO
AI
2LSP
2CAPLS
2LSN
A capacitor can be connected between this node and ground
Analog differential loudspeaker amplifier output for Left channel or
Right channel or the sum of both. This output can drive 50nF (with
series resistor) or directly an earpiece transductor of 8Ω. Can deliver
up to 500mW.
AO
LSPS, LSNS (sense) pins must be connected on the application
board to LSP, LSN pins respectively. The connection must be as
close as possible to the pins.
L9
AO
P
2LSNS
VCCP
2HPR
Power supply pin for the left and right output drivers (headphones
and line-out). Operating range: from VCCA to 3.3V
L10
L11
Audio single ended headphones amplifier outputs for left and right
channels. The outputs can drive 50nF (with series resistor) or
directly an earpiece transductor of 16Ω.
AO
14/85
STw5098
Pinout
Type definitions
AI
-
-
-
-
-
-
-
-
Analog input
AO
AIO
DI
Analog output
Analog input output
Digital input
DO
DIO
DIOD
P
Digital output
Digital input output
Digital input output open drain
Power supply or ground
15/85
Block diagram
STw5098
3
Block diagram
Figure 2.
STw5098 block diagram
MIXMIC2
MIXLIN2
ADLIN2
ADMIC2
1 N I L A D
1 C I M A D
1 N I L X M I
1 C I M X M I
16/85
STw5098
Functional description
4
Functional description
4.1
Naming convention
The STw5098 is composed of two identical entities, with their respective set of control
registers.
Regarding the pin labelling, a pin name preceded by 1 refers to entity 1 and a pin name
preceded by 2 refers to entity 2 (ie.g. 1SCLK, 2SCLK). In the following sections, no
distinction is made between the two entities when it is not relevant. Consequently, the 1 and
2 prefixes for entities 1 and 2 respectively are omitted. The same naming convention applies
to the control registers (CRxxx).
4.2
Power supply
STw5098 can have different supply voltages for different blocks, to optimize performance,
power consumption and connectivity. See Section 9.2 on page 59 for voltage definition.
The correct sequence to apply supply voltage is to set first (and unset last) the digital I/O
supply (VCCIO). The other supply voltages can be set in any order and can be disconnected
individually, if needed. Disconnection does not cause any harm to the device and no extra
current is pulled from any supply during this operation. Moreover if a voltage conflict is
detected, like VCCA < VCC (not allowed), simply all blocks connected to VCCA are set to
power down and no extra current is pulled from supply.
When VCCIO is set and VCC (digital supply) is not set, all the digital output pins are in high
impedance state, while the digital inputs are disconnected to avoid power consumption for
any input voltage value between GND and VCCIO. Before VCC is disconnected the device
has to be reset (SWRES bit in CR30).
When the analog supply (VCCA) is set and VCC is not set, all the analog inputs are in high
impedance state.
The two sets of control registers are powered by VCC pins (digital supply) so if these pins
are disconnected all the information stored in control registers is lost. When the digital
supply voltage is set, a power-on-reset (POR) circuit sets all the registers content to the
default value and then generates IRQ signals writing 1 in bits PORMSK end POREV in
CR31 and CR32 respectively for both entities.
All supplies must be on during operation.
17/85
Functional description
STw5098
4.3
Device programming
STw5098 can be programmed by writing Control Registers with SPI or I2C compatible
control interface (both slave). The interface is always active, there is no need to have the
master clock running to program the device registers. The control interfaces of each entity
can be operated independently either in SPI or I2C modes.
The choice between the two interfaces for each entity is done via their input pins 1CMOD
and 2CMOD (CMOD):
1. CMOD connected to GND: I2C compatible mode selected
The device address is selected with AS pin:
AS/CSB connected to GND:
AS/CSB connected to VCCIO
chip address 00110101(35hex) for reading, 00110100 (34hex) for writing
chip address 00110111(37hex) for reading, 00110110 (36hex) for writing
:
When this mode is selected control registers are accessed through pins:
SCLK (clock)
SDA (serial data out/in, open drain)
2. CMOD connected to VCCIO: SPI compatible mode selected
When this mode is selected control registers are accessed through:
AS/CSB (chip select, active low)
SCLK (clock)
SDIN (serial data in)
AD_OCK or DA_OCK or IRQ (serial data out, if selected)
Device Programming: I2C. The I2C Control Interface timing is shown in Section 6.1 on
page 50. The interface has an internal counter that keeps the current address of the control
register to be read or written. At each write access of the interface the address counter is
loaded with the data of the register address field. The value in the address counter is
increased after each data byte read or write. It is possible to access the interface in 2
modes: single-byte mode in which the address and data of a single register are specified,
and multi-byte mode in which the address of the first register to be written or read is
specified and all the following bytes exchanged are the data of successive registers starting
from the one specified (in multi-byte mode the internal address counter restart from register
0 after the last register 36). Using the multi-byte mode it is possible to write or read all the
registers with a single access to the device on the I2C bus. This applies to both entities of
the device.
Device Programming: SPI. The SPI Control Interface timing is shown in section
Section 6.2 on page 51. Bits SPIOSEL (SPI Output Select) in CR33 control the out pin
selection for serial data out (none, AD_OCK, DA_OCK or IRQ), while bit SPIOHIZ=1 in
CR33 selects the high impedance state of serial data out pin when idle. The first bit sent on
SDIN, after AS/CSB falling edge, sets the interface for writing (SDIN=1) or reading
(SDIN=0), then a 7-bit Control Register address follows.
If the interface is set for writing then the last 8 bits on SDIN are written in the control register.
If the interface is set for reading then after the 7 bit address STw5098 sends out 8 bits data
on the pin selected with bits SPIOSEL in CR33, while bits present at SDIN pin are ignored.
If SPIOSEL=00 (no out pin selected) the reading access on SPI interface can still be useful
to clear the IRQ event bits in CR32.
18/85
STw5098
Functional description
4.4
Power up
STw5098 internal blocks can individually be switched on and off according to the user
needs. A general power-up bit is present at bit 7 of CR0. The output drivers should always
be powered up after the general power up. See the following drawing to select the needed
block for the desired function. A fast-settling function is activated to quickly charge external
capacitors when the device is switched on (CAPLS, CAPLINEIN and CAPMIC).
Figure 3.
Power up block diagram: example shown for one entity
POWERUP
ENANA
ENHSD
MBIAS
ENMICL
ENMICR
ENLINL
ENLINR
ENADCL
ENADCR
STw5098
ENADCKGEN
ADMAST ENADOCK
ENLOL
ENHPL
AUDIO I/F
DAMAST ENDAOCK
ENMIXL
ENMIXL
ENLS
ENDACL
ENDACR
ENDACKGEN
ENPLL
ENHPR
ENLOR
ENAMCK
ENOSC
ENOSC=0
ENOSC=1
ENHPVCM
4.5
Master clock
Master clock is applied to both entities. The master clock pin (AMCK) accepts any frequency
from 4 MHz to 32 MHz. The 4-32 MHz range is divided in sub-ranges that have to be
programmed in bits CKRANGE in CR30. The jitter and spectral properties of this clock have
a direct impact on the DAC and ADC performance because it is used to directly or by integer
division drive the continuous-time to sampled-time interfaces.
19/85
Functional description
STw5098
Note that AMCK clock does not need to have any relation to any other digital or analog input
or output.
AMCK can be either a square wave or a sinewave, bit AMCKSIN in CR30 selects the proper
input mode. When a sinewave is used as input, AMCK pin must be decoupled with a
capacitor. Specification for sinusoid input can be found in Section 10.2 on page 62.
The AMCK clock is not needed when only analog functions are used. For this purpose an
internal oscillator with no external components can be used to operate the device (see
Section 4.14 on page 25).
4.6
Data rates
STw5098 supports any data rate in 2 ranges: 8 kHz to 48 kHz and 88 kHz to 96 kHz. The
range is selected with bits DA96K and AD96K in CR29 for AD and DA paths respectively.
Note:
When AD96K=1 it is required to have DA96K=1.
The rates are fully independent in A/D and D/A paths. Moreover the rates do not have to be
specified to the device and they can change on the fly, within one range, while data is
flowing.
The 2 audio data interfaces (for A/D and D/A) can independently operate in master or slave
modes.
4.7
Clock generators and master mode function
STw5098 provides 4 internal clock generators that can drive, if needed, the audio interfaces
(master mode), and/or two independent master clocks.
The AMCK clock input frequency is internally raised via a PLL on each entity to obtain a
clock (MCK) in the range 32 MHz to 48 MHz. The ratio MCK/AMCK is defined in CR30 (see
MCKCOEFF in Section 4.7 on page 20).
MCK is used to obtain, by fractional division, the oversampled clock (OCK), word clock
(SYNC) and bit clock (CK), that will therefore have edges aligned with MCK (the OCK period
can have jitter of 1 MCK period).
The frequency of OCK, SYNC and CK is set with DAOCKF in CR21/20 for DA interface, and
ADOCKF in CR24/23 for AD interface.
The ratio between OCK and SYNC clocks is selected with bit DAOCK512 in CR22 for DA
interface and bit ADOCK512 in CR25 for AD interface. The ratio between CK and SYNC
clocks depends on the selected interface format (see Audio digital interfaces paragraph
below). Note that SPI format can only be slave.
The ADOCK and DAOCK output clocks are activated by bits ENADOCK and ENDAOCK
respectively, while master mode generation is activated with two bits: first ADMAST
(DAMAST) sets ADSYNC and ADCK (DASYNC and DACK) pins as outputs, then
ADMASTGEN (DAMASTGEN) generates the SYNC and CK clocks. The logical value at
SYNC and CK pins before data generation depends on the interface selected format.
See description of CR20 to CR25 for further details.
20/85
STw5098
Functional description
4.8
Audio digital interfaces
Four separate audio data interfaces are provided for AD and DA paths to have maximum
flexibility in communicating with other devices. The 4 interfaces can have different rates and
can work in different formats and modes (i.e an AD interface can be 8 kHz PCM slave while
a DA is 44.1 kHz I2S master).
The pins used by the interfaces are:
AD_SYNC, AD_CK and AD_DATA for AD paths word clock, bit clock and data, respectively,
and
DA_SYNC, DA_CK and DA_DATA for DA paths word clock, bit clock and data, respectively.
Data is exchanged with MSB first and left channel data first in all formats. Data word-length
is selected with bits DAWL in CR26 and ADWL in CR27. AD_DATA pin, outside the selected
time slot, is in the impedance condition selected by bit ADHIZ in CR28 in all data formats
except right aligned format.
In the following paragraphs SYNC, CK and DATA will be used when the distinction between
AD and DA is not relevant. When Master Mode is selected (bits DAMAST and ADMAST in
CR22 and CR25 respectively) the SYNC and CK clocks are generated internally. In addition,
an oversampled clock can be generated for each interface (AD_OCK and DA_OCK). The
clock is available in Slave Mode also, if needed.
The AD and DA interfaces can also be used as a single bidirectional interface when they are
configured with the same format (Delayed, DSP, etc.) and AD_SYNC is connected to
DA_SYNC and DA_CK to AD_CK. Master Mode is still available selecting ADMAST or
DAMAST (not both).
The interfaces features are controlled with control registers CR26, CR27 and CR28.
Supported operating formats:
●
Delayed format (I2S compatible) (DAFORM or ADFORM =000): the Audio Interface is
I2S compatible (Figure 9 on page 54). The number of CK periods within one SYNC
period is not relevant, as long as enough CK periods are used to transfer the data and
the maximum frequency limit specified for bit clock is not exceeded. CK can be either a
continuous clock or a sequence of bursts. In master mode there are 32 CK periods per
SYNC period (that means 16 CK periods per channel) when the word length is 16 bit,
while there are 64 CK periods per SYNC period (or 32 CK periods per channel) when
word length is 18bit or higher. Bits ADSYNCP, DASYNCP and ADCKP, DACKP affect
the interface format inverting the polarity of SYNC and CK pins respectively.
●
●
●
Left aligned format (DAFORM or ADFORM =001): this format is equivalent to delayed
format without the 1 bit clock delay at the beginning of each frame (Figure 9 on
page 54).
Right aligned format (DAFORM or ADFORM =010): this format is equivalent to
delayed format, except that the audio data is right aligned and that the number of CK
periods is fixed to 64 for each SYNC period (Figure 9 on page 54).
DSP format (DAFORM or ADFORM =011) in this format the audio interface starting
from a frame sync pulse on SYNC receives (DA) or sends (AD) the left and right data
one after the other (Figure 10 on page 55). The number of CK periods within one
SYNC period is not relevant, as long as enough CK periods are used to transfer the
data and the maximum frequency limit specified for bit clock is not exceeded. CK can
be either a continuous clock or a sequence of bursts. In Master Mode there are 32 CK
periods per SYNC period when the word length is 16 bit, while there are 64 CK periods
per SYNC period when word length is 18bit or higher. Bit CKP (ADCKP and DACKP)
21/85
Functional description
STw5098
affects the interface format inverting the polarity of CK pin. Bit SYNCP (ADSYNCP and
DASYNCP) switches between delayed (SYNCP=0) and non delayed (SYNCP=1)
formats.
DSP format is suited to interface with a multi-channel serial port.
●
SPI format (DAFORM or ADFORM =100) in this format left and right data is received
with separate data burst. Every burst is identified with a low level on SYNC signal
(Figure 10 on page 55). There is no timing difference between the left and right data
burst: the two channels are identified by the startup order: the first burst after AD path
or DA path power-up identifies the left channel data, the second one is the Right
channel data, then left and right data repeat one after the other. CK must have 16
periods per channel in case of 16 bit data word and 32 periods per channel in case of
18 bit to 32 bit data word.
The SPI interface can be configured as a single-channel (mono) interface with bit SPIM
(ADSPIM and DASPIM). The mono interface always exchanges the left channel
sample.
SPI-format can only be slave: if Master Mode is selected the CK and SYNC pins are set
to 0. Bit CKP (ADCKP and DACKP) affects the interface format inverting the polarity of
CK pin.
●
PCM format (DAFORM or ADFORM =111): this format is monophonic, as it can only
receive (DA) and transmit (AD) single channel data (Figure 10 on page 55). It is mainly
used when voice filters are selected. If audio filters are used then the same sample is
sent from DA-PCM interface to both channel of DA path, and the left channel sample
from AD path is sent to AD-PCM interface. If in the AD path the right channel has to be
sent to the PCM interface then the following must be set: ADRTOL=1 (CR27) and
ENADCR=0 (CR1). In Master Mode the number of CK periods per SYNC period is
between 16 and 512 (see DAPCMF in CR22 and ADPCMF in CR25 Section 4.7 on
page 20 for details). Bit CKP (ADCKP and DACKP) affects the interface format
inverting the polarity of CK pin. Bit SYNCP (ADSYNCP and DASYNCP) switches
between delayed (SYNCP=0) and non delayed (SYNCP=1) formats.
4.9
Analog inputs
Each entity of the STw5098 has a stereo Microphone preamplifier and a stereo Line In
amplifier, with inputs selectable among 5: MIC (for Microphone preamplifiers only), LINEIN
(for Line In amplifiers only) and 3 different AUX inputs (for Microphone and Line In
amplifiers). The AUX inputs can be used simultaneously for Line In amplifiers and
Microphone preamplifiers.
The following description is for one entity, it is similar for the other entity.
●
Microphone preamplifier: it has a very low noise input, specifically designed for low
amplitude signals. For this reason the preamplifier has a high input gain (up to 39 dB)
keeping a constant 50 kΩ input impedance for the whole gain range. However it can
also be used as line in preamplifier because it can accept a high dynamic input signal
(up to 4 Vpp). There are two separate gain and attenuation stages in order to improve
the S/N ratio when the preamplifier output range is below full scale (volume
control).The gain and attenuation controls are separate for left and right channel (CR3
and CR4 respectively). The Preamplifier input is selected with bits MICSEL in CR18,
and it is disconnected when MICMUTE=1. If a single ended input is selected then the
preamplifier uses the selected pin as the positive input and connects the negative input
(for both left and right channels) to CAPMIC pin, which has to be connected through a
capacitor to a low noise ground (typically the same reference ground of the input).
22/85
STw5098
Functional description
Each stereo Microphone preamplifier is powered up with bits ENMICL and ENMICR in
CR1.
●
Line In amplifier: each line in amplifier is designed for high level input signal. The input
gain is in the range -20 dB up to 18 dB. The Line In amplifier input is selected with bits
LINSEL in CR18, and it is disconnected when LINMUTE=1. If a single ended input is
selected then the amplifier uses the selected pin as the positive input and connects the
negative input (for both left and right channels) to CAPLINEIN pin, which has to be
connected through a capacitor to a low noise ground (typically the same reference
ground of the input).
The stereo Line In amplifier is powered up with bits ENLINL and ENLINR in CR1.
4.10
Analog output drivers
Each entity of the STw5098 provides 3 different analog signal outputs and 1 common mode
reference output. The description here below is for one entity. VCCP and VCCL are common
for both entities.
●
Line out drivers: it is a stereo differential output, it can be used as single-ended output
just by using the positive or negative pin. It can drive 1 kΩ resistive load. The load can
be connected between the positive and negative pins or between one pin and ground
through a decoupling capacitor. The output gain is regulated with LOG bits in CR7, in
the range 0 to -18 dB, simultaneously for left and right channels. When used as a single
ended output the effective gain is 6 dB lower. It is muted with bit MUTELO in CR19. The
input signal of this stereo output can come from the analog mixer or directly from MIC
preamplifiers. The output Common Mode Voltage level is controlled with bits VCML in
CR19. The supply voltage of line out drivers is VCCP
.
The line out drivers are powered up with bits ENLOL and ENLOR in CR1. The output
pins are in high impedance state with a 180kΩpull-down resistor when the line out
drivers are powered down.
●
Headphones drivers: it is a stereo single ended output. It can drive 16 ohm resistive
load and deliver up to 40 mW. The output gain is regulated with HPLG and HPRG bits
in CR8 and CR9 respectively, with a range of -40 to 6 dB. It is muted with bit MUTEHP
in CR19. The input signal of this stereo output comes from the analog mixer.The output
common mode voltage is controlled with bits VCML in CR19. The supply voltage of
headphones drivers is VCCP
.
The headphones drivers are powered up with bits ENHPL and ENHPR in CR2.The
output pins are in high impedance state when the headphones drivers are powered
down.
●
Common mode voltage driver: it is a single ended output with output voltage value
selectable with bits VCML in CR19, from 1.2 V to 1.65 V in steps of 150 mV. The output
voltage should be set to the value closest to VCCP/2 to optimize output drivers
performance. The common mode voltage driver is designed to be connected to the
common pin of stereo headphones, so that decoupling capacitors are not needed at
HPL and HPR outputs. The supply voltage of the common mode voltage driver is
VCCP
.
The common mode voltage driver is powered up with bit ENHPVCM in CR2.The output
pin is in high impedance state when the common mode voltage driver is powered down.
23/85
Functional description
STw5098
●
Loudspeaker driver (one entity only): it is a monophonic differential output. It can
drive 8 Ω resistive load and deliver up to 500 mW to the load. The output gain is
regulated with LSG bits in CR7, in the range -24 to +6 dB. The input signal of the
loudspeaker driver comes from the analog mixers: bits LSSEL in CR29 select left
channel, right channel, (L+R)/2 (mono) or mute. The output common mode voltage is
obtained with an internal voltage divider from VCCLS and it is connected to CAPLS pin.
The supply voltage of the loudspeaker driver is VCCLS
.
The loudspeaker driver is powered up with bit ENLS in CR2.The output pin is in high
impedance state when the loudspeaker driver is powered down.
Note:
1
Together with the LS driver, only a second power output is allowed among:
Ear (1EARP - 1EARN)
Headphones 1 (1HPL and 1HPR)
Headphones 2 (2HPL and 2HPR)
●
Earphone driver (one entity only): it is a monophonic differential output. It can drive
32 Ω resistive load and deliver up to 125 mW to the load. The output gain is regulated
with EARG bits in CR7, in the range -24 to +6 dB. The input signal of the loudspeaker
driver comes from the analog mixers: bits EARSEL in CR29 select left channel, right
channel, (L+R)/2 (mono) or mute. The output Common Mode Voltage is obtained with
an internal voltage divider from VCCLS and it is connected to CAPEAR pin. The supply
voltage of the loudspeaker driver is VCCLS
.
The loudspeaker driver is powered up with bit ENEAR in CR2.The output pin is in high
impedance state when the loudspeaker driver is powered down.
Note:
Note on direct connection of VCCLS to the battery:
The voltage of batteries of handheld devices during charging is usually below 5.5 V, making
V
CCLS supply pin suitable for a direct connection to the battery. In this case if STw5098 is
delivering the maximum power to the load and the ambient temperature is above 70 °C then
the simultaneous charging of the battery can overheat the device. A basic protection
scheme is implemented in STw5098 (activated with bit LSLIM in CR19): it limits the
maximum gain of the loudspeaker to -6 dB when VCCLS is above 4.2 V, and it removes the
limit for VCCLS below 4.0 V. The loudspeaker gain is left unchanged if it is set below -6 dB
with bits LSG. This event (VCCLS > 4.2 V) can generate, if enabled (bit VLSMSK in CR31),
an IRQ signal.
4.11
Analog mixers
STw5098 can send to the output drivers the sum of stereo audio signals from 3 different
sources of each entity: DA path (bit MIXDAC in CR17), Microphone Preamplifiers (bit
MIXMIC in CR17) and Line In Amplifiers (bit MIXLIN in CR17). The analog mixers do not
have a gain control on the inputs, therefore the user should reduce the levels of the input
signals within the analog signal range.
The stereo analog mixers are powered up with bits ENMIXL and ENMIXR in CR2.
4.12
AD paths
In each entity the AD path converts audio signals from Microphone Preamplifiers (selected
with bit ADMIC in CR17) and Line In Amplifiers (bit ADLIN in CR17) inputs to digital domain.
If both inputs are selected then the sum of the two is converted. After AD conversion the
audio data is resampled with a sample rate converter and then processed with the internal
DSP. Two different filters are selectable in the DSP (bit ADVOICE in CR29): stereo Audio
24/85
STw5098
Functional description
Filter, with DC offset removal and FIR image filtering; and a standard mono voice-channel
filter (uses left channel input and feeds both channel output). The AD path includes a digital
gain control (ADCLG, ADCRG in CR12 and CR13 respectively) in the range -57 to +8 dB.
The maximum gain from Mic Preamplifier to AD interface is then 47 dB. When Audio filter is
selected in both AD and DA paths then DA audio data can be summed to AD data and sent
to the AD Audio Interface (see DA2ADG in CR15). Left and right channels can be
independently switched on and off to save power, if needed (bits ENADCL and ENADCR in
CR1)
4.13
DA paths
In each entity the DA path converts digital data from the digital audio interface to analog
domain and feeds it to the analog mixer. Incoming audio data is processed with a DSP
where different filters are selectable (bit DAVOICE in CR29): Audio filter, stereo, with FIR
image filtering, bass and treble controls (bits BASS and TREBLE in CR14), de-emphasis
filter; and a standard voice channel filter, mono (uses left channel input and feeds both
channel output). A dynamic compression function is available for both audio and voice filters
(bit DYNC in CR14). The DA path includes a digital gain control (DACLG, DACRG in CR10
and CR11 respectively) in the range -65 to 0 dB. AD to DA mixing (sidetone) can be
enabled: see CR16 for details. Left and right channel can be independently switched on and
off to save power, if needed (bits ENDACL and ENDACR in CR1).
4.14
Analog-only operations
Each entity from the STw5098 can operate without AMCK master clock if analog-only
functions are used. It is possible to mix Microphone and Line In preamplifiers signals and
listen through headphones, loudspeaker or send them to line-out. The analog-only operation
is enabled with bit ENOSC in CR0. When ENOSC=1 the AD and DA paths cannot be used.
In Analog Mode, each of the two entities can handle two different stereo audio signals, so it
can be used as a front end for an external voice codec that does not include microphone
preamplifiers and power drivers: mic signal is sent through Microphone preamplifiers directly
to line out drivers (Transmit path), while Receive signal is sent through Line In amplifiers to
the selected power drivers.
4.15
Automatic Gain Control (AGC)
STw5098 provides a digital Automatic Gain Control in AD path for each entity. The circuit
can control the input gain at MIC preamplifier, Line In amplifier or both (bits ENAGCMIC and
ENAGCLIN in CR35). When one input is selected, the center gain value used for the input is
fixed with bits MICLG, MICRG, LINLG and LINRG in CR3 to CR6 (like in normal operation),
then the AGC circuit adds to all the gains a value in the range -10.5 dB to +10.5 dB (or,
extended with bit AGCRANGE in CR35, -21 dB to 21 dB), in order to obtain an average level
at the digital interface output in the range -6 dB to -30 dB (selected with bits AGCLEV in
CR35). The AGC added gain acts directly in the input gain, to avoid input saturation and
improve S/N ratio, so it cannot exceed the input gain range. When MIC and Line-In inputs
are selected simultaneously the control is performed on the sum of the two, preserving the
balance fixed with input gains. Different values for Attack and Decay constants can be
selected, depending on the kind of signal the AGC has to control (i.e. voice, music). The
25/85
Functional description
STw5098
Attack and Decay time constants are related to the AD data rate (see bits AGCATT and
AGCDEL in CR34).
4.16
Interrupt request: IRQ pins
On each entity of the STw5098, the interrupt request feature can signal to a control device
the occurrence of particular events on each entity. Two control registers are used to choose
the behavior of IRQ pin: the first is a Status/Event Register (CR32), where bits can
represent the status of an internal function (i.e. a voltage is above or below a threshold) or
an event (i.e. a voltage changed crossing a threshold); the second is a Mask Register
(CR31) where if a bit in the mask is set to 1 then the corresponding bit in the Status/Event
Register can affect IRQ pin status.
On each entity, the IRQ pin is always active low. At VCC power up an interrupt request is
generated by the Power-On-Reset circuit that sets to 1 bits PORMSK in CR31 and POREV
in CR32. After this event the PORMSK bit should be cleared by the user and bit IRQCMOS
in CR33 should be set according to the application (open drain or CMOS).
When an IRQ event occurs and SPI control interface is selected with no serial output pin it is
still possible to identify the event (and relative status) that generated the interrupt request.
This can be done by setting the IRQ mask/enable bits (in CR31) one at the time (with
successive writings) and reading the IRQ pin status. A simple example of this is the headset
plug-in detection: at first we set bit HSDETMSK=1 in CR31 (with all the other bits set to 0). If
there is an interrupt request then we set HSDETMSK=0 and HSDETEN=1, so we can read
the HSDET status at IRQ pin. Then we read CR32 to clear its content (even if no data is
sent out).
4.17
Headset plug-in and push-button detection
Each entity of the STw5098 can detect the plug-in of a microphone connector and the
press/release event of a call/answer push-button. An application example can be found
below, while specifications can be found in Section 10.4 on page 64.
Figure 4.
Plug-in and push-button detection application note
HDET
AUX1L
200nF
AUX1R
VCCA
STw5095
3kΩ
200nF
CAPMIC
1.5kΩ
Call/Answer Button
10µF
From driver
Generic Connector
26/85
STw5098
Functional description
4.18
Microphone biasing circuits
The Microphone Biasing Circuits can drive mono or stereo microphones and can switch
them off when not needed in order to save the current used by the microphone biasing
network on each entity. Two bits control the behavior of the microphone bias circuit: MBIAS
in CR17 enables the circuit (fixed voltage at MBIAS pin), while bit MBIASPD in CR17 affects
the behavior of MBIAS pin when the function is not enabled. In particular when MBIASPD=1
the MBIAS pin is pulled down, otherwise it is left in tristate mode. The specification for the
microphone biasing circuits can be found in Section 10.6 on page 64.
27/85
Control registers
STw5098
5
Control registers
5.1
Summary
Table 2.
Control register summary
CR#
(hex)
Description
D7
D6
D5
D4
D3
D2
D1
D0
Def.
CR0 Supply & power
(00h) control #1
POWER
UP
0000
0000
ENANA
ENAMCK
ENOSC
ENDACR
ENHPR
ENPLL
ENHSD
A24V
D12V
CR1
0000
0000
ENADCL ENADCR ENDACL
ENMICL
ENMICR
ENLINL
ENMIXL
ENLINR
ENMIXR
Power control #2
(01h)
CR2
ENHPVC
M
1ENEAR
2ENLS
0000
0000
ENLOL
ENLOR
ENHPL
Power control #3
(02h)
CR3
0000
0000
MICLA(2:0)
MICLG(4:0)
MICRG(4:0)
LINLG(4:0)
LINRG(4:0)
Mic gain left
(03h)
CR4
0000
0000
MICRA(2:0)
Mic gain right
(04h)
CR5
0000
1001
X
X
X
X
Line in gain left
(05h)
CR6
0000
1001
X
X
Line in gain right
(06h)
CR7 LO gain & LS
(07h) gain
1EARG(3:0)
2LSG(3:0)
0000
0011
X
LOG(2:0)
CR8
0000
0011
X
X
X
X
X
X
X
X
X
HPLG(4:0)
HPL gain
(08h)
CR9
0000
0011
X
HPRG(4:0)
HPR gain
(09h)
CR10 DAC digital gain
(0Ah) left
0000
0000
X
DACLG(5:0)
CR11 DAC digital gain
(0Bh) right
0000
0000
X
X
DACRG(5:0)
ADCLG(5:0)
ADCRG(5:0)
CR12 ADC digital gain
(0Ch) left
0000
1000
CR13 ADC digital gain
(0Dh) right
0000
1000
X
CR14 Bass/treble/de-
(0Eh) emphasis
0000
0000
DYNC
X
TREBLE(2:0)
X
BASS(3:0)
CR15 DA to AD mixing
(0Fh) gain
0000
0000
X
X
DA2ADG(4:0)
AD to DA
CR16
0000
0000
X
AD2DAG(5:0)
mix/sidetone
(10h)
gain
CR17 Mixer switches &
(11h) mic bias
M
0000
0000
MBIAS
ADMIC
ADLIN
MIXMIC
MIXLIN
MIXDAC
MICLO
BIASPD
28/85
STw5098
Table 2.
Control registers
Control register summary
CR#
(hex)
Description
D7
D6
D5
D4
D3
D2
D1
D0
Def.
CR18
(12h)
0010
0100
X
IN2VCM LINMUTE
LINSEL(1:0)
MICMUTE
MICSEL(1:0)
Input switches
Drivers control
CR19
(13h)
1EARLIM
2LSLIM
1EARSEL(1:0)
2LSSEL(1:0)
0101
1000
VCML(1:0)
X
MUTELO
MUTEHP
CR20 DAOCK
(14h) frequency LSB
0000
0000
DAOCKF(7:0)
CR21 DAOCK
(15h) frequency MSB
0000
0000
DAOCKF(15:8)
CR22 DA clock
(16h) generator control
DA
MASTGEN
END
AOCK
DAO
CK512
0000
0000
X
X
DAMAST
DAPCMF(1:0)
CR23 ADOCK
(17h) frequency LSB
0000
0000
ADOCKF(7:0)
CR24 ADOCK
(18h) frequency MSB
0000
0000
ADOCKF(15:8)
CR25 AD Clock
(19h) generator control
AD
MASTGEN
ENA
DOCK
ADO
CK512
0000
0000
X
X
X
ADMAST
ADPCMF(1:0)
CR26 DAC data IF
(1Ah) control
0000
0000
DAFORM(2:0)
ADFORM2:0)
DASPIM
ADSPIM
ADCKP
DAWL(2:0)
CR27 ADC data IF
(1Bh) control
0000
0000
ADRTOL
ADWL(2:0)
ADMONO
CR28 DAC&ADC data
(1Ch) IF control
AMC
KINV
AD
SYNCP
0000
0000
DACKP DASYNCP DAMONO
ADHIZ
TXNH
CR29 Digital filters
(1Dh) control
0000
0000
X
DAVOICE
X
DA96K
X
RXNH
X
ADVOICE
AMCKSIN
AD96K
ADNH
CR30 Soft reset &
(1Eh) AMCK range
0000
0000
SWRES
VLSHEN
VLSH
X
CKRANGE(2:0)
CR31
PUSH
BEN
PUSH
BMSK
HSDET
MSK
0000
0000
HSDETEN VLSHMSK
OVFMSK PORMSK
Interrupt mask
(1Fh)
CR32
0000
0000
PUSHB
X
HSDET
VLSHEV
PUSHBEV HSDETEV
OVFEV
OVFDA
POREV
OVFAD
Interrupt status
(20h)
CR33
0000
0000
SPIOHIZ
SPIOSEL(1:0)
IRQCMOS
Misc. control
(21h)
AGC
CR34
0000
0000
AGCATT(3:0)
AGCDEC(3:0)
attack/decay
(22h)
coeff.
CR35
ENA
GCLIN
ENAG
CMIC
AGC
RANGE
0000
0000
X
X
AGCLEV(3:0)
AGC control
(23h)
CR36
0000
0000
X
X
X
X
X
X
X
RESERVED
(24h)
Note: X reserved, write zero
29/85
Control registers
STw5098
Caution:
In the following Section 5: Control registers, reference to each entity is omitted. Each entity
of the STw5098 has the same register set.
5.2
Supply and power control
CR#
(hex)
Description
D7
D6
D5
D4
D3
D2
D1
D0
Def.
CR0
(00h)
Supply & power
control #1
POWER
UP
0000
0000
ENANA
ENAMCK
ENOSC
ENPLL
ENHSD
ENMICR
ENLS
A24V
D12V
CR1
(01h)
0000
0000
ENADCL ENADCR ENDACL ENDACR
ENMICL
ENLINL
ENMIXL
ENLINR
ENMIXR
Power control #2
Power control #3
CR2
(02h)
ENH
PVCM
0000
0000
ENLOL
ENLOR
ENHPL
ENHPR
Table 3.
Bits
CR0 description
Name Val.
CR0 description
Def.
1
0
All the enabled analog and digital blocks are in power up
All the device is in power down
7
6
5
POWERUP
ENANA
0
1
0
The analog blocks can be enabled
0
0
All the analog blocks are in power down
1
0
AMCK clock input pin is enabled
AMCK clock input pin is disabled
ENAMCK
1
0
The Internal oscillator is enabled.
The analog blocks use oscillator clock
4
ENOSC
0
The internal oscillator is in power down
1
0
The PLL is enabled
3
2
1
0
ENPLL
ENHSD
A24V
0
0
0
0
The PLL is in power down
1
0
The headset plug-in detector is enabled
The headset plug-in detector is disabled
1
0
Analog supply pins voltage range is 2.4V<VCCA<2.7V
Analog supply pins voltage range is 2.7V<VCCA<3.3V
1
0
Digital I/O pin voltage range is 1.2V<VCCIO<1.8V
Digital I/O pin voltage range is 1.71V<VCCIO<VCC
D12V
30/85
STw5098
Control registers
Table 4.
Bits
CR1 description
Name
Value
CR1 description
Def.
1
0
The left channel A/D converter is enabled
7
6
5
4
3
2
1
0
ENADCL
0
The left channel A/D converter is in power down
1
0
The right channel A/D converter is enabled
ENADCR
0
0
0
0
0
0
0
The right channel A/D converter is in power down
1
0
The left channel D/A converter is enabled
ENDACL
ENDACR
ENMICL
ENMICR
ENLINL
ENLINR
The left channel D/A converter is in power down
1
0
The right channel D/A converter is enabled
The right channel D/A converter is in power down
1
0
The left channel microphone preamplifier is enabled
The left channel microphone preamplifier is in power down
1
0
The right channel microphone preamplifier is enabled
The right channel microphone preamplifier is in power down
1
0
The left channel line-in preamplifier is enabled
The left channel line-in preamplifier is in power down
1
0
The right channel line-in preamplifier is enabled
The right channel line-in preamplifier is in power down
Table 5.
Bit #
CR2 description
Name
Value
CR2 Description
Def.
1
0
The left channel line out driver is enabled
7
6
5
4
3
ENLOL
0
The left channel line out driver is in power down (default)
1
0
The right channel line out driver is enabled
ENLOR
0
0
The right channel line out driver is in power down (default)
1
0
The left channel headphones driver is enabled
ENHPL
The left channel headphones driver is in power down (default)
1
0
The right channel headphones driver is enabled
ENHPR
ENHPVCM
1ENEAR
2ENLS
0
0
0
0
0
0
The right channel headphones driver is in power down (default)
1
0
The headphones reference voltage generator is enabled
The headphones reference voltage generator is in power down (def)
1
0
The 32Ω earphone amplifier is enabled
The 32Ω earphone amplifier is in power down (default)
2
1
0
The 8Ω loudspeaker amplifier is enabled
The 8Ω loudspeaker amplifier is in power down (default)
1
0
The left channel analog output mixer is enabled
1
0
ENMIXL
ENMIXR
The left channel analog output mixer is in power down (default)
1
0
The right channel analog output mixer is enabled
The right channel analog output mixer is in power down (default)
31/85
Control registers
STw5098
Def.
5.3
Gains
CR#
(hex)
Description
D7
D6
D5
D4
D3
D2
D1
D0
CR3
(03h)
0000
0000
MICLA(2:0)
MICLG(4:0)
MICRG(4:0)
LINLG(4:0)
LINRG(4:0)
Mic gain left
CR4
(04h)
0000
0000
MICRA(2:0)
Mic gain right
Line in gain left
Line in gain right
CR5
(05h)
0000
1001
X
X
X
X
X
X
X
X
X
X
X
X
CR6
(06h)
0000
1001
X
CR7
(07h)
LO gain & LS
gain
0000
0011
LOG(2:0)
LSG(3:0)
CR8
(08h)
0000
0011
X
X
X
X
X
X
X
X
HPLG(4:0)
HPRG(4:0)
HPL gain
HPR gain
CR9
(09h)
0000
0011
CR10
(0Ah)
DAC digital gain
left
0000
0000
DACLG(5:0)
CR11
(0Bh)
DAC digital gain
right
0000
0000
DACRG(5:0)
ADCLG(5:0)
ADCRG(5:0)
CR12
(0Ch)
ADC digital gain
left
0000
1000
CR13
(0Dh)
ADC digital gain
right
0000
1000
Table 6.
Bits
CR3 and CR4 description
Name CR3
Name CR4
Value
CR3 and CR4 description
Def.
Left (CR3) and right (CR4) channels microphone attenuation
000
0.0 dB gain (default)
-1.5 dB gain
001
010
...
MICLA(2:0)
MICRA(2:0)
7-5
-3.0 dB gain
000
...step 1.5 dB
-9.0 dB gain
110
111
-12.0 dB gain
Left (CR3) and right (CR4) channels microphone gain
00000
00001
00010
...
0.0 dB gain (default)
1.5 dB gain
MICLG(4:0)
MICRG(4:0)
4-0
00000
3.0 dB gain
...step 1.5 dB
39.0 dB gain
11010
32/85
STw5098
Control registers
Def.
Table 7.
Bits
CR5 and CR6 description
Name CR5
Name CR6
Value
CR5 and CR6 description
Left (CR5) and right (CR6) channels line in gain
18.0 dB gain
00000
00001
00010
...
16.0 dB gain
LINLG(4:0)
LINRG(4:0)
14.0 dB gain
4-0
01001
...step 2.0 dB
01001
...
0.0 dB gain (default)
...step 2.0 dB
10011
-20.0 dB gain
Table 8.
Bits
CR7 description
Name
Value
CR7 description
Def.
Left and right channel line out drivers gain
Gain to differential output
18.0 dB gain (default)
-15.0 dB gain
Equivalent single-ended gain
000
-24.0 dB gain (default)
-21.0 dB gain
-18.0 dB gain
...step 3 dB
6-4
LOG(2:0)
001
010
...
000
-12.0 dB gain
...step 3 dB
110
00 dB gain
-6.0 dB gain
1EARG(3:0)
2LSG(3:0)
32Ωearphone gain/ 8Ω loudspeaker gain
6.0 dB gain
0000
0001
0010
0011
...
4.0 dB gain
3-0
2.0 dB gain
0011
0.0 dB gain (default)
...step 2.0 dB
1111
-24.0 dB gain
Table 9.
Bits
CR8 and CR9 description
Name CR8
Name CR9
Value
CR8 and CR9 description
Def.
Left (CR8) and right (CR9) channels headphones driver gain
00000
00001
00010
00011
...
0.0 dB gain
-2.0 dB gain
HPLG(4:0)
HPRG(4:0)
4-0
-4.0 dB gain
00011
-6.0 dB gain (default)
...step 2.0 dB
-40.0 dB gain
10100
33/85
Control registers
STw5098
Def.
Table 10. CR10 and CR11 description
Name CR10
Bits
Value
CR10 and CR11 description
Name CR11
Left (CR10) and right (CR11) channels DAC digital gain
0.0 dB gain (default)
-1.0 dB gain
000000
000001
000010
000011
000100
000101
000110
000111
001000
001001
001010
001011
001100
001101
001110
001111
010000
010001
010010
010011
010100
010101
010110
010111
011000
011001
011010
011011
011100
011101
011110
011111
100000
100001
100010
100011
100100
-2.0 dB gain
-3.0 dB gain
-4.0 dB gain
-5.0 dB gain
-6.0 dB gain
-7.0 dB gain
-8.0 dB gain
-9.0 dB gain
-10.0 dB gain
-11.0 dB gain
-12.0 dB gain
-13.0 dB gain
-14.0 dB gain
-15.0 dB gain
-16.0 dB gain
-17.0 dB gain
-18.0 dB gain
-20.0 dB gain
-22.0 dB gain
-24.0 dB gain
-26.0 dB gain
-28.0 dB gain
-30.0 dB gain
-32.0 dB gain
-34.0 dB gain
-36.0 dB gain
-38.0 dB gain
-41.0 dB gain
-44.0 dB gain
-47.0 dB gain
-50.0 dB gain
-53.0 dB gain
-56.0 dB gain
-59.0 dB gain
-65.0 dB gain
DACLG(5:0)
DACRG(5:0)
5-0
000000
100101 -∞dB gain
34/85
STw5098
Control registers
Table 11. CR12 and CR13 description
Name CR12
Bits
Value
CR12 and CR13 description
Def.
Name CR13
Left (CR12) and right (CR13) channels ADC digital gain
8.0 dB gain
000000
000001
000010
000011
000100
000101
000110
000111
001000
001001
001010
001011
001100
001101
001110
001111
010000
010001
010010
010011
010100
010101
010110
010111
011000
011001
011010
011011
011100
011101
011110
011111
100000
100001
100010
100011
100100
100101
7.0 dB gain
6.0 dB gain
5.0 dB gain
4.0 dB gain
3.0 dB gain
2.0 dB gain
1.0 dB gain
0.0 dB gain (default)
-1.0 dB gain
-2.0 dB gain
-3.0 dB gain
-4.0 dB gain
-5.0 dB gain
-6.0 dB gain
-7.0 dB gain
-8.0 dB gain
-9.0 dB gain
ADCLG(5:0)
ACDRG(5:0)
-10.0 dB gain
-11.0 dB gain
-12.0 dB gain
-14.0 dB gain
-16.0 dB gain
-18.0 dB gain
-20.0 dB gain
-22.0 dB gain
-24.0 dB gain
-26.0 dB gain
-28.0 dB gain
-30.0 dB gain
-33.0 dB gain
-36.0 dB gain
-39.0 dB gain
-42.0 dB gain
-45.0 dB gain
-48.0 dB gain
-51.0 dB gain
-57.0 dB gain
5-0
001000
100110 -∞dB gain
35/85
Control registers
STw5098
Def.
5.4
DSP control
CR#
(hex)
Description
D7
D6
D5
D4
D3
D2
D1
D0
CR14
(0Eh)
Bass/treble/de-
emphasis
0000
0000
DYNC
X
TREBLE(2:0)
X
BASS(3:0)
CR15
(0Fh)
DA to AD mixing
gain
0000
0000
X
X
DA2ADG(4:0)
AD to DA
mix/sidetone
gain
CR16
(10h)
0000
0000
X
AD2DAG(5:0)
Table 12. CR14 description
Bits Name Value
CR14 description
Def.
1
0
Audio dynamic compression in D/A path is enabled
Audio dynamic compression in D/A path is disabled
7
DYNC
0
Treble control in D/A path
+6.0 dB treble gain
+4.0 dB treble gain
+2.0 dB treble gain
0.0 dB treble gain
011
010
001
000
111
110
101
100
6-4
TREBLE(2:0)
000
-2.0 dB treble gain
-4.0 dB treble gain
-6.0 dB treble gain
De-emphasis filter enabled
Bass control in D/A path
+12.5 dB bass gain
+10.0 dB bass gain
+7.5 dB bass gain
+5.0 dB bass gain
+2.5 dB bass gain
0.0 dB bass gain
0101
0100
0011
0010
0001
0000
1111
1110
1101
1100
1011
3-0
BASS(3:0)
0000
-2.5 dB bass gain
-5.0 dB bass gain
-7.5 dB bass gain
-10.0 dB bass gain
-12.5 dB bass gain
36/85
STw5098
Control registers
Def.
Table 13. CR15 description
Bits
Name
Value
CR15 description
DA to AD mixing (Audio filter in D/A and A/D path selected)
DA to AD mixing disabled (default)
+2.0 dB gain
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
10000
10001
10010
10011
10100
10101
10110
0.0 dB gain
-2.0 dB gain
-4.0 dB gain
-6.0 dB gain
-8.0 dB gain
-10.0 dB gain
-12.0 dB gain
-14.0 dB gain
-16.0 dB gain
4-0
DA2ADG(4:0)*
00000
-18.0 dB gain
-20.0 dB gain
-22.0 dB gain
-24.0 dB gain
-26.0 dB gain
-28.0 dB gain
-30.0 dB gain
-32.0 dB gain
-34.0 dB gain
-36.0 dB gain
-38.0 dB gain
-40.0 dB gain
* When Voice filter in D/A or A/D path is selected this function is disabled
Note:
D/A to A/D mixing is performed at AD data rate, so if A/D and D/A rates are different then asynchronous sampling artifacts
may occur.
37/85
Control registers
STw5098
Def.
Table 14. CR16 description
Bits
Name
Value
CR16 description
AD to DA mixing (sidetone)
000000 AD to DA mixing disabled (default)
000001
000010
000011
000100
000101
000110
000111
001000
001001
001010
001011
001100
001101
001110
001111
010000
010001
010010
010011
010100
010101
010110
010111
011000
011001
011010
011011
011100
011101
011110
011111
100000
100001
100010
100011
100100
100101
100110
100111
101000
101001
101010
-1.0 dB gain
-2.0 dB gain
-3.0 dB gain
-4.0 dB gain
-5.0 dB gain
-6.0 dB gain
-7.0 dB gain
-8.0 dB gain
-9.0 dB gain
-10.0 dB gain
-11.0 dB gain
-12.0 dB gain
-13.0 dB gain
-14.0 dB gain
-15.0 dB gain
-16.0 dB gain
-17.0 dB gain
-18.0 dB gain
-19.0 dB gain
-20.0 dB gain
-21.0 dB gain
-22.0 dB gain
-23.0 dB gain
-24.0 dB gain
-25.0 dB gain
-26.0 dB gain
-27.0 dB gain
-28.0 dB gain
-29.0 dB gain
-30.0 dB gain
-31.0 dB gain
-32.0 dB gain
-33.0 dB gain
-34.0 dB gain
-35.0 dB gain
-36.0 dB gain
-37.0 dB gain
-38.0 dB gain
-39.0 dB gain
-40.0 dB gain
-41.0 dB gain
-42.0 dB gain
5-0 AD2DAG(5:0)
000000
38/85
STw5098
Control registers
5.5
Analog functions
CR#
(hex)
Description
D7
D6
D5
D4
D3
D2
D1
D0
Def.
CR17
(11h)
Mixer switches &
Mic Bias
0000
0000
MBIAS
X
MBIASPD
IN2VCM
ADMIC
LINMUTE
X
ADLIN
MIXMIC
MIXLIN
MICMUTE
LSLIM
MIXDAC
MICLO
CR18
(12h)
0010
0100
LINSEL(1:0)
MICSEL(1:0)
Input switches
Drivers control
CR19
(13h)
0101
1000
VCML(1:0)
MUTELO MUTEHP
LSSEL(1:0)
Table 15. CR17 description
Bits
Name
Value
CR17 description
Def.
1
0
Microphone Bias enabled (2.1V typ at MBIAS pin)
Microphone Bias disabled
7
MBIAS
0
0
1
0
MBIAS pin is pulled down when microphone bias is disabled
6
MBIASPD
MBIAS pin is in high impedance state when microphone Bias is
disabled
1
0
Microphone preamplifiers are connected to AD path
Microphone preamplifiers are not connected to AD path
5
4
3
2
1
0
ADMIC
ADLIN
0
0
0
0
0
0
1
0
Line in preamplifiers are connected to AD path
Line in preamplifiers are not connected to AD path
1
0
Microphone preamplifiers are connected to mixers
Microphone preamplifiers are not connected to mixers
MIXMIC
MIXLIN
MIXDAC
MICLO
1
0
Line in preamplifiers are connected to mixers
Line in preamplifiers are not connected to mixers
1
0
Stereo DAC path is connected to mixers
Stereo DAC path is not connected to mixers
1
0
Microphone preamplifiers are connected to line out drivers
Mixers are connected to line out drivers
Table 16. CR18 description
Bits
Name
Value
CR18 description
Def.
1
0
Unused analog input pins are biased to common mode voltage
Unused analog input pins are in high impedance state
6
IN2VCM
0
1
0
Line in preamplifiers are muted
5
LINMUTE
1
Line in preamplifiers are not muted
Input pins connected to line in preamplifiers (if LINMUTE=0)
00
01
10
11
LINEIN
AUX1
AUX2
AUX3
(LINEINL, LINEINR)
4-3 LINSEL(1:0)
(AUX1L, AUX1R)
00
(AUX2LP-AUX2LN, AUX2RP-AUX2RN)
(AUX3L, AUX3R)
39/85
Control registers
STw5098
Table 16. CR18 description
Bits
Name
Value
CR18 description
Microphone preamplifiers are muted
Def.
1
0
2
MICMUTE
1
Microphone preamplifiers are not muted
Input pins connected to microphone preamplifiers (if MICMUTE=0)
00
01
10
11
MIC
(MICLP-MICLN, MICRP-MICRN)
(AUX1L, AUX1R)
1-0
MICSEL(1:0)
AUX1
AUX2
AUX3
00
(AUX2LP-AUX2LN, AUX2RP-AUX2RN)
(AUX3L, AUX3R)
Table 17. CR19 description
Bits
Name
Value
CR19 Description
Def.
Common mode voltage level for line out and headphones drivers
00
01
10
11
1.20 V
7-6
VCML(1:0)
1.35 V (default)
1.50 V
01
1.65 V
1
0
Line out drivers are muted
4
3
MUTELO
MUTEHP
1
1
Line out drivers are not muted
1
0
Headphones drivers (HP) are muted
Headphones drivers (HP) are not muted
1EARLIM
EAR/LS driver gain is limited when VCCLS is above 4.2V typ
EAR/LS driver (LS) gain is not limited
1
0
2
0
2LSLIM
1EARSEL(1:0)
00
01
10
11
Mute Loudspeaker driver (LS) is muted
Right Right channel mixer only connected to loudspeaker driver
Left Left channel mixer only connected to loudspeaker driver
1-0
00
2LSSEL(1:0)
Mono (Left + Right)/2 channel mixers connected to loudspeaker
driver
40/85
STw5098
Control registers
5.6
Digital audio interfaces master mode and clock generators
CR#
(hex)
Description
D7
D6
D5
D4
D3
D2
D1
D0
Def.
CR20
(14h)
DAOCK
frequency LSB
0000
0000
DAOCKF(7:0)
CR21
(15h)
DAOCK
frequency MSB
0000
0000
DAOCKF(15:8)
CR22
(16h)
DA clock
generator control
DA
MASTGEN
END
OCK
DAO
CK512
0000
0000
X
X
DAMAST
DAPCMF(1:0)
CR23
(17h)
ADOCK
frequency LSB
0000
0000
ADOCKF(7:0)
CR24
(18h)
ADOCK
frequency MSB
0000
0000
ADOCKF(15:8)
AD clock
generator
control
CR25
(19h)
AD
MASTGEN
ENA
DOCK
ADO
CK512
0000
0000
X
X
ADMAST
ADPCMF(1:0)
Table 18. CR21-20 and CR24-23 description
Name CR21-20
Bits
Value
CR21-20 and CR24-23 Description
Def.
Name CR24-23
The following formulas can be used to obtain the value of K for the
desired FS or OCK respectively in the clock generator
25
FS
⎛
⎞
K(FS) = round 2 --------------------------------------------------------------
⎝
⎠
AMCK ⋅ MCKCOEFF
25
OCK
K(OCK) = round 2 -----------------------------------------------------------------------------------
⎛
⎞
⎝
⎠
AMCK ⋅ MCKCOEFF ⋅ OSR
DAOCKF(15:0)
ADOCKF(15:0)
15-0
K
0000h
FS: Data rate (DA_SYNC or AD_SYNC frequency in master mode)
OCK: Oversampled clock frequency (DA_OCK or AD_OCK)
AMCK: Input master clock frequency
MCKCOEFF: See CR30 for definition
OSR: See bit 2 in CR22 and CR25
Note: CR21-20 and CR24-23 are meaningful in master mode only.
Table 19. CR22 and CR25 description
Name CR22
Bits
Value
CR22 and CR25 description
Def.
(Name CR25)
DAMAST
1
0
DA (AD) Audio interface is in master mode (low impedance output)
DA (AD) Audio interface is in slave mode (high impedance input)
5
0
0
0
(ADMAST)
DAMASTGEN
1
0
DA (AD) Master generator is enabled
DA (AD) Master generator is disabled
4
3
(ADMASTGEN)
ENDAOCK
1
0
DA_OCK (AD_OCK) output clock is enabled
DA_OCK (AD_OCK) output clock is disabled
(ENADOCK)
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Control registers
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Table 19. CR22 and CR25 description
Name CR22
Bits
Value
CR22 and CR25 description
Def.
(Name CR25)
Definition of DA_OSR (AD_OSR)
DAOCK512
1
0
DA_OCK/DA_SYNC (AD_OCK/AD_SYNC) ratio in master mode is
512
2
0
(ADOCK512)
da_ock/da_sync (ad_ock/ad_sync) ratio in master mode is 256
DA_CK/DA_SYNC (AD_CK/AD_SYNC) Ratio in PCM master mode
- 16 when CR26 DAWL=000 (CR27 ADWL=000)
- 32 when CR26 DAWL≠000 (CR27 ADWL≠000)
- 64
00
00
01
10
11
11
DAPCMF(1:0)
1-0
00
(ADPCMF(1:0))
- 128
- 256 when CR22 DAOCK512=0 (CR25 ADOCK512=0)
- 512 when CR22 DAOCK512=1 (CR25 ADOCK512=1)
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Control registers
5.7
Digital audio interfaces
CR#
(hex)
Description
D7
D6
D5
D4
D3
D2
D1
D0
Def.
CR26
(1Ah)
DAC data IF
control
0000
0000
X
DAFORM(2:0)
ADFORM2:0)
DASPIM
ADSPIM
ADCKP
DAWL(2:0)
ADWL(2:0)
ADMONO
CR27
(1Bh)
ADC data IF
control
0000
0000
ADRTOL
AMCKINV
CR28
(1Ch)
DAC&ADC data
IF control
AD
SYNCP
0000
0000
DACKP
DASYNCP DAMONO
ADHIZ
Table 20. CR26 description
Bits
Name
Value
CR26 Description
Def.
DA audio interface format selection
Delayed format (I2S compatible)
Left aligned format
000
001
010
011
100
111
6-4
DAFORM(2:0)
Right aligned format
000
DSP format
SPI format
PCM format (uses left channel)
1
0
DA interface in SPI mode receives one word for both channels
3
DASPIM
0
DA interface in SPI mode receives two words
(alternated, left channel first)
DA interface word length
000
001
010
011
100
16 bit
18 bit
20 bit
24 bit
32 bit
2-0
DAWL(2:0)
000
Table 21. CR27 description
Bits
Name
Value
CR27 description
Def.
1
0
AD right channel sent to PCM I/F (must set ENADCR=0 in CR1)
Normal operation
7
ADRTOL
0
AD audio interface format selection
Delayed format (I2S compatible)
Left aligned format
000
001
010
011
100
111
6-4
ADFORM(2:0)
Right aligned format
000
DSP format
SPI format
PCM format (sends out left channel)
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Table 21. CR27 description (continued)
Bits
Name
Value
CR27 description
Def.
1
0
AD interface in SPI mode sends one channel (left)
3
ADSPIM
0
AD interface in SPI mode sends two channels (alternated, left first)
AD interface word length
000
001
010
011
100
16 bit
18 bit
20 bit
24 bit
32 bit
2-0
ADWL(2:0)
000
Table 22. CR28 description
Bits
Name
Value
CR28 description
Def.
1
0
AMCK is inverted
7
AMCKINV
0
AMCK is not inverted
1
0
DA Bit clock pin (DA_CK) polarity is inverted
DA Bit clock pin (DA_CK) polarity is not inverted
6
5
DACKP
0
0
DSP and PCM formats in DA interface
Non delayed format
1
0
Delayed format
DASYNCP
Delayed, left-aligned, right-aligned and SPI formats in DA interface
DA sync pin (DA_SYNC) polarity is inverted
1
0
DA sync pin (DA_SYNC) polarity is not inverted
1
0
Mono mode: (L+R)/2 from Audio Interface is used on both DAC
channels
4
3
DAMONO
ADCKP
0
0
Stereo mode
1
0
AD Bit clock pin (AD_CK) polarity is inverted
AD Bit clock pin (AD_CK) polarity is not inverted
DSP and PCM formats in AD interface
Non delayed format
1
0
Delayed format
2
ADSYNCP
0
Delayed, left-aligned, right-aligned and SPI formats in AD interface
DA sync pin (DA_SYNC) polarity is inverted
1
0
DA sync pin (DA_SYNC) polarity is not inverted
1
Mono mode: (L+R)/2 from ADC is sent to both channels in the Audio
interface
1
0
ADMONO
ADHIZ
0
0
0
1
Stereo mode
AD data pin (AD_DATA) is in high impedance state when no data is
available
0
AD data pin (AD_DATA) is forced to 0 when no data is available
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Control registers
5.8
Digital filters, software reset and master clock control
CR#
(hex)
Description
D7
D6
D5
D4
D3
D2
D1
D0
Def.
CR29
(1Dh)
Digital filters
control
0000
0000
X
DAVOICE
X
DA96K
X
RXNH
X
ADVOICE
AMCKSIN
AD96K
ADNH
TXNH
CR30
(1Eh)
Soft reset &
AMCK range
0000
0000
SWRES
CKRANGE(2:0)
Table 23. CR29 description
Bits
Name
Value
CR29 description
Def.
1
0
DA path voice RX filter is enabled (single channel, left used)
DA path voice filters are enabled
6
DAVOICE
0
0
0
0
0
0
0
1
0
DA path data rate is in the range 88 kHz to 96 kHz
DA path data rate is in the range 8 kHz to 48 kHz
5
4
3
2
1
0
DA96K
RXNH
1
0
DA path high pass voice RX filter is disabled
DA path high pass voice RX filter is enabled (300Hz @ 8kHz rate)
1
0
AD path voice TX filter is enabled (single channel, left used)
AD path audio filters are enabled
ADVOICE
AD96K
ADNH
1
0
AD path data rate is in the range 88 kHz to 96 kHz
AD path data rate is in the range 8 kHz to 48 kHz
1
0
AD path audio DC filter is disabled
AD path audio DC filter is enabled
1
0
AD path high pass voice TX filter is disabled
TXNH
AD path high pass voice TX filter is enabled (300Hz @ 8kHz rate)
Table 24. CR30 description
Bits
Name
Value
CR30 description
Def.
1
0
Software reset: All registers content is reset to the default value
Control Register content is left unchanged
7
SWRES
0
1
0
Signal at AMCK pin is a sinusoid
3
AMCKSIN
0
Signal at AMCK pin is a square wave
AMCK range
MCKCOEFF
000
001
010
011
100
101
4.0 MHz to 6.0 MHz
6.0 MHz to 8.0 MHz
8.0 MHz to 12.0 MHz
12.0 MHz to 16.0 MHz
16.0 MHz to 24.0 MHz
24.0 MHz to 32.0 MHz
8.0
6.0
4.0
3.0
2.0
1.5
2-0
CKRANGE(2:0)
000
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Control registers
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5.9
Interrupt control and control interface SPI out mode
CR#
(hex)
Description
D7
D6
D5
D4
D3
D2
D1
D0
Def.
CR31
(1Fh)
PUSH
BEN
PUSH
BMSK
HSDET
MSK
0000
0000
VLSHEN
VLSH
x
HSDETEN VLSHMSK
OVFMSK PORMSK
Interrupt mask
Interrupt status
Misc. control
CR32
(20h)
0000
0000
PUSHB
X
HSDET
VLSHEV PUSHBEV HSDETEV
OVFEV
OVFDA
POREV
OVFAD
CR33
(21h)
0000
0000
SPIOHIZ
SPIOSEL(1:0)
IRQCMOS
Table 25. CR31 description
Bits
Name
Value
CR31description
Def.
1
0
VLSH status can be seen at IRQ output
VLSH status is masked
7
VLSHEN
0
1
0
PUSHB status can be seen at IRQ output
PUSHB status is masked
6
PUSHBEN
HSDETEN
VLSHMSK
PUSHBMSK
HSDETMSK
OVFMSK
0
0
0
0
0
0
0
1
0
HSDET status can be seen at IRQ output
HSDET status is masked
5
1
0
VLSH event can be seen at IRQ output
VLSH event is masked
4
1
0
PUSHB event can be seen at IRQ output
PUSHB event is masked
3
1
0
HSDET event can be seen at IRQ output
HSDET event is masked
2
1
1
0
OVF event can be seen at IRQ output
OVF event is masked
1
0
POR event can be seen at IRQ output
POR event is masked
0
PORMSK
Note:
Value at IRQ pin is:
IRQ =
⎧
⎨
⎩
(1 or Z) when (CR31 & CR32) = 00 hex
0
when (CR31 & CR32) ≠ 00 hex
Table 26. CR32 description
Read
Bits
Name
CR32 description
Def.
0
only
1
0
VCCLS is above 4.2 V
VCCLS is below 4.0 V
7
VLSH*
1
0
Headset Button is pressed
Headset Button is released
6
PUSHB*
HSDET*
0
1
0
Headset Connector is inserted
5
0
Headset Connector is not inserted
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Control registers
Table 26. CR32 description (continued)
Read
Bits
Name
CR32 description
Def.
0
only
1
0
VLSH bit has changed
4
VLSHEV
VLSH bit has not changed
1
0
Headset Button Status has changed
3
PUSHBEV
HSDETEV
OVFEV
0
Headset Button Status has not changed
1
0
Headset Connector Status has changed
Headset Connector Status has not changed
2
0
1
0
An Audio Data overflow has occurred in DSP
No Audio Data overflow has occurred in DSP
1
0
1
0
Device was reset by power-on-reset
0
POREV
0
Device was not reset by power-on-reset
Note: content of bits 4 to 0 in CR32 is cleared after reading, while it is left unchanged if accessed for writing.
*Bits 7 to 5 represent the status when the Control register is read, not when the event occurred.
Table 27. CR33 description
Bits
Name
Val.
CR33 description
Def.
1
SPI control interface out pin is set to high impedance state when
inactive
5
SPIOHIZ
0
0
SPI control interface out pin is set to zero when inactive
Out pin selection for SPI control interface
No output. Control registers cannot be read in SPI mode
SPI output sent to IRQ pin
00
01
10
11
4-3 SPIOSEL(1:0)
00
SPI output sent to DA_OCK pin
SPI output sent to AD_OCK pin
1
0
IRQ interrupt request pin is set to CMOS (active low)
IRQ interrupt request pin is set to pull down
2
1
0
IRQCMOS
OVFDA
0
0
0
1
0
An overflow (saturation) occurred in DA path
No overflow occurred in DA channel
1
0
An overflow (saturation) occurred in AD path
No overflow occurred in AD channel
OVFAD
Note: content of bits 1 to 0 in CR33 is cleared after reading, while it is left unchanged if accessed for writing.
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Control registers
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5.10
AGC
CR#
(hex)
Description
D7
D6
D5
D4
D3
D2
D1
D0
Def.
AGC
attack/decay
coeff.
CR34
(22h)
0000
0000
AGCATT(3:0)
AGCDEC(3:0)
CR35
(23h)
0000
0000
ENAG
CLIN
ENAG
CMIC
AGC
RANGE
X
AGCLEV(3:0)
AGC control
Table 28. CR 34 description
Bits
Name
Value
CR 34 description
AGC attack time constant; FS=AD data rate
Def.
Audio filter in AD path
4096 / FS
2048 / FS
1365 / FS
1024 / FS
683 / FS
Voice filter in AD path
8192 / FS
4096 / FS
2731 / FS
2048 / FS
1365 / FS
1024 / FS
683 / FS
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
512 / FS
7-4 AGCATT(3:0)
0000
341 / FS
256 / FS
512 / FS
171 / FS
341 / FS
128 / FS
256 / FS
85 / FS
171 / FS
64 / FS
128 / FS
43 / FS
85 / FS
32 / FS
64 / FS
AGC decay time constant; FS=AD data rate
Audio filter in AD path
Voice filter in AD path
131072 / FS
65536 / FS
43691 / FS
32768 / FS
21845 / FS
16384 / FS
10923 / FS
8192 / FS
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
65536 / FS
32768 / FS
21845 / FS
16384 / FS
10923 / FS
8192 / FS
5461 / FS
4096 / FS
2731 / FS
2048 / FS
1365 / FS
1024 / FS
683 / FS
3-0 AGCDEC(3:0)
0000
5461 / FS
4096 / FS
2731 / FS
2048 / FS
1365 / FS
512 / FS
1024 / FS
341 / FS
683 / FS
256 / FS
512 / FS
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Control registers
Table 29. CR 35 description
Bits
Name
Value
CR35 description
Def.
1
0
AGC control on AD path acts on Line In Gain
6
ENAGCLIN
0
AGC control on AD path does not act on Line In Gain
1
0
AGC control on AD path acts on Mic Gain
5
4
ENAGCMIC
AGCRANGE
0
0
AGC control on AD path does not act on Mic Gain
1
0
AGC action range is -21.0 dB to +21.0 dB
AGC action range is -10.5 dB to +10.5 dB
AGC requested output level
-30.0 dB gain
-30.0 dB gain
-27.0 dB gain
-24.0 dB gain
-21.0 dB gain
-18.0 dB gain
-15.0 dB gain
-12.0 dB gain
-9.0 dB gain
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
3-0 AGCLEV(3:0)
0000
-6.0 dB gain
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Control interface and master clock
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6
Control interface and master clock
Unless specified, the following description applies to both entities.
2
6.1
Control interface I C mode
Figure 5.
Control interface I2C format
ACK
ACK
ACK
DEVICE ADDRESS
0 0 1 1 0 1 AS0
REG n DATA IN
WRITE
SINGLE BYTE
REG n ADDRESS
START
STOP
ACK
REG n+m DATA IN
ACK
DEVICE ADDRESS
ACK
REG n DATA IN
ACK
ACK
WRITE
MULTI BYTE
REG n ADDRESS
0 0 1 1 0 1 AS0
START
m+1 data bytes
STOP
ACK
NO ACK
CURRENT ADDR
READ
SINGLE BYTE
DEVICE ADDRESS
Current REG DATA OUT
0 0 1 1 0 1 AS1
START
STOP
ACK
ACK
ACK
NO ACK
CURRENT ADDR
READ
MULTI BYTE
DEVICE ADDRESS
Current REG DATA OUT
Curr REG+m DATA OUT
0 0 1 1 0 1 AS1
START
m+1 data bytes
STOP
ACK
ACK
REG n ADDRESS
ACK
DEVICE ADDRESS
NO ACK
REG n DATA OUT
RANDOM ADDR
READ
DEVICE ADDRESS
0 0 1 1 0 1 AS0
START
0 0 1 1 0 1 AS1
START
ACK
REG n ADDRESS
SINGLE BYTE
STOP
ACK ACK
REG n DATA OUT
ACK
ACK
NO ACK
RANDOM ADDR
READ
MULTI BYTE
DEVICE ADDRESS
DEVICE ADDRESS
0 0 1 1 0 1 AS1
REG n+m DATA OUT
0 0 1 1 0 1 AS0
START
START
m+1 data bytes
STOP
Note:
CMOD pin tied to GND
Control interface: I2C format timing
Figure 6.
SDA
t
t
t
t
t
t
t
t
t
BUF
HD
(STA)
LOW
HD
(DAT)
HIGH
SU
(DAT)
SU
(STA)
HD
(STA)
SU
(STO)
SCLK
t
t
F
R
P
P = STOP
S = START
Sr = START repeated
S
S
P
r
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Control interface and master clock
Table 30. Control interface timing with I²C format
Symbol
fSCL
tHIGH
tLOW
Parameter
Clock frequency
Test conditions
Min.
Typ.
Max.
Unit
400
kHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Clock pulse width high
Clock pulse width low
SDA and SCLK rise time
SDA and SCLK fall time
Start condition hold time
Start condition setup time
Data input hold time
600
1300
tR
1000
300
tF
tHD:STA
tSU:STA
tHD:DAT
tSU:DAT
tSU:STO
tBUF
600
600
0
Data input setup time
Stop condition setup time
Bus free time
250
600
1300
6.2
Control interface SPI mode
Figure 7.
Control interface SPI format(a)
CSB
SCLK
SDIN
W/R A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
8 bit Address
8 bit Data
D7 D6 D5 D4 D3 D2 D1 D0
8 bit Data
SDO
SPIOHIZ=1
a. CMOD pin tied to V
; SDO pin position selected with bits SPIOSEL in CR33.
CCIO
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Control interface and master clock
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Figure 8.
Control interface: SPI format timing
tHICS
CSB
tPSCK
tSCSF
tHCS
tSCSR
tLSCK
tHSCK
SCLK
SDIN
SDO
0
8
15
tSDI
tHDI
W/R
D7
D0
D0
tDDOF
tDDO
tDDOL
SPIOHIZ=1
SPIOHIZ=0
D7
Table 31. Control interface signal timing with SPI format
Symbol
tHICS
Parameter
Test conditions
Min.
Typ.
Max.
Unit
CSB pulse width high
80
ns
Setup time CSB rising
edge to SCLK rising edge
tSCSR
tSCSF
tHCS
tSDI
20
20
20
20
20
ns
ns
ns
ns
ns
ns
ns
ns
Setup time CSB falling
edge to SCLK rising edge
Hold time CSB rising edge
from SCLK rising edge
Setup time SDIN to SCLK
rising edge
Hold time SDIN from SCLK
rising edge
tHDI
SDO first Delay time from
SCLK falling edge
tDDOF
tDDO
tDDOL
30
20
30
SDO Delay time from
SCLK falling edge
SDO Delay time from CSB
rising edge
tPSCK
tHSCK
tLSCK
Period of SCK
100
40
ns
ns
ns
SCK pulse width high
SCK pulse width low
Measured from VIH to VIH
Measured from VIL to VIL
40
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Control interface and master clock
6.3
Master clock timing
Table 32. AMCK timing
Symbol
Parameter
AMCK range
MHz-8 MHz
MHz-32 MHz
Min.
Typ.
Max.
Unit
4
8
45
40
55
60
%
%
tCKDC
AMCK duty cycle
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Audio interfaces
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7
Audio interfaces
Information included in the following section is valid for both entities.
Figure 9.
Audio interfaces formats: delayed, left and right justified
I2S format (delayed) with default polarity settings, ADHIZ=0
DA_SYNC/
AD_SYNC
DA_CK/
AD_CK
1 AD_CK/DA_CK
1 AD_CK/DA_CK
1
MSB
2
n-1
n
LSB
1
MSB
2
n-1
n
LSB
DA_DATA
AD_DATA
n-bit word Left data
n-bit word Right data
1
2
n-1
n
1
2
n-1
n
MSB
LSB
MSB
LSB
n-bit word Right data
n-bit word Left data
Left justified format with default polarity settings, ADHIZ=0
DA_SYNC/
AD_SYNC
DA_CK/
AD_CK
1
MSB
2
n-1
n
LSB
1
MSB
2
n-1
n
LSB
DA_DATA
AD_DATA
n-bit word Left data
n-bit word Right data
1
2
n-1
n
1
2
n-1
n
MSB
LSB
MSB
LSB
n-bit word Right data
n-bit word Left data
Right justified format with default polarity settings
32 AD_CK/DA_CK
32 AD_CK/DA_CK
DA_SYNC/
AD_SYNC
DA_CK/
AD_CK
1
MSB
2
n-1
n
LSB
1
MSB
2
n-1
n
LSB
DA_DATA
AD_DATA
n-bit word Left data
n-bit word Right data
1
2
n-1
n
1
2
n-1
n
MSB
LSB
MSB
LSB
n-bit word Right data
n-bit word Left data
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Audio interfaces
Figure 10. Audio interfaces formats: DSP, SPI and PCM
DSP format delayed and non-delayed (default AD_CK/DA_CK polarity, ADHIZ=0)
SYNCP=0
DA_SYNC/
AD_SYNC
{
SYNCP=1
DA_CK/
AD_CK
1
MSB
2
n-1
n
1
2
n-1
n
LSB
DA_DATA
AD_DATA
LSB MSB
n-bit word Left data
n-bit word Right data
1
2
n-1
n
1
2
n-1
n
MSB
LSB MSB
LSB
n-bit word Right data
n-bit word Left data
SPI format (slave only) (default AD_CK/DA_CK polarity, ADHIZ=1 - Stereo or Mono)
DA_SYNC/
AD_SYNC
DA_CK/
AD_CK
1
MSB
2
3
n-1
n
LSB
1
MSB
2
3
DA_DATA
AD_DATA
n-bit word Left/Mono data
n-bit word Right/Mono data
High impedance
x
1
2
3
n-1
n
x
1
2
3
MSB
LSB
MSB
n-bit word Left/Mono data
n-bit word Right/Mono data
PCM format (default AD_CK/DA_CK polarity, ADHIZ=1)
SYNCP=0
DA_SYNC/
AD_SYNC
{
SYNCP=1
DA_CK/
AD_CK
1
MSB
2
2
3
n-1
n-1
n
LSB
1
MSB
DA_DATA
n-bit word Mono data
High impedance
1
MSB
3
n
1
MSB
AD_DATA
LSB
n-bit word Mono data
55/85
Audio interfaces
STw5098
Figure 11. Audio interface timings: master mode
DA_SYNC/
AD_SYNC
tDSY
CKP=0
DA_CK/
AD_CK
{
CKP=1
tSDDA
tHDDA
DA_DATA
tDAD
tDAD
tDADZ
ADHIZ=1
ADHIZ=0
ADHIZ=1
AD_DATA
PCM format only
ADHIZ=0
tDAD
ADHIZ=1
ADHIZ=0
ADHIZ=1
ADHIZ=0
AD_DATA
All other formats
Figure 12. Audio interface timing: slave mode
DA_SYNC/
AD_SYNC
tHSY
tSSY
CKP=0
CKP=1
tHCK
tLCK
DA_CK/
AD_CK
{
tSDDA tHDDA
tPCK
DA_DATA
tDADST tDAD
tDADZ
ADHIZ=1
ADHIZ=0
ADHIZ=1
ADHIZ=0
AD_DATA
PCM format
tDAD
ADHIZ=1
ADHIZ=0
ADHIZ=1
ADHIZ=0
AD_DATA
All other formats
tDAD
56/85
STw5098
Audio interfaces
Table 33. Audio interface signal timings
Symbol
Parameter
Test conditions
Min.
Typ.
Max.
Unit
Delay of
AD_SYNC/DA_SYNC
edge from AD_CK/DA_CK
active edge
tDSY
Master Mode
10
ns
Setup time DA_DATA to
DA_CK active edge
tSDDA
tHDDA
tDAD
10
10
ns
ns
ns
Hold time DA_DATA from
DA_CK active edge
Delay of AD_DATA edge
from AD_CK active edge
30
30
Delay of the first AD_DATA
edge from AD_SYNC
active edge
AD_SYNC active edge comes
after AD_CK active edge
tDADST
ns
ns
Delay of AD_DATA high
impedance from
AD_SYNC inactive edge
tDADZ
PCM format
Slave Mode
10
20
50
Setup time
AD_SYNC/DA_SYNC to
AD_CK/DA_CK active
edge
tSSY
ns
ns
Hold time
AD_SYNC/DA_SYNCfrom
AD_CK/DA_CK active
edge
tHSY
Slave Mode
20
tPCK
tHCK
Period of AD_CK/DA_CK Slave Mode
100
40
ns
ns
AD_CK/DA_CK pulse
Measured from VIH to VIH
Measured from VIL to VIL
width high
AD_CK/DA_CK pulse
width low
tLCK
40
ns
57/85
Timing specifications
STw5098
8
Timing specifications
Information included in this section is valid for both entities.
Unless otherwise specified, VCCIO = 1.71V to 2.7V, Tamb = -30°C to 85°C, max capacitive
load 20 pF; typical characteristics are specified at VCCIO = 2.4 V, Tamb = 25 °C; all signals
are referenced to GND, see Note below figure for timing definitions.
Figure 13. A.C. testing input-output waveform
Input/output
0.8²VCCIO
0.7²VCCIO
0.3²VCCIO
0.7²VCCIO
0.3²VCCIO
TEST POINTS
0.2²VCCIO
AC Testing: inputs are driven at 0.8
•
VCCIO for a logic ‘1’ and 0.2
•
VCCIO for a logic ‘0’.
Timing measurements are made at 0.7•VCCIO for a logic ‘1’ and 0.3•VCCIO for a logic ‘0’.
Note:
Note:
A signal is valid if it is above VIH or below VIL and invalid if it is between VIL and VIH. For the
purpose of this specification the following conditions apply (see Figure 13 above):
a) All input signal are defined as: VIL = 0.2•VCCIO, VIH = 0.8•VCCIO, tR < 10ns, tF < 10ns.
b) Delay times are measured from the inputs signal valid to the output signal valid.
c) Setup times are measured from the data input valid to the clock input invalid.
d) Hold times are measured from the clock signal valid to the data input invalid.
All timing specifications subject to change.
58/85
STw5098
Operative ranges
9
Operative ranges
9.1
Absolute maximum ratings
Table 34. Absolute maximum ratings
Parameter
Value
Unit
VCC or VCCIO to GND
-0.5 to 3.6
-0.5 to 5
-0.5 to 7
V
V
V
V
CCA or VCCP to GND
CCLS to GND
V
Voltage at analog inputs (VCCA ≤3.3V)
Maximum power delivered to the load from LSP/N
Peak current at HPR,HPL
GND-0.5 to VCCA+0.5
V
mW
mA
mA
mA
V
500
100
350
Current at VCCP, VCCLS, GNDP
Current at any digital output
50
Voltage at any digital input (VCCIO ≤2.7V); limited at ± 50mA
Storage temperature range
GND-0.5 to VCCIO+0.5
-65 to 150
-30 to 85
°C
Operating temperature range(1)
°C
Electrostatic discharge voltage (Vesd)
Human body model(2)
Charge device model(3)
-2 to +2
kV
V
-500 to +500
1. in some operating conditions the temperature can be limited to 70 °C. See loudspeaker driver description from Section 4.10
for details.
2. HBM tests have been performed in compliance with JESD22-A114-B and ESD STM 5.1-2001.HBM
3. CDM tests have been performed in compliance with CDM ANSI-ESDSTM5.3.1-1999
9.2
Operative supply voltage
Table 35. Operative supply voltage
Symbol Parameter
VCC Digital supply
Condition
Min.
Max.
Unit
1.71
2.7
V
Analog supply
A24V=0 (bit 1 in CR0)
A24V=1 (bit 1 in CR0)
2.7
2.4
3.3
2.7
V
V
VCCA
Note: VCCA ≥ VCC
D12V=0 (bit 0 in CR0)
D12V=1 (bit 0 in CR0)
1.71
1.2
VCC
1.8
V
V
VCCIO
Digital I/O supply
VCCP
Stereo power drivers supply
Mono power driver supply
VCCA
VCCA
3.3
5.5
V
V
VCCLS
VCC
=
VCCA
=VCCIO=VCCP=VCCLS
VG
Single supply voltage range
2.4
2.7
V
A24V=1 (bit 1 in CR0)
59/85
Operative ranges
STw5098
9.3
Power dissipation
Unless otherwise specified, VCCP = VCCLS = VCCA = 2.7V to 3.3V, VCCIO = VCC = 1.71V to
2.7V, Tamb = -30°C to 85°C, all analog outputs not loaded; typical characteristics are
specified at VCCIO = VCC = 1.8V, VCCP = VCCLS = VCCA = 2.7V, Tamb = 25°C.
Table 36. Power dissipation
Symbol
Parameter
Test conditions
No Master Clock
AMCK=13MHz
Min.
Typ.
Max.
Unit
0.8
5.8
µW
µW
POFF
Power Down Dissipation
PAD
Stereo ADC power
52.6
46.6
93.8
27.6
mW
mW
mW
mW
PDA
Stereo DAC power
PDAAD
PAA
Stereo ADC+DAC power
Stereo Analog Path power
9.4
Typical power dissipation by entity
Tamb = 25°C; Analog Supply: VCCP = VCCLS = VCCA = 2.7V;
digital supply: VCCIO = VCC = 1.8V.
Full scale signal in every path, 20kΩ load at analog outputs.
No master clock
Table 37. Typical power dissipation, no master clock
CR0-CR2
N.
Function
Other settings
Supply
Analog:
Current
Power
setting
CR0=0x00
CR1=0x00
CR2=0x00
0.02 µA
0.20 µA
0.05 µW
0.36 µW
0.41 µW
1
Power Down
Digital:
Total:
CR0=0xD0
CR1=0x0C
CR2=0xC0
Analog:
Digital:
Total:
4.3 mA
11.6 mW
0.0 mW
Stereo analog path
(Mic-LO)
MICLO=1
2
3
2.0 µA
MICSEL=2
11.6 mW
Analog:
Digital:
Total:
5.4 mA
14.6 mW
0.0 mW
CR0=0xD0;
CR1=0x0C;
CR2=0xC3
Stereo analog path
(Mic-Mixer-LO)
MIXMIC=1
MICSEL=2
2.0 µA
14.6 mW
60/85
STw5098
Operative ranges
Master clock AMCK = 13 MHz
Table 38. Typical power dissipation with master clock AMCK = 13 MHz
CR0-CR2
N.
Function
Other settings
Supply
Current
Power
setting
CR0=0x00
CR1=0x00
CR2=0x00
Analog:
0.02 µA
2.20 µA
0.05 µW
3.96 µW
4.01 µW
4
Power Down
Digital:
Total:
CR0=0xE8
CR1=0xCC
CR2=0x00
Analog:
Digital:
Total:
7.9 mA
2.8 mA
21.3 mW
5.0 mW
MICSEL=1
5
6
7
8
9
Stereo ADC
Stereo DAC
ADMIC=1
26.3 mW
CR0=0xE8
CR1=0x30
CR2=0x33
Analog:
Digital:
Total:
6.1 mA
3.8 mA
16.5 mW
6.8 mW
MIXDAC=1
23.3 mW
CR0=0xE8
CR1=0x0C
CR2=0xC0
Analog:
Digital:
Total:
4.8 mA
0.8 mA
13.0 mW
1.4 mW
Stereo analog path
(Mic-LO)
MICLO=1
MICSEL=2
13.8 mW
CR0=0xE8
CR1=0xFC
CR2=0x33
MICSEL=2
ADMIC=1
MIXDAC=1
Analog:
Digital:
Total:
13.5 mA
5.8 mA
36.5 mW
10.4 mW
46.9 mW
Stereo ADC
Stereo DAC
Stereo ADC
Stereo DAC
CR0=0xE8
CR1=0xFF
LINSEL=2; MICSEL=2
ADLIN=1;MIXDAC=1
MICLO=1
Analog:
Digital:
Total:
15.2 mA
5.8 mA
41.0 mW
10.4 mW
51.4 mW
Stereo analog path CR2=0xF3
MICSEL=2;
LSMODE=2
VCCA,VCCP
:
:
6.8 mA
1.3 mA
2.5 mA
18.4 mW
5.5 mW
4.5 mW
28.4 mW
CR0=0xE8
VCCLS
ADMIC=1 MIXDAC=1
ADVOICE=1
10 Voice TX+RX
CR1=0xA8
CR2=0x06
Digital
Total:
DAVOICE=1
61/85
Electrical characteristics
STw5098
10
Electrical characteristics
Unless otherwise specified, VCCIO = 1.71V to 2.7V, Tamb = -30°C to 85°C; typical
characteristic are specified at VCCIO = 2.0V, Tamb = 25°C; all signals are referenced to GND.
10.1
Digital interfaces
Table 39. Digital interfaces specifications
Symbol
Parameter
Test conditions
All digital inputs
Min.
Typ.
Max.
Unit
DC
AC
0.3•VCCIO
0.2•VCCIO
V
V
VIL
Input low voltage
All digital inputs,
DC
AC
0.7•VCCIO
0.8•VCCIO
V
V
VIH
VOL
VOH
IIL
Input high voltage
Output low voltage
Output high voltage
Input low current
Input high current
All digital outputs IL = 10µA
IL = 2µA
0.1
0.4
V
V
All digital outputs IL = 10µA
IL = 2µA
VCCIO-0.1
VCCIO-0.4
V
V
Any digital input,
GND < VIN < VIL
-1
-1
1
1
µA
µA
Any digital input,
VIH < VIN < VCCIO
IIH
Output current in
high impedance
(Tristate)
IOZ
Tristate outputs
-1
1
µA
Note:
See Figure 13: A.C. testing input-output waveform on page 58.
10.2
AMCK with sinusoid input
Table 40. AMCK with sinusoid input specifications
Symbol
Parameter
Test conditions
Min.
Typ.
Max.
Unit
Minimum External
Capacitance
CAMCK
AMCKSIN=1, see CR30
100
pF
AMCK sinusoidal voltage
swing
VAMCK
AMCKSIN=1, see CR30
0.5
VCCIO
VPP
62/85
STw5098
Electrical characteristics
10.3
Analog interfaces
Information below is for each entity.
Table 41. Analog interface specifications
Symbol
IMIC
Parameter
Test conditions
GND< VMIC< VCCA
Min.
Typ.
Max.
Unit
MIC input leakage
-100
30
+100
µA
kΩ
kΩ
RMIC
RLIN
MIC input resistance
Line in input resistance
50
30
Headphones (HP) drivers HPL, HPR to GNDP or
RLHP
14.4
30
16/32
32
Ω
Ω
Ω
load resistance
VCMHP
Earphone (EAR) drivers
load resistance
RLEAR
RLLS
1 EARP to 1EARN
Loudspeaker (LS) drivers
load resistance
2LSP to 2LSN
6.4
8
Headphones (HP) drivers HPL, HPR to GNDP or
50
50*
pF
nF
CLHP
load capacitance
VCMHP
Earphone (EAR) drivers
load capacitance
50
50*
pF
nF
CLEAR
CLLS
VOFFLS
VOFFEAR
1 EARP to 1EARN
Loudspeaker (LS) drivers
load capacitance
50
50*
pF
nF
2LSP to 2LSN
Differential offset voltage
at 2LSP, 2LSN
RL = 50Ω
-50
-50
+50
+50
mV
mV
Differential offset voltage
at 1EARP, 1EARN
RL = 50Ω
OLP/ORP to OLN/ORN or
Line out (OL) diff./single-
ended driver load
resistance
RLOL
1
kΩ
OLP/ORP to GND
(decoupled)
* with series resistor
63/85
Electrical characteristics
STw5098
10.4
Headset plug-in and push-button detector
Information below is for each entity.
Table 42. Headset plug-in and push-button detector specifications
Symbol
HDVL
Parameter
Test conditions
Voltage at HDET
Min.
Typ.
Max.
Unit
Plug-in detected
VCCA-1
V
V
HDVH
HDH
Plug-in undetected
Voltage at HDET
VCCA-0.5
Plug-in detector hysteresis
Push-button pressed
Push-button released
100
mV
V
PBVL
PBVH
Voltage at HDET
Voltage at HDET
0.5
50
1
V
Push-button de-bounce
time
PBD
15
ms
10.5
Microphone bias
Information below is for each entity.
Table 43. Microphone bias specifications
Symbol
Parameter
Test conditions
Min.
Typ.
Max.
Unit
MBIAS output
voltage
VMBIAS
1.95
2.1
2.25
1.1
V
MBIAS output
current
IMBIAS
From MBIAS to ground
mA
kΩ
pF
RMBIAS
CMBIAS
MBIAS output load
3.5
MBIAS output
capacitance
150
PSRMB4
PSRMB20
MBIAS power
supply rejection
f<4kHz
f<20kHz
60
50
dB
dB
10.6
Power supply rejection ratio
Table 44. Power supply rejection ratio specifications
Symbol
Parameter
Test conditions
Min.
Typ.
Max.
Unit
Each output (LSP, LSN)
f<20kHz
PSRL20
PSRL200
PSRR VCCLS
65
47
dB
dB
f<200kHz
PSRPH
PSRPOS
PSRPOD
Headphones f<20kHz
Line out single ended f<20kHz
Line out differential f<20kHz
65
65
65
dB
dB
dB
PSRR VCCP
PSRR VCCA
PSRAM
PSRAL
Mic input f<20kHz
Line In f<20kHz
50
50
dB
dB
64/85
STw5098
Electrical characteristics
10.7
LS and EAR gain limiter
Information below is for each entity.
Table 45. LS and EAR gain limiter
Symbol
Parameter
Test conditions
CCLS raising
VCCLS falling
Min.
Typ.
Max.
Unit
High voltage at VCCLS
(VLSH=1)
VLSLIMH
V
4.2
V
Low voltage at VCCLS
(VLSH=0)
VLSLIML
VLSLIMD
4.0
V
VCCLS Hysteresis
200
mV
Note: See CR32 for VLSH definition. See Loudspeaker driver description in Section 4.10 for details.
65/85
Analog input/output operative ranges
STw5098
11
Analog input/output operative ranges
Information included in this section applies to both entities.
11.1
Analog levels
Table 46. Reference full scale analog levels
Symbol
Parameter
Test conditions
Min.
Typ.
Max.
Unit
12
4
dBVpp
Vpp
0dBFS level
2.7V < VCCA < 3.3V
10
dBVpp
Vpp
0dBFS level low voltage
mode
2.4V < VCCA < 2.7V
3.18
11.2
Microphone input levels
Analog supply range: 2.7 V < VCCA < 3.3 V
Table 47. Microphone input levels, absolute levels at pins connected to preamplifiers
Symbol
Parameter
Test conditions
Min.
Typ.
Max.
Unit
707
2
-6
mVRMS
Vpp
dBFS
Overload level, single
ended
MIC gain = 0 to 6dB
Overload level, single
ended, versus MIC gain
MIC gain > 6dB
−(MIC_Gain)
dBFS
1.41
4
mVRMS
Vpp
Overload level, differential MIC gain = 0dB
0
dBFS
Overload level, differential,
MIC gain > 0dB
−(MIC_Gain)
dBFS
versus MIC gain
Note: When 2.4 V < V
< 2.7 V, voltage values are reduced by 2dB.
CCA
Table 48. Microphone input levels, absolute levels at pins connected to the line-in amplifiers
Symbol
Parameter
Test conditions
Min.
Typ.
Max.
Unit
707
2
-6
mVRMS
Vpp
dBFS
Overload level, single
ended
Line in gain from −20dB to 6dB
Overload level (single
ended) versus line in gain
Line in gain > 6dB
−(Line_In_Gain)
dBFS
1.41
4
0
mVRMS
Vpp
dBFS
Overload level (differential) Line in gain from −20dB to 0dB
66/85
STw5098
Analog input/output operative ranges
Table 48. Microphone input levels, absolute levels at pins connected to the line-in amplifiers
Symbol
Parameter
Test conditions
Line in gain > 0dB
Min.
Typ.
Max.
Unit
Overload level (differential)
versus line in gain
−(Line_In_Gain)
dBFS
Note: When 2.4 V < V
< 2.7 V, the values are reduced by 2dB
CCA
11.3
Line output levels
Analog supply range: 2.7 V < VCCA < 3.3 V
Table 49. Absolute levels at OLP/OLN, ORP/ORN
Symbol
Parameter
Test conditions
Min.
Typ.
Max.
Unit
707
2
-6
mVRMS
Vpp
dBFS
0 dB gain
Full scale digital input
Output level, single ended
1.41
4
0
mVRMS
Vpp
dBFS
0 dB gain
Output level, differential
Full scale digital input
Note: When 2.4 V < V
< 2.7 V, the values are reduced by 2dB
CCA
11.4
Power output levels HP
Analog supply range: 2.7 V < VCCA < 3.3 V
Table 50. Absolute levels at HPL - HPR
Symbol Parameter
Test conditions
Min.
Typ.
Max.
Unit
707
2
mVRMS
Vpp
-6dB gain
Output level
Full scale digital input
-6
dBFS
16 Ω load
Max output power(1)
40
mW
VCCP > 3.2 V
1. In some operating conditions the maximum output power can be limited. See “Section 9.1: Absolute maximum ratings” and
“loudspeaker driver” description from Section 4.10: Analog output drivers for details.
Note: When 2.4 V < V
< 2.7 V, the values are reduced by 2dB
CCA
11.5
Power output levels LS and EAR
Analog supply range: 2.7 V < VCCA < 3.3 V
67/85
Analog input/output operative ranges
STw5098
Unit
Table 51. Absolute levels at 1EARP-1EARN and 2LSP - 2LSN
Symbol
Parameter
Test conditions
Min.
Typ.
Max.
1.41
4
VRMS
Vpp
0 dB gain
Output level
Full scale digital input
0
dBFS
32 Ω load
Max EAR output power
Max LS output power(1)
125
500
mW
VCCLS > 4V
8 Ω load
VCCLS > 4V
mW
1. In some operating conditions the maximum output power can be limited. See “Section 9.1: Absolute maximum ratings” and
“loudspeaker driver” description from Section 4.10: Analog output drivers for details.
Note: When 2.4 V < V
< 2.7 V, the values are reduced by 2dB
CCA
68/85
STw5098
Stereo audio ADC specifications
12
Stereo audio ADC specifications
Information included in this section applies to both entities. Typical measures at
VCCA=VCCP=VCCLS=2.7V; VCCIO=VCC=1.8 V; Tamb=25° C;13 MHz AMCK
Table 52. Stereo audio ADC specifications
Symbol
ADN
Parameter
Resolution
Test conditions
Min.
Typ.
Max.
Unit
20
Bits
20Hz to 20kHz, A-weighted
Measured at -60dBFS
ADDRM
ADDRLI
Dynamic range
87
89
91
93
dB
dB
MIC input, 21dB gain
Line-In, 0dB gain
Max level at MIC input, 21dB gain
ADSNA
ADSN
Signal to noise ratio
A-weighted
Unweighted (20 Hz to 20 kHz)
90
86
dB
dB
A-weighted
Mic input 0dB gain
Mic input 21dB gain
Mic input 39dB gain
Line in input 0dB gain
Line in input 18dB gain
37
3.3
1.9
30
µV
µV
µV
µV
µV
Input referred ADC
noise
7.5
Total harmonic
distortion
ADTHD
Max level at MIC input, 21dB gain
0.001
0.003
1
%
Measurement bandwidth 20Hz to
20kHz, Fs= 48kHz. Combined digital
and analog filter characteristics
Deviation from
linear phase
Deg
Combined digital and analog filter
characteristics AD96K=0
ADfPB
Passband
0
0.45Fs
0.2
kHz
dB
Combined digital and analog filter
characteristics AD96K=0
Passband ripple
Stopband
Combined digital and analog filter
characteristics AD96K=0
ADfSB
0.55Fs
60
kHz
Measurement bandwidth up to
3.45Fs. Combined digital and analog
filter characteristics, AD96K=0
Stopband
Attenuation
dB
Audio filters, 96kHz FS
Audio filters, 48kHz FS
Audio filters, 8kHz FS
0.11
0.4
2.6
ms
ms
ms
ADtgd
Group delay
Interchannel
isolation
90
dB
Interchannel gain
mismatch
0.2
0.5
dB
dB
Gain error
Note: When 2.4 V < V
< 2.7 V, the values are reduced by 2dB
CCA
69/85
Stereo audio DAC specifications
STw5098
13
Stereo audio DAC specifications
Information included in this section applies to both entities.
Typical measures at VCCA=VCCP=VCCLS=2.7V; VCCIO=VCC=1.8V; Tamb=25° C;13MHz
AMCK
Table 53. Stereo audio DAC specifications
Symbol
DAN
Parameter
Resolution
Test conditions
Min.
Typ.
Max.
Unit
20
Bits
20Hz to 20kHz, A-weighted.
Measured at -60dBFS
Differential line out
90
95
93
94
94
dB
dB
dB
dB
DADR
Dynamic range
Single-ended line out
HPL/HPR to GND or VCMHP
LSP-LSN
2Vpp output
HPL, HPR gain set to -6dB, 16Ω load
DASNA
DASN
Signal to noise ratio
A-weighted
94
90
dB
dB
Unweighted (20 Hz to 20 kHz)
Total harmonic
distortion
2Vpp output
DATHDL
DATHD
0.02
0.04
%
%
HPL, HPR gain set to -6dB, 16Ω load
Worst case load
Total harmonic
distortion
2Vpp output,
HPL, HPR gain set to -6dB, 1kΩ load
0.004
Measurement bandwidth 20Hz to
20kHz, Fs= 48kHz.
Deviation from
linear phase
1
Deg
Combined digital and analog filter
characteristics
Combined digital and analog filter
characteristics, DA96K=0
DAfPB
Passband
0
0.45Fs
0.2
kHz
dB
Combined digital and analog filter
characteristics, DA96K=0
Passband ripple
Stopband
Combined digital and analog filter
characteristics, DA96K=0
DAfSB
0.55Fs
50
kHz
Measurement bandwidth up to
3.45Fs.
Combined digital and analog filter
characteristics, DA96K=0
Stopband
attenuation
dB
Transient
TSF
suppression filter
cut-off frequency
15
23
Hz
Measurement bandwidth 20 kHz to
100 kHz. Zero input signal
Out of band noise
-85
dBr
70/85
STw5098
AD to DA mixing (sidetone) specifications
Table 53. Stereo audio DAC specifications (continued)
Symbol
Parameter
Test conditions
Min.
Typ.
Max.
Unit
Audio filters, 96kHz FS
0.09
0.4
ms
ms
ms
DAtgd
Group delay
Audio filters, 48kHz FS
Audio filters, 8kHz FS
2.6
2Vpp output
HPR, HPL unloaded
100
60
dB
dB
Interchannel
isolation
HPR, HPL with 16Ω to VCMHP
Interchannel gain
mismatch
0.2
0.5
dB
dB
Gain error
Startup time from
power up
FS=48 kHz
Line out
HPL/R out
1
10
ms
ms
SUT
Note: When 2.4 V < V
< 2.7 V, values are reduced by 2 dB
CCA
14
AD to DA mixing (sidetone) specifications
Information included in this section applies to both entities.
Typical measures at VCCA=VCCP=VCCLS=2.7V; VCCIO=VCC=1.8V; Tamb=25° C;13MHz
AMCK.
Table 54. AD to DA mixing (sidetone) specifications
Symbol
Parameter
Test conditions
Min.
Typ.
Max.
Unit
AD to DA mixing
(sidetone) delay
STDEL
Valid for audio and voice filters
5
10
µs
71/85
Stereo analog-only path specifications
STw5098
15
Stereo analog-only path specifications
Information included in this section applies to both entities.
Measured at differential line-out, ENOSC=1, No master clock.
Typical measures at VCCA=VCCP=VCCLS=2.7V; VCCIO=VCC=1.8V; Tamb=25° C
Table 55. Stereo analog-only path specifications
Symbol
Parameter
Test conditions
Min.
Typ.
Max.
Unit
20Hz to 20kHz, A-weighted.
Measured at -60dBFS
AADRM
AADRLI
Dynamic range
MIC input, 21dB gain
90
90
95
97
dB
dB
Line-In, 0dB gain
Max level at line-in input, 0dB gain,
AASNA
AASN
Signal to noise ratio
97
94
dB
dB
A-weighted
Unweighted (20 Hz to 20 kHz)
1kHz @ 0dBFS
Total harmonic
distortion
AATHD
MIC input, 21dB gain
Line-in input, 0dB gain
0.003
0.004
0.01
0.02
%
%
Note: When 2.4V<V
<2.7V, the values are reduced by 2dB.
CCA
72/85
STw5098
ADC (TX) & DAC (RX) specifications with voice filters selected
16
ADC (TX) & DAC (RX) specifications with voice filters
selected
Information included in this section applies to both entities.
Typical measures at VCCA=VCCP=VCCLS=2.7V; VCCIO=VCC=1.8V; Tamb=25° C;13MHz
AMCK
Table 56. ADC (TX) & DAC (RX) specifications with voice filters selected
Symbol
Parameter
Test conditions
Min.
Typ.
Max.
Unit
300Hz to 3.4kHz; 1kHz @ -60dBFS
TX Path, MIC input, 21dB gain
RX Path, LS Output, 0dB gain
TXDR
Dynamic range
86
83
89
86
dB
dB
RXDR
300Hz to 3.4kHz; 1kHz @ 0dBFS
TX Path, MIC input, 21dB gain
TXSN
RXSN
Signal to noise ratio
THD
88
86
dB
dB
RX Path, LS and EAR outputs, 0dB gain
1kHz @ 0dBFS
THD
TXG
TX Path, MIC input, 21dB gain
RX Path, LS and EAR outputs, 0dB gain
<0.001
0.005
%
%
f=60Hz
f=100Hz
-30
-24
-6
dB
dB
dB
dB
dB
dB
dB
dB
dB
f=200Hz
f=300Hz
-1.5
-0.5
-1.5
0.5
0.5
0.0
-14
-35
-47
TX gain mask
f=400Hz-3000Hz
f=3400Hz
f=4000H
f=4600Hzz
f=8000Hz
f=60Hz
f=100Hz
-20
-12
-2
dB
dB
dB
dB
dB
dB
dB
dB
f=200Hz
f=300Hz
-1.5
-0.5
-1.5
0.5
0.5
0.0
-14
-50
RXG
RX gain mask
f=400Hz-3000Hz
f=3400Hz
f=4000Hz
f=5000Hz
RX out of band
noise
Measurement bandwidth 4kHz to
100kHz. Zero input signal
-85
dBr
TX path
RX path
0.32
0.28
ms
ms
Group delay
Note: When 2.4V<V
<2.7V, the values are reduced by 2dB
CCA
73/85
Typical performance plots
STw5098
17
Typical performance plots
Figure 14. Bass treble control, de-emphasis
Figure 15. Dynamic compressor transfer
filter
function
15
1
0.75
0.5
10
5
0.25
0
0
-5
-0.25
-0.5
-0.75
-1
-10
-15
100
1k
10k
-1 -0.75-0.5-0.25 0 0.25 0.5 0.75 1
Input Amplitude [FS]
Frequency [Hz]
Bass and treble gains are independently selectable in any combination.
The de-emphasis filter (thick line, alternative to treble control)
compensates for pre-emphasis used on some audio CDs.
Audio signal transfer function when the Dynamic Compressor is active.
Gain error < 0.1dB. Filter characteristics at Fs=44.1kHz are plotted
Figure 16. ADC audio path measured filter
response
Figure 17. ADC in band audio path measured
filter response
0.5
0.4
0.3
0.2
0.1
0
-0.1
-0.2
-0.3
-0.4
-0.5
0
-10
-20
-30
-40
-50
-60
-70
-80
100
1k
10k
100k
0
5k
10k
15k
20k
Frequency [Hz]
Frequency [Hz]
48 kHz sample rate.
Full ADC path Frequency response up to 100 kHz.
48 kHz Sample Rate.
In band Frequency response
Figure 18. DAC digital audio filter
characteristics
Figure 19. DAC in band digital audio filter
characteristics
0.5
0.4
0.3
0.2
0.1
0
-0.1
-0.2
-0.3
-0.4
-0.5
0
-20
-40
-60
-80
100
1k
10k
100k
0
5k
10k
15k
20k
Frequency [Hz]
Frequency [Hz]
DA96K=0; 48 kHz Sample Rate
Frequency response up to 166kHz (3.45 Fs @ 48kHz sampling rate)
48 kHz Sample Rate
In band Frequency response
74/85
STw5098
Typical performance plots
Figure 20. ADC 96 kHz audio path measured Figure 21. ADC 96 kHz audio in-band
filter response
measured filter response
1
0
0
-10
-20
-30
-40
-50
-60
-70
-80
-1
-2
-3
-4
-5
0
5k 10k 15k 20k 25k 30k 35k 40k 45k
Frequency [Hz]
10
100
1k
10k
100k
Frequency [Hz]
The plot is extended down to 5 Hz to show the high pass filter
implemented in the ADC 96 kHz sample rate,
96 kHz audio filter selected signal from Mic input
96 kHz sample rate,
96 kHz audio filter selected signal from Mic input.
Figure 22. ADC voice TX path measured filter Figure 23. ADC voice TX path measured in-
response
band filter response
0.5
0.4
0.3
0.2
0.1
0
-0.1
-0.2
-0.3
-0.4
-0.5
0
-10
-20
-30
-40
-50
-60
-70
500 1k 1500 2k 2500 3k 3500 4k
Frequency [Hz]
100
1k
Frequency [Hz]
10k
8 kHz sample rate, tx voice filter selected signal from Mic input.
8 kHz Sample rate, tx voice filter selected.
Signal from Mic input
Figure 24. DAC voice (RX) digital filter
characteristics
Figure 25. DAC voice (RX) in-band digital filter
characteristics
0.5
0.4
0.3
0.2
0.1
0
-0.1
-0.2
-0.3
-0.4
0
-10
-20
-30
-40
-50
-60
-70
-0.5
100
1k
10k
500 1k 1500 2k 2500 3k 3500 4k
Frequency [Hz]
Frequency [Hz]
8 kHz sample rate, rx voice filter
8 kHz sample rate, rx voice filter
75/85
Typical performance plots
Figure 26. ADC path FFT
STw5098
Figure 27. ADC S/N versus input-level
100
90
80
70
60
50
40
30
20
0
-20
-40
-60
-80
-100
-120
-60
-50
-40
-30
-20
-10
0
0
2k 4k 6k 8k 10k 12k 14k 16k 18k 20k
Frequency [Hz]
Input Level [dBFS]
12 MHz master clock.
12 MHz master clock
Differential input at Mic preamplifier, 21 dB gain.
48 kHz sampling rate.
Differential input at Line-In Amplifier, 0 dB gain.
48 kHz Sampling Rate
Both channels active
A-Weighted, Both channels active
Figure 28. DAC path FFT
Figure 29. DAC S/N versus input-level
100
90
80
70
60
50
40
30
20
0
-20
-40
-60
-80
-100
-120
0
2k 4k 6k 8k 10k 12k 14k 16k 18k 20k
Frequency [Hz]
-60
-50
-40
-30
-20
-10
0
Input Level [dBFS]
12 MHz master clock.
48 kHz sampling rate
Differential output at line-out, 1kΩ load.
Both channels active
12 MHz master clock.
48 kHz Sampling Rate
Differential output at Line-Out, 1kΩ load.
A-Weighted, Both channels active
Figure 30. Analog path FFT
Figure 31. Analog path S/N versus input-level
100
90
80
70
60
50
40
30
20
0
-20
-40
-60
-80
-100
-120
-60
-50
-40
-30
-20
-10
0
0
2k 4k 6k 8k 10k 12k 14k 16k 18k 20k
Frequency [Hz]
Input Level [dBFS]
Differential input at Mic Preamplifier, 21 dB gain.
Direct Mic to Line-Out connection (MICLO=1)
Differential input at Line-In Amplifier, 0 dB gain.
Line-In to DA-Mixer to Line-Out connection.
Differential output at Line-Out, 20kΩ load. Both channels active
Differential output at Line-Out, 20kΩ load. A-weighted, both channels
active
76/85
STw5098
Package mechanical data
18
Package mechanical data
In order to meet environmental requirements, ST offers these devices in ECOPACK®
packages. These packages have a Lead-free second level interconnect. The category of
second Level Interconnect is marked on the package and on the inner box label, in
compliance with JEDEC Standard JESD97. The maximum ratings related to soldering
conditions are also marked on the inner box label. ECOPACK is an ST trademark.
ECOPACK specifications are available at: www.st.com.
77/85
Package mechanical data
STw5098
18.1
LFBGA 6x6x1.4
Table 57. Dimensions of LFBGA 6x6x1.4 112 4R11x11. 0.5
Databook (mm)
Typ.
Drawing (mm)
Reference
Notes
Min.
Max.
Min.
Typ.
Max.
A
1.40
1.26
0.26
1.04
0.24
0.80
0.35
6.10
Note 1
A1
A2
A3
A4
b
0.15
0.16
0.93
0.16
0.77
0.25
5.90
0.21
0.985
0.20
0.785
0.30
6.00
5.00
6.00
5.00
0.50
0.50
0.985
0.20
0.80
0.35
6.15
0.25
5.85
0.30
6.00
5.00
6.00
5.00
0.50
0.50
Note 2
D
D1
E
5.85
6.15
5.90
6.10
E1
e
F
ddd
eee
fff
0.08
0.15
0.05
0.08
0.15
0.05
Note 4
Note 5
Note:
1
LFBGA stands for Low Profile Fine Pitch Ball Grid Array.
- Low profile: the total profile height (DIm A) is measured from the seating plane to the top of
the component. The maximum total package height is calculated as follows:
2
2
2
A2Typ + A1Typ + (A1 + A3 + A4 tolerancevalues) . Fine pitch: e<1.0 mm pitch
2
3
The typical ball diameter before mounting is 0.30 mm
The tolerance of position that controls the location of the pattern of balls with respect to
datum A and B. For each ball there is a cylindrical tolerance zone eee perpendicular to
datum C and located on true position with respect to datum A and B as defined by e. The
axis perpendicular to datum C of each ball must lie within this tolerance zone.
4
5
The tolerance of position that controls the location of the balls within the matrix with respect
to each other. For each ball there is a cylindrical tolerance zone fff perpendicular to datum C
and located on true position as defined by e. The axis perpendicular to datum C of each ball
must lie within this tolerance zone. Each tolerance zone fff in the array is contained entirely
in the respective zone eee above.
The axis of each ball must lie simultaneously in both tolerance zones.
The terminal A1 corner must be identified on the top surface by using a corner chamfer, ink
or metallized markings, or other feature of package body or integral heatslug. A
distinguishing feature is allowable on the bottom surface of the package to identify the
terminal A1 corner. Exact shape of each corner is optional.
78/85
STw5098
Package mechanical data
Figure 32. LFBGA 6x6x1.4 112 4R11x11 0.5 drawing
SEATING
PLANE
C
D
D1
e
f
K
J
I
H
G
F
E
D
C
B
A
1 2 3 4 5 6 7 8 9 10 11
BOTTOM VIEW
A1 CORNER INDEX AREA Øb (112 BALLS)
(SEE NOTE 3)
79/85
Package mechanical data
STw5098
18.2
VFBGA 5x5x1.0
Table 58. Dimensions of VFBGA 5x5x1.0 112 balls 0.4 mm pitch
Databook (mm)
Typ.
Drawing (mm)
Typ.
Reference
Notes
Min.
Max.
Min.
Max.
A
1.00
0.99
0.205
0.82
0.22
0.60
0.30
5.05
Note 1
A1
A2
A3
A4
b
0.125
0.125
0.71
0.14
0.57
0.22
4.95
0.165
0.765
0.18
0.585
0.26
5.00
4.00
5.00
4.00
0.40
0.50
0.765
0.18
0.60
0.30
5.05
0.22
4.95
0.26
5.00
4.00
5.00
4.00
0.40
0.50
Note 2
D
D1
E
4.95
5.05
4.95
5.05
E1
e
Note 3
F
ddd
eee
fff
0.08
0.13
0.04
0.08
0.13
0.04
Note 4
Note 5
Note:
1
VFBGA stands for Very thin Profile Fine Pitch Ball Grid Array.
The maximum total package height is calculated by the following methodology:
A2Typ + A1Typ + (A1 + A3 + A4 tolerancevalues) .
2
2
2
Very thin profile: 0.80mm < A ≤1.00mm Max/Fine pitch: e<1.0 mm
2
3
4
The typical ball diameter before mounting is 0.25 mm
VFBGA with 0.40mm ball pitch is not yet registered into JEDEC publications.
The tolerance of position that controls the location of the pattern of balls with respect to
datum A and B. For each ball there is a cylindrical tolerance zone eee perpendicular to
datum C and located on true position with respect to datum A and B as defined by e. The
axis perpendicular to datum C of each ball must lie within this tolerance zone.
5
6
The tolerance of position that controls the location of the balls within the matrix with respect
to each other. For each ball there is a cylindrical tolerance zone fff perpendicular to datum C
and located on true position as defined by e. The axis perpendicular to datum C of each ball
must lie within this tolerance zone. Each tolerance zone fff in the array is contained entirely
in the respective zone eee above.
The axis of each ball must lie simultaneously in both tolerance zones.
The terminal A1 corner must be identified on the top surface by using a corner chamfer, ink
or metallized markings, or other feature of package body or integral heatslug. A
distinguishing feature is allowable on the bottom surface of the package to identify the
terminal A1 corner. Exact shape of each corner is optional.
80/85
STw5098
Package mechanical data
Figure 33. VFBGA 5x5x1.0 112 0.4 drawing
81/85
Application schematics
STw5098
19
Application schematics
See Figure 34: STw5098 application schematics.
82/85
STw5098
Application schematics
Figure 34. STw5098 application schematics
83/85
Ordering information
STw5098
20
Ordering information
Table 59. Order codes
Part Number
Package
Packing
STw5098
LFBGA 6x6x1.4, 0.5 mm pitch, 112 pins
LFBGA 6x6x1.4, 0.5 mm pitch, 112 pins
VFBGA 5x5x1.0, 0.4 mm pitch, 112 pins
VFBGA 5x5x1.0, 0.4 mm pitch, 112 pins
Tray
STw5098T
Tape and reel
Tray
STw5098BBLR/LF
STw5098BBLT/LF
Tape and reel
21
Revision history
Table 60. Document revision history
Date
Revision
Changes
24-Apr-2007
1
Initial release.
84/85
STw5098
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85/85
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