TDA7330BD [STMICROELECTRONICS]

SINGLE CHIP RDS DEMODULATOR FILTER; 单芯片RDS解调滤波器


型号：	TDA7330BD
厂家：	ST
描述：	SINGLE CHIP RDS DEMODULATOR FILTER 单芯片RDS解调滤波器 LTE
文件：	总9页 (文件大小：117K)
中文：	中文翻译
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TDA7330B

SINGLE CHIP RDS DEMODULATOR + FILTER

HIGH PERFORMANCE, 57KHz BANDPASS

FILTER (8th ORDER)

FILTER ADJUSTMENT FREE AND WITHOUT

EXTERNAL COMPONENTS

PURELY DIGITAL RDS DEMODULATION

WITHOUT EXTERNAL COMPONENTS

ARI (SK INDICATION) AND RDS SIGNAL

QUALITY OUTPUT

4.332MHz CRYSTAL OSCILLATOR

(8.664MHz OPTIONAL)

LOW NOISE MIXED BIPOLAR/CMOS TECH-

NOLOGY

DIP20

SO20

ORDERING NUMBERS:

DESCRIPTION

TDA7330B

TDA7330BD

The TDA7330B is a RDS demodulator. It recov-

ers the additional inaudible RDS information

which is transmitted by FM radio broadcasting

stations.

The output data signal (RDDA) and clock signal

(RDCL) can be further processed by a suitable

RDS decoder (microprocessor).

The device operates in accordance with the EBU

(European BroadcastingUnion) specifications.

The IC includes a 2nd order antialiasing input fil-

ter, a 57KHz switched capacitor band pass filter,

a smoothing filter and cross detector, a bit rate

clock recovery circuit, a 57KHz PLL, BI-PHASE

PSK decoder, differential decoding circuit, ARI in-

dication and RDS signal quality output.

BLOCK DIAGRAM

November 1999

1/9

TDA7330B

ABSOLUTE MAXIMUM RATINGS

Symbol

Parameter

Value

Unit

V_CC

T_op

Supply Voltage

Operating Temperature Range

Storage Temperature

-40 to 85

-40 to 150

T_stg

°C

THERMAL DATA

Symbol

Description

DIP20

100

SO20

Unit

R_{th j-case}

Thermal Resistance Junction-case

Typ.

200

°C/W

PIN CONNECTION (Top view)

PIN FUNCTION

Nr.

Name

Description

MUXIN

V_ref

COMP

FIL OUT

GND

RDS input signal.

Reference voltage

Not inverting comparator input (smoothing filter)

Filter Output

Ground

Testing output pin (not to be used)

Oscillator output

OSC OUT

OSC IN

T57

RDCL

RDDA

QUAL

ARI

Oscillator Input

Testing output pin: 57KHz clock output

RDS clock output (1187.5Hz)

RDS data output

Output for signal quality indication (High = good)

Output for ARI indication (High when RDS + ARI signals are present)

(High when only ARI is present)

(Low when only RDS is present)

(indefined when no signal is present)

Supply Voltage

Testing output pin (not to be used)

Frequency selector pin: open = 4.332MHz, closed to V_CC= 8.664MHz

Test mode pin (open = normal RUN)

(closed to V_CC= Test mode)

V_CC

FSEL

POR

Reset Input for testing (active high)

2/9

TDA7330B

ELECTRICAL CHARACTERISTICS (V_CC= 5V, Tamb = 25°C; Rg = 600Ω; fosc = 4.332MHz;

_IN= 20mVrmsunless otherwise specified)

Symbol

Parameter

Test Condition

Min.

Typ.

Max.

Unit

SUPPLY

V_CC

I_S

Supply Voltage

4.5

5.5

KΩ

Supply Current

R_POR

POR_ON

POR Pull Down Resistor

POR Threshold

pin 20

2.5

FILTER(measured an pin 4 FILOUT)

F_C

Center Frequency

3dB Bandwidth

Gain

56.5

2.5

57.5

3.5

KHz

f = 57KHz

Attenuation

∆f = +4KHz

f = 38KHz; V_i= 500mVrms

f = 67KHz; V_i= 250mVrms

∆

Phase non linearity

A (see note1)

B (see note1)

C (see note1)

0.5

7.5

DEG

R_i

S/N

V_i

Input Impedance

100

160

200

KΩ

Signal to Noise Ratio

V_i= 3mVrms

Maximum Input Signal Capability f = 19KHz; T3 < –40dB (see note2)

f = 57KHz (RDS + ARI)

Vrms

mVrms

R_L

Load Impedance

Pin 4

100

KΩ

CROSS DETECTOR

Resistance pin 3-4

KΩ

OSCILLATOR

F_OSC

Oscillator Frequency

F_SEL= Open (*)

4.332

8.664

MHz

F_SEL= Closed to V_CC(**)

VCLL

VCLH

Clock Input level LOW (pin 10)

Clock Input Level HIGH (pin 10)

Output Amplitude (pin 9)

4.5

V_PP

(*) FSEL pin has an internal 40KΩ pull down resistor A 4.332MHz QUARTZ must be used (**) A 8.664MHz QUARTZ must be used.

DEMODULATOR

Max Oscillator Deviation

RDS Detection Sensitivity

ARI Detection Sensitivity

RDS Lockup Time

F_SEL= Open

+ 1.2

100

KHz

mVrms

∆

S_RDS

S_ARI

T_lock

V_OH

V_OL

f_RDS

t_D

Output HIGH Voltage

Output LOW Voltage

I_L= 0.5mA; pins 12, 13, 14, 15

RDCL pin

Data Rate for RDS

1187.5

4.3

RDDA Transition versus RDCL

(see figure 2)

µsec

Note(1):

The phase non linearity is defined as: ∆Ph = | -2 φf2 + φf1 + φf3 |

where φfx is the input-output phase difference at the frequency fx (x = 1,2,3)

3/9

TDA7330B

ELECTRICAL CHARACTERISTICS

(continued)

Measure f1 (KHz) f2 (KHz) f3 (KHz) ∆Ph max

56.5

57.5

<7.5°

<10°

55.5

58.5

Note(2):

The 3th harmonic (57KHz) must be less than -40dB in respect to the input signal 19KHz plus gain.

Figure 2:

RDS timing diagram

data change can results on the falling or on the

rising clock edge.

OUTPUT TIMING

The generated 1187.5Hz output clock (RDCL

line) is synchronized to the incoming data.

According to the internal PLL lock condition this

Whichever clock edge is used by the decoder (ris-

ing or falling edge) the data will remain valid for

416.7 sec after the clock transition.

Figure 3:

Test Circuit

4/9

TDA7330B

APPLICATION SUGGESTION

The Layout path pin2 - C2 - pin5 must be as

short as possible.

If the supply line, after the power on has a soft

and disturbed (spikes) slope, a capacitor of

100nF, between POR and V_CC, is racom-

mended.

A good DC decoupling between V_CCand

GROUND is necessary: a 100nF ceramic ca-

pacitor, with low resistance and low inductance

at high frequency,directly connected on pin 16

(V_CC)and 5 (GND) is recommended.

A small series inductance (100 H) or resistor

(27Ω) may be used for supply line filtering.

The various testing pins have no sense for the

customer.

Figure 4: P.C. board and component layout of fig. 3 (1:1 scale)

5/9

TDA7330B

Figure 5: Gain vs. Frequency

Figure 6: Group Delay vs. Frequency

6/9

TDA7330B

inch

OUTLINE AND

MECHANICAL DATA

DIM.

MIN. TYP. MAX. MIN. TYP. MAX.

0.254

1.39

0.010

1.65 0.055

0.065

1.000

0.45

0.25

0.018

0.010

25.4

8.5

0.335

0.100

0.900

2.54

22.86

7.1

0.280

0.155

3.93

3.3

0.130

DIP20

1.34

0.053

7/9

TDA7330B

inch

OUTLINE AND

MECHANICAL DATA

DIM.

MIN. TYP. MAX. MIN. TYP. MAX.

2.35

0.1

2.65 0.093

0.3 0.004

0.104

0.012

0.020

0.013

0.512

0.299

0.33

0.23

12.6

7.4

0.51 0.013

0.32 0.009

0.496

0.291

7.6

1.27

0.050

0.25

0.4

10.65 0.394

0.75 0.010

0.419

0.030

0.050

1.27 0.016

SO20

0° (min.)8° (max.)

h x 45°

SO20MEC

8/9

TDA7330B

Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences

of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is

granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are

subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products

are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.

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9/9

TDA7330BD [STMICROELECTRONICS]

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