TDA7442D
更新时间：2024-09-18 02:24:53
描述：TONE CONTROL AND SURROUND DIGITALLY CONTROLLED AUDIO PROCESSOR
概述
规格参数
数据手册
替代型号TDA7442D 概述
TONE CONTROL AND SURROUND DIGITALLY CONTROLLED AUDIO PROCESSOR 音调控制和环绕声数字控制音频处理器 音频控制集成电路
TDA7442D 规格参数
| 是否无铅： | 不含铅 | 是否Rohs认证： | 符合 |
| 生命周期： | Active | 零件包装代码： | SOIC |
| 包装说明： | SOP, SOP28,.4 | 针数： | 28 |
| Reach Compliance Code： | compliant | ECCN代码： | EAR99 |
| HTS代码： | 8542.39.00.01 | 风险等级： | 5.19 |
| 信道分离： | 90 dB | 商用集成电路类型： | TONE CONTROL CIRCUIT |
| 谐波失真： | 0.01% | JESD-30 代码： | R-PDSO-G28 |
| JESD-609代码： | e4 | 长度： | 17.9 mm |
| 频带数量： | 2 | 信道数量： | 2 |
| 功能数量： | 1 | 端子数量： | 28 |
| 最高工作温度： | 70 °C | 最低工作温度： | -10 °C |
| 封装主体材料： | PLASTIC/EPOXY | 封装代码： | SOP |
| 封装等效代码： | SOP28,.4 | 封装形状： | RECTANGULAR |
| 封装形式： | SMALL OUTLINE | 峰值回流温度（摄氏度）： | NOT SPECIFIED |
| 电源： | 9 V | 认证状态： | Not Qualified |
| 座面最大高度： | 2.65 mm | 子类别： | Other Consumer ICs |
| 最大压摆率： | 26 mA | 最大供电电压 (Vsup)： | 10.2 V |
| 最小供电电压 (Vsup)： | 7 V | 表面贴装： | YES |
| 技术： | BICMOS | 温度等级： | COMMERCIAL |
| 端子面层： | Nickel/Palladium/Gold (Ni/Pd/Au) | 端子形式： | GULL WING |
| 端子节距： | 1.27 mm | 端子位置： | DUAL |
| 处于峰值回流温度下的最长时间： | NOT SPECIFIED | 宽度： | 7.5 mm |
| Base Number Matches： | 1 |
TDA7442D 数据手册
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PDF下载TDA7442
TDA7442D
TONE CONTROL AND SURROUND
DIGITALLY CONTROLLED AUDIO PROCESSOR
1 FEATURES
■ 4 STEREO INPUTS
Figure 1. Packages
■ INPUT ATTENUATION CONTROL IN 0.5dB
STEP
■ TREBLE AND BASS CONTROL
■ TWO SURROUND MODE AVAILABLE WITH 4
SELECTABLE RESPONSES:
SO-28
SDIP-32
Table 1. Order Codes
– MUSIC
– SIMULATED STEREO
Part Number
TDA7442
Package
SDIP-32
■ TWO SPEAKER ATTENUATORS:
– 2 INDEPENDENT SPEAKER CONTROLS IN
1dB STEPS FOR BALANCE FACILITY
– INDEPENDENT MUTE FUNCTION
■ ALL FUNCTIONS PROGRAMMABLE VIA
SERIAL BUS
TDA7442D
SO-28
TDA7442D013TR
Tape & Reel
mable phase shifter. Control of all the functions is
accomplished by serial bus.
■ 2 MONITOR OUTPUT (ONLY FOR TDA7442)
The AC signal setting is obtained by resistor net-
works and switches combined with operational
amplifiers.
2 DESCRIPTION
The TDA7442/42D is volume tone (bass and tre-
ble) balance (Left/Right) processors for quality au-
dio applications in TV and Hi-Fi systems.
Thanks to the BIPOLAR/CMOS Technology used,
Low Distortion, Low Noise and DC stepping are
obtained.
It reproduces surround sound by using a program-
Figure 2. Pin Connections (Top views)
R-IN2
R-IN1
1
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
R-IN3
R-IN4
L-OUT
R-OUT
AGND
VS
2
R_IN3
R_IN2
1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
R_IN4
LOUT
ROUT
AGND
VS
MONITOR(L)
MONITOR(R)
L-IN1
3
2
4
R_IN1
3
5
L_IN1
4
L-IN2
6
L_IN2
5
L-IN3
7
CREF
SDA
L_IN3
6
CREF
SDA
L-IN4
8
L_IN4
7
SDIP32
SO28
MUXOUT(L)
IN(L)
9
SCL
MUXOUTL
IN(L)
8
SCL
10
11
12
13
14
15
16
DIGGND
TREBLE-R
N.C.
9
DIG-GND
TREBLE(R)
TREBLE(L)
PS1
MUXOUT(R)
N.C.
MUXOUT(R)
IN(R)
10
11
12
13
14
IN(R)
TREBLE-L
PS1
BIN(R)
BIN(R)
BOUT(R)
BIN(L)
LP
BOUT(R)
BIN(L)
LP
BOUT(L)
BOUT(L)
D98AU948
D01AU1247
REV. 2
1/17
June 2004
TDA7442 - TDA7442D
Figure 3. Block Diagram (TDA7442)
5.6K
5.6nF
100nF
100nF
100nF
2.2µF
MONITOR(L)
3
MUXOUT(L)
PS1
19
TREBLE-L
20
BIN(L) BOUT(L)
17
0.47µF
L-IN1
0.47µF
L-IN2
0.47µF
L-IN3
0.47µF
L-IN4
31.5dB
control
9
10
16
5
6
7
8
RB
RPS1
FIX
50K
50K
50K
50K
30K
PS1
90Hz
OFF
79dB CONTROL
SPKR
ATT
-
VAR
FIX
SURR
30
+
MUSIC/
SYMULATED
LOUT
-
SYMULATED
MUTE
+
+
L+R
MIXING
AMP
MUSIC
TREBLE
BASS
OFF
-
L-R
24
25
23
+
SCL
SDA
2
0.47µF
R-IN1
0.47µF
R-IN2
0.47µF
R-IN3
0.47µF
R-IN4
I
C BUS DECODER + LATCHES
2
DIG GND
50K
50K
50K
50K
1
TREBLE
BASS
LPF
9KHz
EFFECT
CONTROL
MIXING
AMP
FIX
SPKR
ATT
SURR
+
-
VAR
29
32
31
ROUT
30K
OFF
MUTE
79dB CONTROL
31.5dB
control
Vref
SUPPLY
RB
4
11
13
18
LP
27
28
26
22
14
BIN(R)
13
MONITOR(R) MUXOUT(R)
V
CREF
TREBLE-R
BOUT(R)
D98AU947B
S
1.2nF
22µF
2.2µF
100nF
100nF
5.6nF
5.6K
Figure 4. Block Diagram (TDA7442D)
5.6K
5.6nF
100nF
100nF
100nF
2.2µF
MUXOUT(L)
PS1
TREBLE-L
18
BIN(L)
15
BOUT(L)
0.47µF
L-IN1
0.47µF
L-IN2
0.47µF
L-IN3
0.47µF
L-IN4
31.5dB
control
8
9
17
14
4
5
6
7
RB
RPS1
FIX
50K
50K
50K
50K
30K
PS1
90Hz
OFF
79dB CONTROL
SPKR
ATT
-
VAR
FIX
SURR
27
+
MUSIC/
SYMULATED
LOUT
-
SYMULATED
MUTE
+
+
L+R
MIXING
AMP
MUSIC
TREBLE
BASS
OFF
-
L-R
21
22
20
+
SCL
SDA
2
0.47µF
R-IN1
0.47µF
R-IN2
0.47µF
R-IN3
0.47µF
R-IN4
I
C BUS DECODER + LATCHES
3
DIG GND
50K
50K
50K
50K
2
TREBLE
BASS
LPF
9KHz
EFFECT
CONTROL
MIXING
AMP
FIX
SPKR
ATT
SURR
+
-
VAR
26
1
ROUT
30K
OFF
MUTE
28
79dB CONTROL
31.5dB
control
Vref
SUPPLY
RB
10
11
16
LP
24
25
23
19
12
BIN(R)
13
MUXOUT(R)
V
CREF
TREBLE-R
BOUT(R)
D01AU1248
S
1.2nF
22µF
2.2µF
100nF
5.6K
100nF
5.6nF
2/17
TDA7442 - TDA7442D
Table 2. Quick Reference Data
Symbol
Parameter
Min.
Typ.
Max.
Unit
V
V
S
Supply Voltage
7
2
9
10.2
V
Max. input signal handling
Vrms
%
CL
THD
S/N
Total Harmonic Distortion V = 1Vrms f = 1KHz
0.01
106
90
0.1
Signal to Noise Ratio V = 1Vrms (mode = OFF)
dB
dB
dB
dB
dB
out
S
C
Channel Separation f = 1KHz
Treble Control (2db step)
Bass Control (2dB step)
-14
-14
-79
+14
+14
0
Balance Control 1dB step (L , R
)
CH
CH
Mute Attenuation
100
dB
Table 3. Thermal Data
Symbol
Parameter
Value
Unit
R
Thermal Resistance Junction-pins
Max.
85
°C/W
th j-pins
Table 4. Absolute Maximum Ratings
Symbol
Parameter
Value
11
Unit
V
V
S
Operating Supply Voltage
T
Operating Ambient Temperature
Storage Temperature Range
-10 to 70
°C
°C
amb
T
-55 to +150
stg
Table 5. Electrical Characteristics
Refer to the test circuit T = 25°C, V = 9V, R = 10KΩ, V = 1Vrms; R = 600Ω, all controls flat (G =
amb
S
L
in
G
0dB), Effect Ctrl = -6dB, MODE = OFF; f = 1KHz unless otherwise specified.
Symbol
SUPPLY
Parameter
Test Condition
Min.
Typ.
Max.
Unit
V
Supply Voltage
7
9
10.2
26
V
S
I
S
Supply Current
Ripple Rejection
10
60
18
80
mA
dB
SVR
INPUT STAGE
L
CH
/ RCH out, Mode = OFF
R
Input Resistance
Clipping Level
35
2
50
2.5
31.5
0
65
KΩ
Vrms
dB
IN
V
CL
THD = 0.3%
C
Control Range
Min. Attenuation
Max. Attenuation
Step Resolution
RANGE
AV
-1
1
32
1
dB
MIN
A
VMAX
31
31.5
0.5
dB
A
STEP
dB
BASS CONTROL
G
Control Range
Max. Boost/cut
±11.5
1
±14.0
2
±16.0
3
dB
dB
KΩ
b
B
Step Resolution
STEP
R
Internal Feedback Resistance
32
44
56
B
3/17
TDA7442 - TDA7442D
Table 5. Electrical Characteristics (continued)
Refer to the test circuit T
= 25°C, V = 9V, R = 10KΩ, V = 1Vrms; R = 600Ω, all controls flat (G =
S L in G
amb
0dB), Effect Ctrl = -6dB, MODE = OFF; f = 1KHz unless otherwise specified.
Symbol
Parameter
Test Condition
Min.
Typ.
Max.
Unit
TREBLE CONTROL
G
Control Range
Step Resolution
EFFECT CONTROL
Max. Boost/cut
+13.0
1
+14.0
2
+15.0
3
dB
dB
t
T
STEP
C
Control Range
Step Resolution
- 21
0.5
- 6
dB
dB
RANGE
S
1
1.5
STEP
SURROUND SOUND MATRIX PHASE
R
R
R
R
Phase Shifter 1: D1 = 0, D0 = 0
Phase Shifter 1: D1 = 0, D0 = 1
Phase Shifter 1: D1 = 1, D0 = 0
Phase Shifter 1: D1 = 1, D0 = 1
8.3
10
11.8
14.1
17.9
37.3
15.2
18.3
KΩ
KΩ
KΩ
KΩ
PS10
PS11
PS12
PS13
12.6
26.4
23.3
48.85
SURROUND SOUND MATRIX
TEST CONDITION (Phase Resistor Selection D0=0, D1=1, D2=0. D3=1, D4=0, D5=1, D6=0, D7=1
G
In-phase Gain (OFF)
Mode OFF, Input signal of
-1
0
1
1
dB
OFF
1kHz, 1.4 V , R → R
L
→
p-p
in
out in
L
out
D
LR In-phase Gain Difference
(OFF)
Mode OFF, Input signal of 1kHz,
1.4 V → R , L → L
-1
0
7
dB
dB
GOFF
R
p-p in
out in
out
G
MUS
In-phase Gain (Music)
Music mode, Effect Ctrl = -6dB
Input signal of 1kHz, 1.4 V (R
p-p
in
in
→ R ), (L → L )
out
out
in
D
LR In-phase Gain Difference
(Music)
Music mode, Effect Ctrl = -6dB
Input signal of 1kHz, 1.4 V (R
0
dB
GMUS
p-p
→ R ) - (L → L )
out
out
in
SPEAKER ATTENUATORS
C
Control Range
79
1
dB
dB
dB
dB
mV
dB
KΩ
range
S
STEP
Step Resolution
Attenuation set error
-0.5
-1.5
-3
1.5
1.5
2
E
A
Av = 0 to -20dB
0
Av = -20 to -79dB
0
V
DC Steps
adjacent att. steps
-3
0
3
DC
A
MUTE
Output Mute Condition
Input Impedance
+70
21
100
30
R
39
VEA
AUDIO OUTPUTS
N
Output Noise (OFF)
Output Mute, Flat
4
5
µVrms
µVrms
O(OFF)
B
W
= 20Hz to 20KHz
N
Output Noise (Music)
Mode = Music ,
= 20Hz to 20KHz,
30
mVrms
O(MUS)
B
W
N
Output Noise (Pseudo Stereo) Mode = Pseudo Stereo
= 20Hz to 20KHz,
30
mVrms
O(PSEUDO)
B
W
d
Distorsion
Av = 0 ; V = 1Vrms
0.01
90
0.1
50
%
dB
in
S
C
Channel Separation
Clipping Level
70
2
V
d = 0.3%
2.5
30
Vrms
Ω
OCL
OUT
R
Output Resistance
10
4/17
TDA7442 - TDA7442D
Table 5. Electrical Characteristics (continued)
Refer to the test circuit T = 25°C, V = 9V, R = 10KΩ, V = 1Vrms; R = 600Ω, all controls flat (G =
amb
S
L
in
G
0dB), Effect Ctrl = -6dB, MODE = OFF; f = 1KHz unless otherwise specified.
Symbol
Parameter
DC Voltage Level
MONITOR OUTPUTS
Distorsion
Test Condition
Min.
Typ.
Max.
Unit
V
OUT
3.8
V
d
Av = 0 ; V = 1Vrms
0.01
90
0.1
%
dB
Vrms
Ω
in
S
C
Channel Separation
Clipping Level
70
2
V
OCL
R
OUT
V
OUT
d = 0.3%
2.5
50
Output Resistance
DC Voltage Level
20
70
1
4.5
V
BUS INPUTS
V
Input Low Voltage
Input High Voltage
Input Current
V
V
IL
IH
IN
V
3
I
-5
+5
µA
V
V
O
Output Voltage SDA
Acknowledge
I
O
= 1.6mA
0.4
5/17
TDA7442 - TDA7442D
3 I2C BUS INTERFACE
Data transmission from microprocessor to the TDA7442D and vice versa takes place through the 2 wires
2
I C BUS interface, consisting of the two lines SDA and SCL (pull-up resistors to positive supply voltage
must be connected).
3.1 Data Validity
As shown in fig. 5, the data on the SDA line must be stable during the high period of the clock. The HIGH
and LOW state of the data line can only change when the clock signal on the SCL line is LOW.
3.2 Start and Stop Conditions
As shown in fig. 6 a start condition is a HIGH to LOW transition of the SDA line while SCL is HIGH. The
stop condition is a LOW to HIGH transition of the SDA line while SCL is HIGH.
3.3 Byte Format
Every byte transferred on the SDA line must contain 8 bits. Each byte must be followed by an acknowledge
bit. The MSB is transferred first.
3.4 Acknowledge
The master (µP) puts a restive HIGH level on the SDA line during the acknowledge clock pulse (see fig.
3). The peripheral (audio processor) that acknowledges has to pull-down (LOW) the SDA line during this
clock pulse.
The audio processor which has been addressed has to generate an acknowledge after the reception of
each byte, otherwise the SDA line remains at the HIGH level during the ninth clock pulse time. In this case
the master transmitter can generate the STOP information in order to abort the transfer.
3.5 Transmission without Acknowledge
Avoiding to detect the acknowledge of the audio processor, the µP can use a simpler transmission: simply
it waits one clock without checking the slave acknowledging, and sends the new data.
This approach of course is less protected from misworking.
2
Figure 5. Data Validity on the I CBUS
SDA
SCL
DATA LINE
STABLE, DATA
VALID
CHANGE
DATA
ALLOWED
D99AU1031
2
Figure 6. Timing Diagram of I CBUS
SCL
I2CBUS
SDA
D99AU1032
START
STOP
2
Figure 7. Acknowledge on the I CBUS
SCL
1
2
3
7
8
9
SDA
MSB
ACKNOWLEDGMENT
FROM RECEIVER
START
D99AU1033
6/17
TDA7442 - TDA7442D
4 SOFTWARE SPECIFICATION
Interface Protocol
The interface protocol comprises:
■ A start condition (S)
■ A chip address byte, containing the TDA7442D
■ A subaddress bytes
■ A sequence of data (N byte + acknowledge)
■ A stop condition (P)
CHIP ADDRESS
SUBADDRESS
DATA 1 to DATA n
MSB
1
LSB
0
MSB
B
LSB
MSB
LSB
S
0
0
0
0
0
A
ACK
DATA
ACK
DATA
ACK
P
D95AU226A
ACK = Acknowledge
S = Start
P = Stop
A = Address
B = Auto Increment
4.1 EXAMPLES
4.1.1 No Incremental Bus
The TDA7442D receives a start condition, the correct chip address, a subaddress with the MSB = 0 (no
incremental bus), N-datas (all these data concern the subaddress selected), a stop condition.
CHIP ADDRESS
SUBADDRESS
DATA
MSB
1
LSB
0
MSB
0
LSB
D3 D2 D1 D0 ACK
MSB
LSB
S
0
0
0
0
0
A
ACK
X
X
X
DATA
ACK
P
D95AU306
4.1.2 Incremental Bus
The TDA7442D receive a start conditions, the correct chip address, a subaddress with the MSB = 1 (in-
cremental bus): now it is in a loop condition with an autoincrease of the subaddress whereas SUBAD-
DRESS from "1XXX1010" to "1XXX1111" of DATA are ignored.
The DATA 1 concern the subaddress sent, and the DATA 2 concerns the subaddress sent plus one sent
in the loop etc, and at the end it receivers the stop condition.
CHIP ADDRESS
SUBADDRESS
DATA 1 to DATA n
MSB
1
LSB
0
MSB
1
LSB
D3 D2 D1 D0 ACK
MSB
LSB
S
0
0
0
0
0
A
ACK
X
X
X
DATA
ACK
P
D95AU307
7/17
TDA7442 - TDA7442D
5 DATA BYTES
Address = 80(HEX)
5.1 Function Selection:
The first byte (subaddress)
MSB
LSB
D0
0
SUBADDRESS
D7
B
D6
X
D5
X
D4
X
D3
0
D2
0
D1
0
INPUT ATTENUATION
B
X
X
X
0
0
0
1
SURROUND & OUT & EFFECT
CONTROL
B
B
B
B
B
B
B
B
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
0
0
0
0
0
1
1
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
0
1
PHASE RESISTOR
BASS
TREBLE
SPEAKER ATTENUATION "L"
SPEAKER ATTENUATION "R"
NOT ALLOWED
NOT ALLOWED
INPUT MULTIPLEXER
B = 1 incremental bus; active
B = 0 no incremental bus;
X = indifferent 0,1
Input Attenuation Selection
MSB
LSB
D0
0
INPUT ATTENUATION
D7
D6
1
D5
D4
D3
D2
0
D1
0
0.5 dB STEPS
0
1
0
0
1
-0.5
1
0
1
0
-1
1
0
1
1
-1.5
1
1
0
0
-2
1
1
0
1
-2.5
1
1
1
0
-3
1
1
1
1
-3.5
4 dB STEPS
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
-4
-8
-12
-16
-20
-24
-28
INPUT ATTENUATION = 0 ~ -31.5dB
8/17
TDA7442 - TDA7442D
5.2 Surround Selection
MSB
LSB
D0
0
D7
D6
D5
D4
D3
D2
D1
0
SURROUND MODE
SIMULATED STEREO
0
1
MUSIC
1
0
OFF
OUT
0
1
VAR
FIX
EFFECT CONTROL
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
-6
-7
-8
-9
-10
-11
-12
-13
-14
-15
-16
-17
-18
-19
-20
-21
PHASE RESISTOR SELECTION
MSB
LSB
D0
0
SURROUND PHASE RESISTOR
D7
D6
D5
D4
D3
D2
D1
0
PHASE SHIFT 1 (KΩ)
12
14
18
37
0
1
1
0
1
1
BASS SELECTION
MSB
LSB
D0
0
BASS
D7
X
X
X
X
X
X
X
X
X
D6
X
X
X
X
X
X
X
X
X
D5
X
X
X
X
X
X
X
X
X
D4
1
D3
0
D2
0
D1
0
2 dB STEPS
-14
-12
-10
-8
1
0
0
0
1
1
0
0
1
0
1
0
0
1
1
1
0
1
0
0
-6
1
0
1
0
1
-4
1
0
1
1
0
-2
1
0
1
1
1
0
1
1
1
1
1
0
9/17
TDA7442 - TDA7442D
5.2 Surround Selection (continued)
MSB
LSB
D0
0
BASS
D7
X
D6
X
D5
X
D4
1
D3
1
D2
1
D1
1
2 dB STEPS
2
4
X
X
X
1
1
1
0
1
X
X
X
1
1
1
0
0
6
X
X
X
1
1
0
1
1
8
X
X
X
1
1
0
1
0
10
12
14
X
X
X
1
1
0
0
1
X
X
X
1
1
0
0
0
SPEAKER SELECTION
MSB
LSB
D0
0
SPEAKER/ATT
D7
X
D6
D5
D4
D3
D2
0
D1
0
1 dB STEPS
0
X
0
0
1
-1
X
0
1
0
-2
X
0
1
1
-3
X
1
0
0
-4
X
1
0
1
-5
X
1
1
0
-6
X
1
1
1
-7
8 dB STEPS
X
X
X
X
X
X
X
X
X
X
0
0
0
0
0
0
0
0
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
0
1
0
1
0
-8
-16
-24
-32
-40
-48
-56
-64
-72
MUTE
X
X
1
1
0
1
1
X
X
X
X = INDIFFERENT 0,1
SPEAKER ATTENUATION = 0dB ~ -79dB
TREBLE SELECTION
MSB
LSB
D0
0
TREBLE
D7
0
D6
0
D5
0
D4
0
D3
1
D2
1
D1
1
2 dB STEPS
-14
-12
-10
-8
0
0
0
1
1
1
1
0
0
0
1
0
1
1
1
0
0
0
1
1
1
1
1
0
0
1
0
0
1
1
1
0
-6
0
1
0
1
1
1
1
0
-4
10/17
TDA7442 - TDA7442D
5.2 Surround Selection (continued)
MSB
LSB
D0
0
TREBLE
D7
0
D6
1
D5
1
D4
0
D3
1
D2
1
D1
1
2 dB STEPS
-2
0
0
1
1
1
1
1
1
0
1
1
1
1
1
1
1
0
0
1
1
1
0
1
1
1
0
2
1
1
0
1
1
1
1
0
4
1
1
0
0
1
1
1
0
6
1
0
1
1
1
1
1
0
8
1
0
1
0
1
1
1
0
10
12
14
1
0
0
1
1
1
1
0
1
0
0
0
1
1
1
0
INPUT SELECTION
MSB
LSB
D0
0
D7
X
D6
D5
D4
D3
D2
0
D1
0
INPUT MULTIPLEXER
IN2
IN3
IN4
IN1
X
0
1
0
X
1
0
0
X
1
1
0
X = INDIFFERENT 0,1
SPEAKER ATTENUATION = 0dB ~ -79dB
TREBLE SELECTION
MSB
LSB
D0
0
TREBLE
D7
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
D6
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
D5
0
0
1
1
0
0
1
1
1
1
0
0
1
1
0
0
D4
0
1
0
1
0
1
0
1
1
0
1
0
1
0
1
0
D3
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
D2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
D1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2 dB STEPS
-14
-12
-10
-8
-6
-4
-2
0
0
0
0
0
0
0
0
0
0
0
2
0
4
0
6
0
8
0
10
12
14
0
0
INPUT SELECTION
MSB
LSB
D0
0
D7
X
D6
D5
D4
D3
D2
0
D1
0
INPUT MULTIPLEXER
IN2
IN3
IN4
IN1
X
0
1
0
X
1
0
0
X
1
1
0
11/17
TDA7442 - TDA7442D
Table 6.
POWER ON RESET
BASS
2dB
TREBLE
0dB
SURROUND & OUT CONTROL+ EFFECT CONTROL
SPEAKER ATTENUATION L &R
INPUT ATTENUATION
OFF + FIX + MAX ATTENUATION
MUTE
MAX ATTENUATION
IN1
INPUT
Figure 8. PIN: TREBLE-L, TREBLE-R
Figure 11. PIN: CREF
VS
VS
20µA
20µA
20K
42K
20K
GND
25K
D95AU336
GND
Figure 12. PIN: SCL, SDA
D95AU309
20µA
Figure 9. PIN: VOUT REF
VS
20µA
GND
D94AU205
Figure 13. PIN: LP
VS
GND
20µA
D95AU233A
10K
GND
Figure 10. PIN: L-IN, R-IN, L-IN2, R-IN2, L-IN3,
R-IN3,L-IN4, R-IN4,
GND
D95AU308
Figure 14. PIN: L-OUT, R-OUT
VS
VS
20µA
20µA
50K
GND
VREF
D94AU200
GND
D95AU230
12/17
TDA7442 - TDA7442D
Figure 15. PIN: BASS-LI, BASS-RI
Figure 16. PIN: BASS-LO, BASS-RO
VS
VS
20µA
20µA
45K
45K : Bass
GND
GND
BASS-LO
BASS-RO
BASS-LI,BASS-RI
D98AU950
D98AU949
13/17
TDA7442 - TDA7442D
Figure 17. SO-28 Mechanical Data & Package Dimensions
mm
inch
DIM.
OUTLINE AND
MECHANICAL DATA
MIN. TYP. MAX. MIN. TYP. MAX.
A
a1
b
2.65
0.3
0.104
0.012
0.019
0.013
0.1
0.004
0.35
0.23
0.49 0.014
0.32 0.009
b1
C
0.5
0.020
c1
D
45° (typ.)
17.7
10
18.1 0.697
10.65 0.394
0.713
0.419
E
e
1.27
0.050
0.65
e3
F
16.51
7.4
0.4
7.6
0.291
0.299
0.050
L
1.27 0.016
SO-28
S
8 ° (max.)
14/17
TDA7442 - TDA7442D
Figure 18. SDIP-32 Mechanical Data & Package Dimensions
mm
inch
OUTLINE AND
MECHANICAL DATA
DIM.
MIN. TYP. MAX. MIN.
TYP. MAX.
A
A1
A2
B
3.556 3.759 5.080 0.14 0.147
0.508 0.020
3.048 3.556 4.572 0.12
0.2
0.14
0.18
0.356 0.457 0.584 0.014 0.018 0.023
0.762 1.016 1.397 0.03 0.04 0.055
0.203 0.254 0.356 0.008 0.01 0.014
27.43 27.94 28.45 1.08 1.1 1.12
9.906 10.41 11.05 0.39 0.409 0.433
B1
C
D
E
E1
e
7.620 8.890 9.398
0.3
0.35
0.070
0.400
0.37
1.778
10.16
eA
eB
L
SDIP-32
(Shrink Plastic Dip 32L)
12.70
0.500
0.15
2.540 3.048 3.810
0.1
0.12
E
E1
A2
A
L
A1
B
B1
e
eA
eB
D
C
32
17
16
1
SDIP32M
0123183
15/17
TDA7442 - TDA7442D
Table 7. Revision History
Date
Revision
Description of Changes
January 2001
June 2004
1
2
First issue.
Changed the Style-sheet in compliance to the new “Corporate Technical
Pubblications Design Guide”
16/17
TDA7442 - TDA7442D
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
The ST logo is a registered trademark of STMicroelectronics.
All other names are the property of their respective owners
© 2004 STMicroelectronics - All rights reserved
STMicroelectronics GROUP OF COMPANIES
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www.st.com
17/17
TDA7442D 替代型号
| 型号 | 制造商 | 描述 | 替代类型 | 文档 |
| TDA7442D013TR | STMICROELECTRONICS | TONE CONTROL AND SURROUND DIGITALLY CONTROLLED AUDIO PROCESSOR | 完全替代 |
|
TDA7442D 相关器件
| 型号 | 制造商 | 描述 | 价格 | 文档 |
| TDA7442D013TR | STMICROELECTRONICS | TONE CONTROL AND SURROUND DIGITALLY CONTROLLED AUDIO PROCESSOR | 获取价格 |
|
| TDA7443D | STMICROELECTRONICS | TONE CONTROL AND SURROUND DIGITALLY CONTROLLED AUDIO PROCESSOR WITH AGC | 获取价格 |
|
| TDA7444 | STMICROELECTRONICS | SPECIALTY CONSUMER CIRCUIT, PDIP28, DIP-28 | 获取价格 |
|
| TDA7445 | STMICROELECTRONICS | SPECIALTY CONSUMER CIRCUIT, PDIP28, DIP-28 | 获取价格 |
|
| TDA7445D | STMICROELECTRONICS | SPECIALTY CONSUMER CIRCUIT, PDSO28, SO-28 | 获取价格 |
|
| TDA7448 | STMICROELECTRONICS | 6 CHANNEL VOLUME CONTROLLER | 获取价格 |
|
| TDA744813TR | STMICROELECTRONICS | 6 CHANNEL VOLUME CONTROLLER | 获取价格 |
|
| TDA7448_04 | STMICROELECTRONICS | 6 CHANNEL VOLUME CONTROLLER | 获取价格 |
|
| TDA7449 | STMICROELECTRONICS | TONE CONTROL DIGITALLY CONTROLLED AUDIO PROCESSOR | 获取价格 |
|
| TDA7449D | STMICROELECTRONICS | TONE CONTROL DIGITALLY CONTROLLED AUDIO PROCESSOR | 获取价格 |
|
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