TEA2164 [STMICROELECTRONICS]
SWITCH MODE POWER SUPPLY PRIMARY CIRCUIT; 开关电源初级电路
| 型号： | TEA2164 |
| 厂家： | 
ST |
| 描述： | SWITCH MODE POWER SUPPLY PRIMARY CIRCUIT |
| 文件： | 总15页 (文件大小：179K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TEA2164
SWITCH MODE POWER SUPPLY PRIMARY CIRCUIT
.
.
.
POSITIVE AND NEGATIVE OUTPUT CUR-
RENT UP TO 1.2A AND – 1.7A
A TWO LEVEL COLLECTOR CURRENT LIMI-
TATION
COMPLETE TURN OFF AFTER LONG DURA-
TION OVERLOADS
UNDER AND OVER VOLTAGE LOCK-OUT
SOFT START BY PROGRESSIVE CURRENT
LIMITATION
DOUBLE PULSE SUPPRESSION
BURST MODE OPERATION UNDER STAND-
BY CONDITIONS
.
.
.
.
DESCRIPTION
In amaster slave architecture,the TEA2164control
IC achieves the slave function. Primarily designed
for TV receivers and monitors applications, this
circuit provides an easy synchronizationand smart
solution for low power stand by operation.
POWERDIP16
(Plastic Package)
Located at the primary side the TEA2164 Control
IC ensures :
ORDER CODE : TEA2164
- the power supply start-up
- the power supply control under stand-by condi-
tions
- the process of the regulation signals sent by the
master circuit located at the secondary side
- directbasedrive ofthe bipolarswitchingtransistor
- the protection of the transistor and the power
supply under abnormal conditions.
For more details, refer to application note AN409.
PIN CONNECTIONS
GROUND
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VCC SUPPLY VOLTAGE
I COPY
LONG CAPACITOR OVERLOAD CAPACITO R
SUBSTRATE
OUTPUT STAGE POSITIVE SUPPLY VOLTAGE
OUTPUT (BASE CURRENT)
SUBSTRATE
SUBSTRATE
SUBSTRATE
PULSE INPUT
IC (max.) SENSE
LOW FREQUENCY OSCILLATOR CAPACITOR
FEEDBACK INPUT IS BURST MODE
OSCILLATOR TIMING RESISTOR
OSCILLATOR TIMING CAPACITOR
1/15
December 1992
TEA2164
BLOCK DIAGRAM
2/15
TEA2164
Figure 1 : Simplified Application Diagram
ABSOLUTE MAXIMUM RATINGS
Symbol
VCC
Parameter
Value
18
Unit
V
Positive Power Supply V16-V1
V+
Positive Power Supply of the Output Stage V15-V1
Negative Power Supply V4, 5, 12, 13-V1
Total Power Supply V16-V4, 5, 12, 13 or V15-V4, 5, 12, 13
18
V
V–
– 5
20
V
VCC - V–
V+ - V–
V
Iout+
Iout–
Tj
Positive Output Current
1.5
2
A
A
Negative Output Current
Operating Junction Temperature
Storage Temperature Range
150
°
C
Tstag
– 40, + 150
°
C
THERMAL DATA
Symbol
Parameter
Junction Case Thermal Resistance
Value
Unit
Rth(j-c)
11
°
C/W
MAXIMUM POWER DISSIPATION
3/15
TEA2164
RECOMMANDED OPERATING CONDITIONS
Symbol
VCC
Parameter
Min. Typ. Max. Unit
Positive Power Supply
10
14
5
V
V
V–
Negative Power Supply (absolute value) (note 1)
Total Power Supply
0
V
CC – V–
Iout+
Iout–
Fsw
Ro
18
V
Positive Output Current
1.2
1.7
50
A
Negative Output Current
A
Switching Frequency
khz
kΩ
pF
Oscillator Resistor Range
30
470
0.1
1
150
2700
4.7
22
Co
Oscillator Capacitor Range
Starting Oscillator Capacitor Range
Repetitive Overload Protection Capacitor
C1
µ
F
C2
µF
0.5
– 20
1
V
Vin
Input Pulses Amplitude (peak) (derivated pulses - time constant = 1 µs)
Toper
Operating Ambiant Temperature
70
°
C
-
V
CC
I
> 0
< 0
B
12 13
12 13
I
B
14
1
TEA2164
I
TEA2164
14
1
4
5
4
5
I
B
capacitive
coupling
-
V
CC
I
< 0
B
I
< 0
B
ELECTRICAL OPERATING CHARACTERISTICS
Tamb = 25oC, VCC = 10V, VCC- = 0V, potentialsreferenced to ground (Pin 1)
(unless otherwise specified)
Symbol
POWER SUPPLY
VCC (start)
Parameter
Min.
Typ.
Max.
Unit
Starting Voltage (VCC increasing)
8
5
9
9.6
7.4
V
V
V
CC (stop)
∆VCC
Stopping Voltage (VCC decreasing)
Hysteresis (VCC start – VCC stop)
Overvoltage Lock-out
6.2
2.8
15.5
0.8
2
3.5
V
Vccmax
Iccstart
14.8
0.5
16.2
1.5
V
Starting Positive Supply Current
mA
CURRENT LIMITATION AND PROTECTION (pin 11)
VCM1
VCM2
∆VCM
Pulse by Pulse Current Limitation Threshold
Current Monitoring 2nd Threshold
720
1200
300
840
1350
500
970
1500
700
mV
mV
mV
∆VCM = VCM2
– VCM1
REPETITIVE OVERCURRENT PROTECTION
VCM3
VCM3-VCM1
VC2
Repetitive Overcurrent Threshold (pin 11)
700
– 20
2.4
10
900
50
3
1100
130
3.6
mV
mV
V
(VCM3-VCM1)
Lock-out Voltage on Pin 3
I3 disch
I3 ch.
Capacitor C2 Discharge Current (synchronized mode)
Capacitor C2 Charge Current
20
80
30
µ
µ
A
A
50
110
OSCILLATOR, MAX DUTY CYCLE, SYNCHRONIZATION
To
Oscillator Initial Accuracy RT = 50 K, CT = 1 nF
Maximum Duty Cycle (Tsyn = 1.05 To)
19.3
60
21
70
22.7
85
µs
Ton(max)
%
4/15
TEA2164
ELECTRICAL OPERATING CHARACTERISTICS (continued)
Symbol
Parameter
Min.
Typ.
Max.
Unit
OSCILLATOR, MAX DUTY CYCLE, SYNCHRONIZATION (continued)
Tsyn
Synchronization Window
TO
1.0
1.5
OUTPUT STAGE
I14/I2
IBON
Ic Copy Current Gain
1000
300
Base Current Starting Pulse
mA
%
VERY LOW FREQUENCY OSCILLATOR
Burst Duty Cycle
13
I. FIELD OF APPLICATION
- stand-by mode output power (1W ≤ Psb ≤ 6W ;
efficiency > 50%)
- operating frequencyup to 50kHz
The TEA2164 control circuit has been designed
primarily for discontinuous mode flyback built with
a master-slave architecture, whatever the field of
application.
- power-switch : bipolar transistor
Adapted master-circuit :
But due to its capability to synchronize the transis-
tor switching-off with an external signal (line fly-
back) and dueto an adaptedburst-mode operation
for a low power stand-by operation, the TEA2164
offers a smart solution for monitors and TV sets
applications.
Monitor application
Standard TV application →
→
TEA5170
TEA2028B
TEA2029C
TEA2128
TEA5170
TEA5170
Digital TV application
→
Power supply main features :
- maximum output power 140W (transistor forced
gain : 3.5)
(TEA2028B, TEA2029C and TEA2128 are deflec-
tion processors with built-in PWM generator).
Figure 2 : Master Slave Power Supply Architecture
Muting
AUDIO
Control
OUTPUT
STAGE
R
Remote
Stand-by
P1
Synchronization
MAINS
INPUT
SCANNING
DEVICE
P2
C
VOLTAGE
REGULATOR
Remote
Stand-by
VCC
µP
TEA2164
TEA5170
VCC
INFRA-RED
RECEIVER
PWM
Small signal primary ground
Power primary ground
P1 : Output voltage adjustement in normal mode
P2 : Output voltage adjustement in stand-by
Secondary ground (isolated from mains)
5/15
TEA2164
II. GENERAL DESCRIPTION
In a master slave architecture, the TEA2164 Con-
trol IC, located at the primary side of an off line
power supplyachievesthe slavefunction; whereas
the master circuit is located at the secondary side.
The link between both circuits is realized by a small
pulse transformer (Figure 3).
Figure 3 : SystemDescription Waveforms
6/15
TEA2164
In the operation of the master-slave architecture,
four majors cases must be considered :
- normal operating
- stand-by mode
- power supply start-up
sends PWM signals, the structure is not synchro-
nized ; and the TEA2164 operates in burst mode.
The average power consumption at the secondary
side may be very low 1W ≤ P ≤ 6W (as it is
consumed in TV set during stand by).
- abnormalconditions : off load, short circuit, ...
By action on the maximum duty cycle control, a
primary loop maintains a semi-regulation of the
outputvoltages. Voltageon feed-backis applied on
Pin 9.
II.1. Normal Operating (master slave mode)
In this configuration, the master circuit generatesa
pulse width modulatedsignal issuedfromthe moni-
toring of the output voltage which needs the best
accuracy (in TV applications: the horizontaldeflec-
tionstagesupplyvoltage).Themaster circuit power
supply can be supplied by another output.
Burst period is externallyprogrammedby capacitor
C1.
II.3. Power Supply Start-up
The PWM signal are sent towards the primary side
through small differentiating transformer. For the
TEA2164 positive pulses are transistor switching-
on commands ; and negative pulses are transistor
switching-off commands (Figure 4). In this configu-
ration, only by synchronizing the master oscillator,
the switching transistor may be synchronized with
an external signal.
After the mains have been switched-on, the VCC
storage capacitor of the TEA2164 is charged
through a high value resistor connected to the
rectified high voltage. When Vcc reaches VCC start
threshold (9V typ), the TEA2164 starts operatingin
burst mode. Since available output power is low in
burst mode the output power consumption must
remain low before complete setting-up of output
voltage. In TV application it can be achieved by
maintaining the TV in stand-by mode during start-
up (Figure 6).
II.2. Stand-by Mode
In this configuration the master circuit no longer
Figure 4 : Master Slave Mode Waveforms
Sync.
Pulses
Synchro.
PWM
Signal
SLAVE
CIRCUIT
MASTER
CIRCUIT
Pulse
Input
Base
Current
7/15
TEA2164
Figure 5 : Burst Mode Waveforms
Figure 6 : Power Supply Start-up
Tch ≈ 1s (typ)
T1 ≈ 0.3s (typ)
T1 :necessary time for voltage setting-up
Tstart-up = Tch + T1
d) Abnormal conditions : safety functions
Power Limitation, Current Protection, Long
Duration Overload Protection
- Output power limitation : by a pulse by pulse
collector current limitation the TEA2164 limits the
maximum output power. VCM1 is the correspond-
ing voltage threshold, its detection is memorized
up to the next period.
- Current protection (transistor protection)
Under particular conditions a hard overload or
short circuit may induce a flux runaway in spite of
the current limitation (VCM1).
Overvoltage Protection
When VCC exceeds VCC max, an internal flip-flop
stops output conduction signals. The circuit will
start again after the capacitor C1 discharge ; it
means : after loss of synchronization or after Vcc
stop crossing (Figure 7).
In flyback converters, this function protects the
power supply against output voltage runaway.
The TEA2164 control circuit features a second
current protection, VCM2. When this threshold is
reached an internal flip-flop memorizes it and
Under Voltage Lock-out
The TEA2164 control circuit stops operating when
VCC goes under VCC stop.
8/15
TEA2164
output conduction signals are inhibited. The cir-
cuit will send base drives again aftercapacitorC1
discharge (Figure 7).
keeps charging at each period and its voltage
encreases gradually. When the voltage on Pin 3
exceeds VC2, the TEA2164 control circuit stops
sending base drives and memorizes this event.
No restart is allowed as long as Vpin 3 is higher
than VC2 and VCC higher than 4.8V.
- Long duration overload protection : (Figure 8)
An overload is detected when the sense-voltage
on Pin 11 reaches VCM3 before a negativepulse
has been appliedto Pin 6. In thiscase the capaci-
tor C2 (connected to Pin 3) is charged with I3 ch
up to the end of the period and discharged with I3
disch until a next VCM3 detector. By this way in
case of long duration overload, the capacitor
* Remark :
- The harder is the overload the faster is the pro-
tection
- The capacitorkeeps charging between two burst
after VCM2 detection.
Figure 7 : OvervoltagesLock-out
Figure 8 : Long Duration Overload Monitoring Circuit
Figure 9 : Long Duration Overload Detection
9/15
TEA2164
Figure 10 : Repetitive Over-current Protection
III. SWITCHING OSCILLATOR AND SYNCHRONIZATION
III.1. Switching oscillator
oscillators are not synchonuous. In order to avoid
any erratic conduction of the power transistor, the
first synchronization pulse will arrive simultanously
with the sawtooth return of the TEA2164 oscillator.
When the TEA2164 controlcircuit operates in burst
mode, the switching frequency is fixed by the free
frequency oscillator. The period is determined by
two external components CO and RO.
To get synchronization the free frequency must be
higher than the synchronization frequency.
III.2. Synchronization
When the master-circuit starts to send pulses both
TO < Tsync. < 1.50 TO
Figure 11 : Free Frequency Running
Figure 12 : Synchronization Pulse Shaper and Synchronization
10/15
TEA2164
Operation after synchronization
(1) NORMAL OPERATION
(2) NEGATIVE PULSE MISSING
Transistor turn-off is ensured by VCM1 current limitation cross-
ing or by an internal tON (max.) limitation set by a 2.5V threshold
∆T : synchronization window
Operation after synchronization
(3) ERRATIC POSITIVE PULSES
(4) Fsynchro < 0.65 Fo
Signal S1 triggers burst oscillator capacitor discharge.
The TEA2164 restarts in burst-mode
P1 and P2 are masked due to the synchronization window
Cases (2) (3) (4) do not occur in normal operating.
IV - MAXIMUM DUTY CYCLE LIMITATION
that realizes an efficient transistor turn-on.
- After the starting pulse IBON, the base current is
proportional to the collector current. The current
gain is easily fixed by a resistor R (Figure 14).
- A fast and safe transistor turn-off is realized by a
fast positive base current cut-off and by applying
a negative base drive which draws stored carri-
ers. A typical 0.7s delay preventsfrom cross-con-
duction of positive and negative output stages.
Burst mode : Themaximum dutycycle is controlled
by the voltage on Pin 9 (Figure 13).
Synchronized mode : Normally the maximum duty
cycle is set by the master circuit. Oowever the
maximum conducting time will never exceed the
value given by the comparison of the oscillator
wave-form with the 2.5V internal threshold.
Remark : In order to reduce power dissipation on
the positive output stage with the low gain transis-
tors, forhigh basecurrentsthepositiveoutputstage
operates in saturated mode (Figure 15). This can
be achieved by using a resistorbetween VCC and
V+.
V - OUTPUT STAGE
TEA2164 output stage has been designed to drive
switching bipolar transistor.
- Each base drive beginswith a positive pulse IBON
11/15
TEA2164
Figure 13 : Maximum Duty Cycle Limitation
Figure 14 : OutputStage Architecture and Base Drive
IB
IBON
V
t
VCC
16
15
CURRENT
MIRROR
IC
ICmax
IB
14
Virtual
Ground
t
VCM1
RS
V
2
IC
RB
ICOPY
4-5-12-13
GF
IC
RS
R B
=
IB
ICmax
IC
GF =
=
IB
1000 x RS
VI - MONITOR APPLICATIONS
The energy of the starting burst must be high
enough to ensure start-up, then the capacitor C1
must be higher in these applications than on TV
application (typ. : 1µF).
In most of monitor applications, the power supply
must start-up under full load conditions and the
stand -by mode is no longer useful.
Figure 15 : Power Supply Start-up and Normal Operation
12/15
TEA2164
COMPLETE APPLICATION DIAGRAM (SMPS + DEFLECTION) (with stand-by function)
Ω 8 k 6 .
Ω
3 9 0
0 1 0 n F
1 k
Ω 1 k
Ω
Ω 1 k
Ω 1 k
. 7 4 n F
0 n 1 F 0
( 1 % Ω ) 3 . 2 3 k
. 3 3 n F
2 2 0 n F
2 2 n F
1 0 0 n F
Ω k 1 2
1 1 0 k
Ω
13/15
TEA2164
STAND-ALONE 32kHz POWER SUPPLY ELECTRICAL DIAGRAM
14/15
TEA2164
PACKAGE MECHANICAL DATA
16 PINS - PLASTIC POWERDIP
b1
B
b
e
E
Z
e3
D
9
8
16
1
Millimeters
Typ.
Inches
Typ.
Dimensions
Min.
0.51
0.85
Max.
Min.
0.020
0.033
Max.
a1
B
b
1.4
0.055
0.5
0.020
b1
D
E
e
0.38
0.5
20
0.015
0.020
0.787
8.8
2.54
17.78
0.346
0.100
0.700
e3
F
7.1
5.1
0.280
0.201
i
L
3.3
0.130
Z
1.27
0.050
Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsibility
for the consequences of use of such information norfor any infringement of patents or other rights of third partieswhich may result
from itsuse. No licence is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics.
Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all
information previously supplied. SGS-THOMSON Microelectronics productsare not authorized for use as critical components in life
support devices or systems without express written approval of SGS-THOMSON Microelectronics.
1994 SGS-THOMSON Microelectronics - All Rights Reserved
Purchase of I2C Components of SGS-THOMSON Microelectronics, conveys a license under the Philips
I2C Patent. Rights to use these components in a I2C system, is granted provided that the system conforms to
the I2C Standard Specifications as defined by Philips.
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