TS4984EIJT [STMICROELECTRONICS]
1.2W Stereo Audio Power Amplifier with Active Low Standby Mode; 1.2W立体声音频功率放大器有源低待机模式
| 型号： | TS4984EIJT |
| 厂家： | 
ST |
| 描述： | 1.2W Stereo Audio Power Amplifier with Active Low Standby Mode |
| 文件： | 总30页 (文件大小：1647K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TS4984FC
1.2W Stereo Audio Power Amplifier with
Active Low Standby Mode
■ Operating from V = 2.2V to 5.5V
CC
TS4984 - flip-chip 15 bumps
■ 1.2W output power per channel @ V = 5V,
CC
THD+N = 1%, R = 8Ω
L
■ 10nA standby current
■ 62dB PSRR @ 217Hz with grounded inputs
■ High SNR: 106dB(A) typ.
Pin connections (top view)
■ Near-zero pop & click
■ Available in a 15-bump flip-chip (lead-free)
VCC
IN2+
IN2-
VCC
BYPASS
STDBY
Description
VOUT2+
GND
VOUT1+
IN1+
The TS4984 has been designed for top-class
stereo audio applications. Thanks to its compact
and power dissipation efficient flip-chip package, it
suits various applications.
VOUT2-
VOUT1-
IN1-
BYPASS
GND
With a output BTL configuration, this audio power
amplifier is capable of delivering 1.2W per
channel of continuous RMS output power into an
8Ω load @ 5V.
Applications
An externally-controlled standby mode reduces
the supply current to less than 10nA per channel.
The device also features an internal thermal
shutdown protection.
■ Cellular mobile phones
■ Notebook & PDA computers
■ LCD monitors & TVs
The gain of each channel can be configured by
external gain setting resistors.
■ Portable audio devices
Order Codes
Part Number
TS4984EIJT
Temperature Range
Package
Packing
Marking
Lead free flip-chip
Lead free flip-chip +
back coating
-40, +85°C
Tape & Reel
A84
TS4984EIKJT
Rev 2
1/30
November 2005
www.st.com
30
Typical Application Schematic
TS4984FC
1
Typical Application Schematic
Figure 1 show a typical application schematic for the TS4984FC.
Figure 1. Application information
Cfeed1
Rfeed1
22k
VCC
Cs
U1
Cin1
INPUT1
A1
B2
IN1-
-
A3
Rin1
22k
VOUT1-
100nF
IN1+
+
OUTPUT1
+
-
VOUT1+ B4
AV = -1
C5
C3
BYPASS
+
Cb
STDBY
StandBy
Control
Bias
D6
E5
IN2+
IN2-
+
-
Wire optional
Internal connection
E3
VOUT2-
OUTPUT2
+
Cin2
INPUT2
Rin2
22k
100nF
-
D4
VOUT2+
AV = -1
C1
BYPASS
+
22k
Rfeed2
Cfeed2
Table 1.
External component descriptions
Functional Description
Inverting input resistors which sets the closed loop gain in conjunction with R
Components
.
feed
R
C
in L,R
These resistors also form a high pass filter with C = 1/2 x Pi x R x C ))
in
in
in
Input coupling capacitors which blocks the DC voltage at the amplifier input terminal
in L,R
R
Feedback resistors which sets the closed loop gain in conjunction with R
Supply Bypass capacitor which provides power supply filtering
Bypass pin capacitor which provides half supply filtering
feed L,R
in
C
s
C
b
A
Closed loop gain in BTL configuration = 2 x (R
/ R ) on each channel
V L, R
feed in
2/30
TS4984FC
Absolute Maximum Ratings
2
Absolute Maximum Ratings
Table 2.
Symbol
Key parameters and their absolute maximum ratings
Parameter
Value
Unit
(1)
V
6
V
CC
Supply voltage
(2)
V
GND to V
V
Input Voltage
i
CC
T
Operating Free Air Temperature Range
Storage Temperature
-40 to + 85
-65 to +150
150
°C
°C
°C
oper
T
stg
T
Maximum Junction Temperature
j
Thermal Resistance Junction to Ambient for
Flip-chip15
R
180
°C/W
thja
P
Power Dissipation
Internally Limited
2
diss
(3)
ESD
ESD
kV
V
Human Body Model
Machine Model
200
Latch-up Immunity
200mA
1. All voltages values are measured with respect to the ground pin
2. The magnitude of input signal must never exceed VCC + 0.3V / GND - 0.3V
3. All voltage values are measured from each pin with respect to supplies
Table 3.
Symbol
Operating conditions
Parameter
Value
Unit
V
V
Supply Voltage
2.2 to 5.5
1.2V to V
CC
V
Common Mode Input Voltage Range
Standby Voltage Input:
V
ICM
CC
1.35 ≤ V
≤ V
CC
V
V
STBY
Device ON
STBY
GND ≤ V
≤ 0.4
Device OFF
STBY
R
Load Resistor
≥ 4
Ω
L
R
Resistor Output to GND (V
= GND)
≥ 1
MΩ
°C
OUTGND
STBY
T
Thermal Shutdown Temperature
150
SD
Thermal Resistance Junction to Ambient
R
110
°C/W
thja
(1)
Flip-chip15
1. When mounted on a 4-layer PCB
3/30
Electrical Characteristics
TS4984FC
3
Electrical Characteristics
Table 4.
Symbol
V
= +5V, GND = 0V, T
= 25°C (unless otherwise specified)
amb
CC
Parameter
Conditions
Min.
Typ. Max.
Unit
mA
nA
I
Supply Current
Standby Current
No input signal, no load
7.4
10
1
12
1000
10
CC
(1)
I
No input signal, V
= GND, R = 8Ω
STBY L
STBY
V
No input signal, R = 8Ω
Output Offset Voltage
Output Power
mV
W
OO
L
P
THD = 1% Max, F = 1kHz, R = 8Ω
0.9
1.2
out
L
P
= 1Wrms, A = 2
V
Total Harmonic Distortion
+ Noise
out
THD + N
PSRR
0.2
62
64
%
20Hz ≤ F ≤ 20kHz, R = 8Ω
L
R = 8Ω, A = 2, V = 200mVpp,
ripple
Input Grounded, F = 217Hz
L
V
55
55
Power Supply Rejection
dB
(2)
Ratio
R = 8Ω, A = 2, V = 200mVpp,
Input Grounded, F = 1kHz
L
V
ripple
R = 8Ω, F = 1kHz
107
82
L
Crosstalk Channel Separation,
dB
R = 8Ω, F = 20Hz to 20kHz
L
t
C = 1µF
Wake-Up Time
Standby Time
90
130
ms
µs
wu
b
t
C = 1µF
10
stby
b
Standby Voltage Level
High
V
1.3
0.4
V
V
STBYH
Standby Voltage Level
Low
V
STBYL
Phase Margin at Unity
Gain
Φ
R = 8Ω, C = 500pF
65
Degrees
M
L
L
R = 8Ω, C = 500pF
GM
Gain Margin
15
dB
L
L
R = 8Ω
GBP
Gain Bandwidth Product
1.5
MHz
L
1. Standby mode is activated when VSTBY is tied to Gnd.
2. All PSRR data limits are guaranteed by production sampling tests.
Dynamic measurements - 20*log(rms(Vout)/rms(Vripple)). Vripple is the sinusoidal signal superimposed upon VCC
.
4/30
TS4984FC
Electrical Characteristics
= 25°C (unless otherwise specified)
amb
Table 5.
Symbol
V
= +3.3V, GND = 0V, T
Parameter
CC
Min. Typ. Max.
Unit
mA
nA
I
Supply Current
Standby Current
No input signal, no load
6.6
10
1
12
1000
10
CC
(1)
I
No input signal, V
= GND, R = 8Ω
STBY L
STBY
V
No input signal, R = 8Ω
Output Offset Voltage
Output Power
mV
mW
OO
L
P
THD = 1% Max, F = 1kHz, R = 8Ω
375
500
out
L
P
= 400mWrms, A = 2
V
Total Harmonic Distortion
+ Noise
out
THD + N
PSRR
0.1
61
63
%
20Hz ≤ F ≤ 20kHz, R = 8Ω
L
R = 8Ω, A = 2, V = 200mVpp,
ripple
Input Grounded, F = 217Hz
L
V
55
55
Power Supply Rejection
dB
(2)
Ratio
R = 8Ω, A = 2, V = 200mVpp,
Input Grounded, F = 1kHz
L
V
ripple
R = 8Ω, F = 1kHz
107
82
L
Crosstalk Channel Separation,
dB
R = 8Ω, F = 20Hz to 20kHz
L
t
C = 1µF
Wake-Up Time
Standby Time
110
10
140
ms
µs
wu
b
t
C = 1µF
stby
b
Standby Voltage Level
High
V
1.2
0.4
V
V
STBYH
Standby Voltage Level
Low
V
STBYL
Phase Margin at Unity
Gain
Φ
R = 8Ω, C = 500pF
65
Degrees
M
L
L
R = 8Ω, C = 500pF
GM
Gain Margin
15
dB
L
L
R
= 8Ω
GBP
Gain Bandwidth Product
1.5
MHz
L
1. Standby mode is activated when VSTBY is tied to Gnd.
2. All PSRR data limits are guaranteed by production sampling tests.
Dynamic measurements - 20*log(rms(Vout)/rms(Vripple)). Vripple is the sinusoidal signal superimposed upon VCC
.
5/30
Electrical Characteristics
TS4984FC
Table 6.
Symbol
V
= +2.6V, GND = 0V, T
= 25°C (unless otherwise specified)
amb
CC
Parameter
Min. Typ. Max.
Unit
mA
nA
I
Supply Current
Standby Current
No input signal, no load
6.2
10
1
12
1000
10
CC
(1)
I
No input signal, V
= GND, R = 8Ω
STBY
STBY L
V
No input signal, R = 8Ω
Output Offset Voltage
Output Power
mV
mW
OO
L
P
THD = 1% Max, F = 1kHz, R = 8Ω
220
300
out
L
P
= 200mWrms, A = 2
V
Total Harmonic Distortion
+ Noise
out
THD + N
PSRR
0.1
60
62
%
20Hz ≤ F ≤ 20kHz, R = 8Ω
L
R = 8Ω, A = 2, V = 200mVpp,
ripple
Input Grounded, F = 217Hz
L
V
55
55
Power Supply Rejection
dB
(2)
Ratio
R = 8Ω, A = 2, V = 200mVpp,
Input Grounded, F = 1kHz
L
V
ripple
R = 8Ω, F = 1kHz
107
82
L
Crosstalk Channel Separation,
dB
R = 8Ω, F = 20Hz to 20kHz
L
t
C = 1µF
Wake-Up Time
Standby Time
125
10
150
ms
µs
wu
b
t
C = 1µF
stby
b
Standby Voltage Level
High
V
1.2
0.4
V
V
STBYH
Standby Voltage Level
Low
V
STBYL
Phase Margin at Unity
Gain
Φ
R = 8Ω, C = 500pF
Degrees
M
L
L
65
15
R = 8Ω, C = 500pF
GM
Gain Margin
dB
L
L
R
= 8Ω
GBP
Gain Bandwidth Product
MHz
L
1.5
1. Standby mode is activated when VSTBY is tied to Gnd.
2. All PSRR data limits are guaranteed by production sampling tests.
Dynamic measurements - 20*log(rms(Vout)/rms(Vripple)). Vripple is the sinusoidal signal superimposed upon VCC
.
6/30
TS4984FC
Table 7.
Electrical Characteristics
Index of graphics
Description
Figure
Page
Open Loop Frequency Response
Figure 2 to 7
Figure 8 to 13
page 8
page 9
Power Supply Rejection Ratio (PSRR) vs. Frequency
page 10 to
page 11
Power Supply Rejection Ratio (PSRR) vs. DC Output Voltage
Figure 14 to 22
Figure 23
Power Supply Rejection Ratio (PSRR) at F=217Hz vs. Bypass
Capacitor
page 11
page 11 to
page 12
Output Power vs. Power Supply Voltage
Output Power vs. Load Resistor
Figure 24 to 27
Figure 28 to 30
Figure 31 to 33
page 12
page 12 to
page 13
Power Dissipation vs. Output Power
Figure 34,
Figure 35
Clipping Voltage vs. Power Supply Voltage and Load Resistor
Current Consumption vs. Power Supply Voltage
Current Consumption vs. Standby Voltage
Power Derating Curves
page 13
page 13
Figure 36
Figure 37 to 39
Figure 40
page 13 to
page 14
page 14
page 14 to
page 15
THD+N vs. Output Power
Figure 41 to 49
THD+N vs. Frequency
Crosstalk vs. Frequency
Figure 50 to 52
Figure 53 to 55
page 16
page 16
SIgnal to Noise Ratio vs. Power Supply with Unweighted Filter
(20Hz to 20kHz)
Figure 56,
Figure 57
page 17
page 17
Figure 58,
Figure 59
SIgnal to Noise Ratio vs. Power Supply with A-weighted Filter
Output Noise Voltage, Device ON
Figure 60
Figure 61
page 17
page 17
Output Noise Voltage, Device in Standby
7/30
Electrical Characteristics
TS4984FC
Figure 3. Open loop frequency response
Figure 2. Open loop frequency response
100
80
60
40
20
0
0
60
40
20
0
0
Gain
Gain
-40
-80
-120
-160
-200
-40
-80
-120
-160
-200
Phase
Phase
-20
-40
-60
Vcc = 5V
RL = 8
Vcc = 5V
CL = 560pF
-20
Ω
Tamb = 25
°C
Tamb = 25
°C
-40
0.1
1
10
100
1000
10000
0.1
1
10
100
1000
10000
Frequency (kHz)
Frequency (kHz)
Figure 4. Open loop frequency response
Figure 5. Open loop frequency response
60
40
20
0
0
100
80
60
40
20
0
0
Gain
Gain
-40
-80
-120
-160
-200
-40
Phase
-80
Phase
-120
-160
-200
-20
-40
-60
Vcc = 3.3V
RL = 8
Vcc = 3.3V
CL = 560pF
-20
Ω
Tamb = 25
°C
Tamb = 25
°C
-40
0.1
0.1
1
10
100
1000
10000
1
10
100
1000
10000
Frequency (kHz)
Frequency (kHz)
Figure 6. Open loop frequency response
Figure 7. Open loop frequency response
60
40
20
0
0
100
80
60
40
20
0
0
Gain
Gain
-40
-80
-120
-160
-200
-40
-80
-120
-160
-200
Phase
Phase
-20
-40
-60
Vcc = 2.6V
RL = 8
Vcc = 2.6V
CL = 560pF
Ω
-20
-40
Tamb = 25
°C
Tamb = 25
°C
0.1
1
10
100
1000
10000
0.1
1
10
100
1000
10000
Frequency (kHz)
Frequency (kHz)
8/30
TS4984FC
Electrical Characteristics
Figure 8. Power supply rejection ratio (PSRR) Figure 9. Power supply rejection ratio (PSRR)
vs. frequency
vs. frequency
0
-10
-20
-30
-40
-50
-60
-70
-80
0
-10
-20
-30
-40
-50
-60
-70
Vripple = 200mVpp
Vripple = 200mVpp
Av = 2
Input = Grounded
Vcc = 2.2, 2.6, 3.3, 5V
Rfeed = 22k
Input = Floating
Cb = 0.1
RL >= 4
Tamb = 25
Ω
µF
Cb = Cin = 1
RL >= 4
Tamb = 25
µ
F
Vcc :
2.2V
2.6V
3.3V
5V
Ω
Ω
°C
°
C
100
1000
10000
Frequency (Hz)
100000
100
1000
10000
100000
Frequency (Hz)
Figure 10. Power supply rejection ratio (PSRR) Figure 11. Power supply rejection ratio (PSRR)
vs. frequency
vs. frequency
0
-10
-20
-30
-40
-50
-60
0
-10
-20
-30
-40
-50
-60
-70
-80
Vripple = 200mVpp
Av = 5
Input = Grounded
Vripple = 200mVpp
Vcc :
Vcc = 2.2, 2.6, 3.3, 5V
Rfeed = 22k
Input = Floating
Cb = 1
RL >= 4
Tamb = 25
Ω
2.2V
2.6V
3.3V
5V
Cb = Cin = 1
RL >= 4
Tamb = 25
µ
F
µF
Ω
Ω
°
C
°C
100
1000
10000
100000
100
1000
10000
Frequency (Hz)
100000
Frequency (Hz)
Figure 12. Power supply rejection ratio (PSRR) Figure 13. Power supply rejection ratio (PSRR)
vs. frequency
vs. frequency
0
-10
-20
-30
-40
-50
0
-10
-20
-30
-40
-50
-60
Vripple = 200mVpp
Av = 10
Input = Grounded
Vripple = 200mVpp
Av = 2
Input = Grounded
Vcc :
2.2V
2.6V
3.3V
5V
Cb = Cin = 1
RL >= 4
Tamb = 25
µ
F
Cb = 0.1
RL >= 4
Tamb = 25
µF, Cin = 1µF
Ω
Ω
°
C
°C
Vcc = 5, 3.3, 2.5 & 2.2V
100
1000
10000
100000
100
1000
10000
100000
Frequency (Hz)
Frequency (Hz)
9/30
Electrical Characteristics
TS4984FC
Figure 14. Power supply rejection ratio (PSRR) Figure 15. Power supply rejection ratio (PSRR)
vs. DC output voltage
vs. DC output voltage
0
-10
-20
-30
-40
-50
-60
-70
0
-10
-20
-30
-40
-50
-60
Vcc = 5V
Vripple = 200mVpp
Vcc = 5V
Vripple = 200mVpp
RL = 8
Ω
RL = 8
Ω
Cb = 1µF
Cb = 1µF
AV = 2
Tamb = 25°C
AV = 5
Tamb = 25°C
-5
-4
-3
-2
-1
0
1
2
3
4
5
-5
-4
-3
-2
-1
0
1
2
3
4
5
Differential DC Output Voltage (V)
Differential DC Output Voltage (V)
Figure 16. Power supply rejection ratio (PSRR) Figure 17. Power supply rejection ratio (PSRR)
vs. DC output voltage
vs. DC output voltage
0
-10
-20
-30
-40
-50
-60
-70
0
-10
-20
-30
-40
-50
Vcc = 3.3V
Vripple = 200mVpp
Vcc = 5V
Vripple = 200mVpp
RL = 8
Ω
RL = 8
Ω
Cb = 1µF
Cb = 1µF
AV = 2
Tamb = 25°C
AV = 10
Tamb = 25°C
-3.0 -2.5 -2.0 -1.5 -1.0 -0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0
-5
-4
-3
-2
-1
0
1
2
3
4
5
Differential DC Output Voltage (V)
Differential DC Output Voltage (V)
Figure 18. Power supply rejection ratio (PSRR) Figure 19. Power supply rejection ratio (PSRR)
vs. DC output voltage
vs. DC output voltage
0
-10
-20
-30
-40
-50
-60
0
-10
-20
-30
-40
-50
Vcc = 3.3V
Vripple = 200mVpp
Vcc = 3.3V
Vripple = 200mVpp
RL = 8
Ω
RL = 8
Ω
Cb = 1µF
Cb = 1µF
AV = 5
Tamb = 25°C
AV = 10
Tamb = 25°C
-3.0 -2.5 -2.0 -1.5 -1.0 -0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0
-3.0 -2.5 -2.0 -1.5 -1.0 -0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0
Differential DC Output Voltage (V)
Differential DC Output Voltage (V)
10/30
TS4984FC
Electrical Characteristics
Figure 20. Power supply rejection ratio (PSRR) Figure 21. Power supply rejection ratio (PSRR)
vs. DC output voltage
vs. DC output voltage
0
-10
-20
-30
-40
-50
-60
-70
0
-10
-20
-30
-40
-50
-60
Vcc = 2.6V
Vripple = 200mVpp
Vcc = 2.6V
Vripple = 200mVpp
RL = 8
Ω
RL = 8
Ω
Cb = 1µF
Cb = 1µF
AV = 2
Tamb = 25°C
AV = 5
Tamb = 25°C
-2.5 -2.0 -1.5 -1.0 -0.5 0.0 0.5 1.0 1.5 2.0 2.5
-2.5 -2.0 -1.5 -1.0 -0.5 0.0 0.5 1.0 1.5 2.0 2.5
Differential DC Output Voltage (V)
Differential DC Output Voltage (V)
Figure 22. Power supply rejection ratio (PSRR) Figure 23. Power supply rejection ratio (PSRR)
vs. DC output voltage
at F = 217Hz vs. bypass capacitor
0
-10
-20
-30
-40
-50
Av=10
Vcc:
2.6V
3.3V
5V
Vcc = 2.6V
Vripple = 200mVpp
-30
-40
-50
-60
-70
-80
RL = 8
Ω
Cb = 1µF
AV = 10
Tamb = 25°C
Av=2
Vcc:
2.6V
3.3V
5V
Av=5
Vcc:
2.6V
3.3V
5V
Tamb=25°C
0.1
1
-2.5 -2.0 -1.5 -1.0 -0.5 0.0 0.5 1.0 1.5 2.0 2.5
Bypass Capacitor Cb ( F)
Differential DC Output Voltage (V)
Figure 24. Output power vs. power supply
voltage
Figure 25. Output power vs. power supply
voltage
11/30
Electrical Characteristics
TS4984FC
Figure 27. Output power vs. power supply
Figure 26. Output power vs. power supply
voltage
voltage
Figure 28. Output power vs. load resistor
Figure 29. Output power vs. load resistor
Figure 30. Output power vs. load resistor
Figure 31. Power dissipation vs. output power
per channel
12/30
TS4984FC
Electrical Characteristics
Figure 32. Power dissipation vs. output power Figure 33. Power dissipation vs. output power
per channel
per channel
Figure 34. Clipping voltage vs. power supply
voltage and load resistor
Figure 35. Clipping voltage vs. power supply
voltage and load resistor
Figure 36. Current consumption vs. power
supply voltage
Figure 37. Current consumption vs. standby
voltage at V
= 5V
CC
No Loads
Tamb=25°C
Vcc = 5V
No Loads
Tamb=25°C
13/30
Electrical Characteristics
TS4984FC
Figure 38. Current consumption vs. standby
Figure 39. Current consumption vs. standby
voltage at V = 2.6V
voltage at V = 3.3V
CC
CC
Vcc = 3.3V
No Loads
Vcc = 2.6V
No Loads
Tamb=25°C
Tamb=25°C
Figure 40. Power derating curves
Figure 41. THD + N vs. output power
Figure 42. THD + N vs. output power
Figure 43. THD + N vs. output power
14/30
TS4984FC
Electrical Characteristics
Figure 45. THD + N vs. output power
Figure 44. THD + N vs. output power
Figure 46. THD + N vs. output power
Figure 47. THD + N vs. output power
Figure 48. THD + N vs. output power
Figure 49. THD + N vs. output power
15/30
Electrical Characteristics
TS4984FC
Figure 50. THD + N vs. frequency
Figure 51. THD + N vs. frequency
Figure 52. THD + N vs. frequency
Figure 53. Crosstalk vs. frequency
0
Vcc = 2.6V
−2 0 Pout = 200mW
RL = 8
Av = 2
BW < 125kHz
Tamb = 25°C
Ω
−4 0
−6 0
OUT1 to OUT2
OUT2 to OUT1
−8 0
−100
−120
−140
100
1000
Frequency(Hz)
10000
Figure 54. Crosstalk vs. frequency
Figure 55. Crosstalk vs. frequency
0
0
Vcc = 3.3V
Vcc = 5V
−2 0 Pout = 400mW
−2 0 Pout = 1W
RL = 8
Av = 2
BW < 125kHz
Tamb = 25°C
Ω
RL = 8
Av = 2
BW < 125kHz
Tamb = 25°C
Ω
−4 0
−6 0
−4 0
−6 0
OUT1 to OUT2
OUT1 to OUT2
OUT2 to OUT1
OUT2 to OUT1
−8 0
−8 0
−100
−120
−140
−100
−120
−140
100
1000
Frequency(Hz)
10000
100
1000
Frequency(Hz)
10000
16/30
TS4984FC
Electrical Characteristics
Figure 56. Signal to noise ratio vs. power
supply with unweighted filter (20Hz
to 20kHz)
Figure 57. Signal to noise ratio vs. power
supply with unweighted filter (20Hz
to 20kHz)
Figure 58. Signal to noise ratio vs. power
supply with A weighted filter
Figure 59. Signal to noise ratio vs. power
supply with A weighted filter
Figure 60. Output noise voltage, device ON
Figure 61. Output noise voltage, device in
standby
17/30
Application Information
TS4984FC
4
Application Information
The TS4984 integrates two monolithic power amplifiers with a BTL (Bridge Tied Load) output
type (explained in more detail in Section 4.1). For this discussion, only the left-channel amplifier
will be referred to.
Referring to the schematic in Figure 62, we assign the following variables and values:
V = Vin1-
in
V
= VOUT1+
= VOUT1-
out1
V
out2
R = Rin1
in
R
C
= Rfeed1
= Cfeed1
feed
feed
Figure 62. Typical application schematic - left channel
Cfeed = Cfeed1
VCC
Rfeed = Rfeed1
Cs
1u
TS4984
Cin = Cin1
Vin- = VIN1-
IN1
-
2
1
GND
Rin = Rin1
Vout1 = VOUT1+
Vout2 = VOUT1-
Vin+ = VIN1+
+
RL
-
STDBY
Bias
AV = -1
BYPASS
+
Cb
1u
4.1
BTL configuration principle
BTL (Bridge Tied Load) means that each end of the load is connected to two single-ended
output amplifiers. Thus, we have:
Single-ended output 1 = V
Single-ended output 2 = V
= V
(V),
out1
out2
out
= -V
(V), V
- V
= 2V
(V)
out
out1
out2
out
18/30
TS4984FC
The output power is:
Application Information
2
(2VoutRMS
Pout = ---------------------------------
RL
)
For the same power supply voltage, the output power in a BTL configuration is four times higher
than the output power in a single-ended configuration.
4.2
Gain in typical application schematic
The typical application schematic (Figure 62) is shown on page 18.
In the flat region (no C effect), the output voltage of the first stage is:
in
Rfeed
--------------
Vout1 = (–Vin)
(V)
Rin
For the second stage:
V
= -V
(V)
out2
out1
The differential output voltage is:
Rfeed
--------------
Rin
V
out2 – Vout1 = 2Vin
(V)
The differential gain, referred to as G for greater convenience, is:
v
Rfeed
--------------
Rin
V
out2 – Vout1
Gv = ---------------------------------- = 2
Vin
V
is in phase with V and V
is phased 180° with V . This means that the positive
out2
in
out1 in
terminal of the loudspeaker should be connected to V
and the negative to V
.
out2
out1
4.3
Low and high frequency response
In the low frequency region, C starts to have an effect. C forms with R a high-pass filter with
in
in
in
a -3dB cut-off frequency:
1
------------------------
FCL
=
(Hz)
2πRinCin
In the high frequency region, you can limit the bandwidth by adding a capacitor (C
) in
feed
parallel with R
. It forms a low-pass filter with a -3dB cut-off frequency. F is in Hz.
feed
CH
1
------------------------------------
FCH
=
(Hz)
2πRfeedCfeed
19/30
Application Information
The following graph (Figure 63) shows an example of Cin and Cfeed influence.
TS4984FC
Figure 63. Frequency response gain versus C & C
in
feed
10
5
0
-5
Cfeed = 330pF
Cfeed = 680pF
Cfeed = 2.2nF
Cin = 470nF
-10
-15
-20
-25
Cin = 22nF
Cin = 82nF
Rin = Rfeed = 22k
Ω
Tamb = 25
°C
10
100
Frequency (Hz)
1000
10000
4.4
Power dissipation and efficiency
Hypotheses:
●
Voltage and current in the load are sinusoidal (V and I ).
out out
●
Supply voltage is a pure DC source (V ).
CC
Regarding the load we have:
and
Vout = VPEAK sinωt (V)
Vout
------------
RL
Iout
=
(A)
and
2
VPEAK
----------------------
2RL
Pout
=
(W)
Therefore, the average current delivered by the supply voltage is:
VPEAK
-----------------
ICC
= 2
(A)
AVG
πRL
The power delivered by the supply voltage is:
Psupply = VCC ⋅ ICC
(W)
(W)
AVG
Then, the power dissipated by each amplifier is:
Pdiss = Psupply – Pout
2 2VCC
----------------------
Pdiss
=
⋅
P
out – Pout
(W)
π RL
20/30
TS4984FC
and the maximum value is obtained when:
Application Information
∂Pdiss
------------------
∂Pout
= 0
and its value is:
2Vc2c
Pdissmax = -------------
π2RL
(W)
Note:
This maximum value is only depending on power supply voltage and load values.
The efficiency, η, is the ratio between the output power and the power supply:
Pout
πVPEAK
4VCC
------------------- ----------------------
η =
=
Psupply
The maximum theoretical value is reached when V
= V , so that:
CC
PEAK
π
---- = 78.5%
4
The TS4984 has two independent power amplifiers, and each amplifier produces heat due to its
power dissipation. Therefore, the maximum die temperature is the sum of the each amplifier’s
maximum power dissipation. It is calculated as follows:
P
P
= Power dissipation due to the 1st channel power amplifier.
= Power dissipation due to the 2nd channel power amplifier.
diss1
diss2
Total P
= P
+ P
(W)
diss2
diss
diss1
In most cases, P
= P
, giving:
diss1
diss2
Total Pdiss= Pdiss1= Pdiss2
(W)
or, stated differently:
4 2VCC
----------------------
Total Pdiss
=
P
out – 2Pout
(W)
π RL
4.5
Decoupling the circuit
Two capacitors are needed to correctly bypass the TS4984. A power supply bypass capacitor
C and a bias voltage bypass capacitor C .
S
b
C has particular influence on the THD+N in the high frequency region (above 7kHz) and an
S
indirect influence on power supply disturbances. With a value for C of 1µF, you can expect
S
similar THD+N performances to those shown in the datasheet. For example:
●
In the high frequency region, if C is lower than 1µF, it increases THD+N and disturbances
S
on the power supply rail are less filtered.
●
On the other hand, if C is higher than 1µF, those disturbances on the power supply rail
S
are more filtered.
C has an influence on THD+N at lower frequencies, but its function is critical to the final result
b
of PSRR (with input grounded and in the lower frequency region), in the following manner:
●
If C is lower than 1µF, THD+N increases at lower frequencies and PSRR worsens.
b
21/30
Application Information
TS4984FC
●
If C is higher than 1µF, the benefit on THD+N at lower frequencies is small, but the benefit
b
to PSRR is substantial.
Note:
The TS4984FC has two BYPASS pins. C can be connected equally to pin C5 or to pin C1.
b
These pins are internally connected. Connecting pin C5 and pin C1 together by an external
wire is optional.
C has a non-negligible effect on PSRR at lower frequencies. The lower the value of C , the
in
in
higher the PSRR.
4.6
Wake-up time, twu
When the standby is released to put the device ON, the bypass capacitor C will not be charged
b
immediately. As C is directly linked to the bias of the amplifier, the bias will not work properly
b
until the C voltage is correct. The time required to reach this voltage is called the wake-up time
b
or t and specified in the tables in Chapter 3: Electrical Characteristics with C = 1µF.
wu
b
If C has a value other than 1µF, please refer to the graph in Figure 64 to establish the wake-up
b
time value.
Due to process tolerances, the maximum value of wake-up time could be establish by the graph
in Figure 65.
Figure 64. Typical wake-up time vs. C
Figure 65. Maximum wake-up time vs. C
b
b
600
Tamb=25°C
Tamb=25°C
600
500
400
300
200
100
0
Vcc=3.3V
500
400
300
200
100
0
Vcc=3.3V
Vcc=2.6V
Vcc=2.6V
Vcc=5V
Vcc=5V
1
2
3
4
0.1
4.7
0.1
1
2
3
4
4.7
Bypass Capacitor Cb ( F)
Bypass Capacitor Cb ( F)
Note:
Bypass capacitor C as also a tolerance of typically +/-20%. To calculate the wake-up time with
b
this tolerance, refer to the previous graph (considering for example for C = 1µF in the range of
b
0.8µF ≤ 1µF ≤ 1.2µF).
4.7
Shutdown time
When the standby command is set, the time required to put the two output stages in high
impedance and the internal circuitry in shutdown mode is a few microseconds.
Note:
In shutdown mode, Bypass pin and Vin- pin are short-circuited to ground by internal switches.
This allows for the quick discharge of the C and C capacitors.
b
in
22/30
TS4984FC
Application Information
4.8
Pop performance
Pop performance is intimately linked with the size of the input capacitor C and the bias voltage
in
bypass capacitor C .
b
The size of C is dependent on the lower cut-off frequency and PSRR values requested. The
in
size of C is dependent on THD+N and PSRR values requested at lower frequencies.
b
Moreover, C determines the speed with which the amplifier turns ON. In order to reach near
b
zero pop and click, the equivalent input constant time,
τ = (R + 2kΩ) x C (s) with R ≥ 5kΩ
in
in
in
in
must not reach the τ maximum value as indicated in the graph below in Figure 66.
in
Figure 66. τ max. versus bypass capacitor
in
Tamb=25°C
160
120
80
40
0
Vcc=3.3V
Vcc=2.6V
Vcc=5V
1
2
3
4
Bypass Capacitor Cb ( F)
By following the previous rules, the TS4984 can reach near zero pop and click even with high
gains such as 20dB.
Example calculation:
With R = 22kΩ and a 20Hz, -3dB lower cut-off frequency, C = 361nF.
in
in
So, C =390nF with standard value which gives a lower cut-off frequency equal to 18.5Hz.
in
In this case, (R + 2kΩ) x C = 9.36ms.
in
in
When referring to the previous graph, if C =1µF and V = 5V, we read 20 ms max.
b
CC
This value is twice as high as our current value, thus we can state that pop and click will be
reduced to its lowest value. Minimizing both C and the gain benefits both the pop phenomena,
in
and the cost and size of the application.
23/30
Application Information
TS4984FC
4.9
Application example: differential-input BTL power stereo
amplifier
The schematic in Figure 67 shows how to design the TS4984 to work in differential-input mode.
For this discussion, only the left-channel amplifier will be referred to.
Let:
R
C
= R = R , R = R = R
2L 1 2R 2L
1R
2
= C = C
in
inR
inL
The gain of the amplifier is:
R2
R1
-------
GVdif= 2
In order to reach the optimal performance of the differential function, R and R should be
1
2
matched at 1% maximum.
Figure 67. Differential input amplifier configuration
R2L
VCC
CinL
CinL
R1L
R1L
Neg. Input LEFT
Pos. Input LEFT
Cs
TS4984
IN-L
-
VO-L
IN+L
+
R2L
LEFT Speaker
8 Ohms
-
StandBy
BypassL
StandBy
Control
Bias
VO+L
AV = -1
+
R2R
R1R
CinR
CinR
Pos. Input RIGHT
Neg. Input RIGHT
IN+R
IN-R
+
-
VO-R
R1R
RIGHT Speaker
8 Ohms
-
AV = -1
VO+R
BypassR
+
Cb
R2R
The value of the input capacitor C can be calculated with the following formula, using the -3dB
in
lower frequency required (where F is the lower frequency required):
L
1
--------------------
Cin
≈
(F)
2πR1FL
24/30
TS4984FC
Note: This formula is true only if:
Application Information
1
---------------------------------------
FCB
=
(Hz)
2π(R1 + R2)Cb
is 5 times lower than F .
L
The following bill of materials is provided as an example of a differential amplifier with a gain of
2 and a -3dB lower cut-off frequency of about 80Hz.
Table 8.
Example of a bill of materials
Designator
Part Type
R
R
= R
= R
20kΩ / 1%
20kΩ / 1%
100nF
1L
2L
1R
2R
C
= C
inR
inL
C = C
1µF
b
s
U1
TS4984
4.10 Demoboard
A demoboard for the TS4984 in flip-chip package is available.
For more information about this demoboard, please refer to Application Note AN2153, which
can be found on www.st.com.
Figure 68 shows the component locations, and Figure 69 and Figure 70 show top layer and
bottom layers of the demoboard, respectively. Figure 71 shows a schematic of the demoboard
Figure 68. Component locations
25/30
Application Information
Figure 69. Top layer
TS4984FC
Figure 70. Bottom layer
26/30
TS4984FC
Figure 71. Demoboard schematic
Application Information
C2
1
2
2
R2
1
22K
VCC
Cn9
1
2
Vcc
GND
C7
1uF
C8
100nF
U1
TS4984_FC_ADAPTER
C1
Cn1
Cn3
R1
1
2
1
1
2
1
1
2
2
6
5
IN-L
neg.
GND
-
22K
VO-L
100nF
C3
2
4
Input L
R3
1
2
IN+L
pos.
GND
+
VCC
Cn7
1
2
3
Cn2
-
STDBY
7
2
1
neg.
pos.
Jumper J1
Bias
VO+L
3
AV = -1
OUTL
StandBy
+
C4
2
Cn4
Cn6
R4
1
2
1
1
1
1
2
2
13
14
IN-R
neg.
GND
-
22K
Cn5
100nF
C6
2
VO-R
11
2
1
neg.
pos.
OUTR
Input R
R6
1
2
IN+R
pos.
GND
+
-
R7
R8
VO+R
12
AV = -1
Bypass
Bypass
8
+
15
C9
1uF
R5
1
2
2
22K
C5
1
27/30
Package Mechanical Data
TS4984FC
5
Package Mechanical Data
Figure 72. Pinout (top view)
VCC
6
IN2+
IN2-
VCC
BYPASS
STDBY
5
4
VOUT2+
GND
VOUT1+
IN1+
VOUT2-
VOUT1-
3
2
1
IN1-
BYPASS
GND
Note: Balls are underneath
A
B
C
D
E
Figure 73. Marking (top view)
Marking shows:
■ ST Logo
Product & assembly code: XXX
E
■
- A84 from Tours
- 848 from Singapore
- 84K from Shenzhen
XXX
YWW
■ 3-digit datecode: YWW
■ “E” lead-free symbol
■ The dot marks position of pin A1
28/30
TS4984FC
Figure 74. Package mechanical data for 15-bump flip-chip
Package Mechanical Data
2.40 mm
■ Die size: 2.40 x 1.90 mm 30µm
■ Die height (including bumps): 600µm
0.25m
m
0.5mm
■ Back Coating height (optional):
1.90 mm
60µm 10µm
■ Bump Diameter: 315µm 50µm
■ Bump Diameter Before Reflow:
300µm 10µm
∅ 0.3mm
0.86mm
■ Bump Height: 250µm 40µm
■ Die Height: 350µm 20µm
■ Pitch: 500µm 50µm
60 µm Back coating *
600 µm
■ Coplanarity: 60µm max.
* Optional
Figure 75. Tape & Reel specification (top view)
1.5
4
1
1
A
A
8
Die size X + 70µm
4
All dimensions are in mm
User direction of feed
29/30
Revision History
TS4984FC
6
Revision History
Date
Revision
Changes
20 May 2005
1
Initial release.
Typical application schematic corrected see Figure 1: Application
information on page 2.
Nov. 2005
2
Change to layout of tables in Chapter 3: Electrical Characteristics on
page 4.
Minor grammatical and formatting changes throughout.
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is
granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are
subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products
are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
The ST logo is a registered trademark of STMicroelectronics.
All other names are the property of their respective owners
© 2005 STMicroelectronics - All rights reserved
STMicroelectronics group of companies
Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan -
Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America
www.st.com
30/30
相关型号：
©2020 ICPDF网 联系我们和版权申明