TSA1005I-40IF_技术文档

TSA1005

DUAL-CHANNEL, 10-BIT, 20/40MSPS A/D CONVERTER

■ 10-bit, dual-channel A/D converter in deep

submicron CMOS technology, 20/40Msps

■ Single supply voltage: 2.5V

PIN CONNECTIONS (top view)

Independent supply for CMOS output stage

with 2.5V/3.3V capability

index

corner

37

48 47 46 45 44 43 42 41 40 39 38

D0(LSB)

D1

■ ENOB=9.5 @ 20Msps, ENOB=9.2 @

1

36

35

AGND

INI

40Msps, Fin=10MHz

2

3

D2

34

■ SFDR typically up to 62.5dB @ 40Msps,

Fin=10MHz.

AGND

INIB

4

5

D3

D4

33

32

AGND

■ 1GHz analog bandwidth Track-and-Hold

■ Common clocking between channels

■ Multiplexed outputs

31

30

29

28

6

7

D5

IPOL

D6

AVCCB

TSA1005

D7

8

9

AGND

INQ

D8

DESCRIPTION

D9(MSB)

VCCBE

GNDBE

10

27

26

AGND

INBQ 11

AGND

The TSA1005 belongs to a new generation of high

speed, dual-channel Analog to Digital converters,

processed in a mainstream 0.25 µm CMOS tech-

nology and yielding high performances.

25

12

13 14 15 16 17 18 19 20 21 22 23 24

The TSA1005 is specifically designed for applica-

tions requiring a very low noise floor, high SFDR

and good isolation between channels. It is based

on a pipeline structure and digital error correction,

providing high static linearity at 20/40 Msp, and

Fin = 10 MHz.

BLOCK DIAGRAM

VCCBE

+2.5V/3.3V

SELECT OEB

CLK

For each channel, a voltage reference is integrat-

ed to simplify the design and minimize external

components. It is nevertheless possible to use the

circuit with external references.

Each ADC output is multiplexed on a common bus

with small number of pins. A tri-state capability is

available for the output signals, allowing for chip

selection. The input signals of the ADC must be

differentially driven.

Timing

VINI

10

AD 10

I channel

VINBI

VINCMI

common mode

VREFPI

REF I

VREFMI

10

D0

TO

D9

M

U

X

The TSA1005 is supports an extended (0 to

+85°C) temperature range, and is available in the

small 48-pin TQFP package.

Buffers

Polar.

IPOL

VREFPQ

VREFMQ

VINCMQ

REF Q

common mode

APPLICATIONS

VINQ

■ Medical imaging and ultrasound

■ I/Q signal processing applications

■ High speed data acquisition system

■ Portable instrumentation

AD 10

Q channel

10

VINBQ

GND

GNDBE

■ High resolution fax and scanners

ORDER CODE

PACKAGE

Temperature

Range

Part Number

Status

Conditioning

7 × 7 mm TQFP48

TSA1005-20IF

TSA1005-20IFT

TSA1005I-40IF

TSA1005-40IFT

-40°C to +85°C

0°C to +85°C

Sample

Tray

Tape & Reel

Tray

Production

Tape & Reel

EVAL1005-20/BA

EVAL1005-40/BA

Evaluation board

June 2003

1/22

TSA1005

ABSOLUTE MAXIMUM RATINGS

Symbol

Parameter

Values

Unit

(1)

AVCC

DVCC

0 to 3.3

0 to 3.6

V

Analog Supply voltage

1)

Digital Supply voltage

1)

VCCBE

Digital buffer Supply voltage

VCCBI

IDout

Tstg

0 to 3.3

-100 to 100

+150

V

Digital buffer Supply voltage

Digital output current

mA

°C

Storage temperature

(2)

HBM: Human Body Model

2

ESD

kV

(3)

1.5

CDM: Charged Device Model

(4)

Latch-up

A

Class

1

All voltage values, except for differential voltage, are with respect to the network ground terminal. The magnitude of input and output volt-

ages must not exceed -0.3 V or VCC

2

3

4

ElectroStatic Discharge pulse (ESD pulse) simulating a human body discharge of 100 pF through 1.5 kΩ

Discharge to Ground of a device that has been previously charged.

Corporate ST Microelectronics procedure number 0018695

OPERATING CONDITIONS

(1)

TSA1005-40

Typ.

TSA1005-20

Symbol

Parameter

Min.

Typ.

Max.

Min.

Max.

Unit

AVCC

DVCC

Analog Supply voltage

2.25

2.5

2.7

3.5

2.7

2.25

2.5

2.7

3.5

2.7

V

Digital Supply voltage

VCCBE

VCCBI

External Digital buffer Supply voltage

Internal Digital buffer Supply voltage

VREFPI

VREFPQ

VREFMI

VREFMQ

INCMI

Forced top voltage reference

0.94

0

1.4

0.4

1

0.94

0

1.4

0.4

1

V

Forced bottom reference voltage

Forced input common mode voltage

0.2

INCMQ

2/22

TSA1005

PIN CONNECTIONS (top view)

index

corner

37

48 47 46 45 44 43 42 41 40 39 38

D0(LSB)

D1

1

36

35

AGND

INI

2

3

D2

34

AGND

INIB

4

5

D3

D4

33

32

AGND

31

30

29

28

6

7

D5

IPOL

D6

AVCCB

AGND

INQ

TSA1005

D7

8

9

D8

D9(MSB)

VCCBE

GNDBE

10

AGND

27

26

INBQ 11

AGND

25

12

13 14 15 16 17 18 19 20 21 22 23 24

PIN DESCRIPTION

Pin No

Name

Description

Analog ground

Observation

Pin No

Name

Description

Observation

1

2

AGND

INI

0V

25

26

27

28

29

30

31

32

33

34

35

36

37

38

GNDBE Digital buffer ground

0V

2.5V/3.3V

I channel analog input

Analog ground

VCCBE Digital Buffer power supply

D9(MSB) Most Significant Bit output

3

AGND

INBI

CMOS output (2.5V/3.3V)

4

I channel inverted analog input

Analog ground

D8

D7

D6

D5

D4

D3

D2

D1

Digital output

5

AGND

IPOL

AVCC

AGND

INQ

6

Analog bias current input

Analog power supply

Analog ground

7

2.5V

0V

8

9

Q channel analog input

Analog ground

10

11

12

13

14

AGND

INBQ

AGND

0V

Q channel inverted analog input

Analog ground

D0(LSB) Least Significant Bit output

REFPQ Q channel top reference voltage

NC

Non connected

REFMQ Q channel bottom reference

voltage

15

INCMQ Q channel input common mode

39

VCCBE Digital Buffer power supply

GNDBE Digital buffer ground

2.5V/3.3V - See Application

Note

16

17

18

19

20

21

22

23

24

AGND

AVCC

DVCC

DGND

CLK

Analog ground

0V

40

41

42

43

44

45

46

47

48

0V

Analog power supply

Digital power supply

Digital ground

2.5V

VCCBI

OEB

Digital Buffer power supply

Digital Power Supply

2.5V

0V

Output Enable input

2.5V/3.3V CMOS input

Clock input

2.5V CMOS input

AVCC

INCMI

REFMI

REFPI

Analog power supply

2.5V

SELECT Channel selection

2.5V CMOS input

Analog power supply

DGND

DVCC

Digital ground

0V

I channel input common mode

Digital power supply

2.5V

0V

I channel bottom reference voltage 0V

I channel top reference voltage

GNDBI Digital buffer ground

3/22

TSA1005

ELECTRICAL CHARACTERISTICS

AVCC = DVCC = VCCB = 2.5 V, Fs = 20/40 Msps, Fin = 10.13 MHz, Vin@ -1 dBFS, VREFP = 0.8 V,

VREFM = 0 V

Tamb = 25°C (unless otherwise specified)

TIMING CHARACTERISTICS

(1)

TSA1005-40

Typ.

TSA1005-20

Symbol

Parameter.

Min.

0.5

Typ.

Max.

Min.

Max.

Unit

FS

DC

Sampling Frequency

20

0.5

45

40

55

MHz

%

Clock Duty Cycle

50

25

50

TC1

TC2

Clock pulse width (high)

Clock pulse width (low)

12.5

ns

Data Output Delay (Clock edge to Data

Valid) - 10pF load capacitance

Tod

5

ns

Tpd I

Data Pipeline delay for I channel

Data Pipeline delay for Q channel

7

cycles

Tpd Q

7.5

Falling edge of OEB to digital output

valid data

Ton

Toff

1

ns

Rising edge of OEB to digital output

tri-state

1

Preliminary data.

TIMING DIAGRAM

Simultaneous sampling

on I/Q channels

N+4

N+5

N+13

N+3

N+6

N+12

I

N+11

N+7

N+2

N-1

N

N+1

N+8

N+10

N+9

Q

CLK

Tpd I + Tod

Tod

SELECT

CLOCK AND SELECT CONNECTED TOGETHER

OEB

sample N-6

Q channel

sample N+2

Q channel

sample N+1

Q channel

sample N-8

I channel

sample N

Q channel

DATA

OUTPUT

sample N-9

I channel

sample N-7

Q channel

sample N+3

I channel

sample N+1

I channel

sample N+2

I channel

4/22

TSA1005

CONDITIONS

AVCC = DVCC = VCCB = 2.5V, Fs= 20/40Msps, Fin=2MHz, Vin@ -1dBFS, VREFM=0V

Tamb = 25°C (unless otherwise specified)

ANALOG INPUTS

(1)

TSA1005-40

Typ.

TSA1005-20

Symbol

Parameter

Min.

1.1

Typ.

Max.

Min.

Max.

Unit

VIN-VINB Full scale reference voltage

2.0

7.0

3.3

2.8

1.1

2.0

7

2.8

Vpp

pF

Cin

Input capacitance

Req

Equivalent input resistor

Analog Input Bandwidth

Vin Full scale, Fs max

Effective Resolution Bandwidth

1.6

KΩ

BW

1000

70

1000

70

MHz

ERB

1

Preliminary data

DIGITAL INPUTS AND OUTPUTS

Symbol

Parameter

Test conditions

Min

Typ

Max

Unit

Clock and Select inputs

VIL

VIH

Logic "0" voltage

Logic "1" voltage

0

0.8

V

2.0

2.5

OEB input

0.25 x

VCCBE

VIL

Logic "0" voltage

Logic "1" voltage

0

V

0.75 x

VCCBE

VIH

VCCBE

Digital Outputs

VOL

VOH

IOZ

Iol=10µA

Ioh=10µA

0.1 x

VCCBE

Logic "0" voltage

0

V

0.9 x

VCCBE

-1.67

Logic "1" voltage

VCCBE

0

High Impedance leakage current OEB set to VIH

Output Load Capacitance

1.67

15

µA

pF

C

L

REFERENCE VOLTAGE

(1)

TSA1005-40

Typ.

TSA1005-20

Symbol

Parameter

Min.

Typ.

Max.

Min.

Max.

Unit

VREFPI

Top internal reference voltage

Input common mode voltage

0.81

0.41

0.88

0.94

0.81

0.88

0.46

0.94

V

VREFPQ

VINCMI

0.46

0.50

0.41

0.50

V

VINCMQ

5/22

TSA1005

CONDITIONS

AVCC = DVCC = VCCB = 2.5V, Fs= 20/40Msps, Fin=2MHz, Vin@ -1dBFS, VREFP=0.8V, VREFM=0V

Tamb = 25°C (unless otherwise specified)

POWER CONSUMPTION

(1)

TSA1005-40

Typ.

TSA1005-20

Symbol

Parameter

Min.

Typ.

Max.

Min.

Max.

Unit

ICCA

ICCD

Analog Supply current

Digital Supply Current

30

4

69.5

3.5

72.8

3.6

mA

Digital Buffer Supply Current (10pF

load)

ICCBE

ICCBI

Pd

6

6.5

131

199.5

80

6.9

149

mA

uA

Digital Buffer Supply Current

274

100

80

Power consumption in normal opera-

tion mode

207.7

mW

°C/W

Rthja

Thermal resistance (TQFP48)

ACCURACY

Symbol

(1)

TSA1005-40

Typ.

TSA1005-20

Parameter

Min.

Typ.

Max.

Min.

Max.

Unit

OE

GE

DNL

INL

-

Offset Error

2.97

0.1

2.97

0.1

LSB

%

Gain Error

Differential Non Linearity

Integral Non Linearity

Monotonicity and no missing codes

±0.5

±0.6

±1

LSB

±0.7

Guaranteed

DYNAMIC CHARACTERISTICS

(1)

TSA1005-40

TSA1005-20

Symbol

Min.

Typ.

Max.

Min.

Typ.

Max.

Unit

Spurious Free Dynamic Range

Signal to Noise Ratio

-73

60

-62.6

59.8

-62

-58.1

dBc

dB

SFDR

57.1

SNR

Total Harmonics Distortion

Signal to Noise and Distortion Ratio

Effective number of bits

-73

59

-57.5

dBc

dB

THD

54.9

8.8

57.3

9.2

SINAD

ENOB

9.5

bits

MATCHING BETWEEN CHANNELS

(1)

TSA1005-40

Typ.

TSA1005-20

Symbol

Parameter

Min.

Typ.

Max.

Min.

Max.

Unit

GM

OM

Gain match

Offset match

Phase match

0.04

0.5

1

0.04

0.5

1

%

LSB

dg

PHM

XTLK

Crosstalk rejection

85

dB

1

Preliminary data

6/22

TSA1005

Static parameter: Integral Non Linearity

Fs=20MSPS; Icca=30mA; Fin=10MHz

1

0.8

0.6

0.4

0.2

0

-0.2

-0.4

-0.6

-0.8

-1

0

200

400

600

800

1000

Output Code

Static parameter: Integral Non Linearity

Fs=40MSPS; Icca=45mA; Fin=10MHz

2

1.5

1

0.5

0

-0.5

-1

-1.5

-2

0

200

400

600

800

1000

Output Code

Static parameter: Differential Non Linearity

Fs=20MSPS; Icca=30mA; Fin=10MHz

1

0.8

0.6

0.4

0.2

0

-0.2

-0.4

-0.6

-0.8

-1

0

200

400

600

800

1000

Output Code

7/22

TSA1005

Static parameter: Differential Non Linearity

Fs=40MSPS; Icca=45mA; Fin=10MHz

1

0.8

0.6

0.4

0.2

0

-0.2

-0.4

-0.6

-0.8

-1

0

200

400

600

800

1000

Output Code

Linearity vs. Fin

Fs=20MHz; Icca=30mA

Distortion vs. Fin

Fs=20MHz; Icca=30mA

0

-20

-40

100

90

12

11

10

9

ENOB_Q

ENOB_I

80

70

60

50

40

30

SFDR_I

THD_I

-60

SNR_Q

SINAD_Q

-80

8

-100

-120

-140

THD_Q

7

SFDR_Q

SNR_I

SINAD_I

20

6

5

0

20

40

60

0

40

60

Fin (MHz)

Linearity vs. Fin

Fs=40MHz; Icca=45mA

Distortion vs. Fin

Fs=40MHz; Icca=45mA

100

90

10

9

0

-20

-40

ENOB_Q

SNR_Q

ENOB_I

80

8

THD_I

SFDR_I

70

60

50

SINAD_Q

7

-60

-80

6

SFDR_Q

THD_Q

SNR_I

SINAD_I

20

-100

-120

5

40

30

4

0

20

40

60

0

40

60

Fin (MHz)

8/22

TSA1005

Linearity vs. AVCC

Fs=20MSPS; Icca=30mA; Fin=5MHz

Distortion vs. AVCC

Fs=20MSPS; Icca=30mA; Fin=5MHz

-30

-40

-50

80

10

9.8

9.6

9.4

9.2

9

75

70

65

60

55

50

ENOB_I

ENOB_Q

SFDR_Q

THD_Q

-60

-70

SNR_Q

SINAD_Q

-80

8.8

8.6

8.4

8.2

8

-90

THD_I

2.35

SFDR_I

-100

-110

-120

SINAD_I

SNR_I

2.25

2.45

2.55

2.65

2.25

2.35

2.45

2.55

2.65

AVCC (V)

Distortion vs. AVCC

Linearity vs. AVCC

Fs=40MSPS; Icca=45mA; Fin=5MHz

-30

-40

-50

100

90

10

9.5

9

SFDR_Q

THD_Q

ENOB_Q ENOB_I

80

8.5

8

-60

-70

70

7.5

7

SFDR_I

-80

SNR_Q

SINAD_Q

SNR_I

-90

60

50

40

THD_I

6.5

6

-100

-110

-120

SINAD_I

2.35

5.5

5

2.25

2.35

2.45

2.55

2.65

2.25

2.45

2.55

2.65

AVCC (V)

Linearity vs. DVCC

Fs=20MSPS; Icca=30mA; Fin=10MHz

Distortion vs. DVCC

Fs=20MSPS; Icca=30mA; Fin=10MHz

-40

-50

80

75

10

9.8

9.6

9.4

9.2

9

ENOB_Q

ENOB_I

THD_Q

SFDR_Q

-60

-70

70

65

60

55

50

-80

SNR_Q

SNR_I

8.8

8.6

8.4

8.2

8

-90

THD_I

SFDR_I

-100

-110

-120

SINAD_I

SINAD_Q

2.55

2.25

2.35

2.45

2.55

2.65

2.25

2.35

2.45

2.65

DVCC (V)

9/22

TSA1005

Linearity vs. DVCC

Fs=40MSPS; Icca=45mA; Fin=10MHz

Distortion vs. DVCC

Fs=40MSPS; Icca=45mA; Fin=10MHz

0

-20

-40

100

10

9.5

9

90

80

70

60

50

40

ENOB_Q

ENOB_I

8.5

8

SFDR_I

SFDR_Q

-60

-80

7.5

7

SINAD_Q

SNR_Q

6.5

6

THD_I

THD_Q

SNR_I

-100

SINAD_I

5.5

5

-120

2.25

2.35

2.45

2.55

2.65

2.25

2.35

2.45

2.55

2.65

DVCC (V)

Linearity vs. VCCBI

Fs=20MSPS; Icca=30mA; Fin=10MHz

Distortion vs. VCCBI

Fs=20MSPS; Icca=30mA; Fin=10MHz

-40

90

85

10

9.8

9.6

9.4

9.2

9

-50

THD_Q

ENOB_I ENOB_Q

80

-60

-70

SFDR_Q

75

70

-80

8.8

8.6

8.4

8.2

8

-90

SNR_Q

65

60

55

50

SFDR_I

SNR_I

THD_I

-100

-110

-120

SINAD_I

SINAD_Q

2.25

2.35

2.45

2.55

2.25

2.35

2.45

2.55

2.65

VCCBI (V)

Linearity vs. VCCBI

Fs=40MSPS; Icca=45mA; Fin=10MHz

Distortion vs. VCCBI

Fs=40MSPS; Icca=45mA; Fin=10MHz

-40

90

10

9.5

9

-50

85

THD_Q

ENOB_Q

-60

-70

SFDR_Q

ENOB_I

80

8.5

8

75

-80

70

7.5

7

-90

SINAD_Q

THD_I

SNR_Q

65

60

55

50

SFDR_I

6.5

6

-100

-110

-120

SINAD_I

2.35

5.5

5

SNR_I

2.25

2.35

2.45

2.55

2.25

2.45

2.55

2.65

VCCBI (V)

10/22

TSA1005

Linearity vs. VCCBE

Fs=20MSPS; Icca=30mA; Fin=10MHz

Distortion vs. VCCBE

Fs=20MSPS; Icca=30mA; Fin=10MHz

-60

90

85

10

9.8

9.6

9.4

9.2

9

THD_Q

SFDR_Q

-65

-70

-75

-80

-85

-90

-95

-100

ENOB_I

ENOB_Q

80

75

70

65

60

55

50

8.8

8.6

8.4

8.2

8

THD_I

SNR_I

SINAD_I

SFDR_I

SNR_Q

SINAD_Q

1.8

2.3

2.8

3.3

1.8

2.3

2.8

3.3

VCCBE (V)

Linearity vs. VCCBE

Fs=40MSPS; Icca=45mA; Fin=10MHz

Distortion vs. VCCBE

Fs=40MSPS; Icca=45mA; Fin=10MHz

-30

-40

90

85

80

10

9.8

9.6

9.4

9.2

9

-50

-60

SFDR_Q

THD_Q

ENOB_Q

ENOB_I

75

70

-70

-80

8.8

8.6

8.4

8.2

8

65

THD_I

SNR_I

-90

SFDR_I

SINAD_I

60

-100

-110

-120

SINAD_Q

3.25

55

50

SNR_Q

2.25

2.75

3.25

2.25

2.75

VCCBE (V)

Linearity vs. Duty Cycle

Fs=20MHz; Icca=30mA; Fin=5MHz

Distortion vs. Duty Cycle

Fs=20MHz; Icca=30mA; Fin=5MHz

-40

90

10

9.5

9

-50

85

ENOB_I

SFDR_Q

ENOB_Q

-60

80

75

70

65

60

55

50

THD_Q

-70

-80

8.5

8

SINAD_I

SFDR_I

-90

-100

-110

-120

SNR_I

THD_I

7.5

7

SINAD_Q

53

SNR_Q

45

47

49

51

55

45

47

49

51

53

55

Positive Duty Cycle (%)

11/22

TSA1005

Linearity vs. Duty Cycle

Fs=40MHz; Icca=45mA; Fin=5MHz

Distortion vs. Duty Cycle

Fs=40MHz; Icca=45mA; Fin=5MHz

100

10

9.5

9

-40

-50

SFDR

90

ENOB

-60

-70

8.5

8

80

70

7.5

7

-80

SNR

SINAD

THD

-90

-100

-110

-120

60

50

40

6.5

6

5.5

5

45

47

49

51

53

55

45

47

49

51

53

55

Positive Duty Cycle (%)

Single-tone 8K FFT at 24.8Msps - Q Channel

Fin=10MHz; Icca=30mA, Vin@-1dBFS

0

-20

-40

-60

-80

-100

-120

-140

2

4

6

8

10

12

Frequency (MHz)

Single-tone 8K FFT at 39.7Msps - Q Channel

Fin=10MHz; Icca=45mA, Vin@-1dBFS

0

-20

-40

-60

-80

-100

-120

-140

2

4

6

8

10

12

14

16

18

20

Frequency (MHz)

12/22

TSA1005

DEFINITIONS OF SPECIFIED PARAMETERS

STATIC PARAMETERS

components in the Nyquist band (f /2) excluding

DC, fundamental and the first five harmonics.

SNR is reported in dB.

s

Static measurements are performed using a

histogram method with on a 2 MHz input signal,

sampled at 40 Msps, which is high enough to fully

characterize the test frequency response. An

input level of +1 dBFS is required to saturate the

signal.

Signal to Noise and Distortion Ratio (SINAD)

Similar ratio as for SNR but including the

harmonic distortion components in the noise

figure (not DC signal). It is expressed in dB.

Differential Non Linearity (DNL)

The average deviation of any output code width

from the ideal code width of 1 LSB.

From the SINAD, the Effective Number of Bits

(ENOB) can easily be deduced using the formula:

SINAD= 6.02 × ENOB + 1.76 dB.

Integral Non linearity (INL)

An ideal converter presents a transfer function as

When the applied signal is not Full Scale (FS), but

being the straight line from the starting code to the

ending code. The INL is the deviation for each

transition from this ideal curve.

has an A amplitude, the SINAD expression

0

becomes:

SINAD

= SINAD

+ 20 log (2A /FS)

2Ao

Full Scale 0

DYNAMIC PARAMETERS

Dynamic measurements are performed by

spectral analysis, applied to an input sine wave of

various frequencies and sampled at 40 Msps.

SINAD = 6.02 ×ENOB + 1.76dB + 20 log (2A /FS)

2Ao 0

The ENOB is expressed in bits.

The input level is -1 dBFS to measure the linear

behavior of the converter. All the parameters are

given without correction for the full scale

amplitude performance except the calculated

ENOB parameter.

Analog Input Bandwidth

The maximum analog input frequency at which

the spectral response of a full power signal is

reduced by 3 dB. Higher values can be achieved

with smaller input levels.

Spurious Free Dynamic Range (SFDR)

Effective Resolution Bandwidth (ERB)

The band of input signal frequencies that the ADC

is intended to convert without loosing linearity i.e.

the maximum analog input frequency at which the

SINAD is decreased by 3dB or the ENOB by 1/2

bit.

The ratio between the power of the worst spurious

signal (not always an harmonic) and the

amplitude of fundamental tone (signal power)

over the full Nyquist band. It is expressed in dBc.

Total Harmonic Distortion (THD)

The ratio of the rms sum of the first five harmonic

distortion components to the rms value of the

fundamental line. It is expressed in dB.

Pipeline delay

Delay between the initial sample of the analog

input and the availability of the corresponding

digital data output, on the output bus. Also called

data latency. It is expressed as a number of clock

cycles.

Signal to Noise Ratio (SNR)

The ratio of the rms value of the fundamental

component to the rms sum of all other spectral

13/22

TSA1005 APPLICATION NOTE

DETAILED INFORMATION

The TSA1005 is a dual-channel, 10-bit resolution

analog to digital converter based on a pipeline

structure and the latest deep sub micron CMOS

process to achieve the best performances in

terms of linearity and power consumption.

Each channel achieves 10-bit resolution through

the pipeline structure. A latency time of 7 clock pe-

riods is necessary to obtain the digitized data on

the output bus.

and enables to keep the same package as single

channel ADC like TSA1002.

The selection of the channel information is done

through the "SELECT" pin. When set to high level

(VIH), the I channel data are present on the bus

D0-D9. When set to low level (VIL), the Q channel

data are on the output bus D0-D9.

The input signals are simultaneously sampled on

both channels on the rising edge of the clock. The

output data is valid on the rising edge of the clock

for I channel and on the falling edge of the clock

for Q channel. The digital data out from the differ-

ent stages must be time delayed depending on

their order of conversion. Then a digital data cor-

rection completes the processing and ensures the

validity of the ending codes on the output bus.

The structure has been specifically designed to

accept differential signals.

Connecting SELECT to CLK allows I and Q chan-

nels to be simultaneously present on D0-D9; I

channel on the rising edge of the clock and Q

channel on the falling edge of the clock. (see tim-

ing diagram page 2).

REFERENCES AND COMMON MODE

CONNECTION

VREFM must be always connected externally.

The TSA1005 is pin to pin compatible with the

dual 12bits/20Msps TSA1204 and the dual 12bits/

40Msps TSA1203.

Internal reference and common mode

COMPLEMENTARY FUNCTIONS

In the default configuration, the ADC operates with

its own reference and common mode voltages

generated by its internal bandgap. VREFM pins

are connected externally to the Analog Ground

while VREFP (respectively INCM) are set to their

internal voltage of 0.88V (respectively 0.46V). It is

recommended to decouple the VREFP and INCM

in order to minimize low and high frequency noise

(refer to Figure 1)

Some functionalities have been added in order to

simplify as much as possible the application

board. These operational modes are described as

followed.

Output Enable (OEB)

When set to low level (VIL), all digital outputs

remain active and are in low impedance state.

When set to high level (VIH), all digital outputs

buffers are in high impedance state while the

converter goes on sampling. When OEB is set to a

low level again, the data are then present on the

output with a very short Ton delay.

Figure 1: Internal reference and common mode

setting

Therefore, this allows the chip select of the device.

The timing diagram summarizes this functionality.

In order to remain in the normal operating mode,

this pin should be grounded through a low value of

resistor.

330pF 10nF 4.7uF

VREFP

VIN

TSA1005

INCM

330pF 10nF 4.7uF

VINB

SELECT

VREFM

The digital data out from each ADC core are mul-

tiplexed together to share the same output bus.

This prevents from increasing the number of pins

14/22

TSA1005

External reference and common mode

1:4) to reduce the driving requirement on the

analog signal source.

Each of the voltages VREFP and INCM can be

fixed externally to better fit to the application

Each analog input can drive a 1.4Vpp amplitude

input signal, so the resultant differential amplitude

is 2.8Vpp.

needs

(Refer

to

table

’OPERATING

CONDITIONS’ page 4 for min/max values).

The VREFP, VREFM voltages set the analog

dynamic at the input of the converter that has a full

scale amplitude of 2*(VREFP-VREFM). Using

internal references, the dynamic range is 1.8V.

The INCM is the mid voltage of the analog input

signal.

Figure 3: Differential input configuration with

transformer

ADT1-1

Analog source

1:1

It is possible to use an external reference voltage

device for specific applications requiring even

VIN

TSA1005

50Ω

33pF

I or Q ch.

better

linearity,

accuracy

or

enhanced

VINB

temperature behavior.

INCM

Using the STMicroelectronics TS821 or

TS4041-1.2 Vref leads to optimum performances

when configured as shown on Figure 2.

330pF

10nF

470nF

Figure 2: External reference setting

1k

Ω

Figure 4 represents the biasing of a differential

input signal in AC-coupled differential input

configuration. Both inputs VIN and VINB are

centered around the common mode voltage, that

can be let internal or fixed externally.

330pF 10nF 4.7uF

VCCA VREFP

VIN

TSA1005

TS821

TS4041

external

reference

VINB

VREFM

Figure 4: AC-coupled differential input

VIN

DRIVING THE DIFFERENTIAL ANALOG

INPUTS

10nF

50Ω

100kΩ

TSA1005

33pF

INCM

common

The TSA1005 has been designed to obtain

optimum performances when being differentially

driven. An RF transformer is a good way to

achieve such performances.

mode

100kΩ

VINB

10nF

50Ω

Figure 3 describes the schematics. The input

signal is fed to the primary of the transformer,

while the secondary drives both ADC inputs. The

common mode voltage of the ADC (INCM) is

connected to the center-tap of the secondary of

the transformer in order to bias the input signal

around this common voltage, internally set to

0.46V. It determines the DC component of the

analog signal. As being an high impedance input,

it acts as an I/O and can be externally driven to

adjust this DC component. The INCM is

decoupled to maintain a low noise level on this

node. Our evaluation board is mounted with a 1:1

ADT1-1WT transformer from Minicircuits. You

might also use a higher impedance ratio (1:2 or

Figure 5: AC-coupled Single-ended input

Signal source

10nF

VIN

100kΩ

50Ω

TSA1005

INCM

33pF

100kΩ

VINB

15/22

TSA1005

Clock input

APPLICATION

The TSA1005 performance is very dependant on

your clock input accuracy, in terms of aperture

jitter; the use of low jitter crystal controlled

oscillator is recommended.

Layout precautions

To use the ADC circuits in the best manner at high

frequencies, some precautions have to be taken

for power supplies:

- First of all, the implementation of 4 separate

proper supplies and ground planes (analog,

digital, internal and external buffer ones) on the

PCB is recommended for high speed circuit

applications to provide low inductance and low

resistance common return.

The separation of the analog signal from the

digital part is mandatory to prevent noise from

coupling onto the input signal. The best

compromise is to connect from one part AGND,

DGND, GNDBI in a common point whereas

GNDBE must be isolated. Similarly, the power

supplies AVCC, DVCC and VCCBI must be

separated from the VCCBE one.

- Power supply bypass capacitors must be placed

as close as possible to the IC pins in order to

improve high frequency bypassing and reduce

harmonic distortion.

- Proper termination of all inputs and outputs must

be incorporated with output termination resistors;

then the amplifier load will be only resistive and

the stability of the amplifier will be improved. All

leads must be wide and as short as possible

especially for the analog input in order to decrease

parasitic capacitance and inductance.

The duty cycle must be between 45% and 55%.

The clock power supplies must be separated from

the ADC output ones to avoid digital noise

modulation at the output.

It is recommended to always keep the circuit

clocked, even at the lowest specified sampling

frequency of 0.5Msps, before applying the supply

voltages.

Power consumption

So as to optimize both performance and power

consumption of the TSA1005 according the

sampling frequency, a resistor is placed between

IPOL and the analog Ground pins. Therefore, the

total dissipation is adjustable from 5Msps up to

40Msps.

The TSA1005 will combine highest performances

and lowest consumption at 20Msps when Rpol is

equal to 70kΩ, at 40Msps when Rpol is equal to

35kΩ. These values are nevertheless dependant

on application and environment.

At lower sampling frequency range, this value of

resistor may be adjusted in order to decrease the

analog current without any degradation of

dynamic performances.

- To keep the capacitive loading as low as

possible at digital outputs, short lead lengths of

routing are essential to minimize currents when

the output changes. To minimize this output

capacitance, buffers or latches close to the output

pins will relax this constraint.

The figure 6 sums up the relevant data.

- Choose component sizes as small as possible

(SMD).

Figure 6: analog current consumption

optimization depending on Rpol value

Digital Interface application

100

90

80

70

60

50

40

30

20

10

0

250

200

150

100

50

Thanks to its wide external buffer power supply

range, the TSA1005 is perfectly suitable to plug in

to 2.5V low voltage DSPs or digital interfaces as

well as to 3.3V ones.

ICCA

Medical Imaging application

Driven by the demand of the applications requiring

nowadays either portability or high degree of par-

allelism (or both), this product has been devel-

oped to satisfy medical imaging, and telecom in-

frastructures needs.

As a typical system diagram shows figure 10, a

narrow input beam of acoustic energy is sent into

a living body via the transducer and the energy re-

flected back is analyzed.

RPOL

25

0

5

15

35

45

55

Fs (MHz)

16/22

TSA1005

Figure 7: Medical imaging application

noise and very high linearity are mandatory fac-

tors.

These applications need high speed, low power

and high performance ADCs. 10-12 bit resolution

is necessary to lower the quantification noise. As

multiple channels are used, a dual converter is a

must for room saving issues.

HV TX amps

TX

The input signal is in the range of 2 to 20MHz

(mainly 2 to 7MHz) and the application uses most-

ly a 4 over-sampling ratio for Spurious Free Dy-

namic Range (SFDR) optimization.

The next RX beam former and processing blocks

enable the analysis of the outputs channels ver-

sus the input beam.

Mux

AD

RX

and

TGC amplifier

Proces

EVAL1005/BA evaluation board

The EVAL1005/BA is a 4-layer board with high

decoupling and grounding level. The schematic of

the evaluation board is reported figure 11 and its

top overlay view figure 10.The characterization of

the board has been made with a fully ADC

devoted test bench as shown on Figure 8. The

analog input signal must be filtered to be very

pure.

The dataready signal is the acquisition clock of the

logic analyzer.

The ADC digital outputs are latched by the octal

buffers 74LCX573.

The transducer is a piezoelectric ceramic such as

zirconium titanate. The whole array can reach up

to 512 channels.

The TX beam former, amplified by the HV TX

amps, delivers up to 100V amplitude excitation

pulses with phase and amplitude shifts.

The mux and T/R switch is a two way input signal

transmitter/ output receiver.

To compensate for skin and tissues attenuation

effects, The Time Gain Compensation (TGC) am-

plifier is an exponential amplifier that enables the

amplification of low voltage signals to the ADC in-

put range. Differential output structure with low

All characterization measurements have been

made with:

- SFSR=1dB for static parameters.

- SFSR=-1dB for dynamic parameters.

Figure 8: Analog to Digital Converter characterization bench

HP8644

Data

Vin

ADC

evaluation

Sine Wave

Generator

Logic

PC

Clk

Pulse

HP8133

HP8644

Sine Wave

Generator

17/22

TSA1005

Operating conditions of the evaluation board:

Find below the connections to the board for the

power supplies and other pins:

Grounding consideration

So as to better reject noise on the board, connect

on the bottom overlay AG (AGND), DG(DGND),

GB1(GNDBI) together from one part, and

GB2(GNDBE) with GB3(GNDB3) from the other

part.

board

internal

external

connection

voltage (V)

notation

2.5

AV

AG

AVCC

AGND

Mode select

0

0.94 to 1.4

0 to 0.4

0.2 to 1

0.94 to 1.4

0 to 0.4

0.2 to 1

2.5

So as to evaluate a single channel or the dual

ones, you have to connect on the board the

relevant position for the SELECT pin.

With the strap connected:

- to the upper connectors, the I channel at the out-

put is selected.

- horizontally, the Q channel at the output is se-

lected.

- to the lower connectors, both channels are se-

lected, relative to the clock edge.

0.88

RPI

REFPI

REFMI

INCMI

RMI

CMI

RPQ

RMQ

CMQ

DV

0.46

0.88

REFPQ

REFMQ

INCMQ

DVCC

0.46

Figure 9: mode select

0

DG

DGND

GNDBI

VCCBI

GNDBE

VCCBE

GNDB3

VCCB3

SELECT

0

GB1

VB1

GB2

VB2

GB3

VB3

I channel

2.5

SELECT

0

Q channel

2.5/3.3

0

I/Q channels

CLK

DGND DVCC

2.5

schematic

board

Care should be taken for the evaluation board

considering the fact that the outputs of the con-

verter are 2.5V/3.3V (VB2) tolerant whereas the

74LCX573 external buffers are operating up to

2.5V.

The ADC outputs on the connector J6 are D11

(MSB) to D2 (LSB).

Consumption adjustment

Before any characterization, care should be taken

to adjust the Rpol (Raj1) and therefore Ipol value

in function of your sampling frequency.

Single and Differential Inputs:

The ADC board components are mounted to test

the TSA1005 with single analog input; the

ADT1-1WT transformer enables the differential

drive into the converter; in this configuration, the

resistors RSI6, RSI7, RSI8 for I channel (respec-

tively RSQ6, RSQ7, RSQ8 for Q one) are con-

nected as short circuits whereas RSI5, RSI9 (re-

spectively RSQ5, RSQ9) are open circuits.

The other way is to test it via JI1 and JI1B differen-

tial inputs. So, the resistances RSI5, RSI9 for I

channel (respectively RSQ5, RSQ9 for Q one) are

connected as short circuits whereas RSI6, RSI7,

RSI8 (respectively RSQ6, RSQ7, RSQ8 for Q

one) are open circuits.

18/22

TSA1005

Figure 10: Printed circuit of evaluation board.

19/22

TSA1005

Figure 11: TSA1005 Evaluation board schematic

+

3

2

1

V c c B

n d G B

V c c B

n d G B

V c c B

n d G B

+

N C

C C V B E

G N D B

C C V B I

O E

I

G N D B

D V C

D G N D

E S L E C

K C L

D G N D

D V C

A V C

3 7

3 8

3 9

4 0

4 1

4 2

4 3

4 4

4 5

4 6

4 7

4 8

2 4

C

2 3

2 2

2 1

2 0

1 9

1 8

1 7

1 6

1 5

1 4

1 3

+

E

T

B

C

A V C

A G N D

I

M C I N

M F R E

F P E I R

Q M C I N

Q M F R E

F P E Q R

N D

C C

+

M C I N

M F R E

P F R E

M C I N

M F R E

P F R E

20/22

TSA1005

Figure 12: Printed circuit board - List of components

Name

Footprint Name

Footprint Name Part

Type

Footprint

Part

Type

0

47

Part

Type

10nF

RSQ6

RSQ7

RSQ8

RSI6

RSI7

RSI8

R3

R5

RQ19

RI1

805

603

CD2

C40

C39

603

C26

C20

C33

C25

CI1

CQ1

C34

C42

C35

C44

C36

C32

C37

330pF 603

33pF 603

47µF RB.1

470nF 805

CQ6

CI6

U2

U3

U1

NC

74LCX573

STG719

805

TSSOP20

SOT23-6

CQ12 10nF

CQ9

C52

C18

C21

C4

C15

C27

C11

CI9

10nF

JA

ANALOGIC connector

J17

J25

J4

J27

J26

JD

BUFPOW

CKDATA

CLK

CON2

DIGITAL

InI

connector

SMA

SIP2

connector

SMA

RQ1

RI19 47

RSI9 0NC 805

JI1

0NC

RSQ5

RSQ9

RSI5

R24

R23

R21

R22

R2

805

CI12

CI31

CQ31 10nF

CQ10 470nF 805

C28

CI10

JI1B

JQ1

JQ1B InQB

InIB

InQ

470nF 805

CQ30 330pF 603

CQ32 470nF 805

CQ13 470nF 805

SW1 SWITCH

connector

CI11

C51

C2

330pF 603

S5

S4

SW-SPST

0NC 805

CI32

C13

C53

C16

C3

C22

CI13

C38

CD1

C19

470nF 805

TI2

TQ2

JI2

JQ2

J6

T2-AT1-1WT ADT

VREFI

VREFQ

32Pin

1K

603

VR5

trimmer

1210

C17

CD3

C10

CQ8

47K

200K

R12

R11

Raj1

connector

IDC-32

CQ11 330pF 603

CI8

connector

10µF

C23

C41

C29

330pF 603

10µF 1210

C14

CI30

NC: non soldered

21/22

TSA1005

PACKAGE MECHANICAL DATA

TQFP48 MECHANICAL DATA

mm.

inch

TYP.

DIM.

MIN.

TYP

MAX.

1.6

MIN.

MAX.

0.063

0.006

0.057

0.011

0.0079

A

A1

A2

B

0.05

1.35

0.17

0.09

0.15

1.45

0.27

0.20

0.002

0.053

0.007

0.0035

1.40

0.22

0.055

0.009

C

D

9.00

7.00

5.50

0.50

9.00

7.00

5.50

0.60

1.00

3.5˚

0.354

0.276

0.216

0.020

0.354

0.276

0.216

0.024

0.039

3.5˚

D1

D3

e

E

E1

E3

L

0.45

0˚

0.75

7˚

0.018

0˚

0.030

7˚

L1

K

0110596/C

Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the

consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from

its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications

mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information

previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or

systems without express written approval of STMicroelectronics.

The ST logo is a registered trademark of STMicroelectronics

STMicroelectronics GROUP OF COMPANIES

Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco

Singapore - Spain - Sweden - Switzerland - United Kingdom

http://www.st.com

22/22


型号：	TSA1005I-40IF
厂家：	ST
描述：	DUAL-CHANNEL, 10-BIT, 20/40MSPS A/D CONVERTER 双通道， 10位， 20 / 40MSPS的A / D转换器转换器
文件：	总22页 (文件大小：546K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

TSA1005I-40IF [STMICROELECTRONICS]

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