TSB571IYLT [STMICROELECTRONICS]
Low-power, 2.5 MHz, RR IO, 36 V BiCMOS operational amplifier;
| 型号： | TSB571IYLT |
| 厂家： | 
ST |
| 描述： | Low-power, 2.5 MHz, RR IO, 36 V BiCMOS operational amplifier |
| 文件： | 总31页 (文件大小：4083K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TSB571, TSB572
Datasheet
Low-power, 2.5 MHz, RR IO, 36 V BiCMOS operational amplifier
Features
TSB571
•
•
•
•
•
•
•
•
•
•
•
•
Low-power consumption: 380 µA typ.
Wide supply voltage: 4 V - 36 V
Rail-to-rail input and output
Gain bandwidth product: 2.5 MHz
Low input bias current: 30 nA max.
No phase reversal
SOT23-5
TSB572
High tolerance to ESD: 4 kV HBM
Extended temperature range: -40 °C to 125 °C
Automotive grade
Small SMD packages
40 V BiCMOS technology
MiniSO8
Enhanced stability vs. capacitive load
SO8
Applications
DFN8 (3x3 mm)
•
•
•
•
•
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Active filtering
Audio systems
Automotive
Power supplies
Industrial
Low/high side current sensing
Maturity status link
TSB571, TSB572
Description
Related products
The TSB571 (single) and TSB572 (dual) operational amplifiers offer an extended
voltage operating range from 4 V to 36 V and rail-to-rail input/output.
For below 100 µA
solution
TSB611
The TSB571 and TSB572 give a very good speed/power consumption ratio with a
2.5 MHz gain bandwidth product and a consumption of 380 µA typically only at 36 V
supply voltage.
TSB711
TSB712
For a higher precision
Stability and robustness of these devices make them an ideal solution for a wide
voltage range of applications.
DS11248 - Rev 7 - May 2020
For further information contact your local STMicroelectronics sales office.
www.st.com
TSB571, TSB572
Package pin connections
1
Package pin connections
Figure 1. Pin connections (top view)
VCC+
OUT
VCC-
IN+
IN-
SOT23-5
Table 1. Pin description (SOT23-5)
Pin n°
Pin name
Description
1
2
3
4
5
OUT
Output channel
V
Negative supply voltage
Non-inverting input channel
Inverting input channel
Positive supply voltage
CC-
IN1+
IN-
V
CC+
DS11248 - Rev 7
page 2/31
TSB571, TSB572
Package pin connections
Figure 2. Pin connections for each package (top view)
Out1
In1-
VCC+
Out2
In2-
Out1
In1-
VCC+
Out2
In2-
In1+
VCC-
In1+
VCC-
In2+
In2+
SO8
MiniSO8
1
2
3
4
8
7
6
5
Out1
In1-
VCC+
Out2
In2-
In1+
VCC-
In2+
DFN8 (3 x 3) (1)
1.
Exposed pad can be left floating or connected to ground.
Table 2. Pin description (miniSO8/SO8/DFN8)
Pin
1
Pin name
OUT1
IN1-
Description
Output channel 1
2
Inverting input channel 1
Non-inverting input channel 1
Negative supply voltage
Non-inverting input channel 2
Inverting input channel 2
Output channel 2
3
IN1+
V
4
CC-
5
IN2+
IN2-
6
7
OUT2
V
8
Positive supply voltage
CC+
DS11248 - Rev 7
page 3/31
TSB571, TSB572
Absolute maximum ratings and operating conditions
2
Absolute maximum ratings and operating conditions
Table 3. Absolute maximum ratings
Symbol
Parameter
Supply voltage (1)
Value
Unit
V
40
±1
CC
Differential input voltage (2)
Input voltage (3)
V
V
id
-
+
V
(V
CC
) - 0.2 to (V
) + 0.2
CC
in
Input current (4)
I
10
mA
°C
in
T
Storage temperature
-65 to 150
stg
T
Maximum junction temperature
150
250
190
40
j
SOT23-5
MiniSO8
DFN8 3x3
SO-8
Thermal resistance junction to
ambient (5) (6)
R
thja
°C/W
125
4
Human body model (HBM) (7)
Machine model (MM) (8)
CDM: charged device model (9)
Latch-up immunity
kV
V
ESD
100
1.5
100
kV
mA
1. All voltage values, except the differential voltage are with respect to network ground terminal.
2. Differential voltages are the non-inverting input terminal with respect to the inverting input terminal.
3.
4. Input current must be limited by a resistor in-series with the inputs.
5. are typical values.
V
-V must not exceed 40 V, Vin must not exceed 40 V.
CC in
R
th
6. Short-circuits can cause excessive heating and destructive dissipation.
7. According to JEDEC standard JESD22-A114F.
8. According to JEDEC standard JESD22-A115A.
9. According to ANSI/ESD STM5.3.1.
Table 4. Operating conditions
Symbol
Parameter
Value
4 to 36
Unit
V
Supply voltage
CC
V
-
+
V
Common mode input voltage range
Operating free-air temperature range
(V
) - 0.1 to (V
) + 0.1
icm
CC
CC
T
-40 to 125
°C
oper
DS11248 - Rev 7
page 4/31
TSB571, TSB572
Electrical characteristics
3
Electrical characteristics
Table 5. Electrical characteristics at Vcc = 4 V, Vicm = Vcc/2, Tamb = 25 °C, and RL connected to Vcc/2 (unless otherwise
specified)
Symbol
Parameter
Conditions
Min. Typ. Max.
Unit
DC performance
-1.5
-2.1
1.5
2.1
6
V
Input offset voltage
mV
io
-40 °C < T < 125 °C
ΔV /ΔT
Input offset voltage drift
Input offset current
-40 °C < T < 125 °C
-40 °C < T < 125 °C
-40 °C < T < 125 °C
1.5
2
μV/°C
io
15
35
30
70
I
io
nA
8
I
Input bias current
ib
C
Input capacitor
2
1
pF
IN
R
IN
Input impedance
TΩ
V
= (V ) to (V
) - 1.5 V, V = V /2
90
80
75
70
90
85
114
icm
CC-
CC+
out
CC
-40 °C < T < 125 °C
= (V ) to (V
Common mode rejection ratio 20 log
CMR
(ΔV /ΔV )
icm
io
V
icm
), V = V /2
97
100
19
CC-
CC+
out
CC
dB
-40 °C < T < 125 °C
R = 10 kΩ, V = 0.5 to 3.5 V
L
out
A
Large signal voltage gain
vd
-40 °C < T < 125 °C
R = 10 kΩ
60
80
50
70
L
High level output voltage (drop
V
OH
voltage from (V
))
CC+
-40 °C < T < 125 °C
mV
R = 10 kΩ
L
12
V
Low level output voltage
OL
-40 °C < T < 125 °C
V
= V
CC
20
5
38
out
I
sink
-40 °C < T < 125 °C
= 0 V
I
mA
μA
out
CC
V
10
5
32
out
I
source
-40 °C < T < 125 °C
No load, V = V /2
340 430
500
out
CC
I
Supply current (per channel)
-40 °C < T < 125 °C
AC performance
R = 10 kΩ, C = 100 pF
1.5
1.2
2.2
L
L
GBP
Gain bandwidth product
MHz
-40 °C < T < 125 °C
ϕ
R = 10 kΩ, C = 100 pF
Phase margin
Gain margin
45
5
degrees
dB
m
L
L
G
R = 10 kΩ, C = 100 pF
m
L
L
V
= 3.5 to 0.5 V, A = 1, 10 % to 90 %, R = 10 kΩ,
v L
in
0.50 0.78
0.37
C = 100 pF
L
Negative slew rate
SR
V/μs
-40 °C < T < 125 °C
DS11248 - Rev 7
page 5/31
TSB571, TSB572
Electrical characteristics
Symbol
Parameter
Conditions
= 0.5 to 3.5 V, A = 1, 10 % to 90 %, R = 10 kΩ,
Min. Typ. Max.
Unit
V
in
v
L
0.50 0.89
C = 100 pF
SR
L
V/μs
Positive slew rate
-40 °C < T < 125 °C
f = 1 kHz
0.37
20
nV/√Hz
μVpp
%
e
Equivalent input noise voltage
n
f = 0.1 Hz to 10 Hz
0.7
f = 1 kHz, V = 3.8 V , R = 10 kΩ, C = 100 pF
THD+N Total harmonic distortion + noise
0.001
in
pp
L
L
DS11248 - Rev 7
page 6/31
TSB571, TSB572
Electrical characteristics
Table 6. Electrical characteristics at Vcc = 12 V, Vicm = Vcc/2, Tamb = 25 °C, and RL connected to Vcc/2 (unless otherwise
specified)
Symbol
Parameter
Conditions
Min. Typ. Max.
Unit
DC performance
-1.5
-2.1
1.5
2.1
6
V
Input offset voltage
mV
io
-40 °C < T < 125 °C
ΔV /ΔT
Input offset voltage drift
Input offset current
-40 °C < T < 125 °C
-40 °C < T < 125 °C
-40 °C < T < 125 °C
1.5
2
μV/°C
io
15
35
30
70
I
io
nA
8
I
Input bias current
ib
C
Input capacitor
2
1
pF
IN
R
IN
Input impedance
TΩ
V
= (V ) to (V
) - 1.5 V, V = V /2
100
90
85
80
90
80
95
90
123
icm
CC-
CC+
out
CC
-40 °C < T < 125 °C
= (V ) to (V
Common mode rejection ratio 20 log
CMR
SVR
(ΔV /ΔV )
icm
io
V
), V = V /2
106
99
icm
CC-
CC+
out
CC
-40 °C < T < 125 °C
= 4 to 12 V
dB
V
CC
Supply voltage rejection ratio 20 log
(ΔV /ΔV )
CC
io
-40 °C < T < 125 °C
R = 10 kΩ, V = 0.5 to 11.5 V
106
38
L
out
A
Large signal voltage gain
vd
-40 °C < T < 125 °C
R = 10 kΩ
100
150
70
L
High level output voltage (drop
V
OH
voltage from V
)
CC+
-40 °C < T < 125 °C
mV
R = 10 kΩ
L
16
V
I
Low level output voltage
OL
-40 °C < T < 125 °C
90
V
= V
CC
20
8
42
out
I
sink
-40 °C < T < 125 °C
= 0 V
mA
μA
out
V
15
7
35
out
I
source
-40 °C < T < 125 °C
No load, V = V /2
360
450
530
out
CC
I
Supply current (per channel)
CC
-40 °C < T < 125 °C
AC performance
R = 10 kΩ, C = 100 pF
1.6
1.3
2.4
L
L
GBP
Gain bandwidth product
MHz
-40 °C < T < 125 °C
ϕ
R = 10 kΩ, C = 100 pF
Phase margin
Gain margin
50
6
degrees
dB
m
L
L
G
R = 10 kΩ, C = 100 pF
m
L
L
V
= 10.5 to 1.5 V, A = 1, 10 % to 90 %, R = 10 kΩ,
v L
in
0.53 0.82
0.40
C = 100 pF
L
Negative slew rate
Positive slew rate
-40 °C < T < 125 °C
SR
V/μs
V
= 1.5 to 10.5 V, A = 1, 10 % to 90 %, R = 10 kΩ,
v L
in
0.55 0.92
C = 100 pF
L
DS11248 - Rev 7
page 7/31
TSB571, TSB572
Electrical characteristics
Symbol
Parameter
Positive slew rate
Conditions
Min. Typ. Max.
Unit
SR
V/μs
-40 °C < T < 125 °C
f = 1 kHz
0.40
20
nV/√Hz
μVpp
%
e
Equivalent input noise voltage
n
f = 0.1 Hz to 10 Hz
0.7
f = 1 kHz, V = 7 V , R = 10 kΩ, C = 100 pF
THD+N Total harmonic distortion + noise
0.0005
in
pp
L
L
DS11248 - Rev 7
page 8/31
TSB571, TSB572
Electrical characteristics
Table 7. Electrical characteristics at Vcc = 36 V, Vicm = Vcc/2, Tamb = 25 °C, and RL connected to Vcc/2 (unless otherwise
specified)
Symbol
Parameter
Conditions
Min. Typ. Max.
Unit
DC performance
-1.5
-2.1
1.5
2.1
6
V
Input offset voltage
mV
io
-40 °C < T < 125 °C
ΔV /ΔT
Input offset voltage drift
-40 °C < T < 125 °C
T = 25 °C
1.5
1.5
2
μV/°C
io
Long-term input offset voltage drift (1)
ΔV
µV/√month
io
15
35
30
70
I
io
Input offset current
Input bias current
-40 °C < T < 125 °C
-40 °C < T < 125 °C
nA
8
I
ib
C
Input capacitor
2
1
pF
IN
R
IN
Input impedance
TΩ
V
= (V ) to (V
) - 1.5 V, V = V /2
105 129
95
icm
CC-
CC+
out
CC
-40 °C < T < 125 °C
= (V ) to (V
Common mode rejection ratio 20 log
CMR
SVR
(ΔV /ΔV )
icm
io
V
), V = V /2
CC+
95
90
90
85
95
90
115
104
114
78
icm
CC-
out
CC
-40 °C < T < 125 °C
= 4 to 36 V
dB
V
CC
Supply voltage rejection ratio 20 log
(ΔV /ΔV )
CC
io
-40 °C < T < 125 °C
R = 10 kΩ, V = 0.5 to 35.5 V
L
out
A
Large signal voltage gain
vd
-40 °C < T < 125 °C
R = 10 kΩ
150
200
90
L
High level output voltage (drop
V
OH
voltage from V
)
CC+
-40 °C < T < 125 °C
mV
R = 10 kΩ
L
30
V
I
Low level output voltage
OL
-40 °C < T < 125 °C
120
V
= V
CC
25
10
20
10
65
out
I
sink
-40 °C < T < 125 °C
= 0 V
mA
μA
out
V
50
out
I
source
-40 °C < T < 125 °C
No load, V = V /2
380 470
550
out
CC
I
Supply current (per channel)
CC
-40 °C < T < 125 °C
AC performance
R = 10 kΩ, C = 100 pF
1.7
1.4
2.5
L
L
GBP
Gain bandwidth product
MHz
-40 °C < T < 125 °C
ϕ
R = 10 kΩ, C = 100 pF
Phase margin
Gain margin
50
8
degrees
dB
m
L
L
G
R = 10 kΩ, C = 100 pF
m
L
L
V
= 22.5 to 13.5 V, A = 1, 10 % to 90 %, R = 10 kΩ,
v L
in
0.57 0.88
0.44
C = 100 pF
L
Negative slew rate
SR
V/μs
-40 °C < T < 125 °C
DS11248 - Rev 7
page 9/31
TSB571, TSB572
Electrical characteristics
Symbol
Parameter
Conditions
= 13.5 to 22.5 V, A = 1, 10 % to 90 %, R = 10 kΩ,
Min. Typ. Max.
Unit
V
in
v
L
0.60 1.00
C = 100 pF
SR
L
V/μs
Positive slew rate
-40 °C < T < 125 °C
f = 1 kHz
0.44
20
nV/√Hz
μVpp
%
e
Equivalent input noise voltage
n
f = 0.1 Hz to 10 Hz
0.7
f = 1 kHz, V = 7 V , R = 10 kΩ, C = 100 pF
THD+N Total harmonic distortion + noise
0.001
in
pp
L
L
1. Typical value is based on the V drift observed after 1000h at 125 °C extrapolated to 25 °C using Arrhenius
io
law and assuming an activation energy of 0.7 eV. The operational amplifier is aged in follower mode
configuration (see Section 4.5 Section 4.5).
DS11248 - Rev 7
page 10/31
TSB571, TSB572
Electrical characteristics
Figure 4. Input offset voltage distribution at VCC = 4 V
Figure 3. Supply current vs. supply voltage
0.5
35
Vicm = Vcc/2
Vcc=4V
Vicm=2V
T=25°C
T = 125 °C
30
25
20
15
10
5
0.4
T = 25°C
0.3
0.2
T = -40°C
0.1
0.0
0
0
5
10
15
20
25
30
35
-1.5
-1.2
-0.9
-0.6
-0.3
0.0
0.3
0.6
0.9
1.2
1.5
Supply Voltage (V)
Input offset voltage (mV)
Figure 5. Input offset voltage distribution at VCC = 12 V
Figure 6. Input offset voltage distribution at VCC = 36 V
35
35
Vcc=36V
Vicm=18V
T=25°C
Vcc=12V
Vicm=6V
T=25°C
30
25
20
15
10
5
30
25
20
15
10
5
0
0
-1.5
-1.2
-0.9
-0.6
-0.3
0.0
0.3
0.6
0.9
1.2
1.5
-1.5
-1.2
-0.9
-0.6
-0.3
0.0
0.3
0.6
0.9
1.2
1.5
Input offset voltage (mV)
Input offset voltage (mV)
Figure 7. Input offset voltage vs. temperature at
VCC = 36 V
Figure 8. Input offset voltage temperature variation
distribution at VCC = 36 V
2.5
Vio limit
2.0
1.5
1.0
0.5
0.0
-0.5
-1.0
-1.5
Vcc=36V
Vicm=18V
-2.0
-2.5
-40 -20
0
20
40
60
80 100 120
Temperature(°C)
DS11248 - Rev 7
page 11/31
TSB571, TSB572
Electrical characteristics
Figure 10. Input offset voltage vs. common-mode voltage
at VCC = 4 V
Figure 9. Input offset voltage vs. supply voltage
-0.2
Vicm=Vcc/2
-0.3
-0.4
-0.5
-0.6
T=-40°C
T=25°C
T=125°C
-0.7
-0.8
4
8
12
16
20
24
28
32
36
Supply voltage (V)
Figure 11. Input offset voltage vs. common-mode voltage
at VCC = 36 V
Figure 12. Input bias current vs. temperature at
VICM = VCC/2
0
Vicm=Vcc/2
-2
-4
-6
Vcc=36V
Vcc=4V
Vcc=12V
-8
-10
-40
-20
0
20
40
60
80
100
120
Temperature (°C)
Figure 13. Input bias current vs. common-mode voltage at
VCC = 36 V
Figure 14. Output current vs. output voltage at VCC = 4 V
50
60
Sink
Vid=-1V
40
Vcc=36V
T=-40°C
40
30
20
T=25°C
20
10
T=125°C
T=125°C
0
-10
-20
-30
-40
-50
T=25°C
Vcc=4V
0
-20
-40
-60
T=-40°C
Source
Vid=1V
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0
0
5
10
15
20
25
30
35
Output Voltage (V)
Input Common Mode Voltage (V)
DS11248 - Rev 7
page 12/31
TSB571, TSB572
Electrical characteristics
Figure 15. Output current vs. output voltage at VCC = 36 V
Figure 16. Output voltage (Voh) vs. supply voltage
70
110
100
90
Vcc=36V
Sink
Vid=-1V
56
42
80
28
70
14
60
0
T=125°C
T=25°C T=-40°C
50
-14
-28
-42
-56
-70
40
T=125°C
T=25°C
T=-40°C
30
20
10
0
Source
Vid=1V
Vid=0.1V
Rl=10kΩ to Vcc/2
24 28 32
Power supply voltage (V)
4
8
12
16
20
36
0
5
10
15
20
25
30
35
Output Voltage (V)
Figure 18. Negative slew rate at VCC = 36 V
Figure 17. Output voltage (Vol) vs. supply voltage
1.2
40
35
30
25
20
15
10
1.0
0.8
Vcc=36V
Vicm=Vcc/2
Rl=10kΩ
0.6
T=-40°C
T=25°C
Cl=100pF
0.4
0.2
0.0
-0.2
-0.4
-0.6
-0.8
-1.0
-1.2
T=125°C
T=-40°C T=25°C
Vid=-0.1V
T=125°C
5
0
Rl=10kΩ to Vcc/2
4
8
12
16
20 24 28
32
36
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
Power supply voltage (V)
Time (µs)
Figure 19. Positive slew rate at VCC = 36 V
Figure 20. Slew rate vs. supply voltage
1.4
1.2
1.0
0.8
0.6
0.4
0.2
1.2
1.0
0.8
0.6
0.4
0.2
0.0
Vicm=Vcc/2
Vload=Vcc/2
Rl=10kΩ
T=-40°C
T=125°C T=25°C T=-40°C
0.0
-0.2
-0.4
-0.6
-0.8
-1.0
-1.2
-1.4
-0.2
T=25°C
Cl=100pF
Vcc=36V
Vicm=Vcc/2
Rl=10kΩ
-0.4
T=125°C
-0.6
-0.8
-1.0
-1.2
Cl=100pF
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.0 8.0 12.0 16.0 20.0 24.0 28.0 32.0 36.0
Time (µs)
Supply Voltage (V)
DS11248 - Rev 7
page 13/31
TSB571, TSB572
Electrical characteristics
Figure 21. Bode diagram at VCC = 4 V
Figure 22. Bode diagram at VCC = 36 V
60
40
20
0
0
60
40
20
0
0
T=-40°C
T=25°C
T=125°C
T=-40°C
T=25°C
T=125°C
-60
-60
Phase
Phase
-120
-180
-240
-300
-360
-120
-180
-240
-300
-360
Gain
Gain
-20
-40
-60
-20
-40
-60
Vcc=4V
Vcc=36V
Vicm=18V
Rl=10kΩ
Cl=100pF
Gain=100
Vicm=2V
Rl=10kΩ
Cl=100pF
Gain=100
1k
10k
100k
1M
10M
1k
10k
100k
1M
10M
Frequency (Hz)
Frequency (Hz)
Figure 23. Phase margin vs. output current at VCC = 4 V
Figure 24. Phase margin vs. output current at VCC = 36 V
100
90
80
70
60
50
40
30
20
10
0
100
90
80
70
60
50
40
30
20
10
0
-1.0 -0.8 -0.6 -0.4 -0.2 0.0
0.2
0.4
0.6
0.8
1.0
-1.0 -0.8 -0.6 -0.4 -0.2 0.0
0.2
0.4
0.6
0.8
1.0
Figure 26. Overshoot vs. capacitive load at VCC = 36 V
Figure 25. Phase margin vs. capacitive load
50
100
Vcc=36V
Vicm=Vcc/2
Rl=10kΩ
Vin=100mVpp
Gain=1
40
80
T=25°C
30
60
Vcc=4V
40
20
Vcc=36V
Vicm=Vcc/2
Rl=10kΩ
T=25°C
20
10
Sustained Oscillations
0
0
10
100
1000
10000
100
200
300
400 500
700
1000
Capacitive load (pF)
Capacitive load (pF)
DS11248 - Rev 7
page 14/31
TSB571, TSB572
Electrical characteristics
Figure 27. Small step response vs. time at VCC = 4 V
Figure 28. Output desaturation vs. time
0.15
Vcc=4V
Vicm=2V
Rl=10kΩ
20
15
10
5
Vcc=+/-18V
Vicm=0V
Gain=4.7
Rl=10kΩ
Cl=100pF
Follower
Configuration
T=25°C
0.07
Cl=100pF
0
0.00
-0.07
-0.15
-5
-10
-15
-20
0
200
400
600
800
1000
Time (µs)
0.0
2.5
5.0
Time (µs)
7.5
10.0
Figure 29. Amplifier behavior close to the rails at
VCC = 36 V
Figure 30. Noise vs. frequency at VCC = 36 V
100
36.00
35.95
35.90
35.85
35.80
35.75
35.70
@Vcc=36V
@Vcc=12V
@Vcc=4V
Vicm=Vcc/2
T=25°C
80
60
40
20
0
0.25
T=-40°C
T=25°C
T=125°C
0.20
0.15
Vcc=36V
0.10
Follower configuration
0.05
0.00
10
100
1000
10000
Input voltage (V)
Frequency (Hz)
Figure 31. Noise vs. time at VCC = 36 V
Figure 32. THD+N vs. frequency
0.01
1E-3
1E-4
400
Vicm=Vcc/2
Gain=1
Vcc=36V
Vicm=Vcc/2
Vload=Vcc/2
300
200
100
0
Rl=10kΩ
Cl=100pF
BW=80kHz
T=25°C
Vcc=4V
with Vin=3.8Vpp
Vcc=12V
with Vin=7Vpp
-100
-200
-300
-400
Vcc=36V
with Vin=7Vpp
0
1
2
3
4
5
6
7
8
9
10
10
100
1000
10000
Time (s)
Frequency (Hz)
DS11248 - Rev 7
page 15/31
TSB571, TSB572
Electrical characteristics
Figure 34. PSRR vs. frequency at VCC = 36 V
Figure 33. THD+N vs. output voltage
-20
0.1
-40
0.01
1E-3
1E-4
-60
PSRR +
Vicm=Vcc/2
Gain=1
f=1kHz
BW=22kHz
Rl=10kΩ
Cl=100pF
T=25°C
-80
4V
12V
PSRR -
-100
-120
36V
10
100
1k
10k
100k
0.01
0.1
1
10
Output Voltage (Vpp)
Frequency (Hz)
Figure 35. Channel separation vs. frequency at VCC= 36 V
160
Vcc=36V
Vicm=18V
140
Gain=11
Vin = 1Vpp
120
100
80
60
40
20
0
100
1k
10k
100k
1M
Frequency (Hz)
DS11248 - Rev 7
page 16/31
TSB571, TSB572
Application information
4
Application information
4.1
Operating voltages
The TSB571 and TSB572 can operate from 4 V to 36 V. The parameters are fully specified for 4 V, 12 V, and 36 V
power supplies. However, the parameters are stable in the full VCC range. Additionally, the main specifications are
guaranteed in extended temperature ranges from -40 to 125 °C.
4.2
Input pin voltage ranges
The TSB571 and TSB572 have an internal ESD diode protection on the inputs. These diodes are connected
between the inputs and each supply rail to protect the input transistors from electrical discharge.
If the input pin voltage exceeds the power supply by 0.2 V, the ESD diodes become conductive and excessive
current can flow through them. Without limitation this over current can damage the device.
In this case, it is important to limit the current to 10 mA, by adding resistance on the input pin, as shown in
Figure 37. Input current limitation.
Figure 36. Input current limitation
16 V
+
R
-
V
out
V
+
in
-
4.3
4.4
Rail-to-rail input
The TSB571 and TSB572 have rail-to-rail inputs. The input common mode range is extended from (VCC -) - 0.1 V
to (VCC+) + 0.1 V at T = 25 °C.
Input offset voltage drift over temperature
The maximum input voltage drift variation over temperature is defined as the offset variation related to the offset
value measured at 25 °C. The operational amplifier is one of the main circuits of the signal conditioning chain, and
the amplifier input offset is a major contributor to the chain accuracy. The signal chain accuracy at 25 °C can be
compensated during production at application level. The maximum input voltage drift over temperature enables
the system designer to anticipate the effect of temperature variations.
The maximum input voltage drift over temperature is computed using Equation 1.
Equation 1
∆Vio
∆T
°C
Vio(T) – Vio(25
T – 25 °C
)
= max
where T = -40 °C and 125 °C.
The TSB571 and TSB572 datasheet maximum value is guaranteed by measurements on a representative sample
size ensuring a Cpk (process capability index) greater than 1.3.
DS11248 - Rev 7
page 17/31
TSB571, TSB572
Long term input offset voltage drift
4.5
Long term input offset voltage drift
To evaluate product reliability, two types of stress acceleration are used:
•
•
Voltage acceleration, by changing the applied voltage
Temperature acceleration, by changing the die temperature (below the maximum junction temperature
allowed by the technology) with the ambient temperature.
The voltage acceleration has been defined based on JEDEC results, and is defined using Equation 2.
Equation 2
S – VU
)
AFV = eβ . (V
Where:
AFV is the voltage acceleration factor
β is the voltage acceleration constant in 1/V, constant technology parameter (β = 1)
VS is the stress voltage used for the accelerated test
VU is the voltage used for the application
The temperature acceleration is driven by the Arrhenius model, and is defined in Equation 3.
Equation 3
Ea
1
1
.
------
–
AFT = e k
TU TS
Where:
AFT is the temperature acceleration factor
Ea is the activation energy of the technology based on the failure rate
k is the Boltzmann constant (8.6173 x 10-5 eV.K-1)
TU is the temperature of the die when VU is used (K)
TS is the temperature of the die under temperature stress (K)
The final acceleration factor, AF, is the multiplication of the voltage acceleration factor and the temperature
acceleration factor (Equation 4).
Equation 4
AF = AFT × AFV
AF is calculated using the temperature and voltage defined in the mission profile of the product. The AF value can
then be used in Equation 5 to calculate the number of months of use equivalent to 1000 hours of reliable stress
duration.
Equation 5
(
/
Months = AF × 1000 h × 12 months 24 h × 365 25 days)
.
To evaluate the op amp reliability, a follower stress condition is used where VCC is defined as a function of the
maximum operating voltage and the absolute maximum rating (as recommended by JEDEC rules).
The Vio drift (in µV) of the product after 1000 h of stress is tracked with parameters at different measurement
conditions (see Equation 6).
Equation 6
VCC = maxVop with Vicm = VCC
2
/
The long term drift parameter (ΔVio), estimating the reliability performance of the product, is obtained using the
ratio of the Vio (input offset voltage value) drift over the square root of the calculated number of months (Equation
7).
Equation 7
DS11248 - Rev 7
page 18/31
TSB571, TSB572
Capacitive load
Viodrift
∆Vio
=
(months)
Where Vio drift is the measured drift value in the specified test conditions after 1000 h stress duration.
4.6
Capacitive load
Driving large capacitive loads can cause stability problems. Increasing the load capacitance produces gain
peaking in the frequency response, with overshoot and ringing in the step response. It is usually considered that
with a gain peaking higher than 2.3 dB an op amp might become unstable.
Generally, unity gain configuration is the worst situation for stability and the ability to drive large capacitive loads.
Figure 38. Stability criteria with a serial resistor at different supply voltages shows the serial resistor that must be
added to the output, to make a system stable. Figure 39. Test configuration for Riso shows the test configuration
using an isolation resistor, Riso.
Figure 37. Stability criteria with a serial resistor at different supply voltages
Vcc=36V
Vicm=18V
follower
100
Stable
configuration
T=25°C
10
Unstable
1
@Vcc=4V
@Vcc=12V
@Vcc=36V
0.1
102
103
104
105
106
Capacitive load (pF)
Figure 38. Test configuration for Riso
V
CC+
Riso
C
-
V
OUT
V
+
IN
10 kΩ
load
V
CC-
4.7
PCB layout recommendations
Particular attention must be paid to the layout of the PCB tracks connected to the amplifier, load, and power
supply. The power and ground traces are critical as they must provide adequate energy and grounding for all
circuits. The best practice is to use short and wide PCB traces to minimize voltage drops and parasitic
inductance.
In addition, to minimizing parasitic impedance over the entire surface, a multi-via technique that connects the
bottom and top layer ground planes together in many locations is often used.
The copper traces that connect the output pins to the load and supply pins should be as wide as possible to
minimize trace resistance.
DS11248 - Rev 7
page 19/31
TSB571, TSB572
Optimized application recommendation
4.8
Optimized application recommendation
It is recommended to place a 22 nF capacitor as close as possible to the supply pin. A good decoupling will help
to reduce electromagnetic interference impact.
DS11248 - Rev 7
page 20/31
TSB571, TSB572
Package information
5
Package information
In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages,
depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product
status are available at: www.st.com. ECOPACK is an ST trademark.
5.1
SOT23-5 package information
Figure 39. SOT23-5 package outline
Table 8. SOT23-5 package mechanical data
Dimensions
Ref.
Millimeters
Typ.
Inches
Typ.
Min.
Max.
1.45
0.15
1.30
0.50
0.20
3.00
Min.
Max.
0.057
0.006
0.051
0.020
0.020
0.118
A
A1
A2
B
0.90
1.20
0.035
0.047
0.90
0.35
0.09
2.80
1.05
0.40
0.15
2.90
1.90
0.95
2.80
1.60
0.35
0.035
0.014
0.004
0.110
0.041
0.016
0.006
0.114
0.075
0.037
0.110
0.063
0.014
C
D
D1
e
E
2.60
1.50
0.10
0°
3.00
1.75
0.60
10°
0.102
0.059
0.004
0°
0.118
0.069
0.024
10°
F
L
K
DS11248 - Rev 7
page 21/31
TSB571, TSB572
MiniSO8 package information
5.2
MiniSO8 package information
Figure 40. MiniSO8 package outline
Table 9. MiniSO8 package mechanical data
Dimensions
Millimeters
Ref.
Inches
Min.
Typ.
Max.
1.1
Min.
Typ.
Max.
0.043
0.0006
0.037
0.016
0.009
0.126
0.203
0.122
A
A1
A2
b
0
0.15
0.95
0.40
0.23
3.20
5.15
3.10
0
0.75
0.22
0.08
2.80
4.65
2.80
0.85
0.030
0.009
0.003
0.11
0.033
c
D
3.00
4.90
3.00
0.65
0.60
0.95
0.25
0.118
0.193
0.118
0.026
0.024
0.037
0.010
E
0.183
0.11
E1
e
L
0.40
0°
0.80
0.016
0°
0.031
L1
L2
k
8°
8°
ccc
0.10
0.004
DS11248 - Rev 7
page 22/31
TSB571, TSB572
DFN8 3x3 package information
5.3
DFN8 3x3 package information
Figure 41. DFN8 3x3 package outline and mechanical data
BOTTOM VIEW
DETAIL A
SIDE VIEW
TOP VIEW
Table 10. DFN8 3x3 mechanical data
mm
Symbol
Min.
0.70
0.0
Typ.
Max.
0.80
0.05
A
A1
A3
b
0.75
0.20 Ref.
0.30
0.25
2.95
2.25
0.35
3.05
2.45
D
3.00
D2
e
2.35
0.65 BSC
3.00
E
2.95
1.45
0.35
3.05
1.65
0.55
E2
L
1.55
0.45
K
2.75 Ref.
8
N
DS11248 - Rev 7
page 23/31
TSB571, TSB572
DFN8 3x3 package information
Figure 42. DFN8 3x3 footprint data
DS11248 - Rev 7
page 24/31
TSB571, TSB572
SO-8 package information
5.4
SO-8 package information
Figure 43. SO-8 package outline
0016023_So-807_fig2_Rev10
Table 11. SO-8 mechanical data
mm
Dim.
Min.
Typ.
Max.
1.75
0.25
A
A1
A2
b
0.10
1.25
0.31
0.28
0.10
0.10
4.80
5.80
3.80
0.51
0.48
0.25
0.23
5.00
6.20
4.00
b1
c
c1
D
4.90
6.00
3.90
1.27
E
E1
e
h
0.25
0.40
0.50
1.27
L
L1
L2
k
1.04
0.25
0°
8°
ccc
0.10
DS11248 - Rev 7
page 25/31
TSB571, TSB572
Ordering information
6
Ordering information
Table 12. Order codes
Order code
TSB571ILT
Temperature range
Package
Packing
Marking
K31
-40 °C to +125 °C
-40 °C to 125 °C
SOT23-5
Tape and reel
TSB571IYLT (1)
TSB572IQ2T
TSB572IYQ2T (1)
TSB572IST
K32
K31
DFN8 3x3
K32
Tape and reel
K31
MiniSO8
TSB572IYST (1)
TSB572IDT
K32
SO8 package
TSB572I
1. Automotive qualification according to AEC-Q100.
DS11248 - Rev 7
page 26/31
TSB571, TSB572
Revision history
Table 13. Document revision history
Date
Version
Changes
12-Oct-2015
1
Initial release
Section 2: "Absolute maximum ratings and operating conditions": updated ESD,
MM value. Section 6: "Ordering information": removed footnote (1) from order code
TSB572IQ2T
17-Dec-2015
2
In Table1: "Absolute maximum ratings":
- Updated Latch-up immunity Parameter Value
- updated footnote (3)
26-Jun-2017
10-Nov-2017
3
4
Added: new SO-8 Package information and new order code TSB572IDT Section 6
Ordering information
26-Mar-2018
22-Jul-2019
06-May-2020
5
6
7
Updated: Section 5.2 DFN8 3x3 package information
Added the root part number TSB571 and updated the whole document accordingly.
Updated cover page
DS11248 - Rev 7
page 27/31
TSB571, TSB572
Contents
Contents
1
2
3
4
Package pin connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2
Absolute maximum ratings and operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
Electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Application information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
4.1
4.2
4.3
4.4
4.5
4.6
4.7
4.8
Operating voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Input pin voltage ranges. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Rail-to-rail input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Input offset voltage drift over temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Long term input offset voltage drift . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Capacitive load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
PCB layout recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Optimized application recommendation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
5
6
Package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
5.1
5.2
5.3
5.4
SOT23-5 package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
MiniSO8 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
DFN8 3x3 package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
SO-8 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
DS11248 - Rev 7
page 28/31
TSB571, TSB572
List of tables
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Pin description (SOT23-5). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Pin description (miniSO8/SO8/DFN8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Electrical characteristics at Vcc = 4 V, Vicm = Vcc/2, Tamb = 25 °C, and RL connected to Vcc/2 (unless otherwise
specified) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Electrical characteristics at Vcc = 12 V, Vicm = Vcc/2, Tamb = 25 °C, and RL connected to Vcc/2 (unless otherwise
specified) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Electrical characteristics at Vcc = 36 V, Vicm = Vcc/2, Tamb = 25 °C, and RL connected to Vcc/2 (unless otherwise
specified) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
SOT23-5 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
MiniSO8 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 6.
Table 7.
Table 8.
Table 9.
Table 10. DFN8 3x3 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 11. SO-8 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 12. Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 13. Document revision history. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
DS11248 - Rev 7
page 29/31
TSB571, TSB572
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Pin connections (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Pin connections for each package (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Supply current vs. supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Input offset voltage distribution at VCC = 4 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Input offset voltage distribution at VCC = 12 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Input offset voltage distribution at VCC = 36 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Input offset voltage vs. temperature at VCC = 36 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Input offset voltage temperature variation distribution at VCC = 36 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Input offset voltage vs. supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Input offset voltage vs. common-mode voltage at VCC = 4 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Input offset voltage vs. common-mode voltage at VCC = 36 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Input bias current vs. temperature at VICM = VCC/2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Input bias current vs. common-mode voltage at VCC = 36 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Output current vs. output voltage at VCC = 4 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Output current vs. output voltage at VCC = 36 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Output voltage (Voh) vs. supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Output voltage (Vol) vs. supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Negative slew rate at VCC = 36 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Positive slew rate at VCC = 36 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Slew rate vs. supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Bode diagram at VCC = 4 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Bode diagram at VCC = 36 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Phase margin vs. output current at VCC = 4 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Phase margin vs. output current at VCC = 36 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Phase margin vs. capacitive load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Overshoot vs. capacitive load at VCC = 36 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Small step response vs. time at VCC = 4 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Output desaturation vs. time. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Amplifier behavior close to the rails at VCC = 36 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Noise vs. frequency at VCC = 36 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Noise vs. time at VCC = 36 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
THD+N vs. frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
THD+N vs. output voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
PSRR vs. frequency at VCC = 36 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Channel separation vs. frequency at VCC= 36 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Input current limitation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Stability criteria with a serial resistor at different supply voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Test configuration for Riso . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
SOT23-5 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
MiniSO8 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
DFN8 3x3 package outline and mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
DFN8 3x3 footprint data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
SO-8 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Figure 23.
Figure 24.
Figure 25.
Figure 26.
Figure 27.
Figure 28.
Figure 29.
Figure 30.
Figure 31.
Figure 32.
Figure 33.
Figure 34.
Figure 35.
Figure 36.
Figure 37.
Figure 38.
Figure 39.
Figure 40.
Figure 41.
Figure 42.
Figure 43.
DS11248 - Rev 7
page 30/31
TSB571, TSB572
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DS11248 - Rev 7
page 31/31
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