TSC2011IDT [STMICROELECTRONICS]
High voltage, precision, bidirectional current sense amplifiers;
| 型号： | TSC2011IDT |
| 厂家： | 
ST |
| 描述： | High voltage, precision, bidirectional current sense amplifiers |
| 文件： | 总54页 (文件大小：1868K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TSC2010, TSC2011, TSC2012
Datasheet
High voltage, precision, bidirectional current sense amplifiers
Features
•
•
•
•
Wide common mode voltage: - 20 to 70 V
Offset voltage: ± 200 µV max
2.7 to 5.5 V supply voltage
Different gain available
SO8
–
–
–
TSC2010: 20 V/V
TSC2011: 60 V/V
TSC2012: 100 V/V
•
•
•
•
Gain error: 0.3% max
MiniSO8
Offset drift: 5 µV/°C max
Quiescent current: 20 µA in shutdown mode
SO8 and MiniSO8 package
Applications
•
•
•
•
•
•
•
High-side current sensing
Low-side current sensing
Data acquisition and instrumentation
Test and measurement equipment
Industrial process control
Motor control
Solenoid control
Maturity status link
TSC2010, TSC2011, TSC2012
Description
The TSC2010, TSC2011 and TSC2012 are precision bidirectional current sense
amplifiers. They can sense the current thanks to a shunt resistor over a wide range of
common mode voltages, from - 20 to + 70 V, whatever the supply voltage is. They
are available with an amplifier gain of 20V/V for TSC2010, 60 V/V for TSC2011 and
100 V/V for TSC2012.
They are able to sense very low drop voltages as low as 10 mV full scale minimizing
the measurement error.
The TSC2010, TSC2011 and TSC2012 can also be used in other functions such as:
precision current measurement, overcurrent protection, current monitoring, and
feedback loops.
This device fully operates over the broad supply voltage range from 2.7 to 5.5 V and
over the industrial temperature range from -40 to 125 °C.
DS13057 - Rev 4 - August 2020
www.st.com
For further information contact your local STMicroelectronics sales office.
TSC2010, TSC2011, TSC2012
Diagram
1
Diagram
Figure 1. Block diagram
DS13057 - Rev 4
page 2/54
TSC2010, TSC2011, TSC2012
Pin configuration
2
Pin configuration
Figure 2. Pin connection (top view)
Table 1. Pin description
Pin
1
Pin name
IN -
Description
Negative input
Ground
2
GND
VREF2
SHDN
OUT
3
Reference voltage 2
Shutdown
4
5
Output
6
VCC
Supply voltage
Reference voltage 1
Positive input
7
VREF1
IN +
8
DS13057 - Rev 4
page 3/54
TSC2010, TSC2011, TSC2012
Maximum ratings
3
Maximum ratings
Table 2. Absolute maximum ratings
Symbol
Parameter
Value
-0.3 to 7
-25 to 76
7
Unit
V
Supply voltage (1)
V
CC
V
Common mode voltage on input pins
Differential voltage between input pins (In+, In-)
Voltage present on pins Ref1, Ref2, Out
Input current to any pins (2)
V
ICM
V
DIF
V
V
V
V
Gnd - 0.3 to V + 0.3
V
REF1 REF2 OUT
cc
I
5
mA
°C
°C
IN
T
Storage temperature
-65 to 150
150
STG
T
J
Junction temperature
Thermal resistance junction to ambient (3)(4)
R
THJA
°C/W
SO8
125
190
MiniSO8
Human body model (HBM) (5)
Charged device model (CDM) (6)
Latch-up immunity
2000
1000
200
ESD
V
mA
1. All voltage values, except the differential voltage are with respect to the network ground terminal.
2. Input voltage can go beyond supply voltage but input current must be limited. Using a serial resistor with the input is highly
recommended in that case.
3. Short-circuits can cause excessive heating and destructive dissipation.
4.
R are typical values.
th
5. According to JEDEC standard JESD22-A114F.
6. According to ANSI/ESD STM5.3.1.According to ANSI/ESD STM5.3.1.
Table 3. Operating conditions
Symbol
Parameter
Value
Unit
V
V
Supply voltage
2.7 to 5.5
-20 to +70
cc
V
icm
Common mode voltage on input pins
Output offset adjustment range
V
V
0 to V
V
ref
cc
T
Operating free-air temperature range
-40 to 125
°C
DS13057 - Rev 4
page 4/54
TSC2010, TSC2011, TSC2012
Electrical characteristics
4
Electrical characteristics
Table 4. Electrical characteristics Vcc = 2.7 V, Vicm = 12 V, T = 25 °C (unless otherwise specified).
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Unit
Power supply
V
= -20 to 70 V
1.5
20
2.3
2.3
icm
Current consumption
mA
µA
T
< T < T
max
min
I
cc
V
= - 20 to 70 V
50
icm
Current consumption with
shutdown active
150
T
< T < T
min
max
Input
V
= 1 V
200
700
icm
T
< T < T
min
max
Offset voltage (RTI) (1)
|V
|
os
µV
V
= 12 V
500
icm
T
< T < T
1100
min
max
V
V
V
= 1 V, T
< T < T
5
8
icm
min max
|ΔV /ΔT|
Offset drift vs. temperature
Common mode rejection
Input bias current
µV/°C
dB
os
= 12 V, T
< T < T
max
icm
min
= -20 to 70 V, DC mode
115
350
100
90
85
icm
min
CMR
T
< T < T
max
max
V
T
= 12 V
icm
I
ib+
< T < T
, V
= -20 to 70 V
icm
-400
-150
600
350
min
µA
V
= 12 V
icm
min
I
ib-
Input bias current
T
< T < T
, V = - 20 to 70 V
icm
max
max
max
max
TSC2010
< T < T
123.6
122.4
T
min
TSC2011
< T < T
40.5
39.3
Vsense operating range with
Eg ≤ 0.3% (2)
|V
|
mV
sense
T
min
TSC2012
< T < T
23.9
22.7
T
min
Output
TSC2010
TSC2011
TSC2012
20
60
G
Gain
V/V
%
100
ΔV = 100 mV to (V - 100 mV)
0.3
0.3
out
cc
Eg
Gain error vs. temperature
T
< T < T
min
min
max
T
< T < T
= 12 V
ΔEg/ΔT
NLE
Gain error drift
Linearity error
25
ppm/°C
%
max
V
0.03
8
icm
I
= 0.2 mA
15
20
source
V
- V
oh
Drop voltage output high
mV
cc
T
< T < T
max
min
DS13057 - Rev 4
page 5/54
TSC2010, TSC2011, TSC2012
Electrical characteristics
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Unit
I
= 0.2 mA
12
20
30
sink
V
Output voltage low
mV
ol
T
< T < T
max
min
Sink mode
< T < T
12
8
20
10
25
30
T
min
max
I
Output current
mA
out
Source mode
6
4
14
17
T
I
< T < T
max
min
= - 10 to +4 mA
Reg Load Load regulation
0.3
1.5
mV/mA
out
OFFSET adjustment
R
Ratiometric accuracy
Accuracy, RTO
0.5
0.1
V/V
%
t
Voltage applied to Vref1 and Vref2 in
parallel
Acc
Dynamic performances
R = 10 kΩ, C = 100 pF
l
l
TSC2010
TSC2010, T
600
300
750
620
415
< T < T
< T < T
< T < T
min
min
max
max
max
BW
Small signal -3 dB bandwidth TSC2011
TSC2011, T
500
250
kHz
TSC2012
330
170
TSC2012, T
min
R = 10 kΩ, C = 100 pF, V = 1 V
icm
l
l
TSC2010, Vsense = 120 mV
TSC2010, T < T < T
3.0
2.7
3.9
3.5
2.8
min
max
SR
Slew rate
TSC2011, Vsense = 40 mV
TSC2011, T < T < T
2.7
2.5
V/µs
min
max
TSC2012, Vsense = 24 mV
TSC2012, T < T < T
2.0
1.8
min
max
Noise, RTI
0.1 Hz to 10 Hz
f = 1 kHz
37
µVpp
E
n
Spectral density, RTI
100
nV/√Hz
Shutdown function (active high)
V
V
0.3xV
Logical low level
Logical high level
Leakage current
0
il
cc
V
0.7xV
V
cc
ih
cc
I
ih
V
V
= V (Shutdown mode)
cc
0.9
µA
shdn
shdn
= 2.7 V to 0 V, R = 10 kΩ
l
T
Turn-on time
Turn-off time
µs
µs
TSC2011
6
8
on
off
TSC2010, TSC2012
V
= 0 V to 2.7 V, R = 10 kΩ
l
shdn
T
TSC2011
4
5
TSC2010, TSC2012
DS13057 - Rev 4
page 6/54
TSC2010, TSC2011, TSC2012
Electrical characteristics
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Unit
I
Output leakage current
Shdn active
50
nA
out
1. RTI stands for “Related to input”.
2. =(V ) – (V ).
V
sense
in+
in-
DS13057 - Rev 4
page 7/54
TSC2010, TSC2011, TSC2012
Electrical characteristics
Table 5. Electrical characteristics (Vcc = 5 V, Vicm = 12 V, T = 25 °C unless otherwise specified)
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Unit
Power supply
V
= -20 to 70 V
1.6
20
2.4
2.4
icm
Current consumption
mA
T
< T < T
max
min
I
cc
V
= - 20 to 70 V
50
icm
Current consumption with
shutdown active
µA
dB
150
T
< T < T
max
min
80
75
100
V
cc
= 2.7 to 5.5 V
SVR
Supply voltage rejection
T
< T < T
min
max
Input
V
= 1 V
200
700
icm
T
< T < T
min
max
Offset voltage (RTI) (1)
|V
os
|
µV
V
= 12 V
500
icm
T
< T < T
1100
min
max
V
V
V
= 1 V, T
< T < T
5
8
icm
min max
|ΔV /ΔT|
Offset drift vs. temperature
Common mode rejection
Input bias current
µV/°C
dB
os
= 12 V, T
< T < T
max
icm
min
= -20 to 70 V, DC mode
90
85
120
350
100
icm
min
CMR
T
< T < T
max
max
V
T
= 12 V
icm
I
ib+
< T < T
, V
= -20 to 70 V
icm
-400
-150
600
350
min
µA
V
= 12 V
icm
min
I
ib-
Input bias current
T
< T < T
, V = - 20 to 70 V
icm
max
max
max
max
TSC2010
< T < T
238.3
237.1
T
min
TSC2011
< T < T
78
Vsense operating range with
Eg ≤ 0.3% (2)
|V
|
mV
sense
T
77.6
min
TSC2012
< T < T
46.9
45.7
T
min
Output
TSC2010
TSC2011
TSC2012
20
60
G
Gain
V/V
%
100
ΔV = 100 mV to (V - 100 mV)
0.3
0.3
out
cc
Eg
Gain error vs. temperature
T
< T < T
min
min
max
T
< T < T
= 12 V
ΔEg/ΔT
NLE
Gain error drift
Linearity error
25
ppm/°C
%
max
V
0.03
15
icm
I
= 0.2 mA
30
35
source
V
- V
oh
Drop voltage output high
mV
cc
T
< T < T
max
min
DS13057 - Rev 4
page 8/54
TSC2010, TSC2011, TSC2012
Electrical characteristics
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Unit
I
= 0.2 mA
26
40
50
sink
V
Output voltage low
mV
ol
T
< T < T
max
min
Sink mode
< T < T
25
15
36
25
50
60
T
min
max
I
Output current
mA
out
Source mode
12
8
45
55
T
I
< T < T
max
min
= -10 to +10 mA
Reg Load Load regulation
0.3
1.5
mV/mA
out
OFFSET adjustment
R
Ratiometric accuracy
Accuracy, RTO
0.5
0.1
V/V
%
t
Voltage applied to Vref1 and Vref2 in
parallel
Acc
Dynamic performance
R = 10 kΩ, C = 100 pF
l
l
TSC2010
TSC2010, T
650
330
600
300
390
200
820
750
490
< T < T
< T < T
< T < T
min
min
max
max
max
BW
Small signal -3 dB bandwidth TSC2011
TSC2011, T
kHz
TSC2012
TSC2012, T
min
R = 10 kΩ, C = 100 pF, V = 1 V
icm
l
l
TSC2010, Vsense = 230 mV
TSC2010, T < T < T
5.7
4.4
7.5
7
min
max
SR
Slew rate
TSC2011, Vsense = 78 mV
TSC2011, T < T < T
5.4
4.1
V/µs
min
max
TSC2012, Vsense = 47 mV
TSC2012, T < T < T
4.4
3.2
5.2
min
max
Noise, RTI
0.1 Hz to 10 Hz
f = 1 kHz
37
µVpp
E
n
Spectral density, RTI
100
nV/√Hz
Shutdown function (active high)
V
V
0.3xV
Logical low level
Logical high level
Leakage current
0
il
cc
V
0.7xV
V
cc
ih
cc
I
ih
V
V
= V (Shutdown mode)
cc
1.2
µA
shdn
shdn
= 5 V to 0 V, R = 10 kΩ
l
T
Turn-on time
Turn-off time
µs
µs
TSC2011
6
8
on
off
TSC2010, TSC2012
V
shdn
= 0 V to 5 V, R = 10 kΩ
l
T
TSC2011
4
5
TSC2010, TSC2012
DS13057 - Rev 4
page 9/54
TSC2010, TSC2011, TSC2012
Electrical characteristics
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Unit
I
Output leakage current
Shdn active
50
nA
out
1. RTI stands for “Related to input”.
2. = (V ) – (V ).
V
sense
in+
in-
DS13057 - Rev 4
page 10/54
TSC2010, TSC2011, TSC2012
Typical characteristics
4.1
Typical characteristics
TSC2011 is used for typical characteristics, unless otherwise noted.
Figure 3. Supply current vs. supply voltage
Figure 4. Supply current vs. input common mode
1.9
1.9
Vref=Vcc/2
Vsense=0V
T=25°C
Vicm=2.5V
1.8
1.7
1.6
1.5
1.4
1.3
1.8
1.7
1.6
1.5
1.4
1.3
Vicm=0V
Vicm=12V
Vicm=70V
Vcc=5V
Vcc=3.3V
Vcc=2.7V
Vref=Vcc/2
Vsense=0V
T=25°C
2.8
3.1
3.5
3.9
4.2
4.5
4.9
5.3
-20
-10
0
10
20
30
40
50
60
70
Vicm (V)
Supply voltage (V)
Figure 6. Supply current vs. input common mode with
active shutdown mode
Figure 5. Supply current vs. temperature
1.9
1.8
1.7
1.6
1.5
1.4
1.3
24
22
20
18
16
Vicm=-20V
Vicm=0V
Vicm=12V
Vicm=70V
Vcc=5V
14
12
10
8
Vcc=3.3V
Vicm=48V
Vref=Vcc/2
SHDN=Vcc
Vsense=0V
T=25°C
6
Vcc=2.7V
Vref=Vcc/2
Vsense=0V
Vcc=5V
4
2
0
-20
-40 -20
0
20
40
60
80
100 120
-10
0
10
20
30
40
50
60
70
Temperature (°C)
Vicm (V)
DS13057 - Rev 4
page 11/54
TSC2010, TSC2011, TSC2012
Typical characteristics
Figure 7. Input bias current vs. input common mode with
shutdown active
Figure 8. Input bias current vs. temperature VCC = 2.7 V
600
500
400
400
300
Iibp
300
200
100
0
Iibp 25°C
Iibp -40 °C
200
100
Iibn
Iibn [-40° : 125°]
0
-100
-200
-300
-400
-500
-600
-100
Iibp 125°C
Vref=Vcc/2
-200
SHDN=Vcc
Vsense=0V
T=25 °C
Vref=VCC/2
Vsense=0V
Vcc=2.7V
-300
Vcc=2.7 to 5.5V
-400
-20 -10
0
10
20
30
40
50
60
70
-20 -10
0
10
20
30
40
50
60
70
Vicm (V)
Vicm (V)
Figure 9. Input bias current vs. temperature with VCC = 5 V
Figure 10. Input offset voltage vs. temperature
600
500
400
700
600
500
Vicm=48V
Vicm=12V
Vicm=70V
400
300
200
100
0
Iibp -40 °C
300
200
100
0
Vicm=-20V
Iibp 25°C
Iibn [-40 °:125 °]
Vicm=0V
-100
-200
-300
-400
-500
-600
-700
-100
-200
-300
-400
-500
-600
Iibp 125°C
Vref=Vcc/2
Vsense=0V
Vcc=5V
Vref=Vcc/2
Vsense=0V
Vcc=5V
-20 -10
0
10
20
30
40
50
60
70
-40 -20
0
20
40
60
80
100 120
Temperature (°C)
Vicm (V)
DS13057 - Rev 4
page 12/54
TSC2010, TSC2011, TSC2012
Typical characteristics
Figure 11. Input offset voltage vs. input common mode
with VCC = 2.7 V
Figure 12. Input offset voltage vs. input common mode
with VCC = 5 V
700
600
700
600
T=125°C
T=125°C
500
500
400
400
300
200
T=25 °C
T=25°C
T=85°C
T=85 °C
300
200
100
0
-100
100
T=-20°C
T=0°C
0
T=-20°C
T=-40°C
-100
T=-40°C
-200
-300
-400
-200
-300
T=0°C
-400
Vref=Vcc/2
Vsense=0V
Vref=Vcc/2
-500
-500
Vsense=0V
Vcc=5V
-600
-700
Vcc=2.7V
-600
-700
-20 -10
0
10
20
30
40
50
60
70
-20 -10
0
10
20
30
40
50
60
70
Vicm(V)
Vicm (V)
Figure 13. Input offset voltage vs. supply voltage
Figure 14. Output current vs. output voltage
40
500
35
30
25
20
15
10
5
400
300
200
100
0
Vicm=12V
Isink
Vicm=5V
Vcc=2.7V
Vcc=3.3V
Vcc=5.5V
0
-5
Vicm=1V
Vicm=48V
Vicm= -20V
Vicm= -10V
-100
-200
-300
-400
-500
-10
-15
-20
-25
-30
-35
-40
Vicm=70V
Vref=Vcc/2
Vsense=100mV
Vicm=12V
Vref=Vcc/2
Vsense=0V
T=25°C
Isource
T=25°C
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
3.0
3.5
4.0
Vcc (V)
4.5
5.0
5.5
Vout (V)
DS13057 - Rev 4
page 13/54
TSC2010, TSC2011, TSC2012
Typical characteristics
Figure 15. Output current vs. temperature with VCC = 5 V Figure 16. Output current vs. temperature with VCC = 2.7 V
50
45
40
35
30
25
20
15
10
5
50
45
40
35
30
25
20
15
10
5
Vcc=2.7V
Vicm=12V
Vref=Vcc/2
Vsense=100mV
Isink
Isink
Isource
Vcc=5V
Vicm=12V
Vref=Vcc/2
Vsense=100mV
Isource
0
0
-40 -20
0
20
40
60
80 100 120
-40 -20
0
20
40
60
80
100 120
Temperature (°C)
Temperature (°C)
Figure 17. Voh and Vol vs. input common mode voltage
with VCC = 5 V
Figure 18. (Output voltage + Vref) vs. Vsense
unidirectionnal with VCC = 5 V
6.0
Vref=0V
Vcc=5V
T=25 °C
Unidirectionnal
5.4
4.8
4.2
3.6
3.0
2.4
1.8
1.2
0.6
0.0
-0.6
Vcc=5V; Vref=Vcc/2
Vsense=100mV
Rl=10kΩ connected to Vcc/2
T=25 °C
43
34
26
VOL
VOH
17
9
0
-10
0
10 20 30 40 50 60 70 80 90
Vsense (mV)
-20 -10
0
10
20
30
40
50
60
70
Vicm (V)
DS13057 - Rev 4
page 14/54
TSC2010, TSC2011, TSC2012
Typical characteristics
Figure 19. (Output voltage + Vref) vs. Vsense bidirectionnal
with VCC = 5 V
Figure 20. Output rail linearity vs. load with VCC = 5 V
5.5
6.0
Vcc=5V
Vref=Vcc/2
Vcc=5V
T=25°C
Bidirectionnal
5.4
Vicm=12V
Vref=Vcc/2
T=25°C
No load
Rl=10kΩ
4.8
4.2
3.6
3.0
2.4
1.8
1.2
0.6
0.0
-0.6
5.0
4.5
Rl=1kΩ
0.0
Rl=2kΩ
Rl=4.7k Ω
-0.5
-50 -40 -30 -20 -10
0
10 20 30 40 50
Vsense (mV)
Vsense (mV)
Figure 21. Linearity vs. Vsense with VCC = 5 V
Figure 22. Linearity vs. Vsense and temperature
0.15
0.15
0.12
0.09
0.06
0.12
0.09
0.06
Vicm=1V
Vicm=-10V
0.03
T=25°C
0.03
0.00
0.00
-0.03
-0.06
-0.09
-0.12
-0.15
-0.03
-0.06
-0.09
-0.12
-0.15
T=-40°C
Vicm=12V
T=125°C
Vref=Vcc/2
Vcc=5V
T=25°C
Vref=Vcc/2
Vcc=5V
Vicm=12V
-50 -40 -30 -20 -10
0
10 20 30 40 50
-50 -40 -30 -20 -10
0
10 20 30 40 50
Vsense(mV)
Vsense(mV)
DS13057 - Rev 4
page 15/54
TSC2010, TSC2011, TSC2012
Typical characteristics
Figure 24. Gain error vs. input common mode and
temperature
Figure 23. Gain error vs. input common mode
0.30
0.30
0.25
0.20
0.25
0.20
0.15
0.15
0.10
T=125°C
0.10
Vcc=2.7V
0.05
Vcc=3.3V
Vcc=5V
T=25°C
0.05
0.00
0.00
-0.05
-0.10
-0.15
-0.20
-0.25
-0.30
-0.05
-0.10
-0.15
-0.20
-0.25
-0.30
T=-40°C
Vref=Vcc/2
T=25°C
Vref=Vcc/2
Vcc=5V
-20 -10
0
10
20
30
40
50
60
70
-20 -10
0
10
20
30
40
50
60
70
Vicm(V)
Vicm(V)
Figure 25. Load regulation with VCC = 5 V
Figure 26. Gain vs. frequency
1.30
1.25
1.20
1.15
1.10
Vcc = 3.3 V
Vcc = 5 V
40
20
0
Isink
Isource
Vcc = 2.7 V
Vicm=70V
Vicm=12V
Vicm=-20V
Vicm=0V
-20
-40
Vref=Vcc/2
Vsense=19.8mV
Vcc=5V
Vicm = 12 V, Vref = Vcc / 2
Rl = 10kΩ,Cl = 100 pF connected to Vcc / 2
T=25°C
-15.0
-10.0
-5.0
0.0
5.0
10.0
15.0
1
10
100
1000
10000
Iout (mA)
Frequency (kHz)
DS13057 - Rev 4
page 16/54
TSC2010, TSC2011, TSC2012
Typical characteristics
Figure 27. Gain vs. frequency VCC = 5 V
Figure 28. Gain vs. frequency different capacitive load
TSC2012
40
20
0
40
CI = 100 pF
TSC2011
20
TSC2010
CI = 330 pF
0
CI = 470 pF
-20
-20
-40
Vcc=5V, Vicm=12V, Vref=Vcc/2
-40
Vcc = 5 V, Vicm = 12 V, Vref = Vcc/2
Rl = 10kΩ,Cl = 10 pF connected to Vcc/2
RI=10kΩ connected to Vcc/2
1
10
100
1000
10000
1
10
100
1000
10000
Frequency (kHz)
Frequency (kHz)
Figure 29. Gain vs. frequency different capacitive load
(TSC2010)
Figure 30. Gain vs. frequency different capacitive load
(TSC2012)
40
40
Cl = 100 pF
Cl = 100 pF
20
20
Cl = 330 pF
Cl = 330 pF
0
Cl = 470 pF
Cl = 680 pF
0
-20
-40
Cl = 470 pF
Cl = 680 pF
-20
Vcc = 5 V, Vicm = 12 V, Vref = Vcc/2
Rl = 10 kΩ connected to Vcc/2
-40
Vcc = 5 V, Vicm = 12 V, Vref = Vcc / 2
RI = 10kΩ connected to Vcc / 2
1
10
100
1000
10000
1
10
100
1000
10000
Frequency (kHz)
Frequency (kHz)
DS13057 - Rev 4
page 17/54
TSC2010, TSC2011, TSC2012
Typical characteristics
Figure 31. Bandwidth vs. input common mode
Figure 32. Bandwidth vs. input common mode (TSC2010)
1.2M
1.1M
1.1M
T = -40°C
T = 25°C
1.0M
900.0k
800.0k
700.0k
600.0k
500.0k
400.0k
300.0k
200.0k
100.0k
0.0
1.0M
T = -40°C
T = 25°C
900.0k
800.0k
700.0k
T =125°C
600.0k
T = 125°C
500.0k
400.0k
300.0k
Vref = Vcc/2
Vcc= 5 V
Rl = 10kΩ,Cl = 100pF connectedto Vcc/2
200.0k
Vref=Vcc/2
Vcc=5V
100.0k
0.0
Rl=10kΩ, Cl=100pF connected to Vcc/2
-20
-10
0
10
20
30
40
50
60
70
-20
-10 10 20 30 40
0
50
60
70
Vicm (V)
Vicm (V)
Figure 33. Bandwidth vs. input common mode (TSC2012)
Figure 34. Overshoot vs. capacitive load
40
35
30
25
20
15
10
5
1.2M
1.1M
TSC2011
Vsense step= 10mVpp
1.0M
T = -40°C
T = 25°C
TSC2010
Vsense step= 30mVpp
900.0k
800.0k
700.0k
600.0k
T = 125°C
500.0k
400.0k
300.0k
TSC2012
Vsense step= 6 mVpp
Vref = Vcc/2
Vcc= 5 V
200.0k
Vcc= 5 V,
Vref = Vcc/2, Vicm [-20V : 70V],
Rl = 10kΩ, Cl connect to Gnd
Rl = 10kΩ,Cl = 100pF connectedto Vcc/2
100.0k
0.0
0
-20
-10
0
10
20
30
40
50
60
70
100
200
300
400
500
600
700
Vicm (V)
Capacitive load (pF)
DS13057 - Rev 4
page 18/54
TSC2010, TSC2011, TSC2012
Typical characteristics
Figure 35. Small signal response with VCC = 5 V
Figure 36. Small signal response with VCC = 5 V
(TSC2010)
1.0
0.5
50
25
0
Vout
Vsense
0.0
-0.5
-25
Vcc=5V, Vicm=12V, Vsense=10mVpp
T=25°C, Cl=100pF
-1.0
-60µ
-50
20µ
-40µ
-20µ
0
Time (s)
Figure 37. Small signal response with VCC = 5 V
(TSC2012)
Figure 38. Small signal response with VCC= 2.7 V
1.0
0.5
50
25
0
1.0
50
Vout
0.5
25
0
Vout
Vsense
0.0
0.0
Vsense
-0.5
-1.0
-25
-50
-0.5
-25
Vcc=2.7V, Vicm=12V, Vsense=10mVpp
T=25°C, Cl=100pF
Vcc = 5 V, Vicm = 12 V, Vsense = 6 mVpp
T = 25 °C, Cl = 100 pF
-1.0
-60µ
-50
20µ
-60µ
-40µ
-20µ
0
20µ
-40µ
-20µ
0
Time (s)
Time (s)
DS13057 - Rev 4
page 19/54
TSC2010, TSC2011, TSC2012
Typical characteristics
Figure 40. Large signal response with VCC = 5 V
(TSC2010)
Figure 39. Large signal response with VCC = 5 V
3
2
50
25
0
3
2
150
125
100
75
1
1
50
25
Vsense
Vsense
Vout
Vout
0
0
0
-25
-50
-75
-100
-125
-150
Vcc = 5 V,
Vcc=5V,
-1
-2
-3
-1
-2
-3
Vicm = 12 V,
Vsense = 230 mVpp
Cl =100 pF,
T = 25 °C
Vicm=12V,
Vsense=80mVpp
Cl=100pF,
T=25°C
-25
-50
15µ
-5µ
0
5µ
10µ
15µ
-5µ
0
5µ
10µ
Time (s)
Time (s)
Figure 41. Large signal response with VCC = 5 V
(TSC2012)
Figure 42. Large signal response with VCC = 2.7 V
3
2
50
25
0
3
2
150
125
100
75
1
50
1
25
Vsense
Vout
Vsense
Vout
0
0
0
-25
-50
-75
-100
-125
-150
Vcc =5 V,
-1
-2
-3
Vcc=2.7V,
-1
-2
-3
Vicm = 12 V,
Vsense = 45 mVpp
Cl = 100 pF,
T = 25°C
Vicm=12V,
Vsense=40mVpp
Cl=100pF,
T=25°C
-25
-50
-5µ
0
5µ
10µ
15µ
-5µ
0
5µ
10µ
15µ
Time (s)
Time (s)
DS13057 - Rev 4
page 20/54
TSC2010, TSC2011, TSC2012
Typical characteristics
Figure 43. 12 V common mode step response recovery
Figure 44. 50 V common mode step response recovery
5
4
70
60
50
40
30
20
10
0
5
4
20
15
10
5
Vicm
Vicm
Vout
Vout
3
3
2
2
0
1
-10
-20
-30
-40
-50
-60
-70
1
-5
Vcc=5V,
Vcc=5V,
0
0
Vicm edge 10ns,
Vsense=0V, Vref=2.5V
Rl=10kΩ, Cl=100pF,
T=25°C
Vicm edge 10ns,
Vsense=0V, Vref=2.5V
Rl=10kΩ , Cl=100pF,
T=25°C
-10
-15
-20
-1
-2
-1
-2
-10µ
0
10µ
20µ
30µ
-10µ
0
10µ
20µ
30µ
Time (s)
Time (s)
Figure 45. PSRR vs. frequency
Figure 46. CMRR vs. frequency
-120
-100
-80
-60
-40
-20
0
-120
-100
-80
-60
-40
-20
0
Vcc=3.3V
Vcc=2.7V
Vcc=3.3V
Vcc=2.7V
Vcc=5V
Vcc=5V
Vicm=12V
Vicm=12V
Vripple=100mVpp
T=25°C
Vripple=100mVpp
T=25°C
100
1k
10k
100k
1M
10M
100
1k
10k
100k
1M
10M
Frequency(Hz)
Frequency(Hz)
DS13057 - Rev 4
page 21/54
TSC2010, TSC2011, TSC2012
Typical characteristics
Figure 47. Positive overvoltage recovery VCC = 2.7 V
Figure 48. Negative overvoltage recovery VCC = 2.7 V
100
3
2
1
0
200
150
100
50
Vcc=2.7V,
Vicm=12V,
CI=100pF
T=25°C
0
50
Vsense
0
-1
-50
Vout
Vout
Vsense
-100
-150
-200
Vcc=2.7V,
Vicm=12V,
CI=100pF,
T=25°C
0
-2
-3
-50
-100
6µ
-3µ
-2µ
-1µ
0
1µ
2µ
3µ
4µ
5µ
6µ
-3µ
-2µ
-1µ
0
1µ
2µ
3µ
4µ
5µ
Time (s)
Time (s)
Figure 49. Overvoltage recovery vs. Vicm VCC = 5 V
Figure 50. Noise vs. frequency
2.0
10000
1000
100
10
Vref = Vcc / 2
Vcc = 5 V,
T = 25 °C
1.8
Vout = 100 mV drop after Vsense edge
5V
1.5
Negative recovery time
3.3V
1.3
1.0
0.8
0.5
2.7V
Vicm=Vcc/2
Tamb=25°C
Positive recovery time
0.3
1
0.0
-20
100m
1
10
100
1k
10k 100k 1M
-10
0
10
20
30
40
Frequency (Hz)
Vicm (V)
DS13057 - Rev 4
page 22/54
TSC2010, TSC2011, TSC2012
Typical characteristics
Figure 52. Output voltage vs. Vsense beyond the sense
operating
Figure 51. ON/OFF delay for shutdown mode
3
4.0
Vout phase reversal for Vsense<-4V
3.2
2.4
2
1
VSHDN
1.6
Vout
0.8
0
0.0
Vref=Vcc/2
Vsense=20mV,
Vcc=5V, Vicm=12V,
RI=10kΩconnected to Vcc-,
T=25°C
-0.8
-1.6
-2.4
-3.2
-4.0
-1
-2
-3
Vref=Vcc/2
Vcc=5V
Vicm=12V
T=25°C
-10µ
0
10µ 20µ 30µ 40µ 50µ 60µ 70µ
Time (s)
-7 -6 -5 -4 -3 -2 -1
0
1
2
3
4
5
6
7
Vsense (V)
Figure 53. Power up time delay
6
5
Vcc
4
3
2
Vout
1
0
Vref=0V
Vsense=20mV,
Vcc=5V, Vicm=12V,
RI=10kΩ, Cl=100pF connected to Vcc-,
T=25°C
-1
-2
-3
-40µ -20µ
0
20µ 40µ 60µ 80µ 100µ 120µ 140µ
Time (s)
DS13057 - Rev 4
page 23/54
TSC2010, TSC2011, TSC2012
Application information
5
Application information
5.1
Overview
The TSC2011 is especially designed to accurately measure the current by amplifying the voltage across a shunt
resistor connected to its input. This voltage drop Vsense is then amplified by an instrumentation amplifier providing
a max. input offset voltage of 500 µV (25°C) for an input common voltage of 12 V.
The TSC2011 is a fixed gain current sensing amplifier of 60 V/V. Thanks to a thin film resistor, the TSC2011 offers
an extremely precise gain and a very high CMRR performance even in a high frequency range. Moreover, by
fixing the output common mode voltage, the TSC2011 can be either used as unidirectional or bidirectional current
sensing amplifier.
The TSC2011 provides an extended input common range from - 20 V below the negative supply voltage, and up
to 70 V allowing either low-side or high-side current sensing, while the TSC2011 device can operate from 2.7 to
5.5 V.
The parameters are very stable in the full Vcc range and characterization curves show the TSC2011
characteristics at 2.7 V and 5.0 V. Moreover, the main specifications are guaranteed in an extended temperature
range from -40 to 125 °C.
5.2
Theory of operation
The main feature of the TSC2011 is the ability to work with an input common mode voltage largely beyond the
power supply Vcc range (2.7 V to 5.5 V). It is ideal, for example for automotive applications where a reverse
battery can be supported by the TSC2011 without any damage. It also works with 48 V battery applications as the
TSC2011 can support and measure the current on line at voltage up to 70 V. No additional protective components
are needed in that range.
•
Vcc < Vicm < 70 V
In this case, the power supply of the TSC2011 is issued by the input and not only by the Vcc power supply. More
precisely, a current is drawn by the common mode rail as depicted in the Figure 54. Power supply when Vicm
Vcc to power it.
>
Figure 54. Power supply when Vicm > Vcc
DS13057 - Rev 4
page 24/54
TSC2010, TSC2011, TSC2012
Theory of operation
In Figure 55. Input bias current vs. common mode voltage Vcc = 5 V, the current used to power the TSC2011
increases together with the Vicm voltage. The slope represents the internal common mode resistances. The most
part of the current is drawn by the pin In+ as we can see on the iibp curve of Figure 9. Input bias current vs.
temperature with VCC = 5 V the current is around 450 µA. Some of it being Vicm / (R4+R1) and some supplies the
input stage of the circuit, roughly 250 µA. On the In- pin 250 µA is drawn only.
So due to the architecture of the TSC2011, the current to be measured must be much larger than the input bias
current. In case of small current to measure the Iib current must be taken into account.
Figure 55. Input bias current vs. common mode voltage Vcc = 5 V
600
500
400
300
Iibp
200
100
Iibn
0
-100
-200
-300
-400
-500
-600
Vref=Vcc/2
Vsense=0V
Vcc=5V
-20 -10
0
10
20
30
40
50
60
70
Vicm(V)
•
Gnd < Vicm < Vcc
In this manner, the TSC2011 is only powered by the power supply Vcc, and the iib currents are very close to 0 µA
and do not have any impact on the current measurement.
•
- 20 V < Vicm < Gnd
The TSC2011 is fully functional in this range of common mode voltage and has also been characterized.
As the high positive common mode voltage, in this specific range, the TSC2011 is also powered by the input, see
Figure 56. Power supply when Vicm < Gnd.
DS13057 - Rev 4
page 25/54
TSC2010, TSC2011, TSC2012
Theory of operation
Figure 56. Power supply when Vicm < Gnd
Most part of the current is still due to the pin In+ as we can see on the iibp curve of Figure 9. Input bias current vs.
temperature with VCC = 5 V. The current is about - 300 µA, some of it being Vicm / (R4 + R1) and some other
supplies the circuit, roughly 250 µA. A small part of the current, coming from the common mode rail, is also due to
the input In– in order to power the TSC2011, in a range of - 100 µV.
•
Output common mode range
The TSC2011 output common mode voltage level can be set thanks to voltages applied on the Vref1 and Vref2
pins. These two pins allow the device to be set either in bidirectional or in unidirectional operation. The voltage
applied to those pins must not exceed the Vcc range. The different configurations are detailed in the section
Unidirectionnal/Bidirectionnal operation.
As depicted by the Figure 57. Vref powered by an external voltage source, Vref1 and Vref2 pins can be driven by
an external voltage source capable of sourcing/sinking a current following the equation below:
Vicm − Vref
Iref =
(1)
5kΩ + 275kΩ + 25kΩ
Figure 57. Vref powered by an external voltage source
DS13057 - Rev 4
page 26/54
TSC2010, TSC2011, TSC2012
Theory of operation
When the output common mode voltage is supplied by an external power supply, in order to improve the output
voltage measurement, it is recommended to measure the Vout differentially with respect to Vref voltage. It provides
a better CMRR measurement, better noise immunity and also a more accurate Vout voltage. A decoupling
capacitance of 1 nF minimum can be also added to better filter the power supply, and can also be used as a tank
capacitance in case an ADC is connected to this reference voltage.
DS13057 - Rev 4
page 27/54
TSC2010, TSC2011, TSC2012
Unidirectionnal / bidirectionnal operation
5.3
Unidirectionnal / bidirectionnal operation
•
Unidirectional operation
Unidirectional mode of operation allows the device to measure the current through a shunt resistor in one
direction only. The output reference can be ground or Vcc and can be set by using Vref1 and Vref2 pins for
adjustment.
•
Ground referenced
Figure 58. Output reference to ground
In this configuration Vref1 pin and Vref2 pin are connected together to the ground. The output common mode
voltage is then automatically set to GND when no current flows through the Rshunt resistance. This configuration
allows the full scale output in unidirectional mode. It allows a current to be measured as described in
Figure 58. Output reference to ground.
•
Vcc referenced
Figure 59. Output reference to Vcc
DS13057 - Rev 4
page 28/54
TSC2010, TSC2011, TSC2012
Unidirectionnal / bidirectionnal operation
In this configuration Vref1 pin and Vref2 pin are connected together to the Vcc power supply. The output common
mode voltage is then automatically set to Vcc voltage when no current flows through the Rshunt resistance. This
configuration allows the full scale output in unidirectional mode. It measures the current as described in
Figure 59. Output reference to Vcc.
•
Bidirectional operation
Bidirectional mode of operation allows the device to measure currents through a shunt resistor in two directions.
The output reference can be set anywhere within the power supply range. If the output common mode voltage is
set at mid-range, the full scale current measurement range is equal in both directions. This is achieved by
connecting one Vref pin to Vcc and the other Vref pin to Gnd as described by Figure 60. Split supply. It can be
done as well connecting both Vref pins to Vcc / 2 voltage as described by Figure 61. External supply. In case the
current measurement is not equal in both directions, user can set the output in a non-symmetrical configuration,
adjusting Vref according to the user's needs.
•
Split supply
Figure 60. Split supply
The great advantage of this configuration, is that the TSC2011 can be used in bidirectional mode with an output
common mode voltage set at the middle of scale, with an accuracy of 0.1%, without any added external
component or power supply. This configuration creates a midscale offset ratiometric to the power supply.
DS13057 - Rev 4
page 29/54
TSC2010, TSC2011, TSC2012
RSENSE selection
•
External
Figure 61. External supply
In this configuration, Vref1 pin and Vref2 pin are connected together to a reference voltage. The output common
mode voltage is then automatically set to this reference voltage value when no current flows through the Rshunt
resistance. This configuration adjusts the output offset as needed by the application. A DAC for calibration of the
analog chain could also be used.
5.4
R
SENSE
selection
The selection of the shunt resistor is a tradeoff between the dynamic range and power dissipation.
Generally, in high current sensing application, the main focus is to reduce as much as possible the power
dissipation (I²R) by choosing the smallest value of shunt. It could be quite easy if a full scale current to measure is
small.
In low current applications the Rsense value could be higher, to minimize the impact of the offset voltage on the
circuit. Due to input bias current of several µA, the TSC2011 cannot measure the current in the same range, when
the common mode voltage overpasses the power supply voltage (refer to section about theory of operation).
The tradeoff is mainly when a dynamic range of current to measure is large, meaning ability to measure with the
same shunt value from low current to high current. Generally, the current full scale (Imax-Imin) defines the shunt
value thanks to the full output voltage range, the gain of the TSC2011. The TSC2011 can work with a full scale
∆Vout = 100 mV to Vcc - 100 mV with maximum gain accuracy of 0.3%.
At first order, the full current range to measure through Rsense can be defined by equation 2, just by taking the
gain error and input offset voltage as inaccuracy parameters:
Vcc − 200mV
TSC_Gain 1 + Eg
Isense_full_scale*Rsense =
− 2 Vio
(2)
The Vsense parameter is defined in the electrical characteristics following the equation 2.
Its purpose is to highlight that the product Rsense*TSC_gain is determined by the application, and that once one of
these two parameters is selected, the maximum value of the second one can be calculated.
•
If power dissipation in the shunt is the key point, RSense should be chosen as follows:
Pmax
Rsense ≤
Imax²
and then choosing the right gain. For example, for high current to sense, the TSC2012 can offer a gain of
100, in this manner a smaller shunt can be used and so limited power losses. However accuracy can be
lower.
•
Or choosing the product available on the shelf, and then size the shunt resistor value accordingly.
DS13057 - Rev 4
page 30/54
TSC2010, TSC2011, TSC2012
Input offset voltage drift overtemperature
5.5
Input offset voltage drift overtemperature
The maximum input offset voltage drift overtemperature is defined as the offset variation related to the offset value
measured at 25 °C. The signal chain accuracy at 25 °C can be compensated during production at application
level. The maximum input voltage drift overtemperature enables the system designer to anticipate the effect of
temperature variations.
The maximum input voltage drift over temperature is computed using equation 3:
ΔV
io
ΔT
V
T
− V 25°C
io
io
= max
(3)
T − 25°C
Where T = -40 °C and 125 °C.
The TSC2011 datasheet maximum value is guaranteed by measurements on a representative sample size
ensuring a Cpk (process capability index) greater than 1.3.
DS13057 - Rev 4
page 31/54
TSC2010, TSC2011, TSC2012
Error calculation
5.6
Error calculation
The principal source of error, such as: input offset voltage, gain error, common mode rejection ration, are
described separately in the electrical characteristics. This chapter summarizes the most important error to take
into account during a design phase.
•
Input offset voltage error
The equation 2 depicts a first order error calculation just by taking into account the input offset voltage. In a
temperature environment, the deviation of the Vio and the error linked to the input offset on the output voltage can
be written as equation 4:
Vio Error = ± Vio ± Dvio/Dt *Gain
(4)
•
Gain error and shunt resistance accuracy
Gain error = Gain 1 + εgain
(5)
(6)
Rsense error = Gain 1 + εRsense
Where εgain is the gain error 0.3% max for the TSC2011.
Where εRsense is the shunt resistance error. Shunt resistors from 5 mΩ to 100 mΩ are available with 1%
accuracy or better.
•
CMR error
In the electrical characteristics, CMR is specified at one input common mode voltage. So in order to take into
consideration the variation of the input voltage offset depending the Vicm, the calculus must be done till this known
point. Let us get the Vicm = 12 V as reference point.
So the error on Vout due to a common mode voltage variation can be written as the equation 7:
Vicm − 12V
CMR error = ±
*Gain
(7)
CMR
•
Output common mode error (Vocm)
This error can be taken into account when the output common mode voltage is set like suggested in the
Figure 62. Schematic for Vocm error, and so by using the internal divider bridge. Otherwise it is important to take
into consideration the error linked to the voltage source applied on the VRef1 pin and Vref2 pin.
Figure 62. Schematic for Vocm error
The divider bridge is made by two resistances of 50 kΩ given an output common mode voltage of:
Vref1 + Vref2
2
DS13057 - Rev 4
page 32/54
TSC2010, TSC2011, TSC2012
Error calculation
Due to a small mismatch of the internal resistance the error, on the output common mode voltage, can be
described as equation 8:
Vref1 + Vref2
Vocm =
. 1 + εAcc
(8)
2
Where εAcc is the accuracy referred to the output with a typical value of 0.1%.
Noise
•
The Section 4.1 expresses the noise referred to the input of the TSC2011. This device shows a 1/f noise until 10
kHz frequency. Above this limit the white noise density is 29 nV/ Hz , until the bandwidth of the TSC2011.
The noise can be then expressed as two terms, the former related to the 1/f noise and the latter due to the white
noise. If we consider that there is no additional filter on the TSC2011 and it is only bandwidth limited, it can be
considered that over the 750 kHz, there is an attenuation of the noise with a first order filtering. So the equivalent
π
noise bandwidth is 750kHz .
.
2
The RMS value of the output noise is the integration of the spectral noise over the bandwidth of interest and can
be expressed as equation 9:
2
π
2
−9
750000 .
2
10000 29 . 10
−9
29 . 10
enRMS =
∫
df + ∫
df *Gain
(9)
0.1
0.1
f
3
10 . 10
•
Total error
The maximum total error expected on the output of the device can be described as the sum of the different source
described just above. The total output accuracy can be written as equation 10.
Vicm − 12V
Vout
err
= Gain*Rsense* Iload εgain + εRsense + Gain . Vio + Gain .
+
(10)
CMR
Vocm εAcc + noise
Iload is described in Figure 63. Input current and the output noise is described by the equation 9.
Note that the input bias currents are not taken into account in this section, as they are already integrated in the
Vsense. The Figure 63. Input current below depicts the current flowing from the source to the load when the input
common mode voltage is higher than the supply voltage.
Figure 63. Input current
From a calculation approach, when Vicm voltage is beyond Vcc, Iload must be considered as the sum of Isource and
Input bias current (Iib). Note that the input bias current on the pin – is largely lower and can be neglected.
The Figure 63. Input current also expresses that the TSC2011 cannot measure the current in the same order as
input bias current (several hundreds of µA).
DS13057 - Rev 4
page 33/54
TSC2010, TSC2011, TSC2012
Shutdown mode
The linearity is not taken into account in the error calculus as it represents 0.03% of error only and it is negligible.
Nevertheless, as the gain error has been calculated thanks to the best fit line approach, it gives the information
that the gain error can be relatively constant throughout the linear input range of the TSC2011.
The equation 10 has been described for a temperature of 25 °C. For sure with a temperature variation, Dvio/DT
error term must be added. And if the power supply is susceptible to change, the SVR parameter must also be
taken into account.
•
Example
Let us consider that the maximum total error can happen on the output of the TSC2011.
Use case:
•
–
–
–
–
–
–
Vcc = 5 V
Vicm = 24 V
Vocm = 2.5 V
Temperature = 25 °C
Iload = 5 A
Shunt 5 mΩ with 1% accuracy
Theoretically the expected output voltage should be Vout = Rshunt * Iload *60 + Vocm = 4 V.
From the equations above, all the error terms are detailed by using the maximum value of the electrical
characteristics (when available), in order to express as much as possible, the worst case condition. The % error
on output of the following table is expressed in reference of Vout – Vref, so in this typical example: 1.5 V.
Table 6. Gain error
% error on
Error source
Gain error
Calculus
Output voltage error
output
0.3%
2%
−3
4.5 mV
30 mV
60*5 . 10 *5*0.3%
V
error
60*500µV
io
24V − 12V
60*
CMRR error
error
22.7 mV
2.5 mV
1.5%
90
10
20
V
2.5*0.1%
0.2%
ocm
29nV
π
2
0.4% (1)
1.98 mV
Noise
60*
10kHz* ln 10k − ln 0.1 + 750kHz* − 0.1Hz
RMS
Hz
60 mV
Total
4.4%
+1.98 mV
RMS
1. The percentage is based on voltage peak value, which is 3 times RMS value.
So the maximum output voltage in the worst case condition at ambient temperature is 4.060 V + 1.98 mVRMS
instead of 4 V expected. This represents an error on the current reading about 4.4%. 1% more must be added
due to the shunt accuracy.
This calculus comes from all the maximum values and all the error terms which have been added to each other,
meaning that the chance to get 4.4% precision in the use case above is extremely low and on the whole
population, the error is largely smaller.
5.7
Shutdown mode
If the SHDN pin is driven between 0.7 x Vcc and Vcc the TSC2011 enters low power shutdown mode, drawing less
than 20 µA, over the Vcc and Vicm range. In SHDN mode the output is in HiZ state.
DS13057 - Rev 4
page 34/54
TSC2010, TSC2011, TSC2012
Stability
Although there is an internal current source of 500 nA on the SHDN pin, keeping a low state allowing the
TSC2011 to work without any voltage applied on the SHDN pin, it is strongly recommended to apply the dedicated
voltage on the SHDN pin to ensure the full functionality of the TSC2011, especially when fast common mode
variation appears.
The figure below depicts the architecture of the SHDN pin.
Figure 64. SHDN pin
•
•
With GND applied to SHDN pin the TSC2011 is in active mode
With Vcc applied to SHDN pin the TSC2011 is in shutdown mode
5.8
Stability
•
Driving switched capacitive loads
Some ADCs get their signal thanks to a sample and hold capacitor. If before a sampling this capacitance is fully
discharged, a fast current load can appear on the output of the TSC2011 during the sampling phase.
The scope probe in the figure below shows the output voltage of the TSC2011 excited by a 40 pF capacitor with a
3.3 Vpp signal at 50 kHz to simulate the sample and hold circuit of the ADC120.
Figure 65. Capacitive load response at Vcc = 3.3 V
8
7
1000
900
800
700
600
500
400
300
200
100
0
6
5
4
Sample and hold
3
2
1
0
-100
-200
-300
-400
-500
-600
-700
-800
-900
-1000
-1
-2
-3
-4
-5
-6
-7
-8
Vout
Vcc=3.3V, Vicm=1.65V, Vsense=0Vpp
T=25°C,
50kHz square signal of 3.3V amplitude
injected in the output through 40pF
-4µ
0
4µ
8µ
12µ
Time (s)
The ADC120 has a conversion rate of 50 ksps, which is perfect to sample and hold the output of the TSC2011
without any error.
The graph shows the behavior of the output of the TSC2011 under the worst case condition, as for example,
when there is an ADC120 channel change between two measurements.
DS13057 - Rev 4
page 35/54
TSC2010, TSC2011, TSC2012
Stability
If a single channel is used, for sure the change on the sample and hold capacitance are very small, and so the
recovery time is extremely low as described by the figure below.
Figure 66. Capacitive load response at Vcc = 3.3 V with a step of 100 mV
100
80
1000
900
800
700
600
500
400
300
200
100
0
60
Sample and hold
40
20
Vout
0
-100
-200
-300
-400
-500
-600
-700
-800
-900
-1000
-20
-40
-60
-80
-100
Vcc=3.3V, Vicm=1.65V, Vsense=0Vpp
T=25°C,
50kHz square signal of 100mV amplitude
injected in the output through 40pF
-4µ
0
4µ
8µ
12µ
Time (s)
The effect of the ADC sampling and hold can be easily smoothed thanks to an RC filter. As suggested on the
schematic below. The capacitor of the external filter must be chosen much higher than the internal ADC capacitor,
in order to easily absorb the sudden voltage variation on the output due to the sampling and hold of the ADC. The
resistance must be chosen accordingly to the application speed of the system in order not to impact the whole
application. The main advantage of using an RC filter is to have an antialiasing system. For sure the used ADC
must have sample and hold conversion in accordance with the RC filter value, in order to let the output recover
before sampling.
Figure 67. RC filter when driving ADC
In the figure Figure 68. Capacitive load response at Vcc = 3.3 V with 720 kHz RC filter an Rs = 470 Ω resistance
and a Ct = 470 pF capacitance have been set. Given a low-pass filter of 720 kHz and a response time of roughly
660 ns.
In the figure Figure 69. Capacitive load response at Vcc = 3.3 V with 194 kHz RC filter an Rs = 820 Ω resistance
and a Ct = 1 nF capacitance have been set. Given a low-pass filter of 194 kHz and a response time of roughly 2.5
µs.
DS13057 - Rev 4
page 36/54
TSC2010, TSC2011, TSC2012
Stability
Figure 68. Capacitive load response at Vcc = 3.3 V with
720 kHz RC filter
Figure 69. Capacitive load response at Vcc = 3.3 V with
194 kHz RC filter
8
7
1000
900
800
700
600
500
400
300
200
100
0
8
7
1000
900
800
700
600
500
400
300
200
100
0
6
6
5
5
4
4
Sampleandhold
Sampleandhold
3
3
2
2
1
1
0
0
-100
-200
-300
-400
-500
-600
-700
-800
-900
-1000
-100
-200
-300
-400
-500
-600
-700
-800
-900
-1000
-1
-2
-3
-4
-5
-6
-7
-8
-1
-2
-3
-4
-5
-6
-7
-8
Vout
Vout
Vcc=3.3V, Vicm=1.65V, Vsense=0Vpp
T=25°C,
Rs=820Ω,Ct=1nF
50kHzsquaresignal of 3.3Vamplitude
injectedintheoutputthrough40pF
Vcc=3.3V, Vicm=1.65V, Vsense=0Vpp
T=25°C,
Rs=470Ω,Ct=470pF
50kHz squaresignal of 3.3Vamplitude
injectedintheoutput through40pF
-4µ
0
4µ
8µ
12µ
-4µ
0
4µ
8µ
12µ
Time(s)
Time(s)
The value of the added external capacitor must be taken into account. Indeed, if this one is chosen with an
excessive value and the serial resistance with a too small value, the risk of instability on the output of the
TSC2011 is high.
•
Driving large capacitive Cload
Increasing the load capacitance produces gain peaking in the frequency response, with an overshoot and ringing
in the step response.
The figure below, shows the serial resistors that must be added to the output, to make a system stable. The
chosen criteria ensures the stability of the system and it is an overshoot lower than 24%.
Figure 70. Stability criteria with a serial resistor at VCC = 5 V
500
Vcc=5V, Vicm=0V,
Vref=Vcc/2,
T=25°C,
400
300
200
100
0
Stable
Unstable
1
0.1
10
CapacitiveLoad(nF)
100
DS13057 - Rev 4
page 37/54
TSC2010, TSC2011, TSC2012
Power supply recommendation
5.9
Power supply recommendation
In order to decouple correctly the TSC2011, a 100 nF bypass capacitor can be placed between Vcc and Gnd. This
capacitor must be placed as closer as possible to the supply pins. The figure below shows a start-up time with a
decoupling capacitance of 100 nF.
Figure 71. Start-up time with a decoupling capacitance of 100 nF
6
5
4
Vcc
3
Vout
2
1
0
Vref=0V
Vsense=20mV,
Vcc=5V, Vicm=12V,
RI=10k Ω, Cl=10pF connected to Vcc-,
T=25°C
-1
-2
-3
-200µ
0
200µ
400µ
600µ
800µ
Time (s)
Vref pin is used to fix the output common mode voltage and it is driven by a low impedance voltage source and
can be decoupled thanks to a 10 nF bypass capacitor.
A greater bypass capacitor added on Vcc pin and Vref pin helps to enhance CMRR and PSRR performance.
5.10
PCB layout recommendations
The layout of the PCB tracks connected to the current sensing, load and power supply is very important. It is a
good practice to use short and wide PCB traces to minimize voltage drops and parasitic inductance.
When a shunt resistance, lower than 1 Ω, is used, a 4-wire connection technique should be used to sense the
current as described in the schematic below. This technique separates pairs of current carrying and voltage-
sensing electrodes to make more accurate measurements by eliminating the lead and contact resistance from the
measurement.
The track connected to the input pin of the TSC2011 has to be considered as a differential pair, it must have the
same length and width, and ideally placed on the same PCB plane, and above all must be routed as far as
possible from noisy source. As this track carries the input bias current, in a range of hundreds of µA, it can be
designed small but always by taking care of its resistivity. Any via in these input tracks are non-recommended to
avoid any parasitic resistance in this path.
To minimize parasitic impedance over the entire surface, a multi-via technique that connects the bottom and top
layer ground planes together in many locations is often used.
A ground plane generally helps to reduce EMI, that is why a multilayer PCB use is suggested as well as the
ground planes as a shield to protect the internal track. In this case, the digital from the analog ground must be
separated and any ground loop must be avoided. Loop area or antenna must be reduced to minimize EMI impact.
The Figure 72. Recommended layout suggests a possible routing for the TSC2011, in order to minimum parasitic
effect.
DS13057 - Rev 4
page 38/54
TSC2010, TSC2011, TSC2012
EMI rejection ration (EMIRR)
Figure 72. Recommended layout
5.11
EMI rejection ration (EMIRR)
The electromagnetic interference (EMI) rejection ratio, or EMIRR, describes the EMI immunity of current sensing
device. An adverse effect that is common to many current sensing is a change in the offset voltage as a result of
RF signal rectification. A first order internal low pass filter is included on the input of the TSC2011 to minimize
susceptibility to EMIRR. Figure 73 shows the EMIRR on pin IN+, Figure 74 shows the EMIRR on pin IN- of the
TSC2011 measured from 400 MHz up to 2.4 GHz.
Figure 73. EMIRR on pin+
Figure 74. EMIRR on pin-
120
100
80
60
40
20
0
120
100
80
60
40
20
0
Vcc=5V, T=25°C
Prf=-10dBm
Vcc=5V, T=25°C
Prf=-10dBm
400 600 800 1000 1200 1400 1600 1800 2000 2200 2400
400 600 800 1000 1200 1400 1600 1800 2000 2200 2400
Frequency (MHz)
Frequency (MHz)
Figure 75 shows the EMIRR on pin IN+, Figure 76 shows the EMIRR on pin IN- of the TSC2010 measured from
10 MHz up to 2.4 GHz.
DS13057 - Rev 4
page 39/54
TSC2010, TSC2011, TSC2012
EMI rejection ration (EMIRR)
Figure 75. EMIRR on pin+ (TSC2010)
Figure 76. EMIRR on pin- (TSC2010)
120
100
80
60
40
20
0
120
100
80
60
40
20
0
Vcc = 5 V, T = 25°C
Prf = 10 dBm
Vcc = 5 V, T = 25°C
Prf = 10 dBm
200 400 600 800 1000 1200 1400 1600 1800 2000 2200 2400
Frequency (MHz)
200 400 600 800 1000 1200 1400 1600 1800 2000 2200 2400
Frequency (MHz)
DS13057 - Rev 4
page 40/54
TSC2010, TSC2011, TSC2012
Overload recovery
5.12
Overload recovery
Overload recovery is defined as the time required for the current sensing output to recover from a saturated state
to a linear state.
The saturation state occurs when the output voltage gets very close to rails in the application. It results from an
excessive input voltage.
When the output of the TSC2011 enters saturation state, less than 1 µs is needed to get back to a linear state as
shown by Figure 77 and Figure 78.
Figure 47 and Figure 48 show the overvoltage recovery for a VCC = 2.7 V.
Figure 78. Positive overvoltage recovery VCC = ± 2.5 V
Figure 77. Negative overvoltage recovery VCC = ± 2.5 V
DS13057 - Rev 4
page 41/54
TSC2010, TSC2011, TSC2012
Application examples
5.13
Application examples
5.13.1
Half-bridge motor control
The half-bridge topology is very popular in motor control, DC-DC converters, LED lighting control and other
bidirectional loads from a single supply potential.
The TSC2011 provides a feedback control system about current but also detects overload conditions.
The Figure 79. Half-bridge application describes a typical schematic using the TSC2011 in a motor control
application. A 20 mΩ shunt resistance in series with the motor monitors a measurable voltage drop representing
the load current, and the TSC2011 amplifies the Vsense in order to give some information about the current flowing
into the motor in real time. These information are then digitalizing by the 12-bit ADC (ADC120).
Figure 79. Half-bridge application
General overview:
To make the motor rotation occur, the NMOS H1, H2, L1, L2 are driven by a half-bridge quad power MOSFET
driver. We have to consider that the current flows from the 12 V to the GND, through H1 NMOS and L2 NMOS. A
PWM is applied on the NMOS L2 in order to control the current and thus the speed of the motor.
By PWM, the average voltage applied on the motor is controlled. H1 remains always ON and the PWM is applied
on L2. When L2 is turned off, H2 must be turned ON, for freewheeling, allowing the discharge of the motor
inductance current. This phenomenon generates a fast input common mode voltage transition on the TSC2011,
from 0 V to 12 V.
Thanks to a good recovery time due to fast input common mode change, the TSC2011 follows the current flowing
into the motor as depicted by the scope probe in Figure 80. TSC2011 H Bridge application.
The black curve represents the fast Vicm variation step of 12 V in 500 ns when the freewheeling is activated. The
blue curve represents the current flowing into the motor measured with a current probe.
The red curve represents the output voltage - 1.35 V (Vref voltage) of the TSC2011 probe after the RC filter.
The RC filter, used to drive the ADC120, smooths a bit the output signal and adds a small constant time, in the
range of 1 µs.
DS13057 - Rev 4
page 42/54
TSC2010, TSC2011, TSC2012
Application examples
Figure 80. TSC2011 H Bridge application
1.0
0.8
0.6
0.4
0.2
0.0
-0.2
-0.4
1.20
0.96
0.72
0.48
0.24
0.00
-0.24
-0.48
Vicm variation from 0V to 12V
Vout
Current flowing into the motor
-50µ -40µ -30µ -20µ -10µ
0
10µ
20µ
30µ
40µ
50µ
Time(s)
After a fast variation of the input common mode, the TSC2011 needs less than 5 µs to recover its normal
behavior.
5.13.2
Solenoid valve
In automotive applications, the automatic transmission relies on bands and clutches to change gears, and the
only way they can be applied is by fluid pressure. The transmission solenoid is responsible for opening or closing
valves in the valve body to allow transmission fluid to enter, at which point the fluid can pressurize the clutches
and bands. Solenoids consist of a spring loaded plunger wrapped with a coil of wire, and it is generally driven
thanks to a MOS transistor.
In the schematic below the TSC2011 is used in mono directional mode. When the MOS is ON, the current can
flow through the solenoid and actuate this one. The input common mode is high in this case.
When the MOS is turned OFF, as the current stored into the solenoid cannot stop instantaneously, the diode turns
ON allowing a freewheeling to discharge the solenoid resulting in a common mode one diode voltage drop below
ground.
Thanks to its large input common mode range, the TSC2011 can be used for such applications depicted in figure
below.
In order not to saturate the output when no current is flowing into Rsense, a small voltage on Vref has to be applied.
DS13057 - Rev 4
page 43/54
TSC2010, TSC2011, TSC2012
Application examples
Figure 81. Solenoid valve application
DS13057 - Rev 4
page 44/54
TSC2010, TSC2011, TSC2012
Package information
6
Package information
In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages,
depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product
status are available at: www.st.com. ECOPACK is an ST trademark.
DS13057 - Rev 4
page 45/54
TSC2010, TSC2011, TSC2012
SO8 package information
6.1
SO8 package information
Figure 82. SO8 package outline
Table 7. SO-8 mechanical data
Inches
mm
Dim.
Min.
Typ.
Max.
1.75
0.25
Min.
Typ.
Max.
0.069
0.01
A
A1
A2
b
0.1
1.25
0.28
0.17
4.8
0.004
0.049
0.011
0.007
0.189
0.228
0.15
0.48
0.23
5
0.019
0.01
c
D
4.9
6
0.193
0.236
0.154
0.05
0.197
0.244
0.157
E
5.8
6.2
4
E1
e
3.8
3.9
1.27
h
0.25
0.4
0.5
0.01
0.02
0.05
L
1.27
0.016
L1
k
1.04
0.04
0
8 °
1 °
8 °
ccc
0.1
0.004
DS13057 - Rev 4
page 46/54
TSC2010, TSC2011, TSC2012
MiniSO8 package information
6.2
MiniSO8 package information
Figure 83. MiniSO8 package outline
Table 8. MiniSO8 mechanical data
Inches
Dim.
Millimeters
Min.
Typ.
Max.
1.1
Min.
Typ.
Max.
0.043
0.006
0.037
0.016
0.009
0.126
0.203
0.122
A
A1
A2
b
0
0.15
0.95
0.4
0
0.75
0.22
0.08
2.8
0.85
0.03
0.009
0.003
0.11
0.033
c
0.23
3.2
D
3
0.118
0.193
0.118
0.026
0.024
0.037
0.01
E
4.65
2.8
4.9
3
5.15
3.1
0.183
0.11
E1
e
0.65
0.6
0.95
0.25
L
0.4
0°
0.8
0.016
0°
0.031
L1
L2
k
8°
8°
ccc
0.1
0.004
DS13057 - Rev 4
page 47/54
TSC2010, TSC2011, TSC2012
Ordering information
7
Ordering information
Table 9. Order codes
Package
Order code
TSC2010IDT
Gain (V/V)
Packaging
Marking
TSC2010
TSC2010Y
TSC2011
TSC2011Y
TSC2012
TSC2012Y
O117
20
60
TSC2010IYDT (1)
TSC2011IDT
SO8
TSC2011IYDT (1)
TSC2012IDT
100
20
TSC2012IYDT (1)
TSC2010IST
Tape and reel
TSC2010IYST (1)
TSC2011IST
O120
O118
60
MiniSO8
TSC2011IYST (1)
TSC2012IST
O121
O119
100
TSC2012IYST (1)
O122
1. Qualified and characterized according to AEC Q100 and Q003 or equivalent, advanced screening according to AEC Q001 &
Q002 or equivalent.
DS13057 - Rev 4
page 48/54
TSC2010, TSC2011, TSC2012
Revision history
Table 10. Document revision history
Date
Revision
Changes
11-Sep-2019
1
Initial release.
Added new part number TSC2012, Figure 25. Gain vs. frequency (V = 5 V),
CC
Figure 27. Gain vs. different capacitive load (TSC2012), Figure 29. Bandwidth vs.
input common mode (TSC2012) and Figure 32. Small signal response with V = 5 V
CC
(TSC2012).
30-Jan-2020
2
Updated description on the cover page, Figure 30. Overshoot vs. capacitive load,
Figure 42. Overvoltage recovery vs. V , V = 5 V, Table 4. Electrical characteristics
icm
CC
V
= 2.7 V, V
= 12 V, T = 25 °C (unless otherwise specified)., Table 5. Electrical
icm
CC
characteristics (V = 5 V, V
= 12 V, T = 25 °C unless otherwise specified) and
CC
icm
Table 9. Order codes.
Added new part number TSC2010, Figure 75 and Figure 76.
Updated:
- Features and description on the cover page
- |Vsense|, G, BW and SR conditions in Table 4 and Table 5.
- Section 4.1 Typical characteristics.
- Table 9. Order codes.
10-Apr-2020
05-Aug-2020
3
4
Updated Figure 77 and Figure 78.
DS13057 - Rev 4
page 49/54
TSC2010, TSC2011, TSC2012
Contents
Contents
1
2
3
4
Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2
Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
Electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
4.1
Typical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
5
Application information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
5.1
5.2
5.3
5.4
5.5
5.6
5.7
5.8
5.9
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
Theory of operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
Unidirectionnal / bidirectionnal operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
R
SENSE
selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
Input offset voltage drift overtemperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
Error calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
Shutdown mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
Stability. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
Power supply recommendation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
5.10 PCB layout recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
5.11 EMI rejection ration (EMIRR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
5.12 Overload recovery. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
5.13 Application examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
5.13.1 Half-bridge motor control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
5.13.2 Solenoid valve. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
6
7
Package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
6.1
6.2
SOT23-3L package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
MiniSO8 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
DS13057 - Rev 4
page 50/54
TSC2010, TSC2011, TSC2012
List of tables
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Pin description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Electrical characteristics Vcc = 2.7 V, Vicm = 12 V, T = 25 °C (unless otherwise specified). . . . . . . . . . . . . . . . . . . 5
Electrical characteristics (Vcc = 5 V, Vicm = 12 V, T = 25 °C unless otherwise specified). . . . . . . . . . . . . . . . . . . . 8
Gain error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
SO-8 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
MiniSO8 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Table 10. Document revision history. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
DS13057 - Rev 4
page 51/54
TSC2010, TSC2011, TSC2012
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Pin connection (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Supply current vs. supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Supply current vs. input common mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Supply current vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Supply current vs. input common mode with active shutdown mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Input bias current vs. input common mode with shutdown active . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Input bias current vs. temperature VCC = 2.7 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Input bias current vs. temperature with VCC = 5 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Input offset voltage vs. temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Input offset voltage vs. input common mode with VCC = 2.7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Input offset voltage vs. input common mode with VCC = 5 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Input offset voltage vs. supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Output current vs. output voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Output current vs. temperature with VCC = 5 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Output current vs. temperature with VCC = 2.7 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Voh and Vol vs. input common mode voltage with VCC = 5 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
(Output voltage + Vref) vs. Vsense unidirectionnal with VCC = 5 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
(Output voltage + Vref) vs. Vsense bidirectionnal with VCC = 5 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Output rail linearity vs. load with VCC = 5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Linearity vs. Vsense with VCC = 5 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Linearity vs. Vsense and temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Gain error vs. input common mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Gain error vs. input common mode and temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Load regulation with VCC = 5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Gain vs. frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Gain vs. frequency VCC = 5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Gain vs. frequency different capacitive load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Gain vs. frequency different capacitive load (TSC2010) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Gain vs. frequency different capacitive load (TSC2012) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Bandwidth vs. input common mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Bandwidth vs. input common mode (TSC2010). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Bandwidth vs. input common mode (TSC2012). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Overshoot vs. capacitive load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Small signal response with VCC = 5 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Small signal response with VCC = 5 V (TSC2010) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Small signal response with VCC = 5 V (TSC2012) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Small signal response with VCC= 2.7 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Large signal response with VCC = 5 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Large signal response with VCC = 5 V (TSC2010) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Large signal response with VCC = 5 V (TSC2012) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Large signal response with VCC = 2.7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
12 V common mode step response recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
50 V common mode step response recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
PSRR vs. frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
CMRR vs. frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Positive overvoltage recovery VCC = 2.7 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Negative overvoltage recovery VCC = 2.7 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Overvoltage recovery vs. Vicm VCC = 5 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Figure 23.
Figure 24.
Figure 25.
Figure 26.
Figure 27.
Figure 28.
Figure 29.
Figure 30.
Figure 31.
Figure 32.
Figure 33.
Figure 34.
Figure 35.
Figure 36.
Figure 37.
Figure 38.
Figure 39.
Figure 40.
Figure 41.
Figure 42.
Figure 43.
Figure 44.
Figure 45.
Figure 46.
Figure 47.
Figure 48.
Figure 49.
DS13057 - Rev 4
page 52/54
TSC2010, TSC2011, TSC2012
List of figures
Figure 50.
Figure 51.
Figure 52.
Figure 53.
Figure 54.
Figure 55.
Figure 56.
Figure 57.
Figure 58.
Figure 59.
Figure 60.
Figure 61.
Figure 62.
Figure 63.
Figure 64.
Figure 65.
Figure 66.
Figure 67.
Figure 68.
Figure 69.
Figure 70.
Figure 71.
Figure 72.
Figure 73.
Figure 74.
Figure 75.
Figure 76.
Figure 77.
Figure 78.
Figure 79.
Figure 80.
Figure 81.
Figure 82.
Figure 83.
Noise vs. frequency. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
ON/OFF delay for shutdown mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Output voltage vs. Vsense beyond the sense operating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Power up time delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Power supply when Vicm > Vcc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Input bias current vs. common mode voltage Vcc = 5 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Power supply when Vicm < Gnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Vref powered by an external voltage source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Output reference to ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Output reference to Vcc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Split supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
External supply. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Schematic for Vocm error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Input current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
SHDN pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Capacitive load response at Vcc = 3.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Capacitive load response at Vcc = 3.3 V with a step of 100 mV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
RC filter when driving ADC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Capacitive load response at Vcc = 3.3 V with 720 kHz RC filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Capacitive load response at Vcc = 3.3 V with 194 kHz RC filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Stability criteria with a serial resistor at VCC = 5 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Start-up time with a decoupling capacitance of 100 nF. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Recommended layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
EMIRR on pin+. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
EMIRR on pin- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
EMIRR on pin+ (TSC2010) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
EMIRR on pin- (TSC2010) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Negative overvoltage recovery VCC = ± 2.5 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Positive overvoltage recovery VCC = ± 2.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Half-bridge application. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
TSC2011 H Bridge application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Solenoid valve application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
SO8 package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
MiniSO8 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
DS13057 - Rev 4
page 53/54
TSC2010, TSC2011, TSC2012
IMPORTANT NOTICE – PLEASE READ CAREFULLY
STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST
products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST
products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement.
Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of
Purchasers’ products.
No license, express or implied, to any intellectual property right is granted by ST herein.
Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product.
ST and the ST logo are trademarks of ST. For additional information about ST trademarks, please refer to www.st.com/trademarks. All other product or service
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Information in this document supersedes and replaces information previously supplied in any prior versions of this document.
© 2020 STMicroelectronics – All rights reserved
DS13057 - Rev 4
page 54/54
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