TSDC02IJT [STMICROELECTRONICS]
MONO 1 W SPEAKER AND STEREO 160 mW HEADSET BTL DRIVERS WITH DIGITAL VOLUME CONTROL; MONO 1 W喇叭和立体声160毫瓦耳机BTL带数字音量控制驱动器
| 型号： | TSDC02IJT |
| 厂家： | 
ST |
| 描述： | MONO 1 W SPEAKER AND STEREO 160 mW HEADSET BTL DRIVERS WITH DIGITAL VOLUME CONTROL |
| 文件： | 总28页 (文件大小：1227K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TS4851
Mono 1W Speaker and Stereo 160mW Headset
BTL Drivers with Digital Volume Control
■
■
■
Operating from VCC = 3V to 5.5V
Pin Connections (top view)
Rail to rail input/output
Speaker driver with 1 W output @ Vcc = 5V,
THD+N = 1%, F = 1kHz, 8Ω load
Headset drivers with 160 mW output @
Vcc = 5V, THD+N = 1%, F = 1kHz, 32Ω load
Headset output is 30mW in stereo @
Vcc = 3V
THD+N < 0.5% Max @ 20mW into 32Ω BTL,
50Hz < Frequency < 20kHz
32-step digital volume control from -
34.5dB to +12dB
TS485IJT - Flip-chip
TS485EIJT - Lead free Flip-chip
■
■
■
■
■
■
■
■
■
■
+6dB power up volume and full standby
8 different output modes
Pop & click reduction circuitry
Low shutdown current (< 100nA)
Thermal shutdown protection
Flip-chip package 18 x 300µm bumps
Pin Out (top view)
Description
The TS4851 is a low power audio amplifier that
can drive either both a mono speaker or a stereo
headset. To the speaker, it can deliver 400 mW
(typ.) of continuous RMS output power into an 8Ω
load with a 1% THD+N value. To the headset
driver, the amplifier can deliver 30 mW (typ.) per
channel of continuous average power into a
stereo 32 Ω bridged-tied load with 0.5% THD+N
@ 3.3V.
R
OUT<
-
L
GND
VCC
OUT -
R
L
OUT +
OUT +
R
IN
DATA
L
IN
NC
PHONE
IN
VCC
GND
ENB
CLK
SPKR
OUT -
SPKR
OUT+
BYPASS
This device features a 32-step digital volume
control and 8 different output selections. The
digital volume and output modes are controlled
through a three-digit SPI interface bus.
Applications
■
Mobile Phones
Order Codes
Part Number
Temperature Range
Package
Packaging
Marking
TS4851IJT
Flip-Chip
A51
A51
-40, +85°C
Tape & Reel
TS4851EIJT
Lead free Flip-Chip
J = Flip Chip Package - only available in Tape & Reel (JT))
March 2005
Revision 5
1/28
TS4851
Application Information
1 Application Information
Figure 1: Application information for a typical application
Table 1. External component description
Component
Functional Description
C
This is the input coupling capacitor. It blocks the DC voltage at, and couples the input signal to the
amplifier’s input terminals. Cin also creates a highpass filter with the internal input impedance Zin at Fc
in
=1/ (2πi x Zin x Cin).
This is the Supply Bypass capacitor. It provides power supply filtering.
C
s
C
This is the Bypass pin capacitor. It provides half-supply filtering.
B
2/28
SPI Bus Interface
TS4851
2 SPI Bus Interface
Table 2. Pin description
Pin
Functional Description
DATA
CLK
ENB
This is the serial data input pin.
This is the clock input pin.
This is the SPI enable pin active at high level.
2.1 Description of SPI operation
The serial data bits are organized into a field containing 8 bits of data as shown in Table 3. The DATA 0 to
DATA 2 bits determine the output mode of the TS4851 as shown in Table 2. The DATA 3 to DATA 7 bits
determine the gain level setting as illustrated by Table 3. For each SPI transfer, the data bits are written to
the DATA pin with the least significant bit (LSB) first. All serial data are sampled at the rising edge of the
CLK signal. Once all the data bits have been sampled, ENB transitions from logic-high to logic low to
complete the SPI sequence. All 8 bits must be received before any data latch can occur. Any excess CLK
and DATA transitions will be ignored after the height rising clock edge has occurred. For any data
sequence longer than 8 bits, only the first 8 bits will get loaded into the shift register and the rest of the bits
will be disregarded.
Table 3. Bit allocation
DATA
MODES
LSB
DATA 0
DATA 1
DATA 2
DATA 3
DATA 4
DATA 5
DATA 6
DATA 7
Mode 1
Mode 2
Mode 3
gain 1
gain 2
gain 3
gain 4
gain 5
MSB
Table 4. Output mode selection: G from -34.5dB to +12dB (by steps of 1.5dB)
Output
Mode #
1
DATA 2
DATA 1
DATA 0
Rout
Lout
SPKERout
0
1
2
3
4
5
0
0
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
SD
6dBxP
SD
Gx(R+L)
SD
SD
SD
0dBxP
SD
GxR
SD
SD
SD
0dBxP
SD
GxL
SD
Gx(R+L)
+6dBxP
SD
6dBxP
6
7
1
1
1
1
0
1
GxR+0dBxP
GxR+0dBxP
GxL+0dBxP
GxL+0dBxP
1)
SD = Shutdown Mode, P = Phone in Input, R = Rin input and L = Lin input
3/28
TS4851
SPI Bus Interface
DATA 3
Table 5. Volume control settings
K : Gain (dB)
DATA 7
DATA 6
DATA 5
DATA 4
-34.5
-33.0
-31.5
-30.0
-28.5
-27.0
-25.5
-24.0
-22.5
-21.0
-19.5
-18.0
-16.5
-15.0
-13.5
-12.0
-10.5
-9.0
-7.5
-6.0
-4.5
-3.0
-1.5
0.0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1.5
3.0
4.5
6
7.5
9
10.5
12
4/28
SPI Bus Interface
TS4851
Figure 2: SPI timing diagram
5/28
TS4851
Absolute Maximum Ratings
3 Absolute Maximum Ratings
Table 6. Key parameters and their absolute maximum ratings
Symbol
Parameter
Value
Unit
1
VCC
6
V
°C
Supply voltage
T
Operating Free Air Temperature Range
Storage Temperature
-40 to + 85
-65 to +150
150
oper
T
°C
stg
T
Maximum Junction Temperature
°C
j
2
R
200
°C/W
thja
Flip Chip Thermal Resistance Junction to Ambient
Power Dissipation
Pd
Internally Limited
ESD
ESD
Human Body Model
2
kV
V
Machine Model
100
200
Latch-up Immunity
mA
°C
Lead Temperature (soldering, 10sec)
Lead Temperature (soldering, 10sec) for Lead-Free version
250
260
1) All voltages values are measured with respect to the ground pin.
2) Device is protected in case of over temperature by a thermal shutdown active @ 150°C
Table 7. Operating conditions
Symbol
Parameter
Value
Unit
VCC
Supply Voltage
3 to 5.5
V
V
V
Maximum Phone In Input Voltage
Maximum Rin & Lin Input Voltage
Thermal Shut Down Temperature
G
G
to V
to V
phin
ND
ND
CC
CC
VRin/VLin
TSD
V
150
90
°C
°C/W
1
R
thja
Flip Chip Thermal Resistance Junction to Ambient
1) Device is protected in case of over temperature by a thermal shutdown active @ 150°C
6/28
Electrical Characteristics
TS4851
4 Electrical Characteristics
Table 8. Electrical characteristics at VCC = +5V, GND = 0V, Tamb = 25°C (unless otherwise
specified)
Symbol
Parameter
Min.
Typ. Max.
Unit
ICC
Supply Current
mA
Output Mode 7, Vin = 0V, no load
All other output modes, Vin = 0V, no load
8
4.5
11
6.5
ISTANDBY Standby Current
Output Mode 0
µA
0.1
5
2
Voo
Output Offset Voltage (differential)
mV
Vin = 0V
50
0.4
5
Vil
Vih
Po
“Logic low” input Voltage
“Logic high” input Voltage
Output Power
0
1.4
V
V
mW
SPKERout, RL = 8Ω, THD = 1%, F = 1kHz
Rout & Lout, RL = 32Ω, THD = 0.5%, F = 1kHz
800
80
1000
120
THD + N Total Harmonic Distortion + Noise
%
Rout & Lout, Po = 80mW, F = 1kHz, RL = 32Ω
0.5
1
SPKERout, Po = 800mW, F = 1kHz, RL = 8Ω
Rout & Lout, Po = 50mW, 20Hz < F < 20kHz, RL = 32Ω
SPKERout, Po = 40mW, 20Hz < F < 20kHz, RL = 8Ω
0.5
1
SNR
PSRR
Signal To Noise Ratio (A-Weighted)
90
dB
dB
1
Power Supply Rejection Ratio
Vripple = 200mV Vpp, F = 217Hz, Input(s) Terminated 10Ω
70
70
55
57
52
56
Ouput Mode 1
Ouput Mode 2
Ouput Mode 3 (G=+12dB)
Ouput Mode 4 (G=+12dB)
Ouput Mode 5 (G=+12dB)
Ouput Mode 6, 7 (G=+12dB)
G
Digital Gain Range - Rin & Lin
no load
dB
-34.5
+12
Digital gain stepsize
Stepsize
1.5
dB
dB
G ≥ -22.5dB
G < -22.5dB
-0.5
-1
+0.5
+1
Phone In Gain, no load
dB
BTL gain from Phone In to SPKERout
BTL gain from Phone In to Rout & Lout
6
0
Zin
Zin
tes
teh
tel
Phone In Input Impedance
Rin & Lin Input Impedance (all gain setting)
Enable Stepup Time - ENB
Enable Hold Time - ENB
Enable Low Time - ENB
15
37.5
20
20
30
20
50
25
62.5
kΩ
kΩ
ns
ns
ns
tds
tdh
tcs
tch
tcl
Data Setup Time- DATA
Data Hold Time - DATA
Clock Setup time - CLK
Clock Logic High Time - CLK
Clock Logic Low Time - CLK
Clock Frequency - CLK
20
20
20
50
50
DC
ns
ns
ns
ns
ns
MHz
fclk
10
1) Dynamic measurements [20 x log(rms(Vout)/rms(Vripple)]. Vripple is the superimposed sinus signal to Vcc @ F = 217Hz
7/28
TS4851
Electrical Characteristics
Table 9. Electrical characteristics at VCC = +3V, GND = 0V, Tamb = 25°C (unless otherwise
specified)
Symbol
Parameter
Min.
Typ. Max.
Unit
ICC
Supply Current
mA
Output Mode 7, Vin = 0V,no load
All other output modes, Vin = 0V,no load
7.5
4.5
10
6.5
ISTANDBY Standby Current
Output Mode 0
µA
0.1
5
2
Voo
Output Offset Voltage (differential)
mV
Vin = 0V
50
0.4
5
Vil
Vih
Po
“Logic low” input Voltage
“Logic high” input Voltage
Output Power
0
1.4
V
V
mW
SPKERout, RL = 8Ω, THD = 1%, F = 1kHz
Rout & Lout, RL = 32Ω, THD = 0.5%, F = 1kHz
300
20
340
30
THD + N Total Harmonic Distortion + Noise
%
Rout & Lout, Po = 20mW, F = 1kHz, RL = 32Ω
0.5
1
SPKERout, Po = 300mW, F = 1kHz, RL = 8Ω
Rout & Lout, Po = 15mW, 20Hz < F < 20kHz, RL = 32Ω
SPKERout, Po = 250mW, 20Hz < F < 20kHz, RL = 8Ω
0.5
1
SNR
Signal To Noise Ratio (A-Weighted)
86
dB
dB
1
2
PSRR
Power Supply Rejection Ratio
Vripple = 200mV Vpp, F = 217Hz, Input(s) Terminated 10Ω
65
70
54
54
51
53
Ouput Mode 1
Ouput Mode 2
Ouput Mode 3 (G=+12dB)
Ouput Mode 4 (G=+12dB)
Ouput Mode 5 (G=+12dB)
Ouput Mode 6, 7 (G=+12dB)
G
Digital Gain Range - Rin & Lin
no load
dB
-34.5
-
+12
Digital gain stepsize
1.5
dB
dB
Stepsize error
G ≥ -22.5dB
G < -22.5dB
-0.5
-1
+0.5
+1
Phone In Gain, no load
dB
BTL gain from Phone In to SPKERout
BTL gain from Phone In to Rout & Lout
6
0
1
Zin
Zin
15
20
25
kΩ
kΩ
Phone In Input Impedance
1
37.5
50
62.5
Rin & Lin Input Impedance (All Gain Setting)
tes
teh
tel
tds
tdh
tcs
tch
tcl
Enable Stepup Time - ENB
Enable Hold Time - ENB
Enable Low Time - ENB
Data Setup Time- DATA
Data Hold Time - DATA
Clock Setup time - CLK
Clock Logic High Time - CLK
Clock Logic Low Time - CLK
Clock Frequency - CLK
20
20
30
20
20
20
50
50
DC
ns
ns
ns
ns
ns
ns
ns
ns
MHz
fclk
10
1) All PSRR data limits are guaranted by evaluation desgin test.
2) Dynamic measurements [20 x log(rms(Vout)/rms(Vripple)]. Vripple is the superimposed sinus signal to Vcc @ F = 217Hz
8/28
Electrical Characteristics
TS4851
Table 10. Index of graphics
Description
Figure
Page
THD + N vs. Output Power
THD + N vs. Frequency
Output Power vs. Power Supply Voltage
PSRR vs. Frequency
Frequency Response
Signal to Noise Ratio vs. Power Supply Voltage
Crosstalk vs. Frequency
-3 dB Lower Cut Off Frequency vs. Input Capacitor
Current Consumption vs. Power Supply Voltage
Power Dissipation vs. Output Power
Power Derating Curves
Figures 3 to 12
Figures 13 to 22
Figures 23 to 30
Figures 31 to 40
Figures 41 to 44
Figures 45 to 48
Figures 49 to 50
Figures 51 to 52
Figure 53
page 10 to page 11
page 11 to page 13
page 13 to page 14
page 14 to page 16
page 16
page 17
page 18
page 18
page 18
Figures 54 to 57
Figure 58
page 18 to page 19
page 19
-3 dB Lower Cut Off Frequency vs. Gain Setting
Figure 59
page 19
Note: In the graphs that follow, the abbreviations Spkout = Speaker Output, and HDout = Headphone Output are used.
All measurements made with Cin = 220nF, Cb = Cs = 1µF except in PSRR condition where Cs = 0.
9/28
TS4851
Electrical Characteristics
Figure 3: Spkout THD+N vs. output power
(output modes 1, 7)
Figure 6: HDout THD+N vs. output power
(output mode 2)
10
10
RL = 4
Output mode 1, 7
BW < 125 kHz
Ω
RL = 16
Output mode 2
BW < 125 kHz
Ω
Vcc=5V
F=20kHz
Vcc=5V
F=20kHz
Tamb = 25°C
Tamb = 25°C
Vcc=3V
F=20kHz
1
0.1
1
0.1
Vcc=3V
F=20kHz
Vcc=3V
F=1kHz
Vcc=5V
F=1kHz
Vcc=3V
F=1kHz
Vcc=5V
F=1kHz
0.01
0.01
1E-3
0.01
0.1
Output power (W)
1
1E-3
0.01
Output power (W)
0.1
Figure 4: Spkout THD+N vs. output power
(output modes 1, 7)
Figure 7: HDout THD+N vs. output power
(output mode 2)
10
10
RL = 8
Output mode 1, 7
BW < 125 kHz
Ω
Vcc=5V
F=20kHz
RL = 32
Output mode 2
BW < 125 kHz
Ω
Vcc=5V
F=20kHz
Tamb = 25°C
Tamb = 25°C
Vcc=3V
F=20kHz
1
0.1
1
0.1
Vcc=3V
F=20kHz
Vcc=3V
F=1kHz
Vcc=5V
F=1kHz
Vcc=3V
F=1kHz
Vcc=5V
F=1kHz
0.01
0.01
1E-3
0.01
0.1
1
1E-3
0.01
0.1
Output power (W)
Output power (W)
Figure 5: Spkout THD+N vs. output power
(output modes 1, 7)
Figure 8: Spkout THD+N vs. output power
(output mode 3, G=+12dB)
10
10
RL = 16
Output mode 1, 7
BW < 125 kHz
Ω
RL = 4
Out. mode 3; G = +12dB
BW < 125 kHz
Tamb = 25°C
Ω
Vcc=5V
F=20kHz
Vcc=5V
F=20kHz
Tamb = 25°C
Vcc=3V
F=20kHz
1
0.1
Vcc=3V
F=20kHz
1
Vcc=3V
F=1kHz
Vcc=5V
F=1kHz
Vcc=3V
F=1kHz
0.1
Vcc=5V
F=1kHz
0.01
1E-3
0.01
0.1
1
1E-3
0.01
0.1
Output power (W)
1
Output power (W)
10/28
Electrical Characteristics
TS4851
Figure 9: Spkout THD+N vs. output power
(output mode 3, G=+12dB)
Figure 12: HDout THD+N vs. output power
(output mode 4, G=+12dB)
10
10
RL = 8
Out. mode 3; G = +12dB
BW < 125 kHz
Ω
Vcc=5V
F=20kHz
RL = 32
Output mode 4
G = +12dB
Ω
Vcc=5V
F=20kHz
Tamb = 25
°C
Vcc=3V
F=20kHz
BW < 125 kHz
Tamb = 25°C
Vcc=3V
F=20kHz
1
1
0.1
0.01
Vcc=3V
F=1kHz
Vcc=5V
F=1kHz
0.1
Vcc=5V
F=1kHz
Vcc=3V
F=1kHz
1E-3
0.01
0.1
1
1E-3
0.01
0.1
Output power (W)
Output power (W)
Figure 10: Spkout THD+N vs. output power
(output mode 3, G=+12dB)
Figure 13: Spkout THD+N vs. frequency
(output modes 1, 7)
10
10
RL = 4
Output mode 1, 7
BW < 125kHz
Ω
Vcc=5V
F=20kHz
RL = 16
Output mode 3
G = +12dB
BW < 125 kHz
Tamb = 25°C
Ω
Tamb = 25°C
Vcc=3V
F=20kHz
1
0.1
1
0.1
Vcc=3V
P=400mW
Vcc=5V
P=1.1W
Vcc=3V
F=1kHz
Vcc=5V
F=1kHz
0.01
0.01
1E-3
0.01
0.1
1
100
1000
10000
Output power (W)
Frequency (Hz)
Figure 11: HDout THD+N vs. output power
(output mode 4, G=+12dB)
Figure 14: Spkout THD+N vs. frequency
(output modes 1, 7)
10
10
RL = 8
Output mode 1, 7
BW < 125kHz
Ω
RL = 16
Output mode 4
G = +12dB
BW < 125 kHz
Tamb = 25°C
Ω
Vcc=5V
F=20kHz
Tamb = 25°C
Vcc=3V
F=20kHz
1
0.1
1
0.1
Vcc=3V
P=320mW
Vcc=5V
P=800mW
Vcc=3V
F=1kHz
Vcc=5V
F=1kHz
0.01
0.01
1E-3
0.01
Output power (W)
0.1
100
1000
10000
Frequency (Hz)
11/28
TS4851
Electrical Characteristics
Figure 15: Spkout THD+N vs. frequency
(output modes 1, 7)
Figure 18: Spkout THD+N vs.frequency
(output mode 3, G = +12 dB)
10
10
RL = 16
Ω
RL = 4
Output mode 3
G = +12dB
BW < 125kHz
Ω
Output mode 1, 7
BW < 125kHz
Tamb = 25°C
1
0.1
Vcc=5V
P=1.1W
Tamb = 25
°C
Vcc=3V
P=150mW
Vcc=5V
P=550mW
1
Vcc=3V
P=400mW
0.1
0.01
100
1000
10000
100
1000
Frequency (Hz)
10000
Frequency (Hz)
Figure 16: HDout THD+N vs. frequency
(output mode 2)
Figure 19: Spkout THD+N vs. frequency
(output mode 3, G = +12 dB)
10
10
RL = 16
Output mode 2
BW < 125kHz
Ω
RL = 8
Output mode 3
G = +12dB
BW < 125kHz
Ω
Tamb = 25°C
1
0.1
Tamb = 25°C
1
Vcc=5V
P=220mW
Vcc=3V
P=40mW
Vcc=3V
P=320mW
Vcc=5V
P=800mW
0.1
0.01
100
1000
10000
100
1000
10000
Frequency (Hz)
Frequency (Hz)
Figure 17: HDout THD+N vs. frequency
(output mode 2)
Figure 20: Spkout THD+N vs. frequency
(output mode 3, G = +12 dB)
10
10
RL = 32
Output mode 2
BW < 125kHz
Ω
RL = 16
Output mode 3
G = +12dB
Ω
Tamb = 25°C
BW < 125kHz
Tamb = 25°C
Vcc=3V
P=180mW
1
0.1
1
0.1
Vcc=5V
P=140mW
Vcc=3V
P=20mW
Vcc=5V
P=550mW
0.01
0.01
100
1000
10000
100
1000
Frequency (Hz)
10000
Frequency (Hz)
12/28
Electrical Characteristics
TS4851
Figure 21: HDout THD+N vs. frequency
(output mode 4, G = +12 dB)
Figure 24: Speaker output power vs. power
supply voltage (output mode 1, 7)
10
2.4
2.0
1.6
1.2
0.8
0.4
0.0
F = 1kHz
Output mode 1, 7
BW < 125kHz
RL = 16
Output mode 4
G = +12dB
BW < 125kHz
Tamb = 25°C
Ω
Tamb = 25°C
Vcc=3V
P=40mW
4
Ω
1
0.1
8
Ω
16
Ω
Vcc=5V
P=220mW
32
Ω
0.01
100
1000
Frequency (Hz)
10000
3.0
3.5
4.0
4.5
5.0
5.5
Vcc (V)
Figure 22: HDout THD+N vs. frequency
(output mode 4, G = +12 dB)
Figure 25: Headphone output power vs. load
resistor (output mode 2)
10
0.35
F = 1kHz
Output mode 2
BW < 125kHz
Tamb = 25°C
RL = 32
Output mode 4
G = +12dB
BW < 125kHz
Ω
0.30
16
Ω
0.25
0.20
0.15
0.10
0.05
0.00
Vcc=3V
P=20mW
1
0.1
Tamb = 25°C
32
Ω
Vcc=5V
P=140mW
64
Ω
0.01
100
1000
Frequency (Hz)
10000
3.0
3.5
4.0
4.5
5.0
5.5
Vcc (V)
Figure 23: Speaker output power vs. power
supply voltage (output mode 1, 7)
Figure 26: Headphone output power vs. load
resistor (output mode 2)
2.0
0.40
F = 1kHz
Output mode 1, 7
F = 1kHz
Output mode 2
0.35
0.30
0.25
0.20
0.15
0.10
0.05
0.00
16
Ω
BW < 125kHz
Tamb = 25°C
BW < 125kHz
Tamb = 25
1.6
°C
4
Ω
32
Ω
1.2
0.8
0.4
0.0
8
Ω
16
Ω
64
Ω
32
Ω
3.0
3.5
4.0
4.5
5.0
5.5
3.0
3.5
4.0
4.5
5.0
5.5
Vcc (V)
Vcc (V)
13/28
TS4851
Electrical Characteristics
Figure 27: Speaker output power vs. power
supply voltage (output mode 3)
Figure 30: Headphone output power vs. load
resistance (output mode 2)
2.0
0.40
F = 1kHz
Output mode 3
F = 1kHz
Output mode 4
0.35
0.30
0.25
0.20
0.15
0.10
0.05
0.00
16
Ω
BW < 125kHz
BW < 125kHz
Tamb = 25
1.6
Tamb = 25
°C
°C
4
Ω
32
Ω
1.2
0.8
0.4
0.0
8
Ω
16
Ω
32
Ω
64
Ω
3.0
3.5
4.0
4.5
5.0
5.5
3.0
3.5
4.0
4.5
5.0
5.5
Vcc (V)
Vcc (V)
Figure 28: Speaker output power vs. power
supply voltage (output mode 3)
Figure 31: Spkout PSRR vs. frequency
(output modes 1, 7, input grounded)
2.4
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
F = 1kHz
Output mode 3
Output mode 1, 7
RL = 8
Vripple = 0.2Vpp
Tamb = 25
Ω
2.0
1.6
1.2
0.8
0.4
0.0
BW < 125kHz
Tamb = 25
°C
4
Ω
°C
8
Ω
Vcc=3V
16
Ω
Vcc=5V
32
Ω
3.0
3.5
4.0
4.5
5.0
5.5
100
1000
10000
100000
Frequency (Hz)
Vcc (V)
Figure 29: Headphone output power vs. load
resistor (output mode 4)
Figure 32: HDout PSRR vs. frequency
(output mode 2, input grounded)
0.35
0
-10
-20
-30
-40
-50
-60
-70
-80
F = 1kHz
Output mode 4
Output mode 2
16
Ω
0.30
0.25
0.20
0.15
0.10
0.05
0.00
RL = 32
Vripple = 0.2Vpp
Tamb = 25
Ω
BW < 125kHz
Tamb = 25
°C
°C
32
Ω
Vcc = 3V & 5V
64
Ω
3.0
3.5
4.0
4.5
5.0
5.5
100
1000
10000
100000
Frequency (Hz)
Vcc (V)
14/28
Electrical Characteristics
TS4851
Figure 33: Spkout PSRR vs. frequency
(output mode 3, inputs grounded)
Figure 36: HDout PSRR vs. frequency
(output mode 4, inputs grounded)
0
-10
-20
-30
-40
-50
-60
-70
0
Output mode 4
Vcc = +3V
-10
RL = 32
Vripple=0.2Vpp
Tamb = 25
Ω
G=+12dB
G=+6dB
G=+9dB
-20
-30
-40
-50
-60
-70
-80
-90
G=+6dB
G=+12dB
G=+9dB
G=-12dB
°C
Output mode 3
Vcc = +5V
G=-12dB
G=0dB
RL = 8
Vripple = 0.2Vpp
Tamb = 25
Ω
G=0dB
G=-34.5dB
10000 100000
°
G=-34.5dB
1000
Frequency (Hz)
100
1000
Frequency (Hz)
100
10000
100000
Figure 34: Spkout PSRR vs. frequency
Figure 37: Spkout PSRR vs. frequency
(output mode 3, inputs grounded)
(output mode 5, inputs grounded)
0
-10
-20
-30
-40
-50
-60
-70
-80
0
-10
-20
-30
-40
-50
-60
-70
Output mode 5
Vcc = +5V
Output mode 3
Vcc = +3V
G=+6dB
G=+12dB
RL = 8
Ω
RL = 8
Vripple=0.2Vpp
Tamb = 25
Ω
Vripple=0.2Vpp
Tamb = 25
G=+12dB
G=+9dB
G=-12dB
°C
°C
G=+6dB
G=+9dB
G=0dB
G=-34.5dB
G=-34.5dB
G=-12dB
10000
G=0dB
1000
100
100000
100
1000
10000
100000
Frequency (Hz)
Frequency (Hz)
Figure 35: HDout PSRR vs. frequency
Figure 38: Spkout PSRR vs. frequency
(output mode 4, inputs grounded)
(output mode 5, inputs grounded)
0
-10
-20
-30
-40
-50
-60
-70
-80
0
-10
-20
-30
-40
-50
-60
-70
Output mode 4
Vcc = +5V
Output mode 5
Vcc = +3V
RL = 8
Vripple=0.2Vpp
Tamb = 25
G=+6dB
G=+12dB
G=+9dB
G=-12dB
RL = 32
Vripple=0.2Vpp
Tamb = 25
Ω
Ω
G=+12dB
G=+6dB
G=+9dB
G=-12dB
°C
°C
G=0dB
G=0dB
G=-34.5dB
10000
G=-34.5dB
100
1000
Frequency (Hz)
100000
100
1000 10000
Frequency (Hz)
100000
15/28
TS4851
Electrical Characteristics
Figure 39: HDout PSRR vs. frequency (output
modes 6, 7, inputs grounded)
Figure 42: HDout frequency response
(output mode 2)
0
-2
-4
-6
0
Output mode 6, 7
-10
-20
-30
-40
-50
-60
-70
Vcc = +5V
RL = 32
Vripple=0.2Vpp
Tamb = 25
G=+6dB
Ω
Vcc=3V
Vcc=5V
°C
G=+12dB
G=+9dB
G=-12dB
Output mode 2
RL = 32
Cin = 220 nF
Ω
G=0dB
G=-34.5dB
10000
BW < 125 kHz
Tamb = 25
°C
100
1000
Frequency (Hz)
100000
20
100
1000
Frequency (Hz)
10000
Figure 40: HDout PSRR vs. freq., (output
modes 6, 7, inputs grounded)
Figure 43: Spkout frequency response
(output mode 3)
12
10
0
Output mode 6, 7
-10
Vcc = +3V
G=+6dB
Vcc=5V
Vcc=3V
RL = 32
Vripple=0.2Vpp
Tamb = 25
Ω
-20
-30
-40
-50
-60
-70
G=+12dB
8
6
4
2
0
°C
G=+9dB
G=-12dB
Output mode 3
RL = 8
Ω
G = +12dB
Cin = 220 nF
BW < 125 kHz
G=0dB
G=-34.5dB
10000 100000
Tamb = 25
°C
100
1000
Frequency (Hz)
20
100
1000
Frequency (Hz)
10000
Figure 41: Spkout frequency response
(output mode 1, 7)
Figure 44: HDout frequency response
(output mode 4)
6
12
10
Vcc=5V
Vcc=3V
Vcc=3V
4
2
0
Vcc=5V
8
6
4
2
0
Output mode 4
RL = 32
Ω
Output mode 1, 7
RL = 8
Cin = 220 nF
BW < 125 kHz
Tamb = 25
G = +12dB
Cin = 220 nF
BW < 125 kHz
Ω
Tamb = 25
°C
°C
20
20
100
1000
Frequency (Hz)
10000
100
1000
10000
Frequency (Hz)
16/28
Electrical Characteristics
TS4851
Figure 45: Spkout SNR vs. power supply
voltage, unweighted filter,
Figure 47: HDout SNR vs. power supply
voltage, unweighted filter,
BW = 20 Hz to 20 kHz
BW = 20 Hz to 20 kHz
100
100
98
96
94
92
90
88
86
84
82
80
78
76
Vcc=3V
Vcc=3V
Vcc=5V
98
Vcc=5V
96
RL = 8
Ω
RL = 32
Ω
94
92
90
88
86
84
82
80
78
76
Unweighted filter (20Hz to 20kHz)
THD + N < 0.7%
Tamb = 25°C
Unweighted filter (20Hz to 20kHz)
THD + N < 0.7%
Tamb = 25°C
G=+12dB
G=+12dB
1
2
3
4
5
6
7
1
2
3
4
Output mode
5
6
7
Output mode
Figure 46: Spkout SNR vs. power supply
voltage, weighted filter A,
Figure 48: HDout SNR vs. power supply
voltage, weighted filter A,
BW = 20 Hz to 20 kHz
BW = 20 Hz to 20 kHz
104
104
Vcc=3V
Vcc=3V
Vcc=5V
Vcc=5V
RL = 32
Weighted filter type A
THD + N < 0.7%
102
102
100
98
RL = 8
Ω
Ω
100
98
96
94
92
90
88
86
Weighted filter type A
THD + N < 0.7%
Tamb = 25°C
Tamb = 25°C
96
94
92
G=+12dB
90
G=+12dB
88
86
1
2
3
4
5
6
7
1
2
3
4
5
6
7
Output mode
Output mode
17/28
TS4851
Electrical Characteristics
Figure 49: Crosstalk vs. frequency
(output mode 4)
Figure 52: -3 dB lower cut off frequency vs.
input capacitance
0
Rin & Lin Inputs
All gain setting
Tamb=25°C
Output mode 4
Vcc = 5V
RL = 32
Ω
-20
-40
-60
-80
G = +12dB
Pout = 100mW
BW < 125kHz
10
Typical Input
Impedance
Tamb = 25°C
Minimum Input
Impedance
Lout -> Rout
Rout -> Lout
Maximum Input
Impedance
1
0.1
1
20
100
1000
10000
Input Capacitor (µF)
Frequency (Hz)
Figure 50: Crosstalk vs. frequency
(output mode 4)
Figure 53: Current consumption vs.
power supply voltage
0
10
No loads
Tamb = 25°C
Output mode 4
Vcc = 3V
9
8
7
6
5
4
3
2
1
0
Mode 7
RL = 32
Ω
-20
-40
-60
-80
G = +12dB
Pout = 20mW
BW < 125kHz
Mode 2, 4, 6
Tamb = 25°C
Lout -> Rout
Rout -> Lout
Reset state
Mode 1, 3, 5
100
1000
10000
0
1
2
3
4
5
Frequency (Hz)
Vcc (V)
Figure 51: -3 dB lower cut off frequency vs.
input capacitor
Figure 54: Power dissipation vs. output power
(speaker output)
100
1.4
Phone In Input
Vcc=5V
Tamb=25°C
F=1kHz
THD+N<1%
1.2
RL=4Ω
1.0
0.8
0.6
0.4
0.2
0.0
Typical Input
Impedance
Minimum Input
Impedance
RL=8
Ω
10
Maximum Input
Impedance
RL=16
Ω
0.1
1
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
Output Power (W)
Input Capacitor ( F)
18/28
Electrical Characteristics
TS4851
Figure 55: Power dissipation vs. output power
(speaker output)
Figure 58: Power derating curves
0.5
100
Rin & Lin Inputs
Vcc=3V
Input Impedance is Nominal
Tamb=25°C
F=1kHz
THD+N<1%
Cin=100nF
Cin=220nF
RL=4Ω
0.4
0.3
0.2
0.1
0.0
10
RL=8
Ω
RL=16
Ω
Cin=1
µF
Cin=470nF
0
1
-34.5
0.0
0.1
0.2
0.3
0.4
0.5
-20
12
Gain Setting (dB)
Output Power (W)
Figure 56: Power dissipation vs. output power
(headphone output, one channel)
Figure 59: -3 dB lower cut off frequency vs. gain
setting (output modes 3, 4, 5, 6, 7)
1.4
0.4
Vcc=5V
F=1kHz
THD+N<1%
0.3
Heat sink surface = 125mm2
1.2
1.0
0.8
0.6
0.4
RL=16Ω
0.2
0.1
0.0
RL=32Ω
No Heat sink
0.2
0.0
0
25
50
75
100
125
150
0.00
0.05
0.10
0.15
0.20
0.25
Output Power (W)
Ambiant Temperature ( C)
Figure 57: Power dissipation vs. output power
(headphone output one channel)
Table 11. Output noise (all inputs grounded)
Outp
ut
Mode
Unweighted
Filter from 3V
to 5V
Weighted Filter
(A) from 3V to
5V
120
Vcc=3V
F=1kHz
THD+N<1%
100
1
2
3
4
5
6
23µVrms
20µVrms
70µVrms
53µVrms
79µVrms
60µVrms
20µVrms
17µVrms
60µVrms
45µVrms
67µVrms
51µVrms
80
60
40
20
0
RL=16
Ω
RL=32
Ω
0
10
20
30
40
50
60
70
Output Power (mW)
19/28
TS4851
Application Information
5 Application Information
5.1 BTL configuration principles
The TS4851 integrates 3 monolithic power amplifier having BTL output. BTL (Bridge Tied Load) means
that each end of the load is connected to two single-ended output amplifiers. Thus, we have:
Single ended output 1 = Vout1 = Vout (V)
Single ended output 2 = Vout2 = -Vout (V)
and
Vout1 - Vout2 = 2Vout (V)
The output power is:
2
(2 Vout RMS
RL
)
Pout =
(W)
For the same power supply voltage, the output power in BTL configuration is four times higher than the
output power in single ended configuration.
5.2 Power dissipation and efficiency
Hypotheses:
Voltage and current in the load are sinusoidal (Vout and Iout).
Supply voltage is a pure DC source (Vcc).
Regarding the load we have:
VOUT = VPEAK sinωt (V)
and
VOUT
IOUT = ---------------- (A)
RL
and
2
VPEAK
POUT = ---------------------- ( W )
2RL
Then, the average current delivered by the supply voltage is:
VPEAK
πRL
ICC
= 2------------------- (A)
AVG
The power delivered by the supply voltage is:
Psupply = Vcc Icc
(W)
AVG
Then, the power dissipated by each amplifier is
Pdiss = Psupply - Pout (W)
2 2 VCC
P
=
POUT − POUT (W)
diss
π RL
20/28
Application Information
TS4851
and the maximum value is obtained when:
∂Pdiss
--------------------- = 0
∂POUT
and its value is:
2Vcc2
π2RL
Pdissmax =
(W)
Note: This maximum value is depends only on power supply voltage and load values.
The efficiency is the ratio between the output power and the power supply:
POUT
πVPEAK
η = ----------------------- =-----------------------
Psupply
4VCC
The maximum theoretical value is reached when Vpeak = Vcc, so:
π
---- = 78.5%
4
The TS4851 has three independent power amplifiers. Each amplifier produces heat due to its power
dissipation. Therefore, the maximum die temperature is the sum of each amplifier’s maximum power
dissipation. It is calculated as follows:
P
P
= Power dissipation due to the speaker power amplifier.
diss speaker
= Power dissipation due to the Headphone power amplifier
diss head
Total P
= P
+ P
+ P (W)
diss head2
diss
diss speaker
diss head1
In most cases, P
= P
, giving:
diss head1
diss head2
Total P
= P
+ 2P
(W)
diss
diss speaker
diss head
⎡
⎢
⎤
⎥
POUT SPEAKER
POUT HEAD
2 2 VCC
TotalPdiss
=
+ 2
π
RL SPEAKER
RLHEAD
⎢
⎥
⎣
⎦
−
[POUT SPEAKER + 2POUT HEAD
]
(W)
The following graph (Figure 60) shows an example of the previous formula, with Vcc set to +5V,
set to 8Ω and R set to 16Ω.
R
load speaker
load headphone
Figure 60: Example of total power dissipation vs. speaker and headphone output power
21/28
TS4851
Application Information
5.3 Low frequency response
In low frequency region, the effect of Cin starts. Cin with Zin forms a high pass filter with a -3dB cut off
frequency.
1
2 π Zin Cin
FCL
=
(Hz)
Zin is the input impedance of the corresponding input:
•
•
20kΩ for Phone In IHF input
50kΩ for the 3 other inputs
Note: For all inputs, the impedance value remains constant for all gain settings. This means that the lower cut-off
frequency doesn’t change with gain setting. Note also that 20kΩ and 50kΩ are typical values and there are
tolerances around these values (see Electrical Characteristics on page 7).
In Figures 39 to 41, you could easily establish the Cin value for a -3dB cut-off frequency required.
5.4 Decoupling of the circuit
Two capacitors are needed to bypass properly the TS4851, a power supply bypass capacitor Cs and a
bias voltage bypass capacitor Cb.
Cs has especially an influence on the THD+N in high frequency (above 7kHz) and indirectly on the power
supply disturbances.
With 1µF, you could expect similar THD+N performances like shown in the datasheet.
If Cs is lower than 1µF, THD+N increases in high frequency and disturbances on the power supply rail are
less filtered.
To the contrary, if Cs is higher than 1µF, those disturbances on the power supply rail are more filtered.
Cb has an influence on THD+N in lower frequency, but its value is critical on the final result of PSRR with
input grounded in lower frequency:
•
•
If Cb is lower than 1µF, THD+N increases at lower frequencies and the PSRR worsens upwards.
If Cb is higher than 1µF, the benefit on THD+N and PSRR in the lower frequency range is small.
5.5 Startup time
When the TS4851 is controlled to switch from the full standby mode (output mode 0) to another output
mode, a delay is necessary to stabilize the DC bias. This delay depends on the Cb value and can be
calculated by the following formulas.
Typical startup time = 0.0175 x Cb (s)
Max. startup time = 0.025 x Cb (s)
(Cb is in µF in these formulas)
These formulas assume that the Cb voltage is equal to 0V. If the Cb voltage is not equal to 0V, the startup
time will be always lower.
The startup time is the delay between the negative edge of Enable input (see Description of SPI operation
on page 3) and the power ON of the output amplifiers.
Note: When the TS4851 is set in full standby mode, Cb is discharged through an internal switch.. The time to reach 0V
of Cb voltage is about ms.
22/28
Application Information
TS4851
5.6 Pop and Click performance
The TS4851 has internal Pop and Click reduction circuitry. The performance of this circuitry is closely
linked with the value of the input capacitor Cin and the bias voltage bypass capacitor Cb.
The value of Cin is due to the lower cut-off frequency value requested. The value of Cb is due to THD+N
and PSRR requested always in lower frequency.
The TS4851 is optimized to have a low pop and click in the typical schematic configuration (see page 2).
Note: The value of Cs is not an important consideration as regards pop and click.
5.7 Notes on PSRR measurement
What is the PSRR?
The PSRR is the Power Supply Rejection Ratio. The PSRR of a device, is the ratio between a power
supply disturbance and the result on the output. We can say that the PSRR is the ability of a device to
minimize the impact of power supply disturbances to the output.
How we measure the PSRR?
The PSSR was measured according to the schematic shown in Figure 61.
Figure 61: PSRR measurement schematic
Principles of operation
•
•
•
The DC voltage supply (Vcc) is fixed.
The AC sinusoidal ripple voltage (Vripple) is fixed.
No bypass capacitor Cs is used.
The PSRR value for each frequency is:
PSRR = 20 × Log
⎡
⎢
⎤
⎥
RMS
RMS
(Output
( Vripple
)
)
(dB )
⎢
⎣
⎥
⎦
RMS is a rms selective measurement.
5.8 Power-On Reset
When Power is applied to Vdd, an internal Power On Reset holds the TS4851 in a reset state until the
Supply Voltage reached its nominal value.
The Power On reset has a typical threshold at 1.8V.
23/28
TS4851
Package Information
6 Package Information
Flip-chip - 18 bumps: TS4851JT
Pin out (top view)
R
OUT-
L
7
6
5
GND
OUT -
L
R
OUT +
OUT +
R
IN
VCC
VCC
DATA
ENB
L
IN
4
3
NC
PHONE
IN
SPKR
OUT +
SPKR
OUT -
2
1
BYPASS
GND
CLK
A
B
C
D
E
Note: The solder bumps are on the underside.
Marking (top view):
The following markings are present on the topside of the flip-chip:
The ST logo.
The part number: A51.
A 3-digit date code: YWW.
A dot marking the location of Pin1A.
E
Symbol for
Lead-Free
A51
YWW
24/28
Package Information
TS4851
TS4851 Footprint recommendation
866µm
75µm Min
100µm max.
Φ=250µm
Φ=400µm
433µm
Track
150µm min.
Non Solder mask opening
Pad in Cu 18µm thickness with Flash NiAu (6µm, 0.15µm)
Package mechanical data
Symmetry axis
2440um
Die size: 2170µm x 2440µm 30µm
Die height (including bumps): 600µm 30µm
Bumps diameter: 315µm 50µm
Bumps height: 250µm 40µm
Pitch: 500µm 10µm
Symmetry axis
866um
354um
866um
600um
25/28
TS4851
Daisy Chain Samples
7 Daisy Chain Samples
A daisy chain sample is a “dummy” silicon chip that can be used to test your flip-chip soldering process
and connection continuity. The daisy chain sample features paired connections between bumps, as
shown in the schematic below. On your PCB layout, you should design the bump connections such that
they are complementary to the above schema (meaning that different pairs of bumps are connected on
the PCB side). In this way, by simply connecting an ohmmeter between pin 1A and pin 5A, you can test
the continuity of your soldering process.
The order code for daisy chain samples is given below.
Figure 62: Daisy chain sample mechanical data
2.44 mm
R
OUT-
L
7
6
5
GND
OUT -
L
R
OUT +
OUT +
R
IN
VCC
VCC
DATA
ENB
L
IN
2.17 mm
4
3
NC
PHONE
IN
SPKR
OUT +
SPKR
OUT -
2
1
BYPASS
GND
CLK
A
B
C
D
E
Order code for daisy chain samples
Package
Part Number
TSDC02IJT
Temperature Range
Marking
J
-40, +85°C
•
DC2
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Tape & Reel Specification
TS4851
8 Tape & Reel Specification
Figure 63: Top view of tape and reel
1
1
A
A
User direction of feed
Device orientation
The devices are oriented in the carrier pocket with pin number 1A adjacent to the sprocket holes.
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TS4851
Revision History
9 Revision History
Date
Revision
Description of Changes
01 July 2002
01 April 2003
01 April 2004
01 Jan. 2005
01 March 2005
1
2
3
4
5
First Release
Curves inserted in the document
Curves updated in the document
Leadfree codification added in the document
Realignment of curve data in the document
Informatio n fu rnish ed is bel ieve d to b e accurate a nd rel iab le. H owe ver, STMicro ele ctro nics assu mes no resp onsi bil ity for th e consequences
of useofsuchi nformationnor for any infringement of patents or other rights of third parti es which may result from its use. No licenseis granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specificationsmentioned in this publication are subject
to change without notice. This publication supersedes and replacesall information previously supplied. STMicroelectronics produ cts are no t
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectroni cs.
The ST logo is a registered trademark of STMicroelectronics
Al l other na mes are the pro perty of the ir respe cti ve own ers
© 2005 STMicroelectronics - All rights reserved
STMi croelectronics group of companies
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Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America
www.st.com
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