TSH110ILT [STMICROELECTRONICS]
WIDE BAND, LOW NOISE OPERATIONAL AMPLIFIERS; 宽频带，低噪声运算放大器
| 型号： | TSH110ILT |
| 厂家： | 
ST |
| 描述： | WIDE BAND, LOW NOISE OPERATIONAL AMPLIFIERS |
| 文件： | 总19页 (文件大小：425K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TSH110-111-112-113-114
WIDE BAND, LOW NOISE OPERATIONAL AMPLIFIERS
■ LOW NOISE: 3nV/√Hz
PIN CONNECTIONS (top view)
■ LOW SUPPLY CURRENT: 3.2mA
■ 47mA OUTPUT CURRENT
■ BANDWIDTH: 100MHz
TSH110 : SOT23-5
Output
VCC - 2
Non Inverting Input
1
5
VCC +
■ 5V to 12V SUPPLY VOLTAGE
■ SLEW-RATE: 450V/µs
+ -
Inverting Input
3
4
■ SPECIFIED FOR 100Ω Load
■ VERY LOW DISTORTION
TSH111 : SO8/TSSOP8
NC
1
2
3
4
8
7
6
5
STANDBY
VCC +
Output
NC
■ TINY: SOT23-5, TSSOP and SO PACKAGES
_
+
Inverting Input
Non Inverting Input
VCC -
DESCRIPTION
The singles TSH110 and TSH111, the dual
TSH112, the triple TSH113 and the quad TSH114
are current feedback operational amplifiers featur-
ing a very high slew rate of 450V/µs and a large
bandwidth of 100MHz, with only a 3.2mA quies-
cent supply current. The TSH111 and TSH113
feature a Standby function for each operator. This
function is a power down mode with a high output
impedance.
TSH112 : SO8/TSSOP8
Output1
VCC +
1
2
3
4
8
7
6
5
Inverting Input1
Non Inverting Input1
VCC -
Output2
_
+
Inverting Input2
Non Inverting Input2
_
+
TSH113 : SO14/TSSOP14
These devices operate from ±2.5V to ±6V dual
supply voltage or from 5V to 12V single supply
voltage. They are able to drive a 100Ω load with a
swing of 9V minimum (for a 12V power supply).
STANDBY1
1
2
3
4
5
14
13
Output3
Inverting Input3
STANDBY2
STANDBY3
VCC +
_
+
12 Non Inverting Input3
11 VCC -
The harmonic and intermodulation distortions of
these devices are very low, making this circuit a
good choice for applications requiring wide band-
width with multiple carriers.
10
9
Non Inverting Input1
Non Inverting Input2
Inverting Input2
+
_
+
_
6
7
Inverting Input1
Output1
Output2
8
For board space and weight saving, the TSH110
comes in miniature SOT23-5 package, the
TSH111 comes in SO8 and TSSOP8 packages,
the TSH112 comes in SO8 and TSSOP8 packag-
es, the TSH113 and TSH114 comes in SO14 and
TSSOP14 packages.
TSH114 : SO14/TSSOP14
1
2
3
4
5
14
13
12
Output1
Inverting Input1
Non Inverting Input1
VCC +
Output4
_
+
Inverting Input4
Non Inverting Input4
_
+
11 VCC -
APPLICATIONS
10
9
Non Inverting Input2
Non Inverting Input3
Inverting Input3
+
_
+
_
■ High End Video Drivers
■ Receiver for xDSL
6
7
Inverting Input2
Output2
Output3
8
■ A/D Converter Driver
■ High End Audio Applications
February 2002
1/19
TSH110-TSH111-TSH112-TSH113-TSH114
ABSOLUTE MAXIMUM RATINGS
Symbol
VCC
Parameter
Value
Unit
1)
14
V
Supply Voltage
2)
Vid
±1
V
Differential Input Voltage
3)
Vi
Toper
Tstg
Tj
±6
V
Input Voltage
Operating Free Air Temperature Range
-40 to +85
-65 to +150
150
°C
°C
°C
Storage Temperature
Maximum Junction Temperature
Thermal resistance junction to case
SOT23-5
SO8
80
28
22
37
32
Rthjc
°C/W
SO14
TSSOP8
TSSOP14
Thermal resistance junction to ambiante area
SOT23-5
SO8
250
157
125
130
110
2.0
Rthja
°C/W
kV
SO14
TSSOP8
TSSOP14
Human Body Model
Machine Model
Charged Device Model
ESD
0.2
1.5
4)
ouput short circuit duration
1. All voltages values, except differential voltage are with respect to network ground terminal
2. Differential voltages are non-inverting input terminal with respect to the inverting terminal
3. The magnitude of input and output must never exceed V +0.3V
CC
4. Short-circuits can cause excessive heating. Destructive dissipation can result.
OPERATING CONDITIONS
Symbol
VCC
Parameter
Value
Unit
Supply Voltage
Common Mode Input Voltage Range
5 to 12
V
V
V
CC-+1.5 to VCC+-1.5
Vicm
ORDER CODES
Type
Temperature
Package
TSH110ILT (code K302)
TSH111ID
SOT23-5
SO8
TSH111IDT
TSH111IPT
TSH112ID
SO8
TSSOP8
SO8
TSH112IDT
TSH112IPT
TSH113ID
SO8
-40° to +85°C
TSSOP8
SO14
TSH113IDT
TSH113IPT
TSH114ID
SO14
TSSOP14
SO14
TSH114IDT
TSH114IPT
SO14
TSSOP14
D = Small Outline Package (SO) - also available in Tape & Reel (DT)
P = Thin Shrink Small Outline Package (TSSOP) - only available in Tape & Reel (PT)
L = Tiny Package (SOT23-5) - only available in Tape & Reel (LT)
2/19
TSH110-TSH111-TSH112-TSH113-TSH114
ELECTRICAL CHARACTERISTICS (pages 3 and 4)
Dual Supply Voltage, VCC= ±2.5Volts, R*fb = 680Ω, Tamb = 25 C (unless otherwise specified)
°
Symbol
Parameter
Test Condition
Min.
Typ.
Max.
Unit
DC PERFORMANCE
Tamb
Tmin. < Tamb < Tmax.
min. < Tamb < Tmax.
-1.5
0.3
1
2.0
mV
mV
µV/°C
µA
Vio
∆Vio
Iib+
Input Offset Voltage
T
Input Offset Voltage Drift vs. Temperature
5
Tamb
-10
-3
1.4
2.5
1.9
2.5
750
3.2
3.5
13
7
Non Inverting Input Bias Current
Tmin. < Tamb < Tmax.
Tamb
µA
µA
Iib-
ROL
ICC
Inverting Input Bias Current
Transimpedance
Tmin. < Tamb < Tmax.
RL=100Ω
µA
500
kΩ
Tamb
4
mA
mA
Supply Current per Operator
Tmin. < Tamb < Tmax.
Common Mode Rejection Ratio
(∆Vic/∆Vio)
CMR
SVR
PSR
56
70
60
80
48
dB
dB
dB
Supply Voltage Rejection Ratio
(∆VCC/∆Vio)
Power Supply Rejection Ratio
(∆VCC/∆Vout)
Gain=1, Rload=3.9kΩ
DYNAMIC PERFORMANCE and OUTPUT CHARACTERISTICS
Tamb
RL = 100Ω
1.4
2
V
V
V
V
Voh
High Level Output Voltage
Low Level Output Voltage
T
min. < Tamb < Tmax.
1.9
-1.8
-1.7
RL = 100Ω GND
Tamb
RL = 100Ω
-1.3
Vol
T
min. < Tamb < Tmax.
RL = 100Ω
| Isink
|
Tmin. < Tamb < Tmax.
Output Sink current
20
18
mA
mA
Isource
Tmin. < Tamb < Tmax.
Output Source current
Vout=1Vpk, Rfb*=820Ω//2pF
Load=100Ω
BW
-3dB Bandwidth
Slew Rate
AVCL=+2
81
MHz
AVCL=+2, 2V step
SR
160
230
V/µs
Load=100Ω
Tr
Tf
Rise Time
9
9
ns
ns
%
ns
%
°
for 200mV step
Fall Time
A
VCL=+2, Rfb*=820Ω//2pF
Ov
St
Overshoot
16
Load=100Ω
Settling Time @ 0.05%
Differential gain
Differential phase
60
∆G
∆φ
0.05
0.05
AVCL=+2, RL=100Ω
F=4.5MHz, Vout=1Vpeak
3/19
TSH110-TSH111-TSH112-TSH113-TSH114
Symbol
Parameter
Test Condition
Min.
Typ.
Max.
Unit
NOISE AND HARMONIC PERFORMANCE
en
in
Equivalent Input Voltage Noise
Equivalent Input Current Noise
3
nV/√Hz
pA/√Hz
Frequency : 1MHz
VCL=+2, F=2MHz
8.5
A
RL=100Ω
THD
Total Harmonic Distortion
64.4
dB
Vout=2Vpeak
AVCL=+2, Vout=2Vpp
RL=100Ω
F1=1MHz, F2=1.1MHz
@900kHz
@1.2MHz
@3.1MHz
@3.2MHz
90
90
86
83
IM3
Third order inter modulation product
dBc
MATCHING CHARACTERISTICS
Gf Gain Flatness
Vo1/Vo2 Channel Separation
F=(DC) to 6MHz
0.1
65
dB
dB
AVCL=+2, Vout=2Vpp
F=1MHz to 10MHz
(*) Rfb is the feedback resistance between the output and the inverting input of the amplifier.
4/19
TSH110-TSH111-TSH112-TSH113-TSH114
ELECTRICAL CHARACTERISTICS (pages 5 and 6)
Dual Supply Voltage, VCC=±6Volts, R*fb = 680Ω, Tamb = 25 C (unless otherwise specified)
°
Symbol
Parameter
TestCondition
Min.
Typ.
Max.
Unit
DC PERFORMANCE
Tamb
Tmin. < Tamb < Tmax.
min. < Tamb < Tmax.
-1.0
0.9
1.3
5
3.0
mV
mV
µV/°C
µA
Vio
∆Vio
Iib+
Input Offset Voltage
T
Input Offset Voltage Drift vs Temperature
Tamb
-12
-4
1
14
10
Non Inverting Input Bias Current
Tmin. < Tamb < Tmax.
Tamb
1.7
3
µA
µA
Iib -
ROL
ICC
Inverting Input Bias Current
Transimpedance
Tmin. < Tamb < Tmax.
RL=100Ω
3.4
900
4
µA
600
kΩ
Tamb
5
mA
mA
Supply Current per Operator
Tmin. < Tamb < Tmax.
4.1
Common Mode Rejection Ratio
(∆Vic/∆Vio)
CMR
SVR
PSR
58
72
63
80
49
dB
dB
dB
Supply Voltage Rejection Ratio
(∆Vcc/∆Vio)
Power Supply Rejection Ratio
(∆Vcc/∆Vout)
Gain=1, Rload=3.9kΩ
DYNAMIC PERFORMANCE and OUTPUT CHARACTERISTICS
Tamb
RL = 100Ω
4.5
4.7
4.6
V
V
V
V
Voh
High Level Output Voltage
Low Level Output Voltage
T
min. < Tamb < Tmax.
RL = 100Ω
Tamb
RL = 100Ω
-4.7
-4.6
-4.3
Vol
T
min. < Tamb < Tmax.
RL = 100Ω
| Isink
|
Tmin. < Tamb < Tmax.
Output Sink current
47
46
mA
mA
Isource
Tmin. < Tamb < Tmax.
Output Source current
Vout=1Vpk, Rfb*=680Ω//2pF
Load=100Ω
Bw
-3dB Bandwidth
Slew Rate
AVCL=+2
100
450
MHz
AVCL=+2, 6V step
SR
240
V/µs
Load=100Ω
Tr
Tf
Rise Time
10.4
12.2
17
ns
ns
%
ns
%
°
for 200mV step
Fall Time
A
VCL=+2, Rfb*=680Ω//2pF
Ov
St
Overshoot
Load=100Ω
Settling Time @ 0.05%
Differential gain
Differential phase
40
∆G
∆φ
0.05
0.05
AVCL=+2, RL=100Ω
F=4.5MHz, Vout=2Vpeak
5/19
TSH110-TSH111-TSH112-TSH113-TSH114
Symbol
Parameter
TestCondition
Min.
Typ.
Max.
Unit
NOISE AND HARMONIC PERFORMANCE
en
in
Equivalent Input Voltage Noise
Equivalent Input Current Noise
3
nV/√Hz
pA/√Hz
Frequency : 1MHz
VCL=+2, F=2MHz
8.6
A
RL=100Ω
THD
Total Harmonic Distortion
67.7
dB
Vout=4Vpp
AVCL=+2, Vout=4Vpp
RL=100Ω
F1=1MHz, F2=1.1MHz
@900kHz
@1.2MHz
@3.1MHz
@3.2MHz
82
84
77
73
IM3
Third order inter modulation product
dBc
MATCHING CHARACTERISTICS
Gf Gain Flatness
Vo1/Vo2 Channel Separation
F=(DC) to 6MHz
0.1
65
dB
dB
AVCL=+2, Vout=4Vpp
F=1MHz to 10MHz
(*) Rfb is the feedback resistance between the output and the inverting input of the amplifier.
6/19
TSH110-TSH111-TSH112-TSH113-TSH114
STANDBY MODE
amb = 25°C (unless otherwise specified), VCC=±6Volts
T
Symbol
Parameter
Standby Low Level
Test Condition
Min.
Typ.
Max.
Unit
-
(VCC
-
Vlow
V
VCC
+0.8)
-
+
Vhigh
ICC SBY
Isol
Standby High Level
V
(VCC +2)
(VCC
40
)
Current Consumption per Operator in
Standby mode
26
µA
dB
Input/Output Isolation
F=1MHz
-90
Rout
Cout
31
25
MΩ
pF
Zout
Output Impedance (Rout // Cout)
Time from Standby Mode to Active
Mode
Ton
Toff
2
µs
µs
Time from Active Mode to Standby
Mode
Down to ICC SBY = 40µA
13
TSH111 STANDBY CONTROL pin 8 (SBY)
OPERATOR STATUS
Vlow
Standby
Active
Vhigh
TSH113 STANDBY CONTROL
OPERATOR STATUS
pin 1
(SBY OP1)
pin 2
(SBY OP2)
pin 3
(SBY OP)
OP1
OP1
OP3
Vlow
x
x
x
x
x
Standby
x
x
x
x
x
Vhigh
Active
x
Vlow
Vhigh
x
x
x
x
x
x
x
x
x
Standby
Active
Vlow
x
x
Standby
Active
Vhigh
x
7/19
TSH110-TSH111-TSH112-TSH113-TSH114
(fig.1) Closed Loop Gain vs. Frequency
(fig.2) Closed Loop Gain vs. Frequency
A =+1, R =2.2kΩ, C =2pF, R =100Ω, V =100mVp
A =-1, R =2.2kΩ, C =2pF, R =100Ω, V =100mVp
V
fb
fb
L
in
V
fb
fb
L
in
2
0
-140
-160
-180
-200
-220
-240
-260
-280
-300
2
0
40
Vcc=±2.5V
Vcc=±6V
gain
20
Vcc=±6V
0
Vcc=±2.5V
-2
-2
-20
-40
-60
-80
-100
-120
phase
Vcc=±2.5V
Vcc=±6V
-4
-4
Vcc=±2.5V
Vcc=±6V
-6
-6
-8
-8
-10
-10
1
10
100
1
10
100
Frequency (MHz)
Frequency (MHz)
(fig.3) Closed Loop Gain vs. Frequency
(fig.4) Closed Loop Gain vs. Frequency
A =+2, R =680Ω, C =2pF, R =100Ω, V =100mVp
A =-2, R =680kΩ, C =2pF, R =100Ω, V =100mVp
V
fb
fb
L
in
V fb fb L in
-140
-160
-180
-200
-220
-240
-260
-280
-300
40
Vcc=±2.5V
6
4
6
4
gain
Vcc=±6V
gain
20
Vcc=±2.5V
Vcc=±6V
0
phase
phase
-20
-40
-60
-80
-100
-120
2
2
Vcc=±2.5V
Vcc=±6V
Vcc=±2.5V
Vcc=±6V
0
0
-2
-4
-2
-4
1
10
100
1
10
100
Frequency (MHz)
Frequency (MHz)
(fig.5) Closed Loop Gain vs. Frequency
(fig.6) Closed Loop Gain vs. Frequency
A =+10, R =510Ω, R =100Ω, V =30mVp
A =-10, R =510Ω, R =100Ω, V =30mVp
V
fb
L
in
V fb L in
22
20
18
16
14
12
10
-140
-160
-180
-200
-220
-240
-260
-280
-300
22
20
18
16
14
12
10
40
20
gain
gain
0
Vcc=±6V
Vcc=±2.5V
Vcc=±2.5V
Vcc=±6V
phase
-20
-40
-60
-80
phase
Vcc=±2.5V
Vcc=±6V
Vcc=±2.5V
Vcc=±6V
-100
-120
1
10
100
1
10
100
Frequency (MHz)
Frequency (MHz)
8/19
TSH110-TSH111-TSH112-TSH113-TSH114
(fig.8): Negative Slew Rate
(fig.7): Positive Slew Rate
A =+2, R =680Ω, C =2pF, R =100Ω, Vcc=±6V
A =+2, R =680Ω, C =2pF, R =100Ω, Vcc=±6V
V
fb
fb
L
V fb fb L
0V
0V
5ns /div.
5ns /div.
(fig.9): Positive Slew Rate
(fig.10): Negative Slew Rate
A =+2, R =680Ω, C =2pF, R =100Ω, Vcc=±2.5V
A =+2, R =680Ω, C =2pF, R =100Ω, Vcc=±2.5V
V
fb
fb
L
V fb fb L
0V
0V
5ns /div.
5ns /div.
(fig.11): Input Voltage Noise Level
(fig.12): Vio vs. Power Supply
A =+100, R =1kΩ, Input+ connected to Gnd via 10Ω
Open loop, no load
V
fb
1000
900
800
700
600
500
400
300
200
10
9
8
7
6
5
4
3
2
1
0
5
6
7
8
9
10
11
12
100
1k
10k
100k
1M
Vcc (V)
Frequency (Hz)
9/19
TSH110-TSH111-TSH112-TSH113-TSH114
(fig.13): Icc(-) vs. Power Supply
(fig.14): Icc(+) vs. Power Supply
Open loop, no load
Open loop, no load
-3.3
-3.4
-3.5
-3.6
-3.7
-3.8
-3.9
3.9
3.8
3.7
3.6
3.5
3.4
3.3
5
6
7
8
9
10
10
10
11
11
11
12
12
12
5
6
7
8
9
10
11
12
Vcc (V)
Vcc (V)
(fig.15): Iib(-) vs. Power Supply
Open loop, no load
(fig.16): Iib(+) vs. Power Supply
Open loop, no load
1.0
0.8
0.6
0.4
0.2
0.0
3.2
3.0
2.8
2.6
2.4
2.2
2.0
1.8
5
6
7
8
9
10
11
12
5
6
7
8
9
Vcc (V)
Vcc (V)
(fig.17): Vol vs. Power Supply
Open loop, R =100Ω
(fig.18): Voh vs. Power Supply
Open loop, R =100Ω
L
L
-2.0
-2.5
-3.0
-3.5
-4.0
-4.5
-5.0
5.0
4.5
4.0
3.5
3.0
2.5
2.0
5
6
7
8
9
5
6
7
8
9
10
11
12
Vcc (V)
Vcc (V)
10/19
TSH110-TSH111-TSH112-TSH113-TSH114
(fig.19): Icc vs. Temperature
(fig.20): Icc (Standby) vs. Temperaure
Open loop, no load
Open loop, no load
5
4
30
20
10
0
Icc(+) for Vcc=±6V
3
Icc(+) for Vcc=±2.5V
2
1
0
-1
-2
-3
-4
-5
-10
-20
-30
Icc(-) for Vcc=±2.5V
Icc(-) for Vcc=±6V
-40
-20
0
20
40
60
80
100
-40
-20
0
20
40
60
80
100
Temperature (°C)
Temperature (°C)
(fig.21): ROL vs. Temperature
(fig.22): CMR vs. Temperature
Open loop, no load
Open loop, no load
68
66
1000
950
900
850
800
Vcc=±6V
Vcc=±6V
64
62
Vcc=±2.5V
60
58
Vcc=±2.5V
-40
-20
0
20
40
60
80
100
-40
-20
0
20
40
60
80
100
Temperature (°C)
Temperature (°C)
(fig.23): VOH & VOL vs. Temperature
(fig.24): Slew Rate vs. Temperature
Open loop, R =100Ω
A =+2, R =100Ω
L
V L
6
600
550
500
450
400
350
300
250
200
150
100
VOH for Vcc=±6V
pos. SR for Vcc=±6V
5
4
3
2
VOH for Vcc=±2.5V
1
0
neg. SR for Vcc=±6V
-1
-2
-3
-4
-5
-6
VOL for Vcc=±2.5V
VOL for Vcc=±6V
pos. SR for Vcc=±2.5V
neg. SR for Vcc=±2.5V
-40
-20
0
20
40
60
80
100
-40
-20
0
20
40
60
80
100
Temperature (°C)
Temperature (°C)
11/19
TSH110-TSH111-TSH112-TSH113-TSH114
(fig.25): Group Delay
(fig.26): Gain Flatness
A =+2, R =680Ω, C =2pF, R =100Ω
A =+2, R =680Ω, C =2pF, R =100Ω
V
fb
fb
L
V fb fb L
6.30
6.25
6.20
6.15
6.10
6.05
6.00
5.95
5.90
8
7
6
5
4
3
2
Vcc=±2.5V
Vcc=±2.5V
Vcc=±6V
Vcc=±6V
1k
10k
100k
1M
10M
100M
0.1
1
10
100
Frequency (Hz)
Frequency (MHz)
(fig.27): Frequency Response vs. Load
(fig.28): Frequency Response vs. Load
A =+2, R =680Ω, C =2pF, V =±2.5V, (fig.29)
A =+2, R =680Ω, C =2pF, V =±6V, (fig.29)
V
fb
fb
CC
V fb fb CC
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
C=30pF Rs=30
C=30pF Rs=39
C=100pF Rs=12
C=1nF Rs=6
C=100pF Rs=12
C=1nF Rs=5
1
10
100
1
10
100
Frequency (MHz)
Frequency (MHz)
(fig.29): Capacitive Load Schematic.
measurements on (fig.27) and (fig.28)
+
OUT
TSH11x
Rs(Ω)
_
C
1kΩ
Rfb, 680Ω
RG
680Ω
Cfb 2pF
12/19
TSH110-TSH111-TSH112-TSH113-TSH114
Intermodulation Distortion
A non-ideal output of the amplifier can be de-
scribed by the following development :
The following graphs show the IM3 of the amplifier
in two cases as a function of the output amplitude.
The two-tones input signal is achieved by the mul-
tisource generator Marconi 2026. Each tone has
the same amplitude. The measurement is
achieved by the spectrum analyser HP 3585A.
Both instruments are phase locked to enhance
measurement precision.
V
=C0+C1(Vin)+C2(Vin)2+C3(Vin)3+...+Cn(Vin)n
out
due to a non-linearity in the input-output amplitude
transfert. In the case of V =Asinωt, C is the DC
in
O
n
component, C (V ) is the fundamental, C A is
1
in
n
rd
(fig.30): 3 Order Intermodulation (180kHz &
the amplitude of the harmonics.
280kHz)
A one-frequency or one-tone input signal contrib-
utes to a harmonic distortion. A two-tones input
signal contributes to a harmonic distortion and in-
termodulation product.
A =+4, R =680Ω, no C , R =100Ω, Vcc=±6V
V
fb
fb
L
-60
-65
-70
-75
-80
-85
-90
-95
-100
This intermodulation product or intermodulation
distortion of a two-tones input signal is the first
step of the amplifier study for driving capability in
the case of a multitone signal.
In this case V =Asinω t+Bsinω t, and :
in
1
2
740kHz
380kHz
Vout=
CO+C1(Asinω1t+Bsinω2t)
+
80kHz
C2(Asinω1t+Bsinω2t)2+C3(Asinω1t+Bsinω2t)3
640kHz
+
...Cn(Vin)n
0
1
2
3
4
5
Output Amplitude (Vpeak
)
Vout=
CO+C1(Asinω1t+Bsinω2t)
+
rd
(fig.31): 3
1.1MHz)
Order Intermodulation (1MHz &
C2(A2+B2)/2-(C2/2)(A2cos2ω1t+B2cos2ω2t)
+
A =+2, R =680Ω, C =2pF, R =100Ω, Vcc=±2.5V
V
fb
fb
L
2C2AB(cos(ω1-ω2)t-cos(ω1+ω2)t)
+
(3C3/4)
(A3sinω1t+B3sinω2t+2A2Bsinω2t+2B2Asinω1t)
-60
-65
-70
-75
-80
-85
-90
-95
-100
+
(C3A3sin3ω1t+B3sin3ω2t)
+
(3C3A2B/2)(sin(2ω1-ω2)t-1/2sin(2ω1+ω2)t)
3.2MHz
+
3.1MHz
1.2MHz
(3C3B2A/2)(sin(−ω1+2ω2)t-1/2sin(ω1+2ω2)t)
+
...Cn(Vin)n
900kHz
In this expression, we can recognize the second
order intermodulation IM2 by the frequencies
0.0
0.5
1.0
1.5
2.0
Output Amplitude (Vpeak
)
(ω -ω ) and (ω +ω ) and the third order intermod-
1
2
1
2
ulation IM3 by the frequencies (2ω -ω ), (2ω +ω ),
1
2
1
2
(−ω +2ω ) and (ω +2ω ).
1
2
1
2
13/19
TSH110-TSH111-TSH112-TSH113-TSH114
Printed Circuit Board Layout Considerations
In this range of frequency, printed circuit board
parasitics can affect the closed-loop performance.
The implementation of a proper ground plane in
both sides of the PCB is mandatory to provide low
inductance and low resistance common return.
Most important for controlling the gain flatness
and the bandwidth are stray capacitances at the
output and inverting input. For minimizing the cou-
pling, the space between signal lines and ground
plane will be increased. Connections of the feed-
back components must be as short as possible on
order to decrease the associated inductance
which affect high frequency gain errors. It is very
important to choose external components as small
as possible such as surface mounted devices,
SMD, in order to minimize the size of all the dc and
ac connections.
Nevertheless, the PCB layout has also an effect
on the crosstalk level. Capacitive coupling be-
tween signal wires, distance between critical sig-
nal nodes, power supply bypassing, are the most
significant points.
(fig.33): Crosstalk vs. Frequency.
A =+2, R =680Ω, C =2pF, R =100Ω, Vcc=±6V, ±2.5V
V
fb
fb
L
0
-20
-40
-60
-80
Power Supply Bypassing
A proper power supply bypassing comes very im-
portant for optimizing the performance in high fre-
quency range. Bypass capacitors must be placed
as close as possible to the IC pins to improve high
frequency bypassing. A capacitor greater than
1µF is necessary to minimize the distortion. For a
better quality bypassing a capacitor of 0.1µF will
be added following the same condition of imple-
mentation. These bypass capacitors must be in-
corporated for the negative and the positive sup-
plies.
-100
10k
100k
1M
10M
100M
Frequency (Hz)
Single Power Supply
The TSH11x operates from 12V down to 5V power
supplies. This is achieved with a dual power sup-
ply of ±6V and ±2.5V or a single power supply of
12V and 5V referenced to the ground. In the case
of this asymmetrical supplying, a biasing is neces-
sary to assume a positive output dynamic range
between 0V and +Vcc supply rails. Considering
the values of VOH and VOL, the amplifier will pro-
vide an ouput dynamic from +1.35V to 10.75V for
a 12V supplying, from 0.6V to 4.5V for a 5V sup-
plying.
(fig.32): Circuit for power supply bypassing.
+VCC
1µF
0.1µF
The following figure show the case of a 5V single
power supply configuration.
+
TSH11x
(fig.34): Circuit for +5V single supply.
_
0.1µF
+5V
1µF
10µF
+
IN
+5V
R1
100µF
OUT
50Ω
Rin
1kΩ
TSH11x
-VCC
50Ω
_
5kΩ
Channel Separation or Crosstalk
Rfb, 680Ω
RG
680Ω
The following figure show the crosstalk from an
amplifier to a second amplifier. This phenomenon,
accented in high frequencies, is unavoidable and
intrinsic of the circuit.
10nF
+
1µF
R1
5kΩ
+
Cfb
2pF
CG
14/19
TSH110-TSH111-TSH112-TSH113-TSH114
The amplifier must be biased with a mid supply
(nominaly +Vcc/2), in order to maintain the DC
component of the signal at this value. Several op-
tions are possible to provide this bias supply (such
as a virtual ground using an operational amplifier),
or a two-resistance divider which is the cheapest
solution. A high resistance value is required to lim-
it the current consumption. On the other hand, the
current must be high enough to bias the non-in-
verting input of the amplifier. If we consider this
bias current (5µA) as the 1% of the current
through the resistance divider (500µA) to keep a
stable mid supply, two 5kΩ resistances can be
used.
Assuming a low level active onto the disable pins
(1,2,3) as described on page 7 of the datasheet,
any operator can be disable/enable independent-
ly. The two disabled operators will be in standby
mode featuring a high ouput impedance with a
high input/output isolation and a low quiescent
current.
(fig.36): Typical output response in standby mode on/off
Enabled
Output
The input provides a high pass filter with a break
frequency below 10Hz which is necessary to re-
move the original 0 volt DC component of the input
signal, and to hold it at 2.5V.
Disabled
Output
Video Multiplexing using the TSH113
+2.4V
(fig.35): Circuit for switching 3 video signals with the tri-
ple TSH113.
Standby
Signal
-2.4V
100ns /div.
+
IN1
(fig.37): Typical output response in standby mode off/on
TSH113
_
Enabled
Output
ENABLE1
Rfb, 680Ω
RG
680Ω
Cfb, 2pF
+
Disabled
Output
Common
OUT
IN2
75Ω
75Ω
cable
TSH113
_
+2.4V
75Ω
Standby
Signal
-2.4V
ENABLE2
Rfb, 680Ω
RG
680Ω
10µs /div.
Cfb, 2pF
+
_
IN3
TSH113
ENABLE3
Rfb, 680Ω
RG
680Ω
Cfb, 2pF
15/19
TSH110-TSH111-TSH112-TSH113-TSH114
(fig.38): Input / Output Isolation vs. Frequency..
(tab.1): Closed-loop Gain and Feedback Components.
0.1dB
Bw
(MHz)
-3dB
Bw
Rfb
Cfb
VCC
(V)
Gain
0
-20
-40
-60
-80
(Ω)
(pF)
(MHz)
+10
-10
+2
-2
510
510
680
680
2.2k
2.2k
510
510
680
680
2.2k
2.2k
-
46
42
14
13
50
40
30
20
13
12
25
30
50
18
-
2
2
2
2
-
105
90
±6
Standby mode
+1
-1
170
110
37
-100
-120
+10
-10
+2
-2
0.01
0.1
1
10
100
Frequency (MHz)
-
36
2
2
2
2
93
±2.5
86
Choice of the Feedback Circuit
The TSH11x is a serie of current feedback
amplifiers. For a current feedback structure the
bandwidth depends on the value of the feedback
components and the value of supply voltage.
+1
-1
130
100
A good choice of these components is necessary
to achieve the gain flatness and the stability.
Inverting Amplifier Biasing
In this case a resistance (R on fig.40) is necessary
to achieve a good input biasing.
The following table shows the typical -3dB
bandwidth and 0.1dB bandwidth assuming
different gains and power supply on 100Ω load.
Please see also the Closed Loop Gain vs.
Frequency curves on page 8 of the datasheet.
This resistance is calculated by assuming the
negative and positive input bias current. The aim
is to make the compensation of the offset bias
current which could affect the input offset voltage
and the output DC component.
(fig.39): Non-inverting and Inverting Implementation..
Assuming Ib-, Ib+, Rin, Rfb and a zero volt output,
the resistance R comes : R = Rin // Rfb .
Non-Inverting
Gain = 1+ Rfb / RG
Input
+
(fig.40): Compensation of the Input Bias Current..
Output
_
49.9Ω
50Ω
Rfb
Rfb
RG
Cfb
Rfb
Ib-
Rin
Vcc+
Vcc-
_
Output
Inverting
+
Gain = - Rfb / Rin
Rin
Load
Input
Cfb
_
Ib+
Output
49.9Ω
50Ω
R
+
R
16/19
TSH110-TSH111-TSH112-TSH113-TSH114
PACKAGE MECHANICAL DATA
8 PINS - PLASTIC MICROPACKAGE (SO)
PACKAGE MECHANICAL DATA
8 PINS - THIN SHRINK SMALL OUTLINE
PACKAGE (TSSOP)
k
0,25 mm
.010 inch
c
GAGE PLANE
A
E
A2
A1
PIN 1 IDENTIFICATION
Millimeters
Typ.
Inches
Typ.
Millimeters
Typ.
Inches
Typ.
Dim.
Dim.
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
A
a1
a2
a3
b
1.75
0.069
0.010
0.065
0.033
0.019
0.010
0.020
A
A1
A2
b
1.20
0.15
0.05
0.1
0.25 0.004
1.65
0.05
0.80
0.19
0.09
2.90
0.01
0.006
1.00
1.05 0.031 0.039 0.041
0.65
0.35
0.19
0.25
0.85 0.026
0.48 0.014
0.25 0.007
0.30 0.007
0.20 0.003
0.15
c
0.012
b1
C
D
E
3.00
6.40
4.40
0.65
3.10
0.114 0.118 0.122
0.252
0.5
0.010
c1
D
45° (typ.)
E1
e
4.30
4.50 0.169 0.173 0.177
0.025
4.8
5.8
5.0
6.2
0.189
0.228
0.197
0.244
E
k
0°
8°
0°
8°
e
1.27
3.81
0.050
0.150
l
0.50
0.60
0.75
0.09 0.0236 0.030
e3
F
3.8
0.4
4.0
0.150
0.157
0.050
0.024
L
1.27 0.016
0.6
M
S
8° (max.)
17/19
TSH110-TSH111-TSH112-TSH113-TSH114
PACKAGE MECHANICAL DATA
14 PINS - PLASTIC MICROPACKAGE (SO)
PACKAGE MECHANICAL DATA
14 PINS - THIN SHRINK SMALL OUTLINE
PACKAGE (TSSOP)
k
c
0,25 mm
.010 inch
GAGE PLANE
L
G
c1
b
e
s
e3
D
E
A
E
M
A2
A1
14
1
8
7
8
7
14
1
PIN 1 IDENTIFICATION
Millimeters
Typ.
Inches
Typ.
Millimeters
Typ.
Inches
Typ.
Dim.
Dim.
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
0.05
0.006
A
a1
a2
b
1.75
0.2
0.069
0.008
0.063
0.018
0.010
A
A1
A2
b
1.20
0.15
0.1
0.004
0.05
0.80
0.19
0.09
4.90
0.01
1.6
1.00
1.05 0.031 0.039 0.041
0.35
0.19
0.46 0.014
0.25 0.007
0.30 0.007
0.20 0.003
0.15
b1
C
c
0.012
0.5
0.020
D
E
5.00
6.40
4.40
0.65
5.10 0.192 0.196 0.20
c1
45° (typ.)
0.252
4.50 0.169 0.173 0.177
0.025
D (1) 8.55
8.75 0.336
0.344
0.244
E1
e
4.30
E
e
5.8
6.2
0.228
1.27
7.62
0.050
0.300
k
0°
8°
0°
8°
e3
F (1)
G
l
0.50
0.60
0.75
0.09 0.0236 0.030
3.8
4.6
0.5
4.0
5.3
0.150
0.181
0.157
0.208
0.050
0.027
L
1.27 0.020
0.68
M
S
8° (max.)
Note : (1) D and F do not include mold flash or protrusions - Mold flash
or protrusions shall not exceed 0.15mm (.066 inc) ONLY FOR DATA
BOOK.
18/19
TSH110-TSH111-TSH112-TSH113-TSH114
PACKAGE MECHANICAL DATA
2
5 PINS - TINY PACKAGE (SOT23)
A
E
A2
D
b
A1
L
C
E1
Millimeters
Inches
Dim.
Min.
Typ.
Max.
Min.
Typ.
Max.
A
A1
A2
B
0.90
0
1.20
1.45
0.15
1.30
0.50
0.20
3.00
0.035
0.047
0.057
0.006
0.051
0.020
0.008
0.118
0.90
0.35
0.09
2.80
1.05
0.40
0.15
2.90
1.90
0.95
2.80
1.60
0.5
0.035
0.014
0.004
0.110
0.041
0.016
0.006
0.114
0.075
0.037
0.110
0.063
0.014
C
D
D1
e
E
2.60
1.50
0.10
0d
3.00
1.75
0.60
10d
0.102
0.059
0.004
0d
0.0118
0.069
0.024
10d
F
L
K
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the
consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from
its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications
mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information
previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or
systems without express written approval of STMicroelectronics.
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19/19
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