TSV791 [STMICROELECTRONICS]
High bandwidth (50 MHz) low offset (200 μV) rail-to-rail 5 V op-amp;
| 型号： | TSV791 |
| 厂家： | 
ST |
| 描述： | High bandwidth (50 MHz) low offset (200 μV) rail-to-rail 5 V op-amp |
| 文件： | 总36页 (文件大小：5802K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TSV791, TSV792
Datasheet
High bandwidth (50 MHz) low offset (200 µV) rail-to-rail 5 V op-amp
Features
•
•
•
•
•
•
•
•
•
•
Gain bandwidth product 50 MHz, unity gain stable
Slew rate 30 V/µs
Low input offset voltage 50 µV typ., 200 µV max.
Low input bias current: 2 pA typ.
Low input voltage noise density 6.5 nV/√Hz @ 10 kHz
Wide supply voltage range: 2.2 V to 5.5 V
Rail-to-rail input and output
Extended temperature range: - 40 °C to +125 °C
Automotive grade version available
Benefits:
–
–
Accuracy of measurement virtually unaffected by noise or input bias current
Signal conditioning for high frequencies
Applications
•
•
•
•
•
High bandwidth low-side and high-side current sensing
Photodiode transimpedance amplification
A/D converters input buffers
Power management in solar-powered systems
Power management in automotive applications
Maturity status link
Description
TSV791, TSV792
The TSV791 and TSV792 are single and dual 50 MHz-bandwidth unity-gain-stable
amplifiers. The rail-to-rail input stage and the slew rate of 30 V/µs make the
TSV791 and TSV792 ideal for low-side current measurement. The excellent accuracy
provided by maximum input voltage of 200 µV allows amplifying accurately small-
amplitude input signal. The TSV792 can operate from a 2.2 V to 5.5 V single supply;
it can typically handle an output capacitor up to 1 nF and is fully specified on a load
of 22 pF, therefore allowing easy usage as A/D converters input buffer.
Related products
TSZ181
TSZ182
Zero drift amplifiers with
more power savings (3 MHz)
36 V high-bandwidth
amplifiers (6 MHz)
TSB712
36 V high-bandwidth
amplifiers (20 MHz)
TSB7192
DS13480 - Rev 1 - November 2020
For further information contact your local STMicroelectronics sales office.
www.st.com
TSV791, TSV792
Pin description
1
Pin description
1.1
TSV791 single operational amplifier
Figure 1. Pin connections (top view)
Table 1. Pin description
Pin n°
Pin name
OUT
Description
1
2
3
4
5
Output channel
VCC-
IN+
Negative supply voltage
Non-inverting input channel
Inverting input channel
Positive supply voltage
IN-
VCC+
DS13480 - Rev 1
page 2/36
TSV791, TSV792
TSV792 dual operational amplifier
1.2
TSV792 dual operational amplifier
Figure 2. Pin connections (top view)
1.
The exposed pad of the DFN8 2x2 can be connected to VCC- or left floating.
Table 2. Pin description
Pin n°
Pin name
OUT1
IN1-
Description
1
2
3
4
5
6
7
8
Output channel 1
Inverting input channel 1
Non-inverting input channel 1
Negative supply voltage
Non-inverting input channel 2
Inverting input channel 2
Output channel 2
IN1+
VCC-
IN2+
IN2-
OUT2
VCC+
Positive supply voltage
DS13480 - Rev 1
page 3/36
TSV791, TSV792
Absolute maximum ratings and operating conditions
2
Absolute maximum ratings and operating conditions
Table 3. Absolute maximum ratings
Parameter (1)
Symbol
Value
Unit
V
V
Supply voltage
6
CC
(2)
V
±V
Input voltage differential (V
Input voltage
- V )
IN-
V
id
CC
IN+
V
(V ) - 0.2 to (V
) + 0.2
V
in
CC-
CC+
I
Input current
±10
mA
°C
°C
in
T
Storage temperature
-65 to +150
150
stg
T
Maximum junction temperature
j
Thermal resistance junction-to-ambient
SOT23-5
250
57
(3)
R
DFN8 2x2
°C / W
th-ja
MiniSO8
127
125
SO8
Thermal resistance junction-to-case
SOT23-5
TBD
TBD
51
(4)
R
DFN8 2x2
°C / W
th-jc
MiniSO8
SO8
TBD
4
HBM: human body model (industrial grade) (5)
HBM: human body model (automotive grade) (6)
CDM: charged device model (7)
kV
kV
kV
ESD
4
1
1. All voltage values are with respect to the VCC- pin, unless otherwise specified.
2. The maximum input voltage differential value may be extended to the condition that the input current is limited to ±10 mA.
3.
4.
R
is a typical value, obtained with PCB according to JEDEC 2s2p without vias.
is a typical value, obtained with PCB according to JEDEC 1s0p without vias.
th-ja
th-jc
R
5. Human body model: HBM test according to the standard ESDA-JS-001-2017.
6. Human body model: HBM test according to the standard AEC-Q100-002.
7. Charged device model: the CDM test is done according to the standard AEC-Q100-011.
Table 4. Operating conditions
Symbol
Parameter
Value
V
Supply voltage
2.2 V to 5.5 V
CC
V
V
– 0.1 V to V
+ 0.1 V
Common mode input voltage range
Operating free air temperature range
icm
CC-
CC+
T
-40 °C to +125 °C
oper
DS13480 - Rev 1
page 4/36
TSV791, TSV792
Electrical characteristics
3
Electrical characteristics
Table 5. Electrical characteristics at VCC = 5 V, VICM = VOUT = VCC / 2, T = 25 °C, RL = 10 kΩ connected to VCC / 2 and
CL = 22 pF (unless otherwise specified).
Symbol
Parameter
Conditions
DC performance
T = 25 °C
Min.
Typ.
Max.
Unit
± 200
± 700
± 5
V
Input offset voltage
µV
io
-40 °C ≤ T ≤ 125 °C
-40 °C ≤ T ≤ 125 °C
Input offset voltage temperature drift (1)
Input offset voltage long-term drift
∆V /∆T
µV/°C
io
(2)
∆V
T = 25 °C
750
2
nV/√month
io
T = 25 °C
(3)
I
Input bias current
Input offset current
pA
pA
ib
-40 °C ≤ T ≤ 125 °C
T = 25 °C
75
1
(3)
I
io
-40 °C ≤ T ≤ 125 °C
20
V
+ 200 mV ≤ V
≤ V
≤ V
- 200
- 200
CC-
OUT
CC+
CC+
mV,
T = 25 °C
+ 200 mV ≤ V
110
90
133
113
132
V
CC-
OUT
mV,
-40 °C ≤ T ≤ 125 °C
R = 600 Ω, T = 25 °C
A
Open loop gain
dB
VD
L
105
V
+ 300 mV ≤ V
≤ V
≤ V
- 300
CC-
OUT
CC+
mV,
R = 600 Ω,
L
V
+ 300 mV ≤ V
- 300 mV
85
CC-
OUT
CC+
-40 °C ≤ T ≤ 125 °C
V
V
≤ V
≤ V
≤ V
≤ V
- 2 V, T = 25°C
- 2 V,
100
90
120
120
100
92
CC-
icm
CC+
CMR1
CMR2
dB
dB
CC-
icm
CC+
Common-mode rejection ratio
-40 °C ≤ T ≤ 125 °C
20.log (∆V /∆V
)
V
V
≤ V
≤ V
≤ V , T = 25 °C
CC+
io
icm
80
CC-
CC-
icm
icm
≤ VCC+,
76
-40 °C ≤ T ≤ 125 °C
2.2 V ≤ V ≤ 5.5 V, T = 25°C,
CC
90
90
109
108
V
= 0 V
ICM
Supply-voltage rejection ratio 20.log
(∆V /∆
SVR
dB
V
)
io CC CC
2.2 V ≤ V ≤ 5.5 V,
CC
-40 °C ≤ T ≤ 125 °C, V
= 0 V
ICM
High level output voltage drop
(V = V - V
T = 25°C
20
25
10
15
V
mV
OH
)
OUT
-40 °C ≤ T ≤ 125 °C
T = 25 °C
OH
CC+
Low level output voltage drop
V
mV
mA
OL
(V = V
OL
)
OUT
-40 °C ≤ T ≤ 125 °C
OUT connected to V , T = 25 °C
CC+
60
70
I
I
OUT
SINK
DS13480 - Rev 1
page 5/36
TSV791, TSV792
Electrical characteristics
Symbol
Parameter
Conditions
Min.
35
Typ.
60
Max.
Unit
OUT connected to V
-40 °C ≤ T ≤ 125 °C
,
CC+
I
I
SINK
I
mA
OUT connected to V , T = 25°C
OUT
50
CC-
OUT connected to V
-40 °C ≤ T ≤ 125 °C
T = 25 °C
,
SOURCE
CC-
40
5.5
6
6
I
Supply current (by operational amplifier)
mA
CC
-40 °C ≤ T ≤ 125 °C
AC performance
R = 10 kΩ, C = 22 pF
GBP
SR
Gain bandwidth product
Slew rate
35
50
30
MHz
V/µs
L
L
R = 10 kΩ, C = 22 pF, A = 1 V/V,
L
L
V
10 % to 90 %
V
A
= 4 V , R = 10 kΩ,
pp L
OUT
CR
Cross talk
126
dB
= +101, f = 1 kHz
V
R = 10 kΩ
Φm
Phase margin
53
140
43
degrees
L
f = 10 Hz
en
Input voltage noise density
f = 100 Hz
nV/√Hz
f = 10 kHz
6.5
9
µV
en p-p
Input noise voltage
Input capacitance
0.1 Hz ≤ f ≤ 10 Hz
Differential
pp
6.3
1.6
C
in
pF
Common mode
1. See Section 5.2 Input offset voltage drift overtemperature.
2. See Section 5.3 Long term input offset voltage drift.
3. Guaranteed by characterization.
DS13480 - Rev 1
page 6/36
TSV791, TSV792
Electrical characteristics
Table 6. Electrical characteristics at VCC = 3.3 V, VICM = VOUT = VCC / 2, T = 25 °C, RL = 10 kΩ connected to VCC / 2 and
CL = 22 pF (unless otherwise specified).
Symbol
Parameter
Conditions
DC performance
T = 25 °C
Min.
Typ.
Max.
Unit
± 200
± 700
± 5
V
Input offset voltage
µV
µV/°C
pA
io
-40 °C ≤ T ≤ 125 °C
-40 °C ≤ T ≤ 125 °C
T = 25 °C
∆V /∆T (1)
Input offset voltage temperature drift
Input bias current
io
1.5
60
1
(2)
I
ib
-40 °C ≤ T ≤ 125 °C
T = 25 °C
(2)
I
Input offset current
pA
io
-40 °C ≤ T ≤ 125 °C
20
V
+ 200 mV ≤ V
≤ V
≤ V
- 200 mV,
- 200 mV,
CC-
OUT
CC+
CC+
105
90
130
113
129
T = 25 °C
V
+ 200 mV ≤ V
CC-
OUT
-40 °C ≤ T ≤ 125 °C
R = 600 Ω, T = 25 °C
L
A
Open loop gain
dB
VD
100
V
+ 300 mV ≤ V
≤ V
≤ V
- 300 mV,
- 300 mV
CC-
OUT
CC+
R = 600 Ω,
L
V
+ 300 mV ≤ V
85
99
CC-
OUT
CC+
-40 °C ≤ T ≤ 125 °C
V
V
≤ V
≤ V
≤ V
≤ V
- 2 V, T = 25°C
- 2 V,
95
85
77
70
116
111
97
CC-
icm
CC+
CMR1
CMR2
dB
dB
CC-
icm
CC+
-40 °C ≤ T ≤ 125 °C
Common-mode rejection ratio 20.log
(∆V /∆V
)
icm
io
V
V
≤ V
≤ V
≤ V , T = 25 °C
CC+
CC-
icm
icm
≤ VCC+,
CC-
90
-40 °C ≤ T ≤ 125 °C
T = 25 °C
High level output voltage drop
(V = V - V
25
40
15
30
V
mV
mV
OH
)
OUT
-40 °C ≤ T ≤ 125 °C
T = 25 °C
OH
CC+
Low level output voltage drop
V
OL
(V = V
OL
)
OUT
-40 °C ≤ T ≤ 125 °C
OUT connected to V
, T = 25 °C
,
55
35
50
35
63
63
CC+
CC+
I
OUT connected to V
-40 °C ≤ T ≤ 125 °C
SINK
I
mA
mA
OUT
OUT connected to V , T = 25 °C
CC-
I
OUT connected to V
-40 °C ≤ T ≤ 125 °C
T = 25 °C
,
SOURCE
CC-
5.3
5.8
5.8
I
Supply current (by operational amplifier)
CC
-40 °C ≤ T ≤ 125 °C
AC performance
R = 10 kΩ, C = 22 pF
GBP
SR
Gain bandwidth product
Slew rate
35
50
30
MHz
V/µs
L
L
R = 10 kΩ, C = 22 pF, A = 1 V/V,
L
L
V
DS13480 - Rev 1
page 7/36
TSV791, TSV792
Electrical characteristics
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Unit
10 % to 90 %
= 4 V , R = 10 kΩ, A = +101,
V
OUT
pp
L
V
CR
Cross talk
126
dB
f = 1 kHz
R = 10 kΩ
Φm
Phase margin
53
140
43
degrees
L
f = 10 Hz
en
Input voltage noise density
Input capacitance
f = 100 Hz
f = 10 kHz
Differential
nV/√Hz
pF
6.5
6.3
1.6
C
in
Common mode
1. See Section 5.2 Input offset voltage drift overtemperature.
2. Guaranteed by characterization.
DS13480 - Rev 1
page 8/36
TSV791, TSV792
Electrical characteristics
Table 7. Electrical characteristics at VCC = 2.2 V, VICM = VOUT = VCC / 2, T = 25 °C, RL = 10 kΩ connected to VCC / 2 and
CL = 22 pF (unless otherwise specified).
Symbol
Parameter
Conditions
DC performance
T = 25 °C
Min.
Typ.
Max.
Unit
± 50
± 200
± 700
± 5
V
Input offset voltage
µV
µV/°C
pA
io
-40 °C ≤ T ≤ 125 °C
-40 °C ≤ T ≤ 125 °C
T = 25 °C
∆V /∆T (1)
Input offset voltage temperature drift
Input bias current
io
1
45
1
(2)
I
ib
-40 °C ≤ T ≤ 125 °C
T = 25 °C
(2)
I
Input offset current
pA
io
-40 °C ≤ T ≤ 125 °C
13
V
+ 200 mV ≤ V
≤ V
≤ V
- 200 mV,
- 200 mV,
CC-
OUT
CC+
CC+
95
85
120
107
T = 25 °C
V
+ 200 mV ≤ V
CC-
OUT
-40 °C ≤ T ≤ 125 °C
R = 600 Ω,
L
A
Open loop gain
dB
VD
90
80
119
99
V
+ 300 mV ≤ V
≤ V
≤ V
- 300 mV,
- 300 mV
CC-
OUT
CC+
T = 25 °C
R = 600 Ω,
L
V
+ 300 mV ≤ V
CC-
OUT
CC+
-40 °C ≤ T ≤ 125 °C
V
V
≤ V
≤ V
≤ V
≤ V
- 2 V, T = 25 °C
- 2 V,
73
67
94
85
CC-
icm
CC+
Common-mode rejection ratio 20.log
CMR
dB
CC-
icm
CC+
(∆V /∆V
)
icm
io
-40 °C ≤ T ≤ 125 °C
T = 25 °C
High level output voltage drop
(V = V - V
25
40
15
30
V
mV
mV
OH
)
OUT
-40 °C ≤ T ≤ 125 °C
T = 25 °C
OH
CC+
Low level output voltage drop
V
OL
(V = V
OL
)
OUT
-40 °C ≤ T ≤ 125 °C
OUT connected to V
, T = 25 °C
55
35
50
35
62
62
5
CC+
I
OUT connected to V
-40 °C ≤ T ≤ 125 °C
,
SINK
CC+
I
mA
mA
OUT
OUT connected to V , T = 25 °C
CC-
I
OUT connected to V
-40 °C ≤ T ≤ 125 °C
,
SOURCE
CC-
V
= 0 V, T = 25 °C
5.5
5.5
ICM
ICM
I
Supply current (by operational amplifier)
CC
V
= 0 V, -40 °C ≤ T ≤ 125 °C
AC performance
R = 10 kΩ
GBP
SR
Gain bandwidth product
Slew rate
35
50
30
MHz
V/µs
L
R = 10 kΩ, A = 1 V/V, 10 % to 90 %
L
V
V
= 4 V , R = 10 kΩ, A = +101,
pp L V
OUT
CR
Cross talk
126
dB
f = 1 kHz
DS13480 - Rev 1
page 9/36
TSV791, TSV792
Electrical characteristics
Symbol
Parameter
Conditions
Min.
Typ.
69
Max.
Unit
R = 10 kΩ
L
Φm
Phase margin
degrees
f = 10 Hz
250
94
en
Input voltage noise density
Input capacitance
f = 100 Hz
f = 10 kHz
Differential
Common mode
nV/√Hz
pF
15
6.3
1.6
C
in
1. See Section 5.2 Input offset voltage drift overtemperature.
2. Guaranteed by characterization.
DS13480 - Rev 1
page 10/36
TSV791, TSV792
Typical performance characteristics
4
Typical performance characteristics
RL = 10 kΩ connected to VCC / 2 and CL = 22 pF, unless otherwise specified.
Figure 4. Input offset voltage distribution at
VCC = 5 V
Figure 3. Supply current vs. supply voltage
Figure 6. Input offset voltage vs. temperature at
VCC = 5 V
Figure 5. Input offset voltage distribution at
VCC = 2.2 V
DS13480 - Rev 1
page 11/36
TSV791, TSV792
Typical performance characteristics
Figure 7. Input offset voltage vs. temperature at
VCC = 2.2 V
Figure 8. Input offset voltage thermal coefficient
distribution at VCC = 5 V
Figure 9. Input offset voltage thermal coefficient at
VCC = 2.2 V
Figure 10. Input offset voltage vs. supply voltage
Figure 11. Input offset voltage vs. common mode
voltage at VCC = 5 V
Figure 12. Input offset voltage vs. common mode
voltage at VCC = 2.2 V
DS13480 - Rev 1
page 12/36
TSV791, TSV792
Typical performance characteristics
Figure 13. Input bias current vs. temperature at
VICM = VCC / 2
Figure 14. Input bias current vs. common mode
voltage at VCC = 5 V
Figure 15. Output current vs. output voltage at VCC Figure 16. Output current vs. output voltage at VCC
= 5 V
= 2.2 V
Figure 17. Output saturation voltage (VOL) vs.
supply voltage
Figure 18. Output saturation voltage (VOH) vs.
supply voltage
DS13480 - Rev 1
page 13/36
TSV791, TSV792
Typical performance characteristics
Figure 19. Positive slew rate at VCC = 5 V
Figure 20. Negative slew rate at VCC = 5 V
Figure 22. Open loop bode diagram at VCC = 5 V
Figure 24. Closed loop bode diagram at VCC = 5 V
Figure 21. Slew rate vs. VCC
Figure 23. Open loop bode diagram at VCC = 2.2 V
DS13480 - Rev 1
page 14/36
TSV791, TSV792
Typical performance characteristics
Figure 26. Phase margin vs. common mode voltage
and load current at VCC = 5 V
Figure 25. Closed loop bode diagram at VCC = 2.2 V
Figure 28. Small step response at VCC = 5 V
Figure 27. Phase margin vs. capacitive load
Figure 29. Small step response at VCC = 2.2 V
Figure 30. Desaturation from low rail at VCC = 5 V
DS13480 - Rev 1
page 15/36
TSV791, TSV792
Typical performance characteristics
Figure 32. Settling time output high to low at
VCC = 5 V
Figure 31. Desaturation from high rail at VCC = 5 V
Figure 33. Settling time output low to high at
VCC = 5 V
Figure 34. Settling time output high to low at
VCC = 2.2 V
Figure 36. Small step overshoot vs. load
capacitance
Figure 35. Settling time output low to high at
VCC = 2.2 V
DS13480 - Rev 1
page 16/36
TSV791, TSV792
Typical performance characteristics
Figure 38. Noise vs. frequency
Figure 37. Linearity vs. load resistance at VCC = 5 V
Figure 39. Noise vs. time at VCC = 5 V
Figure 40. THD+N vs. frequency
Figure 41. THD+N vs. output voltage
Figure 42. CMRR vs. frequency at VCC = 5 V
DS13480 - Rev 1
page 17/36
TSV791, TSV792
Typical performance characteristics
Figure 43. PSRR vs. frequency at VCC = 5 V
Figure 44. Crosstalk vs. frequency at VCC = 5 V
DS13480 - Rev 1
page 18/36
TSV791, TSV792
Application information
5
Application information
5.1
Operating voltages
The TSV79x devices can operate from 2.2 to 5.5 V. The parameters are fully specified at 2.2 V, 3.3 V and 5 V
power supplies. However, the parameters are very stable over the full VCC range and several characterization
curves show the TSV79x device characteristics over the full operating range. Additionally, the main specifications
are guaranteed in extended temperature range from - 40 to 125 °C.
The TSV79X devices are rail-to-rail input and output, and feature two input transistor pairs, allowing the op-amp
to operate over all the common mode range, from Vcc- - 0.1 V, to Vcc+ + 0.1 V. The input pair transition typically
occurs at Vcc+ - 1.4 V, as seen in figures 11 and 12. The precision and dynamic performances are particularly
optimized on the low pair, from Vcc- - 0.1 V to Vcc+ - 2 V, and operating in this Vicm range is advised for best
performance whenever possible. Also, operating near the pair transition should be avoided when precision is a
concern, as CMRR can be lower in these conditions.
5.2
Input offset voltage drift overtemperature
The maximum input voltage drift variation overtemperature is defined as the offset variation related to the offset
value measured at 25 °C. The operational amplifier is one of the main circuits of the signal conditioning chain, and
the amplifier input offset (Vio) is a major contributor to the chain accuracy.
The signal chain accuracy at 25 °C can be compensated during production at application level. The maximum
input voltage drift overtemperature enables the system designer to anticipate the effect of temperature variations.
The maximum input voltage drift overtemperature is computed using Equation 1.
∆ V
io
∆ T
V
T − V 25°C
io
io
= max
(1)
T − 25°C
T = − 40°C and T = 125°C
The datasheet maximum value is guaranteed by a measurement on a representative sample size ensuring a Cpk
(process capability index) greater than 1.3.
5.3
Long term input offset voltage drift
To evaluate product reliability, two types of stress acceleration are used:
•
•
Voltage acceleration, by changing the applied voltage
Temperature acceleration, by changing the die temperature (below the maximum junction temperature
allowed by the technology) with the ambient temperature.
The voltage acceleration has been defined based on JEDEC results, and is defined using Equation 2
β . V − V
S
U
A
= e
(2)
FV
Where:
AFV is the voltage acceleration factor
β is the voltage acceleration constant in 1/V, constant technology parameter (β = 1)
VS is the stress voltage used for the accelerated test
VU is the voltage used for the application
The temperature acceleration is driven by the Arrhenius model, and is defined in Equation 3.
E
a
1
1
.
−
A
= e
(3)
k
T
T
FT
U
S
Where:
AFT is the temperature acceleration factor
Ea is the activation energy of the technology based on the failure rate
k is the Boltzmann constant (8.6173 x 10-5 eV . K-1)
TU is the temperature of the die when VU is used (K)
TS is the temperature of the die under temperature stress (K)
DS13480 - Rev 1
page 19/36
TSV791, TSV792
Unused channel
The final acceleration factor, AF, is the multiplication of the voltage acceleration factor and the temperature
acceleration factor (Equation 4).
A
= A . A
FT FV
(4)
F
AF is calculated using the temperature and voltage defined in the mission profile of the product. The AF value can
then be used in Equation x to calculate the number of months of use equivalent to 1000 hours of reliable stress
duration.
Months = AF × 1000 h × 12 months / (24 h × 365.25 days)
To evaluate the op-amp reliability, a follower stress condition is used where VCC is defined as a function of the
maximum operating voltage and the absolute maximum rating (as recommended by JEDEC rules). The Vio drift
(in µV) of the product after 1000 h of stress is tracked with parameters at different measurement conditions (see
Equation 5).
V
cc
V
= max V
op
witℎ V
icm
=
(5)
CC
2
The long term drift parameter ΔVio (in µV.month-1/2), estimating the reliability performance of the product, is
obtained using the ratio of the Vio (input offset voltage value) drift over the square root of the calculated number of
months (Equation 6).
V
drift
io
∆ V
io
=
(6)
(7)
montℎs
Where Vio drift is the measured drift value in the specified test conditions after 1000 h stress duration.
The Vio final drift, in µV, to be measured on the device in real operation conditions can be computed from
Equation 7.
E
a
1
297
1
β . V − V
CC CC nom
.
−
V
t
, T , V
= ∆ V
io
.
t
. e
. e
k
T
io final drift op op CC
op
op
Where:
ΔVio is the long term drift parameter in µV.√month
top is the operating time seen by the device, in months
Top is the operating temperature
VCC is the power supply during operating time
VCC nom is the nominal VCC at which the ΔVio is computed (5 V for TSV79x)
Ea is the activation energy of the technology (here 0.7 eV).
5.4
Unused channel
When one of the two channels of the TSV792 is not used, it must be properly connected in order to avoid
internal oscillations that can negatively impact the signal integrity on the other channel, as well as the current
consumption. Two different configurations can be used:
Gain configuration: the channel can be set in gain, the input can be set to any voltage within the Vicm operating
range.
Comparator configuration: the channel can be set to a comparator configuration (without negative feedback). In
this case, positive and negative inputs can be set to any value provided these values are significantly different
(100 mV or more, to avoid oscillation between positive and negative state).
5.5
EMI rejection
The electromagnetic interference (EMI) rejection ratio, or EMIRR, describes the EMI immunity of operational
amplifiers. An adverse effect that is common to many op-amps is a change in the offset voltage as a result of RF
signal rectification. EMIRR is defined in Equation 8:
V
in pp
EMIRR = 20 . log
(8)
∆ V
io
DS13480 - Rev 1
page 20/36
TSV791, TSV792
Maximum power dissipation
The TSV79x has been specially designed to minimize susceptibility to EMIRR and shows a low sensitivity. As
seen in Figure 45, EMI rejection ratio has been measured on both inputs and output, from 400 MHz to 2.4 GHz.
Figure 45. EMIRR on IN+ and IN- pins
EMIRR performances might be improved by adding small capacitances (in the pF range) on the inputs, power
supply and output pins. These capacitances help to minimize the impedance of these nodes at high frequencies.
5.6
Maximum power dissipation
The usable output load current drive is limited by the maximum power dissipation allowed by the device package.
The absolute maximum junction temperature for the TSV79x is 150 °C. The junction temperature can be
estimated as follows:
T
= P × θ + T
JA A
(9)
J
D
TJ is the die junction temperature
PD is the power dissipated in the package
θJA is the junction to ambient thermal resistance of the package.
TA is the ambient temperature.
The power dissipated in the package PD is the sum of the quiescent power dissipated and the power dissipated
by the output stage transistor. It is calculated as follows:
P
P
= V × I
+ V
+ V
− V
× ILoad when the op-amp is sourcing the current.
× ILoad when the op-amp is sinking the current.
D
CC
CC
CC +
OUT
= V × I
− V
CC −
D
CC
CC
OUT
Do not exceed the 150 °C maximum junction temperature for the device. Exceeding the junction temperature limit
can cause degradation in the parametric performance or even destroy the device.
5.7
Capacitive load and stability
Stability analysis must be performed for large capacitive loads over 22 pF. Increasing the load capacitance to high
values produces gain peaking in the frequency response, with overshoot and ringing in the step response.
DS13480 - Rev 1
page 21/36
TSV791, TSV792
Resistor values for high speed op-amp design
Generally, unity gain configuration is the worst situation for stability and the ability to drive large capacitive loads.
For additional capacitive load drive capability in unity-gain configuration, stability can be improved by inserting a
small resistor RISO (10 Ω to 22 Ω) in series with the output (see Figure 36). This resistor significantly reduces
ringing while maintaining DC performance for purely capacitive loads. However, if there is a resistive load in
parallel with the capacitive load, a voltage divider is created introducing a gain error at the output and slightly
reducing the output swing. The error introduced is proportional to the ratio RISO / RL. RISO modifies the maximum
capacitive load acceptable from a stability point-of-view as described in the figure below:
Figure 46. Test configuration for RISO
Please note that RISO = 22 Ω is sufficient to make the TSV79x stable whatever the capacitive load.
5.8
Resistor values for high speed op-amp design
Due to its high gain bandwidth product (GBP), this op-amp is particularly sensitive to parasitic impedances. Board
parasitics should be taken into account in any sensitive design. Indeed, excessive parasitics (both capacitive
and inductive) in the op-amp frequency range can alter performances and stability. These issues can often be
mitigated by lowering the resistive impedances.
More specifically, the RC network created by the schematic resistors (Rf and Rg) and the parasitic capacitances
of both the op-amp (as documented in Table 5 to Table 7 and illustrated in Figure 46) and the PCB can generate
a pole below or in the same order of magnitude than the closed-loop bandwidth of the circuit. In this case, the
feedback circuit is not able to fully play its role at high frequency, and the application can be unstable. This issue
can happen when the schematic gain is low (typically < 5), or the device is used in follower mode with a resistor in
the feedback. In these cases, it is advised to use a low value feedback resistor (Rf), typically 600 Ω.
Figure 47. Inverting amplifier configuration with parasitic input capacitances
DS13480 - Rev 1
page 22/36
TSV791, TSV792
Settling time
Also, some designs use an input resistor on the positive input, generally of the same value than the input on the
negative resistor. This resistor can be useful to balance the input currents on the positive and negative inputs,
and reduce the impact of those input currents on precision. However, this is not useful on TSV79x as the input
currents are very low. Furthermore, this resistor can also interact with the input capacitances to generate a pole.
The frequency of this pole should be kept higher than the closed-loop bandwidth frequency.
The macromodel provided takes into account the circuit parasitic capacitors. Thus, a transient SPICE simulation
(100 mV step) is an easy way to evaluate the stability of the application. However, this cannot replace hardware
evaluation of the application circuit.
5.9
Settling time
Settling time in an application can be defined as the amount of time between the input changes, and the output
reaching its final value. It is usually defined with a given tolerance, so the output stability is reached when the
output stays within the given range around the final value.
In Figure 32 to Figure 35, the settling time is measured in an inverting configuration, using the so-called “false
summing node” circuit.
Figure 48. Settling time measurement configuration
This circuit is used with a step input voltage from a positive or negative value, to 0 V. The measurement point
being (Vin - Vout) / 2, and Vout being in an ideal circuit equal to -Vin, the measurement point gives half of the error
on Vout, comparatively to Vin. This error is compared to the tolerance, 0.1% for this circuit, to deduce the settling
time.
This characteristic is particularly useful when driving an ADC. It is related to the slew rate, GBP and stability of the
circuit. It also varies with the circuit gain, the circuit load, and the input voltage step value. However, computing
the value of the settling time in a given configuration is not straightforward. The macromodel can give a good
estimation, but prototyping can be needed for fine circuit optimization.
5.10
PCB layout recommendations
Particular attention must be paid to the layout of the PCB tracks connected to the amplifier, load, and power
supply. The power and ground traces are critical as they must provide adequate energy and grounding for
all circuits. The best practice is to use short and wide PCB traces to minimize voltage drops and parasitic
inductance. In addition, to minimize parasitic impedance over the entire surface, a multi-via technique that
connects the bottom and top layer ground planes together in many locations is often used. The copper traces that
connect the output pins to the load and supply pins should be as wide as possible to minimize trace resistance.
DS13480 - Rev 1
page 23/36
TSV791, TSV792
Decoupling capacitor
5.11
5.12
Decoupling capacitor
In order to ensure op-amp full functionality, it is mandatory to place a decoupling capacitor of at least 22 nF as
close as possible to the op-amp supply pins. A good decoupling helps to reduce electromagnetic interference
impact.
Macro model
Accurate macro models of the TSV79x device are available on the STMicroelectronics’ website at: www.st.com.
These models are a trade-off between accuracy and complexity (that is, time simulation) of the TSV79x
operational amplifier. They emulate the nominal performance of a typical device at 25 °C within the specified
operating conditions mentioned in the datasheet. They also help to validate a design approach and to select the
right operational amplifier, but they do not replace onboard measurements.
DS13480 - Rev 1
page 24/36
TSV791, TSV792
Typical applications
6
Typical applications
6.1
Low-side current sensing
Power management mechanisms are found in most electronic systems. Current sensing is useful for protecting
applications. The low-side current sensing method consists of placing a sense resistor between the load and the
circuit ground. The resulting voltage drop is amplified using the TSV79x (see Figure 48).
Figure 49. Low-side current sensing schematic
Vout can be expressed as follows:
R
R
R
R
. R
R
R
g2
+ R
f1
g2 f2
f1
V
= R
. I 1 −
. 1 +
+ I
.
. 1 +
− I . R
f1
(10)
(11)
Out
sℎunt
p
n
R
R
+ R
g2
f2
g1
g2
f2
g1
R
f1
− V . 1 +
io
R
g1
Assuming that Rf2 = Rf1 = Rf and Rg2 = Rg1 = Rg, Equation 10 can be simplified as follows:
R
R
R
R
f
f
V
= R
sℎunt
. I .
− V . 1 +
io
+ R . I
io
Out
f
g
g
The main advantage of using the TSV79x for a low-side current sensing relies on its low Vio, compared to general
purpose operational amplifiers. For the same current and targeted accuracy, the shunt resistor can be chosen
with a lower value, resulting in lower power dissipation, lower drop in the ground path, and lower cost. Particular
attention must be paid to the matching and precision of Rg1, Rg2, Rf1, and Rf2, to maximize the accuracy of the
measurement.
6.2
Photodiode transimpedance amplification
The TSV79x, with high bandwidth and slew rate, is well suited for photodiode signal conditioning in a
transimpedance amplifier circuit. This application is useful in high performance UV sensors, smoke detectors
or particle sensors.
DS13480 - Rev 1
page 25/36
TSV791, TSV792
Photodiode transimpedance amplification
Figure 50. Photodiode transimpedance amplifier circuit
The transimpedance amplifier circuit converts the small photodiode output current in the nA range, into a voltage
signal readable by an ADC following Equation 12:
V
= R . I
pℎotodiode
(12)
Out
f
The feedback resistance is usually in the MΩ range, in order to get a large enough voltage output range.
However, together with the diode parasitic capacitance, the op-amp input capacitances and the PCB stray
capacitance, this feedback network creates a pole that makes the circuit oscillate. Using a small (few pF)
capacitor in parallel with the feedback resistor is mandatory to stabilize the circuit. The value of this capacitor can
be tuned to optimize the application settling time with a spice simulation using the op-amp macromodel, or by
prototyping.
For more details on tuning this circuit, please read the application note AN4451.
DS13480 - Rev 1
page 26/36
TSV791, TSV792
Package information
7
Package information
In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages,
depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product
status are available at: www.st.com. ECOPACK is an ST trademark.
DS13480 - Rev 1
page 27/36
TSV791, TSV792
SOT23-5 package information
7.1
SOT23-5 package information
Figure 51. SOT23-5 package outline
Table 8. SOT23-5 package mechanical data
Dimensions
Millimeters
Ref.
Inches
Min.
Typ.
Max.
1.45
0.15
1.30
0.50
0.20
3.00
Min.
Typ.
Max.
0.057
0.006
0.051
0.020
0.020
0.118
A
A1
A2
B
0.90
1.20
0.035
0.047
0.90
0.35
0.09
2.80
1.05
0.40
0.15
2.90
1.90
0.95
2.80
1.60
0.35
0.035
0.014
0.004
0.110
0.041
0.016
0.006
0.114
0.075
0.037
0.110
0.063
0.014
C
D
D1
e
E
2.60
1.50
0.10
0°
3.00
1.75
0.60
10°
0.102
0.059
0.004
0°
0.118
0.069
0.024
10°
F
L
K
DS13480 - Rev 1
page 28/36
TSV791, TSV792
DFN8 2x2 package information
7.2
DFN8 2x2 package information
Figure 52. DFN8 2x2 package outline
Table 9. DFN8 2x2 package mechanical data
Dimensions
Millimeters
Ref.
Inches
Min.
Typ.
Max.
0.60
0.05
Min.
Typ.
Max.
0.024
0.002
A
A1
A3
b
0.51
0.55
0.020
0.022
0.15
0.25
2.00
1.60
2.00
0.90
0.50
0.325
0.006
0.010
0.079
0.063
0.079
0.035
0.020
0.013
0.18
1.85
1.45
1.85
0.75
0.30
2.15
1.70
2.15
1.00
0.007
0.073
0.057
0.073
0.030
0.012
0.085
0.067
0.085
0.039
D
D2
E
E2
e
L
0.225
0.425
0.08
0.009
0.017
0.003
ddd
DS13480 - Rev 1
page 29/36
TSV791, TSV792
DFN8 2x2 package information
Figure 53. DFN8 2x2 recommended footprint
Note:
The exposed pad of the DFN8 2x2 can be connected to VCC- or left floating.
DS13480 - Rev 1
page 30/36
TSV791, TSV792
MiniSO8 package information
7.3
MiniSO8 package information
Figure 54. MiniSO8 package outline
Table 10. MiniSO8 package mechanical data
Dimensions
Millimeters
Ref.
Inches
Min.
Typ.
Max.
1.1
Min.
Typ.
Max.
0.043
0.0006
0.037
0.016
0.009
0.126
0.203
0.122
A
A1
A2
b
0
0.15
0.95
0.40
0.23
3.20
5.15
3.10
0
0.75
0.22
0.08
2.80
4.65
2.80
0.85
0.030
0.009
0.003
0.11
0.033
c
D
3.00
4.90
3.00
0.65
0.60
0.95
0.25
0.118
0.193
0.118
0.026
0.024
0.037
0.010
E
0.183
0.11
E1
e
L
0.40
0°
0.80
0.016
0°
0.031
L1
L2
k
8°
8°
ccc
0.10
0.004
DS13480 - Rev 1
page 31/36
TSV791, TSV792
SO-8 package information
7.4
SO-8 package information
Figure 55. SO-8 package outline
0016023_So-807_fig2_Rev10
Table 11. SO-8 mechanical data
mm
Dim.
Min.
Typ.
Max.
1.75
0.25
A
A1
A2
b
0.10
1.25
0.31
0.28
0.10
0.10
4.80
5.80
3.80
0.51
0.48
0.25
0.23
5.00
6.20
4.00
b1
c
c1
D
4.90
6.00
3.90
1.27
E
E1
e
h
0.25
0.40
0.50
1.27
L
L1
L2
k
1.04
0.25
0°
8°
ccc
0.10
DS13480 - Rev 1
page 32/36
TSV791, TSV792
Ordering information
8
Ordering information
Table 12. Order code
Temperature range
Order code
Channel
Package
SOT23-5
DFN8 2x2
MiniSO8
SO8
Marking
K2B
TSV791ILT
TSV792IQ2T
TSV792IST
TSV792IDT
TSV791IYLT
TSV792IYST
TSV792IYDT
1
1
2
2
2
2
2
K2B
-40 °C to 125 °C
K2B
TSV792I
K227
SOT23-5
MiniSO8
SO8
-40 °C to 125 °C
K227
automotive grade (1)
TSV792Y
1. Qualification and characterization according to AEC Q100 and Q003 or equivalent, advanced screening
according to AEC Q001 & Q 002 or equivalent are on-going.
DS13480 - Rev 1
page 33/36
TSV791, TSV792
Revision history
Table 13. Document revision history
Date
09-Nov-2020
Revision
Changes
1
Initial release.
DS13480 - Rev 1
page 34/36
TSV791, TSV792
Contents
Contents
1
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2
1.1
1.2
TSV791 single operational amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
TSV792 dual operational amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2
3
4
5
Absolute maximum ratings and operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
Electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Typical performance characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Application information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
5.1
5.2
5.3
5.4
5.5
5.6
5.7
5.8
5.9
Operating voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Input offset voltage drift over the temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Long term input offset voltage drift . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Unused channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
EMI rejection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Maximum power dissipation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Capacitive load and stability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Resistor values for high speed op-amp design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Settling time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
5.10 PCB layout recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
5.11 Decoupling capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
5.12 Macro model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
Typical applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
6
7
6.1
6.2
Low-side current sensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
Photodiode transimpedance amplification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
Package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
7.1
7.2
7.3
7.4
DFN8 2x2 mm package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
DFN8 2x2 package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
MiniSO8 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
SO-8 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
8
Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
DS13480 - Rev 1
page 35/36
TSV791, TSV792
IMPORTANT NOTICE – PLEASE READ CAREFULLY
STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST
products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST
products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement.
Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of
Purchasers’ products.
No license, express or implied, to any intellectual property right is granted by ST herein.
Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product.
ST and the ST logo are trademarks of ST. For additional information about ST trademarks, please refer to www.st.com/trademarks. All other product or service
names are the property of their respective owners.
Information in this document supersedes and replaces information previously supplied in any prior versions of this document.
© 2020 STMicroelectronics – All rights reserved
DS13480 - Rev 1
page 36/36
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