UC2844A [STMICROELECTRONICS]
HIGH PERFORMANCE CURRENT MODE PWM CONTROLLER; 高性能电流模式PWM控制器
| 型号： | UC2844A |
| 厂家： | 
ST |
| 描述： | HIGH PERFORMANCE CURRENT MODE PWM CONTROLLER |
| 文件： | 总16页 (文件大小：172K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
UC284XA
UC384XA
HIGH PERFORMANCE CURRENT MODE PWM CONTROLLER
NOT FOR NEW DESIGN
1
FEATURES
Figure 1. Package
■ TRIMMED OSCILLATOR DISCHARGE
CURRENT
■ CURRENT MODE OPERATION TO 500kHz
AUTOMATIC FEED FORWARD
COMPENSATION
DIP-8
SO-8
■ LATCHING PWM FOR CYCLE-BY-CYCLE
CURRENT LIMITING
■ INTERNALLY TRIMMED REFERENCE WITH
UNDERVOLTAGE LOCKOUT
■ HIGH CURRENT TOTEM POLE OUTPUT
UNDERVOLTAGE LOCKOUT WITH
HYSTERESIS
■ LOW START-UP CURRENT (< 0.5mA)
DOUBLE PULSE SUPPRESSION
Table 1. Order Codes
Part Number
Package
UC2842AD1; UC3842AD1;
UC2843AD1; UC3843AD1;
UC2844AD1; UC3844AD1;
UC2845AD1; UC3845AD1
SO-8
DIP-8
UC2842AN; UC3842AN;
UC2843AN; UC3843AN;
UC2844AN; UC3844AN;
UC2845AN; UC3845AN
2
DESCRIPTION
The UC384xA family of control ICs provides the
necessary features to implement off-line or DC to
DC fixed frequency current mode control schemes
with a minimal external parts count. Internally im-
plemented circuits include a trimmed oscillator for
precise DUTY CYCLE CONTROL under voltage
lockout featuring start-up current less than 0.5mA,
a precision reference trimmed for accuracy at the
error amp input, logic to insure latched operation,
a PWM comparator which also provides current
limit control, and a totem pole output stage de-
signed to source or sink high peak current. The
output stage, suitable for driving N-Channel MOS-
FETs, is low in the off-state.
Differences between members of this family are
the under-voltage lockout thresholds and maxi-
mum duty cycle ranges. The UC3842A and
UC3844A have UVLO thresholds of 16V (on) and
10V (off), ideally suited off-line applications The
corresponding thresholds for the UC3843A and
UC3845A are 8.5 V and 7.9V. The UC3842A and
UC3843A can operate to duty cycles approaching
100%. A range of the zero to < 50 % is obtained by
the UC3844A and UC3845A by the addition of an
internal toggle flip flop which blanks the output off
every other clock cycle.
Figure 2. Block Diagram (toggle flip flop used only in UC3844A and UC3845A)
7
Vi
UVLO
34V
8
6
5V
REF
VREF
5V 50mA
5
S/R
GROUND
INTERNAL
BIAS
2.50V
VREF GOOD
LOGIC
OUTPUT
4
RT/CT
OSC
ERROR AMP.
T
2R
+
-
S
2
1
3
VFB
R
PWM
LATCH
R
1V
COMP
CURRENT
SENSE
CURRENT
SENSE
COMPARATOR
D95IN331
REV. 5
1/16
May 2004
UC384XA - UC284XA
Table 2. Absolute Maximum Ratings
Symbol
Parameter
Value
Unit
Vi
Vi
Supply Voltage (low impedance source)
Supply Voltage (Ii < 30mA)
30
Self Limiting
±1
V
IO
Output Current
A
µJ
V
EO
Output Energy (capacitive load)
Analog Inputs (pins 2, 3)
5
– 0.3 to 5.5
10
Error Amplifier Output Sink Current
Power Dissipation at Tamb ≤ 25 °C (DIP-8)
Power Dissipation at Tamb ≤ 25 °C (SO-8)
Storage Temperature Range
mA
W
Ptot
Ptot
Tstg
TJ
1.25
800
mW
°C
°C
°C
– 65 to 150
– 40 to 150
300
Junction Operating Temperature
Lead Temperature (soldering 10s)
TL
* All voltages are with respect to pin 5, all currents are positive into the specified terminal.
Figure 3. DIP-8/SO-8 Pin Connection (Top view)
COMP
VFB
1
2
3
4
8
7
6
5
VREF
Vi
ISENSE
RT/CT
OUTPUT
GROUND
D95IN332
Table 3. Pin Description
N°
1
Pin
COMP
VFB
Function
This pin is the Error Amplifier output and is made available for loop compensation.
2
This is the inverting input of the Error Amplifier. It is normally connected to the switching power
supply output through a resistor divider.
3
4
ISENSE
A voltage proportional to inductor current is connected to this input. The PWM uses this
information to terminate the output switch conduction.
RT/CT
The oscillator frequency and maximum Output duty cycle are programmed by connecting
resistor RT to Vref and cpacitor CT to ground. Operation to 500kHz is possible.
5
6
GROUND This pin is the combined control circuitry and power ground.
OUTPUT This output directly drives the gate of a power MOSFET. Peak currents up to 1A are sourced
and sunk by this pin.
7
8
VCC
Vref
This pin is the positive supply of the control IC.
This is the reference output. It provides charging current for capacitor CT through resistor RT.
2/16
UC384XA - UC284XA
Table 4. Thermal Data
Symbol
Parameter
DIP-8
SO-8
Unit
Rth j-amb
Thermal Resistance Junction-ambient
Max.
100
150
°C/W
Table 5. Electrical Characteristcs
( [note 1] Unless otherwise stated, these specifications apply for -25 < Tamb < 85°C for UC284XA;
0 < Tamb < 70°C for UC384XA; Vi = 15V (note 5); RT = 10K; CT = 3.3nF)
UC284XA
UC384XA
Symbol
Parameter
Test Condition
Unit
Min. Typ. Max. Min. Typ. Max.
REFERENCE SECTION
VREF
∆VREF
∆VREF
Output Voltage
Tj = 25°C Io= 1mA
12V ≤ Vi ≤ 25V
1 ≤ Io ≤ 20mA
4.95 5.00 5.05 4.90 5.00 5.10
V
mV
mV
mV/°C
V
Line Regulation
2
3
20
25
2
3
20
25
Load Regulation
∆VREF/∆
T
Temperature Stability
Total Output Variation
Output Noise Voltage
(Note 2)
0.2
0.2
Line, Load, Temperature
4.9
5.1 4.82
5.18
25
eN
10Hz ≤ f ≤ 10KHz
Tj = 25°C (note 2)
50
5
50
5
µV
T
Long Term Stability
25
mV
amb = 125°C, 1000Hrs
(note 2)
Output Short Circuit
-30 -100 -180 -30 -100 -180 mA
ISC
OSCILLATOR SECTION
fOSC Frequency
fOSC
VREF
VOSC
Idischg
Tj = 25°C
47
–
52
0.2
5
57
1
47
–
52
0.2
5
57
1
KHz
%
∆
/
∆
V
Frequency Change with Volt. VCC = 12V to 25V
Frequency Change with Temp. TA = Tlow to Thigh
∆
/
∆
T
–
–
–
–
%
Oscillator Voltage Swing
Discharge Current (VOSC =2V)
(peak to peak)
TJ = 25°C
–
1.6
8.3
–
–
1.6
8.3
–
V
7.8
8.8
7.8
8.8
mA
ERROR AMP SECTION
V2
Ib
Input Voltage
VPIN1 = 2.5V
VFB = 5V
2.45 2.50 2.55 2.42 2.50 2.58
V
µA
Input Bias Current
AVOL
-0.1
90
1
-1
-0.1
90
1
-2
2V ≤ Vo ≤ 4V
TJ = 25°C
65
0.7
60
2
65
0.7
60
2
dB
BW
Unity Gain Bandwidth
MHz
dB
PSRR Power Supply Rejec. Ratio 12V ≤ Vi ≤ 25V
70
12
70
12
Io
Output Sink Current
VPIN2 = 2.7V
PIN1= 1.1V
mA
V
Io
Output Source Current
VOUT High
VPIN2 = 2.3V VPIN1 = 5V
-0.5
5
-1
-0.5
5
-1
mA
V
VPIN2 = 2.3V;RL = 15KΩ to
6.2
6.2
Ground
VOUT Low
VPIN2 = 2.7V;RL = 15KΩ to
0.8
1.1
0.8
1.1
V
Pin 8
CURRENT SENSE SECTION
GV
V3
Gain
(note 3 & 4)
2.85
0.9
3
1
3.15 2.85
3
1
3.15 V/V
Maximum Input Signal
Supply Voltage Rejection
Input Bias Current
Delay to Output
VPIN1 = 5V (note 3)
12 ≤ Vi ≤ 25V (note 3)
1.1
0.9
1.1
V
SVR
Ib
70
-2
70
-2
dB
µA
ns
-10
-10
150 300
150 300
3/16
UC384XA - UC284XA
Table 5. Electrical Characteristcs (continued)
( [note 1] Unless otherwise stated, these specifications apply for -25 < Tamb < 85°C for UC284XA;
0 < Tamb < 70°C for UC384XA; Vi = 15V (note 5); RT = 10K; CT = 3.3nF)
UC284XA
UC384XA
Symbol
Parameter
Test Condition
Unit
Min. Typ. Max. Min. Typ. Max.
OUTPUT SECTION
VOL Output Low Level
ISINK = 20mA
0.1
1.6
0.4
2.2
0.1
1.6
0.4
2.2
V
V
V
V
V
ISINK = 200mA
VOH
Output High Level
ISOURCE = 20mA
13
12
13.5
13.5
0.7
13
12
13.5
13.5
0.7
ISOURCE = 200mA
VOLS
tr
UVLO Saturation
Rise Time
VCC = 6V; I
SINK = 1mA
1.2
1.2
Tj = 25°C
CL = 1nF (2)
50
50
150
50
50
150
ns
ns
tf
Fall Time
Tj = 25°C
150
150
CL = 1nF (2)
UNDER-VOLTAGE LOCKOUT SECTION
Start Threshold
X842A/4A
15
7.8
9
16
8.4
10
17
9.0
11
14.5
7.8
16
8.4
10
17.5
9.0
V
V
V
X843A/5A
X842A/4A
Min Operating Voltage
After Turn-on
8.5
11.5
PWM SECTION
Maximum Duty Cycle
X842A/3A
X844A/5A
94
47
96
48
100
50
0
94
47
96
48
100
50
0
%
%
%
Minimum Duty Cycle
TOTAL STANDBY CURRENT
Ist
Start-up Current
Vi = 6.5V for UCX843A/
45A
0.3
0.5
0.3
0.5
mA
Vi = 14V for UCX842A/44A
VPIN2 = VPIN3 = 0V
Ii = 25mA
0.3
12
36
0.5
17
0.3
12
36
0.5
17
mA
mA
V
Ii
Operating Supply Current
Zener Voltage
Viz
30
30
Notes: 1. Max package power dissipation limits must be respected; low duty cycle pulse techniques are used during test maintain Tj as close
to Tamb as possible.
2. These parameters, although guaranteed, are not 100% tested in production.
3. Parameter measured at trip point of latch with VPIN2 = 0.
4. Gain defined as : A = ∆VPIN1/∆VPIN3; 0 ≤ VPIN3 ≤ 0.8V
5. Adjust Vi above the start threshold before setting at 15 V.
4/16
UC384XA - UC284XA
Figure 4. Open Loop Test Circuit.
VREF
4.7KΩ
RT
2N2222
A
Vi
VREF
0.1µF
100KΩ
COMP
VFB
8
1
7
Vi
ERROR AMP.
ADJUST
2
3
4
1W
1KΩ
1KΩ
0.1µF
ISENSE
RT/CT
ISENSE
4.7KΩ
OUTPUT
GROUND
ADJUST
5KΩ
6
5
OUTPUT
GROUND
CT
D95IN343
High peak currents associated with capacitive loads necessitate careful grounding techniques. Timing and
bypass capacitors should be connected close to pin 5 in a single point ground. The transistor and 5 KΩ
potentiometer are used to sample the oscillator waveform and apply an adjustable ramp to pin 3.
Figure 5. Oscillator Frequency vs Timing
Resistance
Figure 7. Oscillator Discharge Current vs.
Temperature.
f
o
I
D95IN335
dischg
D96IN362
(Hz)
(mA)
V =15V
i
V
=2V
OSC
1M
8.5
8.0
7.5
7.0
100K
10K
1K
-55 -25
0
25
50
75 100 T (˚C)
A
300
1K
3K
10K
30K
R (Ω)
T
Figure 6. Maximum Duty Cycle vs Timing
Resistor
Figure 8. Error Amp Open-Loop Gain and
Phase vs. Frequency.
f
D95IN337
o
D96IN363
(dB)
80
60
40
20
0
φ
(Hz)
V =15V
i
V =2V to 4V
O
R =100K
L
30
80
Gain
T =25˚C
A
60
60
40
90
Phase
120
150
180
20
0
-20
10
100
1K
10K 100K 1M f(Hz)
300
1K
3K
10K
30K
R (Ω)
T
5/16
UC384XA - UC284XA
Figure 9. Current Sense Input Threshold vs.
Error Amp Output Voltage.
Figure 12. Output Saturation Voltage vs. Load
Current.
V
(V)
D95IN338
V
th
(V)
sat
D95IN341
Source Saturation
(Load to Ground)
V =15V
i
V
i
-1
-2
1.0
T =25˚C
A
T =-40˚C
A
T =25˚C
A
V =15V
i
0.8
0.6
0.4
0.2
0.0
80µs Pulsed Load 120Hz Rate
T =125˚C
A
3
2
1
0
T =-40˚C
A
T =25˚C
A
T =-40˚C
A
Sink Saturation
(Load to V )
GND
i
0
2
4
6
V (V)
O
0
200
400
600
I (mA)
O
Figure 10. Reference Voltage Change vs.
Source Current..
Figure 13. Supply Current vs. Supply Voltage.
D95IN339
D95IN342
I
i
60
(mA)
V =15V
i
50
40
30
20
10
0
20
T =-40˚C
A
15
10
5
T =125˚C
A
R =10K
T
C =3.3nF
T
V =0V
FB
I
=0V
Sense
T =25˚C
A
0
0
20
40
60
80
100 I (mA)
ref
0
10
20
30
V (V)
i
Figure 11. Reference Short Circuit Current vs.
Temperature..
D95IN340
I
SC
(mA)
V =15V
i
R ≤0.1Ω
L
100
90
80
70
60
50
-55 -25
0
25
50
75 100 T (˚C)
A
6/16
UC384XA - UC284XA
Figure 14. Output Waveform.
Figure 15. Output Cross Conduction
Figure 16. Oscillator and Output Waveforms.
Vi
7
CT
8
5V REG
OUTPUT
PWM
6
RT
OUTPUT
LARGE RT/SMALL CT
CLOCK
4
OSCILLATOR
CT
ID
CT
OUTPUT
5
SMALL RT/LARGE CT
GND
D95IN344
Figure 17. Error Amp Configuration.
2.5V
1mA
+
-
VFB
2
Zi
COMP
Zf
1
D95IN345
7/16
UC384XA - UC284XA
Figure 18. Under Voltage Lockout.
7
ON/OFF COMMAND
TO REST OF IC
Vi
ICC
<17mA
<0.5mA
UC3842A UC3843A
UC3844A UC3845A
VON
16V
10V
8.4V
7.6V
VCC
VOFF VON
VOFF
D95IN346mod
Figure 19. Current Sense Circuit.
ERROR
AMPL.
2R
R
IS
1
3
1V
COMP
CURRENT
SENSE
COMPARATOR
R
CURRENT
SENSE
RS
C
5
GND
D95IN347
Peak current (is) is determined by the formula
1.0V
------------
I
≈
Smax
R
S
A small RC filter may be required to suppress switch transients.
Figure 20. Slope Compensation Techniques.
VREG
VREG
8
8
4
RT
RT
RT/CT
RT/CT
IS
4
3
IS
RSLOPE
R1
CT
ISENSE
CT
ISENSE
RSLOPE
R1
3
5
5
RS
RS
GND
GND
D95IN348
8/16
UC384XA - UC284XA
Figure 21. Isolated MOSFET Drive and Current Transformer Sensing.
VCC
Vin
7
+
-
ISOLATION
BOUNDARY
5.0V
ref
VGS Waveforms
Q1
+
0
+
0
+
-
6
-
-
50% DC
25% DC
NS
S
R
Q
V(pin 1) -1.4
Ipk
=
( )
3RS
NP
-
+
R
COMP/LATCH
3
RS
NS
NP
C
D95IN349
Figure 22. Latched Shutdown.
4
8
OSC
R
R
BIAS
+
1mA
2R
+
-
2
1
EA
R
5
2N
3905
2N
3903
D95IN350
SCR must be selected for a holding current of less than 0.5mA at TA(min)
.
The simple two transistor circuit can be used in place of the SCR as shown. All resistors are 10K.
9/16
UC384XA - UC284XA
Figure 23. Error Amplifier Compensation
+
From VO
Ri
2.5V
1mA
2R
+
-
2
1
EA
R
Rd Cf
Rf
5
Error Amp compensation circuit for stabilizing any current-mode topology except
for boost and flyback converters operating with continuous inductor current.
+
From VO
RP
2.5V
1mA
2R
+
-
Ri
2
1
EA
R
CP
Rd
Cf
Rf
5
D95IN351
Error Amp compensation circuit for stabilizing current-mode boost and flyback
topologies operating with continuous inductor current.
Figure 24. External Clock Synchronization.
VREF
8
4
R
R
BIAS
OSC
RT
CT
+
EXTERNAL
SYNC INPUT
2R
0.01µF
+
-
2
1
EA
47Ω
R
5
D95IN352
The diode clamp is required if the Sync amplitude is large enough to cause
the bottom side of CT to go more than 300mV below ground
10/16
UC384XA - UC284XA
Figure 25. External Duty Cycle Clamp and Multi Unit Synchronization.
VREF
8
RA
RB
R
BIAS
R
8
4
5K
5K
5K
6
5
+
-
3
7
4
R
S
OSC
+
Q
2R
+
-
+
-
2
2
1
EA
C
R
1
NE555
5
TO ADDITIONAL
UCX84XAs
1.44
(RA + 2RB)C
RB
RA + 2RB
f =
Dmax
=
D95IN353
Figure 26. Soft-Start Circuit
8
5Vref
R
R
+
-
BIAS
4
OSC
+
1mA
S
2R
+
-
Q
2
+
-
R
1MΩ
EA
R
1V
1
C
5
D95IN354
11/16
UC384XA - UC284XA
Figure 27. Soft-Start and Error Amplifier Output Duty Cycle Clamp.
VCC Vin
7
+
8
4
5Vref
-
R
R
+
-
BIAS
7
6
OSC
2R
Q1
+
1mA
VClamp
S
R
+
-
Q
5
-
2
1
+
EA
R
1V
R2
R1
Comp/Latch
5
RS
C
BC109
R1
VCLAMP
RS
VCLAMP = ·
where 0 <VCLAMP <1V
Ipk(max)
=
D95IN355
R1 + R2
12/16
UC384XA - UC284XA
Figure 28. SO-8 Mechanical Data & Package Dimensions
mm
inch
DIM.
OUTLINE AND
MECHANICAL DATA
MIN. TYP. MAX. MIN.
TYP. MAX.
0.069
A
A1
A2
B
1.35
0.10
1.10
0.33
0.19
4.80
1.75 0.053
0.25 0.004
1.65 0.043
0.51 0.013
0.25 0.007
5.00 0.189
0.010
0.065
0.020
C
0.010
(1)
D
0.197
E
e
3.80
4.00
0.15
0.157
0.050
1.27
H
5.80
0.25
0.40
6.20 0.228
0.50 0.010
1.27 0.016
0˚ (min.), 8˚ (max.)
0.10
0.244
h
0.020
L
0.050
k
ddd
0.004
Note: (1) Dimensions D does not include mold flash, protru-
sions or gate burrs.
SO-8
Mold flash, potrusions or gate burrs shall not exceed
0.15mm (.006inch) in total (both side).
0016023 C
13/16
UC384XA - UC284XA
Figure 29. DIP-8 Mechanical Data & Package Dimensions
mm
inch
DIM.
OUTLINE AND
MECHANICAL DATA
MIN.
TYP. MAX. MIN.
3.32
TYP. MAX.
0.131
A
a1
B
0.51
1.15
0.020
1.65 0.045
0.55 0.014
0.304 0.008
10.92
0.065
0.022
b
0.356
0.204
b1
D
E
0.012
0.430
7.95
9.75 0.313
2.54
0.384
e
0.100
e3
e4
F
7.62
0.300
7.62
0.300
6.6
0.260
I
5.08
0.200
L
3.18
3.81 0.125
1.52
0.150
DIP-8
Z
0.060
14/16
UC384XA - UC284XA
Table 6. Revision History
Date
Revision
Description of Changes
March 1999
May 2004
4
5
First Issue in EDOCS
NOT FOR NEW DESIGN
15/16
UC384XA - UC284XA
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
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All other names are the property of their respective owners
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16/16
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