UPSD3212AV-40U1F [STMICROELECTRONICS]
RISC MICROCONTROLLER;
| 型号： | UPSD3212AV-40U1F |
| 厂家： | 
ST |
| 描述： | RISC MICROCONTROLLER 外围集成电路 |
| 文件： | 总181页 (文件大小：1423K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
UPSD3212A
UPSD3212C, UPSD3212CV
Flash programmable system devices
with 8032 MCU and USB and programmable logic
Features
■ Fast 8-bit 8032 MCU
– 40 MHz at 5.0 V, 24 MHz at 3.3 V
– Core, 12-clocks per instruction
LQFP52 (T)
52-lead, thin,
quad flat package
■ Dual Flash memories with memory
LQFP80 (U)
80-lead, thin, quad
management
flat package
– Place either memory into 8032 program
address space or data address space
■ Communication interfas
– Read-while-write operation for in-
application programming and EEPROM
emulation
– USB v1.1, lospeed 1.5 Mbps,
3 endpoints
– I C master/slave bus controller
– Two UARTs with independent baud rate
– Six I/O ports with up to 46 I/O pins
– 8032 address/data bus available on
TQFP80 package
2
– Single voltage program and erase
– 100 K minimum erase cycles, 15-year
retention
■ Clock, reset, and supply management
– Normal, idle, and power down modes
– Power-on and low voltage reset supervisor
– Programmable watchdog timer
– 5 PWM outputs, 8-bit resolution
■ JTAG in-system programming
– Program the entire device in as little as
10 seconds
■ Programmable logic, general-purpose
– 16 macrocells
■ Single supply voltage
– 4.5 to 5.5 V
– Implements state machines, glue-logic, etc.
■ Timers and interrupts
– 3.0 to 3.6 V
– Three 8032 standard 16-bit timers
– 10 Interrupt sources with two external
ierrupt pins
■ ECOPACK® packages
A/D converter
– Four channels, 8-bit resolution, 10 µs
Table 1.
Device summary
Max.clock 1st
2nd
8032
bus
Order code
SRAM GPIO USB
VCC (V)
Pkg.
Temp.
(MHz)
Flash Flash
UPSD3212C-40T6
UPSD3212CV-24T6
UPSD3212C-40U6
UPSD3212CV-24U6
UPSD3212A-40T6
UPSD3212A-40U6
40
24
40
24
40
40
64 KB 16 KB 2 KB
64 KB 16 KB 2 KB
64 KB 16 KB 2 KB
64 KB 16 KB 2 KB
64 KB 16 KB 2 KB
64 KB 16 KB 2 KB
37
37
46
46
37
46
No
No
No 4.5-5.5 TQFP52 –40°C to 85°C
No 3.0-3.6 TQFP52 –40°C to 85°C
Yes 4.5-5.5 TQFP80 –40°C to 85°C
Yes 3.0-3.6 TQFP80 –40°C to 85°C
No 4.5-5.5 TQFP52 –40°C to 85°C
Yes 4.5-5.5 TQFP80 –40°C to 85°C
No
No
Yes
Yes
January 2009
Rev 6
1/181
www.st.com
1
Contents
UPSD3212A, UPSD3212C, UPSD3212CV
Contents
1
UPSD321xx description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
1.1
52-pin package I/O port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2
Architecture overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.1
2.2
Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.2.1
2.2.2
2.2.3
2.2.4
2.2.5
2.2.6
2.2.7
Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
B register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Stack pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Program counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Program status word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Registers R0~R7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Data pointer register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.3
2.4
2.5
2.6
2.7
2.8
Program memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Data memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
XRAM-PSD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
SFR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Addresng modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
.8.1
2.8.2
2.8.3
2.8.4
2.8.5
2.8.6
Direct addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Indirect addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Register addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Register-specific addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Immediate constants addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Indexed addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
2.9
Arithmetic instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
2.10 Logical instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
2.11 Data transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
2.11.1 Internal RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
2.11.2 External RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
2.11.3 Lookup tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
2.12 Boolean instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
2.13 Relative offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
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Contents
2.14 Jump instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
2.15 Machine cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
3
4
UPSD321xx hardware description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
MCU module description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
4.1
Special function registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
5
Interrupt system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
5.1
5.2
5.3
5.4
5.5
5.6
5.7
5.8
5.9
External Int0 interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Timer 0 and 1 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Timer 2 interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
I2C interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
External Int1 interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
USB interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
USART interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Interrupt priority structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Interrupt enable structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
5.10 How interrupts are handled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
6
7
Power-saving mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
6.1
6.2
6.3
6.4
6.5
Idle mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Power-down mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Power control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Idle mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Power-down mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
I/O ports (MCU module) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
7.1
Port type and description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
8
9
Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Supervisory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
9.1
9.2
External reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Low VDD voltage reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
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Contents
UPSD3212A, UPSD3212C, UPSD3212CV
9.3
9.4
Watchdog timer overflow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
USB reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
10
11
Watchdog timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Timer/counters (Timer 0, Timer 1 and Timer 2) . . . . . . . . . . . . . . . . . . 58
11.1 Timer 0 and Timer 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
11.1.1 Mode 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
11.1.2 Mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
11.1.3 Mode 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
11.1.4 Mode 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
11.2 Timer 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
12
Standard serial interface (UART) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
12.1 Multiprocessor communications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
12.2 Serial port control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
12.2.1 Baud rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
12.2.2 Using Timer 1 to geate baud rates . . . . . . . . . . . . . . . . . . . . . . . . . . 67
12.2.3 Using Timer/counter 2 to generate baud rates . . . . . . . . . . . . . . . . . . . 67
12.2.4 More about Mode 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
12.2.5 More about Mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
12.2.6 More about Modes 2 and 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
13
14
Analog-to-digital convertor (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
131 ADC interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Pulse width modulation (PWM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
14.1 4-channel PWM unit (PWM 0-3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
14.2 Programmable period 8-bit PWM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
14.3 PWM 4-channel operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
2
15
I C interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
15.1 Serial status register (SxSTA: S1STA, S2STA) . . . . . . . . . . . . . . . . . . . . 85
15.2 Data shift register (SxDAT: S1DAT, S2DAT) . . . . . . . . . . . . . . . . . . . . . . . 85
15.3 Address register (SxADR: S1ADR, S2ADR) . . . . . . . . . . . . . . . . . . . . . . 86
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Contents
16
USB hardware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
16.1 USB related registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
16.2 Transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
16.2.1 USB physical layer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
16.2.2 Low speed driver characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
16.3 Receiver characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
16.4 External USB pull-up resistor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
17
PSD module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
17.1 Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
17.2 In-system programming (ISP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
18
19
20
21
Development system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
PSD module register description and address offset . . . . . . . . . . . . 103
PSD module detailed operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Memory blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
21.1 Primary Flash memory and secondary Flash memory description . . . . 105
21.2 Memory block select signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
21.2.1 Ready/Busy (PC3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
21.2.Memory operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
21.3 Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
21.4 Power-down instruction and Power-up mode . . . . . . . . . . . . . . . . . . . . . 107
21.4.1 Power-up mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
21.5 Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
21.5.1 Read memory contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
21.5.2 Read memory sector protection status . . . . . . . . . . . . . . . . . . . . . . . . 108
21.5.3 Reading the Erase/Program status bits . . . . . . . . . . . . . . . . . . . . . . . . 108
21.5.4 Data polling flag (DQ7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
21.5.5 Toggle flag (DQ6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
21.5.6 Error flag (DQ5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
21.5.7 Erase time-out flag (DQ3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
21.6 Programming Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
21.6.1 Data Polling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
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21.6.2 Data toggle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
21.7 Erasing Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
21.7.1 Flash Bulk Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
21.7.2 Flash Sector Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
21.7.3 Suspend Sector Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
21.7.4 Resume Sector Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
21.8 Specific features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
21.8.1 Flash memory sector protect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
21.8.2 Reset Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
21.9 SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
21.10 Sector Select and SRAM Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
21.10.1 Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
21.10.2 Memory Select configuration in Program and Data paces . . . . . . . . . 116
21.10.3 Separate Space mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
21.10.4 Combined Space modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
21.11 Page register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
22
PLDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
22.1 Turbo bit in PSD module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
22.2 Decode PLD (DPLD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
22.3 Complex PLD (CPLD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
22.4 Output acrocell (OMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
22.5 Product term allocator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
22.5.1 Loading and Reading the Output Macrocells (OMC) . . . . . . . . . . . . . . 124
22.5.2 OMC mask register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
22.5.3 Output enable of the OMC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
22.6 Input macrocells (IMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
23
I/O ports (PSD module) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
23.1 General port architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
23.2 Port operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
23.3 MCU I/O mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
23.4 PLD I/O mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
23.5 Address Out mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
23.6 Peripheral I/O mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
6/181
UPSD3212A, UPSD3212C, UPSD3212CV
Contents
23.7 JTAG in-system programming (ISP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
23.8 Port configuration registers (PCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
23.8.1 Control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
23.8.2 Direction register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
23.8.3 Drive Select register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
23.9 Port data registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
23.9.1 Data In . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
23.9.2 Data Out register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
23.9.3 Output macrocells (OMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
23.9.4 OMC mask register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
23.9.5 Input macrocells (IMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
23.9.6 Enable out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
23.10 Ports A and B – functionality and structure . . . . . . . . . . . . . . . . . . . . 133
23.11 Port C – functionality and structure . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
23.12 Port D – functionality and structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
23.13 External chip select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
24
Power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
24.1 PLD power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
24.2 PSD chip select input (CSI, PD2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
24.3 Input clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
24.4 Input control signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
25
26
RESET timing and device status at reset . . . . . . . . . . . . . . . . . . . . . . 142
25.1 Warm RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
25.2 I/O pin, register and PLD status at RESET . . . . . . . . . . . . . . . . . . . . . . 142
Programming in-circuit using the JTAG serial interface . . . . . . . . . . 144
26.1 Standard JTAG Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
26.2 JTAG extensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
26.3 Security and Flash memory protection . . . . . . . . . . . . . . . . . . . . . . . . . . 145
27
28
Initial delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
AC/DC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
7/181
Contents
29
UPSD3212A, UPSD3212C, UPSD3212CV
Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
30
30.1 Functional EMS (electromagnetic susceptibility) . . . . . . . . . . . . . . . . . . 151
30.1.1 ESD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
30.1.2 FTB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
30.2 Designing hardened software to avoid noise problems . . . . . . . . . . . . . 151
30.2.1 Software recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
30.2.2 Prequalification trials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
30.3 Absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . . . 152
30.3.1 Electro-static discharge (ESD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
30.3.2 Latch-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
30.3.3 Dynamic latch-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
31
32
33
34
DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
Package mechanical information . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
8/181
UPSD3212A, UPSD3212C, UPSD3212CV
UPSD321xx description
1
UPSD321xx description
The UPSD321xx Series combines a fast 8051-based microcontroller with a flexible memory
structure, programmable logic, and a rich peripheral mix including USB, to form an ideal
embedded controller. At its core is an industry-standard 8032 MCU operating up to 40MHz.
A JTAG serial interface is used for In-System Programming (ISP) in as little as 10 seconds,
perfect for manufacturing and lab development.
The USB 1.1 low-speed interface has one Control endpoint and two Interrupt endpoints
suitable for HID class drivers.
The 8032 core is coupled to Programmable System Device (PSD) architecture to optimize
the 8032 memory structure, offering two independent banks of Flash memory that can be
placed at virtually any address within 8032 program or data address space, and easily
paged beyond 64 Kbytes using on-chip programmable decode logic.
Dual Flash memory banks provide a robust solution for remote product pdates in the field
through In-Application Programming (IAP). Dual Flash banks also sport EEPROM
emulation, eliminating the need for external EEPROM chips.
General purpose programmable logic (PLD) is included to build an endless variety of glue-
logic, saving external logic devices. The PLD is configured using the software development
tool, PSDsoft Express, available from the web at www.st.com/psm, at no charge.
The UPSD321xx also includes supervisor functions such as a programmable watchdog
timer and low-voltage reset.
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
9/181
UPSD321xx description
Figure 1.
UPSD3212A, UPSD3212C, UPSD3212CV
UPSD321xx block diagram
uPSD321x
(3) 16-bit
Timer/
Counters
1st Flash Memory:
64K Bytes
8032
MCU
Core
(2)
External
Interrupts
Programmable
Decode and
Page Logic
2nd Flash Memory:
16K Bytes
I2C
P3.0:7
SRAM:
2K Bytes
UART0
(8) GPIO, Port A
(80-pin only)
PA0:7
PB0:7
PD1:2
(8) GPIO, Port 3
(8) GPIO, Port 1
(4) 8-bit ADC
General
Purpose
Programmable
Logic,
(8) GPIO, Port B
(2) GPIO, Port D
(4) GPIO, Port C
P1.0:7
16 Macrocells
PC0:7
JTAG ISP
UART1
MCU
Bus
8032 Address/Dataol Bus
(80-pin device nly)
(5) 8-bit PWM
Servisor:
Watchdog and Low-Voltage Reset
P4.0:7
(8) GPIO, Port 4
USB+,
USB–
Dedicated
Pins
CC, VDD, GND, Reset, Crystal In
USB v1.1
AI10428b
10/181
UPSD3212A, UPSD3212C, UPSD3212CV
UPSD321xx description
Figure 2.
TQFP52 connections
PD1/CLKIN 1
PC7 2
39 P1.5/ADC1
38 P1.4/ADC0
37 P1.3/TXD1
36 P1.2/RXD1
35 P1.1/T2X
34 P1.0/T2
JTAG TDO 3
JTAG TDI 4
(1)
USB–
5
PC4/TERR_ 6
USB+ 7
33 V
CC
V
8
32 XTAL2
CC
GND 9
31 XTAL1
PC3/TSTAT 10
30 P3.7/SCL1
29 P3.6/SDA1
28 P3.5
27 /T0
PC2/V
11
STBY
JTAG TCK 12
JTAG TMS 13
AI07423c
1. Pull-up resistor required on pin 5 (2 kΩ for 3 V devices, 7.5 kΩ for 5 V devices) for all 52-pin devices, with
or without USB function.
11/181
UPSD321xx description
Figure 3.
UPSD3212A, UPSD3212C, UPSD3212CV
TQFP80 connections
PD2 1
60 P1.5/ADC1
59 P1.4/ADC0
58 P1.3/TXD1
57 A11
P3.3 /EXINT1 2
PD1/CLKIN 3
ALE 4
PC7 5
56 P1.2/RXD1
55 A10
JTAG/TDO 6
JTAG/TDI 7
(1)
54 P1.1/TX2
53 A9
USB–
8
PC4/TERR_ 9
52 P1.0/T2
51 A8
USB+ 10
(2)
NC
V
11
12
50 V
CC
49 XTAL2
48 XTAL1
47 AD7
CC
GND 13
PC3/TSTAT 14
PC2/V
15
46 P3.7/SCL1
45 AD6
STBY
JTAG TCK 16
(2)
NC
17
44 P3.6/SDA1
43 AD5
P4.7/PWM4 18
P4.6/PWM3 19
JTAG TMS 20
42 P3.5/T1
41 AD4
AI07424c
1. Pull-p resistor required on pin 8 (2 kΩ for 3 V devices, 7.5 kΩ for 5 V devices) for all 82-pin devices, with
or without USB function.
2. NC = Not Connected
Table 2.
80-pin package pin description
Function
Port
pin
Signal
name
Pin
no.
In/
out
Basic
Alternate
External Bus: Multiplexed
Address/Data bus A1/D1
AD0
36
I/O
AD1
AD2
AD3
AD4
AD5
AD6
37
38
39
41
43
45
I/O Multiplexed Address/Data bus A0/D0
I/O Multiplexed Address/Data bus A2/D2
I/O Multiplexed Address/Data bus A3/D3
I/O Multiplexed Address/Data bus A4/D4
I/O Multiplexed Address/Data bus A5/D5
I/O Multiplexed Address/Data bus A6/D6
12/181
UPSD3212A, UPSD3212C, UPSD3212CV
UPSD321xx description
Table 2.
80-pin package pin description (continued)
Function
Port
pin
Signal
name
Pin
no.
In/
out
Basic
Alternate
AD7
T2
47
52
54
56
58
59
60
61
64
51
53
55
57
75
77
I/O Multiplexed Address/Data bus A7/D7
I/O General I/O port pin
I/O General I/O port pin
I/O General I/O port pin
I/O General I/O port pin
I/O General I/O port pin
I/O General I/O port pin
I/O General I/O port pin
I/O General I/O port pin
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
Timer 2 Count input
Timer 2 Trigger input
2nd UART Receive
2nd UART Transmit
ADC Channel 0 input
ADC Channel 1 input
ADC Channel 2 input
ADC Channel 3 input
TX2
RxD1
TxD1
ADC0
ADC1
ADC2
ADC3
A8
O
O
O
O
External Bus, Address A8
External Bus, Address A9
External Bus, Address A10
External Bus, Address A11
A9
A10
A11
P3.0
P3.1
RxD0
TxD0
I/O General I/O port pin
I/O Generaport pin
UART Receive
UART Transmit
Interrupt 0 input / Timer 0
gate control
P3.2
P3.3
EXINT0
EXINT1
79
2
I/O General I/O port pin
I/O General I/O port pin
Interrupt 1 input / Timer 1
gate control
P3.4
P3.5
P3.6
P3.7
T0
T1
40
42
44
46
I/O General I/O port pin
I/O General I/O port pin
I/O General I/O port pin
I/O General I/O port pin
Counter 0 input
Counter 1 input
SDA1
SCL1
I2C Bus serial data I/O
I2C Bus clock I/O
DDC
SDA
P4.0
P4.1
P4.2
P4.3
P4.4
P4.5
P4.6
33
31
30
27
25
23
19
I/O General I/O port pin
I/O General I/O port pin
I/O General I/O port pin
I/O General I/O port pin
I/O General I/O port pin
I/O General I/O port pin
I/O General I/O port pin
DDC
SCL
DDC
VSYNC
8-bit Pulse Width
Modulation output 0
PWM0
PWM1
PWM2
PWM3
8-bit Pulse Width
Modulation output 1
8-bit Pulse Width
Modulation output 2
8-bit Pulse Width
Modulation output 3
13/181
UPSD321xx description
Table 2.
UPSD3212A, UPSD3212C, UPSD3212CV
80-pin package pin description (continued)
Function
Port
pin
Signal
name
Pin
no.
In/
out
Basic
Alternate
Programmable 8-bit Pulse
Width modulation output 4
P4.7
PWM4
USB–
18
8
I/O General I/O port pin
Pull-up resistor required (2 kΩ for
3 V devices, 7.5 kΩ for 5 V devices)
I/O
VREF
RD_
70
65
62
63
4
O
O
O
O
O
I
Reference Voltage input for ADC
READ signal, external bus
WR_
WRITE signal, external bus
PSEN_
ALE
PSEN signal, external bus
Address Latch signal, external bus
Active low RESET input
RESET_
XTAL1
XTAL2
68
48
49
35
34
32
28
26
24
22
21
80
78
76
74
73
72
67
66
I
Oscillator input pin for system clock
Oscillator output pin for system clock
O
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
I/O General I/O port pin
I/O General I/O port pi
I/O General I/O port pin
I/O Generaport pin
I/O General I/O port pin
I/O General I/O port pin
I/O General I/O port pin
I/O General I/O port pin
I/O General I/O port pin
I/O General I/O port pin
I/O General I/O port pin
I/O General I/O port pin
I/O General I/O port pin
I/O General I/O port pin
I/O General I/O port pin
I/O General I/O port pin
PLD macrocell outputs
PLD inputs
Latched address out (A0-
A7)
Peripheral I/O mode
PLD macrocell outputs
PLD inputs
Latched address out (A0-
A7)
14/181
UPSD3212A, UPSD3212C, UPSD3212CV
UPSD321xx description
Table 2.
80-pin package pin description (continued)
Function
Port
pin
Signal
name
Pin
no.
In/
out
Basic
Alternate
JTAG
TMS
20
16
I
I
JTAG pin
JTAG pin
JTAG
TCK
PLD macrocell outputs
PLD inputs
PC3
PC4
TSTAT
14
9
I/O General I/O port pin
I/O General I/O port pin
TERR_
JTAG pins are dedicated
pins
JTAG
TDI
7
I
JTAG pin
JTAG pin
JTAG
TDO
6
5
O
PC7
PD1
I/O General I/O port pin
I/O General I/O port pin
PLD I/O
Clock input to PLD and
APD
CLKIN
3
1
PLD I/O
Chip select to PSD module
PD2
I/O General I/O port pin
Vcc
Vcc
12
50
13
29
69
10
11
17
71
GND
GND
GND
USB+
NC
NC
NC
1.1
52-pin package I/O port
The 52-pin package members of the UPSD321xx devices have the same port pins as those
of the 80-pin package except:
●
●
●
●
●
●
Port 0 (P0.0-P0.7, external address/data bus AD0-AD7)
Port 2 (P2.0-P2.3, external address bus A8-A11)
Port A (PA0-PA7)
Port D (PD2)
Bus control signal (RD,WR,PSEN,ALE)
Pin 5 requires a pull-up resistor (2 kΩ for 3 V devices, 7.5 kΩ for 5 V devices) for all
devices, with or without USB function.
15/181
Architecture overview
UPSD3212A, UPSD3212C, UPSD3212CV
2
Architecture overview
2.1
Memory organization
The UPSD321xx devices’ standard 8032 Core has separate 64-Kbyte address spaces for
Program memory and Data Memory. Program memory is where the 8032 executes
instructions from. Data memory is used to hold data variables. Flash memory can be
mapped in either program or data space. The Flash memory consists of two Flash memory
blocks: the main Flash memory (512 Kbit) and the Secondary Flash memory (128 Kbit).
Except during flash memory programming or update, Flash memory can only be read, not
written to. A Page Register is used to access memory beyond the 64-Kbyte address space.
Refer to the PSD module for details on mapping of the Flash memory.
The 8032 core has two types of data memory (internal and external) that can be read and
written. The internal SRAM consists of 256 bytes, and includes the stack area.
The SFR (Special Function Registers) occupies the upper 128 bytes of he internal SRAM,
the registers can be accessed by Direct addressing only. Another 2 bytes resides in the
PSD module that can be mapped to any address space defineby the user.
Figure 4.
Memory map and address space
MAIN
FLASH
EXT. RAM
INT. RAM
SFR
FF
SECONDARY
FLASH
Indirect
Addressing
Direct
Addressing
64KB
2KB
7F
Indirect
or
KB
Direct
Addressing
0
Internal RAM Space
(256 Bytes)
Flash Memory Space
External RAM Space
(MOVX)
AI07425
2.2
Registers
The 8032 has several registers; these are the Program Counter (PC), Accumulator (A), B
Register (B), the Stack Pointer (SP), the Program Status Word (PSW), General purpose
registers (R0 to R7), and DPTR (Data Pointer register).
16/181
UPSD3212A, UPSD3212C, UPSD3212CV
Architecture overview
Figure 5.
8032 MCU registers
Accumulator
B Register
A
B
Stack Pointer
SP
PCL
Program Counter
PCH
Program Status Word
General Purpose
Register (Bank0-3)
PSW
R0-R7
DPTR(DPH) DPTR(DPL) Data Pointer Register
AI06636
2.2.1
Accumulator
The Accumulator is the 8-bit general purpose register, used for data operation such as
transfer, temporary saving, and conditional tests. The Accumulator can be used as a 16-bit
register with B Register as shown below.
Figure 6.
Configuration of BA 16-bit registers
B
B
A
A
Two 8-bit Registern bused as a "BA" 16-bit Registers
AI06637
2.2.2
2.2.3
B register
The B Register the 8-bit general purpose register, used for an arithmetic operation such
as multiply, dsion with Accumulator.
Stack pointer
The Stack Pointer Register is 8 bits wide. It is incremented before data is stored during
PUSH and CALL executions. While the stack may reside anywhere in on-chip RAM, the
Stack Pointer is initialized to 07h after reset. This causes the stack to begin at location 08h.
Figure 7.
Stack pointer
Stack Area (30h-FFh)
Bit 8 Bit 7
Bit 15
Bit 0
00h
SP
00h-FFh
Hardware Fixed
SP (Stack Pointer) could be in 00h-FFh
AI06638
17/181
Architecture overview
UPSD3212A, UPSD3212C, UPSD3212CV
2.2.4
Program counter
The Program Counter is a 16-bit wide which consists of two 8-bit registers, PCH and PCL.
This counter indicates the address of the next instruction to be executed. In RESET state,
the program counter has reset routine address (PCH:00h, PCL:00h).
2.2.5
Program status word
The Program Status Word (PSW) contains several bits that reflect the current state of the
CPU and select Internal RAM (00h to 1Fh: Bank0 to Bank3). The PSW is described in
Figure 8. It contains the Carry flag, the Auxiliary Carry flag, the Half Carry (for BCD
operation), the General Purpose flag, the Register Bank Select flags, the Overflow flag, and
Parity flag.
[Carry flag, CY]. This flag stores any carry or not borrow from the ALU of CPU after an
arithmetic operation and is also changed by the Shift Instruction or Rotate Instruction.
[Auxiliary Carry flag, AC]. After operation, this flag is set when there is a carry from Bit 3 of
ALU or there is no borrow from Bit 4 of ALU.
[Register Bank Select flags, RS0, RS1]. These flags select onof four banks
(00~07H:bank0, 08~0Fh:bank1, 10~17h:bank2, 17~1Fh:bank3) in Internal RAM.
[Overflow flag, OV]. This flag is set to '1' when an overflow occurs as the result of an
arithmetic operation involving signs. An overflow occurs when the result of an addition or
subtraction exceeds +127 (7Fh) or -128 (80h). TCLRV instruction clears the overflow
flag. There is no set instruction. When the BIT instruction is executed, Bit 6 of memory is
copied to this flag.
[Parity flag, P]. This flag reflects the number of Accumulator’s 1. If the number of
Accumulator’s 1 is odd, P=0; otherwise, P=1. The sum when adding Accumulator’s 1 to P is
always even.
2.2.6
2.2.7
Registers R0~R7
General purpose 8-bit registers that are locked in the lower portion of internal data area.
Data pointer register
Data Pointer Register is 16-bit wide which consists of two-8bit registers, DPH and DPL. This
register is used as a data pointer for the data transmission with external data memory in the
PSD module.
Figure 8.
PSW (Program Status Word) register
MSB
LSB
P
CY AC FO RS1 RS0 OV
PSW
Reset Value 00h
Parity Flag
Carry Flag
Auxillary Carry Flag
General Purpose Flag
Bit not assigned
Overflow Flag
Register Bank Select Flags
(to select Bank0-3)
AI06639
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UPSD3212A, UPSD3212C, UPSD3212CV
Architecture overview
2.3
Program memory
The program memory consists of two Flash memories: the main Flash memory (64 Kbit)
and the Secondary Flash memory (16 Kbit). The Flash memory can be mapped to any
address space as defined by the user in the PSDsoft Tool. It can also be mapped to Data
memory space during Flash memory update or programming.
After reset, the CPU begins execution from location 0000h. As shown in Figure 9, each
interrupt is assigned a fixed location in Program Memory. The interrupt causes the CPU to
jump to that location, where it commences execution of the service routine. External
Interrupt 0, for example, is assigned to location 0003h. If External Interrupt 0 is going to be
used, its service routine must begin at location 0003h. If the interrupt is not going to be
used, its service location is available as general purpose Program Memory.
The interrupt service locations are spaced at 8-byte intervals: 0003h for External Interrupt 0,
000Bh for Timer 0, 0013h for External Interrupt 1, 001Bh for Timer 1 and so forth. If an
interrupt service routine is short enough (as is often the case in control applications), it can
reside entirely within that 8-byte interval. Longer service routines can use a jump instruction
to skip over subsequent interrupt locations, if other interrupts are in use
2.4
2.5
Data memory
The internal data memory is divided into four physically separated blocks: 256 bytes of
internal RAM, 128 bytes of Special Function Regters (SFRs) areas and 2 Kbytes (XRAM-
PSD) in the PSD module.
RAM
Four register banks, each 8 registers wide, occupy locations 0 through 31 in the lower RAM
area. Only one of these banks may be enabled at a time. The next 16 bytes, locations 32
through 47, conn 128 directly addressable bit locations. The stack depth is only limited by
the available ernal RAM space of 256 bytes.
Figure 9.
Interrupt location of program memory
008Bh
•
•
•
•
•
•
•
•
•
Interrupt
Location
0013h
8 Bytes
000Bh
0003h
Reset
0000h
AI06640
19/181
Architecture overview
UPSD3212A, UPSD3212C, UPSD3212CV
2.6
XRAM-PSD
The 2 Kbytes of XRAM-PSD resides in the PSD module and can be mapped to any address
space through the DPLD (Decoding PLD) as defined by the user in PSDsoft Development
tool.
2.7
SFR
The SFRs can only be addressed directly in the address range from 80h to FFh. Table 15
gives an overview of the Special Function Registers. Sixteen address in the SFRs space are
both-byte and bit-addressable. The bit-addressable SFRs are those whose address ends in
0h and 8h. The bit addresses in this area are 80h to FFh.
Table 3.
RAM address
Byte address
(in hexadecimal)
Byte address
(in decimal)
¯
¯
FFh
30h
MSB
255
48
Bit address (he)
LSB
78
2Fh
2Eh
2Dh
2Ch
2Bh
2Ah
29h
28h
27h
26h
25h
24h
23h
22h
21h
20h
1Fh
18h
17h
10h
0Fh
08h
07h
00h
7F
77
6F
67
5F
57
4F
7
3F
37
2F
27
1F
17
0F
07
7E
76
6E
66
5E
56
4E
46
3E
36
2E
26
1E
16
0E
06
7D
75
6D
65
5D
55
4D
45
3D
35
2D
25
1D
15
0D
05
7C
7
6C
64
5C
54
4C
44
3C
34
2C
24
1C
14
0C
04
7B
73
6B
63
5B
53
4B
43
3B
33
2B
23
1B
13
0B
03
7A
72
6A
62
5A
52
4A
42
3A
32
2A
22
1A
12
0A
02
79
71
69
61
59
51
49
41
39
31
29
21
19
11
09
01
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
24
23
16
15
8
70
68
60
58
50
48
40
38
30
28
20
18
10
08
00
Register bank 3
Register bank 2
Register bank 1
Register bank 0
7
0
20/181
UPSD3212A, UPSD3212C, UPSD3212CV
Architecture overview
2.8
Addressing modes
The addressing modes in UPSD321xx devices instruction set are as follows
1. Direct addressing
2. Indirect addressing
3. Register addressing
4. Register-specific addressing
5. Immediate constants addressing
6. Indexed addressing
2.8.1
Direct addressing
In a direct addressing the operand is specified by an 8-bit address field in the instruction.
Only internal Data RAM and SFRs (80~FFH RAM) can be directly addressed.
Example:
mov A, 3EH ; A <----- RAM[3E]
Figure 10. Direct addressing
Program Memory
A
3Eh
04
AI06641
2.8.2
Indirect addressing
In indirect addreing the instruction specifies a register which contains the address of the
operand. Botnternal and external RAM can be indirectly addressed. The address register
for 8-baddresses can be R0 or R1 of the selected register bank, or the Stack Pointer. The
address register for 16-bit addresses can only be the 16-bit “data pointer” register, DPTR.
Example:
mov @R1, #40 H ;[R1] <-----40H
Figure 11. Indirect addressing
Program Memory
55h
R1
40h
55
AI06642
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Architecture overview
UPSD3212A, UPSD3212C, UPSD3212CV
2.8.3
Register addressing
The register banks, containing registers R0 through R7, can be accessed by certain
instructions which carry a 3-bit register specification within the opcode of the instruction.
Instructions that access the registers this way are code efficient, since this mode eliminates
an address byte. When the instruction is executed, one of four banks is selected at
execution time by the two bank select bits in the PSW.
Example:
mov PSW, #0001000B ; select Bank0
mov A, #30H
mov R1, A
2.8.4
2.8.5
Register-specific addressing
Some instructions are specific to a certain register. For example, some instructions always
operate on the Accumulator, or Data Pointer, etc., so no address byte is needed to point it.
The opcode itself does that.
Immediate constants addressing
The value of a constant can follow the opcode in Program memory.
Example:
mov A, #10H.
2.8.6
Indexed addressing
Only Program memory can be accessed with indexed addressing, and it can only be read.
This addressing mode is intended for reading look-up tables in Program memory. A 16-bit
base register (either DPTR or PC) points to the base of the table, and the Accumulator is set
up with the table ntry number. The address of the table entry in Program memory is formed
by adding the ccumulator data to the base pointer.
Example:
movc A, @A+DPTR
Figure 12. Indexed addressing
ACC
3Ah
DPTR
1E73h
Program Memory
3Eh
AI06643
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UPSD3212A, UPSD3212C, UPSD3212CV
Architecture overview
2.9
Arithmetic instructions
The arithmetic instructions is listed in Table 4. The table indicates the addressing modes
that can be used with each instruction to access the <byte> operand. For example, the ADD
A, <byte> instruction can be written as:
ADD a, 7FH (direct addressing)
ADD A, @R0 (indirect addressing)
ADD a, R7 (register addressing)
ADD A, #127 (immediate constant)
Note:
Any byte in the internal Data Memory space can be incremented without going through the
Accumulator.
One of the INC instructions operates on the 16-bit Data Pointer. The Data Pointer is used to
generate 16-bit addresses for external memory, so being able to increment it in one 16-bit
operation is a useful feature.
The MUL AB instruction multiplies the Accumulator by the data in the B rgister and puts the
16-bit product into the concatenated B and Accumulator registers.
The DIV AB instruction divides the Accumulator by the data in the B register and leaves the
8-bit quotient in the Accumulator, and the 8-bit remainder n the B register.
In shift operations, dividing a number by 2n shifts its n” bits to the right. Using DIV AB to
perform the division completes the shift in 4?s anleaves the B register holding the bits that
were shifted out. The DAA instruction is for BCD arithmetic operations. In BCD arithmetic,
ADD and ADDC instructions should ays be followed by a DAA operation, to ensure that
the result is also in BCD.
Note:
DAA will not convert a binary number to BCD. The DAA operation produces a meaningful
result only as the second step in the addition of two BCD bytes.
Table 4.
Arithmetic instructions
Addressing modes
Memonic
Operation
Dir.
Ind.
Reg.
Imm.
ADD A,<byte>
ADDC A,<byte>
SUBB A,<byte>
INC
A = A + <byte>
A = A + <byte> + C
A = A – <byte> – C
A = A + 1
X
X
X
X
X
X
X
X
X
X
X
X
Accumulator only
INC <byte>
INC DPTR
DEC
<byte> = <byte> + 1
DPTR = DPTR + 1
A = A – 1
X
X
X
X
Data Pointer only
Accumulator only
DEC <byte>
MUL AB
<byte> = <byte> – 1
B:A = B x A
X
X
Accumulator and B only
Accumulator and B only
Accumulator only
A = Int[ A / B ]
DIV AB
DA A
B = Mod[ A / B ]
Decimal Adjust
23/181
Architecture overview
UPSD3212A, UPSD3212C, UPSD3212CV
2.10
Logical instructions
Table 5 lists logical instructions for UPSD321xx devices. The instructions that perform
Boolean operations (AND, OR, Exclusive OR, NOT) on bytes perform the operation on a bit-
by-bit basis. That is, if the Accumulator contains 00110101B and byte contains 01010011B,
then:
ANL A, <byte>
will leave the Accumulator holding 00010001B.
The addressing modes that can be used to access the <byte> operand are listed in Table 5.
The ANL A, <byte> instruction may take any of the forms:
ANL A,7FH(direct addressing)
ANL A, @R1 (indirect addressing)
ANL A,R6 (register addressing)
ANL A,#53H (immediate constant)
Note:
Boolean operations can be performed on any byte in the internal Data Memory space
without going through the Accumulator. The XRL <byte>, #datinstruction, for example,
offers a quick and easy way to invert port bits, as in:
XRL P1, #0FFH.
If the operation is in response to an interrupt, not using the Accumulator saves the time and
effort to push it onto the stack in the service routine.
The Rotate instructions (RL A, RLC A, .) shift the Accumulator 1 bit to the left or right. For
a left rotation, the MSB rolls into the LSB position. For a right rotation, the LSB rolls into the
MSB position.
The SWAP A instruction interchanges the high and low nibbles within the Accumulator. This
is a useful operation in BCD manipulations. For example, if the Accumulator contains a
binary number which is known to be less than 100, it can be quickly converted to BCD by
the following co
MOVE B,#10
DIV AB
SWAP A
ADD A,B
Dividing the number by 10 leaves the tens digit in the low nibble of the Accumulator, and the
ones digit in the B register. The SWAP and ADD instructions move the tens digit to the high
nibble of the Accumulator, and the ones digit to the low nibble.
Table 5.
Logical instructions
Addressing modes
Mnemonic
Operation
Dir.
Ind.
Reg.
Imm.
ANL A,<byte>
ANL <byte>,A
A = A .AND. <byte>
A = <byte> .AND. A
A = <byte> .AND. #data
A = A .OR. <byte>
X
X
X
X
X
X
X
ANL <byte>,#data
ORL A,<byte>
X
X
X
24/181
UPSD3212A, UPSD3212C, UPSD3212CV
Table 5. Logical instructions
Mnemonic
Architecture overview
Addressing modes
Operation
Dir.
Ind.
Reg.
Imm.
ORL <byte>,A
ORL <byte>,#data
XRL A,<byte>
XRL <byte>,A
XRL <byte>,#data
CRL A
A = <byte> .OR. A
A = <byte> .OR. #data
A = A .XOR. <byte>
A = <byte> .XOR. A
A = <byte> .XOR. #data
A = 00h
X
X
X
X
X
X
X
X
Accumulator only
Accumulator only
Accumulator only
Accumulator only
Acculator only
Accumulator only
Accumulator only
CPL A
A = .NOT. A
RL A
Rotate A Left 1 bit
RLC A
Rotate A Left through Carry
Rotate A Right 1 bit
Rotate A Right through Carry
Swap Nibbles in A
RR A
RRC A
SWAP A
2.11
Data transfers
2.11.1
Internal RAM
Table 6 shows the menu of instructions that are available for moving data around within the
internal memory spaces, and the addressing modes that can be used with each one. The
MOV <dest>, <src> instruction allows data to be transferred between any two internal RAM
or SFR locations ithout going through the Accumulator. Remember, the Upper 128 bytes of
data RAM cabe accessed only by indirect addressing, and SFR space only by direct
addresing.
Note:
In UPSD321xx devices, the stack resides in on-chip RAM, and grows upwards. The PUSH
instruction first increments the Stack Pointer (SP), then copies the byte into the stack. PUSH
and POP use only direct addressing to identify the byte being saved or restored, but the
stack itself is accessed by indirect addressing using the SP register. This means the stack
can go into the Upper 128 bytes of RAM, if they are implemented, but not into SFR space.
The Data Transfer instructions include a 16-bit MOV that can be used to initialize the Data
Pointer (DPTR) for look-up tables in Program Memory.
The XCH A, <byte> instruction causes the Accumulator and ad-dressed byte to exchange
data. The XCHD A, @Ri instruction is similar, but only the low nibbles are involved in the
exchange. To see how XCH and XCHD can be used to facilitate data manipulations,
consider first the problem of shifting and 8-digit BCD number two digits to the right. Table 8
shows how this can be done using XCH instructions. To aid in understanding how the code
works, the contents of the registers that are holding the BCD number and the content of the
Accumulator are shown alongside each instruction to indicate their status after the
instruction has been executed.
25/181
Architecture overview
UPSD3212A, UPSD3212C, UPSD3212CV
After the routine has been executed, the Accumulator contains the two digits that were
shifted out on the right. Doing the routine with direct MOVs uses 14 code bytes. The same
operation with XCHs uses only 9 bytes and executes almost twice as fast. To right-shift by
an odd number of digits, a one-digit must be executed. Table 9 shows a sample of code that
will right-shift a BCD number one digit, using the XCHD instruction. Again, the contents of
the registers holding the number and of the accumulator are shown alongside each
instruction.
Table 6.
Data transfer instructions that access internal data memory space
Addressing modes
Mnemonic
Operation
Dir.
Ind.
Reg.
Imm.
MOV A,<src>
A = <src>
<dest> = A
X
X
X
X
X
X
X
X
X
X
MOV <dest>,A
MOV <dest>,<src>
<dest> = <src>
X
X
DPTR = 16-bit immediate
constant
MOV DPTR,#data16
PUSH <src>
POP <dest>
INC SP; MOV “@SP”,<src>
MOV <dest>,”@SP”; DEC SP
X
X
Exchange contents of A and
<byte>
XCH A,<byte>
XCHD A,@Ri
X
X
X
X
Exchange low nis of A and
@Ri
First, pointers R1 and R0 are set up to point to the two bytes containing the last four BCD
digits. Then a loop is executed which leaves the last byte, location 2EH, holding the last two
digits of the shifted number. The pointers are decremented, and the loop is repeated for
location 2DH. The CJNE instruction (Compare and Jump if Not equal) is a loop control that
will be described ater. The loop executed from LOOP to CJNE for R1 = 2EH, 2DH, 2CH,
and 2B. At that point the digit that was originally shifted out on the right has propagated to
location 2AH. Since that location should be left with 0s, the lost digit is moved to the
Acumulator.
Table 7.
Shifting a BCD number 2 digits to the right (using direct MOVs: 14 bytes)
2A
2B
2C
2D
2E
ACC
MOV
MOV
MOV
MOV
MOV
A,2Eh
00
00
00
00
00
12
12
12
12
00
34
34
34
12
12
56
56
34
34
34
78
56
56
56
56
78
78
78
78
78
2Eh,2Dh
2Dh,2Ch
2Ch,2Bh
2Bh,#0
26/181
UPSD3212A, UPSD3212C, UPSD3212CV
Architecture overview
Table 8.
Shifting a BCD number 2 digits to the right (using direct XCHs: 9 bytes)
2A
2B
2C
2D
2E
ACC
CLR
XCH
XCH
XCH
XCH
A
00
00
00
00
00
12
00
00
00
00
34
34
12
12
12
56
56
56
34
34
78
78
78
78
56
00
12
34
56
78
A,2Bh
A,2Ch
A,2Dh
A,2Eh
Table 9.
Shifting a BCD number one digit to the right
2A
2B
2C
2D
2E
ACC
MOV
MOV
R1,#2Eh
R0,#2Dh
00
00
12
12
34
34
56
56
78
78
xx
xx
; loop for R1 = 2Eh
LOOP:
MOV
XCHD
SWAP
MOV
DEC
A,@R1
00
00
00
00
00
00
00
12
12
12
12
12
12
12
4
34
34
34
34
34
34
56
58
58
58
58
58
58
78
78
78
67
67
67
67
78
76
67
67
67
67
67
A,@R0
A
@R1,A
R1
DEC
R0
CNJE
R1,#2Ah,LOOP
; loop for R1 = 2Dh
; loop for R1 = 2Ch
; loop or R1 = 2Bh
00
00
08
12
18
01
38
23
23
45
45
45
67
67
67
45
23
01
CLR
XCH
A
08
00
01
01
23
23
45
45
67
67
00
08
A,2Ah
2.11.2
External RAM
Table 10 shows a list of the Data Transfer instructions that access external Data Memory.
Only indirect addressing can be used. The choice is whether to use a one-byte address,
@Ri, where Ri can be either R0 or R1 of the selected register bank, or a two-byte
address, @DTPR.
Note:
In all external Data RAM accesses, the Accumulator is always either the destination or
source of the data.
27/181
Architecture overview
UPSD3212A, UPSD3212C, UPSD3212CV
2.11.3
Lookup tables
Table 11 shows the two instructions that are available for reading lookup tables in Program
Memory. Since these instructions access only Program Memory, the lookup tables can only
be read, not updated.
The mnemonic is MOVC for “move constant.” The first MOVC instruction in Table 11 can
accommodate a table of up to 256 entries numbered 0 through 255. The number of the
desired entry is loaded into the Accumulator, and the Data Pointer is set up to point to the
beginning of the table. Then:
MOVC A, @A+DPTR
copies the desired table entry into the Accumulator.
The other MOVC instruction works the same way, except the Program Counter (PC) is used
as the table base, and the table is accessed through a subroutine. First the number of the
desired en-try is loaded into the Accumulator, and the subroutine is called:
MOV A , ENTRY NUMBER
CALL TABLE
The subroutine “TABLE” would look like this:
TABLE: MOVC A , @A+PC
RET
The table itself immediately follows the RET (ret) instruction is Program Memory. This
type of table can have up to 255 entries, numbered 1 through 255. Number 0 cannot be
used, because at the time the MOVC iuction is executed, the PC contains the address of
the RET instruction. An entry numbered 0 would be the RET opcode itself.
Table 10. Data transfer instruction that access external data memory space
Address Width
Mnemonic
Operation
8 bits
8 bits
MOVX A,@Ri
MOVX @Ri,A
READ external RAM @Ri
WRITE external RAM @Ri
READ external RAM @DPTR
WRITE external RAM @DPTR
1bits
16 bits
MOVX A,@DPTR
MOVX @DPTR,a
Table 11. Lookup table READ instruction
Mnemonic
Operation
MOVC A,@A+DPTR
MOVC A,@A+PC
READ program memory at (A+DPTR)
READ program memory at (A+PC)
28/181
UPSD3212A, UPSD3212C, UPSD3212CV
Architecture overview
2.12
Boolean instructions
The UPSD321xx devices contain a complete Boolean (single-bit) processor. One page of
the internal RAM contains 128 address-able bits, and the SFR space can support up to 128
addressable bits as well. All of the port lines are bit-addressable, and each one can be
treated as a separate single-bit port. The instructions that access these bits are not just
conditional branches, but a complete menu of move, set, clear, complement, OR and AND
instructions. These kinds of bit operations are not easily obtained in other architectures with
any amount of byte-oriented software.
The instruction set for the Boolean processor is shown in Table 12. All bits accesses are by
direct addressing.
Bit addresses 00h through 7Fh are in the Lower 128, and bit addresses 80h through FFh
are in SFR space.
Note how easily an internal flag can be moved to a port pin:
MOV C,FLAG
MOV P1.0,C
In this example, FLAG is the name of any addressable bit in tLower 128 or SFR space.
An I/O line (the LSB of Port 1, in this case) is set or cleared depending on whether the Flag
bit is '1' or '0.'
The Carry Bit in the PSW is used as the single-bit Accumulator of the Boolean processor. Bit
instructions that refer to the Carry Bit as C assemble as Carry-specific instructions (CLR C,
etc.). The Carry Bit also has a direct addre, since it resides in the PSW register, which is
bit-addressable.
Note:
The Boolean instruction set includes ANL and ORL operations, but not the XRL (Exclusive
OR) operation. An XRL operation is simple to implement in software. Suppose, for example,
it is required to form the Exclusive OR of two bits:
C = bit 1 .XRL. bit2
The software to do that could be as follows:
MV C , bit1
JNB bit2, OVER
CPL C
OVER: (continue)
First, Bit 1 is moved to the Carry. If bit2 = 0, then C now contains the correct result. That is,
Bit 1 .XRL. bit2 = bit1 if bit2 = 0. On the other hand, if bit2 = 1, C now contains the
complement of the correct result. It need only be inverted (CPL C) to complete the
operation.
This code uses the JNB instruction, one of a series of bit-test instructions which execute a
jump if the addressed bit is set (JC, JB, JBC) or if the addressed bit is not set (JNC, JNB). In
the above case, Bit 2 is being tested, and if bit2 = 0, the CPL C instruction is jumped over.
JBC executes the jump if the addressed bit is set, and also clears the bit. Thus a flag can be
tested and cleared in one operation. All the PSW bits are directly addressable, so the Parity
Bit, or the general-purpose flags, for example, are also available to the bit-test instructions.
29/181
Architecture overview
UPSD3212A, UPSD3212C, UPSD3212CV
Operation
Table 12. Boolean instructions
Mnemonic
ANL C,bit
ANL C,/bit
ORL C,bit
ORL C,/bit
MOV C,bit
MOV bit,C
CLR C
C = A .AND. bit
C = C .AND. .NOT. bit
C = A .OR. bit
C = C .OR. .NOT. bit
C = bit
bit = C
C = 0
CLR bit
bit = 0
SETB C
SETB bit
CPL C
C = 1
bit = 1
C = .NOT
bit = .NOT. bit
Jump if C =1
Jump if C = 0
Jump if bit =1
Jump if bit = 0
Jump if bit = 1; CLR bit
CPL bit
JC rel
JNC rel
JB bit,rel
JNB bit,rel
JBC bit,rel
2.13
2.14
Relative offset
The destination dress for these jumps is specified to the assembler by a label or by an
actual address in Program memory. However, the destination address assembles to a
relative offset byte. This is a signed (two’s complement) offset byte which is added to the PC
in two’s complement arithmetic if the jump is executed.
The range of the jump is therefore -128 to +127 Program Memory bytes relative to the first
byte following the instruction.
Jump instructions
Table 13 shows the list of unconditional jump instructions. The table lists a single “JMP add”
instruction, but in fact there are three SJMP, LJMP, and AJMP, which differ in the format of
the destination address. JMP is a generic mnemonic which can be used if the programmer
does not care which way the jump is en-coded.
The SJMP instruction encodes the destination address as a relative offset, as described
above. The instruction is 2 bytes long, consisting of the opcode and the relative offset byte.
The jump distance is limited to a range of -128 to +127 bytes relative to the instruction
following the SJMP.
30/181
UPSD3212A, UPSD3212C, UPSD3212CV
Architecture overview
The LJMP instruction encodes the destination address as a 16-bit constant. The instruction
is 3 bytes long, consisting of the opcode and two address bytes. The destination address
can be anywhere in the 64K Program Memory space.
The AJMP instruction encodes the destination address as an 11-bit constant. The
instruction is 2 bytes long, consisting of the opcode, which itself contains 3 of the 11 address
bits, followed by another byte containing the low 8 bits of the destination address. When the
instruction is executed, these 11 bits are simply substituted for the low 11 bits in the PC. The
high 5 bits stay the same. Hence the destination has to be within the same 2K block as the
instruction following the AJMP.
In all cases the programmer specifies the destination address to the assembler in the same
way: as a label or as a 16-bit constant. The assembler will put the destination address into
the correct format for the given instruction. If the format required by the instruction will not
support the distance to the specified destination address, a “Destination out of range”
message is written into the List file.
The JMP @A+DPTR instruction supports case jumps. The destination address is computed
at execution time as the sum of the 16-bit DPTR register and the Accuulator. Typically.
DPTR is set up with the address of a jump table. In a 5-way branch, ex-ample, an integer
0 through 4 is loaded into the Accumulator. The code to be exuted might be as follows:
MOV DPTR,#JUMP TABLE
MOV A,INDEX_NUMBER
RL A
JMP @A+DPTR
The RL A instruction converts the indumber (0 through 4) to an even number on the
range 0 through 8, because each entry in the jump table is 2 bytes long:
JUMP TABLE:
AJMP CASE 0
AJMP CASE 1
AJMP CAS2
AJP CASE 3
AJMP CASE 4
Table 13 shows a single “CALL addr” instruction, but there are two of them, LCALL and
ACALL, which differ in the format in which the subroutine address is given to the CPU. CALL
is a generic mnemonic which can be used if the programmer does not care which way the
address is encoded.
The LCALL instruction uses the 16-bit address format, and the subroutine can be anywhere
in the 64K Program Memory space. The ACALL instruction uses the 11-bit format, and the
subroutine must be in the same 2K block as the instruction following the ACALL.
In any case, the programmer specifies the subroutine address to the assembler in the same
way: as a label or as a 16-bit constant. The assembler will put the address into the correct
format for the given instructions.
Subroutines should end with a RET instruction, which returns execution to the instruction
following the CALL.
RETI is used to return from an interrupt service routine. The only difference between RET
and RETI is that RETI tells the interrupt control system that the interrupt in progress is done.
31/181
Architecture overview
UPSD3212A, UPSD3212C, UPSD3212CV
If there is no interrupt in progress at the time RETI is executed, then the RETI is functionally
identical to RET.
Table 13. Unconditional Jump instructions
Mnemonic
Operation
JMP addr
JMP @A+DPTR
CALL addr
RET
Jump to addr
Jump to A+DPTR
Call Subroutine at addr
Return from subroutine
Return from interrupt
No operation
RETI
NOP
Table 14 shows the list of conditional jumps available to the UPSD321xx device user. All of
these jumps specify the destination address by the relative offset method, and so are limited
to a jump distance of -128 to +127 bytes from the instruction following e conditional jump
instruction. Important to note, however, the user specifies to the assmbler the actual
destination address the same way as the other jumps: as a lael or a 16-bit constant.
There is no Zero Bit in the PSW. The JZ and JNZ instructons test the Accumulator data for
that condition.
The DJNZ instruction (Decrement and Jump if NZero) is for loop control. To execute a
loop N times, load a counter byte with N anterminate the loop with a DJNZ to the
beginning of the loop, as shown below N = 10:
MOV COUNTER,#10
LOOP: (begin loop)
•
•
•
(end loo)
DZ COUNTER, LOOP
(continue)
The CJNE instruction (Compare and Jump if Not Equal) can also be used for loop control as
in Table 9. Two bytes are specified in the operand field of the instruction. The jump is
executed only if the two bytes are not equal. In the example of Table 9 Shifting a BCD
Number One Digits to the Right, the two bytes were data in R1 and the constant 2Ah. The
initial data in R1 was 2Eh.
Every time the loop was executed, R1 was decremented, and the looping was to continue
until the R1 data reached 2Ah.
Another application of this instruction is in “greater than, less than” comparisons. The two
bytes in the operand field are taken as unsigned integers. If the first is less than the second,
then the Carry Bit is set (1). If the first is greater than or equal to the second, then the Carry
Bit is cleared.
32/181
UPSD3212A, UPSD3212C, UPSD3212CV
Architecture overview
2.15
Machine cycles
A machine cycle consists of a sequence of six states, numbered S1 through S6. Each state
time lasts for two oscillator periods. Thus, a machine cycle takes 12 oscillator periods or 1µs
if the oscillator frequency is 12MHz. Refer to Table 13: State sequence in UPSD321xx
devices.
Each state is divided into a Phase 1 half and a Phase 2 half. State Sequence in UPSD321xx
devices shows that retrieve/execute sequences in states and phases for various kinds of
instructions.
Normally two program retrievals are generated during each machine cycle, even if the
instruction being executed does not require it. If the instruction being executed does not
need more code bytes, the CPU simply ignores the extra retrieval, and the Program Counter
is not incremented.
Execution of a one-cycle instruction (Figure 13: State sequence in UPSD321xx devices)
begins during State 1 of the machine cycle, when the opcode is latched into the Instruction
Register. A second retrieve occurs during S4 of the same machine cycl. Execution is
complete at the end of State 6 of this machine cycle.
The MOVX instructions take two machine cycles to execute. No program retrieval is
generated during the second cycle of a MOVX instruction. This is the only time program
retrievals are skipped. The retrieve/execute sequence for MOVX instruction is shown in
Figure 13 (d).
Table 14. Conditional jump instructio
Addressing modes
Mnemonic
Operation
Dir.
Ind.
Reg.
Imm.
JZ rel
Jump if A = 0
Accumulator only
Accumulator only
X
JNZ rel
Jump if A ≠ 0
DJNZ <byte>
Decrement and jump if not zero
Jump if A ≠ <byte>
X
X
CJNE A,<byte>,rel
CJNE <byte>,#data,rel
X
Jump if <byte> ≠ #data
X
X
33/181
Architecture overview
UPSD3212A, UPSD3212C, UPSD3212CV
Figure 13. State sequence in UPSD321xx devices
S1
S2
S3
S4
S5
S6
S1
S2
S3
S4
S5
S6
Osc.
(XTAL2)
p1 p2 p1 p2 p1 p2 p1 p2 p1 p2 p1 p2 p1 p2 p1 p2 p1 p2 p1 p2 p1 p2 p1 p2
Read next
opcode and
discard
Read next
opcode
Read opcode
S1
S2
S3
S4
S5
S6
S6
S6
S6
a. 1-Byte, 1-Cycle Instruction, e.g. INC A
Read next
opcode
Read 2nd
Byte
Read opcode
S1
S2
S3
S4
S5
b. 2-Byte, 1-Cycle Instruction, e.g. ADD A, adrs
Read next
opcode and
discard
Read next
opcode and
discard
Read next
opcode and
discard
Read next
opcode
Read opcode
S1
S2
S3
S4
S5
S1
S2
S3
S4
S
S6
c. 1-Byte, 2-Cycle Instruction, e.g. INC DPTR
No Fetch
No ALE
No Fetch
Read next
opcode and
discard
Read next
opcode
Read opcode
(MOVX)
S1
S2
S3
S4
S5
Addr
S2
S3
S4
S5
S6
Data
d. 1-Byte, 2-Cycle MOVX Instruction
Access External Memory
AI06822
34/181
UPSD3212A, UPSD3212C, UPSD3212CV
UPSD321xx hardware description
3
UPSD321xx hardware description
The UPSD321xx devices have a modular architecture with two main functional modules: the
MCU module and the PSD module. The MCU module consists of a standard 8032 core,
peripherals and other system supporting functions. The PSD module provides configurable
Program and Data memories to the 8032 CPU core. In addition, it has its own set of I/O
ports and a PLD with 16 macrocells for general logic implementation. Ports A,B,C, and D
are general purpose programmable I/O ports that have a port architecture which is different
from Ports 0-4 in the MCU module.
The PSD module communicates with the CPU Core through the internal address, data bus
(A0-A15, D0-D7) and control signals (RD_, WR_, PSEN_ , ALE, RESET_). The user
defines the Decoding PLD in the PSDsoft Development Tool and can map the resources in
the PSD module to any program or data address space.
Figure 14. UPSD321xx functional modules
Port 1, Timers and
2nd UART and ADC
cated
USB Pins
Port 3, UART,
Port 4 PWM
2
Intr, Timers,I C
Port 3
Port 1
I2C
3 Timer /
8032 Core
4
USB
&
Transceiver
PWM
5
Channels
Reset Logic
LVD & WDT
Channel
2 UARTs
ADC
Counters
256 Byte SRAM
Interrupt
MCU MODULE
Port 0, 2
Ext. Bus
8032 Internal Bus
A0-A15
RD,PSEN
WR,ALE
Reset
D0-D7
PSD MODULE
128Kb
Secondary
Flash
Bus
Interface
512Kb
Main Flash
16Kb
SRAM
Page Register
Decode PLD
PSD Internal Bus
VCC, GND,
XTAL
JTAG ISP
CPLD - 16 MACROCELLS
Port C,
JTAG, PLD I/O
and GPIO
Port A & B, PLD
I/O and GPIO
Port D
GPIO
Dedicated
Pins
AI07426b
35/181
MCU module description
UPSD3212A, UPSD3212C, UPSD3212CV
4
MCU module description
This section provides a detail description of the MCU module system functions and
Peripherals, including:
●
●
●
●
●
●
●
●
●
●
●
Special function registers
Timers/counter
Interrupts
PWM
Supervisory function (LVD and Watchdog)
USART
Power-saving modes
2
I C Bus
On-chip oscillator
ADC
I/O Ports
4.1
Special function registers
A map of the on-chip memory area called the Special Function Register (SFR) space is
shown in Table 15.
Note:
In the SFRs not all of the addresses are occupied. Unoccupied addresses are not
implemented on the chip. READ accesses to these addresses will in general return random
data, and WRITE accesses will have no effect. User software should write '0s' to these
unimplemented locations.
Table 15. SFR memory mp
F8
FF
F7
EF
E7
DF
D7
CF
C7
BF
B7
AF
A7
9F
97
F0
E8
E0
D8
D0
C8
C0
B8
B0
A8
A0
98
90
B(1)
UISTA(1)
ACC(1)
UIEN
UCON0
UCON1
UCON2
S2CON
TL2
USTA
S2STA
TH2
UADR
UDT1
S2DAT
UDR0
UDT0
USCL
S2ADR
PSW(1)
T2CON(1)
P4(1)
T2MOD
PSCL0L
RCAP2L RCAP2H
IP(1)
P3(1)
PSCL0H PSCL1L PSCL1H
PWM4P PWM4W
IPA
IEA
IE(1)
WDKEY
WDRST
P2(1)
PWMCON
SBUF
PWM0
PWM1
SBUF2
P3SFS
PWM2
PWM3
ASCL
SCON
P1(1)
SCON2
P1SFS
P4SFS
ADAT
ACON
36/181
UPSD3212A, UPSD3212C, UPSD3212CV
Table 15. SFR memory map (continued)
MCU module description
88
TCON(1)
TMOD
TL0
TL1
TH0
TH1
8F
80
P0(1)
SP
DPL
DPH
PCON
87
1. Register can be bit addressing
Table 16. List of all SFRs
Bit Register Name
Reg Name
7
Comments
6
5
4
3
2
1
0
80
81
82
83
87
P0
SP
FF
07
Port 0
Stack Ptr
DPL
DPH
PCON
00 Data Ptr Low
00 Data Ptr High
SMOD
TF1
SMOD1 LVREN ADSFINT RCLK1
TCLK1
IT1
PD
IE0
IDLE
0
00
00
Power Ctrl
Timer / Cntr
Control
88
89
TCON
TMOD
TR1
C/T
TF0
M1
TR0
M0
IE1
Timer / Cntr
mode Control
Gate
Gate
C/T
M1
M0
00
8A
8B
8C
8D
90
TL0
TL1
TH0
TH1
P1
00
00
Timer 0 Low
Timer 1 Low
00 Timer 0 High
00 Timer 1 High
FF
00
Port 1
Port 1 Select
Register
91
93
94
P1SFS
P3SFS
P4SFS
P1S7
P3S7
P4S7
P1S6
PS6
P4S6
P1S5
P4S5
P1S4
P4S4
Port 3 Select
Register
00
00
Port 4 Select
Register
P4S3
P4S2
P4S1
P4S0
8-bit
95
ASCL
00
Prescaler for
ADC clock
ADC Data
Register
96
97
ADAT
ADAT7
ADAT6
ADAT5
ADEN
SM2
ADAT4
ADAT3
ADS1
TB8
ADAT2
ADS0
RB8
ADAT1
ADST
TI
ADAT0
ADSF
RI
00
00
ADC Control
Register
ACON
SerialControl
Register
98
99
9A
SCON
SBUF
SM0
SM0
SM1
SM1
REN
REN
00
00
00
Serial Buffer
2nd UART
Ctrl Register
SCON2
SM2
TB8
RB8
TI
RI
2nd UART
Serial Buffer
9B
A0
SBUF2
P2
00
FF
Port 2
37/181
MCU module description
UPSD3212A, UPSD3212C, UPSD3212CV
Table 16. List of all SFRs (continued)
Bit Register Name
Reg Name
Comments
7
6
5
4
3
2
1
0
PWMControl
Polarity
A1 PWMCON
PWML
PWMP
PWME
CFG4
CFG3
CFG2
CFG1
CFG0
00
00
PWM0
Output Duty
Cycle
A2
A3
A4
A5
PWM0
PWM1
PWM2
PWM3
PWM1
Output Duty
Cycle
00
00
00
PWM2
Output Duty
Cycle
PWM3
Output Duty
Cycle
Watch Dog
Reset
A6
A7
WDRST
IEA
00
00
00
Interrupt
Enable (2nd)
ES2
ES
EI2C
ET0
Interrupt
Enable
A8
A9
AA
IE
EA
-
ET2
ET1
EX1
EX0
PWM 4
Period
PWM4P
PWM4W
00
00
PWM 4 Pulse
Width
AB
Watch Dog
Key Register
AE
B0
B1
WDKEY
P3
00
FF
00
Port 3
Prescaler 0
Low (8-bit)
PSCL0L
Prescaler 0
High (8-bit)
B2
B3
B4
B7
PSCL0H
PSCL1L
PSCL1H
IPA
00
00
00
00
Prescaler 1
Low (8-bit)
Prescaler 1
High (8-bit)
Interrupt
Priority (2nd)
PS2
PS
PI2C
PT0
Interrupt
Priority
B8
C0
C8
IP
P4
PT2
PT1
PX1
TR2
PX0
00
FF
00
New Port 4
Timer 2
Control
T2CON
TF2
EXF2
RCLK
TCLK
EXEN2
C/T2
CP/RL2
38/181
UPSD3212A, UPSD3212C, UPSD3212CV
MCU module description
Table 16. List of all SFRs (continued)
Bit Register Name
Reg Name
Comments
0
7
6
5
4
3
2
1
Timer 2
mode
C9
CA
CB
CC
CD
D0
T2MOD
RCAP2L
RCAP2H
TL2
DCEN
00
00
00
00
00
00
00
00
00
00
Timer 2
Reload low
Timer 2
Reload High
Timer 2 Low
byte
Timer 2 High
byte
TH2
Program
Status Word
PSW
CY
AC
FO
RS1
RS0
OV
P
I2C (S2)
Setup
D2 S2SETUP
I2C Bus
Control Reg
DC
DD
DE
S2CON
S2STA
S2DAT
CR2
GC
EN1
Stop
STA
Intr
STO
ADDR
Bbusy
AA
CR1
CR0
SLV
I2C Bus
Status
TX-Md
Blost
ACK_R
Data Hold
Register
DF
E0
S2ADR
ACC
00
00
I2C address
Accumulator
8-bit
E1
USCL
00
Prescaler for
USB logic
USB Endpt1
Data Xmit
E6
E7
E8
E9
EA
EB
EC
ED
EE
UDT1
UDT0
U.7
UDT0.7
UDT1.6 UDT1.5 UDT1.4 UDT1.3 UDT1.2 UDT1.1 UDT1.0
UDT0.6 UDT0.5 UDT0.4 UDT0.3 UDT0.2 UDT0.1 UDT0.0
00
00
USB Endpt0
Data Xmit
USBInterrupt
Status
UISTA
UIEN
SUSPND
—
RSTF
TXD0F
RXD0F RXD1F
EOPF RESUMF 00
00
USBInterrupt
Enable
USB Endpt0
Xmit Control
UCON0
UCON1
UCON2
USTA
TSEQ0
TSEQ1
—
STALL0
EP12SEL
—
TX0E
—
RX0E
TP0SIZ3 TP0SiZ2 TP0SIZ1 TP0SIZ0
00
00
00
00
00
USB Endpt1
Xmit Control
FRESUM TP1SIZ3 TP1SiZ2 TP1SIZ1 TP1SIZ0
USB Control
Register
—
SOUT
OUT
EP2E
EP1E
STALL2 STALL1
USB Endpt0
Status
RSEQ
USBEN
SETUP
IN
RP0SIZ3 RP0SIZ2 RP0SIZ1 RP0SIZ0
USBAddress
Register
UADR
UADD6 UADD5 UADD4 UADD3 UADD2 UADD1 UADD0
39/181
MCU module description
UPSD3212A, UPSD3212C, UPSD3212CV
Table 16. List of all SFRs (continued)
Bit Register Name
Reg Name
Comments
7
6
5
4
3
2
1
0
USB Endpt0
Data Recv
EF
F0
UDR0
B
UDR0.7
UDR0.6 UDR0.5 UDR0.4 UDR0.3 UDR0.2 UDR0.1 UDR0.0
00
00
B Register
Table 17. PSD module register address offset
CSIOP
addr Register name
offset
Bit register name
Reset
value
Comments
7
6
5
4
3
2
1
0
00
02
Data In (Port A)
Control (Port A)
Reads Port pins as input
Configure pin between I/O or Address Out mode. Bit = 0 selects
I/O
00
00
00
00
Data Out (Port
A)
04
06
08
0A
0C
Latched data for output to Port pins, I/O Output mode
Configures Port pin as input or output. Bit = 0 slects input
Direction (Port
A)
Configures Port pin between CMOS, Open Drain or Slew rate. Bit
= 0 selects CMOS
Drive (Port A)
Input Macrocell
(Port A)
Reads latched von Input Macrocells
Enable Out
(Port A)
Reads the status of the output enable control to the Port pin
driver. Bit = 0 indicates pin is in input mode.
01
03
Data In (Port B)
Control (Port B)
00
00
Data Out (Port
B)
05
Directin (Port
B)
07
09
0B
00
00
Drive (Port B)
Input Macrocell
(Port B)
Enable Out
(Port B)
0D
10
12
Data In (Port C)
Data Out (Port
C)
00
Direction (Port
C)
14
16
18
00
00
Drive (Port C)
Input Macrocell
(Port C)
40/181
UPSD3212A, UPSD3212C, UPSD3212CV
MCU module description
Table 17. PSD module register address offset (continued)
CSIOP
addr Register name
offset
Bit register name
Reset
Comments
value
7
6
5
4
3
2
1
0
Enable Out
1A
(Port C)
Only Bit 1 and
2 are used
11
13
15
17
1B
20
21
22
23
C0
Data In (Port D)
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
Data Out (Port
D)
Only Bit 1 and
00
2 are used
Direction (Port
D)
Only Bit 1 and
00
2 are used
Only Bit 1 and
00
Drive (Port D)
2 are used
Enable Out
(Port D)
Only Bit 1 and
2 are used
Output
Macrocells AB
Output
Macrocells BC
Mask Macrocells
AB
Mask Macrocells
BC
Primary Flash
Protection
Sec3_ Sec2_ Sec1_ Sec0_
Prot
Bit = 1 sector
is protected
Prot
Prot
Prot
Security Bit =
1 device is
secured
SecondaryFlash Surity
Sec1_ Sec0_
C2
B0
*
*
*
*
*
*
Protection
PMMR0
_Bit
Prot
Prot
*
PLD
Mcells array-
clk
PLD
Control PLD
power
consumption
PLD
Turbo
APD
enable
*
*
00
00
clk
PLD
PLD PLD PLD
Blocking
inputs to PLD
array
B4
E0
PMMR2
Page
*
array array array array
*
*
Ale
*
Cntl2 Cntl1 Cntl0
00 Page Register
Configure
8032 Program
and Data
Periph-
mode
FL_ Boot_ FL_ Boot_ SR_
data data code code code
E2
VM
*
Space
1. (Register address = CSIOP address + address offset; where CSIOP address is defined by user in PSDsoft)
* indicates bit is not used and must be set to ‘0’.
41/181
Interrupt system
UPSD3212A, UPSD3212C, UPSD3212CV
5
Interrupt system
There are interrupt requests from 10 sources as follows.
●
●
●
●
●
●
●
●
●
INT0 external interrupt
2nd USART interrupt
Timer 0 interrupt
2
I C interrupt
INT1 external interrupt (or ADC interrupt)
Timer 1 interrupt
USB interrupt
USART interrupt
Timer 2 interrupt
5.1
External Int0 interrupt
●
The INT0 can be either level-active or transition-active depending on Bit IT0 in register
TCON. The flag that actually generates this interrupt is Bit IE0 in TCON.
●
When an external interrupt is generated, the corresponding request flag is cleared by
the hardware when the service routine is veored to only if the interrupt was transition
activated.
●
If the interrupt was level activated en the interrupt request flag remains set until the
requested interrupt is actually generated. Then it has to deactivate the request before
the interrupt service routine is completed, or else another interrupt will be generated.
5.2
5.3
Timer 0 and 1 interrupts
●
Timer 0 nd Timer 1 Interrupts are generated by TF0 and TF1 which are set by an
ovrflow of their respective Timer/Counter registers (except for Timer 0 in Mode 3).
●
These flags are cleared by the internal hardware when the interrupt is serviced.
Timer 2 interrupt
●
Timer 2 Interrupt is generated by TF2 which is set by an overflow of Timer 2. This flag
has to be cleared by the software - not by hardware.
●
It is also generated by the T2EX signal (Timer 2 External Interrupt P1.1) which is
controlled by EXEN2 and EXF2 Bits in the T2CON register.
5.4
I2C interrupt
2
●
The interrupt of the I C is generated by Bit INTR in the register S2STA.
This flag is cleared by hardware.
●
42/181
UPSD3212A, UPSD3212C, UPSD3212CV
Interrupt system
5.5
External Int1 interrupt
●
The INT1 can be either level active or transition active depending on Bit IT1 in register
TCON. The flag that actually generates this interrupt is Bit IE1 in TCON.
●
When an external interrupt is generated, the corresponding request flag is cleared by
the hardware when the service routine is vectored to only if the interrupt was transition
activated.
●
●
If the interrupt was level activated then the interrupt request flag remains set until the
requested interrupt is actually generated. Then it has to deactivate the request before
the interrupt service routine is completed, or else another interrupt will be generated.
The ADC can take over the External INT1 to generate an interrupt on conversion being
completed
5.6
5.7
USB interrupt
●
●
●
The USB interrupt is generated when endpoint0 has transmitted a acket or received a
packet, when Endpoint1 or Endpoint2 has transmitted a packewhen the suspend or
resume state is detected and every EOP received.
When the USB interrupt is generated, the corresponding request flag must be cleared
by software. The interrupt service routine will have to check the various USB registers
to determine the source and clear the corresponding flag.
Please see the dedicated interrupt control registers for the USB peripheral for more
information.
USART interrupt
●
The USART Interrupt is generated by RI (receive interrupt) OR TI (transmit interrupt).
●
When the USART Interrupt is generated, the corresponding request flag must be
cleared by software. The interrupt service routine will have to check the various USART
resters to determine the source and clear the corresponding flag.
●
Both USART’s are identical, except for the additional interrupt controls in the Bit 4 of the
additional interrupt control registers (A7h, B7h)
43/181
Interrupt system
UPSD3212A, UPSD3212C, UPSD3212CV
Figure 15. Interrupt system
IP / IPA Priority
Interrupt
Sources
IE /
High
Low
INT0
USART
Timer
0
I2C
INT1
Timer
1
USB
2nd
USART
Timer
2
Global
Enable
AI07427b
Table 18. SFR register description
Bit Register Name
Rese
t
Valu
e
SFR
Reg
Add
Comments
Name
7
6
5
4
3
2
1
0
r
Interrupt
Enable
(2nd)
A7
A8
B7
B8
IEA
IE
—
EA
—
—
—
—
—
—
ET2
—
ES2
ES
—
ET1
—
—
EX1
—
EI2C
ET0
PI2C
PT0
EUSB
EX0
00
Interrupt
Enable
00
00
00
Interrupt
Priority
(2nd)
IPA
IP
PS2
PS
PUSB
PX0
Interrupt
Priority
—
PT2
PT1
PX1
5.8
Interrupt priority structure
Each interrupt source can be assigned one of two priority levels. Interrupt priority levels are
defined by the interrupt priority special function register IP and IPA.
0 = low priority
1 = high priority
44/181
UPSD3212A, UPSD3212C, UPSD3212CV
Interrupt system
A low priority interrupt may be interrupted by a high priority interrupt level interrupt. A high
priority interrupt routine cannot be interrupted by any other interrupt source. If two interrupts
of different priority occur simultaneously, the high priority level request is serviced. If
requests of the same priority are received simultaneously, an internal polling sequence
determines which request is serviced. Thus, within each priority level, there is a second
priority structure determined by the polling sequence.
5.9
Interrupt enable structure
Each interrupt source can be individually enabled or disabled by setting or clearing a bit in
the interrupt enable special function registers IE and IEA. All interrupt sources can also be
globally disabled by clearing Bit EA in register IE.
Table 19. Priority levels
Source
Priority with Level
Int0
2nd USART
Timer 0
I²C
0 (highest)
1
2
3
Int1
4
Reserved
Timer 1
USB
5
6
7
8
1st USART
Timer 2+EXF2
9 (lowest)
Table 20. scription of the IE bits
Bit
Symbol
Function
Disable all interrupts:
0: no interrupt with be acknowledged
7
EA
1: each interrupt source is individually enabled or disabled by setting or
clearing its enable bit
6
5
4
3
2
1
0
—
Reserved
ET2
ES
Enable Timer 2 Interrupt
Enable USART Interrupt
Enable Timer 1 Interrupt
Enable External Interrupt (Int1)
Enable Timer 0 Interrupt
Enable External Interrupt (Int0)
ET1
EX1
ET0
EX0
45/181
Interrupt system
UPSD3212A, UPSD3212C, UPSD3212CV
Function
Table 21. Description of the IEA bits
Bit
Symbol
7
6
5
4
3
2
1
0
—
—
Not used
Not used
—
Not used
ES2
—
Enable 2nd USART Interrupt
Not used
—
Not used
EI2C
EUSB
Enable I²C Interrupt
Enable USB Interrupt
Table 22. Description of the IP bits
Bit
Symbol
Function
7
6
5
4
3
2
1
0
—
Reserved
Reserved
—
PT2
PS
Timer 2 Interrupt priority level
USART Interrupt priority lev
Timer 1 Interrupt prioy level
External Interrunt1) priority level
Timer 0 Interrupt priority level
External Interrupt (Int0) priority level
PT1
PX1
PT0
PX0
Table 23. Description of the IPA bits
Bit
ymbol
Function
7
6
5
4
3
2
1
0
—
—
Not used
Not used
Not used
—
PS2
—
2nd USART Interrupt priority level
Not used
—
Not used
PI2C
PUSB
I²C Interrupt priority level
USB Interrupt priority level
46/181
UPSD3212A, UPSD3212C, UPSD3212CV
Interrupt system
5.10
How interrupts are handled
The interrupt flags are sampled at S5P2 of every machine cycle. The samples are polled
during following machine cycle. If one of the flags was in a set condition at S5P2 of the
preceding cycle, the polling cycle will find it and the interrupt system will generate an LCALL
to the appropriate service routine, provided this H/W generated LCALL is not blocked by any
of the following conditions:
●
An interrupt of equal priority or higher priority level is already in progress.
●
The current machine cycle is not the final cycle in the execution of the instruction in
progress.
●
The instruction in progress is RETI or any access to the interrupt priority or interrupt
enable registers.
The polling cycle is repeated with each machine cycle, and the values polled are the values
that were present at S5P2 of the previous machine cycle.
Note:
If an interrupt flag is active but being responded to for one of the above mentioned
conditions, if the flag is still inactive when the blocking condition is remed, the denied
interrupt will not be serviced. In other words, the fact that the interruflag was once active
but not serviced is not remembered. Every polling cycle is ne
The processor acknowledges an interrupt request by exeuting a hardware generated
LCALL to the appropriate service routine. The hardwre generated LCALL pushes the
contents of the Program Counter on to the stack (but it does not save the PSW) and reloads
the PC with an address that depends on the source of the interrupt being vectored to as
shown in Table 24.
Execution proceeds from that location until the RETI instruction is encountered. The RETI
instruction informs the processor that the interrupt routine is no longer in progress, then
pops the top two bytes from the stack and reloads the Program Counter. Execution of the
interrupted program continues from where it left off.
Note:
A simple RET instruction would also return execution to the interrupted program, but it would
have left the interrupt control system thinking an interrupt was still in progress, making future
interrups impossible.
Tale 24. Vector addresses
Source
Vector address
Int0
2nd USART
Timer 0
I²C
0003h
004Bh
000Bh
0043h
0013h
001Bh
0033h
0023h
002Bh
Int1
Timer 1
USB
1st USART
Timer 2+EXF2
47/181
Power-saving mode
UPSD3212A, UPSD3212C, UPSD3212CV
6
Power-saving mode
Two software selectable modes of reduced power consumption are implemented.
6.1
Idle mode
In Idle mode, the following functions are switched Off.
●
CPU (Halted)
The following functions remain Active during Idle mode:
●
●
●
●
●
●
●
External Interrupts
Timer 0, Timer 1, Timer 2
PWM Units
USB Interface
USART
8-bit ADC
2
I C Interface
Note:
Interrupt or RESET terminates the Idle mode.
6.2
Power-down mode
●
●
●
●
System Clock Halted
LVD Logic Remains Active
SRAM content remains unchanged
The SFRs retain their value until a RESET is asserted
Note:
The only way o exit Power-down mode is through a RESET.
Table 25. Power-saving mode power consumption
Mode
Addr/data
Ports 1,3,4
PWM
I2C
USB
Idle
Maintain Data
Maintain Data
Maintain Data
Maintain Data
Active
Active
Active
Power-down
Disable
Disable
Disable
6.3
Power control register
The Idle and Power-down modes are activated by software via the PCON register.
Table 26. Pin status during Idle and Power-down mode
Bit Register Name
SFR
Addr
Reg
Name
Reset
Value
Comments
7
6
5
4
3
2
1
0
87
PCON
SMOD
SMOD1 LVREN ADSFINT RCLK1 TCLK1
PD
IDLE
00
Power Ctrl
48/181
UPSD3212A, UPSD3212C, UPSD3212CV
Power-saving mode
Table 27. Description of the PCON bits
Bit Symbol
SMOD
SMOD1 Double baud data rate bit 2nd UART
LVREN LVR disable bit (active High)
Function
7
Double baud data rate bit UART
6
5
4
3
2
1
0
ADSFINT Enable ADC Interrupt
RCLK1(1) Received clock flag (UART 2)
TCLK1(1) Transmit clock flag (UART 2)
PD
Activate Power-down mode (High enable)
Activate Idle mode (High enable)
IDL
1. See the T2CON register for details of the flag description
6.4
Idle mode
The instruction that sets PCON.0 is the last instruction executed in the normal operating
mode before Idle mode is activated. Once in the Idle mode, the CPU status is preserved in
its entirety: Stack pointer, Program counter, Program tatus word, Accumulator, RAM and All
other registers maintain their data during Idle moe.
There are three ways to terminate the Idle ode.
1. Activation of any enabled interrupill cause PCON.0 to be cleared by hardware
terminating Idle mode. The interrupt is serviced, and following return from interrupt
instruction RETI, the next instruction to be executed will be the one which follows the
instruction that wrote a logic '1' to PCON.0.
2. External hardware reset: the hardware reset is required to be active for two machine
cycle to complete the RESET operation.
3. Internal set: the microcontroller restarts after 3 machine cycles in all cases.
6.5
Power-down mode
The instruction that sets PCON.1 is the last executed prior to going into the Power-down
mode. Once in Power-down mode, the oscillator is stopped. The contents of the on-chip
RAM and the Special Function Register are preserved.
The Power-down mode can be terminated by an external RESET.
49/181
I/O ports (MCU module)
UPSD3212A, UPSD3212C, UPSD3212CV
7
I/O ports (MCU module)
The MCU module has five ports: Port 0, Port 1, Port 2, Port 3, and Port 4. (Refer to the PSD
module section on I/O ports A,B,C and D). Ports P0 and P2 are dedicated for the external
address and data bus and is not available in the 52-pin package devices.
Port 1- Port 3 are the same as in the standard 8032 microcontrollers, with the exception of
the additional special peripheral functions. All ports are bi-directional. Pins of which the
alternative function is not used may be used as normal bi-directional I/O.
The use of Port 1-Port 4 pins as alternative functions are carried out automatically by the
UPSD321xx devices provided the associated SFR Bit is set HIGH.
The following SFR registers (Table 29, Table 30, and Table 31) are used to control the
mapping of alternate functions onto the I/O port bits. Port 1 alternate functions are
controlled using the P1SFS register, except for Timer 2 and the 2nd UART which are
enabled by their configuration registers. P1.0 to P1.3 are default to GPIO after reset.
Port 3 pins 6 and 7 have been modified from the standard 8032. The pins that were used
2
for READ and WRITE control signals are now GPIO or I C buins. The READ and WRITE
pins are assigned to dedicated pins.
2
Port 3 (I C) and Port 4 alternate functions are controlled using the P3SFS and P4SFS
Special Function Selection registers. After a reset, the I/O pins default to GPIO. The
alternate function is enabled if the corresponding it in the PXSFS register is set to '1.' Other
Port 3 alternative functions (UART, Interrupand Timer/Counter) are enabled by their
configuration register and do not requetting of the bits in P3SFS.
Table 28. I/O port functions
Port name
Main function
Alternate
Timer 2 - Bits 0,1
2nd UART - Bits 2,3
ADC - Bits 4..7
Port
GPIO
UART - Bits 0,1
Interrupt - Bits 2,3
Timers - Bits 4,5
I2C - Bits 6,7
Port 3
GPIO
Port 4
GPIO
PWM - Bits 3..7
USB +/-
USB +/- Only
Table 29. P1SFS (91h)
7
6
5
4
3
2
1
0
0=Port 1.7 0=Port 1.6 0=Port 1.5 0=Port 1.4
1=ACH3 1=ACH2 1=ACH1 1=ACH0
Bits are reserved
Bits are reserved
50/181
UPSD3212A, UPSD3212C, UPSD3212CV
Table 30. P3SFS (93h)
I/O ports (MCU module)
7
6
5
4
3
2
1
0
0 = Port
3.7
0 = Port
3.6
Bits are reserved
1 = SCL
from I2C
unit
1 = SDA
from I2C
unit
Table 31. P4SFS (94h)
7
6
5
4
3
2
1
0
0=Port 4.1 0=Port 4.0
0=Port 4.7 0=Port 4.6 0=Port 4.5 0=Port 4.4 0=Port 4.3 0=Port 4.2
1=PWM 4 1=PWM 3 1=PWM 2 1=PWM 1 1=PWM 0 1=VSYNC
1=DDC -
SCL
1=DDC -
SDA
7.1
Port type and description
Figure 16. Port type and description (Part 1)
In /
Out
Symbol
RESET
Circuit
Description
I
• Schmitt input with internal pull-up
CMOS compatible interface
NFC : 400ns
NFC
WR, RD,ALE,
PSEN
O
Output only
XTAL1,
XTA2
I
On-chip oscillator
On-chip feedback resistor
Stop in the power down mode
External clock input available
CMOS compatible interface
xon
O
Bidirectional I/O port
Schmitt input
PORT0
I/O
Address Output ( Push-Pull )
CMOS compatible interface
AI06653
51/181
I/O ports (MCU module)
UPSD3212A, UPSD3212C, UPSD3212CV
Figure 17. Port type and description (Part 2)
In/
Out
Function
PORT1 <3:0>,
PORT3,
Bidirectional I/O port with
internal pull-ups
I/O
PORT4<7:3,1:0>
Schmitt input
CMOS compatible interface
PORT2
Bidirectional I/O port with
internal pull-ups
PORT1 < 7:4 >
I/O
Schmitt input
CMOS compatible interface
Analog input option
an_enb
Bidirctional I/O port with internal
pull-ups
I/O
PORT4.2
Schmitt input.
TTL compatible interface
Bidirectional I/O port
Schmitt input
I/O
USB–, USB+
TTL compatible interface
+
–
AI07428b
52/181
UPSD3212A, UPSD3212C, UPSD3212CV
Oscillator
8
Oscillator
The oscillator circuit of the UPSD321xx devices is a single stage inverting amplifier in a
Pierce oscillator configuration. The circuitry between XTAL1 and XTAL2 is basically an
inverter biased to the transfer point. Either a crystal or ceramic resonator can be used as the
feedback element to complete the oscillator circuit. Both are operated in parallel resonance.
XTAL1 is the high gain amplifier input, and XTAL2 is the output. To drive the UPSD321xx
devices externally, XTAL1 is driven from an external source and XTAL2 left open-circuit.
Figure 18. Oscillator
XTAL1
XTAL2
XTAL1
XTAL2
8 to 40 MHz
External Clock
AI06620
53/181
Supervisory
UPSD3212A, UPSD3212C, UPSD3212CV
9
Supervisory
There are four ways to invoke a reset and initialize the UPSD321xx devices.
1.
Via the external RESET pin
Via the internal LVR block
Via USB bus reset signaling
Via Watchdog Timer (WDT)
2.
3.
4.
The RESET mechanism is illustrated in Figure 19.
Each RESET source will cause an internal reset signal active. The CPU responds by
executing an internal reset and puts the internal registers in a defined state. This internal
reset is also routed as an active low reset input to the PSD module.
Figure 19. RESET configuration
Reset
CPU
&
PERI.
Noise
Cancel
CPU
Clock
Sync
WDT
LVR
S
Q
R
RSTE
10m
Time
PSD_RST
Active Low
“
10ms at 40Mhz
50ms at 8Mhz
USB Reset
AI06621
9.1
External reset
The RESET pin is connected to a Schmitt trigger for noise reduction. A RESET is
acomplished by holding the RESET pin LOW for at least 1ms at power up while the
oscillator is running. Refer to AC spec on other RESET timing requirements.
92
Low VDD voltage reset
An internal reset is generated by the LVR circuit when the V drops below the reset
DD
threshold. After V reaching back up to the reset threshold, the RESET signal will remain
DD
asserted for 10ms before it is released. On initial power-up the LVR is enabled (default).
After power-up the LVR can be disabled via the LVREN Bit in the PCON Register.
Note:
The LVR logic is still functional in both the Idle and Power-down modes.
The reset threshold:
●
5 V operation: 4 V 0.25 V
3.3 V operation: 2.5 V 0.2 V
●
This logic supports approximately 0.1 V of hysteresis and 1 µs noise-cancelling delay.
54/181
UPSD3212A, UPSD3212C, UPSD3212CV
Supervisory
9.3
Watchdog timer overflow
The Watchdog timer generates an internal reset when its 22-bit counter overflows. See
Watchdog Timer section for details.
9.4
USB reset
The USB reset is generated by a detection on the USB bus RESET signal. A single-end
zero on its upstream port for 4 to 8 times will set RSTF Bit in UISTA register. If Bit 6 (RSTE)
of the UIEN Register is set, the detection will also generate the RESET signal to reset the
CPU and other peripherals in the MCU.
55/181
Watchdog timer
UPSD3212A, UPSD3212C, UPSD3212CV
10
Watchdog timer
The hardware watchdog timer (WDT) resets the UPSD321xx devices when it overflows. The
WDT is intended as a recovery method in situations where the CPU may be subjected to a
software upset. To prevent a system reset the timer must be reloaded in time by the
application software. If the processor suffers a hardware/software malfunction, the software
will fail to reload the timer. This failure will result in a reset upon overflow thus preventing the
processor running out of control.
In the Idle mode the watchdog timer and reset circuitry remain active. The WDT consists of
a 22-bit counter, the Watchdog Timer RESET (WDRST) SFR and Watchdog Key Register
(WDKEY).
Since the WDT is automatically enabled while the processor is running. the user only needs
to be concerned with servicing it.
The 22-bit counter overflows when it reaches 4194304 (3FFFFFH). The WDT increments
once every machine cycle.
This means the user must reset the WDT at least every 41944 machine cycles (1.258
seconds at 40MHz). To reset the WDT the user must write a value between 00-7EH to the
WDRST register. The value that is written to the WDRST is loaded to the 7MSB of the 22-bit
counter. This allows the user to pre-loaded the countr to an initial value to generate a
flexible Watchdog time out period. Writing a “00” WDRST clears the counter.
The watchdog timer is controlled by the wahdog key register, WDKEY. Only pattern
01010101 (=55H), disables the watchtimer. The rest of pattern combinations will keep
the watchdog timer enabled. This security key will prevent the watchdog timer from being
terminated abnormally when the function of the watchdog timer is needed.
In Idle mode, the oscillator continues to run. To prevent the WDT from resetting the
processor while in Idle, the user should always set up a timer that will periodically exit Idle,
service the WDTand re-enter Idle mode.
Watchdog rest pulse width depends on the clock frequency. The reset period is tf
x 2 .
x 12
OSC
22
15
ThRESET pulse width is tf
x 12 x 2 .
OSC
Table 32. Watchdog timer key register (WDKEY: 0AEh)
7
6
5
4
3
2
1
0
WDKEY7 WDKEY6 WDKEY5 WDKEY4 WDKEY3 WDKEY2 WDKEY1 WDKEY0
Table 33. Description of the WDKEY Bits
Bit
Symbol
Function
WDKEY7
to
WDKEY0
Enable or disable watchdog timer.
01010101 (=55h): disable watchdog timer. Others: enable watchdog timer
7 to 0
56/181
UPSD3212A, UPSD3212C, UPSD3212CV
Figure 20. RESET pulse width
Watchdog timer
Reset pulse width (about 10ms at 40Mhz, about 50ms at 8Mhz)
Reset period
(1.258 second at 40Mhz)
(about 6.291 seconds at 8Mhz)
AI06823
Table 34. Watchdog timer clear register (WDRST: 0A6h)
7
6
5
4
3
2
1
0
Reserved WDRST6 WDRST5 WDRST4 WDRST3 WDRST2 WDRST1 WDRST0
Table 35. Description of the WDRST Bits
Bit
Symbol
Function
7
—
Reserved
To reset watchdog timer, write any value beteen 00h and 7Eh to this
register.
WDRST6
to
WDRST0
6 to 0
This value is loaded to the ost significant bits of the 22-bit counter.
For example: MOV WDRST,#1EH
1. The Watchdog Timer (WDT) is enabled at pr-up or reset and must be served or disabled.
57/181
Timer/counters (Timer 0, Timer 1 and Timer 2)
UPSD3212A, UPSD3212C, UPSD3212CV
11
Timer/counters (Timer 0, Timer 1 and Timer 2)
The UPSD321xx devices has three 16-bit Timer/Counter registers: Timer 0, Timer 1 and
Timer 2. All of them can be configured to operate either as timers or event counters and are
compatible with standard 8032 architecture.
In the “Timer” function, the register is incremented every machine cycle. Thus, one can think
of it as counting machine cycles. Since a machine cycle consists of 6 CPU clock periods,
the count rate is 1/6 of the CPU clock frequency or 1/12 of the oscillator frequency (f
).
OSC
In the “Counter” function, the register is incremented in response to a 1-to-0 transition at its
corresponding external input pin, T0 or T1. In this function, the external input is sampled
during S5P2 of every machine cycle. When the samples show a high in one cycle and a low
in the next cycle, the count is incremented. The new count value appears in the register
during S3P1 of the cycle following the one in which the transition was detected. Since it
takes 2 machine cycles (24 f
clock periods) to recognize a 1-to-0 transition, the
OSC
maximum count rate is 1/24 of the f
. There are no restrictions on thduty cycle of the
OSC
external input signal, but to ensure that a given level is sampled at lst once before it
changes, it should be held for at least one full cycle. In additioto the “Timer” or “Counter”
selection, Timer 0 and Timer 1 have four operating modes from which to select.
11.1
Timer 0 and Timer 1
The “Timer” or “Counter” function is secteby control bits C/ T in the Special Function
Register TMOD. These Timer/Counterave four operating modes, which are selected by
bit-pairs (M1, M0) in TMOD. Modes 0, 1, and 2 are the same for Timers/ Counters. Mode 3
is different. The four operating modes are de-scribed in the following text.
Table 36. Control register (TCON)
7
5
4
3
2
1
0
TF1
TR1
TF0
TR0
IE1
IT1
IE0
IT0
Table 37. Description of the TCON bits
Bit
Symbol
Function
Timer 1 overflow flag. Set by hardware on Timer/Counter overflow. Cleared
by hardware when processor vectors to interrupt routine
7
TF1
Timer 1 run control bit. Set/cleared by software to turn Timer/Counter on or
off
6
5
4
3
2
TR1
TF0
TR0
IE1
Timer 0 overflow flag. Set by hardier on Timer/Counter overflow. Cleared by
hardware when processor vectors to interrupt routine
Timer 0 run control bit. Set/cleared by software to turn Timer/Counter on or
off
Interrupt 1 Edge Flag. Set by hardware when external interrupt edge
detected. Cleared when interrupt processed
Interrupt 1 Type Control Bit. Set/cleared by software to specify falling-
edge/low-level triggered external interrupt
IT1
58/181
UPSD3212A, UPSD3212C, UPSD3212CV
Timer/counters (Timer 0, Timer 1 and Timer 2)
Function
Table 37. Description of the TCON bits
Bit
Symbol
Interrupt 0 Edge Flag. Set by hardware when external interrupt edge
detected. Cleared when interrupt processed
1
IE0
Interrupt 0 Type Control Bit. Set/cleared by software to specify falling-
edge/low-level triggered external interrupt
0
IT0
11.1.1
Mode 0
Putting either Timer into Mode 0 makes it look like an 8048 Timer, which is an 8-bit Counter
with a divide-by-32 prescaler. Figure 21 shows the Mode 0 operation as it applies to Timer
1.
In this mode, the Timer register is configured as a 13-bit register. As the count rolls over
from all '1s' to all '0s,' it sets the Timer Interrupt Flag TF1. The counted input is enabled to
the Timer when TR1 = 1 and either GATE = 0 or /INT1 = 1. (Setting GATE = 1 allows the
Timer to be controlled by external input /INT1, to facilitate pulse width masurements). TR1
is a control bit in the Special Function Register TCON (TCON ControRegister). GATE is in
TMOD.
The 13-bit register consists of all 8 bits of TH1 and the lower 5 bits of TL1. The upper 3 bits
of TL1 are indeterminate and should be ignored. Seting the run flag does not clear the
registers.
Mode 0 operation is the same for the Timer as for Timer 1. Substitute TR0, TF0, and /INT0
for the corresponding Timer 1 signals gure 21 There are two different GATE Bits, one for
Timer 1 and one for Timer0.
Figure 21. Timer/counter mode 0: 13-bit counter
fOSC
÷ 12
C/T = 0
C/T = 1
TH1
(8 bits)
TL1
(5 bits)
TF1
Interrupt
T1 pin
Control
TR1
Gate
INT1 pin
AI06622
11.1.2
Mode 1
Mode 1 is the same as Mode 0, except that the Timer register is being run with all 16 bits.
Table 38. TMOD register (TMOD)
7
6
5
4
3
2
1
0
Gate
C/T
M1
M0
Gate
C/T
M1
M0
59/181
Timer/counters (Timer 0, Timer 1 and Timer 2)
Table 39. Description of the TMOD bits
UPSD3212A, UPSD3212C, UPSD3212CV
Function
Bit
Symbol Timer
Gating control when set. Timer/Counter 1 is enabled only while INT1 pin
is High and TR1 control pin is set. When cleared, Timer 1 is enabled
whenever TR1 control bit is set
7
Gate
Timer or Counter selector, cleared for timer operation (input from internal
system clock); set for counter operation (input from T1 input pin)
6
5
C/T
Timer1
M1
(M1,M0)=(0,0): 13-bit Timer/Counter, TH1, with TL1 as 5-bit prescaler
(M1,M0)=(0,1): 16-bit Timer/Counter. TH1 and TL1 are cascaded. There
is no prescaler.
(M1,M0)=(1,0): 8-bit auto-reload Timer/Counter. TH1 holds a value which
is to be reloaded into TL1 each time it overflows
4
3
M0
(M1,M0)=(1,1): Timer/Counter 1 stopped
Gating control when set. Timer/Counter 0 is enabled only while INT0 pin
is High and TR0 control pin is set. When cleared, Timer 0 is enabled
whenever TR0 control bit is set
Gate
C/T
Timer or Counter selector, cleared for timoperation (input from internal
system clock); set for counter operation (input from T0 input pin)
2
1
M1
(M1,M0)=(0,0): 13-bit Timer/Counter, TH0, with TL0 as 5-bit prescaler
Timer0
(M1,M0)=(0,1): 16-bit Timer/Counter. TH0 and TL0 are cascaded. There
is no prescaler.
(M1,M0)=(1,0): 8-biuto-reload Timer/Counter. TH0 holds a value which
is to be reloadnto TL0 each time it overflows
0
M0
(M1,M0)=(1,1): TL0 is an 8-bit Timer/Counter controlled by the standard
TImer 0 control bits. TH0 is an 8-bit timer only controlled by Timer 1
control bits
11.1.3
Mode 2
Mode 2 configures the Timer register as an 8-bit Counter (TL1) with automatic reload, as
shown n Figure 22. Overflow from TL1 not only sets TF1, but also reloads TL1 with the
contents of TH1, which is preset by software. The reload leaves TH1 unchanged. Mode 2
operation is the same for Timer/Counter 0.
Figure 22. Timer/counter mode 2: 8-bit Auto-reload
fOSC
÷ 12
C/T = 0
C/T = 1
TL1
(8 bits)
TF1
Interrupt
T1 pin
Control
TR1
Gate
INT1 pin
TH1
(8 bits)
AI06623
60/181
UPSD3212A, UPSD3212C, UPSD3212CV
Timer/counters (Timer 0, Timer 1 and Timer 2)
11.1.4
Mode 3
Timer 1 in Mode 3 simply holds its count. The effect is the same as setting TR1 = 0.
Timer 0 in Mode 3 establishes TL0 and TH0 as two separate counters. The logic for Mode 3
on Timer 0 is shown in Figure 23. TL0 uses the Timer 0 control Bits: C/T, GATE, TR0, INT0,
and TF0. TH0 is locked into a timer function (counting machine cycles) and takes over the
use of TR1 and TF1 from Timer 1. Thus, TH0 now controls the “Timer 1“ Interrupt.
Mode 3 is provided for applications requiring an extra 8-bit timer on the counter. With Timer
0 in Mode 3, an UPSD321xx devices can look like it has three Timer/Counters. When Timer
0 is in Mode 3, Timer 1 can be turned on and off by switching it out of and into its own Mode
3, or can still be used by the serial port as a baud rate generator, or in fact, in any application
not requiring an interrupt.
Figure 23. Timer/counter mode 3: two 8-bit counters
fOSC
÷ 12
C/T = 0
C/T = 1
TL0
(8 bits)
TF0
Interrupt
T0 pin
Control
TR0
Gate
INT0 pin
TH1
(8 bits)
fOSC
TF1
Interrupt
AI06624
÷ 12
Control
TR1
11.2
Timer 2
Like Timers 0 and 1, Timer 2 can operate as either an event timer or as an event counter.
This is selected by Bit C/T2 in the special function register T2CON. It has three operating
modes: Capture, Auto-reload, and Baud Rate Generator, which are selected by bits in the
T2CON as shown in Table 41. In the Capture mode there are two options which are selected
by Bit EXEN2 in T2CON. if EXEN2 = 0, then Timer 2 is a 16-bit timer or counter which upon
overflowing sets Bit TF2, the Timer 2 Overflow bit, which can be used to generate an
interrupt. If EXEN2 = 1, then Timer 2 still does the above, but with the added feature that a
1-to-0 transition at external input T2EX causes the current value in the Timer 2 registers,
TL2 and TH2, to be captured into registers RCAP2L and RCAP2H, respectively. In addition,
the transition at T2EX causes Bit EXF2 in T2CON to be set, and EXF2 like TF2 can
generate an interrupt. The Capture mode is illustrated in Figure 24.
In the Auto-reload mode, there are again two options, which are selected by bit EXEN2 in
T2CON. If EXEN2 = 0, then when Timer 2 rolls over it not only sets TF2 but also causes the
Timer 2 registers to be reloaded with the 16-bit value in registers RCAP2L and RCAP2H,
which are preset by software. If EXEN2 = 1, then Timer 2 still does the above, but with the
added feature that a 1-to-0 transition at external input T2EX will also trigger the 16-bit reload
61/181
Timer/counters (Timer 0, Timer 1 and Timer 2)
UPSD3212A, UPSD3212C, UPSD3212CV
and set EXF2. Auto-reload mode is illustrated in the Standard Serial Interface (UART)
Figure 25. The Baud Rate Generation mode is selected by (RCLK, RCLK1)=1 and/or
(TCLK, TCLK1)=1. It is described in conjunction with the serial port.
Table 40. Timer/counter 2 control register (T2CON)
7
6
5
4
3
2
1
0
TF2
EXF2
RCLK
TCLK
EXEN2
TR2
C/T2
CP/RL2
Table 41. Description of the T2CON bits
Bit
Symbol
Function
Timer 2 overflow flag. Set by a Timer 2 overflow, and must be cleared by
software. TF2 will not be set when either (RCLK, RCLK1)=1 or (TCLK,
TCLK)=1
7
TF2
Timer 2 external flag set when either a capture or reload is caused by a
negative transition on T2EX and EXEN2=1. When Timer 2 Interrupt is
enabled, EXF2=1 will cause the CPU to vector to the imer 2 Interrupt
routine. EXF2 must be cleared by software
6
EXF2
Receive clock flag (UART 1). When set, causes the serial port to use Timer
5
4
RCLK(1) 2 overflow pulses for its receive clock n Modes 1 and 3. TCLK=0 causes
Timer 1 overflow to be used for the receive clock
Transmit clock flag (UART 1When set, causes the serial port to use Timer
TCLK(1) 2 overflow pulses for its transmit clock in Modes 1 and 3. TCLK=0 causes
Timer 1 overflow o bsed for the transmit clock
Timer 2 external enable flag. When set, allows a capture or reload to occur
3
2
1
EXEN2
TR2
as a result of a negative transition on T2EX if Timer 2 is not being used to
clock the serial port. EXEN2=0 causes Time 2 to ignore events at T2EX
Start/stop control for Timer 2. A logic 1 starts the timer
Timer or Counter select for Timer 2. Cleared for timer operation (input from
internal system clock, tCPU); set for external event counter operation
(negative edge triggered)
C2
Capture/reload flag. When set, capture will occur on negative transition of
T2EX if EXEN2=1. When cleared, auto-reload will occur either with TImer 2
0
CP/RL2 overflows, or negative transitions of T2EX when EXEN2=1. When either
(RCLK, RCLK1)=1 or (TCLK, TCLK)=1, this bit is ignored, and timer is
forced to auto-reload on Timer 2 overflow
1. The RCLK1 and TCLK1 Bits in the PCON Register control UART 2, and have the same function as RCLK
and TCLK.
62/181
UPSD3212A, UPSD3212C, UPSD3212CV
Timer/counters (Timer 0, Timer 1 and Timer 2)
Table 42. Timer/counter2 operating modes
T2CON
Input clock
T2MOD T2CON P1.1
RxCLK
or
TxCLK
Mode
Remarks
CP/R
L2
External
(P1.0/T2)
DECN
EXEN T2EX
TR2
Internal
0
0
0
0
1
1
0
0
0
1
x
¯
Reload upon overflow
Reload trigger (falling
edge)
16-bit
Auto-
reload
MAX
fOSC/24
fOSC/12
0
0
0
0
1
1
1
1
x
x
0
1
Down counting
Up counting
16-bit Timer/Counter
(only up counting)
0
0
1
1
1
x
1
1
1
x
x
x
0
1
0
x
¯
16-bit
Capture
MAX
fOSC/24
f
OSC/12
Capture (TH1,TL2) →
(RCAP2H,RCAP2L)
No overflow intept
request (TF2)
x
Baud Rate
Generator
MAX
fOSC/24
fOSC/12
Extra External Interrupt
(Time2)
1
x
x
x
1
0
x
x
1
x
¯
Off
x
Tier 2 stops
—
—
1. ↓ = falling edge
Figure 24. Timer 2 in Capture mode
fOSC
÷ 12
C/T2 = 0
C/T2 = 1
TH2
(8 bits)
TL2
(8 bits)
TF2
T2 pin
Control
TR2
Timer 2
Interrupt
Capture
RCAP2H
RCAP2L
Transition
Detector
T2EX pin
EXP2
Control
EXEN2
AI06625
63/181
Timer/counters (Timer 0, Timer 1 and Timer 2)
Figure 25. Timer 2 in Auto-Reload mode
UPSD3212A, UPSD3212C, UPSD3212CV
fOSC
÷ 12
C/T2 = 0
C/T2 = 1
TH2
TF2
TL2
(8 bits)
(8 bits)
T2 pin
Control
TR2
Timer 2
Interrupt
Reload
RCAP2H
RCAP2L
Transition
Detector
T2EX pin
EXP2
Control
EXEN2
AI06626
64/181
UPSD3212A, UPSD3212C, UPSD3212CV
Standard serial interface (UART)
12
Standard serial interface (UART)
The UPSD321xx devices provides two standard 8032 UART serial ports. The first port is
connected to pin P3.0 (RX) and P3.1 (TX). The second port is connected to pin P1.2 (RX)
and P1.3(TX). The operation of the two serial ports are the same and are controlled by the
SCON and SCON2 registers.
The serial port is full duplex, meaning it can transmit and receive simultaneously. It is also
receive-buffered, meaning it can commence reception of a second byte before a previously
received byte has been read from the register. (However, if the first byte still has not been
read by the time reception of the second byte is complete, one of the bytes will be lost.) The
serial port receive and transmit registers are both accessed at Special Function Register
SBUF (or SBUF2 for the second serial port). Writing to SBUF loads the transmit register,
and reading SBUF accesses a physically separate receive register.
The serial port can operate in 4 modes: Mode 0, 1, 2 or 3.
Mode 0
Serial data enters and exits through RxD. TxD outputs the shiclock. 8 bits are
transmitted/received (LSB first). The baud rate is fixed at 1/12 the f
.
OSC
Mode 1
10 bits are transmitted (through TxD) or received (through RxD): a Start bit (0), 8 data bits
(LSB first), and a Stop bit (1). On rece, te Stop bit goes into RB8 in Special Function
Register SCON. The baud rate is variae.
Mode 2
11 bits are transmitted (through TxD) or received (through RxD): Start bit (0), 8 data bits
(LSB first), a programmable 9th data bit, and a Stop bit (1). On Transmit, the 9th data bit
(TB8 in SCON) n be assigned the value of ‘0’ or ‘1’. Or, for example, the Parity bit (P, in the
PSW) could bmoved into TB8. On receive, the 9th data bit goes into RB8 in Special
FunctioRegister SCON, while the Stop bit is ignored. The baud rate is programmable to
either 1/32 or 1/64 the oscillator frequency.
Mode 3
11 bits are transmitted (through TxD) or received (through RxD): a Start bit (0), 8 data bits
(LSB first), a programmable 9th data bit, and a Stop bit (1). In fact, Mode 3 is the same as
Mode 2 in all respects except baud rate. The baud rate in Mode 3 is variable.
In all four modes, transmission is initiated by any instruction that uses SBUF as a destination
register. Reception is initiated in Mode 0 by the condition RI = 0 and REN = 1. Reception is
initiated in the other modes by the incoming start bit if REN = 1.
12.1
Multiprocessor communications
Modes 2 and 3 have a special provision for multiprocessor communications. In these
modes, 9 data bits are received. The 9th one goes into RB8. Then comes a Stop bit. The
port can be programmed such that when the Stop bit is received, the serial port interrupt will
65/181
Standard serial interface (UART)
UPSD3212A, UPSD3212C, UPSD3212CV
be activated only if RB8 = 1. This feature is enabled by setting Bit SM2 in SCON. A way to
use this feature in multi-processor systems is as follows:
When the master processor wants to transmit a block of data to one of several slaves, it first
sends out an address byte which identifies the target slave. An address byte differs from a
data byte in that the 9th bit is '1' in an address byte and 0 in a data byte. With SM2 = 1, no
slave will be interrupted by a data byte. An ad-dress byte, however, will interrupt all slaves,
so that each slave can examine the received byte and see if it is being addressed. The
addressed slave will clear its SM2 bit and prepare to receive the data bytes that will be
coming. The slaves that weren’t being addressed leave their SM2s set and go on about their
business, ignoring the coming data bytes.
SM2 has no effect in Mode 0, and in Mode 1 can be used to check the validity of the Stop
bit. In a Mode 1 reception, if SM2 = 1, the receive interrupt will not be activated unless a
valid Stop bit is received.
12.2
Serial port control register
The serial port control and status register is the Special Function Reister SCON (SCON2
for the second port), shown in Figure 26. This register containnot only the mode selection
bits, but also the 9th data bit for transmit and receive (TB8 and RB8), and the Serial Port
Interrupt bits (TI and RI).
Table 43. Serial port control register (SCON
7
6
5
3
2
1
0
SM0
SM1
SM2
REN
TB8
RB8
TI
RI
Table 44. Description of the SCON bits
Bit
Symbol
Function
7
S0
(SM1,SM0)=(0,0): Shift Register. Baud rate = fOSC/12
(SM1,SM0)=(1,0): 8-bit UART. Baud rate = variable
(SM1,SM0)=(0,1): 8-bit UART. Baud rate = fOSC/64 or fOSC/32
(SM1,SM0)=(1,1): 8-bit UART. Baud rate = variable
6
5
SM1
SM2
Enables the multiprocessor communication features in Mode 2 and 3. In
Mode 2 or 3, if SM2 is set to '1,' RI will not be activated if its received 8th
data bit (RB8) is '0.' In Mode 1, if SM2=1, RI will not be activated if a valid
Stop bit was not received. In Mode 0, SM2 should be '0'
Enables serial reception. Set by software to enable reception. Clear by
software to disable reception
4
3
REN
TB8
The 8th data bit that will be transmitted in Modes 2 and 3. Set or clear by
software as desired
In Modes 2 and 3, this bit contains the 8th data bit that was received. In
Mode 1, if SM2=0, RB8 is the Snap Bit that was received. In Mode 0, RB8
is not used
2
RB8
66/181
UPSD3212A, UPSD3212C, UPSD3212CV
Standard serial interface (UART)
Table 44. Description of the SCON bits (continued)
Bit
Symbol
Function
Transmit Interrupt Flag. Set by hardware at the end of the 8th bit time in
Mode 0, or at the beginning of the Stop bit in the other modes, in any serial
transmission. Must be cleared by software
1
TI
Receive Interrupt Flag. Set by hardware at the end of the 8th bit time in
Mode 0, or halfway through the Stop bit in the other modes, in any serial
reception (except for SM2). Must be cleared by software
0
RI
12.2.1
Baud rates
The baud rate in Mode 0 is fixed:
Mode 0 Baud Rate = f / 12
OSC
The baud rate in Mode 2 depends on the value of Bit SMOD = 0 (which is the value on
reset), the baud rate is 1/64 the oscillator frequency. If SMOD = 1, the baud rate is 1/32 the
oscillator frequency.
SMOD
Mode 2 Baud Rate = (2
/ 64) x f
OSC
In the UPSD321xx devices, the baud rates in Modes 1 and 3 are determined by the Timer 1
overflow rate.
12.2.2
Using Timer 1 to generate baud rates
When Timer 1 is used as the baud raenerator, the baud rates in Modes 1 and 3 are
determined by the Timer 1 overflow rate and the value of SMOD as follows:
SMOD
Modes 1 and 3 Baud Rate = (2
/ 32) x (Timer 1 overflow rate)
The Timer 1 Interrupt should be disabled in this application. The Timer itself can be
configured for either “timer” or “counter” operation, and in any of its 3 running modes. In the
most typical applcations, it is configured for “timer” operation, in the Auto-reload mode (high
nibble of TM= 0010B). In that case the baud rate is given by the formula:
SMOD
Mdes 1 and 3 Baud Rate = (2
/ 32) x (f
/ (12 x [256 – (TH1)]))
OSC
One can achieve very low baud rates with Timer 1 by leaving the Timer 1 Interrupt enabled,
and configuring the Timer to run as a 16-bit timer (high nibble of TMOD = 0001B), and using
the Timer 1 Interrupt to do a 16-bit software reload. Figure 21 lists various commonly used
baud rates and how they can be obtained from Timer 1.
12.2.3
Using Timer/counter 2 to generate baud rates
In the UPSD321xx devices, Timer 2 selected as the baud rate generator by setting TCLK
and/or RCLK (see Figure 21 Timer/ Counter 2 Control Register (T2CON)).
Note:
The baud rate for transmit and receive can be simultaneously different. Setting RCLK and/or
TCLK puts Timer into its Baud Rate Generator mode.
The RCLK and TCLK Bits in the T2CON register configure UART 1. The RCLK1 and TCLK1
Bits in the PCON register configure UART 2.
The Baud Rate Generator mode is similar to the Auto-reload Mmode, in that a roll over in
TH2 causes the Timer 2 registers to be reloaded with the 16-bit value in registers RCAP2H
and RCAP2L, which are preset by software.
67/181
Standard serial interface (UART)
UPSD3212A, UPSD3212C, UPSD3212CV
Now, the baud rates in Modes 1 and 3 are determined at Timer 2’s overflow rate as follows:
Modes 1 and 3 Baud Rate = Timer 2 Overflow Rate / 16
Table 45. Timer 1-generated commonly used baud rates
Timer 1
Baud Rate
fOSC
SMOD
C/T
Mode
Reload Value
Mode 0 Max: 1MHz
12MHz
12MHz
X
1
1
1
0
0
0
0
0
0
0
X
X
0
0
0
0
0
0
0
0
0
X
X
2
2
2
2
2
2
2
2
1
X
X
Mode 2 Max: 375K
Modes 1, 3: 62.5K
12MHz
FFh
FDh
FDh
FAh
F4h
E8h
1Dh
72h
FEEBh
19.2K
9.6K
4.8K
2.4K
1.2K
137.5
110
11.059MHz
11.059MHz
11.059MHz
11.059MHz
11.059MHz
11.059MHz
6MHz
110
12MHz
The timer can be configured for either “timor “counter” operation. In the most typical
applications, it is configured for “timereration (C/T2 = 0). “Timer” operation is a little
different for Timer 2 when it’s being used as a baud rate generator. Normally, as a timer it
would increment every machine cycle (thus at the 1/6 the CPU clock frequency). In the
case, the baud rate is given by the formula:
Modes 1 and 3 Baud Baud Rate = f
/ (32 x [65536 – (RCAP2H, RCAP2L)]
OSC
where (RCAP2HRCAP2L) is the content of RC2H and RC2L taken as a 16-bit unsigned
integer.
Timer 2 also be used as the Baud Rate Generating mode. This mode is valid only if RCLK +
TCLK = 1 in T2CON or in PCON.
Note:
Ne:
A roll-over in TH2 does not set TF2, and will not generate an interrupt. Therefore, the Timer
Interrupt does not have to be disabled when Timer 2 is in the Baud Rate Generator mode.
If EXEN2 is set, a 1-to-0 transition in T2EX will set EXF2 but will not cause a reload from
(RCAP2H, RCAP2L) to (TH2, TL2). Thus when Timer 2 is in use as a baud rate generator,
T2EX can be used as an extra external interrupt, if desired.
It should be noted that when Timer 2 is running (TR2 = 1) in “timer” function in the Baud
Rate Generator mode, one should not try to READ or WRITE TH2 or TL2. Under these
conditions the timer is being incremented every state time, and the results of a READ or
WRITE may not be accurate. The RC registers may be read, but should not be written to,
because a WRITE might overlap a reload and cause WRITE and/or reload errors. Turn the
timer off (clear TR2) before accessing the Timer 2 or RC registers, in this case.
12.2.4
More about Mode 0
Serial data enters and exits through RxD. TxD outputs the shift clock. 8 bits are
transmitted/received: 8 data bits (LSB first). The baud rate is fixed at 1/12 the f
.
OSC
68/181
UPSD3212A, UPSD3212C, UPSD3212CV
Standard serial interface (UART)
Figure 26 shows a simplified functional diagram of the serial port in Mode 0, and associated
timing.
Transmission is initiated by any instruction that uses SBUF as a destination register. The
“WRITE to SBUF” signal at S6P2 also loads a '1' into the 9th position of the transmit shift
register and tells the TX Control block to commence a transmission. The internal timing is
such that one full machine cycle will elapse between “WRITE to SBUF” and activation of
SEND.
SEND enables the output of the shift register to the alternate out-put function line of RxD
and also enable SHIFT CLOCK to the alternate output function line of TxD. SHIFT CLOCK
is low during S3, S4, and S5 of every machine cycle, and high during S6, S1, and S2. At
S6P2 of every machine cycle in which SEND is active, the contents of the transmit shift are
shifted to the right one position.
As data bits shift out to the right, zeros come in from the left. When the MSB of the data byte
is at the output position of the shift register, then the '1' that was initially loaded into the 9th
position, is just to the left of the MSB, and all positions to the left of that contain zeros. This
condition flags the TX Control block to do one last shift and then deactiate SEND and set
T1. Both of these actions occur at S1P1. Both of these actions occut S1P1 of the 10th
machine cycle after “WRITE to SBUF.”
Reception is initiated by the condition REN = 1 and R1 = . At S6P2 of the next machine
cycle, the RX Control unit writes the bits 11111110 to the receive shift register, and in the
next clock phase activates RECEIVE.
RECEIVE enables SHIFT CLOCK to the alternate output function line of TxD. SHIFT
CLOCK makes transitions at S3P1 an6P1 of every machine cycle in which RECEIVE is
active, the contents of the receive shift register are shifted to the left one position. The value
that comes in from the right is the value that was sampled at the RxD pin at S5P2 of the
same machine cycle.
As data bits come in from the right, '1s' shift out to the left. When the '0' that was initially
loaded into the right-most position arrives at the left-most position in the shift register, it flags
the RX Control bck to do one last shift and load SBUF. At S1P1 of the 10th machine cycle
after the WRITE to SCON that cleared RI, RECEIVE is cleared as RI is set.
12.2.5
More about Mode 1
Ten bits are transmitted (through TxD), or received (through RxD): a start Bit (0), 8 data bits
(LSB first). and a Stop bit (1). On receive, the Stop bit goes into RB8 in SCON. In the
UPSD321xx devices the baud rate is determined by the Timer 1 or Timer 2 overflow rate.
Figure 28 shows a simplified functional diagram of the serial port in Mode 1, and associated
timings for transmit receive.
Transmission is initiated by any instruction that uses SBUF as a destination register. The
“WRITE to SBUF” signal also loads a '1' into the 9th bit position of the transmit shift register
and flags the TX Control unit that a transmission is requested. Transmission actually
commences at S1P1 of the machine cycle following the next rollover in the divide-by-16
counter. (Thus, the bit times are synchronized to the divide-by-16 counter, not to the
“WRITE to SBUF” signal.)
The transmission begins with activation of SEND which puts the start bit at TxD. One bit
time later, DATA is activated, which enables the output bit of the transmit shift register to
TxD. The first shift pulse occurs one bit time after that.
69/181
Standard serial interface (UART)
UPSD3212A, UPSD3212C, UPSD3212CV
As data bits shift out to the right, zeros are clocked in from the left. When the MSB of the
data byte is at the output position of the shift register, then the '1' that was initially loaded
into the 9th position is just to the left of the MSB, and all positions to the left of that contain
zeros. This condition flags the TX Control unit to do one last shift and then deactivate SEND
and set TI. This occurs at the 10th divide-by-16 rollover after “WRITE to SBUF.”
Reception is initiated by a detected 1-to-0 transition at RxD. For this purpose RxD is
sampled at a rate of 16 times whatever baud rate has been established. When a transition is
detected, the divide-by-16 counter is immediately reset, and 1FFH is written into the input
shift register. Resetting the divide-by-16 counter aligns its roll-overs with the boundaries of
the incoming bit times.
The 16 states of the counter divide each bit time into 16ths. At the 7th, 8th, and 9th counter
states of each bit time, the bit detector samples the value of RxD. The value accepted is the
value that was seen in at least 2 of the 3 samples. This is done for noise rejection. If the
value accepted during the first bit time is not '0,' the receive circuits are reset and the unit
goes back to looking for an-other 1-to-0 transition. This is to provide rejection of false start
bits. If the start bit proves valid, it is shifted into the input shift register, and reception of the
reset of the rest of the frame will proceed.
As data bits come in from the right, '1s' shift out to the left. Wn the start bit arrives at the
left-most position in the shift register (which in Mode 1 is a 9-bit register), it flags the RX
Control block to do one last shift, load SBUF and RB8, and set RI. The signal to load SBUF
and RB8, and to set RI, will be generated if, and only if, the following conditions are met at
the time the final shift pulse is generated:
1. R1 = 0, and
2. Either SM2 = 0, or the received Sbit = 1.
If either of these two conditions is not met, the received frame is irretrievably lost. If both
conditions are met, the Stop bit goes into RB8, the 8 data bits go into SBUF, and RI is
activated. At this time, whether the above conditions are met or not, the unit goes back to
looking for a 1-to-0 transition in RxD.
12.2.6
More abouModes 2 and 3
Eleven bits are transmitted (through TxD), or received (through RxD): a Start bit (0), 8 data
bits (LSB first), a programmable 9th data bit, and a Stop bit (1). On transmit, the 9th data bit
(TB8) can be assigned the value of '0' or '1.' On receive, the data bit goes into RB8 in
SCON. The baud rate is programmable to either 1/16 or 1/32 the CPU clock frequency in
Mode 2. Mode 3 may have a variable baud rate generated from Timer 1.
Figure 30 and Figure 32 show a functional diagram of the serial port in Modes 2 and 3. The
receive portion is exactly the same as in Mode 1. The transmit portion differs from Mode 1
only in the 9th bit of the transmit shift register.
Transmission is initiated by any instruction that uses SBUF as a destination register. The
“WRITE to SBUF” signal also loads TB8 into the 9th bit position of the transmit shift register
and flags the TX Control unit that a transmission is requested. Transmission commences at
S1P1 of the machine cycle following the next roll-over in the divide-by-16 counter. (Thus, the
bit times are synchronized to the divide-by-16 counter, not to the “WRITE to SBUF” signal.)
The transmission begins with activation of SEND, which puts the start bit at TxD. One bit
time later, DATA is activated, which enables the output bit of the transmit shift register to
TxD. The first shift pulse occurs one bit time after that. The first shift clocks a '1' (the Stop
bit) into the 9th bit position of the shift register. There-after, only zeros are clocked in. Thus,
70/181
UPSD3212A, UPSD3212C, UPSD3212CV
Standard serial interface (UART)
as data bits shift out to the right, zeros are clocked in from the left. When TB8 is at the out-
put position of the shift register, then the Stop bit is just to the left of TB8, and all positions to
the left of that contain zeros. This condition flags the TX Control unit to do one last shift and
then deactivate SEND and set TI. This occurs at the 11th divide-by 16 rollover after “WRITE
to SUBF.”
Reception is initiated by a detected 1-to-0 transition at RxD. For this purpose RxD is
sampled at a rate of 16 times whatever baud rate has been established. When a transition is
detected, the divide-by-16 counter is immediately reset, and 1FFH is written to the input shift
register.
At the 7th, 8th, and 9th counter states of each bit time, the bit detector samples the value of
R-D. The value accepted is the value that was seen in at least 2 of the 3 samples. If the
value accepted during the first bit time is not '0,' the receive circuits are reset and the unit
goes back to looking for another 1-to-0 transition. If the Start bit proves valid, it is shifted into
the input shift register, and reception of the rest of the frame will proceed.
As data bits come in from the right, '1s' shift out to the left. When the Start bit arrives at the
left-most position in the shift register (which in Modes 2 and 3 is a 9-bit egister), it flags the
RX Control block to do one last shift, load SBUF and RB8, and set
The signal to load SBUF and RB8, and to set RI, will be generated if, and only if, the
following conditions are met at the time the final shift pulsis generated:
1. RI = 0, and
2. Either SM2 = 0, or the received 9th data bit 1
If either of these conditions is not met, the ceived frame is irretrievably lost, and RI is not
set. If both conditions are met, the reced 9th data bit goes into RB8, and the first 8 data
bits go into SBUF. One bit time later, whether the above conditions were met or not, the unit
goes back to looking for a 1-to-0 transition at the RxD input.
71/181
Standard serial interface (UART)
Figure 26. Serial port Mode 0 block diagram
UPSD3212A, UPSD3212C, UPSD3212CV
Internal Bus
Write
to
SBUF
RxD
D
CL
S
P3.0 Alt
Output
Function
Q
SBUF
Zero Detector
Shift
Start
Tx Control
T
Send
S6
Tx Clock
Serial
Port
Interrupt
Shift
Clock
TxD
Receive
Shift
6 5 4 3 2 1 0
R
P3.1 Alt
Output
Function
Rx Clock
Start
REN
R1
Rx Control
7
RxD
P3.0 Alt
Input
Func
Input Shift Register
SBUF
Load
SBUF
Shift
Read
SBUF
Internal Bus
AI06824
Figure 27. Serial port Mode 0 waveforms
Write to SBUF
S6P2
Send
Shift
Transmit
Receive
D0
S3P1
D1
S6P1
D2
D3
D4
D5
D6
D7
RxD (Data Out)
TxD (Shift C)
T
Write to SCON
Clear RI
RI
Receive
Shift
D0
D1
D2
D3
D4
D5
D6
D7
RxD (Data In)
TxD (Shift Clock)
AI06825
72/181
UPSD3212A, UPSD3212C, UPSD3212CV
Figure 28. Serial port Mode 1 block diagram
Standard serial interface (UART)
Timer1
Overflow
Timer2
Overflow
Internal Bus
TB8
Write
to
SBUF
D
S
TxD
Q
SBUF
÷2
CL
0
1
Zero Detector
SMOD
0
0
1
Shift
Data
Start
TCLK
Tx Control
TI
Send
÷16
Tx Clock
Serial
1
Port
Interrupt
RCLK
÷16
Sample
Load SBUF
Shift
RI
Rx Clock
Start
1-to-0
Transition
Detector
Rx Control
1FFh
Rx Detector
Input Shift Register
Load
SBUF
RxD
Shift
SBUF
Read
SBUF
Internal Bus
AI06826
Figure 29. Serial port Mode 1 waveforms
Tx Clock
Write to SBU
S1P1
d
Transmit
Data
Shift
Start Bit
D0
D1
D1
D2
D2
D3
D4
D4
D5
D6
D6
D7
D7
TxD
T1
Stop Bit
Stop Bit
÷16 Reset
Rx Clock
RxD
Start Bit
D0
D3
D5
Receive
AI06843
Bit Detector
Sample Times
Shift
RI
73/181
Standard serial interface (UART)
Figure 30. Serial port Mode 2 block diagram
UPSD3212A, UPSD3212C, UPSD3212CV
Phase2 Clock
1/2*f
OSC
Internal Bus
TB8
Write
to
SBUF
D
S
TxD
Q
SBUF
÷2
CL
0
1
Zero Detector
SMOD
Shift
Data
Start
Tx Control
TI
Send
÷16
Tx Clock
Serial
Port
Interrupt
÷16
Sample
Load SBUF
Shift
RI
Rx Clock
Start
1-to-0
Transition
Detector
Rx Control
1FFh
Rx Detector
Input Shift Register
SBUF
Load
SBUF
RxD
Shift
Read
SBUF
Internal Bus
AI06844
Figure 31. Serial port Mode 2 waveforms
Tx Clock
Write to SBU
S1P1
nd
Data
Transmit
Shift
Start Bit
D0
D1
D2
D3
D4
D5
D6
D7
TB8
TxD
TI
Stop Bit
Stop Bit
Generator
÷16 Reset
Rx Clock
Start Bit
D0
D1
D2
D3
D4
D5
D6
D7
RB8
RxD
Stop Bit
Receive
AI06845
Bit Detector
Sample Times
Shift
RI
74/181
UPSD3212A, UPSD3212C, UPSD3212CV
Figure 32. Serial port Mode 3 block diagram
Standard serial interface (UART)
Timer1
Overflow
Timer2
Overflow
Internal Bus
TB8
Write
to
SBUF
D
S
TxD
Q
SBUF
÷2
CL
0
1
Zero Detector
SMOD
0
0
1
Shift
Data
Start
TCLK
Tx Control
TI
Send
÷16
Tx Clock
Serial
1
Port
Interrupt
RCLK
÷16
Sample
Load SBUF
Shift
RI
Rx Clock
Start
1-to-0
Transition
Detector
Rx Control
1FFh
Rx Detector
Input Shift Register
Load
SBUF
RxD
Shift
SBUF
Read
SBUF
Internal Bus
AI06846
Figure 33. Serial port Mode 3 waveforms
Tx Clock
Write to SBU
S1P1
nd
Data
Transmit
Shift
Start Bit
D0
D1
D2
D3
D4
D5
D6
D7
TB8
TxD
TI
Stop Bit
Stop Bit
Generator
÷16 Reset
Rx Clock
Start Bit
D0
D1
D2
D3
D4
D5
D6
D7
RB8
RxD
Stop Bit
Receive
AI06847
Bit Detector
Sample Times
Shift
RI
75/181
Analog-to-digital convertor (ADC)
UPSD3212A, UPSD3212C, UPSD3212CV
13
Analog-to-digital convertor (ADC)
The analog to digital (A/D) converter allows conversion of an analog input to a
corresponding 8-bit digital value. The A/D module has four analog inputs, which are
multiplexed into one sample and hold. The output of the sample and hold is the input into the
converter, which generates the result via successive approximation. The analog supply
voltage is connected to AV
of ladder resistance of A/D module.
REF
The A/D module has two registers which are the control register ACON and A/D result
register ADAT. The register ACON, shown in Table 47, controls the operation of the A/D
converter module. To use analog inputs, I/O is selected by P1SFS register. Also an 8-bit
prescaler ASCL divides the main system clock input down to approximately 6MHz clock that
is required for the ADC logic. Appropriate values need to be loaded into the prescaler based
upon the main MCU clock frequency prior to use.
The processing of conversion starts when the Start bit ADST is set to '1.' After one cycle, it
is cleared by hardware. The register ADAT contains the results of the A/conversion. When
conversion is completed, the result is loaded into the ADAT the A/D onversion Status bit
ADSF is set to '1.'
The block diagram of the A/D module is shown in Figure Figure 34. The A/D Status bit
ADSF is set automatically when A/D conversion is completed, cleared when A/D conversion
is in process.
The ASCL should be loaded with a value that results in a clock rate of approximately 6MHz
for the ADC using the following formul
ADC clock input = (f
/ 2) / (Prescaler register value +1)
OSC
Where f
is the MCU clock input frequency.
OSC
The conversion time for the ADC can be calculated as follows:
ADC Conversion Time = 8 clock * 8bits * (ADC Clock) ~= 10.67usec (at 6MHz)
13.1
ADC nterrupt
The ADSF Bit in the ACON register is set to '1' when the A/D conversion is complete. The
status bit can be driven by the MCU, or it can be configured to generate a falling edge
interrupt when the conversion is complete.
The ADSF Interrupt is enabled by setting the ADSFINT Bit in the PCON register. Once the
bit is set, the external INT1 Interrupt is disabled and the ADSF Interrupt takes over as INT1.
INT1 must be configured as if it is an edge interrupt input. The INP1 pin (p3.3) is available
for general I/O functions, or Timer1 gate control.
76/181
UPSD3212A, UPSD3212C, UPSD3212CV
Figure 34. ADC block diagram
Analog-to-digital convertor (ADC)
Ladder
Resistor
Decode
AVREF
Conversion
Complete
Interrupt
Input
ACH0
MUX
Successive
Approximation
Circuit
ACH1
S/H
ACH2
ACH3
ACON
ADAT
INTERNAL BUS
AI06627
Table 46. ADC SFR memory map
Bit register name
SFR
addr name
Reg
Reset
Comments
value
7
6
5
4
3
2
1
0
8-bit
00 Prescalerfor
ADC clock
95
ASCL
ADC Data
00
96
97
ADAT
ADAT7
ADAT6 ADAT5 ADAT4 ADAT3 ADAT2 ADAT1 ADAT0
ADEN ADS1 ADS0 ADST ADSF
Register
ADCControl
00
ACON
Register
Table 47. Description of the ACON bits
Bit
Symbol
Function
7 to 6
—
Reserved
0 : ADC shut off and consumes no operating current
1 : enable ADC
5
4
ADEN
—
ADC Enable Bit:
Reserved
ADS1,
ADS0
Analog channel select
0, 0
0, 1
1, 0
1, 1
Channel0 (ACH0)
3 to 2
Channel1 (ACH1)
Channel2 (ACH2)
Channel3 (ACH3)
0 : force to zero
1
ADST
ADC Start bit:
1 : start an ADC; after one cycle, bit is cleared to '0'
77/181
Analog-to-digital convertor (ADC)
UPSD3212A, UPSD3212C, UPSD3212CV
Table 47. Description of the ACON bits (continued)
Bit
Symbol
Function
0 : A/D conversion is in process
0
ADSF
ADC Status bit:
1 : A/D conversion is completed, not in process
Table 48. ADC clock input
MCU clock frequency
Prescaler register value
ADC clock
40MHz
36MHz
24MHz
12MHz
2
2
1
0
6.7MHz
6MHz
6MHz
6MHz
78/181
UPSD3212A, UPSD3212C, UPSD3212CV
Pulse width modulation (PWM)
14
Pulse width modulation (PWM)
The PWM block has the following features:
●
●
●
Four-channel, 8-bit PWM unit with 16-bit prescaler
One-channel, 8-bit unit with programmable frequency and pulse width
PWM Output with programmable polarity
14.1
4-channel PWM unit (PWM 0-3)
The 8-bit counter of a PWM counts module 256 (i.e., from 0 to 255, inclusive). The value
held in the 8-bit counter is compared to the contents of the Special Function Register (PWM
0-3) of the corresponding PWM. The polarity of the PWM outputs is programmable and
selected by the PWML Bit in PWMCON register. Provided the contents of a PWM 0-3
register is greater than the counter value, the corresponding PWM output is set HIGH (with
PWML = 0). When the contents of this register is less than or equal to thcounter value, the
corresponding PWM output is set LOW (with PWML = 0). The pulse-width-ratio is therefore
defined by the contents of the corresponding Special Function Register (PWM 0-3) of a
PWM. By loading the corresponding Special Function Reister (PWM 0-3) with either 00H
or FFH, the PWM output can be retained at a constant HIGH or LOW level respectively (with
PWML = 0).
For each PWM unit, there is a 16-bit Prescaler that are used to divide the main system clock
to form the input clock for the corresping PWM unit. This prescaler is used to define the
desired repetition rate for the PWM unit. SFR registers B1h - B2h are used to hold the 16-bit
divisor values.
The repetition frequency of the PWM output is given by:
fPWM = (f
/ prescaler0) / (2 x 256)
OSC
8
And the input clk frequency to the PWM counters is = f
/ 2 / (prescaler data value + 1)
OSC
See Seion 7: I/O ports (MCU module) for more information on how to configure the Port 4
pin as PWM output.
79/181
Pulse width modulation (PWM)
UPSD3212A, UPSD3212C, UPSD3212CV
Figure 35. Four-channel 8-bit PWM block diagram
DATA BUS
8
x 4
8-bit PWM0-PWM3
Data Registers
CPU rd/wr
x 4
load
8-bit PWM0-PWM3
Comparators Registers
x 4
Port4.3
Port4.4
Port4.5
Port4.6
16-bit Prescaler
Register
8-bit PWM0-PWM3
Comparators
4
CPU rd/wr
(B2h,B1h)
PWMCON bit7 (PWML)
8
8-bit Count
Overflow
16-bit Prescaler
Counter
f
OSC/2
clock
load
PWMCON bit5 (PWME)
AI06647
Table 49. PWM SFR memory map
Bit register name
SFR
Reset
value
Reg name
addr
Comments
7
6
5
4
3
2
1
0
PWM Control
Polarity
A1 PWMCON PWML PWMP PWME CFG4 CFG3 CFG2 CFG1 CFG0
00
00
00
00
00
PWM0 Output
Duty Cycle
A2
3
A4
PWM0
PWM1
PWM2
PWM1 Output
Duty Cycle
PWM2 Output
Duty Cycle
PWM3 Output
Duty Cycle
A5
AA
AB
PWM3
PWM4P
PWM4W
00 PWM 4 Period
PWM 4 Pulse
00
Width
Prescaler 0
00
B1
PSCL0L
Low (8-bit)
80/181
UPSD3212A, UPSD3212C, UPSD3212CV
Pulse width modulation (PWM)
Table 49. PWM SFR memory map (continued)
Bit register name
SFR
addr
Reset
Reg name
Comments
value
7
6
5
4
3
2
1
0
Prescaler 0
High (8-bit)
B2
B3
B4
PSCL0H
PSCL1L
PSCL1H
00
00
00
Prescaler 1
Low (8-bit)
Prescaler 1
High (8-bit)
PWMCON register bit definition:
●
●
●
●
●
PWML = PWM 0-3 polarity control
PWMP = PWM 4 polarity control
PWME = PWM enable (0 = disabled, 1= enabled)
CFG3..CFG0 = PWM 0-3 Output (0 = Open Drain; 1 = Push-Pu)
CFG4 = PWM 4 Output (0 = Open Drain; 1 = Push-Pull)
14.2
Programmable period 8-bit PWM
The PWM 4 channel can be programmed to provide a PWM output with variable pulse width
and period. The PWM 4 has a 16-bit Pscler, an 8-bit Counter, a Pulse Width Register,
and a Period Register. The Pulse Width Register defines the PWM pulse width time, while
the Period Register defines the period of the PWM. The input clock to the Prescaler is
f
/2. The PWM 4 channel is assigned to Port 4.7.
OSC
Figure 36. Programmable 4-channel PWM block diagram
DATA BUS
8
8
8
8-bit PWM4P
Register
8-bit PWM4W
Register
CPU RD/WR
(Period)
(Width)
8
8
8
8-bit PWM4
Comparator
Register
8-bit PWM4
Comparator
Register
Load
16-bit Prescaler
Register
CPU RD/WR
Port 4.7
(B4h, B3h)
PWM4
Control
8
8
16
PWMCON
Bit 6 (PWMP)
8-bit PWM4
Comparator
8-bit PWM4
Comparator
f
/ 2
OSC
Match
16-bit Prescaler
Counter
8
8
Load
PWMCON
Bit 5 (PWME)
8-bit Counter
Clock
Reset
AI07091
81/181
Pulse width modulation (PWM)
UPSD3212A, UPSD3212C, UPSD3212CV
14.3
PWM 4-channel operation
The 16-bit Prescaler1 divides the input clock (f
/2) to the desired frequency, the resulting
OSC
clock runs the 8-bit Counter of the PWM 4 channel. The input clock frequency to the PWM 4
Counter is:
f PWM4 = (f
/2)/(Prescaler1 data value +1)
OSC
When the Prescaler1 Register (B4h, B3h) is set to data value '0,' the maximum input clock
frequency to the PWM 4 Counter is f /2 and can be as high as 20MHz.
OSC
The PWM 4 Counter is a free-running, 8-bit counter. The output of the counter is compared
to the Compare Registers, which are loaded with data from the Pulse Width Register
(PWM4W, ABh) and the Period Register (PWM4P, AAh). The Pulse Width Register defines
the pulse duration or the Pulse Width, while the Period Register defines the period of the
PWM. When the PWM 4 channel is enabled, the register values are loaded into the
Comparator Registers and are compared to the Counter output. When the content of the
counter is equal to or greater than the value in the Pulse Width Register, it sets the PWM 4
output to low (with PWMP Bit = 0). When the Period Register equals to he PWM4 Counter,
the Counter is cleared, and the PWM 4 channel output is set to logic 'high' level (beginning
of the next PWM pulse).
The Period Register cannot have a value of “00” and its content should always be greater
than the Pulse Width Register.
The Prescaler1 Register, Pulse Width Register, and Period Register can be modified while
the PWM 4 channel is active. The values of these registers are automatically loaded into the
Prescaler Counter and Comparator Reists when the current PWM 4 period ends.
The PWMCON Register (Bits 5 and 6) controls the enable/disable and polarity of the PWM 4
channel.
Figure 37. PWM 4 with programmable pulse width and frequency
Defined by Period Register
PWM4
Defined by Pulse
Width Register
RESET
Counter
Switch Level
AI07090
82/181
2
UPSD3212A, UPSD3212C, UPSD3212CV
I C interface
2
15
I C interface
2
There are two serial I C ports implemented in the UPSD321xx devices.
2
The serial port supports the twin line I C-bus, consists of a data line (SDAx) and a clock line
(SCLx). Depending on the configuration, the SDA and SCL lines may require pull-up
resistors.
●
SDA1, SCL1: the serial port line for DDC Protocol
2
●
SDA2, SCL2: the serial port line for general I C bus connection
2
In both I C interfaces, these lines also function as I/O port lines as follows.
●
SDA1 / P4.0, SCL1 / P4.1, SDA2 / P3.6, SCL2 / P3.7
The system is unique because data transport, clock generation, address recognition and
bus control arbitration are all controlled by hardware.
2
The I C serial I/O has complete autonomy in byte handling and operates in 4 modes.
●
●
●
●
Master transmitter
Master receiver
Slave transmitter
Slave receiver
These functions are controlled by the SFRs.
●
SxCON: the control of byte handling ad the operation of 4 mode.
●
SxSTA: the contents of its registeay also be used as a vector to various service
routines.
●
●
SxDAT: data shift register.
SxADR: slave address register. Slave address recognition is performed by On-Chip
H/W.
2
Figure 38. ock diagram of the I C bus serial I/O
7
0
0
Slave Address
7
Shift Register
SDAx
SCLx
Arbitration and Sync. Logic
Bus Clock Generator
7
7
0
Control Register
Status Register
0
AI06649
Table 50. Serial control register (SxCON: S1CON, S2CON)
7
6
5
4
3
2
1
0
CR2
ENII
STA
STO
ADDR
AA
CR1
CR0
83/181
2
I C interface
UPSD3212A, UPSD3212C, UPSD3212CV
Function
Table 51. Description of the SxCON bits
Bit
Symbol
This bit along with Bits CR1and CR0 determines the serial clock frequency
when SIO is in the Master mode.
7
CR2
Enable IIC. When ENI1 = 0, the IIC is disabled. SDA and SCL outputs are
in the high impedance state.
6
5
ENII
STA
START flag. When this bit is set, the SIO H/W checks the status of the I2C-
bus and generates a START condition if the bus free. If the bus is busy, the
SIO will generate a repeated START condition when this bit is set.
STOP flag. With this bit set while in Master mode a STOP condition is
generated.
When a STOP condition is detected on the I2C-bus, the I2C hardware
clears the STO flag.
4
3
STO
Note: This bit have to be set before 1 cycle interrupt period of STOP. That
is, if this bit is set, STOP condition in Master mode is generated after 1
cycle interrupt period.
This bit is set when address byte was reced. Must be cleared by
software.
ADDR
Acknowledge enable signal. If this bit is set, an acknowledge (low level to
SDA) is returned during the acknowledge clock pulse on the SCL line
when:
• Own slave address ireceived
2
AA
• A data byte is ived while the device is programmed to be a Master
Receiver
• A data byte is received while the device is a selected Slave Receiver.
When this bit is reset, no acknowledge is returned.
SIO release SDA line as high during the acknowledge clock pulse.
1
0
CR1
CR0
These two bits along with the CR2 Bit determine the serial clock frequency
when SIO is in the Master mode.
Table 52. Selection of the serial clock frequency SCL in Master mode
Bit rate (kHz) at fOSC
fOSC
CR2
CR1
CR0
divisor
12 MHz
24 MHz
36 MHz
40 MHz
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
16
24
375
250
200
100
50
750
500
400
200
100
50
X
750
600
300
150
75
X
833
666
333
166
83
30
60
120
240
480
960
25
12.5
6.25
25
37.5
18.75
41
12.5
20
84/181
2
UPSD3212A, UPSD3212C, UPSD3212CV
I C interface
15.1
Serial status register (SxSTA: S1STA, S2STA)
SxSTA is a “Read-only” register. The contents of this register may be used as a vector to a
service routine. This optimized the response time of the software and consequently that of
2
2
the I C-bus. The status codes for all possible modes of the I C-bus interface are given Table
Table 54.
This flag is set, and an interrupt is generated, after any of the following events occur.
1. Own slave address has been received during AA = 1: ack_int
2. The general call address has been received while GC(SxADR.0) = 1 and AA = 1:
3. A data byte has been received or transmitted in Master mode (even if arbitration is lost):
ack_int
4. A data byte has been received or transmitted as selected slave: ack_int
5. A stop condition is received as selected slave receiver or transmitter: stop_int
15.2
Data shift register (SxDAT: S1DAT, S2DAT)
SxDAT contains the serial data to be transmitted or data whichas just been received. The
MSB (Bit 7) is transmitted or received first; that is, data shifted from right to left.
Table 53. Serial status register (SxSTA)
7
6
5
4
3
2
1
0
GC
STOP
INTR
TXO
BBUSY
BLOST
/ACK_REP
SLV
Table 54. Description of the SxSTA bits
Bit
Symbol
Function
7
6
5
GC
General Call Flag
Stop Flag. This bit is set when a STOP condition is received
SP
INTR(1,2) Interrupt Flag. This bit is set when an I²C Interrupt condition is requested
Transmission mode Flag.
TX_MODE
4
3
This bit is set when the I²C is a transmitter; otherwise this bit is reset
Bus Busy Flag.
BBUSY
BLOST
This bit is set when the bus is being used by another master; otherwise,
this bit is reset
Bus Lost Flag.
2
1
0
This bit is set when the master loses the bus contention; otherwise this bit
is reset
Acknowledge Response Flag.
/ACK_REP This bit is set when the receiver transmits the not acknowledge signal
This bit is reset when the receiver transmits the acknowledge signal
Slave mode Flag.
SLV
This bit is set when the I²C plays role in the Slave mode; otherwise this bit
is reset
1. Interrupt Flag bit (INTR, SxSTA Bit 5) is cleared by Hardware as reading SxSTA register.
2. I2C interrupt flag (INTR) can occur in below case. (except DDC2B mode at SWENB=0)
85/181
2
I C interface
UPSD3212A, UPSD3212C, UPSD3212CV
Table 55. Data shift register (SxDAT: S1DAT, S2DAT)
7
6
5
4
3
2
1
0
SxDAT7
SxDAT6
SxDAT5
SxDAT4
SxDAT3
SxDAT2
SxDAT1
SxDAT0
15.3
Address register (SxADR: S1ADR, S2ADR)
This 8-bit register may be loaded with the 7-bit slave address to which the controller will
respond when programmed as a slave receive/transmitter.
The Start/Stop Hold Time Detection and System Clock registers (Table 57 and Table 58) are
2
included in the I C unit to specify the start/stop detection time to work with the large range of
MCU frequency values supported. For example, with a system clock of 40MHz.
Table 56. Address register (SxADR)
7
6
5
4
3
2
1
0
SLA6
SLA5
SLA4
SLA3
SLA2
SLA1
SLA0
—
1. SLA6 to SLA0: Own slave address.
Table 57. Start /Stop Hold Time Detection Register (S1SETUP, S2SETUP)
Register
Name
Reset
Value
Address
Note
To control the start/stop hold time detection for the
DDC module in Slave mode
D1h
D2h
S1SETUP
S2SETUP
00h
00h
SFR
To control the start/stop hold time detection for the
multi-master I²C module in Slave mode
Table 58. System clock of 40MHz
S1SETUP,
S2SETUP
Regiser Value
Number of
Sample Clock
(fOSC/2 -> 50ns)
Required
Start/Stop Hold
Time
Note
When Bit 7 (enable bit) = 0, the number of
sample clock is 1EA (ignore Bit 6 to Bit 0)
00h
1EA
50ns
80h
81h
82h
...
1EA
2EA
3EA
...
50ns
100ns
150ns
...
Fast mode I²C Start/Stop hold time
specification
8Bh
12EA
600ns
...
...
...
FFh
128EA
6000ns
86/181
2
UPSD3212A, UPSD3212C, UPSD3212CV
I C interface
Table 59. System clock setup examples
S1SETUP,
S2SETUP
Register Value
Number of
Sample Clock
Required Start/Stop Hold
Time
System Clock
40MHz (fOSC/2 -> 50ns)
30MHz (fOSC/2 -> 66.6ns)
20MHz (fOSC/2 -> 100ns)
8MHz (fOSC/2 -> 250ns)
8Bh
89h
86h
83h
12 EA
9 EA
6 EA
3 EA
600ns
600ns
600ns
750ns
87/181
USB hardware
UPSD3212A, UPSD3212C, UPSD3212CV
16
USB hardware
The characteristics of USB hardware are as follows:
●
●
●
●
●
Complies with the Universal Serial Bus specification Rev. 1.1
Integrated SIE (Serial Interface Engine), FIFO memory and transceiver
Low speed (1.5Mbit/s) device capability
Supports control endpoint0 and interrupt endpoint1 and 2
USB clock input must be 6MHz (requires MCU clock frequency to be 12, 24, or
36MHz).
The analog front-end is an on-chip generic USB transceiver. It is designed to allow voltage
levels equal to V from the standard logic to interface with the physical layer of the
DD
Universal Serial Bus. It is capable of receiving and transmitting serial data at low speed
(1.5Mb/s).
The SIE is the digital-front-end of the USB block. This module recovers he 1.5MHz clock,
detects the USB sync word and handles all low-level USB protocols d error checking. The
bit-clock recovery circuit recovers the clock from the incoming SB data stream and is able
to track jitter and frequency drift according to the USB specification. The SIE also translates
the electrical USB signals into bytes or signals. Depending upon the device USB address
and the USB endpoint.
Address, the USB data is directed to the correct endpoint on SIE interface. The data transfer
of this H/W could be of type control or intept.
The device’s USB address and the enabling of the endpoints are programmable in the SIE
configuration header.
16.1
USB related registers
The USB blois controlled via seven registers in the memory: (UADR, UCON0, UCON1,
UCONUISTA, UIEN, and USTA).
Thee memory locations on chip which communicate the USB block are:
●
●
●
USB endpoint0 data transmit register (UDT0)
USB endpoint0 data receive register (UDR0)
USB endpoint1 data transmit register (UDT1)
Table 60. USB address register (UADR: 0EEh)
7
6
5
4
3
2
1
0
USBEN
UADD6
UADD5
UADD4
UADD3
UADD2
UADD1
UADD0
88/181
UPSD3212A, UPSD3212C, UPSD3212CV
USB hardware
Table 61. Description of the UADR Bits
Bit
Symbol
R/W
Function
USB Function Enable Bit.
When USBEN is clear, the USB module will not respond to
any tokens from host.
7
USBEN
R/W
RESET clears this bit.
Specify the USB address of the device.
RESET clears these bits.
UADD6 to
UADD0
6 to 0
R/W
Table 62. USB interrupt enable register (UIEN: 0E9h)
7
6
5
4
3
2
1
0
SUSPNDI
RSTE
RSTFIE
TXD0IE
RXD0IE
TXD1IE
EOPIE
RESUMI
Table 63. Description of the UIEN bits
Bit
Symbol
R/W
Function
7
SUSPNDI
R/W
Enable SUSPND Interrupt
Enable USB Reset; also resets the CPU and PSD modules
when bit is set to '1.'
6
RSTE
R/W
5
4
3
2
1
0
RSTFIE
TXD0IE
RXD0IE
TXD1IE
EOPIE
R/W
R/W
R/W
R/W
R/W
R/W
Enable RSTF (USB Bus Reset Flag) Interrupt
Enable TXD0 Interrupt
EnRXD0 Interrupt
Enable TXD1 Interrupt
Enable EOP Interrupt
RESUMI
Enable USB Resume Interrupt when it is the Suspend mode
Table 64. USinterrupt status register (UISTA: 0E8h)
7
6
5
4
3
2
1
0
SUSPND
—
RSTF
TXD0F
RXD0F
TXD1F
EOPF
RESUMF
Table 65. Description of the UISTA bits
Bit
Symbol
R/W
Function
USB Suspend Mode Flag.
To save power, this bit should be set if a 3ms constant idle
state is detected on USB bus. Setting this bit stops the clock to
the USB and causes the USB module to enter Suspend mode.
Software must clear this bit after the Resume flag (RESUMF)
is set while this Resume Interrupt Flag is serviced
7
6
5
SUSPND
—
R/W
—
Reserved
USB Reset Flag.
This bit is set when a valid RESET signal state is detected on
the D+ and D- lines. When the RSTE bit in the UIEN Register
is set, this reset detection will also generate an internal reset
signal to reset the CPU and other peripherals including the
USB module.
RSTF
R
89/181
USB hardware
UPSD3212A, UPSD3212C, UPSD3212CV
Table 65. Description of the UISTA bits (continued)
Bit
Symbol
R/W
Function
Endpoint0 Data Transmit Flag.
This bit is set after the data stored in Endpoint 0 transmit
buffers has been sent and an ACK handshake packet from the
host is received. Once the next set of data is ready in the
transmit buffers, software must clear this flag. To enable the
next data packet transmission, TX0E must also be set. If
TXD0F Bit is not cleared, a NAK handshake will be returned in
the next IN transactions. RESET clears this bit.
4
TXD0F
R/W
Endpoint0 Data Receive Flag.
This bit is set after the USB module has received a data
packet and responded with ACK handshake packet. Software
must clear this flag after all of the received data has been
read. Software must also set RX0E Bit to one to enable the
next data packet reception. If RXD0F Bit is not cleared, a NAK
handshake will be returned in the next T transaction.
RESET clears this bit.
3
RXD0F
R/W
Endpoint1 / Endpoint2 Data Transmit Flag.
This bit is shared by Endoints 1 and Endpoints 2. It is set
after the data stored in the shared Endpoint 1/ Endpoint 2
transmit buffer has been sent and an ACK handshake packet
from the host is eceived. Once the next set of data is ready in
the transit buffers, software must clear this flag. To enable
the t data packet transmission, TX1E must also be set. If
TXD1F Bit is not cleared, a NAK handshake will be returned in
the next IN transaction. RESET clears this bit.
2
TXD1F
R/W
End of Packet Flag.
This bit is set when a valid End of Packet sequence is
detected on the D+ and D-line. Software must clear this flag.
RESET clears this bit.
1
0
EOPF
R/W
R/W
Resume Flag.
This bit is set when USB bus activity is detected while the
SUSPND Bit is set.
RESUMF
Software must clear this flag. RESET clears this bit.
Table 66. USB Endpoint0 transmit control register (UCON0: 0EAh)
7
6
5
4
3
2
1
0
TSEQ0
STALL0
TX0E
RX0E
TP0SIZ3
TP0SIZ2
TP0SIZ1
TP0SIZ0
90/181
UPSD3212A, UPSD3212C, UPSD3212CV
USB hardware
Table 67. Description of the UCON0 bits
Bit
Symbol
R/W
Function
Endpoint0 Data Sequence Bit. (0=DATA0, 1=DATA1)
This bit determines which type of data packet (DATA0 or
DATA1) will be sent during the next IN transaction. Toggling of
this bit must be controlled by software. RESET clears this bit
7
TSEQ0
R/W
Endpoint0 Force Stall Bit.
This bit causes Endpoint 0 to return a STALL handshake when
polled by either an IN or OUT token by the USB Host
Controller. The USB hardware clears this bit when a SETUP
token is received. RESET clears this bit.
6
5
STALL0
TX0E
R/W
R/W
Endpoint0 Transmit Enable.
This bit enables a transmit to occur when the USB Host
Controller sends an IN token to Endpoint 0. Software should
set this bit when data is ready to be transmitted. It must be
cleared by software when no more Endint 0 data needs to
be transmitted. If this bit is '0' or the D0F is set, the USB will
respond with a NAK handshato any Endpoint 0 IN tokens.
RESET clears this bit.
Endpoint0 receive enable.
This bit enables a receive to occur when the USB Host
Controller sendan OUT token to Endpoint 0. Software should
set this bwhen data is ready to be received. It must be
cleby software when data cannot be received. If this bit is
'0' or the RXD0F is set, the USB will respond with a NAK
handshake to any Endpoint 0 OUT tokens. RESET clears this
bit.
4
RX0E
R/W
R/W
TP0SIZ3
to
TPIZ0
The number of transmit data bytes. These bits are cleared by
RESET.
3 to 0
Table . USB Endpoint1 (and 2) transmit control register (UCON1: 0EBh)
7
6
5
4
3
2
1
0
TSEQ1
EP12SEL
TX1E
FRESUM
TP1SIZ3
TP1SIZ2
TP1SIZ1
TP1SIZ0
91/181
USB hardware
UPSD3212A, UPSD3212C, UPSD3212CV
Function
Table 69. Description of the UCON1 bits
Bit
Symbol
R/W
Endpoint 1/ Endpoint 2 Transmit Data Packet PID. (0=DATA0,
1=DATA1) This bit determines which type of data packet
(DATA0 or DATA1) will be sent during the next IN transaction
directed to Endpoint 1 or Endpoint 2.
7
TSEQ1
R/W
Toggling of this bit must be controlled by software. RESET
clears this bit.
Endpoint 1/ Endpoint 2 Transmit Selection. (0=Endpoint 1,
1=Endpoint 2)
This bit specifies whether the data inside the registers UDT1
are used for Endpoint 1 or Endpoint 2. If all the conditions for a
successful Endpoint 2 USB response to a hosts IN token are
satisfied (TXD1F=0, TX1E=1, STALL2=0, and EP2E=1)
except that the EP12SEL Bit is configured for Endpoint 1, the
USB responds with a NAK handshake packet. RESET clears
this bit.
6
EP12SEL
R/W
Endpoint1 / Endpoint2 TransEnable.
This bit enables a transmit to occur when the USB Host
Controller send an IN token to Endpoint 1 or Endpoint 2. The
appropriate endpoienable bit, EP1E or EP2E Bit in the
UCON2 registe, should also be set. Software should set the
TX1E Bit when data is ready to be transmitted. It must be
cleared software when no more data needs to be
tratted. If this bit is '0' or TXD1F is set, the USB will
respond with a NAK handshake to any Endpoint 1 or Endpoint
2 directed IN token.
5
TX1E
R/W
RESET clears this bit.
Force Resume.
This bit forces a resume state (“K” on non-idle state) on the
USB data lines to initiate a remote wake-up. Software should
control the timing of the forced resume to be between 10ms
and 15ms. Setting this bit will not cause the RESUMF Bit to
set.
4
ESUM
R/W
R/W
TP1SIZ3
to
TP1SIZ0
The number of transmit data bytes. These bits are cleared by
RESET.
3 to 0
Table 70. USB control register (UCON2: 0ECh)
7
6
5
4
3
2
1
0
—
—
—
SOUT
EP2E
EP1E
STALL2
STALL1
Table 71. Description of the UCON2 bits
Bit
Symbol
R/W
Function
7 to 5
—
—
Reserved
Status out is used to automatically respond to the OUT of a
control READ transfer
4
3
SOUT
EP2E
R/W
R/W
Endpoint2 enable. RESET clears this bit
92/181
UPSD3212A, UPSD3212C, UPSD3212CV
USB hardware
Table 71. Description of the UCON2 bits (continued)
Bit Symbol R/W
EP1E R/W
Function
Endpoint1 enable. RESET clears this bit
2
1
0
STALL2
STALL1
R/W
R/W
Endpoint2 Force Stall Bit. RESET clears this bit
Endpoint1 Force Stall Bit. RESET clears this bit
Table 72. USB Endpoint0 status register (USTA: 0EDh)
7
6
5
4
3
2
1
0
RSEQ
SETUP
IN
OUT
RP0SIZ3
RP0SIZ2
RP0SIZ1
RP0SIZ0
Table 73. Description of the USTA bits
Bit
Symbol
R/W
Function
Endpoint0 receive data packet PID. (0=DATA0, 1=DATA1)
7
RSEQ
R/W
This bit will be compared with the type data packet last
received for Endpoint0
SETUP Token Detect Bit. This bit is set when the received
token packet is a SEPUP token, PID = b1101.
6
5
SETUP
IN
R
R
IN Token Detect Bit
This bit is set wen the received token packet is an IN token.
OUT Ton Detect Bit.
4
OUT
R
R
This set when the received token packet is an OUT
token.
RP0SIZ3
to
3 to 0
The number of data bytes received in a DATA packet
RP0SIZ0
Table 74. USEndpoint0 data receive register (UDR0: 0EFh)
7
6
5
4
3
2
1
0
UDR0.7
UDR0.6
UDR0.5
UDR0.4
UDR0.3
UDR0.2
UDR0.1
UDR0.0
Table 75. USB Endpoint0 data transmit register (UDT0: 0E7h)
7
6
5
4
3
2
1
0
UDT0.7
UDT0.6
UDT0.5
UDT0.4
UDT0.3
UDT0.2
UDT0.1
UDT0.0
Table 76. USB Endpoint1 data transmit register (UDT1: 0E6h)
7
6
5
4
3
2
1
0
UDT1.7
UDT1.6
UDT1.5
UDT1.4
UDT1.3
UDT1.2
UDT1.1
UDT1.0
The USCL 8-bit prescaler register for USB is at E1h. The USCL should be loaded with a
value that results in a clock rate of 6 MHz for the USB using the following formula:
USB clock input = (f
/ 2) / (Prescaler register value +1)
OSC
Where f
is the MCU clock input frequency.
OSC
Note:
USB works ONLY with the MCU Clock frequencies of 12, 24, or 36 MHz. The Prescaler
values for these frequencies are 0, 1, and 2.
93/181
USB hardware
UPSD3212A, UPSD3212C, UPSD3212CV
Table 77. USB SFR memory map
SFR
Reg
Bit Register Name
Reset
Add
Comments
value
Name
7
6
5
4
3
2
1
0
r
8-bit
Prescaler
for USB
logic
E1 USCL
00
USB
E6 UDT1
E7 UDT0
UDT1.7 UDT1.6 UDT1.5 UDT1.4 UDT1.3 UDT1.2 UDT1.1 UDT1.0
UDT0.7 UDT0.6 UDT0.5 UDT0.4 UDT0.3 UDT0.2 UDT0.1 UDT0.0
00
00
Endpt1
Data Xmit
USB
Endpt0
Data Xmit
USB
Interrupt
Status
E8 UISTA SUSPND
—
RSTF
TXD0F RXD0F RXD1F EOPF RESUF 00
RESUMI
USB
Interrupt
Enable
SUSPNDI
E9 UIEN
E
RSTE RSTFIE TXD0IE RXD0IE TXD1IE OPIE
00
E
USB
Endpt0
Xmit
EA UCON0 TSEQ0 STALL0 TX0E
RX0E TP0SIZ3 TP0SIZ2 TP0SIZ1 TP0SIZ0 00
Control
USB
Endpt1
Xmit
EP12SE
FRESU
EB UCON1 TSEQ1
—
TP1SIZ3 TP1SIZ2 TP1SIZ1 TP1SIZ0 00
M
L
Control
USB
EC UCON2
ED USTA
—
—
IN
SOUT
EP2E
EP1E STALL2 STALL1
00
Control
Register
USB
Endpt0
Status
RSEQ
SETUP
OUT RP0SIZ3 RP0SIZ2 RP0SIZ1 RP0SIZ0 00
USB
E UADR USBEN UADD6 UADD5 UADD4 UADD3 UADD2 UADD1 UADD0
EF UDR0 UDR0.7 UDR0.6 UDR0.5 UDR0.4 UDR0.3 UDR0.2 UDR0.1 UDR0.0
00
00
Address
Register
USB
Endpt0
Data Recv
16.2
Transceiver
16.2.1
USB physical layer characteristics
The following section describes the UPSD321xx devices compliance to the Chapter 7
Electrical section of the USB Specification, Revision 1.1. The section contains all signaling,
and physical layer specifications necessary to describe a low speed USB function.
94/181
UPSD3212A, UPSD3212C, UPSD3212CV
USB hardware
16.2.2
Low speed driver characteristics
The UPSD321xx devices use a differential output driver to drive the Low Speed USB data
signal onto the USB cable. The output swings between the differential high and low state are
well balanced to minimize signal skew. The slew rate control on the driver minimizes the
radiated noise and cross talk on the USB cable. The driver’s outputs support three-state
operation to achieve bi-directional half duplex operation. The UPSD321xx devices driver
tolerates a voltage on the signal pins of -0.5 V to 3.6 V with respect to local ground
reference without damage. The driver tolerates this voltage for 10.0µs while the driver is
active and driving, and tolerates this condition indefinitely when the driver is in its high
impedance state.
A low speed USB connection is made through an unshielded, untwisted wire cable a
maximum of 3 meters in length. The rise and fall time of the signals on this cable are well
controlled to reduce RFI emissions while limiting delays, signaling skews and distortions.
The UPSD321xx devices driver reaches the specified static signal levels with smooth rise
and fall times, resulting in segments between low speed devices and the ports to which they
are connected.
Figure 39. Low speed driver signal waveforms
One Bit
Time
1.5 Mb/s
V
SE(max)
Signal pins
pass output
spec levels
with minimal
reflections and
ringing
Driver
Signal Pins
VSE(min)
VSS
AI06629
16.3
Receiver characteristics
UPSD321xx devices have a differential input receiver which is able to accept the USB data
signal. The receiver features an input sensitivity of at least 200 mV when both differential
data inputs are in the range of at least 0.8 V to 2.5 V with respect to its local ground
reference. This is the common mode range, as shown in Figure 40. The receiver tolerates
static input voltages between -0.5 V to 3.8 V with respect to its local ground reference
without damage. In addition to the differential receiver, there is a single-ended receiver for
each of the two data lines. The single-ended receivers have a switching threshold between
0.8 V and 2.0 V (TTL inputs).
95/181
USB hardware
UPSD3212A, UPSD3212C, UPSD3212CV
Figure 40. Differential input sensitivity over entire common mode range
1.0
0.8
0.6
0.4
0.2
0.0
0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2
Common Mode Input Voltage (volts)
AI06630
16.4
External USB pull-up resistor
The USB system specifies a pull-up resistor on the D- pin for w-speed peripherals. The
USB Spec 1.1 describes a 1.5 kΩ pull-up resistor to a 3.3 V supply. An approved alternative
method is a 7.5 kΩ pull-up to the USB V supply. This aternative is defined for low-speed
CC
devices with an integrated cable. The chip is specifiefor the 7.5 kΩ pull-up. This eliminates
the need for an external 3.3 V regulator, or for a n dedicated to providing a 3.3 V output
from the chip.
Figure 41. USB data signal timing ad voltage levels
tR
tF
D+
VOH
VCR
VOL
90%
90%
10%
10%
D-
AI06631
Figure 42. Receiver jitter tolerance
TPERIOD
Differential
Data Lines
TJR2
TJR
TJR1
Consecutive
Transitions
N*TPERIOD+TJR1
Paired
Transitions
N*TPERIOD+TJR2
AI06632
96/181
UPSD3212A, UPSD3212C, UPSD3212CV
Figure 43. Differential to EOP transition skew and EOP width
USB hardware
TPERIOD
Crossover
Point Extended
Crossover
Point
Differential
Data Lines
Diff. Data to
SE0 Skew
N*TPERIOD+TDEOP
Source EOP Width: TEOPT
Receiver EOP Width
TEOPR1, TEOPR2
Figure 44. Differential data jitter
TPERIOD
Crossover
Points
Differential
Data Lines
Consecutive
Transitions
N*TPERIOD+TxJR1
Paired
Transitions
N*TPERIOD+2
AI06634
Table 78. Transceiver DC characteristics
Symb
Parameter
Static Output High
Test Conditions(1)
Min
Max
Unit
VOH
VOL
VDI
15 kΩ 5% to GND(2,3)
Notes 2, 3
2.8
—
3.6
0.3
—
V
V
V
Static utput Low
Differential Input Sensitivity
|(D+) - (D-)|, Figure 42
0.2
Differential Input Common
mode
VCM
VSE
Figure 42
0.8
0.8
2.5
2.0
V
V
Single Ended Receiver
Threshold
—
CIN
IIO
Transceiver Capacitance
—
—
20
10
pF
µA
Data Line (D+, D-) Leakage
0 < (D+,D-) < 3.3
–10
External Bus Pull-up
Resistance, D-
RPU
RPD
7.5 kΩ 2% to VCC
15 kΩ 5%
7.35
7.65
kΩ
kΩ
External Bus Pull-down
Resistance
14.25
15.75
1. VCC = 5 V 10%; VSS = 0 V; TA = 0 to 70°C.
2. Level guaranteed for range of VCC = 4.5 V to 5.5 V.
3. With RPU, external idle resistor, 7.5 κ 2%, D- to VCC
.
97/181
USB hardware
UPSD3212A, UPSD3212C, UPSD3212CV
Table 79. Transceiver AC characteristics
Symb
Parameter
Test Conditions(1)
Min
Max
Unit
Ave. bit rate (1.5Mb/s
1.5%)
tDRATE Low Speed Data Rate
1.4775 1.5225 Mbit/s
To next transition,
tDJR1
tDJR2
tDEOP
Receiver Data Jitter Tolerance
–75
–45
–40
75
45
ns
ns
ns
Figure 42(5)
For paired transition,
Differential Input Sensitivity
Figure 42(5)
Differential to EOP Transition
Skew
Figure 43(5)
100
tEOPR1 EOP Width at Receiver
tEOPR2 EOP Width at Receiver
tEOPT Source EOP Width
Rejects as EOP(5,6)
Accepts as EOP(5)
—
165
675
—
—
ns
ns
µs
–1.25
1.50
To next transition,
tUDJ1
tUDJ2
Differential Driver Jitter
Differential Driver Jitter
95
95
ns
ns
Figure 44
To paired transition,
–150
150
Figure 44
tR
tF
USB Data Transition Rise Time
USB Data Transition Fall Time
Rise/Fall Time Matching
Notes 2, 3, 4
Nes 2, 3, 4
tR / tF
75
75
80
300
300
120
ns
ns
%
tRFM
Output Signal Crossover
Voltage
VCRS
—
1.3
2.0
V
1. VCC = 5 V 10%; VSS = 0 V; TA = 0 to 70°C.
2. Level guaranteed for range of VCC = 4.5 V to 5.5 V.
3. With RPU, exterl idle resistor, 7.5κ 2%, D- to VCC
4. CL of 50 pF ns) to 350 pF (300 ns).
.
5. Meaed at crossover point of differential data signals.
6. USB specification indicates 330 ns.
98/181
UPSD3212A, UPSD3212C, UPSD3212CV
PSD module
17
PSD module
The PSD module provides configurable Program and Data memories to the 8032 CPU core
(MCU). In addition, it has its own set of I/O ports and a PLD with 16 macrocells for general
logic implementation.
Ports A,B,C, and D are general purpose programmable I/O ports that have a port
architecture which is different from the I/O ports in the MCU module.
The PSD module communicates with the MCU module through the internal address, data
bus (A0-A15, D0-D7) and control signals (RD, WR, PSEN, ALE, RESET). The user defines
the Decoding PLD in the PSDsoft Development Tool and can map the resources in the PSD
module to any program or data address space. Figure 45 shows the functional blocks in the
PSD module.
17.1
Functional overview
●
512 Kbit Flash memory. This is the main Flash memory. Is divided into four equal-
sized blocks (16 Kbytes each) that can be accessed with user-specified addresses.
●
Secondary 128 Kbit Flash boot memory. It is divided into two equal-sized blocks (8
Kbytes each) thatat can be accessed with user-pecified addresses. This secondary
memory brings the ability to execute code aupdate the main Flash concurrently.
●
●
16 Kbit SRAM.
CPLD with 16 Output Micro Cells MCs} and up to 20 Input Micro Cells (IMCs). The
CPLD may be used to efficiently implement a variety of logic functions for internal and
external control. Examples include state machines, loadable shift registers, and
loadable counters.
●
●
Decode PLD (DPLD) that decodes address for selection of memory blocks in the PSD
module.
Configule I/O ports (Port A,B,C and D) that can be used for the following functions:
–
–
–
–
–
MCU I/Os
PLD I/Os
Latched MCU address output
Special function I/Os
I/O ports may be configured as open-drain outputs
●
●
●
Built-in JTAG compliant serial port allows full-chip In-System Programmability (ISP).
With it, you can program a blank device or reprogram a device in the factory or the field.
Internal page register that can be used to expand the 8032 MCU module address
space by a factor of 256.
Internal programmable Power Management Unit (PMU) that supports a low-power
mode called Power-down mode. The PMU can automatically detect a lack of the 8032
CPU core activity and put the PSD module into Power-down mode.
●
Erase/WRITE cycles:
Flash memory - 100,000 minimum
PLD - 1,000 minimum
Data Retention: 15 year minimum (for Main Flash memory, Boot, PLD and
Configuration bits)
99/181
PSD module
UPSD3212A, UPSD3212C, UPSD3212CV
Figure 45. UPSD321xx PSD module block diagram
AI07431
17.2
In-system programming (ISP)
Using the JTAG signals on Port C, the entire PSD module device can be programmed or
erased without the use of the MCU. The primary Flash memory can also be programmed in-
system by the MCU executing the programming algorithms out of the secondary memory, or
SRAM. The secondary memory can be programmed the same way by executing out of the
primary Flash memory. The PLD or other PSD module configuration blocks can be
programmed through the JTAG port or a device programmer. Table Table 80 indicates which
programming methods can program different functional blocks of the PSD module.
100/181
UPSD3212A, UPSD3212C, UPSD3212CV
PSD module
Table 80. Methods of programming different functional blocks of the PSD module
Functional Block
JTAG programming Device programmer
IAP
Primary Flash memory
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
Secondary Flash memory
PLD array (DPLD and CPLD)
PSD module configuration
No
101/181
Development system
UPSD3212A, UPSD3212C, UPSD3212CV
18
Development system
UPSD321xx devices are supported by PSDsoft, a Windows-based software development
tool (Windows-95, Windows-98, Windows-NT). A PSD module design is quickly and easily
produced in a point and click environment. The designer does not need to enter Hardware
Description Language (HDL) equations, unless desired, to define PSD module pin functions
and memory map information. The general design flow is shown in Figure 46. PSDsoft is
available from our web site (the address is given on the back page of this data sheet) or
other distribution channels.
PSDsoft directly supports a low cost device programmer from ST: FlashLINK (JTAG). The
programmer may be purchased through your local distributor/representative. UPSD321xx
devices are also supported by third party device programmers. See our web site for the
current list.
Figure 46. PSDsoft express development tool
Choose µPSD
Define µPSD Pin and
Node Functions
Point and click defin
PSD pin functions, internal nodes,
and MCU system memory map
Define General Purpose
C Code Generation
Logic in CPLD
GENERATE C CODE
SPECIFIC TO PSD
Point and click definition of combin-
atorial and registered logic in CPLD.
Access HDL is available if needed
FUNCTIONS
Merge MCU Firmware with
PSD Module Configuration
USER'S CHOICE OF
8032
COMPILER/LINKER
MCU FIRMWARE
A composite object file is created
containing MCU firmware and
PSD configuration
HEX OR S-RECORD
FORMAT
*.OBJ FILE
PSD Programmer
FlashLINK (JTAG)
*.OBJ FILE
AVAILABLE
FOR 3rd PARTY
PROGRAMMERS
AI05798
102/181
UPSD3212A, UPSD3212C, UPSD3212CV
PSD module register description and address offset
19
PSD module register description and address offset
Table 81 shows the offset addresses to the PSD module registers relative to the CSIOP
base address. The CSIOP space is the 256 bytes of address that is allocated by the user to
the internal PSD module registers. Table 81 provides brief descriptions of the registers in
CSIOP space. The following section gives a more detailed description.
Table 81. Register address offset
Register Name Port A Port B Port C Port D Other(1)
Description
Reads Port pin as input, MCU I/O Input
mode
Data In
Control
00
02
01
03
10
11
Selects mode between MCU I/O or
Address Out
Stores data for output to Port pins,
MCU I/O Output ode
Data Out
Direction
04
06
05
07
12
14
13
15
Confies Port pin as input or output
Configures Port pins as either CMOS
or Open Drain on some pins, while
selecting high slew rate on other pins.
Drive Select
08
09
16
17
Input Macrocell
Enable Out
0A
0C
0B
0D
18
1A
Reads Input Macrocells
Reads the status of the output enable
to the I/O Port driver
1B
READ – reads output of macrocells AB
WRITE – loads macrocell flip-flops
Output Macrocells
AB
20
20
READ – reads output of macrocells BC
WRITE – loads macrocell flip-flops
Output Macrocells
BC
21
22
23
21
23
Mask Macroce
AB
Blocks writing to the Output Macrocells
AB
22
Msk Macrocells
BC
Blocks writing to the Output Macrocells
BC
Primary Flash
Protection
Read-only – Primary Flash Sector
Protection
C0
C2
Secondary Flash
memory
Protection
Read-only – PSD module Security and
Secondary Flash memory Sector
Protection
PMMR0
PMMR2
Page
B0
B4
E0
Power Management Register 0
Power Management Register 2
Page Register
Places PSD module memory areas in
Program and/or Data space on an
individual basis.
VM
E2
1. Other registers that are not part of the I/O ports.
103/181
PSD module detailed operation
UPSD3212A, UPSD3212C, UPSD3212CV
20
PSD module detailed operation
As shown in Figure 14, the PSD module consists of five major types of functional blocks:
●
●
●
●
●
Memory blocks
PLD blocks
I/O Ports
Power Management Unit (PMU)
JTAG Interface
The functions of each block are described in the following sections. Many of the blocks
perform multiple functions, and are user configurable.
104/181
UPSD3212A, UPSD3212C, UPSD3212CV
Memory blocks
21
Memory blocks
The PSD module has the following memory blocks:
●
●
●
Primary Flash memory
Secondary Flash memory
SRAM
The Memory Select signals for these blocks originate from the Decode PLD (DPLD) and are
user-defined in PSDsoft Express.
21.1
Primary Flash memory and secondary Flash memory
description
The primary Flash memory is divided evenly into four equal sectors. The secondary Flash
memory is divided into two equal sectors. Each sector of either memorblock can be
separately protected from Program and Erase cycles.
Flash memory may be erased on a sector-by-sector basis. Flash sector erasure may be
suspended while data is read from other sectors of the blck and then resumed after
reading.
During a Program or Erase cycle in Flash memorthe status can be output on Ready/Busy
(PC3). This pin is set up using PSDsoft Exess Configuration.
21.2
Memory block select signals
The DPLD generates the Select signals for all the internal memory blocks (see Section 22:
PLDs). Each of the four sectors of the primary Flash memory has a Select signal (FS0-FS3)
which can contaup to three product terms. Each of the two sectors of the secondary Flash
memory has Select signal (CSBOOT0-CSBOOT1) which can contain up to three product
terms. aving three product terms for each Select signal allows a given sector to be
mapped in Program or Data space.
21.2.1
21.2.2
Ready/Busy (PC3)
This signal can be used to output the Ready/Busy status of the Flash memory. The output
on Ready/Busy (PC3) is a '0' (Busy) when Flash memory is being written to, or when Flash
memory is being erased. The output is a '1' (Ready) when no WRITE or Erase cycle is in
progress.
Memory operation
The primary Flash memory and secondary Flash memory are addressed through the MCU
Bus. The MCU can access these memories in one of two ways:
●
The MCU can execute a typical bus WRITE or READ operation.
●
The MCU can execute a specific Flash memory instruction that consists of several
WRITE and READ operations. This involves writing specific data patterns to special
addresses within the Flash memory to invoke an embedded algorithm. These
instructions are summarized in Table 82.
105/181
Memory blocks
UPSD3212A, UPSD3212C, UPSD3212CV
Typically, the MCU can read Flash memory using READ operations, just as it would read a
ROM device. However, Flash memory can only be altered using specific Erase and Program
instructions. For example, the MCU cannot write a single byte directly to Flash memory as it
would write a byte to RAM. To program a byte into Flash memory, the MCU must execute a
Program instruction, then test the status of the Program cycle. This status test is achieved
by a READ operation or polling Ready/Busy (PC3).
21.3
Instructions
An instruction consists of a sequence of specific operations. Each received byte is
sequentially decoded by the PSD module and not executed as a standard WRITE operation.
The instruction is executed when the correct number of bytes are properly received and the
time between two consecutive bytes is shorter than the time-out period. Some instructions
are structured to include READ operations after the initial WRITE operations.
The instruction must be followed exactly. Any invalid combination of instruction bytes or
time-out between two consecutive bytes while addressing Flash memorresets the device
logic into READ mode (Flash memory is read like a ROM device).
The Flash memory supports the instructions summarized in Tble 82:
●
●
●
●
●
Erase memory by chip or sector
Suspend or resume sector erase
Program a Byte
RESET to READ mode
Read Sector Protection Status
These instructions are detailed in Table 82. For efficient decoding of the instructions, the first
two bytes of an instruction are the coded cycles and are followed by an instruction byte or
confirmation byte. The coded cycles consist of writing the data AAh to address X555h
during the first cycle and data 55h to address XAAAh during the second cycle. Address
signals A15-A12 re Don’t Care during the instruction WRITE cycles. However, the
appropriate Sctor Select (FS0-FS3 or CSBOOT0-CSBOOT1) must be selected.
The primary and secondary Flash memories have the same instruction set (except for Read
Prmary Flash Identifier). The Sector Select signals determine which Flash memory is to
receive and execute the instruction. The primary Flash memory is selected if any one of
Sector Select (FS0-FS3) is High, and the secondary Flash memory is selected if any one of
Sector Select (CSBOOT0-CSBOOT1) is High.
Table 82. Instructions
FS0-FS3 or
Instruction
CSBOOT0- Cycle 1
Cycle 2
Cycle 3
Cycle 4
Cycle 5
Cycle 6
Cycle 7
CSBOOT1
“Read”
RD @ RA
READ(5)
1
Read
status @
XX02h
READ Sector
AAh@
X555h
55h@
XAAAh
90h@
X555h
1
1
Protection(6,8,13)
Program a Flash
Byte(13)
AAh@
X555h
55h@
XAAAh
A0h@
X555h
PD@ PA
106/181
UPSD3212A, UPSD3212C, UPSD3212CV
Memory blocks
Table 82. Instructions (continued)
FS0-FS3 or
Instruction
CSBOOT0- Cycle 1
Cycle 2
Cycle 3
Cycle 4
Cycle 5
Cycle 6
Cycle 7
CSBOOT1
Flash Sector
Erase(7,13)
AAh@
X555h
55h@
XAAAh
80h@
X555h
AAh@
X555h
55h@
XAAAh
30h7@
next SA
1
30h@ SA
Flash Bulk
Erase(13)
AAh@
X555h
55h@
XAAAh
80h@
X555h
AAh@
X555h
55h@
XAAAh
10h@
X555h
1
Suspend Sector
Erase(11)
B0h@
XXXXh
1
Resume Sector
Erase(12)
30h@
XXXXh
1
F0h@
RESET(6)
1
XXXXh
1. All bus cycles are WRITE bus cycles, except the ones with the “Read” label
2. All values are in hexadecimal.
3. X = Don’t care. Addresses of the form XXXXh, in this table, must be even addresses
4. RA = Address of the memory location to be read
5. RD = Data READ from location RA during the READ cycle
6. PA = Address of the memory location to be programmedddresses are latched on the falling edge of
WRITE Strobe (WR, CNTL0).
7. PA is an even address for PSD in Word Programng mode.
8. PD = Data word to be programmed at locaA. Data is latched on the rising edge of WRITE Strobe
(WR, CNTL0)
9. SA = Address of the sector to be erased or verified. The Sector Select (FS0-FS3 or CSBOOT0-CSBOOT1)
of the sector to be erased, or verified, must be Active (High).
10. Sector Select (FS0-FS3 or CSBOOT0-CSBOOT1) signals are active High, and are defined in PSDsoft
Express.
11. Only address Bits A11-A0 are used in instruction decoding.
12. No Unlock or inction cycles are required when the device is in the READ mode
13. The RESET truction is required to return to the READ mode after reading the Sector Protection Status,
or if Error flag bit (DQ5) goes High.
14. Additional sectors to be erased must be written at the end of the Sector Erase instruction within 80µs.
15. The data is 00h for an unprotected sector, and 01h for a protected sector. In the fourth cycle, the Sector
Select is active, and (A1,A0)=(1,0)
16. The system may perform READ and Program cycles in non-erasing sectors, read the Flash ID or read the
Sector Protection Status when in the Suspend Sector Erase mode. The Suspend Sector Erase instruction
is valid only during a Sector Erase cycle.
17. The Resume Sector Erase instruction is valid only during the Suspend Sector Erase mode.
18. The MCU cannot invoke these instructions while executing code from the same Flash memory as that for
which the instruction is intended. The MCU must retrieve, for example, the code from the secondary Flash
memory when reading the Sector Protection Status of the primary Flash memory.
21.4
Power-down instruction and Power-up mode
21.4.1
Power-up mode
The PSD module internal logic is reset upon Power-up to the READ mode. Sector Select
(FS0-FS3 and CSBOOT0-CSBOOT1) must be held Low, and WRITE Strobe (WR, CNTL0)
High, during Power-up for maximum security of the data contents and to remove the
107/181
Memory blocks
UPSD3212A, UPSD3212C, UPSD3212CV
possibility of a byte being written on the first edge of WRITE Strobe (WR, CNTL0). Any
WRITE cycle initiation is locked when V is below V
.
LKO
CC
21.5
Read
Under typical conditions, the MCU may read the primary Flash memory or the secondary
Flash memory using READ operations just as it would a ROM or RAM device. Alternately,
the MCU may use READ operations to obtain status information about a Program or Erase
cycle that is currently in progress. Lastly, the MCU may use instructions to read special data
from these memory blocks. The following sections describe these READ functions.
21.5.1
21.5.2
Read memory contents
Primary Flash memory and secondary Flash memory are placed in the READ mode after
Power-up, chip reset, or a Reset Flash instruction (see Table 82). The MCU can read the
memory contents of the primary Flash memory or the secondary Flash memory by using
READ operations any time the READ operation is not part of an instruon.
Read memory sector protection status
The primary Flash memory Sector Protection Status is read with an instruction composed of
4 operations: 3 specific WRITE operations and a READ operation (see Table 82). During the
READ operation, address Bits A6, A1, and A0 mt be '0,' '1,' and '0,' respectively, while
Sector Select (FS0-FS3 or CSBOOT0-CSBOOT1) designates the Flash memory sector
whose protection has to be verified. TEAD operation produces 01h if the Flash memory
sector is protected, or 00h if the sector is not protected.
The sector protection status for all NVM blocks (primary Flash memory or secondary Flash
memory) can also be read by the MCU accessing the Flash Protection registers in PSD I/O
space. See Section 21.8.1: Flash memory sector protect for register definitions.
21.5.3
21.5.4
Reading thErase/Program status bits
The Flash memory provides several status bits to be used by the MCU to confirm the
completion of an Erase or Program cycle of Flash memory. These status bits minimize the
time that the MCU spends performing these tasks and are defined in Table 83. The status
bits can be read as many times as needed.
For Flash memory, the MCU can perform a READ operation to obtain these status bits while
an Erase or Program instruction is being executed by the embedded algorithm. See
Section 21.6: Programming Flash memory, for details.
Data polling flag (DQ7)
When erasing or programming in Flash memory, the Data Polling flag bit (DQ7) outputs the
complement of the bit being entered for programming/writing on the DQ7 Bit. Once the
108/181
UPSD3212A, UPSD3212C, UPSD3212CV
Memory blocks
Program instruction or the WRITE operation is completed, the true logic value is read on the
Data Polling flag bit (DQ7) (in a READ operation).
●
Data Polling is effective after the fourth WRITE pulse (for a Program instruction) or after
the sixth WRITE pulse (for an Erase instruction). It must be performed at the address
being programmed or at an address within the Flash memory sector being erased.
●
During an Erase cycle, the Data Polling flag bit (DQ7) outputs a '0.' After completion of
the cycle, the Data Polling flag bit (DQ7) outputs the last bit programmed (it is a '1' after
erasing).
●
●
If the byte to be programmed is in a protected Flash memory sector, the instruction is
ignored.
If all the Flash memory sectors to be erased are protected, the Data Polling flag bit
(DQ7) is reset to '0' for about 100µs, and then returns to the previous addressed byte.
No erasure is performed.
21.5.5
Toggle flag (DQ6)
The Flash memory offers another way for determining when the Progracycle is
completed. During the internal WRITE operation and when either the FS0-FS3 or
CSBOOT0-CSBOOT1 is true, the Toggle flag bit (DQ6) togglefrom '0' to '1' and '1' to '0' on
subsequent attempts to read any byte of the memory.
When the internal cycle is complete, the toggling stops and the data READ on the Data Bus
D0-D7 is the addressed memory byte. The devics now accessible for a new READ or
WRITE operation. The cycle is finished when two successive Reads yield the same output
data.
●
●
●
The Toggle flag bit (DQ6) is effective after the fourth WRITE pulse (for a Program
instruction) or after the sixth WRITE pulse (for an Erase instruction).
If the byte to be programmed belongs to a protected Flash memory sector, the
instruction is ignored.
If all the Flash memory sectors selected for erasure are protected, the Toggle flag bit
(DQ6) toggles to '0' for about 100µs and then returns to the previous addressed byte.
21.5.6
Error flag (DQ5)
During a normal Program or Erase cycle, the Error flag bit (DQ5) is to '0.' This bit is set to '1'
when there is a failure during Flash memory Byte Program, Sector Erase, or Bulk Erase
cycle.
In the case of Flash memory programming, the Error flag bit (DQ5) indicates the attempt to
program a Flash memory bit from the programmed state, '0', to the erased state, '1,' which is
not valid. The Error flag bit (DQ5) may also indicate a Time-out condition while attempting to
program a byte.
In case of an error in a Flash memory Sector Erase or Byte Program cycle, the Flash
memory sector in which the error occurred or to which the programmed byte belongs must
no longer be used. Other Flash memory sectors may still be used. The Error Flag bit (DQ5)
is reset after a Reset Flash instruction.
21.5.7
Erase time-out flag (DQ3)
The Erase Time-out Flag bit (DQ3) reflects the time-out period allowed between two
consecutive Sector Erase instructions. The Erase Time-out Flag bit (DQ3) is reset to '0' after
109/181
Memory blocks
UPSD3212A, UPSD3212C, UPSD3212CV
a Sector Erase cycle for a time period of 100µs + 20% unless an additional Sector Erase
instruction is decoded. After this time period, or when the additional Sector Erase instruction
is decoded, the Erase Time-out Flag bit (DQ3) is set to ‘1’.
Table 83. Status bit
FS0-FS3/
Functional Block CSBOOT0-
CSBOOT1
DQ7
DQ6
DQ5
DQ4
X
DQ3
DQ2
X
DQ1
X
DQ0
X
Data
Polling
Toggle
Flag
Error
Flag
Erase
Time-out
Flash Memory
VIH
1. X = Not guaranteed value, can be read either '1' or '0.'
2. DQ7-DQ0 represent the Data Bus bits, D7-D0.
3. FS0-FS3 and CSBOOT0-CSBOOT1 are active High.
21.6
Programming Flash memory
Flash memory must be erased prior to being programmed. A byte of Flash memory is
erased to all '1's (FFh), and is programmed by setting selected bits to '0'. The MCU may
erase Flash memory all at once or by-sector, but not byteby-byte. However, the MCU may
program Flash memory byte-by-byte.
The primary and secondary Flash memories reqe the MCU to send an instruction to
program a byte or to erase sectors (see Table 82).
Once the MCU issues a Flash memorrogram or Erase instruction, it must check for the
status bits for completion. The embedded algorithms that are invoked support several
means to provide status to the MCU. Status may be checked using any of three methods:
Data Polling, Data Toggle, or Ready/Busy (PC3).
21.6.1
Data Polling
Polling on the Data Polling Flag bit (DQ7) is a method of checking whether a Program or
Erase cycle is in progress or has completed. Figure 47 shows the Data Polling algorithm.
When the MCU issues a Program instruction, the embedded algorithm begins. The MCU
then reads the location of the byte to be programmed in Flash memory to check status. The
Data Polling Flag bit (DQ7) of this location becomes the complement of b7 of the original
data byte to be programmed. The MCU continues to poll this location, comparing the Data
Polling Flag bit (DQ7) and monitoring the Error Flag bit (DQ5). When the Data Polling Flag
bit (DQ7) matches b7 of the original data, and the Error Flag bit (DQ5) remains '0,' the
embedded algorithm is complete. If the Error Flag bit (DQ5) is '1,' the MCU should test the
Data Polling Flag bit (DQ7) again since the Data Polling Flag bit (DQ7) may have changed
simultaneously with the Error Flag bit (DQ5) (see Figure 47).
The Error Flag bit (DQ5) is set if either an internal time-out occurred while the embedded
algorithm attempted to program the byte or if the MCU attempted to program a '1' to a bit
that was not erased (not erased is logic '0').
It is suggested (as with all Flash memories) to read the location again after the embedded
programming algorithm has completed, to compare the byte that was written to the Flash
memory with the byte that was intended to be written.
110/181
UPSD3212A, UPSD3212C, UPSD3212CV
Memory blocks
When using the Data Polling method during an Erase cycle, Figure 47 still applies. However,
the Data Polling Flag bit (DQ7) is '0' until the Erase cycle is complete. A '1' on the Error Flag
bit (DQ5) indicates a time-out condition on the Erase cycle; a '0' indicates no error. The
MCU can read any location within the sector being erased to get the Data Polling Flag bit
(DQ7) and the Error Flag bit (DQ5).
PSDsoft Express generates ANSI C code functions which implement these Data Polling
algorithms.
Figure 47. Data polling flowchart
START
READ DQ5 & DQ7
at VALID ADDRESS
DQ7
=
YES
DATA
NO
NO
DQ5
= 1
YES
READ DQ7
Q7
YES
DA
NO
FAIL
PASS
AI01369B
21.6.2
Data toggle
Checkthe Toggle Flag bit (DQ6) is a method of determining whether a Program or Erase
cycle is in progress or has completed. Figure 48 shows the Data Toggle algorithm.
When the MCU issues a Program instruction, the embedded algorithm begins. The MCU
then reads the location of the byte to be programmed in Flash memory to check status. The
Toggle Flag bit (DQ6) of this location toggles each time the MCU reads this location until the
embedded algorithm is complete. The MCU continues to read this location, checking the
Toggle Flag bit (DQ6) and monitoring the Error Flag bit (DQ5). When the Toggle Flag bit
(DQ6) stops toggling (two consecutive reads yield the same value), and the Error Flag bit
(DQ5) remains '0,' the embedded algorithm is complete. If the Error Flag bit (DQ5) is '1,' the
MCU should test the Toggle Flag bit (DQ6) again, since the Toggle Flag bit (DQ6) may have
changed simultaneously with the Error Flag bit (DQ5) (see Figure 48).
The Error Flag bit (DQ5) is set if either an internal time-out occurred while the embedded
algorithm attempted to program the byte, or if the MCU attempted to program a '1' to a bit
that was not erased (not erased is logic '0').
It is suggested (as with all Flash memories) to read the location again after the embedded
programming algorithm has completed, to compare the byte that was written to Flash
memory with the byte that was intended to be written.
111/181
Memory blocks
UPSD3212A, UPSD3212C, UPSD3212CV
When using the Data Toggle method after an Erase cycle, Figure 48 still applies. the Toggle
Flag bit (DQ6) toggles until the Erase cycle is complete. A 1 on the Error Flag bit (DQ5)
indicates a time-out condition on the Erase cycle; a '0' indicates no error. The MCU can read
any location within the sector being erased to get the Toggle Flag bit (DQ6) and the Error
Flag bit (DQ5).
PSDsoft Express generates ANSI C code functions which implement these Data Toggling
algorithms.
Figure 48. Data toggle flowchart
START
READ
DQ5 & DQ6
DQ6
NO
=
TOGGLE
YES
NO
DQ5
= 1
YES
READ DQ6
DQ6
=
NO
TOGGLE
YES
FAIL
PASS
AI01370B
21.7
Erasing Flash memory
21.7.1
Flash Bulk Erase
The Flash Bulk Erase instruction uses six WRITE operations followed by a READ operation
of the status register, as described in Table 82. If any byte of the Bulk Erase instruction is
wrong, the Bulk Erase instruction aborts and the device is reset to the READ Flash memory
status.
During a Bulk Erase, the memory status may be checked by reading the Error Flag bit
(DQ5), the Toggle Flag bit (DQ6), and the Data Polling Flag bit (DQ7), as detailed in
Section 21.6: Programming Flash memory. The Error Flag bit (DQ5) returns a '1' if there has
been an Erase Failure (maximum number of Erase cycles have been executed).
It is not necessary to program the memory with 00h because the PSD module automatically
does this before erasing to 0FFh.
During execution of the Bulk Erase instruction, the Flash memory does not accept any
instructions.
112/181
UPSD3212A, UPSD3212C, UPSD3212CV
Memory blocks
21.7.2
Flash Sector Erase
The Sector Erase instruction uses six WRITE operations, as described in Table 82.
Additional Flash Sector Erase codes and Flash memory sector addresses can be written
subsequently to erase other Flash memory sectors in parallel, without further coded cycles,
if the additional bytes are transmitted in a shorter time than the time-out period of about
100µs. The input of a new Sector Erase code restarts the time-out period.
The status of the internal timer can be monitored through the level of the Erase Time-out
Flag bit (DQ3). If the Erase Time-out Flag bit (DQ3) is '0,' the Sector Erase instruction has
been received and the time-out period is counting. If the Erase Time-out Flag bit (DQ3) is '1,'
the time-out period has expired and the embedded algorithm is busy erasing the Flash
memory sector(s). Before and during Erase time-out, any instruction other than Suspend
Sector Erase and Resume Sector Erase instructions abort the cycle that is currently in
progress, and reset the device to READ mode.
During a Sector Erase, the memory status may be checked by reading the Error Flag bit
(DQ5), the Toggle Flag bit (DQ6), and the Data Polling Flag bit (DQ7), as detailed in
Section 21.6: Programming Flash memory.
During execution of the Erase cycle, the Flash memory acceponly RESET and Suspend
Sector Erase instructions. Erasure of one Flash memory sector may be suspended, in order
to read data from another Flash memory sector, and then resumed.
21.7.3
Suspend Sector Erase
When a Sector Erase cycle is in progress, e Suspend Sector Erase instruction can be
used to suspend the cycle by writing 0h to any address when an appropriate Sector
Select (FS0-FS3 or CSBOOT0-CSBOOT1) is High. (See Table 82). This allows reading of
data from another Flash memory sector after the Erase cycle has been suspended.
Suspend Sector Erase is accepted only during an Erase cycle and defaults to READ mode.
A Suspend Sector Erase instruction executed during an Erase time-out period, in addition to
suspending the Erase cycle, terminates the time out period.
The Toggle Fg bit (DQ6) stops toggling when the internal logic is suspended. The status of
this bit ust be monitored at an address within the Flash memory sector being erased. The
Toggle Flag bit (DQ6) stops toggling between 0.1µs and 15µs after the Suspend Sector
Erase instruction has been executed. The Flash memory is then automatically set to READ
mode.
If an Suspend Sector Erase instruction was executed, the following rules apply:
●
Attempting to read from a Flash memory sector that was being erased outputs invalid
data.
●
●
Reading from a Flash sector that was not being erased is valid.
The Flash memory cannot be programmed, and only responds to Resume Sector
Erase and Reset Flash instructions (READ is an operation and is allowed).
●
If a Reset Flash instruction is received, data in the Flash memory sector that was being
erased is invalid.
21.7.4
Resume Sector Erase
If a Suspend Sector Erase instruction was previously executed, the erase cycle may be
resumed with this instruction. The Resume Sector Erase instruction consists of writing 030h
113/181
Memory blocks
UPSD3212A, UPSD3212C, UPSD3212CV
to any address while an appropriate Sector Select (FS0-FS3 or CSBOOT0-CSBOOT1) is
High. (See Table 82.)
21.8
Specific features
21.8.1
Flash memory sector protect
Each primary and secondary Flash memory sector can be separately protected against
Program and Erase cycles. Sector Protection provides additional data security because it
disables all Program or Erase cycles. This mode can be activated through the JTAG Port or
a Device Programmer.
Sector protection can be selected for each sector using the PSDsoft Express Configuration
program. This automatically protects selected sectors when the device is programmed
through the JTAG Port or a Device Programmer. Flash memory sectors can be unprotected
to allow updating of their contents using the JTAG Port or a Device Programmer. The MCU
can read (but cannot change) the sector protection bits.
Any attempt to program or erase a protected Flash memory stor is ignored by the device.
The Verify operation results in a READ of the protected data. This allows a guarantee of the
retention of the Protection status.
The sector protection status can be read by the MCU through the Flash memory protection
registers (in the CSIOP block). See Table 84 and able 85.
Table 84. Sector protection/secubit definition – Flash protection register
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Not used
Not used
Not used
Not used Sec3_Prot Sec2_Prot Sec1_Prot Sec0_Prot
1. Bit Definitions:
Sec<i>_Prot
1 = Primary Flash memory or secondary Flash memory Sector <i> is write-protected.
= Primary Flash memory or secondary Flash memory Sector <i> is not write-protected.
Sec<i>_Prot
Table 8. Sector protection/security bit definition – secondary Flash protection
register
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Security_B
it
Not used
Not used
Not used
Not used
Not used Sec1_Prot Sec0_Prot
1. Bit Definitions:
Sec<i>_Prot
1 = Secondary Flash memory Sector <i> is write-protected.
0 = Secondary Flash memory Sector <i> is not write-protected.
0 = Security Bit in device has not been set; 1 = Security Bit in device has been set.
Sec<i>_Prot
Security_Bit
21.8.2
Reset Flash
The Reset Flash instruction consists of one WRITE cycle (see Table 82). It can also be
optionally preceded by the standard two WRITE decoding cycles (writing AAh to 555h and
55h to AAAh). It must be executed after:
●
Reading the Flash Protection Status or Flash ID
●
An Error condition has occurred (and the device has set the Error Flag bit (DQ5) to '1'
during a Flash memory Program or Erase cycle.
114/181
UPSD3212A, UPSD3212C, UPSD3212CV
Memory blocks
The Reset Flash instruction puts the Flash memory back into normal READ mode. If an
Error condition has occurred (and the device has set the Error Flag bit (DQ5) to '1' the Flash
memory is put back into normal READ mode within a few milliseconds of the Reset Flash
instruction having been issued. The Reset Flash instruction is ignored when it is issued
during a Program or Bulk Erase cycle of the Flash memory. The Reset Flash instruction
aborts any on-going Sector Erase cycle, and returns the Flash memory to the normal READ
mode within a few milliseconds.
21.9
SRAM
The SRAM is enabled when SRAM Select (RS0) from the DPLD is High. SRAM Select
(RS0) can contain up to two product terms, allowing flexible memory mapping.
21.10
Sector Select and SRAM Select
Sector Select (FS0-FS3, CSBOOT0-CSBOOT1) and SRAM Select (RS) are all outputs of
the DPLD. They are setup by writing equations for them in PSDsoft press. The following
rules apply to the equations for these signals:
1. Primary Flash memory and secondary Flash memorSector Select signals must not
be larger than the physical sector size.
2. Any primary Flash memory sector must not e mapped in the same memory space as
another Flash memory sector.
3. A secondary Flash memory sectust not be mapped in the same memory space as
another secondary Flash memory sector.
4. SRAM, I/O, and Peripheral I/O spaces must not overlap.
5. A secondary Flash memory sector may overlap a primary Flash memory sector. In
case of overlap, priority is given to the secondary Flash memory sector.
6. SRAM, I/O, nd Peripheral I/O spaces may overlap any other memory sector. Priority is
given to e SRAM, I/O, or Peripheral I/O.
21.10.1 Example
FS0 is valid when the address is in the range of 8000h to BFFFh, CSBOOT0 is valid from
8000h to 9FFFh, and RS0 is valid from 8000h to 87FFh. Any address in the range of RS0
always accesses the SRAM. Any address in the range of CSBOOT0 greater than 87FFh
(and less than 9FFFh) automatically addresses secondary Flash memory segment 0. Any
address greater than 9FFFh accesses the primary Flash memory segment 0. You can see
that half of the primary Flash memory segment 0 and one-fourth of secondary Flash
memory segment 0 cannot be accessed in this example.
Note:
An equation that defined FS1 to anywhere in the range of 8000h to BFFFh would not be
valid.
Figure 49 shows the priority levels for all memory components. Any component on a higher
level can overlap and has priority over any component on a lower level. Components on the
same level must not overlap. Level one has the highest priority and level 3 has the lowest.
115/181
Memory blocks
UPSD3212A, UPSD3212C, UPSD3212CV
21.10.2 Memory Select configuration in Program and Data spaces
The MCU Core has separate address spaces for Program memory and Data memory. Any
of the memories within the PSD module can reside in either space or both spaces. This is
controlled through manipulation of the VM Register that resides in the CSIOP space.
The VM Register is set using PSDsoft Express to have an initial value. It can subsequently
be changed by the MCU so that memory mapping can be changed on-the-fly.
For example, you may wish to have SRAM and primary Flash memory in the Data space at
Boot-up, and secondary Flash memory in the Program space at Boot-up, and later swap the
primary and secondary Flash memories. This is easily done with the VM Register by using
PSDsoft Express Configuration to configure it for Boot-up and having the MCU change it
when desired. Table 86 describes the VM Register.
Figure 49. Priority level of memory and I/O components in the PSD module
Highest Priority
Level 1
SRAM, I/O, or
Peripheral I/O
Level 2
Secondary
Non-Volatile Memory
Level 3
Primary Flash Mmory
Lowest Priority
AI02867D
Table 86. VM register
Bit 7
Bit 2
Bit 4
Bit 3
Bit 1
Bit 0
Primary
FL_Cod
e
Bit 6
Bit 5
Primary
FL_Data
Secondary
Data
Secondary
Code
SRAM_Co
de
PIO_EN
0 =
PSEN
0 = RD
can’t
0 = PSEN
can’t
0 =
disable
0 = RD can’t
0 = PSEN can’t
can’t
not
not
access
Secondary
Flash memory
access
access
used
used
PIO
mode
access
Secondary
Flash memory
access
SRAM
Flash
memory
Flash
memory
1 =
PSEN
1=
enable
1 = RD
1 = PSEN
access
Secondary
Flash memory
1 = PSEN
1 = RD access
Secondary
Flash memory
not
used
not
used
access
Flash
memory
access
Flash
memory
access
SRAM
PIO
mode
21.10.3 Separate Space mode
Program space is separated from Data space. For example, Program Select Enable (PSEN)
is used to access the program code from the primary Flash memory, while READ Strobe
(RD) is used to access data from the secondary Flash memory, SRAM and I/O Port blocks.
This configuration requires the VM Register to be set to 0Ch (see Figure 50).
116/181
UPSD3212A, UPSD3212C, UPSD3212CV
Memory blocks
21.10.4 Combined Space modes
The Program and Data spaces are combined into one memory space that allows the
primary Flash memory, secondary Flash memory, and SRAM to be accessed by either
Program Select Enable (PSEN) or READ Strobe (RD). For example, to configure the
primary Flash memory in Combined space, Bits b2 and b4 of the VM Register are set to '1'
(see Figure 51).
Figure 50. Separate Space mode
Primary
Flash
Secondary
Flash
SRAM
DPLD
RS0
Memory
Memory
CSBOOT0-1
FS0-FS3
CS
CS
OE
CS
OE
OE
PSEN
RD
AI07433
Figure 51. Combined Space mode
Primary
Flash
Secondary
Flash
SRAM
DPLD
RS0
Memory
Memory
RD
CSBOOT0-1
FS0-FS3
CS
CS
OE
CS
OE
OE
VM REG BIT
M REG BIT 4
PSEN
VM REG BIT 1
RD
VM REG BIT 2
VM REG BIT 0
AI07434
21.11
Page register
The 8-bit Page Register increases the addressing capability of the MCU Core by a factor of
up to 256. The contents of the register can also be read by the MCU. The outputs of the
Page Register (PGR0-PGR7) are inputs to the DPLD decoder and can be included in the
Sector Select (FS0-FS7, CSBOOT0-CSBOOT3), and SRAM Select (RS0) equations.
If memory paging is not needed, or if not all 8 page register bits are needed for memory
paging, then these bits may be used in the CPLD for general logic.
117/181
Memory blocks
UPSD3212A, UPSD3212C, UPSD3212CV
Figure 52 shows the Page Register. The eight flip-flops in the register are connected to the
internal data bus D0-D7. The MCU can write to or read from the Page Register. The Page
Register can be accessed at address location CSIOP + E0h.
Figure 52. Page register
RESET
PGR0
INTERNAL PSD MODULE
SELECTS
AND LOGIC
D0
D1
D2
D3
D4
D5
D6
D7
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
PGR1
PGR2
PGR3
PGR4
PGR5
PGR6
PGR7
D0 - D7
DPLD
AND
CPLD
R/W
PAGE
REGISTER
PLD
AI05799
118/181
UPSD3212A, UPSD3212C, UPSD3212CV
PLDs
22
PLDs
PLDs bring programmable logic functionality to the UPSD. After specifying the logic for the
PLDs using PSDsoft Express, the logic is programmed into the device and available upon
Power-up.
Table 87. DPLD and CPLD Inputs
Input Source
MCU Address Bus
Number of
Signals
Input Name
A15-A0
16
4
1
1
8
8
4
2
8
8
8
1
MCU Control Signals
RESET
PSEN, RD, WR, ALE
RST
Power-down
PDN
Port A Input Macrocells(1)
Port B Input Macrocells
Port C Input Macrocells
Port D Inputs
PA7-PA0
PB7-PB0
PC2-4, PC7
PD2-PD1
Page Register
PGR7-P0
MLLAB.FB7-FB0
MCELLBC.FB7-FB0
Ready/Busy
Macrocell AB Feedback
Macrocell BC Feedback
Flash memory Program Status bit
Note: 1. These inputs are not available in the 52-pin package.
The PSD module contains two PLDs: the Decode PLD (DPLD), and the Complex PLD
(CPLD). The PLs are briefly discussed in the next few paragraphs, and in more detail in
Section 22.2ecode PLD (DPLD), and Section 22.3: Complex PLD (CPLD). Figure 53
shows e configuration of the PLDs.
ThDPLD performs address decoding for Select signals for PSD module components, such
as memory, registers, and I/O ports.
The CPLD can be used for logic functions, such as loadable counters and shift registers,
state machines, and encoding and decoding logic. These logic functions can be constructed
using the Output Macrocells (OMC), Input Macrocells (IMC), and the AND Array. The CPLD
can also be used to generate External Chip Select (ECS1-ECS2) signals.
The AND Array is used to form product terms. These product terms are specified using
PSDsoft. The PLD input signals consist of internal MCU signals and external inputs from the
I/O ports. The input signals are shown in Table 87.
22.1
Turbo bit in PSD module
The PLDs can minimize power consumption by switching off when inputs remain unchanged
for an extended time of about 70ns. Resetting the Turbo bit to '0' (Bit 3 of PMMR0)
automatically places the PLDs into standby if no inputs are changing. Turning the Turbo
mode off increases propagation delays while reducing power consumption.
119/181
PLDs
UPSD3212A, UPSD3212C, UPSD3212CV
See Section 24: Power management for details on how to set the Turbo Bit.
Additionally, five bits are available in PMMR2 to block MCU control signals from entering the
PLDs. This reduces power consumption and can be used only when these MCU control
signals are not used in PLD logic equations.
Each of the two PLDs has unique characteristics suited for its applications. They are
described in the following sections.
Figure 53. PLD diagram
8
PAGE
REGISTER
DATA
BUS
DECODE PLD
8
73
PRIMARY FLASH MEMORY SELECTS
4
1
1
2
SECONDARY NON-VOLATILE MEMORY SELECTS
SRAM SELECT
CSIOP SELECT
PERIPHERAL SELECTS
OUTPUT MACROCELL FEEDBACK
CPLD
IRECT MACROCELL ACCESS FROM MCU DATA BUS
MCELLAB
16
16 OUTPUT
ACROCELL
1
TO PORT A OR B
8
MACROCELL
ALLOC.
P
ALL
73
MCELLBC
TO PORT B OR C
8
2
20 INPUT MACROCELL
(PORT A,B,C)
EXTERNAL CHIP SELECTS
TO PORT D
DIRECT MACROCELL INPUT TO MCU DATA BUS
INPUT MACROCELL & INPUT PORTS
PORT D INPUTS
0
2
AI06600
1. Port A is not available in the 52-pin package
22.2
Decode PLD (DPLD)
The DPLD, shown in Figure 88, is used for decoding the address for PSD module and
external components. The DPLD can be used to generate the following decode signals:
●
4 Sector Select (FS0-FS3) signals for the primary Flash memory (three product terms
each)
●
2 Sector Select (CSBOOT0-CSBOOT1) signals for the secondary Flash memory (three
product terms each)
●
●
●
1 internal SRAM Select (RS0) signal (two product terms)
1 internal CSIOP Select signal (selects the PSD module registers)
2 internal Peripheral Select signals (Peripheral I/O mode).
120/181
UPSD3212A, UPSD3212C, UPSD3212CV
Table 88. DPLD logic array
PLDs
CSBOOT 0
CSBOOT 1
3
3
(INPUTS)
1
3
3
3
3
FS0
I/O PORTS (PORT A,B,C)
(20)
FS1
FS2
4 PRIMARY FLASH
MEMORY SECTOR
SELECTS
(8)
MCELLAB.FB [7:0] (FEEDBACKS)
MCELLBC.FB [7:0] (FEEDBACKS)
(8)
(8)
FS3
PGR0 -PGR7
2
(16)
(2)
[
]
A 15:0
[
]
PD 2:1
PDN (APD OUTPUT)
(1)
(4)
(1)
(1)
2
PSEN, RD, WR, ALE
2
RESET
RS0
2
1
SRAM SELECT
RD_BSY
CSIOP
PSEL0
PSEL1
I/O DECODER
SELECT
1
1
PERIPHERAL I/O
MODE SELECT
AI07436
1. Port A inputs are not available in the 52-pin package
2. Inputs from the MCU module
22.3
Complex PD (CPLD)
The CPD can be used to implement system logic functions, such as loadable counters and
shift registers, system mailboxes, handshaking protocols, state machines, and random logic.
ThCPLD can also be used to generate External Chip Select (ECS1-ECS2), routed to Port
D.
Although External Chip Select (ECS1-ECS2) can be produced by any Output Macrocell
(OMC), these External Chip Select (ECS1-ECS2) on Port D do not consume any Output
Macrocells (OMC).
As shown in Figure 54, the CPLD has the following blocks:
●
●
●
●
●
●
20 Input Macrocells (IMC)
16 Output Macrocells (OMC)
Macrocell Allocator
Product Term Allocator
AND Array capable of generating up to 137 product terms
Four I/O Ports.
Each of the blocks are described in the sections that follow.
121/181
PLDs
UPSD3212A, UPSD3212C, UPSD3212CV
The Input Macrocells (IMC) and Output Macrocells (OMC) are connected to the PSD
module internal data bus and can be directly accessed by the MCU. This enables the MCU
software to load data into the Output Macrocells (OMC) or read data from both the Input and
Output Macrocells (IMC and OMC).
This feature allows efficient implementation of system logic and eliminates the need to
connect the data bus to the AND Array as required in most standard PLD macrocell
architectures.
Figure 54. Macrocell and I/O ports
PRODUCT TERMS
FROM OTHER
MACROCELLS
MCU ADDRESS / DATA BUS
TO OTHER I/O PORTS
CPLD MACROCELLS
I/O PORTS
DATA
LOAD
CONTROL
LATCHED
ADDRESS OUT
PT PRESET
MCU DATA IN
MCU LOAD
PRODUCT TERM
ALLOCATOR
I/O PIN
DATA
D
Q
MUX
WR
UP TO 10
PRODUCT TERMS
MACROCELL
OUT TO
MCU
CPLD OUTPUT
POLARITY
SELECT
PR DI LD
D/T
SELECT
Q
PT
CPLD
OUTPUT
PDR
CLOCK
INPUT
D/T/JK FF
SELECT
COMB.
/REG
SELECT
GLOBAL
CLOCK
MACROCELL
CK
TO
I/O PORT
ALOC
CL
CLOCK
SELECT
Q
DIR
REG.
D
WR
PT CLEAR
(
)
PT OUTPUT ENABLE OE
MACROCELL FEEDBACK
I/O PORT INPUT
INPUT MACROCELLS
Q
Q
D
PT INPUT LATCH GATE/CLOCK
D
G
ALE
AI06602
22.4
Output macrocell (OMC)
Eight of the Output Macrocells (OMC) are connected to Ports A and B pins and are named
as McellAB0-McellAB7. The other eight macrocells are connected to Ports B and C pins and
are named as McellBC0-McellBC7. If an McellAB output is not assigned to a specific pin in
PSDsoft, the Macrocell Allocator block assigns it to either Port A or B. The same is true for a
McellBC output on Port B or C. Table 89 shows the macrocells and port assignment.
The Output Macrocell (OMC) architecture is shown in Figure 55. As shown in the figure,
there are native product terms available from the AND Array, and borrowed product terms
available (if unused) from other Output Macrocells (OMC). The polarity of the product term
is controlled by the XOR gate. The Output Macrocell (OMC) can implement either sequential
logic, using the flip-flop element, or combinatorial logic. The multiplexer selects between the
sequential or combinatorial logic outputs. The multiplexer output can drive a port pin and
has a feedback path to the AND Array inputs.
The flip-flop in the Output Macrocell (OMC) block can be configured as a D, T, JK, or SR
type in PSDsoft. The flip-flop’s clock, preset, and clear inputs may be driven from a product
term of the AND Array. Alternatively, CLKIN (PD1) can be used for the clock input to the flip-
122/181
UPSD3212A, UPSD3212C, UPSD3212CV
PLDs
flop. The flip-flop is clocked on the rising edge of CLKIN (PD1). The preset and clear are
active High inputs. Each clear input can use up to two product terms.
Table 89. Output macrocell port and data bit assignments
Port
Output
Native Product
Terms
Max. Borrowed
Product Terms
Data Bit for
Loading or Reading
Assignment
Macrocell
(1,2)
McellAB0
McellAB1
McellAB2
McellAB3
McellAB4
McellAB5
McellAB6
McellAB7
McellBC0
McellBC1
McellBC2
McellBC3
McellBC4
McellBC5
McellBC6
McellBC7
Port A0, B0
Port A1, B1
Port A2, B2
Port A3, B3
Port A4, B4
Port A5, B5
Port A6, B6
Port A7, B7
Port B0
3
3
3
3
3
3
3
3
4
4
4
4
4
4
4
6
6
6
6
6
6
6
6
5
5
5
5
6
6
6
6
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
Port B1
Port B2, C2
Port B3, C3
Port B4, C4
Port B5
Port B6
Port B7, C7
1. McellAB0-Mcell7 can only be assigned to Port B in the 52-pin package
2. Port PC0, P, PC5, and PC6 are assigned to JTAG pins and are not available as Macrocell outputs.
22.5
Product term allocator
The CPLD has a Product Term Allocator. PSDsoft uses the Product Term Allocator to
borrow and place product terms from one macrocell to another. The following list
summarizes how product terms are allocated:
●
●
●
McellAB0-McellAB7 all have three native product terms and may borrow up to six more
McellBC0-McellBC3 all have four native product terms and may borrow up to five more
McellBC4-McellBC7 all have four native product terms and may borrow up to six more.
Each macrocell may only borrow product terms from certain other macrocells. Product
terms already in use by one macrocell are not available for another macrocell.
If an equation requires more product terms than are available to it, then “external” product
terms are required, which consume other Output Macrocells (OMC). If external product
terms are used, extra delay is added for the equation that required the extra product terms.
This is called product term expansion. PSDsoft Express performs this expansion as needed.
123/181
PLDs
UPSD3212A, UPSD3212C, UPSD3212CV
22.5.1
Loading and Reading the Output Macrocells (OMC)
The Output Macrocells (OMC) block occupies a memory location in the MCU address
space, as defined by the CSIOP block (see Section 23: I/O ports (PSD module)). The flip-
flops in each of the 16 Output Macrocells (OMC) can be loaded from the data bus by a
MCU. Loading the Output Macrocells (OMC) with data from the MCU takes priority over
internal functions. As such, the preset, clear, and clock inputs to the flip-flop can be
overridden by the MCU. The ability to load the flip-flops and read them back is useful in such
applications as loadable counters and shift registers, mailboxes, and handshaking protocols.
Data can be loaded to the Output Macrocells (OMC) on the trailing edge of WRITE Strobe
(WR, edge loading) or during the time that WRITE Strobe (WR) is active (level loading). The
method of loading is specified in PSDsoft Express Configuration.
Figure 55. CPLD output macrocell
MASK
REG.
MACROCELL CS
MCU DATA BUS
[
]
7:0
D
RD
WR
PT
DIRECTION
REGISTER
ALLOCATOR
(
)
ENABLE .OE
(
)
PRESET .PR
MB/REG
SELECT
PT
PT
DIN PR
LD
MUX
I/O PIN
MACROCELL
ALLOCATOR
Q
PT
POLARITY
SELECT
IN
PORT
DRIVER
CLR
PROGRAMMABLE
(
)
CLEAR .RE
(
)
FF D/T/JK/SR
PT CLK
CLKIN
MUX
(
)
FEEDBACK .FB
PORT INPUT
INPUT
MACROCELL
AI06617
22.5.2
OMC mask register
There is one Mask Register for each of the two groups of eight Output Macrocells (OMC).
The Mask Registers can be used to block the loading of data to individual Output Macrocells
(OMC). The default value for the Mask Registers is 00h, which allows loading of the Output
Macrocells (OMC). When a given bit in a Mask Register is set to a '1,' the MCU is blocked
from writing to the associated Output Macrocells (OMC). For example, suppose McellAB0-
McellAB3 are being used for a state machine. You would not want a MCU write to McellAB
to overwrite the state machine registers. Therefore, you would want to load the Mask
Register for McellAB (Mask Macrocell AB) with the value 0Fh.
22.5.3
Output enable of the OMC
The Output Macrocells (OMC) block can be connected to an I/O port pin as a PLD output.
The output enable of each port pin driver is controlled by a single product term from the
124/181
UPSD3212A, UPSD3212C, UPSD3212CV
PLDs
AND Array, ORed with the Direction Register output. The pin is enabled upon Power-up if no
output enable equation is defined and if the pin is declared as a PLD output in PSDsoft
Express.
If the Output Macrocell (OMC) output is declared as an internal node and not as a port pin
output in the PSDabel file, the port pin can be used for other I/O functions. The internal node
feedback can be routed as an input to the AND Array.
22.6
Input macrocells (IMC)
The CPLD has 20 Input Macrocells (IMC), one for each pin on Ports A and B, and 4 on Port
C. The architecture of the Input Macrocells (IMC) is shown in Figure 56. The Input
Macrocells (IMC) are individually configurable, and can be used as a latch, register, or to
pass incoming Port signals prior to driving them onto the PLD input bus. The outputs of the
Input Macrocells (IMC) can be read by the MCU through the internal data bus.
The enable for the latch and clock for the register are driven by a multiplexer whose inputs
are a product term from the CPLD AND Array or the MCU Address Stre (ALE). Each
product term output is used to latch or clock four Input Macrocells (IMC). Port inputs 3-0 can
be controlled by one product term and 7-4 by another.
Configurations for the Input Macrocells (IMC) are specified by equations written in PSDsoft
(see Application Note AN1171). Outputs of the Input Macrocells (IMC) can be read by the
MCU via the IMC buffer.
See Section 23: I/O ports (PSD module).
Figure 56. Input macrocell
MCU DATA BUS
[
]
7:0
D
_
INPUT MACROCELL RD
DIRECTION
REGISTER
(
)
ENABLE .OE
OUTPUT
MACROCELLS BC
PT
AND
MACROCELL AB
I/O PIN
PT
PORT
DRIVER
MUX
Q
D
PT
ALE
MUX
D FF
Q
D
G
FEEDBACK
LATCH
INPUT MACROCELL
AI06603
125/181
I/O ports (PSD module)
UPSD3212A, UPSD3212C, UPSD3212CV
23
I/O ports (PSD module)
There are four programmable I/O ports: Ports A, B, C, and D in the PSD module. Each of the
ports is eight bits except Port D, which is 3 bits. Each port pin is individually user
configurable, thus allowing multiple functions per port. The ports are configured using
PSDsoft Express Configuration or by the MCU writing to on-chip registers in the CSIOP
space. Port A is not available in the 52-pin package.
The topics discussed in this section are:
●
●
●
●
●
General Port architecture
Port operating modes
Port Configuration Registers (PCR)
Port Data Registers
Individual Port functionality.
23.1
General port architecture
The general architecture of the I/O Port block is shown in igure 57. Individual Port
architectures are shown in Figure 59 to Figure 62. In general, once the purpose for a port
pin has been defined, that pin is no longer available for other purposes. Exceptions are
noted.
As shown in Figure 57, the ports contan output multiplexer whose select signals are
driven by the configuration bits in the Control Registers (Ports A and B only) and PSDsoft
Express Configuration. Inputs to the multiplexer include the following:
●
●
●
●
Output data from the Data Out register
Latched address outputs
CPLD macrocell output
Externahip Select (ECS1-ECS2) from the CPLD.
The Pot Data Buffer (PDB) is a tri-state buffer that allows only one source at a time to be
read. The Port Data Buffer (PDB) is connected to the Internal Data Bus for feedback and
can be read by the MCU. The Data Out and macrocell outputs, Direction and Control
Registers, and port pin input are all connected to the Port Data Buffer (PDB).
126/181
UPSD3212A, UPSD3212C, UPSD3212CV
Figure 57. General I/O port architecture
I/O ports (PSD module)
DATA OUT
REG.
DATA OUT
ADDRESS
D
Q
WR
ADDRESS
ALE
PORT PIN
D
G
Q
OUTPUT
MUX
MACROCELL OUTPUTS
EXT CS
READ MUX
P
D
B
OUTPUT
SELECT
DATA IN
CONTROL REG.
ENABLE OUT
D
Q
WR
WR
DIR REG.
D
Q
(
)
ENABLE PRODUCT TERM .OE
INPUT
MACROCELL
CPLD-INPUT
AI06604
The Port pin’s tri-state output driver enable controlled by a two input OR gate whose
inputs come from the CPLD AND Arranable product term and the Direction Register. If
the enable product term of any of the Array outputs are not defined and that port pin is not
defined as a CPLD output in the PSDsoft, then the Direction Register has sole control of the
buffer that drives the port pin.
The contents of these registers can be altered by the MCU. The Port Data Buffer (PDB)
feedback path alows the MCU to check the contents of the registers.
Ports A, B, aC have embedded Input Macrocells (IMC). The Input Macrocells (IMC) can
be congured as latches, registers, or direct inputs to the PLDs. The latches and registers
are clocked by Address Strobe (ALE) or a product term from the PLD AND Array. The
outputs from the Input Macrocells (IMC) drive the PLD input bus and can be read by the
MCU. See Figure 56.
23.2
Port operating modes
The I/O Ports have several modes of operation. Some modes can be defined using PSDsoft,
some by the MCU writing to the Control Registers in CSIOP space, and some by both. The
modes that can only be defined using PSDsoft must be programmed into the device and
cannot be changed unless the device is reprogrammed. The modes that can be changed by
the MCU can be done so dynamically at run-time. The PLD I/O, Data Port, Address Input,
and Peripheral I/O modes are the only modes that must be defined before programming the
device. All other modes can be changed by the MCU at run-time. See Application Note
AN1171 for more detail.
Table 90 summarizes which modes are available on each port. Table 93 shows how and
where the different modes are configured. Each of the port operating modes are described
in the following sections.
127/181
I/O ports (PSD module)
UPSD3212A, UPSD3212C, UPSD3212CV
23.3
MCU I/O mode
In the MCU I/O mode, the MCU uses the I/O Ports block to expand its own I/O ports. By
setting up the CSIOP space, the ports on the PSD module are mapped into the MCU
address space. The addresses of the ports are listed in Table 81.
A port pin can be put into MCU I/O mode by writing a '0' to the corresponding bit in the
Control Register. The MCU I/O direction may be changed by writing to the corresponding bit
in the Direction Register, or by the output enable product term. See Section 23.6: Peripheral
I/O mode. When the pin is configured as an output, the content of the Data Out Register
drives the pin. When configured as an input, the MCU can read the port input through the
Data In buffer. See Figure 57.
Ports C and D do not have Control Registers, and are in MCU I/O mode by default. They can
be used for PLD I/O if equations are written for them in PSDabel.
23.4
PLD I/O mode
The PLD I/O mode uses a port as an input to the CPLD’s Input Macrcells (IMC), and/or as
an output from the CPLD’s Output Macrocells (OMC). The outut can be tri-stated with a
control signal. This output enable control signal can be deined by a product term from the
PLD, or by resetting the corresponding bit in the Direction Register to '0.' The corresponding
bit in the Direction Register must not be set to '1' if the pin is defined for a PLD input signal in
PSDsoft. The PLD I/O mode is specified in PSDsft by declaring the port pins, and then
writing an equation assigning the PLD I/O a port.
23.5
23.6
Address Out mode
Address Out mode can be used to drive latched MCU addresses on to the port pins. These
port pins can, in turn, drive external devices. Either the output enable or the corresponding
bits of both the ection Register and Control Register must be set to a '1' for pins to use
Address Out ode. This must be done by the MCU at run-time. See Table 92 for the
addresoutput pin assignments on Ports A and B for various MCUs.
Peripheral I/O mode
Peripheral I/O mode can be used to interface with external peripherals. In this mode, all of
Port A serves as a tri-state, bi-directional data buffer for the MCU. Peripheral I/O mode is
enabled by setting Bit 7 of the VM Register to a '1.' Figure 58 shows how Port A acts as a bi-
directional buffer for the MCU data bus if Peripheral I/O mode is enabled. An equation for
PSEL0 and/or PSEL1 must be written in PSDsoft. The buffer is tri-stated when PSEL0 or
PSEL1 is low (not active). The PSEN signal should be “ANDed” in the PSEL equations to
disable the buffer when PSEL resides in the data space.
23.7
JTAG in-system programming (ISP)
Port C is JTAG compliant, and can be used for In-System Programming (ISP). For more
information on the JTAG Port, see Section 26: Programming in-circuit using the JTAG serial
interface.
128/181
UPSD3212A, UPSD3212C, UPSD3212CV
Figure 58. Peripheral I/O mode
I/O ports (PSD module)
RD
PSEL0
PSEL
PSEL1
D0-D7
VM REGISTER BIT 7
PA0-PA7
DATA BUS
WR
AI02886
Table 90. Port operating modes
Port mode
MCU I/O
Port A(1)
Port B
Port C
Port D
Yes
Yes
Yes
Yes
PLD I/O
McellAB Outputs
McellBC Outputs
Yes
No
No
Yes
Yes
No
No
Yes(2)
No
No
No
Additional Ext. CS
Outputs
Yes
PLD Inputs
Address Out
Peripheral I/O
JTAG ISP
Yes
Yes
Yes (A7 – 0)
No
Yes
No
Yes
No
No
No
Yes (A7 – 0)
Yes
No
No
Yes(3)
No
1. Port A is not available in the 52-pin package.
2. On pins PC2, PC3, PC4, and PC7 only.
3. JTAG pins (TMS, TCK, TDI, TDO) are dedicated pins.
Table 91. Port operating mode settings
Control
Direction
VM Register
Setting(1)
Mode
Defined in PSDsoft
Register
Register
Setting(1)
Setting(1)
1 = output,
MCU I/O
Declare pins only
Logic equations
Declare pins only
0
N/A
N/A
N/A
0 = input (Note 2)
(Note 2)
PLD I/O
N/A
1
Address Out
(Port A,B)
1 (Note 2)
N/A
Logic equations
(PSEL0 & 1)
Peripheral I/O
(Port A)
N/A
PIO Bit = 1
1. N/A = Not Applicable
2. The direction of the Port A,B,C, and D pins are controlled by the Direction Register ORed with the
individual output enable product term (.oe) from the CPLD AND Array.
Table 92. I/O port latched address output assignments
Port A (PA3-PA0)
Port A (PA7-PA4)
Port B (PB3-PB0)
Port B (PB7-PB4)
Address a3-a0
Address a7-a4
Address a3-a0
Address a7-a4
129/181
I/O ports (PSD module)
UPSD3212A, UPSD3212C, UPSD3212CV
23.8
Port configuration registers (PCR)
Each Port has a set of Port Configuration Registers (PCR) used for configuration. The
contents of the registers can be accessed by the MCU through normal READ/WRITE bus
cycles at the addresses given in Table 81. The addresses in Table 81 are the offsets in
hexadecimal from the base of the CSIOP register.
The pins of a port are individually configurable and each bit in the register controls its
respective pin. For example, Bit 0 in a register refers to Bit 0 of its port. The three Port
Configuration Registers (PCR), shown in Table 93, are used for setting the Port
configurations. The default Power-up state for each register in Table 93 is 00h.
23.8.1
23.8.2
Control register
Any bit reset to '0' in the Control Register sets the corresponding port pin to MCU I/O mode,
and a '1' sets it to Address Out mode. The default mode is MCU I/O. Only Ports A and B
have an associated Control Register.
Direction register
The Direction Register, in conjunction with the output enable (except for Port D), controls the
direction of data flow in the I/O Ports. Any bit set to '1' in te Direction Register causes the
corresponding pin to be an output, and any bit set to 0' causes it to be an input. The default
mode for all port pins is input.
Figure 59 and Figure 60 show the Port Arctecture diagrams for Ports A/B and C,
respectively. The direction of data flow Ports A, B, and C are controlled not only by the
direction register, but also by the output enable product term from the PLD AND Array. If the
output enable product term is not active, the Direction Register has sole control of a given
pin’s direction.
An example of a configuration for a Port with the three least significant bits set to output and
the remainder seto input is shown in Table 96. Since Port D only contains two pins (shown
in Figure 62), he Direction Register for Port D has only two bits active.
23.8.3
Drive Select register
The Drive Select Register configures the pin driver as Open Drain or CMOS for some port
pins, and controls the slew rate for the other port pins. An external pull-up resistor should be
used for pins configured as Open Drain.
A pin can be configured as Open Drain if its corresponding bit in the Drive Select Register is
set to a '1.' The default pin drive is CMOS.
Note:
The slew rate is a measurement of the rise and fall times of an output. A higher slew rate
means a faster output response and may create more electrical noise. A pin operates in a
high slew rate when the corresponding bit in the Drive Register is set to '1.' The default rate
is slow slew.
Table 97 shows the Drive Register for Ports A, B, C, and D. It summarizes which pins can be
configured as Open Drain outputs and which pins the slew rate can be set for.
130/181
UPSD3212A, UPSD3212C, UPSD3212CV
I/O ports (PSD module)
MCU Access
Table 93. Port configuration registers (PCR)
Register Name Port
Control
A,B
WRITE/READ
Direction
A,B,C,D
A,B,C,D
WRITE/READ
WRITE/READ
Drive Select(1)
Note: 1. See Table 97 for Drive Register Bit definition.
Table 94. Port pin direction control, output enable P.T. not defined
Direction Register Bit
Port Pin mode
0
1
Input
Output
Table 95. Port pin direction control, output enable P.T. defined
Direction Register Bit
Output Enable P.T.
Pt Pin mode
0
0
1
1
0
1
0
1
Input
Output
Output
Output
Table 96. Port direction assignmexample
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
0
0
0
1
1
1
23.9
Port data registers
The Pot Data Registers, shown in Table 98, are used by the MCU to write data to or read
daa from the ports. Table 98 shows the register name, the ports having each register type,
and MCU access for each register type. The registers are described below.
23.9.1
23.9.2
Data In
Port pins are connected directly to the Data In buffer. In MCU I/O Input mode, the pin input is
read through the Data In buffer.
Data Out register
Stores output data written by the MCU in the MCU I/O Output mode. The contents of the
Register are driven out to the pins if the Direction Register or the output enable product term
is set to '1.' The contents of the register can also be read back by the MCU.
23.9.3
Output macrocells (OMC)
The CPLD Output Macrocells (OMC) occupy a location in the MCU’s address space. The
MCU can read the output of the Output Macrocells (OMC). If the OMC Mask Register Bits
131/181
I/O ports (PSD module)
UPSD3212A, UPSD3212C, UPSD3212CV
are not set, writing to the macrocell loads data to the macrocell flip-flops. See Section 22:
PLDs.
23.9.4
23.9.5
23.9.6
OMC mask register
Each OMC Mask Register Bit corresponds to an Output Macrocell (OMC) flip-flop. When the
OMC Mask Register Bit is set to a '1,' loading data into the Output Macrocell (OMC) flip-flop
is blocked. The default value is '0' or unblocked.
Input macrocells (IMC)
The Input Macrocells (IMC) can be used to latch or store external inputs. The outputs of the
Input Macrocells (IMC) are routed to the PLD input bus, and can be read by the MCU. See
Section 22: PLDs.
Enable out
The Enable Out register can be read by the MCU. It contains the outpunable values for a
given port. A '1' indicates the driver is in output mode. A '0' indicates he driver is in tri-state
and the pin is in input mode.
Table 97. Drive register pin assignment
Drive
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register
Open
Drain
Open
Drain
Ope
Drain
Open
Drain
Slew
Rate
Slew
Rate
Slew
Rate
Slew
Rate
Port A
Open
Drain
Open
Drain
Open
Drain
Open
Drain
Slew
Rate
Slew
Rate
Slew
Rate
Slew
Rate
Port B
Port C
Port D
Open
Drai
Open
Drain
Open
Drain
Open
Drain
NA(1)
NA(1)
NA(1)
NA(1)
NA(1)
NA(1)
NA(1)
Slew
Rate
Slew
Rate
NA(1)
NA(1)
NA(1)
1. NA = Not Applicable.
Table 98. Port data registers
Register Name Port
Data In A,B,C,D
MCU Access
READ – input on pin
WRITE/READ
Data Out
A,B,C,D
READ – outputs of macrocells
Output Macrocell
A,B,C
WRITE – loading macrocells flip-flop
WRITE/READ – prevents loading into a given
macrocell
Mask Macrocell
A,B,C
Input Macrocell
Enable Out
A,B,C
A,B,C
READ – outputs of the Input Macrocells
READ – the output enable control of the port driver
132/181
UPSD3212A, UPSD3212C, UPSD3212CV
I/O ports (PSD module)
23.10
Ports A and B – functionality and structure
Ports A and B have similar functionality and structure, as shown in Figure 59. The two ports
can be configured to perform one or more of the following functions:
●
MCU I/O mode
●
CPLD Output – Macrocells McellAB7-McellAB0 can be connected to Port A or Port B.
McellBC7-McellBC0 can be connected to Port B or Port C.
●
●
●
CPLD Input – Via the Input Macrocells (IMC).
Latched Address output – Provide latched address output as per Table 92.
Open Drain/Slew Rate – pins PA3-PA0 and PB3-PB0 can be configured to fast slew
rate, pins PA7-PA4 and PB7-PB4 can be configured to Open Drain mode.
●
Peripheral mode – Port A only (80-pin package)
Figure 59. Port A and Port B structure
DATA OUT
REG.
DATA OUT
D
Q
WR
PORT
A OR B PIN
ADDRESS
ALE
ADDRESS
D
G
Q
[
A
]
7:0
OPUT
MUX
MACROCELL OUTPUTS
READ MUX
P
D
B
OUTPUT
SELECT
DATA IN
CONTROL REG.
ENABLE OUT
D
Q
WR
DIR REG.
D
Q
(
)
ENABLE PRODUCT TERM .OE
CPLD-INPUT
INPUT
MACROCELL
AI06605
23.11
Port C – functionality and structure
Port C can be configured to perform one or more of the following functions (see Figure 60):
●
●
●
●
MCU I/O mode
CPLD Output – McellBC7-McellBC0 outputs can be connected to Port B or Port C.
CPLD Input – via the Input Macrocells (IMC)
In-System Programming (ISP) – JTAG pins (TMS, TCK, TDI, TDO) are dedicated pins
for device programming. (See Section 26: Programming in-circuit using the JTAG serial
interface, for more information on JTAG programming.)
●
Open Drain – Port C pins can be configured in Open Drain mode
Port C does not support Address Out mode, and therefore no Control Register is required.
133/181
I/O ports (PSD module)
UPSD3212A, UPSD3212C, UPSD3212CV
Figure 60. Port C structure
DATA OUT
REG.
DATA OUT
D
Q
WR
PORT C PIN
1
SPECIAL FUNCTION
OUTPUT
MUX
[
]
MCELLBC 7:0
READ MUX
P
D
B
OUTPUT
SELECT
DATA IN
ENABLE OUT
DIR REG.
D
Q
WR
(
)
ENABLE PRODUCT TERM .OE
INPUT
MACROCELL
SPECIAL FUNC
CPLD-INPUT
CONFIGURATION
BIT
AI06618
Note: 1. ISP
23.12
Port D – functionality and structure
Port D has two I/O pins (only one pin, PD1, in the 52-pin package). See Figure 61 and
Figure 62. This port does not support Address Out mode, and therefore no Control Register
is required. Of the eight bits in the Port D registers, only Bits 2 and 1 are used to configure
pins PD2 and PD1.
Port D can be configured to perform one or more of the following functions:
●
●
●
●
MCU I/O mode
CD Output – External Chip Select (ECS1-ECS2)
CPLD Input – direct input to the CPLD, no Input Macrocells (IMC)
Slew rate – pins can be set up for fast slew rate
Port D pins can be configured in PSDsoft Express as input pins for other dedicated
functions:
●
CLKIN (PD1) as input to the macrocells flip-flops and APD counter
●
PSD Chip Select Input (CSI, PD2). Driving this signal High disables the Flash memory,
SRAM and CSIOP.
134/181
UPSD3212A, UPSD3212C, UPSD3212CV
Figure 61. Port D structure
I/O ports (PSD module)
DATA OUT
REG.
DATA OUT
D
Q
WR
PORT D PIN
OUTPUT
MUX
[
]
ECS 2:1
READ MUX
OUTPUT
SELECT
P
D
B
DATA IN
ENABLE PRODUCT
TERM (.OE)
DIR REG.
D
Q
WR
CPLD-INPUT
AI06606
23.13
External chip select
The CPLD also provides two External Chip Select (ECS1-ECS2) outputs on Port D pins that
can be used to select external devices. Each External Chip Select (ECS1-ECS2) consists of
one product term that can be configured active High or Low. The output enable of the pin is
controlled by either the output enable product term or the Direction register. (See Figure 62.)
135/181
I/O ports (PSD module)
UPSD3212A, UPSD3212C, UPSD3212CV
Figure 62. Port D external chip select signals
ENABLE (.OE)
DIRECTION
REGISTER
PD1 PIN
ECS1
PT1
POLARITY
BIT
ENABLE (.OE)
DIRECTION
REGISTER
PD2 PIN
ECS
PT2
POLARITY
BIT
AI06607
136/181
UPSD3212A, UPSD3212C, UPSD3212CV
Power management
24
Power management
All PSD modules offer configurable power saving options. These options may be used
individually or in combinations, as follows:
●
The primary and secondary Flash memory, and SRAM blocks are built with power
management technology. In addition to using special silicon design methodology,
power management technology puts the memories into Standby mode when
address/data inputs are not changing (zero DC current). As soon as a transition occurs
on an input, the affected memory “wakes up,” changes and latches its outputs, then
goes back to standby. The designer does not have to do anything special to achieve
Memory Standby mode when no inputs are changing—it happens automatically.
●
●
The PLD sections can also achieve Standby mode when its inputs are not changing, as
described in the sections on the Power Management mode Registers (PMMR).
As with the Power Management mode, the Automatic Power Down (APD) block allows
the PSD module to reduce to Standby current automatically. The APD Unit can also
block MCU address/data signals from reaching the memories and LDs.
●
Built in logic monitors the Address Strobe of the MCU for ctivity. If there is no activity
for a certain time period (MCU is asleep), the APD Unit initiates Power-down mode (if
enabled). Once in Power-down mode, all address/daa signals are blocked from
reaching memory and PLDs, and the memories are deselected internally. This allows
the memory and PLDs to remain in Standby ode even if the address/data signals are
changing state externally (noise, other devices on the MCU bus, etc.). Keep in mind
that any unblocked PLD input sigs at are changing states keeps the PLD out of
Standby mode, but not the memors.
●
●
PSD Chip Select Input (CSI, PD2) can be used to disable the internal memories,
placing them in Standby mode even if inputs are changing. This feature does not block
any internal signals or disable the PLDs. This is a good alternative to using the APD
Unit. There is a slight penalty in memory access time when PSD Chip Select Input
(CSI, PD2) akes its initial transition from deselected to selected.
The PMRs can be written by the MCU at run-time to manage power. The PSD
mdule supports “blocking bits” in these registers that are set to block designated
signals from reaching both PLDs. Current consumption of the PLDs is directly related
to the composite frequency of the changes on their inputs (see Figure Figure 66 and
Figure 67). Significant power savings can be achieved by blocking signals that are not
used in DPLD or CPLD logic equations.
137/181
Power management
Figure 63. APD unit
UPSD3212A, UPSD3212C, UPSD3212CV
APD EN
PMMR0 BIT 1=1
TRANSITION
DETECTION
DISABLE BUS
INTERFACE
ALE
PD
CLR
APD
CSIOP SELECT
FLASH SELECT
COUNTER
RESET
EDGE
DETECT
PD
CSI
PLD
SRAM SELECT
POWER DOWN
CLKIN
(
)
PDN SELECT
DISABLE
FLASH/SRAM
AI06608
The PSD module has a Turbo Bit in PMMR0. This bit can be set to turn the Turbo mode off
(the default is with Turbo mode turned on). While Turbo mode is off, the PLDs can achieve
standby current when no PLD inputs are changing (zero DC current). Een when inputs do
change, significant power can be saved at lower frequencies (AC cuent), compared to
when Turbo mode is on. When the Turbo mode is on, there is significant DC current
component and the AC component is higher.
Automatic Power-down (APD) Unit and Powe-down mode
The APD Unit, shown in Figure 63, puts the PSD module into Power-down mode by
monitoring the activity of Address Strobe (E). If the APD Unit is enabled, as soon as
activity on Address Strobe (ALE) stopfour-bit counter starts counting. If Address Strobe
(ALE/AS, PD0) remains inactive for fifteen clock periods of CLKIN (PD1), Power-down
(PDN) goes High, and the PSD module enters Power-down mode, as discussed next.
Power-down mode
By default, if you enable the APD Unit, Power-down mode is automatically enabled. The
device enters ower-down mode if Address Strobe (ALE) remains inactive for fifteen periods
of CLK(PD1).
The following should be kept in mind when the PSD module is in Power-down mode:
●
If Address Strobe (ALE) starts pulsing again, the PSD module returns to normal
Operating mode. The PSD module also returns to normal Operating mode if either PSD
Chip Select Input (CSI, PD2) is Low or the RESET input is High.
●
●
The MCU address/data bus is blocked from all memory and PLDs.
Various signals can be blocked (prior to Power-down mode) from entering the PLDs by
setting the appropriate bits in the PMMR registers. The blocked signals include MCU
control signals and the common CLKIN (PD1).
Note:
Blocking CLKIN (PD1) from the PLDs does not block CLKIN (PD1) from the APD Unit.
●
All memories enter Standby mode and are drawing standby current. However, the PLD
and I/O ports blocks do not go into Standby mode because you don’t want to have to
wait for the logic and I/O to “wake-up” before their outputs can change. See Table 99 for
Power-down mode effects on PSD module ports.
●
Typical standby current is of the order of microamperes. These standby current values
assume that there are no transitions on any PLD input.
138/181
UPSD3212A, UPSD3212C, UPSD3212CV
Other power-saving options
Power management
The PSD module offers other reduced power saving options that are independent of the
Power-down mode. Except for the PSD Chip Select Input (CSI, PD2) features, they are
enabled by setting bits in PMMR0 and PMMR2.
Figure 64. Enable Power-down flowchart
RESET
Enable APD
Set PMMR0 Bit 1 = 1
OPTIONAL
Disable desired inputs to PLD
by setting PMMR0 bits 4 and 5
and PMMR2 bits 2 through 6.
ALE idle
for 15 CLKIN
clocks?
No
Yes
PSD Module in Power
Don Mode
AI06609
Table 99. Power-down mode’s effect on ports
Port Function
Pin Level
MCU I/O
No Change
PLD Out
No Change
Undefined
Tri-State
Address Out
Peripheral I/O
24.1
PLD power management
The power and speed of the PLDs are controlled by the Turbo Bit (Bit 3) in PMMR0. By
setting the bit to '1,' the Turbo mode is off and the PLDs consume the specified Standby
current when the inputs are not switching for an extended time of 70 ns. The propagation
delay time is increased by 10 ns (for a 5 V device) after the Turbo Bit is set to '1' (turned off)
when the inputs change at a composite frequency of less than 15MHz. When the Turbo Bit
is reset to '0' (turned on), the PLDs run at full power and speed. The Turbo Bit affects the
PLD’s DC power, AC power, and propagation delay. When the Turbo mode is off, the
UPSD321xx devices’ input clock frequency is reduced by 5 MHz from the maximum rated
clock frequency.
Blocking MCU control signals with the bits of PMMR2 can further reduce PLD AC power
consumption.
139/181
Power management
UPSD3212A, UPSD3212C, UPSD3212CV
24.2
PSD chip select input (CSI, PD2)
PD2 of Port D can be configured in PSDsoft Express as PSD Chip Select Input (CSI). When
Low, the signal selects and enables the PSD module Flash memory, SRAM, and I/O blocks
for READ or WRITE operations. A High on PSD Chip Select Input (CSI, PD2) disables the
Flash memory, and SRAM, and reduces power consumption. However, the PLD and I/O
signals remain operational when PSD Chip Select Input (CSI, PD2) is High.
24.3
Input clock
CLKIN (PD1) can be turned off, to the PLD to save AC power consumption. CLKIN (PD1) is
an input to the PLD AND Array and the Output Macrocells (OMC).
During Power-down mode, or, if CLKIN (PD1) is not being used as part of the PLD logic
equation, the clock should be disabled to save AC power. CLKIN (PD1) is disconnected from
the PLD AND Array or the Macrocells block by setting Bits 4 or 5 to a '1' in PMMR0.
24.4
Input control signals
The PSD module provides the option to turn off the MCU signals (WR, RD, PSEN, and
Address Strobe (ALE)) to the PLD to save AC power consumption. These control signals
are inputs to the PLD AND Array. During Power-dwn mode, or, if any of them are not being
used as part of the PLD logic equation, these control signals should be disabled to save AC
power. They are disconnected from thPLAND Array by setting Bits 2, 3, 4, 5, and 6 to a
'1' in PMMR2.
Table 100. Power management mode registers (PMMR0)
Bit 0
Bit 1 APD Enae
Bit 2
X
0
Not used, and should be set to zero.
Automatic Power-down (APD) is disabled.
Automatic Power-down (APD) is enabled.
Not used, and should be set to zero.
PLD Turbo mode is on
0 = off
1 = on
0
X
0 = on
PLD Turbo mode is off, saving power.
Bit 3 PLD Turbo
1 = off
0 = on
UPSD321xx devices operate at 5MHz below the maximum rated
clock frequency
CLKIN (PD1) input to the PLD AND Array is connected. Every
change of CLKIN (PD1) Powers-up the PLD when Turbo Bit is '0.'
PLD Array
Bit 4
clk
CLKIN (PD1) input to PLD AND Array is disconnected, saving
power.
1 = off
0 = on
1 = off
CLKIN (PD1) input to the PLD macrocells is connected.
PLD MCell
Bit 5
clk
CLKIN (PD1) input to PLD macrocells is disconnected, saving
power.
Bit 6
Bit 7
X
X
0
0
Not used, and should be set to zero.
Not used, and should be set to zero.
140/181
UPSD3212A, UPSD3212C, UPSD3212CV
Power management
Table 101. Power management mode registers (PMMR2)
Bit 0
Bit 1
X
X
0
Not used, and should be set to zero.
Not used, and should be set to zero.
0
0 = on
1 = off
0 = on
1 = off
0 = on
1 = off
0 = on
1 = off
0
WR input to the PLD AND Array is connected.
WR input to PLD AND Array is disconnected, saving power.
RD input to the PLD AND Array is connected.
RD input to PLD AND Array is disconnected, saving power.
PSEN input to the PLD AND Array is connected.
PSEN input to PLD AND Array is disconnected, saving power.
ALE input to the PLD AND Array is connected.
ALE input to PLD AND Array is disconnected, saving power.
Not used, and should be set to zero.
PLD Array
WR
Bit 2
Bit 3
Bit 4
Bit 5
PLD Array
RD
PLD Array
PSEN
PLD Array
ALE
Bit 6
Bit 7
X
X
0
Not used, and should be set to zero.
1. The bits of this register are cleared to zero following Power-up. SubsequeRESET pulses do not clear the
registers.
Table 102. APD counter operatio
APD Enable Bit
ALE Level
APD Counter
0
1
X
Not Counting
Not Counting
Pulsing
Counting (Generates PDN after 15
Clocks)
1
0 or 1
141/181
RESET timing and device status at reset
UPSD3212A, UPSD3212C, UPSD3212CV
25
RESET timing and device status at reset
Upon Power-up, the PSD module requires a Reset (RESET) pulse of duration t
after
NLNH-PO
V
is steady. During this period, the device loads internal configurations, clears some of
CC
the registers and sets the Flash memory into operating mode. After the rising edge of Reset
(RESET), the PSD module remains in the Reset mode for an additional period, t
the first memory access is allowed.
, before
OPR
The Flash memory is reset to the READ mode upon Power-up. Sector Select (FS0-FS3 and
CSBOOT0-CSBOOT1) must all be Low, WRITE Strobe (WR, CNTL0) High, during Power-
on RESET for maximum security of the data contents and to remove the possibility of a byte
being written on the first edge of WRITE Strobe (WR). Any Flash memory WRITE cycle
initiation is prevented automatically when V is below V
.
CC
LKO
25.1
25.2
Warm RESET
Once the device is up and running, the PSD module can be reset wa pulse of a much
shorter duration, t . The same t period is needed befoe the device is operational
NLNH
OPR
after a Warm RESET. Figure 65 shows the timing of the Power-up and Warm RESET.
I/O pin, register and PLD status at RESET
Table 103 shows the I/O pin, register PLD status during Power-on RESET, Warm
RESET, and Power-down mode. PLD outputs are always valid during Warm RESET, and
they are valid in Power-on RESET once the internal Configuration bits are loaded. This
loading is completed typically long before the V ramps up to operating level. Once the
CC
PLD is active, the state of the outputs are determined by the PLD equations.
Figure 65. Ret (RESET) timing
VCC(min)
VCC
t
NLNH
t
t
OPR
t
t
OPR
NLNH-PO
Power-On Reset
NLNH-A
Warm Reset
RESET
AI02866b
142/181
UPSD3212A, UPSD3212C, UPSD3212CV
RESET timing and device status at reset
Table 103. Status during Power-on RESET, Warm RESET and Power-down mode
Port Configuration
Power-On RESET
Warm RESET
Input mode
Power-down mode
MCU I/O
Input mode
Unchanged
Valid after internal PSD
configuration bits are
loaded
Depends on inputs to
PLD (addresses are
blocked in PD mode)
PLD Output
Valid
Address Out
Tri-stated
Tri-stated
Tri-stated
Tri-stated
Not defined
Tri-stated
Peripheral I/O
Register
Power-On RESET
Warm RESET
Unchanged
Power-down mode
PMMR0 and PMMR2
Cleared to '0'
Unchanged
Cleared to '0' by
internal Power-on
RESET
Macrocells flip-flop
status
Depends on .re and .pr Depends on .re and .pr
equations
eations
Initialized, based on the Initialized, based the
VM Register(1)
selection in PSDsoft
Configuration menu
selection in PSDsoft
Configuration menu
Unchanged
Unchanged
All other registers
Cleared to '0'
Cleared to '0'
1. The SR_cod and Periphmode Bits in the VM Regiter are always cleared to '0' on Power-on RESET or
Warm RESET.
143/181
Programming in-circuit using the JTAG serial interface UPSD3212A, UPSD3212C, UPSD3212CV
26
Programming in-circuit using the JTAG serial
interface
The JTAG Serial Interface pins (TMS, TCK, TDI, and TDO) are dedicated pins on Port C
(see Table 104). All memory blocks (primary and secondary Flash memory), PLD logic, and
PSD module Configuration Register Bits may be programmed through the JTAG Serial
Interface block. A blank device can be mounted on a printed circuit board and programmed
using JTAG.
The standard JTAG signals (IEEE 1149.1) are TMS, TCK, TDI, and TDO. Two additional
signals, TSTAT and TERR, are optional JTAG extensions used to speed up Program and
Erase cycles.
By default, on a blank device (as shipped from the factory or after erasure), four pins on Port
C are the basic JTAG signals TMS, TCK, TDI, and TDO.
26.1
Standard JTAG Signals
At power-up, the standard JTAG pins are inputs, waiting for a JTAG serial command from an
external JTAG controller device (such as FlashLINK or Automated Test Equipment). When
the enabling command is received, TDO becomes an output and the JTAG channel is fully
functional. The same command that enables the TAG channel may optionally enable the
two additional JTAG signals, TSTAT and TERR.
The RESET input to the uPS3200 shobe active during JTAG programming. The active
RESET puts the MCU module into RESET mode while the PSD module is being
programmed. See Application Note AN1153 for more details on JTAG In-System
Programming (ISP).
UPSD321xx devices support JTAG In-System-Configuration (ISC) commands, but not
Boundary Scan. he PSDsoft Express software tool and FlashLINK JTAG programming
cable implemt the JTAG In-System-Configuration (ISC) commands.
Table 104. JTAG port signals
Port C Pin
JTAG Signals
Description
PC0
PC1
PC3
PC4
PC5
PC6
TMS
TCK
Mode Select
Clock
TSTAT
TERR
TDI
Status (optional)
Error Flag (optional)
Serial Data In
TDO
Serial Data Out
26.2
JTAG extensions
TSTAT and TERR are two JTAG extension signals enabled by an “ISC_ENABLE” command
received over the four standard JTAG signals (TMS, TCK, TDI, and TDO). They are used to
speed Program and Erase cycles by indicating status on uPDS signals instead of having to
144/181
UPSD3212A, UPSD3212C, UPSD3212CV Programming in-circuit using the JTAG serial interface
scan the status out serially using the standard JTAG channel. See Application Note
AN1153.
TERR indicates if an error has occurred when erasing a sector or programming a byte in
Flash memory. This signal goes Low (active) when an Error condition occurs, and stays Low
until an “ISC_CLEAR” command is executed or a chip Reset (RESET) pulse is received
after an “ISC_DISABLE” command.
TSTAT behaves the same as Ready/Busy described in Section 21.2.1: Ready/Busy (PC3).
TSTAT is High when the PSD module device is in READ mode (primary and secondary
Flash memory contents can be read). TSTAT is Low when Flash memory Program or Erase
cycles are in progress, and also when data is being written to the secondary Flash memory.
TSTAT and TERR can be configured as open-drain type signals during an “ISC_ENABLE”
command.
26.3
Security and Flash memory protection
When the Security Bit is set, the device cannot be read on a Device ogrammer or through
the JTAG Port. When using the JTAG Port, only a Full Chip Ee command is allowed.
All other Program, Erase and Verify commands are blocke. Full Chip Erase returns the part
to a non-secured blank state. The Security Bit can be set in PSDsoft Express Configuration.
All primary and secondary Flash memory sectoran individually be sector protected
against erasures. The sector protect bits can be set in PSDsoft Express Configuration.
145/181
Initial delivery state
UPSD3212A, UPSD3212C, UPSD3212CV
27
Initial delivery state
When delivered from ST, the UPSD321xx devices have all bits in the memory and PLDs set
to '1.' The code, configuration, and PLD logic are loaded using the programming procedure.
Information for programming the device is available directly from ST. Please contact your
local sales representative.
146/181
UPSD3212A, UPSD3212C, UPSD3212CV
AC/DC parameters
28
AC/DC parameters
These tables describe the AD and DC parameters of the UPSD321xx devices:
●
●
●
DC Electrical Specification
AC Timing Specification
PLD Timing
–
–
–
–
Combinatorial Timing
Synchronous Clock mode
Asynchronous Clock mode
Input Macrocell Timing
●
MCU module Timing
–
–
–
READ Timing
WRITE Timing
Power-down and RESET Timing
The following are issues concerning the parameters presente
●
In the DC specification the supply current is given for different modes of operation.
●
The AC power component gives the PLD, Flash memory, and SRAM mA/MHz
specification. Figure 66 and Figure 67 show the PLD mA/MHz as a function of the
number of Product Terms (PT) used.
●
In the PLD timing parameters, adhe required delay when Turbo Bit is '0.'
Figure 66. PLD I /frequency consumption (5 V range)
CC
110
100
90
V
= 5V
CC
80
70
60
50
40
30
20
10
0
PT 100%
PT 25%
0
5
10
15
20
25
HIGHEST COMPOSITE FREQUENCY AT PLD INPUTS (MHz)
AI02894
147/181
AC/DC parameters
UPSD3212A, UPSD3212C, UPSD3212CV
Figure 67. PLD I /frequency consumption (3 V range)
CC
60
V
CC
= 3V
50
40
30
20
10
0
PT 100%
PT 25%
0
5
10
15
20
25
HIGHEST COMPOSITE FREQUENCY AT PLD INPUTS (MHz)
AI03100
Table 105. PSD module example, typ. power calculation at V = 5.0 V (Turbo mode
CC
off)
Conditions
MCU clock frequency
Highest Composite PLD input frequency
(Freq PLD)
= 12 MHz
= 8 Hz
MCU ALE frequency (Freq ALE)
% Flash memory access
% SRAM access
2 MHz
= 80%
= 15%
% I/O access
= 5% (no additional power above base)
Operational modes
% Normal
= 40%
= 60%
% ower-down mode
Numbof product terms used
(from fitter report)
= 45 PT
% of total product terms
Turbo mode
= 45/182 = 24.7%
= Off
148/181
UPSD3212A, UPSD3212C, UPSD3212CV
AC/DC parameters
Table 105. PSD module example, typ. power calculation at V = 5.0 V (Turbo mode
CC
off) (continued)
Conditions
Calculation (using typical values)
= ICC(MCUactive) x %MCUactive + ICC(PSDactive) x %PSDactive + IPD(pwrdown) x
%pwrdown
ICC(MCUactive)
IPD(pwrdown)
= 20mA
= 250µA
I
CC(PSDactive)
= ICC(ac) + ICC(dc)
= %flash x 2.5mA/MHz x Freq ALE
+ %SRAM x 1.5mA/MHz x Freq
ALE
I
CC total
+ % PLD x (from graph using
Freq PLD
= 0.8 x 2.5mAHz x 2MHz + 0.15 x
1.5mA/MHz x 2MHz + 24mA
= (4 + 0.45 + 24) mA
28.45mA
ICC total
= 20mA x 40% + 28.45mA x 40% + 250µA x 60%
= 8mA + 11.38mA + 150µA
= 19.53mA
This is the operating power with no Flash memory Erase or Program cycles in progress. Calculation
is based on all I/O pins being disconnected and IOUT = 0mA.
149/181
Maximum ratings
UPSD3212A, UPSD3212C, UPSD3212CV
29
Maximum ratings
Stressing the device above the rating listed in the Absolute Maximum Ratings” table may
cause permanent damage to the device. These are stress ratings only and operation of the
device at these or any other conditions above those indicated in the Operating sections of
this specification is not implied. Exposure to Absolute Maximum Rating conditions for
extended periods may affect device reliability. Refer also to the STMicroelectronics SURE
Program and other relevant quality documents.
Table 106. Absolute maximum ratings
Symbol
Parameter
Min.
Max.
Unit
TSTG
TLEAD
VIO
Storage Temperature
–65
125
235
6.5
°C
°C
V
Lead Temperature during Soldering (20 seconds max.)(1)
Input and Output Voltage (Q = VOH or Hi-Z)
Supply Voltage
–0.5
–
VCC
6.5
V
VPP
Device Programmer Supply Voltage
–0.5
14.0
2000
V
VESD
Electrostatic Discharge Voltage (Human Body Model) 2
–2000
V
1. IPC/JEDEC J-STD-020A
2. JEDEC Std JESD22-A114A (C1=100pF, R1=1500 Ω, R2=500 Ω)
150/181
UPSD3212A, UPSD3212C, UPSD3212CV
EMC characteristics
30
EMC characteristics
Susceptibility test are performed on a sample basis during product characterization.
30.1
Functional EMS (electromagnetic susceptibility)
Based on a simple running application on the product (toggling 2 LEDs through I/O ports),
the product is stressed by two electromagnetic events until a failure occurs (indicated by the
LEDs).
30.1.1
30.1.2
ESD
Electro-Static Discharge (positive and negative) is applied on all pins of the device until a
functional disturbance occurs. This test conforms with the IEC 1000-4-2 Standard.
FTB
A burst of Fast Transient voltage (positive and negative) is appled to V and V through a
DD
SS
100pF capacitor, until a functional disturbance occurs. Ths test conforms with the IEC
1000-4-2 Standard.
A device reset allows normal operations to be remed. The test results are given in
Table 107, based on the EMS levels and classes defined in Application Note AN1709.
30.2
Designing hardened software to avoid noise problems
EMC characterization and optimization are performed at component level with a typical
application environment and simplified MCU software. It should be noted that good EMC
performance is hghly dependent on the user application and the software in particular.
Therefore, it is recommended that the user applies EMC software optimization and
prequalfication tests in relation with the EMC level requested for the user’s application.
30.2.1
30.2.2
Software recommendations
The software flowchart must include the management of ‘runaway’ conditions, such as:
●
●
●
Corrupted program counter
Unexpected reset
Critical data corruption (e.g., control registers)
Prequalification trials
Most of the common failures (unexpected reset and program counter corruption) can be
reproduced by manually forcing a low state on the RESET pin or the oscillator pins for 1
second.
To complete these trials, ESD stress can be applied directly on the device over the range of
specification values. When unexpected behavior is detected, the software can be hardened
to prevent unrecoverable errors occurring (see Application Note AN1015).
151/181
EMC characteristics
UPSD3212A, UPSD3212C, UPSD3212CV
30.3
Absolute maximum ratings (electrical sensitivity)
Based on three different tests (ESD, LU, and DLU) and using specific measurement
methods, the product is stressed in order to determine its performance in terms of electrical
sensitivity. For more details, refer to the Application Note AN1181.
30.3.1
Electro-static discharge (ESD)
Electro-Static discharges (a positive then a negative pulse separated by 1 second) are
applied to the pins of each sample according to each pin combination. The sample size
depends on the number of supply pins in the device (3 parts*(n+1) supply pin). The Human
Body Model is simulated (Table 108). This test complies with the JESD22-A114A Standard.
Table 107. EMS test results
Symbol
Parameter
Conditions
Level/Class (1)
Voltage limits to be applied on any
I/O pin to induce a functional
disturbance
V
DD = 4V; TA = 25°C; fOSC =
VFESD
40MHz; WDT off complies wit
IEC 1000-4-2
3C
1. Data based on characterization results, not tested in production.
Table 108. ESD absolute maximum ratings
Symbol
Parameter
Conditions
Max. Value(1)
Unit
Electro-static discharge voltage
(Human Body Model)
VESD(HBM)
TA = 25°C
2000
V
1. Data based on characterization results, not tested in production
30.3.2
30.3.3
Latch-up
3 complementary static tests are required on 10 parts to assess the latch-up performance. A
supply overvoltae (applied to each power supply pin) and a current injection (applied to
each input, oput, and configurable I/O pin) are performed on each sample. This test
confors to the EIA/JESD 78 IC Latch-up Standard (see Table 109). For more details, refer
to the Application Note, AN1181.
Dynamic latch-up
Electro-static discharges (one positive then one negative test) are applied to each pin of 3
samples when the micro is running to assess the latch-up performance in dynamic mode.
Power supplies are set to the typical values, the oscillator is connected as near as possible
to the pins of the micro, and the component is put in reset mode. This test conforms to the
IEC 1000-4-2 and SAEJ1752/3 Standards (see Table 109). For more details, refer to the
Application Note, AN1181.
Table 109. Latch-up and dynamic latch-up electrical sensitivities
Symbol
Parameter
Conditions
Level/class (1)
LU
Static latch-up class
TA = 25°C
VDD = 5 V; TA = 25°C; fOSC = 40 MHz
A
A
DLU
Dynamic latch-up class
1. Class description: A Class is an STMicroelectronics internal specification. All of its limits are higher than the
JEDEC specifications. This means when a device belongs to “Class A,” it exceeds the JEDEC standard.
“Class B” strictly covers all of the JEDEC criteria (International standards).
152/181
UPSD3212A, UPSD3212C, UPSD3212CV
DC and AC parameters
31
DC and AC parameters
This section summarizes the operating and measurement conditions, and the DC and AC
characteristics of the device. The parameters in the DC and AC Characteristic tables that
follow are derived from tests performed under the Measurement Conditions summarized in
the relevant tables. Designers should check that the operating conditions in their circuit
match the measurement conditions when relying on the quoted parameters.
Table 110. Operating conditions (5 V devices)
Symbol
Parameter
Min.
Max.
Unit
VCC
Supply voltage
4.5
–40
0
5.5
85
70
V
Ambient operating temperature (industrial)
Ambient operating temperature (commercial)
°C
°C
TA
Table 111. Operating conditions (3 V devices)
Symbol
Parameter
M
Max.
Unit
VCC
Supply voltage
3.0
–40
0
3.6
85
70
V
Ambient operating temperature (industrial)
Ambient operating temperature (commercial)
°C
°C
TA
Table 112. AC signal letters for tim
A
C
D
I
Address
Clock
Input Data
Instruction
ALE
L
N
P
Q
R
W
M
RESET Input or Output
PSEN signal
Output Data
RD signal
WR signal
Output Macrocell
1. Example: tAVLX = Time from Address Valid to ALE Invalid.
153/181
DC and AC parameters
UPSD3212A, UPSD3212C, UPSD3212CV
Table 113. AC signal behavior symbols for timing
t
L
Time
Logic Level Low or ALE
Logic Level High
Valid
H
V
X
No Longer a Valid Logic Level
Float
Z
PW
Pulse Width
1. Example: tAVLX = Time from Address Valid to ALE Invalid.
Figure 68. Switching waveforms – key
INPUTS
OUTPUTS
WAVEFORMS
STEADY INPUT
STEADY OUTPUT
MAY CHANGE FROM
HI TO LO
WILL BE CHANGING
FROM HI TO LO
MAY CHANGE OM
LO TO HI
WILL BE CHANGING
LO TO HI
DON'T CARE
CHANGING, STATE
UNKNOWN
OUTPUTS ONLY
CENTER LINE IS
TRI-STATE
AI03102
Table 114. Majr parameters
Parameters/onditions/
comments
5 V test
conditions
3.3 V test
conditions
3.3 V
value
5.0 V value
Unit
Operating voltage
–
–
4.5 to 5.5
–40 to 85
–
–
3.0 to 3.6
–40 to 85
V
Operating temperature
°C
MCU frequency
1 Min, 40
Max
1 Min, 24
Max
12 MHz (min) for USB;
8 MHz (min) for I2C
–
–
MHz
mA
Active current, typical
24 MHz MCU
clock, 12 MHz
PLD input
frequency, 4 MHz
ALE
12 MHz MCU
clock, 6 MHz
PLD input
frequency,
2 MHz ALE
(25°C operation; 80% Flash
and 15% SRAM accesses,
45 PLD product terms used;
PLD Turbo mode Off)
72
25
21
Idle current, typical
24 MHz MCU
clock, 12 MHz
PLD input
12 MHz MCU
clock, 1 MHz
PLD input
(CPU halted but some
peripherals active; 25°C
operation; 45 PLD product
terms used; PLD Turbo
mode Off)
7
mA
frequency
frequency
154/181
UPSD3212A, UPSD3212C, UPSD3212CV
Table 114. Major parameters (continued)
DC and AC parameters
Parameters/conditions/
comments
5 V test
conditions
3.3 V test
conditions
3.3 V
value
5.0 V value
Unit
Standby current, typical
(Power-down mode,
180 µA with LVD
110
100 µA with LVD
60
µA
requires reset to exit mode;
without Low-Voltage Detect
(LVD) Supervisor)
IOL = 8
(max);
IOL = 4
(max);
VOL = 0.25 V
(max);
VOL = 0.15 V
(max);
I/O sink/source current
Ports A, B, C, and D
mA
–
IOH = –2
(min)
IOH = –1
(min)
VOH = 3.9 V (min)
VOH = 2.6 V (min)
PLD macrocells (For
registered or combinatorial
logic)
–
16
–
16
PLD inputs (Inputs from
pins, macrocell feedback, or
MCU addresses)
–
–
–
69
16
15
–
–
–
69
16
22
–
–
PLD outputs (Output to pins
or internal feedback)
PLD propagation delay,
typical (PLD input to output,
Turbo mode)
ns
155/181
DC and AC parameters
UPSD3212A, UPSD3212C, UPSD3212CV
Table 115. DC characteristics (5 V devices)
Test conditions (in
Symbol
Parameter
addition to those in
Min.
Typ. Max.
Unit
Table 110)
Input high voltage (Ports 1,
2, 3, 4[Bits 7,6,5,4,3,1,0],
XTAL1, RESET)
VCC
0.5
+
VIH
VIH1
VIL
4.5 V < VCC < 5.5 V 0.7 VCC
V
V
V
Input high voltage (Ports A,
B, C, D, 4[Bit 2], USB+,
USB–)
VCC
0.5
+
4.5 V < VCC < 5.5 V
2.0
Input low voltage (Ports 1,
2, 3, 4[Bits 7,6,5,4,3,1,0],
XTAL1, RESET)
0.3 VC
4.5 V < VCC < 5.5 V VSS– 0.5
C
Input low voltage
4.5 V < VCC < 5.5 V
–0.5
0.8
0.8
0.1
V
V
V
V
V
V
V
V
(Ports A, B, C, D, 4[Bit 2])
VIL1
Input low voltage
(USB+, USB–)
4.5 V < VCC < 5.5 V VS– 0.5
I
OL = 20 µA
VCC = 4.5 V
OL = mA
0.01
Output low voltage
(Ports A,B,C,D)
VOL
I
0.25 0.45
0.45
VCC = 4.5 V
Output low voltage
VOL1
IOL = 1.6 mA
(Ports 1,2,3,4, WR, RD)
Output low voltage
(Port 0, ALE, PSEN)
VOL2
IOL = 3.2 mA
0.45
IOH = –20 µA
4.4
2.4
4.49
VCC = 4.5 V
Outphigh voltage
(Ports A,B,C,D)
VOH
IOH = –2 mA
3.9
VCC = 4.5 V
Output high voltage (Port 0
in ext. Bus mode, ALE,
PSEN)
IOH = –800 µA
IOH = –80 µA
2.4
V
V
V
VOH2
4.05
3.75
VLVR
VOP
Low Voltage RESET
0.1 V hysteresis
4.0
4.25
3.0
XTAL open bias voltage
(XTAL1, XTAL2)
IOL = 3.2 mA
2.0
2.5
V
VCC(min) for Flash Erase
and Program
VLKO
4.2
–50
V
Logic '0' input current
(Ports 1,2,3,4)
VIN = 0.45 V
IIL
–10
–65
–10
µA
µA
µA
(0 V for Port 4[pin 2])
VIN = 3.5 V
Logic 1-to-0 transition
current (Ports 1,2,3,4)
ITL
–650
–55
(2.5 V for Port 4[pin 2])
Reset pin pull-up current
(RESET)
IRST
VIN = VSS
156/181
UPSD3212A, UPSD3212C, UPSD3212CV
Table 115. DC characteristics (5 V devices) (continued)
DC and AC parameters
Test conditions (in
addition to those in
Table 110)
Symbol
Parameter
Min.
Typ. Max.
Unit
XTAL1 = VCC
XTAL2 = VSS
XTAL feedback resistor
current (XTAL1)
IFR
–20
–50
µA
ILI
Input leakage current
Output leakage current
VSS < VIN < VCC
–1
1
µA
µA
ILO
0.45 < VOUT < VCC
–10
10
V
CC = 5.5 V
250
380
µA
(1)
LVD logic disabled
IPD
Power-down mode
LVD logic enabled
µA
mA
mA
mA
mA
mA
mA
Active (12 MHz)
Idle (12 MHz)
Active (24 MHz)
Idle (24 MHz)
Active (40 MHz)
Idle (40 MHz)
20
8
30
10
38
20
62
30
VCC = 5 V
VCC = 5 V
15
40
20
ICC_CPU
(2,3,6)
V
CC = 5 V
PLD_TURO = Off,
= 0 MHz(4)
0
µA/PT(5)
µA/PT
mA
PLD Only
D_TURBO = On,
f = 0 MHz
400
15
700
30
ICC_PSD Operating
(DC)(6)
supply current
During Flash memory
WRITE/Erase Only
Flash
memory
Read-only, f = 0 MHz
f = 0 MHz
0
0
0
0
mA
mA
SRAM
PLD AC Base
Note 5
IC_PSD
(AC)(6)
Flash memory AC adder
SRAM AC adder
2.5
1.5
3.5
3.0
mA/MHz
mA/MHz
1. IPD (Power-down mode) is measured with:
XTAL1=VSS; XTAL2=not connected; RESET=VCC; Port 0 =VCC; all other pins are disconnected. PLD not
in Turbo mode.
2. ICC_CPU (active mode) is measured with:
XTAL1 driven with tCLCH, tCHCL = 5 ns, VIL = VSS+0.5 V, VIH = Vcc – 0.5 V, XTAL2 = not connected;
RESET=VSS; Port 0=VCC; all other pins are disconnected. ICC would be slightly higher if a crystal oscillator
is used (approximately 1mA).
3. ICC_CPU (Idle mode) is measured with:
XTAL1 driven with tCLCH, tCHCL = 5 ns, VIL = VSS+0.5 V, VIH = VCC– 0.5 V, XTAL2 = not connected;
Port 0 = VCC
;
4. RESET=VCC; all other pins are disconnected.
5. PLD is in non-Turbo mode and none of the inputs are switching.
6. See Figure 66 for the PLD current calculation.
7. I/O current = 0 mA, all I/O pins are disconnected.
157/181
DC and AC parameters
UPSD3212A, UPSD3212C, UPSD3212CV
Table 116. DC characteristics (3 V devices)
Test conditions (in
Symbol
Parameter
addition to those in
Min.
Typ. Max.
Unit
Table 111)
Input high voltage (Ports 1,
2, 3, 4[Bits 7,6,5,4,3,1,0], A, 3.0 V < VCC < 3.6 V
B, C, D, XTAL1, RESET)
VCC
0.5
+
VIH
VIH1
VIL
0.7VCC
2.0
V
V
V
Input high voltage (Port
3.0 V < VCC < 3.6 V
4[Bit 2])
VCC
0.5
+
Input high voltage (Ports 1,
2, 3, 4[Bits 7,6,5,4,3,1,0],
XTAL1, RESET)
0.3
3.0 V < VCC < 3.6 V VSS– 0.5
VCC
0.8
0.8
0.1
Input low voltage
(Ports A, B, C, D)
3.0 V < VCC < 3.6 V
–0.5
V
V
V
V
VIL1
Input low voltage
(Port 4[Bit 2])
3.0 V < VCC < 3.6 V VSS– 0.5
IOL = 20 µA
0.01
VCC = 3.0 V
Output low voltage
(Ports A,B,C,D)
VOL
IOL = 4 mA
0.15 0.45
VCC = 3.0 V
IOL = 1.6 mA
IOL = 100 µA
OL = 3.2 mA
IOL = 200 µA
0.45
0.3
V
V
V
V
Output low voltage
(Ports 1,2,3,4, WR, RD)
VOL1
0.45
0.3
Output low voltage
(Port 0, ALE, PSEN)
VOL2
IOH = –20 µA
VCC = 3.0 V
2.9
2.4
2.99
2.6
V
V
Output high voltage
(Ports A,B,C,D)
VOH
IOH = –1 mA
VCC = 3.0 V
Outphigh voltage (Port 0
in ext. Bus mode, ALE,
PSEN)
I
OH = –800 µA
IOH = –80 µA
2.0
2.7
2.3
V
V
V
VOH
VLVR
VOP
Low voltage reset
0.1 V hysteresis
OL = 3.2 mA
2.5
2.7
2.0
XTAL open bias voltage
(XTAL1, XTAL2)
I
1.0
1.5
–1
V
VCC(min) for Flash Erase
and Program
VLKO
IIL
2.2
–50
–250
–55
–50
V
Logic '0' input current
(Ports 1,2,3,4)
VIN = 0.45 V
µA
µA
µA
µA
(0 V for Port 4[pin 2])
Logic 1-to-0 transition
current (Ports 1,2,3,4)
VIN = 3.5 V
ITL
–25
–10
–20
(2.5 V for Port 4[pin 2])
Reset pin pull-up current
(RESET)
IRST
IFR
VIN = VSS
XTAL feedback resistor
current (XTAL1)
XTAL1 = VCC
XTAL2 = VSS
ILI
Input leakage current
Output leakage current
VSS < VIN < VCC
–1
1
µA
µA
ILO
0.45 < VOUT < VCC
–10
10
158/181
UPSD3212A, UPSD3212C, UPSD3212CV
Table 116. DC characteristics (3 V devices) (continued)
DC and AC parameters
Test conditions (in
addition to those in
Table 111)
Symbol
Parameter
Min.
Typ. Max.
Unit
V
CC = 3.6 V
110
180
µA
(1)
LVD logic disabled
IPD
Power-down mode
LVD logic enabled
µA
mA
mA
mA
mA
Active (12 MHz)
Idle (12 MHz)
Active (24 MHz)
Idle (24 MHz)
8
4
10
5
VCC = 3.6 V
ICC_CPU
(2,3,6)
15
8
20
10
VCC = 3.6 V
PLD_TURBO = Off,
f = 0 MHz(4)
0
µA/PT (5)
µA/PT
mA
PLD Only
PLD_TURBO = On,
f = 0 MHz
200
10
400
25
ICC_PSD Operating
(DC)(6)
supply current
During Flash memory
WRITE/Erase Only
Flash
memory
Read-only, f = 0 MHz
f = 0 MHz
0
0
0
0
mA
mA
SRAM
PLD AC base
Note 5
ICC_PSD
(AC)(6)
Flash memory AC adder
SRAM AC adder
1.5
0.8
2.0 mA/MHz
1.5 mA/MHz
1. IPD (Power-down mode) is measured with:
XTAL1=VSS; XTAL2=not connected; RESET=VCC; Port 0 =VCC; all other pins are disconnected. PLD not
in Turbo mode.
2. ICC_CPU (active mode) is measured with:
XTAL1 driven with tCLCH, tCHCL = 5 ns, VIL = VSS+0.5 V, VIH = Vcc – 0.5 V, XTAL2 = not connected;
RESET=VSS; P0=VCC; all other pins are disconnected. ICC would be slightly higher if a crystal oscillator
is used (appximately 1 mA).
3. ICC_U (Idle mode) is measured with:
XTAL1 driven with tCLCH, tCHCL = 5 ns, VIL = VSS+0.5 V, VIH = VCC– 0.5 V, XTAL2 = not connected;
ort 0 = VCC
;
4. RESET = VCC; all other pins are disconnected.
5. PLD is in non-Turbo mode and none of the inputs are switching.
6. See Figure 66 for the PLD current calculation.
7. I/O current = 0 mA, all I/O pins are disconnected.
159/181
DC and AC parameters
UPSD3212A, UPSD3212C, UPSD3212CV
Figure 69. External program memory Read cycle
t
t
LLPL
LHLL
ALE
t
t
AVLL
PLPH
t
LLIV
t
PLIV
PSEN
t
t
PXAV
LLAX
t
PXIZ
t
AZPL
PORT 0
INSTR
IN
A0-A7
A0-A7
t
AVIV
t
PXIX
A8-A11
A8-A11
PORT 2
AI06848
Table 117. External program memory AC characteristics (with the 5 V MCU module)
Variable oscillator
40 MHz oscillator
1/tCLCL = 24 to 40 MHz
Symbol
Parameter(1)
Unit
Min.
Mx.
Min.
Max.
tLHLL ALE pulse width
35
10
2 tCLCL – 15
tCLCL – 15
tCLCL – 15
ns
ns
ns
ns
ns
ns
ns
tAVLL Address set-up to ALE
tLLAX Address hold after ALE
tLLIV
ALE Low to valid instruction in
ALE to PSEN
55
30
4 tCLCL – 45
tLLPL
10
60
tCLCL – 15
tPLPH PSEN pulse width
tPLIV PSto valid instruction in
3 tCLCL – 15
3 tCLCL – 45
Input instruction hold after
PSEN
tPXIX
0
0
ns
ns
Input instruction float after
PSEN
(2)
tPXIZ
15
70
tCLCL – 10
(2)
tPXAV
Address valid after PSEN
20
–5
tCLCL – 5
ns
ns
ns
tAVIV
Address to valid instruction in
5 tCLCL – 55
tAZPL Address float to PSEN
–5
1. Conditions (in addition to those in Table 110, VCC = 4.5 to 5.5 V): VSS = 0 V; CL for Port 0, ALE and PSEN
output is 100 pF; CL for other outputs is 80 pF
2. Interfacing the UPSD321xx devices to devices with float times up to 20 ns is permissible. This limited bus
contention does not cause any damage to Port 0 drivers.
160/181
UPSD3212A, UPSD3212C, UPSD3212CV
DC and AC parameters
Table 118. External program memory AC characteristics (with the 3 V MCU module)
24 MHz
Variable oscillator
oscillator
1/tCLCL = 8 to 24 MHz
Symbol
Parameter(1)
Unit
Min.
Max.
Min.
Max.
tLHLL ALE pulse width
43
17
17
2 tCLCL – 40
tCLCL – 25
tCLCL – 25
ns
ns
ns
ns
ns
ns
ns
tAVLL Address set-up to ALE
tLLAX Address hold after ALE
tLLIV
ALE Low to valid instruction in
ALE to PSEN
80
60
4 tCLCL – 87
tLLPL
22
95
tCLCL – 20
tPLPH PSEN pulse width
tPLIV PSEN to valid instruction in
3 tCLCL – 30
3 tCLCL – 65
Input instruction hold after
PSEN
tPXIX
0
0
ns
ns
Input instruction float after
PSEN
(2)
tPXIZ
32
tCLCL – 10
(2)
tPXAV
Address valid after PSEN
37
tCLCL – 5
ns
ns
ns
tAVIV
Address to valid instruction in
148
5 tCLCL – 60
tAZPL Address float to PSEN
–10
–10
1. Conditions (in addition to those in Table 11C = 3.0 to 3.6 V): VSS = 0 V; CL for Port 0, ALE and PSEN
output is 100 pF, for 5 V devices, and 50 pF for 3 V devices; CL for other outputs is 80 pF, for 5 V devices,
and 50 pF for 3 V devices)
2. Interfacing the UPSD321xx devices to devices with float times up to 35 ns is permissible. This limited bus
contention does not cause any damage to Port 0 drivers.
Table 119. External clock drive (with the 5 V MCU module)
Variable oscillator
40 MHz oscillator
1/tCLCL = 24 to 40 MHz
Symb
Parameter(1)
Unit
Min.
Max.
Min.
Max.
tRLRH Oscillator period
tWLWH High time
25
41.7
ns
ns
tCLCL
tCLCX
–
10
10
tCLCL
tCLCX
–
tLLAX2 Low time
ns
tRHDX Rise time
tRHDX Fall time
10
10
ns
ns
1. Conditions (in addition to those in Table 110, VCC = 4.5 to 5.5 V): VSS = 0 V; CL for Port 0, ALE and PSEN
output is 100 pF; CL for other outputs is 80 pF
161/181
DC and AC parameters
UPSD3212A, UPSD3212C, UPSD3212CV
Table 120. External clock drive (with the 3 V MCU module)
Variable oscillator 1/tCLCL
= 8 to 24 MHz
24 MHz oscillator
Min. Max.
Symbol
Parameter(1)
Unit
Min.
Max.
tRLRH Oscillator period
41.7
12
125
ns
tWLWH High time
tLLAX2 Low time
tRHDX Rise time
tRHDX Fall time
tCLCL – tCLCX ns
tCLCL – tCLCX ns
12
12
12
ns
ns
1. Conditions (in addition to those in Table 111, VCC = 3.0 to 3.6 V): VSS = 0 V; CL for Port 0, ALE and PSEN
output is 100 pF, for 5 V devices, and 50 pF for 3 V devices; CL for other outputs is 80 pF, for 5 V devices,
and 50 pF for 3 V devices)
Figure 70. External data memory Read cycle
ALE
tLHLL
tWHLH
PSEN
tLLDV
tLLWL
tRLRH
RD
PORT 0
PORT 2
tRHDZ
RLDV
tRLAZ
tAVLL
tLLAX2
tRHDX
A0-A7 from PCL
A0-A7 from
RI or DPL
DATA IN
INSTR IN
tAVWL
tAVDV
P2.0 to P2.3 or A8-A11 from DPH
A8-A11 from PCH
AI07088
Figure 71. External data memory Write cycle
ALE
tLHLL
tWHLH
PSEN
tLLWL
tWLWH
WR
tWHQX
tQVWX
tQVWH
DATA OUT
tAVLL
tLLAX
A0-A7 from
RI or DPL
A0-A7 from PCL
INSTR IN
PORT 0
PORT 2
tAVWL
P2.0 to P2.3 or A8-A11 from DPH
A8-A11 from PCH
AI07089
162/181
UPSD3212A, UPSD3212C, UPSD3212CV
DC and AC parameters
Table 121. External data memory AC characteristics (with the 5 V MCU module)
Variable oscillator
40 MHz oscillator
1/tCLCL = 24 to 40 MHz
Symbol
Parameter(1)
Unit
Min.
Max.
Min.
Max.
tRLRH RD pulse width
120
120
10
6 tCLCL – 30
6 tCLCL – 30
tCLCL – 15
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tWLWH WR pulse width
tLLAX2 Address hold after ALE
tRHDX RD to valid data in
75
5 tCLCL – 50
tRHDX Data hold after RD
tRHDZ Data float after RD
tLLDV ALE to valid data in
tAVDV Address to valid data in
tLLWL ALE to WR or RD
0
0
38
150
150
90
2 tCLCL – 12
8 tCLCL – 50
9 tCLCL – 75
tCLCL + 15
60
70
10
5
3 tCLCL – 5
4 LCL – 30
tCLCL – 15
tCLCL – 20
7 tCLCL – 50
tCLCL – 20
tAVWL Address valid to WR or RD
tWHLH WR or RD High to ALE High
tQVWX Data valid to WR transition
tQVWH Data set-up before WR
tWHQX Data hold after WR
tRLAZ Address float after RD
40
tCLCL + 15
125
0
0
1. Conditions (in addition to those in Table 110, VCC = 4.5 to 5.5 V): VSS = 0 V; CL for Port 0, ALE and PSEN
output is 100 pF; CL for other outputs is 80 pF
163/181
DC and AC parameters
UPSD3212A, UPSD3212C, UPSD3212CV
Table 122. External data memory AC characteristics (with the 3 V MCU module)
Variable oscillator
24 MHz oscillator
1/tCLCL = 8 to 24 MHz
Symbol
Parameter(1)
Unit
Min.
Max.
Min.
Max.
tRLRH RD pulse width
180
180
56
6 tCLCL – 70
6 tCLCL – 70
2 tCLCL – 27
ns
ns
ns
tWLWH WR pulse width
tLLAX2 Address hold after ALE
tRHDX RD to valid data in
118
5 tCLCL – 90 ns
ns
tRHDX Data hold after RD
tRHDZ Data float after RD
tLLDV ALE to valid data in
tAVDV Address to valid data in
tLLWL ALE to WR or RD
0
0
63
2 tCLCL – 20 ns
8 tCLCL – 133 ns
9 tCLCL – 155 ns
200
220
175
75
67
17
5
3 tCLCL – 50
4 CLCL – 97
tCLCL – 25
tCLCL + 50
ns
ns
ns
ns
ns
ns
ns
tAVWL Address valid to WR or RD
tWHLH WR or RD High to ALE High
tQVWX Data valid to WR transition
tQVWH Data set-up before WR
tWHQX Data hold after WR
tRLAZ Address float after RD
67
tCLCL + 25
tCLCL – 37
170
7 tCLCL – 122
tCLCL – 27
0
0
1. Conditions (in addition to those in Table 111, VCC = 3.0 to 3.6 V): VSS = 0 V; CL for Port 0, ALE and PSEN
output is 100 pF, for 5 V devices, and 50 pF for 3 V devices; CL for other outputs is 80 pF, for 5 V devices,
and 50 pF for 3 V devices)
Table 123. A/D analog specification
Test
Symb
Parameter
Min.
Typ.
Max.
Unit
condition
Analog power supply input
voltage range
AVREF
VAN
VSS
VCC
AVREF + 0.3
200
V
Analog input voltage range
VSS – 0.3
V
Current following between VCC
and VSS
IAVDD
µA
CAIN
NNLE
Overall accuracy
Non-linearity error
2
2
2
2
2
2
l.s.b.
l.s.b.
l.s.b.
l.s.b.
l.s.b.
l.s.b.
NDNLE Differential non-linearity error
NZOE
NFSE
NGE
Zero-offset error
Full scale error
Gain error
at 8 MHz
clock
tCONV Conversion time
20
µs
164/181
UPSD3212A, UPSD3212C, UPSD3212CV
Figure 72. Input to output disable / enable
DC and AC parameters
INPUT
tER
tEA
INPUT TO
OUTPUT
ENABLE/DISABLE
AI02863
Table 124. CPLD combinatorial timing (5 V devices)
PT Turbo Slew
Unit
Symbol
Parameter
Conditions
Min.
Max.
aloc
off
rate(1)
CPLD input pin/feedback to
CPLD combinatorial output
(2)
tPD
20
21
21
21
+ 2
+ 10
– 2
ns
ns
ns
ns
ns
ns
CPLD input to CPLD output
enable
tEA
tER
+ 10
+ 10
+ 10
+ 10
– 2
– 2
– 2
CPLD input to CPLD output
disable
CPLD register clear or
preset delay
tARP
tARPW
tARD
CPLD register clear or
preset pulse width
10
A
rocell
CPLD array delay
11
+ 2
1. Fast Slew Rate output available on PA3-PA0, PB3-PB0, and PD2-PD1. Decrement times by given amount
2. tPD for MCU address and control signals refers to delay from pins on Port 0, Port 2, RD WR, PSEN and
ALE to CPLD combinatorial output (80-pin package only)
Table 125. CPLD combinatorial timing (3 V devices)
PT Turbo Slew
Symbol
Parameter
Conditions
Min.
Max.
Unit
aloc
off rate(1)
CPLD input pin/feedback to
CPLD combinatorial output
(2)
tD
40
43
43
40
+ 4
+ 20
+ 20
+ 20
+ 20
+ 20
– 6
– 6
– 6
– 6
ns
ns
ns
ns
ns
ns
CPLD input to CPLD output
enable
tEA
tER
CPLD input to CPLD output
disable
CPLD register clear or
preset delay
tARP
tARPW
tARD
CPLD register clear or
preset pulse width
25
Any
macrocell
CPLD array delay
25
+ 4
1. Fast Slew Rate output available on PA3-PA0, PB3-PB0, and PD2-PD1. Decrement times by given amount
2. tPD for MCU address and control signals refers to delay from pins on Port 0, Port 2, RD WR, PSEN and
ALE to CPLD combinatorial output (80-pin package only)
165/181
DC and AC parameters
UPSD3212A, UPSD3212C, UPSD3212CV
Figure 73. Synchronous clock mode timing – PLD
t
t
CL
CH
CLKIN
INPUT
t
t
H
S
t
CO
REGISTERED
OUTPUT
AI02860
Table 126. CPLD macrocell synchronous clock mode timing (5 V devices)
PT Turbo Slew
Symbol
Parameter
Conditions
Min.
Max.
Unit
Aloc Off rate(1)
Maximum frequency
external feedback
1/(tS+tCO
1/(tS+tCO–10)
1/(tCH+tCL
)
40.0
66
83.3
MHz
MHz
MHz
Maximum frequency
internal feedback (fCNT
fMAX
)
Maximum frequency
pipelined data
)
tS
tH
Input setup time
Input hold time
12
0
+ 2
+ 10
ns
ns
ns
ns
ns
ns
ns
tCH
tCL
Clock high time
Clock low time
Clock input
Clock input
Clock input
Any macrocell
tCH+tCL
6
6
tCO
tARD
tMIN
Clock to output delay
CPLD array delay
13
11
– 2
+ 2
Minimum clock period (2)
12
1. Fast lew Rate output available on PA3-PA0, PB3-PB0, and PD2-PD1. Decrement times by given amount.
2. LKIN (PD1) tCLCL = tCH + tCL
.
166/181
UPSD3212A, UPSD3212C, UPSD3212CV
DC and AC parameters
Table 127. CPLD macrocell synchronous clock mode timing (3 V devices)
PT Turbo Slew
Symbol
Parameter
Conditions
Min.
Max.
Unit
aloc
off
rate (1)
Maximum frequency
external feedback
1/(tS+tCO
1/(tS+tCO–10)
1/(tCH+tCL
)
22.2
28.5
40.0
MHz
MHz
MHz
Maximum frequency
internal feedback (fCNT
fMAX
)
Maximum frequency
pipelined data
)
tS
tH
Input setup time
Input hold time
20
0
+ 4
+ 20
ns
ns
ns
ns
ns
tCH
tCL
tCO
Clock high time
Clock low time
Clock input
Clock input
Clock input
15
10
Clock to output delay
25
25
– 6
Any
macrocell
tARD
tMIN
CPLD array delay
+ 4
ns
ns
Minimum clock period (2)
tCH+tCL
25
1. Fast Slew Rate output available on PA3-PA0, PB3-PB0, d PD2-PD1. Decrement times by given amount.
2. CLKIN (PD1) tCLCL = tCH + tCL
.
Figure 74. Asynchronous Reset / set
tARPW
RESET/PRESET
INPUT
tARP
REGISTER
OUTPUT
AI02864
Figure 75. Asynchronous clock mode timing (product term clock)
tCHA
tCLA
CLOCK
tSA
tHA
INPUT
tCOA
REGISTERED
OUTPUT
AI02859
167/181
DC and AC parameters
UPSD3212A, UPSD3212C, UPSD3212CV
Table 128. CPLD macrocell asynchronous clock mode timing (5 V devices)
PT Turbo Slew
Symbol
Parameter
Conditions
Min
Max
Unit
aloc
off
rate
Maximum frequency
external feedback
1/(tSA+tCOA
)
38.4
62.5
71.4
MHz
MHz
MHz
Maximum frequency
internal feedback (fCNTA
1/(tSA+tCOA
–
fMAXA
)
10)
Maximum frequency
pipelined data
1/(tCHA+tCLA
)
tSA
tHA
Input setup time
7
8
9
9
+ 2
+ 10
ns
ns
ns
ns
ns
ns
ns
Input hold time
tCHA
tCLA
tCOA
Clock input high time
Clock input low time
Clock to output delay
+ 10
+ 10
+ 10
21
1
– 2
tARDA CPLD array delay
Any macrocell
1/fCNTA
+ 2
tMINA Minimum clock period
16
Table 129. CPLD macrocell asynchronous clock mode timing (3 V devices)
PT
aloc
Turbo Slew
Symbol
Parameter
Conditions
Min.
Max.
Unit
off
rate
Maximum frequency
external feedback
1/(tSA+tCOA
)
21.7
MHz
Maximum frequency
1/(tSA+tCOA
–
fMAXA internal feedback
(fCNTA
27.8
33.3
MHz
MHz
10)
)
Maximfrequency
pipened data
1/(tCHA+tCLA
)
tSA
tHA
Input setup time
10
12
17
13
+ 4
+ 20
ns
ns
ns
ns
ns
ns
ns
Input hold time
tCHA
tCLA
tCOA
tARD
tMINA
Clock input high time
Clock input low time
Clock to output delay
CPLD array delay
Minimum clock period
+ 20
+ 20
+ 20
36
25
– 6
Any macrocell
1/fCNTA
+ 4
36
168/181
UPSD3212A, UPSD3212C, UPSD3212CV
DC and AC parameters
Figure 76. Input macrocell timing (product term clock)
t
t
INL
INH
PT CLOCK
INPUT
t
t
IH
IS
OUTPUT
t
INO
AI03101
Table 130. Input macrocell timing (5 V devices)
PT Turbo
Symbol
Parameter
Conditions
Min.
Max.
Unit
aloc
Off
tIS
tIH
Input setup time
(Note 1)
(Note 1)
(Note 1)
(Note 1)
(Note 1)
0
15
9
ns
ns
ns
ns
ns
Input hold time
+ 10
tINH
tINL
tINO
NIB input high time
NIB input low time
NIB input to combinatorial delay
34
+ 2
+ 10
1. Inputs from Port A, B, and C relative to register/ latch clock from the PLD. ALE/AS latch timings refer to
tAVLX and tLXAX
.
Table 131. Input macrocell timing (3 V devices)
PT
aloc
Turbo
Off
Symbol
Parameter
Conditions Min.
Max.
Unit
tIS
tIH
Input setup time
(Note 1)
(Note 1)
(Note 1)
(Note 1)
(Note 1)
0
ns
ns
ns
ns
ns
Input d time
25
12
12
+ 20
tINH
tNL
tINO
NIB input high time
NIB input low time
NIB input to combinatorial delay
46
+ 4
+ 20
1. Inputs from Port A, B, and C relative to register/latch clock from the PLD. ALE latch timings refer to tAVLX
and tLXAX
.
169/181
DC and AC parameters
UPSD3212A, UPSD3212C, UPSD3212CV
Table 132. Program, Write and Erase times (5 V devices)
Symbol
Parameter
Min.
Typ.
Max.
Unit
Flash Program
8.5
3
s
Flash Bulk Erase(1) (pre-programmed)
30
30
s
Flash Bulk Erase (not pre-programmed)
5
s
s
tWHQV3 Sector Erase (pre-programmed)
tWHQV2 Sector Erase (not pre-programmed)
tWHQV1 Byte Program
1
2.2
14
s
150
µs
Program / Erase Cycles (per Sector)
tWHWLO Sector Erase Time-Out
100,000
cycles
µs
100
DQ7 Valid to Output (DQ7-DQ0) Valid (Data
tQ7VQV
30
ns
Polling)(2)
1. Programmed to all zero before erase.
2. The polling status, DQ7, is valid tQ7VQV time units before the data byte, D0-DQ7, is valid for reading.
Table 133. Program, Write and Erase times (3 V devices)
Symbol
Parameter
Min.
Typ.
Max.
Unit
Flash Program
8.5
3
s
Flash Bulk Erase(1) (pre-progmmed)
30
30
s
Flash Bulk Erase (not pre-programmed)
5
s
s
tWHQV3 Sector Erase (pre-programmed)
tWHQV2 Sector Erase (not pre-programmed)
tWHQV1 Byte Program
1
2.2
14
s
150
µs
Pgram / Erase Cycles (per Sector)
tWHWLO Sector Erase Time-Out
100,000
cycles
µs
100
DQ7 Valid to Output (DQ7-DQ0) Valid (Data
tQ7VQV
30
ns
Polling)(2)
1. Programmed to all zero before erase.
2. The polling status, DQ7, is valid tQ7VQV time units before the data byte, DQ0-DQ7, is valid for reading.
170/181
UPSD3212A, UPSD3212C, UPSD3212CV
Figure 77. Peripheral I/O Read timing
DC and AC parameters
ALE
ADDRESS
DATA VALID
A/D BUS
t
(PA)
(PA)
AVQV
t
SLQV
CSI
RD
t
(PA)
RLQV
t
(PA)
RHQZ
t
(PA)
DVQV
DATA ON PORT A
AI06610
Table 134. Port A peripheral data mode Read timing (5 V devices)
Condition
Symbol
Parameter
Min.
Max.
Turbo off Unit
s
tAVQV–PA Address valid to data valid
tSLQV–PA CSI valid to data valid
tRLQV–PA RD to data valid
(Ne 1)
37
27
32
22
23
+ 10
+ 10
ns
ns
ns
ns
ns
(Note 2)
tDVQV–PA Data in to data out valid
tRHQZ–PA RD to data high-Z
1. Any input used to select Port A Data Peripheral mode.
2. Data is already sble on Port A.
Table 135. Port A peripheral data mode Read timing (3 V devices)
Symbol
Parameter
Conditions
Min.
Max. Turbo off Unit
tAVQV–PA Address valid to data valid
tSLQV–PA CSI valid to data valid
tRLQV–PA RD to data valid
(Note 1)
50
37
45
38
36
+ 20
+ 20
ns
ns
ns
ns
ns
(Note 2)
tDVQV–PA Data in to data out valid
tRHQZ–PA RD to data high-Z
1. Any input used to select Port A Data Peripheral mode.
2. Data is already stable on Port A.
171/181
DC and AC parameters
Figure 78. Peripheral I/O Write timing
UPSD3212A, UPSD3212C, UPSD3212CV
ALE
ADDRESS
DATA OUT
A/D BUS
tWHQZ (PA)
tWLQV (PA)
WR
tDVQV (PA)
PORT A
DATA OUT
AI06611
Table 136. Port A peripheral data mode Write timing (5 V devices)
Symbol
Parameter
Conditions
Min.
Max.
Unit
tWLQV–PA WR to Data Propagation Delay
tDVQV–PA Data to Port A Data Propagation Delay
tWHQZ–PA WR Invalid to Port A Tri-state
25
22
20
ns
ns
ns
(Note 1)
1. Data stable on Port 0 pins to data on Port A.
Table 137. Port A peripheral data mode Write timing (3 V devices)
Symbol
Parameter
Conditions
Min.
Max.
Unit
tWLQV–PA WR to data propagation delay
tDVQV–PA Data to Port A data propagation delay
tWHQZ–PA WR invalid to Port A tri-state
42
38
33
ns
ns
ns
(Note 1)
1. Data stable on Pt 0 pins to data on Port A.
Figure 79. Reset (RESET) timing
VCC(min)
VCC
t
NLNH
t
t
OPR
t
t
OPR
NLNH-PO
Power-On Reset
NLNH-A
Warm Reset
RESET
AI02866b
172/181
UPSD3212A, UPSD3212C, UPSD3212CV
DC and AC parameters
Table 138. Reset (RESET) timing (5 V devices)
Symbol
Parameter
Conditions
Min.
Max.
Unit
tNLNH
RESET active low time(1)
150
1
ns
ms
μs
ns
tNLNH–PO Power-on reset active low time
tNLNH–A Warm RESET (2)
25
tOPR
RESET high to operational device
120
1. Reset (RESET) does not reset Flash memory Program or Erase cycles.
2. Warm RESET aborts Flash memory Program or Erase cycles, and puts the device in READ mode.
Table 139. Reset (RESET) timing (3 V devices)
Symbol
Parameter
Conditions
Min.
Max.
Unit
tNLNH
RESET active low time(1)
300
1
ns
ms
μs
ns
tNLNH–PO Power-on reset active low time
tNLNH–A Warm RESET (2)
2
tOPR
RESET high to operational device
300
1. Reset (RESET) does not reset Flash memory Program or Erase cycles.
2. Warm RESET aborts Flash memory Program or Erase cycles, and puts the device in READ mode.
Figure 80. ISC timing
tISCCH
TCK
tISCCL
tISCPSU
tISCPH
TDI/T
t ISCPZV
tISCPCO
ISC OUTPUTS/TDO
tISCPVZ
ISC OUTPUTS/TDO
AI02865
173/181
DC and AC parameters
UPSD3212A, UPSD3212C, UPSD3212CV
Table 140. ISC timing (5 V devices)
Symbol Parameter
Conditions
Min.
Max.
Unit
tISCCF Clock (TCK, PC1) frequency (except for PLD)
tISCCH Clock (TCK, PC1) high time (except for PLD)
tISCCL Clock (TCK, PC1) low time (except for PLD)
tISCCFP Clock (TCK, PC1) frequency (PLD only)
tISCCHP Clock (TCK, PC1) high time (PLD only)
tISCCLP Clock (TCK, PC1) low time (PLD only)
tISCPSU ISC port set-up time
(Note 1)
(Note 1)
(Note 1)
(Note 2)
(Note 2)
(Note 2)
20
MHz
ns
23
23
ns
2
MHz
ns
240
240
7
ns
ns
tISCPH ISC port hold-up time
5
ns
tISCPCO ISC port clock to output
21
21
21
ns
tISCPZV ISC port high-impedance to valid output
tISCPVZ ISC port valid output to high-impedance
ns
ns
1. For non-PLD Programming, Erase or in ISC By-pass mode.
2. For Program or Erase PLD only.
Table 141. ISC timing (3 V devices)
Symbol
Parameter
Conditions
Min.
Max.
Unit
tISCCF Clock (TCK, PC1) frequency (ept for PLD)
tISCCH Clock (TCK, PC1) high time (except for PLD)
tISCCL Clock (TCK, PC1) low time (except for PLD)
tISCCFP Clock (TCK, PC1) frequency (PLD only)
tISCCHP Clock (CK, PC1) high time (PLD only)
tISCCLCloc(TCK, PC1) low time (PLD only)
tISCPSU ISC port set-up time
(Note 1)
(Note 1)
(Note 1)
(Note 2)
(Note 2)
(Note 2)
12
MHz
ns
40
40
ns
2
MHz
ns
240
240
12
ns
ns
tISCPH ISC port hold-up time
5
ns
tISCPCO ISC port clock to output
30
30
30
ns
tISCPZV ISC port high-impedance to valid output
tISCPVZ ISC port valid output to high-impedance
ns
ns
1. For non-PLD Programming, Erase or in ISC By-pass mode.
2. For Program or Erase PLD only.
Figure 81. MCU module AC measurement I/O waveform
V
– 0.5V
0.45V
CC
0.2 V
0.2 V
+ 0.9V
CC
Test Points
– 0.1V
CC
AI06650
1. AC inputs during testing are driven at VCC–0.5 V for a logic '1,' and 0.45 V for a logic '0.'
2. Timing measurements are made at VIH(min) for a logic '1,' and VIL(max) for a logic '0'.
174/181
UPSD3212A, UPSD3212C, UPSD3212CV
Figure 82. PSD module AC float I/O waveform
DC and AC parameters
V
V
– 0.1V
OH
V
+ 0.1V
LOAD
Test Reference Points
V
0.2 V
– 0.1V
– 0.1V
+ 0.1V
AI06651
LOAD
CC
OL
1. For timing purposes, a Port pin is considered to be no longer floating when a 100mV change from load
voltage occurs, and begins to float when a 100mV change from the loaded VOH or VOL level occurs
2. IOL and IOH ≥ 20mA
Figure 83. External clock cycle
Figure 84. Recommended oscillator circuits
1. C1, C2 = 30 pF 0 pF for crystals
2. For ceramic sonators, contact resonator manufacturer
3. Oscilation circuit is designed to be used either with a ceramic resonator or crystal oscillator. Since each
crystal and ceramic resonator
4. have their own characteristics, the user should consult the crystal manufacturer for appropriate values of
external components.
Figure 85. PSD module AC measurement I/O waveform
3.0V
Test Point
1.5V
0V
AI03103b
175/181
DC and AC parameters
UPSD3212A, UPSD3212C, UPSD3212CV
Figure 86. PSD module AC measurement load circuit
2.01 V
195 Ω
Device
Under Test
C
L = 30 pF
(Including Scope and
Jig Capacitance)
AI03104b
Table 142. Capacitance
Symbol
Parameter
Test conditions (1) Typ.(2)
Max.
Unit
CIN
Input capacitance (for input pins)
VIN = 0 V
OUT = 0 V
4
8
6
pF
Output capacitance (for
input/output pins)
COUT
V
12
pF
1. Sampled only, not 100% tested.
2. Typical values are for TA = 25°C and nominal supply voltages.
176/181
UPSD3212A, UPSD3212C, UPSD3212CV
Package mechanical information
32
Package mechanical information
Figure 87. LQFP52 – 52-lead plastic thin, quad, flat package outline
Seating plane
A2
A
c
A1
ddd
C
D
0.25 mm
.010 inch
Gage plane
D1
D2
27
39
L
k
L1
40
26
b
E2
E1
E
14
52
Pin 1 identification
13
1
e
DC_ME
1. Drawing is not to scale.
Table 143. LQFP52 – 52-lead plastic thin, quad, flat package mechanical data
millimeters
Min
inches(1)
Symbol
Typ
Max
Typ
Min
Max
A
A
A2
b
1.60
0.15
1.45
0.38
0.2
0.063
0.0059
0.0571
0.015
0.05
1.35
0.22
0.09
0.002
0.0531
0.0087
0.0035
C
0.0079
D
12
10
0.4724
0.3937
0.3071
0.4724
0.3937
0.3071
0.0256
D1
D2
E
7.8
12
E1
E2
e
10
7.8
0.65
L
0.45
0.75
7°
0.0177
0.0295
7°
L1
k
1
0.0394
0°
0°
ddd
0.100
0.0039
1. Values in inches are converted from mm and rounded to 4 decimal digits.
177/181
Package mechanical information
UPSD3212A, UPSD3212C, UPSD3212CV
Figure 88. LQFP80 – 80-lead plastic thin, quad, flat package outline
D
D1
D3
A2
41
60
61
40
e
b
E3 E1
E
21
80
Pin 1
identification
1
20
A
ccc
L1
c
A1
k
L
9X_ME
1. Drawing is not to scale.
Table 144. LQFP80 – 80-lead plastic thin, quad, flat package mechanical data
millimeters
Min
inches(1)
Symbol
Typ
Max
Typ
Min
Max
A
1.600
0.150
1.450
0.270
0.200
0.0630
0.0059
0.0571
0.0106
0.0079
A1
A2
b
0.050
1.350
0.170
0.090
0.0020
0.0531
0.0067
0.0035
1.400
20
0.0551
0.0087
C
D
14.000
12.000
9.500
0.5512
0.4724
0.3740
0.5512
0.4724
0.3740
0.0197
0.0236
0.0394
D1
D3
E
14.000
12.000
9.500
0.500
E1
E3
e
L
0.600
0.450
0.750
7°
0.0177
0.0295
7°
L1
k
1.000
0°
0°
ccc
0.080
0.0031
1. Values in inches are converted from mm and rounded to 4 decimal digits.
178/181
UPSD3212A, UPSD3212C, UPSD3212CV
Part numbering
33
Part numbering
Table 145. Ordering information scheme
Example:
UPSD
3
2
1
4
B
V
–
24
U
6
T
Device type
UPSD = Microcontroller PSD
Family
3 = 8032 core
PLD size
2 = 16 Macrocells
SRAM Size
1 = 2 Kbytes
Main Flash memory size
2 = 64 Kbytes
3 = 128 Kbytes
4 = 256 Kbytes
IP mix
A = USB, I2C, PWM, DDC, ADC, (2) UARTs,
Supervisor (Reset Out, Reset In, LVD, WD)
B = I2C, PWM, DDC, ADC, (2) UARTs
Supervisor (Reset Out, Reset In, LVD, WD)
Operating voltage
blank = VCC = 4.5 to 5.5 V
V = VCC = 3.0 to 3.6 V
Speed
–24 = 24 MH
–40 = 4MHz
Pkage
T = 52-pin LQFP
U = 80-pin LQFP
Temperature range
1 = 0 to 70°C
6 = –40 to 85°C
Shipping options
F = ECOPACK® Package, Tape & Reel Packing
For other options, or for more information on any aspect of this device, please contact the ST Sales
Office nearest you.
179/181
Revision history
UPSD3212A, UPSD3212C, UPSD3212CV
34
Revision history
Table 146. Document revision history
Date
Revision
Changes
18-Dec-2002
1.0
First Issue
Updates: port information (Table 30); interface information (Figure 30,
Table 44); remove programming guide; PSD module information
(Table 82); PLD information (Figure 55); electrical characteristics
(Table 114, 115, 131, 132)
04-Mar-03
1.1
02-Sep-03
03-Feb-04
1.2
2.0
Update references for Product Catalog
Reformatted; correct package dimensions (Table 145)
Reformatted; add EMC characteristics information (Table 106, 107,
108)
02-July-04
04-Nov-04
3.0
4.0
Updates per requested data brief changes (gure 3, 4; Table 1, 2,
113)
Add USB feature to document (Figure 2, 3, 4, 15, 16, 18, 20, 40, 41,
42, 43, 44, 45; Table 1, 2, 15, 16, 18, 19, 21, 23, 24, 25, 60, 61, 62,
63, 64, 65, 66, 67, 68, 69, 0, 71, 72, 73, 74, 75, 76, 77, 78, 79, 146)
03-Dec-04
5.0
6.0
Removed battery backp feature and related SRAM Standby mode
information. Add Ecopack information and updated Section 32:
Package anical information on page 177.
21-Jan-2009
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UPSD3212A, UPSD3212C, UPSD3212CV
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相关型号：
UPSD3212AV-40U6T
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