UPSD3315AV-24U1 [STMICROELECTRONICS]

Flash Programmable System Device with 8032 Microcontroller Core; 闪存可编程系统设备与8032微控制器内核


型号：	UPSD3315AV-24U1
厂家：	ST
描述：	Flash Programmable System Device with 8032 Microcontroller Core 闪存可编程系统设备与8032微控制器内核闪存微控制器
文件：	总8页 (文件大小：72K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

µPSD3200 FAMILY

Flash Programmable System Device

with 8032 Microcontroller Core

DATA BRIEFING

FEATURES SUMMARY

■ The µPSD3200 Family combines a Flash PSD

Figure 1. Packages

architecture with an 8032 microcontroller core

The µPSD3200 Family of Flash PSDs features

dual banks of Flash memory, SRAM, general

purpose I/O and programmable logic, supervi-

sory functions and access via USB, I C, ADC,

DDC and PWM channels, and an on-board

8032 microcontroller core, with two UARTs,

three 16-bit Timer/Counters and one External

Interrupt. As with other Flash PSD families, the

µPSD3200 Family is also in-system program-

mable (ISP) via a JTAG ISP interface.

■ Large 8 KByte SRAM with battery back-up

option

■ Dual bank Flash memories

TQFP52 (T)

– 128 KByte or 256 KByte main Flash memory

– 32 KByte secondary Flash memory

■ Content Security

– Block access to Flash memory

■ Programmable Decode PLD for flexibleaddress

mapping of all memories.

■ High-speed clock standard 8032 core (12-cycle)

■ USB Interface (µPSD3234A-40U6 only)

■ I C interface for peripheral connections

TQFP80 (U)

■ Five Pulse Width Modulator (PWM) channels

■ Standalone Display Data Channel (DDC)

■ Six I/O ports with up to 50 I/O pins

■ 3000 gate PLD with 16 macrocells

■ Supervisor functions

■ In-System Programming (ISP) via JTAG

■ Zero-Power Technology

■ Single Supply Voltage

– 4.5 to 5.5 V

– 3.0 to 3.6 V

June 2002

1/8

Complete data available on Data-on-Disc CD-ROM or at www.st.com.

µPSD3200 FAMILY

SUMMARY DESCRIPTION

■ Dual bank Flash memories

– One 16-bit PWM unit

– Concurrent operation, read from memory one

while erasing and writing the other. In-Appli-

cation Programming(IAP) for remote updates

■ Standalone Display Data Channel (DDC)

– For use in monitor, projector, and TV applica-

tions

– Large 128 KByte or 256 KByte main Flash

memory for application code, operating sys-

tems, or bit maps for graphic user interfaces

– Compliant with VESA standards DDC1 and

DDC2B

– Eliminate external DDC PROM

– Large 32 KByte secondary Flash memory di-

vided in small sectors. Eliminate external EE-

PROM with software EEPROM emulation

■ Six I/O ports with up to 50 I/O pins

– Multifunction I/O: GPIO, DDC, I C, PWM,

PLD I/O, supervisor, and JTAG

– Secondary Flash memory is large enough for

sophisticated communication protocol (USB)

during IAP while continuing critical system

tasks

– Eliminates need for external latches and logic

■ 3000 gate PLD with 16 macrocells

– Create glue logic, state machines, delays,

etc.

■ Large SRAM with battery back-up option

– Eliminate external PALs, PLDs, and 74HCxx

– Simple PSDsoft Express software ...Free

■ Supervisor functions

– 8 KByte SRAM for RTOS, high-level languag-

es, communication buffers, and stacks

■ Programmable Decode PLD for flexibleaddress

mapping of all memories

– Generates reset upon low voltage or watch-

dog time-out. Eliminate external supervisor

device

– Place individual Flash and SRAM sectors on

any address boundary

– Built-in page register breaks restrictive 8032

limit of 64 KByte address space

– Reset In pin

■ In-System Programming (ISP) via JTAG

– Special register swaps Flash memory seg-

ments between 8032 “program” space and

“data” space for efficient In-Application Pro-

gramming

– Program entire chip in 10 - 25 seconds with

no involvement of 8032

– Allows efficient manufacturing, easy product

testing, and Just-In-Time inventory

■ High-speed clock standard 8032 core (12-cycle)

– Eliminate sockets and pre-programmed parts

– Program with FlashLINK^TMcable and any PC

■ Content Security

– 40 MHz operation at 5 V, 24 MHz at 3.3 V

– Two UARTs with independent baud rate,

three 16-bit Timer/Counters and two External

Interrupts

– Programmable Security Bit blocks access of

device programmers and readers

■ USB Interface (µPSD3234A-40U6 only)

■ Zero-Power Technology

– Supports USB 1.1 Slow Mode (1.5 Mbit/s)

– Memories and PLD automatically reach

standby current between input changes

– Control endpoint 0 and interrupt endpoints 1

and 2

■ Packages

■ I C interface for peripheral connections

– 52-pin TQFP

– Capable of master or slave operation

■ Five Pulse Width Modulator (PWM) channels

– Four 8-bit PWM units

– 80-pin TQFP: allows access to 8032 address/

data/control signals for connecting to external

peripherals

2/8

µPSD3200 FAMILY

Figure 2. µPSD3200 Family Functional Modules

Port 3, UART,

Intr, Timers,I2C

Port 4 PWM

and DDC

Dedicated

USB Pins

Port 1, Timers and

2nd UART and ADC

Port 3

8051 Core

Port 1

I2C

USB

DDC

w/ 256 Byte

PWM

5 Channels

Reset Logic

LVD & WDT

Channel

ADC

3 Timer /

Counters

2 UARTS

Interrupt

SRAM Transceiver

256 Byte SRAM

MCU MODULE

Port 0, 2

Ext. Bus

8032 Internal Bus

A0-A15

D0-D7

RD,PSEN

Reset

WR,ALE

PSD MODULE

256Kb

Secondary

Flash

1Mb or 2Mb

Main Flash

64Kb

SRAM

Page Register

Decode PLD

Bus Interface

PSD Internal Bus

VCC, GND,

XTAL

JTAG ISP

CPLD - 16 MACROCELLS

Port C,

JTAG, PLD I/O

and GPIO

Port A & B, PLD

I/O and GPIO

Port D

GPIO

Dedicated

Pins

AI06619

3/8

µPSD3200 FAMILY

Table 1. 80-Pin Package Pin Description

Function

Signal Name In/Out

Basic

Alternate

AD7-AD0

A11-A8

I/O

Multiplexed Address/Data bus

External Address Bus

RxD2-RxD1

TxD2-TxD1

INT1-INT0

T2-T0

UART Receive

UART Transmit

Interrupt inputs / timer gate controls

Counter inputs

SDA1-SDA2

SCL1-SCL2

I/O

I C Bus serial data I/O / DDC interface

General I/O port pins

I C Bus clock I/O

VSYNC

T2EX

I/O

VSYNC input for DDC interface

Timer 2 Trigger input

ADC3-ADC0

PWM4-PWM0

USB-, USB+

AVREF

ADC Channels input

8-bit Pulse Width Modulation outputs

USB I/O

Reference Voltage input for ADC

Read signal, external bus

Write signal, external bus

PSEN signal, external bus

Address Latch signal, external bus

Active low reset input

RD_

WR_

PSEN_

ALE

RESET_

XTAL1

Oscillator input pin for system clock

Oscillator output pin for system clock

XTAL2

1. PLD Macro-cell outputs

2. PLD inputs

3. Latched Address Out (A0-A7)

4. Peripheral I/O mode

PA7-PA0

PB7-PB0

I/O

General I/O port pins

1. PLD Macro-cell outputs

2. PLD inputs

3. Latched Address Out (A0-A7)

1. PLD Macro-cell outputs

2. PLD inputs

3. SRAM stand by voltage input (VSTBY)

4. JTAG Interface (TDI, TDO, TMS, TCK, TSTAT,

TERR)

PC7-PC0

I/O

General I/O port pins

5. SRAM battery-on indicator (PC4)

1. PLD I/O

PD2-PD1

I/O

General I/O port pin

2. Clock input to PLD and APD

3. Chip select to PSD Module

Note: PSD Port A and MCU Address/Data bus are added for 80-pin device

4/8

µPSD3200 FAMILY

Figure 3. TQFP52 Connections

PD1

PC7

PC6

PC5

39 P1.5 / ADC1

38 P1.4 / ADC0

37 P1.3 / TXD1

36 P1.2 / RXD1

35 P1.1 / T2X

34 P1.0 / T2

PC4

33 V

32 XTAL2

GND 9

PC3 10

PC2 11

PC1 12

PC0 13

31 XTAL1

30 P3.7 / SCL1

29 P3.6 / SDA1

28 P3.5 / T1

27 P3.4 / T0

AI05790B

Note: NC = Not Connected

PU = Pull-up resistor required (2kΩ for 3V devices, 7.5kΩ for 5V devices)

5/8

µPSD3200 FAMILY

Figure 4. TQFP80 Connections

PD2

P3.3 /EXINT1

PD1

60 P1.5 / ADC1

59 P1.4 / ADC0

58 P1.3 / TXD1

57 P2.3, A11

56 P1.2 / RXD1

55 P2.2, A10

54 P1.1 / T2X

53 P2.1, A9

PD0, ALE

PC7

PC6

PC5

USB-

PC4

52 P1.0 / T2

USB+ 10

NC 11

51 P2.0, A8

50 V

49 XTAL2

GND 13

PC3 14

48 XTAL1

47 P0.7, AD7

46 P3.7 / SCL1

45 P0.6, AD6

44 P3.6 / SDA1

43 P0.5, AD5

42 P3.5 / T1

41 P0.4, AD4

PC2 15

PC1 16

NC 17

P4.7 / PWM4 18

P4.6 / PWM3 19

PC0 20

AI05791

Note: 1. NC = Not Connected

2. USB- needs a pull-up resistor (see the description of the USB function)

6/8

µPSD3200 FAMILY

PART NUMBERING

Table 2. Ordering Information Scheme

Example:

uPSD 3

– 24 U

Device Type

uPSD = Microcontroller PSD

Family

3 = 8032 core

PLD Size

2 = 16 Macrocells

3 = 32 Macrocells

SRAM Size

1 = 16 Kbit

3 = 64 Kbit

5 = 256 Kbit

Main Flash Memory Size

3 = 1 Mbit

4 = 2 Mbit

5 = 4 Mbit

IP Mix

A = USB, I C, PWM, DDC, ADC, (2) UARTs

Supervisor (Reset Out, Reset In, LVD, WD)

B = I C, PWM, DDC, ADC, (2) UARTs

Supervisor (Reset Out, Reset In, LVD, WD)

Operating Voltage

blank = V = 4.5 to 5.5V

V = V

= 3.0 to 3.6V

Speed

24 = 24 MHz

40 = 40 MHz

Package

T = 52-pin TQFP

U = 80-pin TQFP

Temperature Range

1 = 0 to 70 °C (commercial)

6 = –40 to 85 °C (industrial)

Option

T = Tape & Reel Packing

For a list of available options (speed, package,

etc.) or for further information on any aspect of this

device, please contact your nearest ST Sales Of-

fice.

7/8

µPSD3200 FAMILY

Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences

of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted

by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject

to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not

authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.

The ST logo is registered trademark of STMicroelectronics

All other names are the property of their respective owners

STMicroelectronics group of companies

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8/8

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