UPSD3333DV-40U1 [STMICROELECTRONICS]
IC,MICROCONTROLLER,8-BIT,8051 CPU,CMOS,QFP,80PIN,PLASTIC;
| 型号： | UPSD3333DV-40U1 |
| 厂家： | 
ST |
| 描述： | IC,MICROCONTROLLER,8-BIT,8051 CPU,CMOS,QFP,80PIN,PLASTIC |
| 文件： | 总123页 (文件大小：1145K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
µPSD33XX (TURBO SERIES)
Fast 8032 MCU With Programmable Logic
PRELIMINARY DATA
FEATURES SUMMARY
8-bit System On Chip for Embedded Control
■ Programmable Counter Array (PCA)
– Dual independent timer/counter blocks, each
with three 16-bit timer/counters modules
– Use any of the 6 modules as: 16-bit capture/
compare, 16-bit timer/counter, 8/16 bit PWM.
The Turbo µPSD3300 Series combines a power-
ful, 8051-based microcontroller with a unique
memory structure, programmable logic, and a rich
peripheral mix to form the ideal SOC for embed-
ded control. At it's core is a fast, 4-cycle 8032 MCU
with a 6-byte instruction prefetch queue and a 4-
entry, fully associative branching cache to maxi-
mize MCU performance, enabling smaller loops of
code to execute very quickly.
■ JTAG Debug and In-System Programming
– Set Breakpoints, trace, single-step, display,
modify memory, and SFRs; external event
pin.
Code development is easily managed without a
hardware In-Circuit Emulator by using the serial
JTAG debug interface. JTAG is also used for In-
System Programming (ISP), perfect for manufac-
turing and lab development. The 8032 core is cou-
pled to Programmable System Device (PSD)
architecture to optimize 8032 memory structure,
offering two independent banks of Flash memory
that can be placed at virtually any address within
8032 program or data space, and easily paged be-
yond 64K bytes using on-chip programmable de-
code logic. Dual Flash memory banks provide a
robust solution for remote product updates in the
field through In-Application Programming (IAP).
Dual Flash banks also support EEPROM emula-
tion, eliminating the need for external EEPROM
chips.
– ISP the chip in 10-20sec, 8032 not involved.
■ Programmable Logic, General Purpose
– 16 Macrocells with architecture similar to in-
dustry standard 22V10 PLDs
– Create shifters, state machines, chip-selects,
glue-logic to keypads, panels, LCDs, others
– Configure PLD with simple PSDsoft Express
software ... download at no charge from web.
■ Dual Flash Memories w/Memory Managment
– True READ-while-WRITE concurrent access
– Main Flash size: 64K, 128K, or 256K Bytes
– Secondary Flash size: 16K or 32K bytes
– 100,000 min erase cycles, 15 year retention
– On-chip programmable memory decode logic
■ SRAM
A wide variety of Flash and SRAM memory sizes
are available, some reaching the largest on the 8-
bit MCU market today. General purpose program-
mable logic is included to build an endless variety
of glue-logic, saving external chips. This SOC also
– 2K, 8K, or 32K Bytes; use as XDATA or code.
– Capable of battery backup w/external battery.
■ Peripheral Interfaces
provides a rich array of peripherals, including ana-
log and supervisor functions.
■ Fast Turbo 8032 MCU
– (8) 10-bit ADC channels, 8 usec conversion
time
2
– Advanced 8032 core: four clocks per instruc-
tion instruction pre-fetch; branching cache
– 10 MIPs peak performance @40MHz clock
– I C Master/Slave bus controller up to 800kHz
– SPI Master bus controller, up to 10Mhz
– Two standard UARTs with independent baud
– IrDA protocol support up to 115K baud rate
– 8032 address/data bus (80 pin package only)
– Up to 46 I/O; eight can sink/source 10mA.
■ Supervisor Functions
5.0V V ... 8 MIPs peak @40MHz, 3.3V V
CC
CC
– 8032 core compatible with 3rd party tools
– Internal clock divider for low-power mode
– Three 8032 16-bit timers and external
interrupts
– Watchdog timer, V monitor with 10ms
CC
– Dual XDATA pointers with auto incr & decr
Reset generator, Filtered Reset input
July 2003
1/123
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
Rev. 1.0
µPSD33XX
■ Operating Range
■ TQFP Packaging
– 3.3V applications: V = 3.3V ± 10%
– 52-pin (10x10mm) or 80-pin (12x12mm)
CC
– 5.0V applications: V : Both 5.0V ± 10% and
CC
3.3V ± 10% sources are required.
– Temp: –40°C to +85°C (Industrial Range)
Figure 1. 52-lead, Thin, Quad, Flat Package
Figure 2. 80-lead, Thin, Quad, Flat Package
TQFP52 (T)
TQFP80 (U)
Table 1. µPSD33XX Device Selector Guide
3 std
2
I C
timers,
Main
2nd
ADC,
Super-
visor
8032 JTAG,
+6 prog
SPI,
Dual
UART,
IrDA
SRAM
Kbyte
Pkg
Op V
CC
Part No. Flash Flash
Kbyte Kbyte
PLD
GPIO Bus ISP, &
Pins Debug
timer/
PWM
modules
µPSD
3312DV-
40T6
16
macro
cells
Up to
37
52-pin
TQFP
64K
64K
16K
16K
32K
32K
32K
32K
32K
32K
32K
32K
2K
2K
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
No
yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
3.3V±10%
3.3V &
µPSD
3312D-
40T6
16
macro
cells
Up to
37
52-pin
TQFP 5.0V±10%
µPSD
3333DV- 128K
40T6
16
macro
cells
Up to
37
52-pin
8K
No
3.3V±10%
TQFP
µPSD
3333D-
40T6
16
macro
cells
Up to
37
52-pin
TQFP 5.0V±10%
3.3V &
128K
8K
No
µPSD
3334DV- 256K
40T6 16
16
macro
cells
Up to
46
80-pin
8K
Yes
Yes
No
3.3V±10%
TQFP
µPSD
3334D-
40U6
16
macro
cells
Up to
46
80-pin
TQFP 5.0V±10%
3.3V &
256K
8K
µPSD
3354DV- 256K
40T6
16
macro
cells
Up to
37
52-pin
32K
32K
32K
32K
3.3V±10%
TQFP
µPSD
3354D-
40T6
16
macro
cells
Up to
37
52-pin
TQFP 5.0V±10%
3.3V &
256K
No
µPSD
3354DV- 256K
40T6 16
16
macro
cells
Up to
46
80-pin
Yes
Yes
3.3V±10%
TQFP
µPSD
3354D-
40U6
16
macro
cells
Up to
46
80-pin
TQFP 5.0V±10%
3.3V &
256K
2/123
µPSD33XX
TABLE OF CONTENTS
µPSD33XX HARDWARE DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
MEMORY ORGANIZATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Program Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Data Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
XRAM-PSD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
8032 CORE PERFORMANCE ENHANCEMENTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Instruction Pre-fetch Queue . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Branch Cache (BC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
MCU MODULE DISCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Special Function Registers (SFRs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Dual Data Pointers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Data Pointer Control Register, DPTC (85H) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Data Pointer Mode Register, DPTM (86H) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Debug Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
INTERRUPT SYSTEM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
External Int0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Timer 0 and 1 Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Timer 2 Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
I2C Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
External Int1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
ADC Interrupt. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
PCA Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
SPI Interrupt. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
UART Interrupt. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Debug Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Interrupt Priority Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Interrupts Enable Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
POWER SAVINGS MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Idle Mode Function Activity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Idle Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Power-down Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
REDUCED FREQUENCY MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
CLOCK GENERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
CPU CLOCK CONTROL REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3/123
µPSD33XX
OSCILLATOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
I/O PORTS (MCU MODULE). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Port 1 Register P1SFS0, Port 1 Register P1SFS1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Port 3 Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Port 4 Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Port 4 High Current Option. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
MCU MEMORY BUS INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
READ Bus Cycle (Code or XDATA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
WRITE Bus Cycle (XDATA). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Bus Control Register (BUSCON) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
SUPERVISORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
External Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Low V Voltage Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
CC
Watchdog Timer Overflow Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Debug Unit Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Reset Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Power-up Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
WATCHDOG TIMER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Watchdog Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
WDT Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
TIMER/COUNTERS (TIMER0, TIMER1, AND TIMER 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Timer 0 and Timer 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Timer 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
STANDARD SERIAL INTERFACE (UART) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Serial Port Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
IRDA INTERFACE TO INFRARED TRANSCEIVER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Baud Rate Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
I2C INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
I2C Registers Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Serial Status Register (S1STA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Data Shift Register (S1DAT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Address Register (S1ADR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
SPI (SYNCHRONOUS PERIPHERAL INTERFACE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
SPI Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
SPI Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
4/123
µPSD33XX
Slave Select Output. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Receive Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
ANALOG-TO-DIGITAL CONVERTOR (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Port 1 ADC Channel Selects. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
PROGRAMMABLE COUNTER ARRAY (PCA) WITH PWM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
PCA Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Operation of TCM Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Capture Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Timer Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Toggle Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
PWM Mode - (X8), Fixed Frequency. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
PWM Mode - (X8), Programmable Frequency. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
PWM Mode - Fixed Frequency, 16-bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Writing to Capture/Compare Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Control Register Bit Definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
TCM Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
PSD MODULE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Functional Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
PSD MODULE REGISTER DESCRIPTION AND ADDRESS OFFSET . . . . . . . . . . . . . . . . . . . . . . . . 67
PSD MODULE DETAILED OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
MEMORY BLOCKS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Primary Flash Memory and Secondary Flash memory Description . . . . . . . . . . . . . . . . . . . . . 68
Memory Block Select Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Flash Memory Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
READ Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Programming Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Erasing Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Specific Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Sector Select and SRAM Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Page Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
PLDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
The Turbo Bit in PSD Module. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Decode PLD (DPLD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Complex PLD (CPLD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Output Macrocell (OMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Product Term Allocator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Input Macrocells (IMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
5/123
µPSD33XX
I/O PORTS (PSD MODULE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
General Port Architecture. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Port Operating Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
MCU I/O Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
PLD I/O Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Address Out Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Peripheral I/O Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
JTAG In-System Programming (ISP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Port Configuration Registers (PCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Port Data Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Ports A and B – Functionality and Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Port C – Functionality and Structure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Port D – Functionality and Structure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
POWER MANAGEMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
PLD Power Management. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
PSD Chip Select Input (CSI, PD2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Input Clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Input Control Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
RESET TIMING AND DEVICE STATUS AT RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Warm RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
I/O Pin, Register and PLD Status at RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Reset of Flash Memory Erase and Program Cycles. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
PROGRAMMING IN-CIRCUIT USING THE JTAG SERIAL INTERFACE . . . . . . . . . . . . . . . . . . . . . . 95
Standard JTAG Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
JTAG Extensions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Security and Flash Memory Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
INITIAL DELIVERY STATE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
AC/DC PARAMETERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . 98
PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
PACKAGE MECHANICAL INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
6/123
µPSD33XX
Figure 3. TQFP52 Connections
(2)
PD1/CLKIN 1
PC7 2
39 P1.5/SPIRXD /ADC5
(2)
38 P1.4/SPICLK /ADC4
(2)
JTAG TDO 3
JTAG TDI 4
DEBUG 5
37 P1.3/TXD1(IrDA) /ADC3
(2)
36 P1.2/RXD1(IrDA) /ADC2
(2)
35 P1.1/T2X /ADC1
(2)
3.3V V
6
34 P1.0/T2 /ADC0
CC
(1)
33 V
PC4/TERR_ 7
DD
(1)
V
8
32 XTAL2
31 XTAL1
DD
GND 9
2
PC3/TSTAT 10
30 P3.7/I CSCL
2
PC2/V
11
29 P3.6/I CSDA
STBY
JTAG TCK 12
JTAG TMS 13
28 P3.5/C1
27 P3.4/C0
AI07822
Note: 1. For 5V applications, V must be connected to a 5.0V source. For 3.3V applications, V must be connected to a 3.3V source.
DD
DD
2. These signals can be used on one of two different ports (Port 1 or Port 4) for flexibility. Default is Port1.
3. V and 3.3V V are shared in the 52-pin package only. ADC channels must use 3.3V as V for the 52-pin package.
REF
CC
REF
7/123
µPSD33XX
Figure 4. TQFP80 Connections
60 P1.5/SPIRXD(2)/ADC5
59 P1.4/SPICLK(2)/ADC4
58 P1.3/TXD1(IrDA)(2)/ADC3
57 MCU A11
PD2 1
P3.3/TG1/EXINT1 2
PD1 3
ALE 4
56 P1.2/RXD1(IrDA)(2)/ADC2
PC7 5
55 MCU A10
JTAG TDO 6
JTAG TDI 7
DEBUG 8
54 P1.1/T2X(2)/ADC1
53 MCU A9
52 P1.0/T2(2)/ADC0
PC4/TERR_ 9
3.3V VCC 10
NC 11
51 MCU A8
(1)
50 VDD
(1)
49 XTAL2
VDD 12
48 XTAL1
GND 13
PC3/TSTAT 14
47 MCU AD7
46 P3.7/I2CSCL
45 MCU AD6
44 P3.6/I2CSDA
43 MCU AD5
42 P3.5/C1
PC2/VSTBY 15
JTAG TCK 16
NC 17
SPISEL_(2)/PCACLK1/P4.7 18
SPITXD(2)/TCM5/P4.6 19
JTAG TMS 20
41 MCU AD4
AI07823
Note: NC = Not Connected
1. For 5V applications, V must be connected to a 5.0V source. For 3.3V applications, V must be connected to a 3.3V source.
DD
DD
2. These signals can be used on one of two different ports (Port 1 or Port 4) for flexibility. Default is Port1.
8/123
µPSD33XX
Table 2. Pin Descriptions
80-
Pin
No.
Function
52-Pin
Signal
Name
Port Pin
In/Out
(1)
No.
Basic
Alternate 1
Alternate 2
External Bus
Multiplexed
Address/Data bus
A0/D0
MCUAD0
AD0
36
N/A
I/O
Multiplexed
Address/Data bus
A1/D1
MCUAD1
MCUAD2
MCUAD3
MCUAD4
MCUAD5
MCUAD6
MCUAD7
AD1
AD2
AD3
AD4
AD5
AD6
AD7
37
38
39
41
43
45
47
N/A
N/A
N/A
N/A
N/A
N/A
N/A
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Multiplexed
Address/Data bus
A2/D2
Multiplexed
Address/Data bus
A3/D3
Multiplexed
Address/Data bus
A4/D4
Multiplexed
Address/Data bus
A5/D5
Multiplexed
Address/Data bus
A6/D6
Multiplexed
Address/Data bus
A7/D7
External Bus, Addr
A8
MCUA8
MCUA9
MCUA10
MCUA11
P1.0
A8
A9
51
53
55
57
52
54
56
58
59
60
61
64
75
N/A
N/A
N/A
N/A
34
O
External Bus, Addr
A9
O
External Bus, Addr
A10
A10
O
External Bus, Addr
A11
A11
O
Timer 2 Count input ADC Channel 0
(T2) input (ADC0)
Timer 2 Trigger input ADC Channel 1
T2 ADC0
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
General I/O port pin
General I/O port pin
General I/O port pin
General I/O port pin
General I/O port pin
General I/O port pin
General I/O port pin
General I/O port pin
General I/O port pin
T2EX
ADC1
P1.1
35
(T2X)
input (ADC1)
RxD1
ADC2
UART1 or IrDA
Receive (RxD1)
ADC Channel 2
input (ADC2)
P1.2
36
TXD1
ADC3
UART or IrDA
Transmit (TxD1)
ADC Channel 3
input (ADC3)
P1.3
37
SPICLK
ADC4
SPI Clock Out
(SPICLK)
ADC Channel 4
input (ADC4)
P1.4
38
SPIRxD
ADC6
SPI Receive
(SPIRxD)
ADC Channel 5
input (ADC5)
P1.5
39
SPITXD
ADC6
SPI Transmit
(SPITxD)
ADC Channel 6
input (ADC6)
P1.6
40
SPISEL
ADC7
SPI Slave Select
(SPISEL)
ADC Channel 7
input (ADC7)
P1.7
41
UART0 Receive
(RxD0)
P3.0
RxD0
23
9/123
µPSD33XX
80-
Pin
No.
Function
52-Pin
Signal
Name
Port Pin
P3.1
In/Out
I/O
(1)
No.
Basic
Alternate 1
Alternate 2
UART0 Transmit
(TxD0)
TXD0
77
24
25
General I/O port pin
Interrupt 0 input
General I/O port pin (EXTINT0)/Timer 0
gate control (TG0)
EXINT0
TGO
P3.2
79
I/O
Interrupt 1 input
General I/O port pin (EXTINT1)/Timer 1
gate control (TG1)
P3.3
INT1
2
26
I/O
P3.4
P3.5
C0
C1
40
42
27
28
I/O
I/O
General I/O port pin Counter 0 input (C0)
General I/O port pin Counter 1 input (C1)
2
I C Bus serial data
2
P3.6
P3.7
44
46
29
30
I/O
I/O
General I/O port pin
I CSDA
2
(I CSDA)
2
I C Bus clock
2
General I/O port pin
I CSCL
2
(I CSCL)
Program Counter
Array0 PCA0-TCM0 (T2)
Timer 2 Count input
P4.0
P4.1
P4.2
P4.3
T2 TCM0
33
31
30
27
25
23
19
18
70
65
62
63
4
22
21
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
General I/O port pin
T2X
TCM1
Timer 2 Trigger input
(T2X)
General I/O port pin PCA0-TCM1
General I/O port pin PCACLK0
General I/O port pin PCACLK0
RXD1
TCM2
UART1 or IrDA
Receive (RxD1)
20
TXD1
PCACLK0
UART1 or IrDA
Transmit (TxD1)
18
SPICLK
TCM3
Program Counter
Array1 PCA1-TCM3 (SPICLK)
SPI Clock Out
P4.4
P4.5
P4.6
P4.7
17
General I/O port pin
SPIRXD
TCM4
SPI Receive
(SPIRxD)
16
General I/O port pin PCA1-TCM4
General I/O port pin PCA1-TCM5
General I/O port pin PCACLK1
SPI Transmit
(SPITxD)
SPITXD
15
SPISEL
PACCLK1
SPI Slave Select
(SPISEL)
14
Reference Voltage
input for ADC
V
N/A
N/A
N/A
N/A
N/A
44
REF
READ Signal,
external bus
RD_
WR_
O
WRITE Signal,
external bus
O
PSEN Signal,
external bus
PSEN_
ALE
O
Address Latch
signal, external bus
O
RESET_
IN_
Active low reset
input
68
48
49
8
I
Oscillator input pin
for system clock
XTAL1
XTAL2
DEBUG
31
I
Oscillator output pin
for system clock
32
O
I/O to the MCU
Debug Unit
5
I/O
10/123
µPSD33XX
80-
Pin
No.
Function
52-Pin
Signal
Name
Port Pin
In/Out
(1)
No.
Basic
Alternate 1
Alternate 2
PA0
PA1
35
34
32
28
26
24
22
21
80
78
76
74
73
71
67
66
20
16
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
52
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
General I/O port pin
General I/O port pin
General I/O port pin
General I/O port pin
General I/O port pin
General I/O port pin
General I/O port pin
General I/O port pin
General I/O port pin
General I/O port pin
General I/O port pin
General I/O port pin
General I/O port pin
General I/O port pin
General I/O port pin
General I/O port pin
JTAG pin (TMS)
All Port A pins
support:
1. PLD Macro-cell
outputs, or
2. PLD inputs, or
PA2
PA3
PA4
3. Latched Address
PA5
Out (A0-A7), or
4. Peripheral I/O
Mode
PA6
PA7
PB0
PB1
51
All Port B pins
support:
1. PLD Macro-cell
outputs, or
2. PLD inputs, or
3. Latched Address
Out (A0-A7)
PB2
50
PB3
49
PB4
48
PB5
46
PB6
43
PB7
42
JTAGTMS
JTAGTCK
TMS
TCK
13
12
I
JTAG pin (TCK)
SRAM Standby
voltage input
PLD Macrocell
output, or PLD input
V
STBY
PC2
15
11
I/O
General I/O port pin
(V
STBY
)
Optional JTAG
Status (TSAT)
PLD, Macrocell
output, or PLD input
PC3
PC4
TSTAT
TERR
14
9
10
7
I/O
I/O
General I/O port pin
General I/O port pin
Optional JTAG
Status (TERR)
PLD, Macrocell
output, or PLD input
JTAGTDI
TDI
7
6
4
3
I
JTAG pin (TDI)
JTAG pin (TDO)
JTAGTDO
TDO
O
PLD, Macrocell
output, or PLD input
PC7
5
2
I/O
General I/O port pin
1. PLD I/O
PD1
CLKIN
CSI
3
1
I/O
General I/O port pin
2. Clock input to
PLD and APD
1. PLD I/O
2. Chip select ot
PSD Module
PD2
1
N/A
I/O
General I/O port pin
3.3V-V
V
V
- MCU Module
- MCU Module
10
72
6
CC
CC
CC
3.3V-V
47
CC
V
V
V
- PSD Module
- 3.3V for 3V
- 5V for 5V
DD
DD
DD
V
DD
12
50
8
3.3V or 5V
V
V
V
- PSD Module
- 3.3V for 3V
- 5V for 5V
DD
DD
DD
V
DD
33
3.3V or 5V
GND
GND
GND
NC
13
29
69
11
17
9
19
45
N/A
N/A
NC
Note: 1. N/A = Signal Not Available on 52-pin package.
11/123
µPSD33XX
µPSD33XX HARDWARE DESCRIPTION
The µPSD33XX has a modular architecture with
two main functional modules: the MCU Module
and the PSD Module (see Figure 5). The MCU
Module consists of a fast 4-cycle 8032 core, pe-
ripherals, and other system-supporting functions.
The PSD Module provides configurable Program
and Data memories to the 8032 CPU core. In ad-
dition, it has its own set of I/O ports and a PLD with
16 macrocells for general logic implementation.
Ports A,B,C, and D are general purpose program-
mable I/O ports that have a port architecture which
is different from I/O Ports in the MCU Module.
The PSD Module communicates with the MCU
Module through the internal address, data bus
(A0-A15, D0-D7) and control signals (RD_, WR_,
PSEN_, ALE, RESET_). The user defines the De-
coding PLD in the PSDsoft Development Tool and
can map the resources in the PSD Module to any
program or data address space.
The modules have their own separate power sup-
ply pins. The MCU module runs at 3.3V while the
PSD module can be 3.3V or 5V, depending on the
device. The MCU module can interface to a 5V
PSD module as its I/O ports are 5V tolerant.
Figure 5. µPSD33XX Functional Modules
Port 3
I2C
Port 3 - UART0,
Port 4 - PCA,
PWM, UART1
Port 1 - Timer, ADC, SPI
Intr, Timers
MCU Module
Port 3
Port 1
VCC Pins
3.3V
Turbo 8032 Core
XTAL
Clock Unit
PCA
PWM
Counters
I2C
Unit
10-bit
ADC
SPI
Dual
3 Timer /
UARTs
Counters
Interrupt
256 Byte SRAM
Ext.
Bus
8032 Internal Bus
Dedicated Memory
Interface
Prefetch, Jump Cache
Reset Input
Reset
Pin
LVD
JTAG
DEBUG
Reset Logic
Internal
Reset
8-Bit Die to
WDT
Die Bus
Enhanced MCU Interface
PSD
Reset
Secondary
Flash
PSD Module
PSD Page Register
SRAM
Main Flash
Decode PLD
PSD Internal Bus
VDD Pins
3.3V or 5V
JTAG ISP
CPLD - 16 MACROCELLS
Port C
JTAG and
GPIO
uPSD33XX
Port D
GPIO
Port A,B,C PLD
I/O and GPIO
AI07842
12/123
µPSD33XX
MEMORY ORGANIZATION
The µPSD33XX Devices' fast 8032 Core has sep-
arate 64KB address spaces (see Figure 6) for Pro-
gram memory and Data Memory. Program
memory is where the 8032 executes instructions
from. Data memory is used to hold data variables.
Flash memory can be mapped in either program or
data space. The Flash memory consists of two
flash memory blocks: the main Flash and the Sec-
ondary Flash. Except during flash memory pro-
gramming or update, Flash memory can only be
read, not written to. A Page Register is used to ac-
cess memory beyond the 64K bytes address
space. Refer to the PSD Module for details on
mapping of the Flash memory. The 8032 core has
two types of data memory (internal and external)
that can be read and written. The internal SRAM
consists of 256 bytes, and includes the stack area.
The Special Function Registers (SFRs) occupy
the upper 128 bytes of the internal SRAM, the reg-
isters can be accessed by Direct addressing only.
There is a block of external SRAM in the
µPSD33XX which resides in the PSD Module that
can be mapped to any address space defined by
the user.
Program Memory
The program memory consists of two Flash mem-
ory: Main Flash (64K, 128K, or 256K Bytes) and
Secondary Flash (16K, 32K Bytes). The Flash
memory can be mapped to any address space as
defined by the user in the PSDsoft Tool. It can also
be mapped to Data memory space during Flash
memory update or programming.
After reset, the CPU begins execution from loca-
tion 0000h. Each interrupt is assigned a fixed loca-
tion in Program Memory. The interrupt causes the
CPU to jump to that location, where it commences
execution of the service routine. External Interrupt
0, for example, is assigned to location 0003h. If
External Interrupt 0 is going to be used, its service
routine must begin at location 0003h. If the inter-
rupt is not going to be used, its service location is
available as general purpose Program Memory.
The interrupt service locations are spaced at 8-
byte intervals: 0003h for External Interrupt 0,
000Bh for Timer 0, 0013h for External Interrupt 1,
001Bh for Timer 1 and so forth. If an interrupt ser-
vice routine is short enough (as is often the case
in control applications), it can reside entirely within
that 8-byte interval. Longer service routines can
use a jump instruction to skip over subsequent in-
terrupt locations, if other interrupts are in use.
Figure 6. µPSD33XX Memory Map and Address Space
Main
Flash
Ext. RAM
64KB,
128KB,
or
SFR
Int. RAM
2KB,
8KB,
or
Secondary
Flash
256KB
FF
Indirect
Addressing
Direct
Addressing
32KB
16KB
or
32KB
7F
0
Indirect
or Direct
Addressing
Internal RAM Space
256 bytes
External RAM
Space
Flash Memory Space
AI07843
13/123
µPSD33XX
Data Memory
XRAM-PSD
The internal data memory is divided into four phys-
ically separated blocks: 256 bytes of internal RAM,
128 bytes of Special Function Registers (SFRs),
and XRAM-PSD in the PSD Module.
The XRAM-PSD (2KB, 8KB, or 32KB) reside in the
PSD Module and can be mapped to any address
space
through the DPLD (Decoding PLD) as defined by
the user in PSDsoft Development tool. The XRAM-
PSD has a battery back-up feature that allows the
data to be retained in the event of a power outage.
The battery is connected to the Port C PC2 pin.
This pin must be configured in PSDSoft to be bat-
tery back-up.
RAM
Four register banks, each 8 registers wide, occupy
locations 0 through 31 in the lower RAM area.
Only one of these banks may be enabled at a time.
The next 16 bytes, locations 32 through 47, con-
tain 128 directly addressable bit locations. The
stack depth is only limited by the available internal
RAM space of 256 bytes.
8032 CORE PERFORMANCE ENHANCEMENTS
The µPSD33XX's CPU Core has implemented an
Instruction Pre-fetch Queue (PFQ) and a Branch
Cache (BC) to provide continuous code stream to
the execution unit. The codes are fetched from
PSD Module flash memory to be stored in the PFQ
and Branch Cache.
queue, then the CPU core will stall until the re-
quested byte is read and given to the CPU and
placed into the Pre-fetch Queue.
Branch Cache (BC)
This is a 4-word cache that maintains the destina-
tion instructions (six bytes) from the previous 4
jumps. When the CPU takes a jump or interrupt
that causes a non-sequential code access, the
Branch Cache is checked to see if it has a match
(address being jumped to). If the cache has a hit
(match) then the corresponding word of data is
transferred to the Pre-fetch Queue. At the same
time the instruction bytes at the target address is
supplied to the CPU. The Branch Cache must be
able to supply the destination instruction to the
CPU in time so that the CPU does not stall when
there is a cache hit to an even or odd address. If
there is a cache miss, then the CPU will stall until
the destination words are fetched and placed into
the Branch Cache. The Branch Cache will use
LRU algorithm to replace cache entries.
Instruction Pre-fetch Queue
The PFQ logic will fetch 8-bit data from the mem-
ories in the PSD Module. The logic will queue up
to 6 bytes from the program instruction stream and
will “feed” the requested bytes to the CPU core as
the instructions are executed. The Pre-fetch
Queue will make use of free memory bandwidth
and try to keep the Pre-fetch Queue full with the
next sequence of instructions. When a jump takes
place (non sequential code access) the Pre-fetch
Queue is cleared and will need to start over at from
the new address. The Pre-fetch Queue must be
able to “feed” instruction bytes to the CPU core so
that it does not stall when the corresponding byte
is in the queue. If the requested byte is not in the
14/123
µPSD33XX
MCU MODULE DISCRIPTION
This section provides a detail description of the
MCU Module system functions and Peripherals,
including:
– Special Function Registers
– Debug Unit
– MCU Bus Interface
– Supervisory Function (LVD and Watchdog)
– Timers/Counter
– UART
– IrDA Interface
– Interrupts
2
– I C Bus
– Power Saving Modes
– Oscillator and MCU Clock Generation
– I/O Ports
– SPI Bus
– ADC
– Programmable Counter Array (PCA)
Special Function Registers (SFRs)
A map of the on-chip memory area called the Spe-
cial Function Register (SFR) space is shown in Ta-
ble 3. The SFRs can only be addressed directly in
the address range from 80h to FFh. Sixteen ad-
dress in the SFR space are both: byte- and bit-ad-
dressable. The bit-addressable SFRs are those
whose address ends in 0h and 8h (as indicated by
* in the table).
Note: In the SFRs not all of the addresses are oc-
cupied. Unoccupied addresses are not implement-
ed on the chip and are reserved.
Table 3. SFR Memory Map
F8
F0
E8
E0
D8
D0
C8
CCON0
CCON2
CCON3
FF
F7
EF
E7
DF
D7
CF
*B
*ACC
*SCON1
*PSW
UDT1
UDT0
SBUF1
S1SETUP
SPISTAT
RCAP2H
S1CON
SPITDR
TL2
S1STA
SPIRDR
TH2
S1DAT
S1ADR
SPICLKD
RCAP2L
SPICON0 SPICON1
*T2CON
IRDACON
DSTAT
CAPCOM CAPCOM CAPCOM
CAPCOM CAPCOM CAPCOM
C0
B8
B0
A8
*P4
*IP
PWMF1
C7
BF
B7
AF
L3
H3
L4
H4
L5
H5
TCM
TCM
TCM
MODE5
PCACL1
PCACH1 PCACON1
MODE3
MODE4
CAPCOM CAPCOM CAPCOM
*P3
*IE
PWMF0
IPA
H1
L2
H2
TCM
TCM
TCM
CAPCOM CAPCOM
L0 H0
CAPCOM
L1
WDKEY
MODE0
MODE1
MODE2
A0
98
90
88
80
*P2
*SCON0
*P1
PCACL0
PCACH0 PCACON0 PCASTA
BUSCON
WDRST
DIR
IEA
DVR
A7
9F
97
8F
87
SBUF0
P3SFS
TMOD
SP
P4SFS0
TL0
P4SFS1
TL1
ADC0S
TH0
ADAT0
TH1
ADAT1
P1SFS0
PDTM
ACON
P1SFS1
PCON
*TCON
*P0
DPL
DPH
DPTC
15/123
µPSD33XX
Dual Data Pointers
Data read access to the program memory and
READ/WRITE access to the XRAM are executed
using the data pointer DPTR as a 16-bit address
register for indirect addressing mode. The DPTR
consists of a high byte (DPH, 83H) and a low byte
(DPL, 82H). Its intended function is to hold a 16-bit
address. It may be manipulated as a 16-bit register
or as two independent 8-bit registers.
The µPSD33XX has two data pointers (DPTR0
and DPTR1), one of which is selected by Bit
DPSEL0 in the Data Pointer Control Register
DPTC. After reset, these registers are set to “00H.”
Only one DPTR is active at any time, and the se-
lected PDTR resides in SFR address 83H and
82H. The DPTR which is not selected remains in
the background and is not accessible by the CPU.
Data Pointer Control Register, DPTC (85H)
The control register allows the DPTR to be select-
ed manually, or automatically switching between
the two data pointers. Bit DPSEL0 selects one of
two pointers. The automatic switching between
DPTR0 and DPTR1 is controlled by Bit AT (Auto
Toggle). When Bit AT is set, Bit DPSEL0 is toggled
automatically every time after the DPTR is access-
ed. Detailed description for register DPTC is
shown in Table 4 and Table 5.
The data pointer currently selected by the PSEL0
Bit can be modified, whereas the other data point-
ers are kept in the background and remain un-
changed.
Table 4. Data Pointer Control Register, DPTC, Bit Definition (85H, Reset Value 00H)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
–
AT
–
–
–
–
–
DPSEL0
Table 5. Data Pointer Control Register Details
BIT
SYMBOL
RW
Definition
7
–
Reserved
0 = Manual Select Data Pointer
6
5-1
0
AT
–
RW
1 = Auto Toggle between DPTR0 and DPTR1
Reserved
0 = DPTR0 Selected
1 = DPTR1 Selected
DPSE0
RW
Note: Standard increment instruction on Register DPTC can be used to toggle Bit DPSEL0.
16/123
µPSD33XX
Data Pointer Mode Register, DPTM (86H)
The µPSD33XX provides automatic increment or
decrement of content of the working DPTR
through the DPTM register. The content of the
working DPTR is modified at the access time. De-
tailed description for DPTM is shown in Table 6
and Table 7.
The automatic decrement or increment function in
the DPTM Register is effective only for the MOVX
instruction.
Table 6. Data Pointer Mode Register, DPTM Bit Definition (86H, Reset Value 00H)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
–
–
–
–
MD11
MD10
MD01
MD00
Table 7. Data Pointer Mode Register Details
BIT
SYMBOL
RW
Definition
7-4
–
Reserved
DPTR1 Mode Bits
00: DPTR1 No Change
01: Reserved
10: Auto Increment
11: Auto Decrement
3-2
MD[11:10]
MD[01:00]
RW
DPTR0 Mode Bits
00: DPTR0 No Change
01: Reserved
1-0
RW
10: Auto Increment
11: Auto Decrement
Debug Unit
The MCU Module has a Debug Unit which sup-
ports debugging functions that are required in new
PC board development. The JTAG port in the
µPSD33XX is responsible for communications be-
tween the host development system and the De-
bug Unit. The basic debugging functions
supported include:
– Halt or Start CPU execution
– Reset the CPU
– Single Step
– Four breakpoints, breaks on address/data
– Debug Interrupt to CPU at breakpoint
– Program tracing
– READ/WRITE to SFR, PC and Memory
The Debug pin can be configured in the host sys-
tem to generate an output pulse for external trig-
gering when a break condition is met. It can also
be configured as an event input to the breakpoint
logic in the Debug Unit. If not used, this pin should
be pulled high.
17/123
µPSD33XX
INTERRUPT SYSTEM
There are interrupt requests from 10 sources as
follows:
of their respective Timer/Counter registers
(except for Timer 0 in Mode 3).
■ Debug Interrupt
– These flags are cleared by the internal
hardware when the interrupt is serviced.
Timer 2 Interrupt
■ INT0 External Interrupt
■ UART0 and UART1 Interrupt
■ Timer 0 Interrupt
– Timer 2 Interrupt is generated by TF2 which
is set by an overflow of Timer 2. This flag has
to be cleared by the software - not by
hardware.
– It is also generated by the T2EX signal (Timer
2 External Interrupt P1.1) which is controlled
by EXEN2 and EXF2 Bits in the T2CON
register.
2
■ I C Interrupt
■ INT1 External Interrupt
■ ADC Interrupt
■ Timer 1 Interrupt
■ SPI Interrupt
■ Timer 2 Interrupt
■ PCA Interrupt
2
I C Interrupt
2
– The interrupt of the I C is generated by Bit
External Int0
INTR in the register S1STA.
– This flag is cleared by hardware.
External Int1
– The INT0 can be either level-active or
transition-active depending on Bit IT0 in
register TCON. The flag that actually
generates this interrupt is Bit IE0 in TCON.
– The INT1 can be either level-active or
transition-active, depending on Bit IT1 in
register TCON.
The flag that actually generates this interrupt
is Bit IE1 in TCON.
– When an external interrupt is generated, the
corresponding request flag is cleared by the
hardware when the service routine is
vectored to, but only if the interrupt was
transition-activated.
– If the interrupt was level-activated, then the
interrupt request flag remains set until the
requested interrupt is actually generated. It
then has to deactivate the request before the
interrupt service routine is completed, or else
another interrupt will be generated.
– When an external interrupt is generated, the
corresponding request flag is cleared by the
hardware when the service routine is
vectored to only if the interrupt was transition
activated.
– If the interrupt was level activated then the
interrupt request flag remains set until the
requested interrupt is actually generated.
Then it has to deactivate the request before
the interrupt service routine is completed, or
else another interrupt will be generated.
Timer 0 and 1 Inputs
– Timer 0 and Timer 1 Interrupts are generated
by TF0 and TF1 which are set by an overflow
18/123
µPSD33XX
ADC Interrupt
UART Interrupt
– The ADC unit generates an interrupt when
conversion is completed and AINTEN Bit of
the ACON register is set.
– After the interrupt is served, software needs
to clear the interrupt flag AINTF.
– The UART Interrupt is generated by RI
(Receive Interrupt) or TI (Transmit Interrupt).
– When the UART Interrupt is generated, the
corresponding request flag must be cleared
with software. The interrupt service routine
will have to check the various UART registers
to determine the source and clear the
corresponding flag.
– Both UARTs are identical, except for the
additional interrupt controls in the Bit 4 of the
additional interrupt control registers (A7H,
B7H).
PCA Interrupt
– Each of the 6 TCMs can generate a "match or
capture" interrupt when enabled. The two 16-
bit counters can also generate two counter
overflow interrupts.
– The 8 PCA interrupts are "ORed" to generate
one interrupt to the CPU.
Debug Interrupt
– After serving the interrupt, the software has to
clear the flag in the Status register.
– The Debug unit generates an interrupt when
a Breakpoint condition is met.
– The interrupt has the highest priority.
SPI Interrupt
– The SPI can generate interrupt when the
receive buffer is full and the transmission
buffer is empty.
– An interrupt can also be generated at the end
of transmission or receive overrun.
After the interrupt is served, the software
needs to clear the interrupt flag in the status
register.
19/123
µPSD33XX
Figure 7. Interrupt System
Priority
High
Interrupt
Sources
IE/IEA
IP/IPA
Debug
Low
Ext
INT0
Timer 0
Ext
INT1
Timer 1
UART0
Timer 2
SPI
Reserved
2
I C
ADC
PCA
UART1
Global
Enable
AI07844
20/123
µPSD33XX
Interrupt Priority Structure
Each interrupt source can be assigned one of two
priority levels. Interrupt priority levels are defined
by the Interrupt Priority special function registers
IP and IPA.
0 = low priority
1 = high priority
received simultaneously, an internal polling se-
quence determines which request is serviced.
Thus, within each priority level, there is a second
priority structure determined by the polling se-
quence.
Interrupts Enable Structure
A low priority interrupt may be halted by a high pri-
ority level interrupt. A high priority interrupt routine
cannot be halted by any other interrupt source. If
two interrupts of different priority occur simulta-
neously, the higher priority level request is ser-
viced. If requests are of the same priority and are
Each interrupt source can be individually enabled
or disabled by setting or clearing a bit in the Inter-
rupt Enable special function register IE and IEA.
All interrupt sources can also be globally disabled
by clearing Bit EA in the IE register.
Table 8. Priority Level
Priority
SOURCE
DEBUG
VECTOR ADDRESS
0063H
0 (Highest)
1
2
ExtINT0
Timer 0
0003H
000BH
3
ExtINT1
Timer 1
0013H
4
001BH
5
UART0
0023H
6
Timer 2 + EXF2
SPI
002BH
7
0053H
8
Reserved
0033H
2
9
0043H
I C
10
11
12
ADC
PCA
003BH
005BH
UART1
004BH
Table 9. Interrupt SFR
Bit Register Name
SFR
Addr
Reg
Name
Reset
Value
Comments
7
6
5
4
3
2
1
0
Interrupt
Enable (2nd)
2
A7
A8
B7
B8
IEA
IE
ADC
SPI
PCA
ES1
–
–
00
EI C
Interrupt
Enable
EA
PADC
–
EDB
PSPI
PDB
ET2
PPCA
PT2
ES0
PS1
PS0
ET1
–
EX1
–
ET0
EX0
00
00
00
Interrupt
Enable (2nd)
2
IPA
IP
PI C
Interrupt
Priority
PT1
PX1
PT0
PX0
21/123
µPSD33XX
Table 10. Interrupt Enable SFR IE Bit Definition (A8H)
BIT
SYMBOL
FUNCTION
Disable all interrupts.
0 = No interrupt will be acknowledged
1 = Each interrupt source is individually enabled or disabled by setting or clearing its
enable bit.
7
EA
6
5
4
3
2
1
0
EDB
ET2
ES0
ET1
EX1
ET0
EX0
Debug Unit Interrupt
Enable Timer 2 Interrupt
UART0 Interrupt
Enable Timer 1 Interrupt
Enable External Interrupt (INT1)
Enable Timer 0 Interrupt
Enable External Interrupt (INT0)
Table 11. Interrupt Enable Addition SFR IEA Bit Definition (A7H)
BIT
7
SYMBOL
EADC
ESPI
EPCA
ES1
FUNCTION
ADC Interrupt
6
SPI Interrupt
5
Programmable Counter Array Interrupt
UART1 Interrupt
Reserved
4
3
–
2
–
Reserved
2
2
1
EI C
Enable I C Interrupt
0
–
Reserved
Table 12. Interrupt Priority Level SFR IP Bit Definition (B8H)
BIT
7
SYMBOL
–
FUNCTION
Reserved
6
PDB
PT2
Debug Interrupt Level
5
Timer 2 Interrupt priority level
UART0 Interrupt priority level
Timer 1 Interrupt priority level
External Interrupt (INT1) priority level
Timer 0 Interrupt priority level
External Interrupt (INT0) priority level
4
PS0
PT1
3
2
PX1
PT0
1
0
PX0
22/123
µPSD33XX
Table 13. Interrupt Priority Level Addition SFR IPA Bit Definition (B7H)
BIT
7
SYMBOL
PADC
PSPI
PPCA
PS1
FUNCTION
ADC Interrupt priority level
SPI Interrupt priority level
PCA Interrupt level
UART1 Interrupt priority level
Not used
6
5
4
3
–
2
–
Not used
2
2
1
0
PI C
I C Interrupt priority level
–
Reserved
POWER SAVINGS MODES
Three software-selectable modes of reduced pow-
er consumption are implemented.
The following functions remain active during Idle
Mode (except when disabled by the control regis-
ters). Some of these functions may generate an in-
terrupt or reset and thus terminate the Idle Mode.
■ Idle Mode
■ Power-down Mode
■ Reduced Frequency Mode
Idle Mode Function Activity
The following functions are switched off when the
microcontroller enters the Idle Mode:
– External Interrupts
– Timer 0, Timer 1 and Timer 2
– Watchdog Timer
– ADC
2
– I C Bus Interface
– CPU (halted - waiting for interrupt to exit halt)
– UART0 and UART1
– ADC
– SPI
– PCA (PWM)
Table 14. Port Status at Power-saving Mode
2
Mode
Idle
Ports 1, 3, 4
Maintain Data
Maintain Data
PCA
Active
Disable
SPI
ADC
Active
Disable
I C
Active
Disable
Active
Disable
Power-down
Table 15. Bus Signals at Power-down and Idle Mode
Mode
Idle
ALE
PSEN_
RD_
WR_
AD0-7
A8-15
FF
0
0
1
1
1
1
1
1
FF
FF
Power-down
FF
23/123
µPSD33XX
Idle Mode
The instruction that sets PCON.0 is the last in-
struction executed in the normal operating mode
before Idle Mode is activated. Once in the Idle
Mode, the CPU status is preserved in its entirety:
Stack pointer, Program counter, Program status
word, Accumulator, RAM, and All other registers
maintain their data during Idle Mode.
– External hardware reset: the hardware reset
is required to be active for two machine
cycles to complete the RESET operation.
– Internal reset: the microcontroller restarts
after 3 machine cycles in all cases.
Power-down Mode
The instruction that sets PCON.1 is the last exe-
cuted prior to going into the Power-down Mode.
Once in Power-down Mode, the oscillator is
stopped. The contents of the on-chip RAM and the
Special Function Register are preserved.
The Power-down Mode can be terminated by an
external RESET.
There are three ways to terminate the Idle Mode:
– Activation of any enabled interrupt will cause
PCON.0 to be cleared by hardware,
terminating Idle Mode. The interrupt is
serviced, and following return from interrupt
instruction, RETI, the next instruction to be
executed will be the one which follows the
instruction that wrote a logic '1' to PCON.0.
Table 16. PCON Register Bit Definition (87H, Reset Value 00H)
BIT
SYMBOL
FUNCTION
Baud Rate Double Bit (UART0)
0 = No Doubling
7
SMOD0
1 = Doubling
Baud Rate Double Bit for 2nd UART (UART1)
0 = No Doubling
1 = Doubling
6
5
4
SMOD1
LVD
Disable LVD by setting this bit.
0 = Enable
1 = Disable
Power-on reset sets this bit to '1.' See SUPERVISORY, page 31 for details.
0 = Clear with software
POR
1 = Set by power-on reset generated by Supervisory circuit
(1)
3
2
Received Clock Flag (UART1)
Transmit Clock Flag (UART1)
RCLK1
(1)
TCLK1
Activate Power-down Mode
0 = Exit from Power-down
1 = Enter into Power-down
1
0
PD
Activate Idle Mode
0 = Exit from Idle Mode
1 = Enter into Idle Mode
IDL
Note: 1. See the T2CON Register (Table 38, page 38) for details of the flag description.
24/123
µPSD33XX
REDUCED FREQUENCY MODE
The MCU consumes less power at lower clock fre-
quency than at maximum frequency. The MCU
can reduce the clock frequency by dividing the
vider the MCU returns to normal mode. See
CLOCK GENERATION, page 25 for more infor-
mation.
f
with the divider as defined in CCON0 Regis-
OSC
In Reduced Frequency Mode, the Peripherals can
ter (see Figure 8). This mode allows the MCU to
remain active while consuming less power at a
slower speed. By changing back to the original di-
still be functional at normal f
frequency.
OSC
Figure 8. Clock Generation Logic
PCON[1] : Power Down
MUX
PCON[0]: IDLE
Buffer
XTAL1
XTAL1
CPUCLK
(CPU, WDT, IO_PORT)
XTAL1 / 2
Q
STALL
XTAL1 / 4
Q
•
CPUCLK_nonstop
(DBG, IRU)
•
•
XTAL1 / 2048
Q
CPU CLK_muxout
PFQCLK
(PFQ)
[Clock Divider]
CPUPS
OSCCLK
(TIMER0/1/2, UART0/1,
PCA0/1, SPI,ADC)
AI07845
Note: 1. XTAL can be divided by 2 to 2048.
CLOCK GENERATION
The clock unit uses the external crystal oscillator
as a reference input clock, whose frequency is de-
breakpoint match or when the CPU is put in the
halt state by the Debug Unit.
noted by F
. Based on the Frequency Selection
OSC
CPUCLK_nonstop. A clock for CPU-loosely-re-
lated peripherals (e.g., Debug, Interrupt). This
clock is the same as CPUCLK, except this clock is
alive in Idle Mode.
Control registers (CCON0), the clock unit gener-
ates the following clocks:
CPUCLK. A clock for CPU and CPU-tightly-relat-
ed peripherals (e.g., JTAG, WDT, IO_PORT). This
clock is disabled in both the Power-down Mode
and the Idle Mode. The frequency of CPUCLK is
PFQCLK. A clock for PFQ. This clock is same as
CPUCLK except that this is alive even in Idle Mode
or when the CPU is stalled.
OSCCLK. A clock for non-CPU related peripher-
als (e.g., TIMER0/1/2, UART0/1, PCA0/1, SPI).
f
, which is obtained based on the f
, CP-
CPU
OSC
UPS[2:0], and internal signals Idle, and Stall.
When 'Idle' is 1, f is 0MHz. Otherwise, f is
a function of f
Stall signal is generated from the Pre-fetch Queue
(PFQ) block when the requested program code is
not prepared in PFQ yet. CPUCLK is alive after a
CPU
CPU
The frequency of OSCCLK is f
, which is ob-
OSC
, CPUPS[2:0], and Stall. The
OSC
tained from the external clock input. This clock is
disabled only in the Power-down Mode.
The clock status is summarized in Table 17, page
26.
25/123
µPSD33XX
Table 17. Clock Status
Name
Power-saving Modes
Modules
Freq.
NORMAL
ON
IDLE
PD
f
CPUCLK
CPUCLK_nonstop
PFQCLK
CPU, JTAG, WDT, IO_PORT
OFF
OFF
OFF
OFF
OFF
OFF
CPU
f
Debug, Interrupt
PFQ
ON
ON
ON
ON
CPU
f
CPU
f
JTAGCLK
JTAG
JTAG
(1)
2
f
OSC
OSCCLK
TIMER0/1/2, UART0/1, PCA0/1, SPI, I C, ADC
Note: 1. OSCCLK is the output of the crystal oscillator.
CPU CLOCK CONTROL REGISTER
The CPU Clock frequency is controlled by the
CCON0 Register. The CPU is running at full fre-
quency at power-up. The CPU Clock frequency
can be changed any time by writing to the CPUPS
Bits in the CCON0 register. After writing to the
CCON0, the CPU Clock will be switched to the
new frequency immediately. The CPU Clock can
be reduced by dividing the f by 2 to 2048.
When the CPU is running at reduced clock fre-
quency and the CPUAR Bit is set, it allows the
CPU Clock to return to full frequency immediately
when any interrupt occurs. This is achieved by au-
tomatically changing the CPUPS Bits to '000.'
OSC
Table 18. CCON0 Register Bit Definition (0F9H, Reset Value 10H)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reserved
Reserved
Reserved
DBGCE
CUPAR
CPUPS[2:0]
Table 19. CCON0 Register Bit Definition Details
BIT
SYMBOL
RW
Definition
7-5
–
Reserved
Debug Address Comparison Enable
0 = DBG Address Comparison is disabled
1 = DBG Address Comparison is enabled (Default during the reset
4
3
DBGCE
CPUAR
RW
RW
period.)
After reset, this bit is set to enable the Debug Unit’s Address
Comparison feature for debugging purposes. This bit should be
set to '0' if the debugging function is not needed.
Automatic CPU Clock Recovery
0 = There is no change of CPUPS[2:0] when an interrupt occurs.
1 = CPUPS[2:0] becomes 3’b000 whenever any interrupt occurs.
CPUCLK Pre-Scaler
000: f
001: f
010: f
011: f
100: f
101: f
110: f
= f
= f
= f
= f
(Default during the reset period)
CPU
CPU
CPU
CPU
CPU
CPU
CPU
CPU
OSC
OSC
OSC
/2
/4
/8
/16
/32
2:0
CPUPS
RW
OSC
= f
= f
= f
= f
OSC
OSC
OSC
/1024
/2048
111: f
OSC
26/123
µPSD33XX
OSCILLATOR
The oscillator circuit of the µPSD33XX Devices is
a single stage, inverting amplifier in a Pierce oscil-
lator configuration. The circuitry between XTAL1
and XTAL2 is basically an inverter biased to the
transfer point. Either a crystal or ceramic resonator
can be used as the feedback element to complete
and XTAL2 is the output. To drive the µPSD33XX
Devices externally, XTAL1 is driven from an exter-
nal source and XTAL2 left open-circuit.
The µPSD33XX can run at maximum 40MHz
clock. The CPU clock frequency can be configured
2
in the CCON0 Register. However, the I C bus re-
the oscillator circuit. Both are operated in parallel
resonance. XTAL1 is the high gain amplifier input,
quires a minimum 8MHz clock to be functional.
Figure 9. Oscillator
XTAL1
XTAL2
XTAL1
XTAL2
8 to 40 MHz
External Clock
AI06620
I/O PORTS (MCU MODULE)
The MCU Module has three ports: Port 1, Port 3,
and Port 4 (see Table 20). (Refer to the PSD
MODULE, page 65 and I/O PORTS (PSD MOD-
ULE), page 84). The ports support:
with the exception of the additional special periph-
eral functions. All ports are bi-directional. Pins
which are not configured as Alternate functions
are normally bi-directional I/O.
■ General Purpose I/O
■ Alternate peripheral functions
■ 5V tolerant
The following SFR registers are used to control the
mapping of alternate functions onto the I/O Port
Bits (see Table 21 and Table 22). Port 1 and 4 al-
ternate functions are controlled using the PXSFS1
registers. Port 3 alternate functions are controlled
using the P3SFS register. After reset, the port SFR
registers are cleared and are defaulted to general
I/O.
■ High current on Port 4
The 80-pin µPSD33XX also has two ports in the
MCU Module that are dedicated for the external
MCU address and data bus. Ports 1, 3, and 4 are
the same as in the standard 8032 microcontrollers,
Table 20. I/O Port Functions
Port Name
General Purpose I/O
Alternate 1 Function
Alternate 2 Function
Timer 2 - Pins 0, 1
UART1 - Pins 2, 3
SPI - Pins 4.. 7
Port 1
GPIO
ADC - PIns 0.. 7
UART0 - Pins 0, 1
Interrupt - Pins 2, 3
Timers - Pins 4, 5
Port 3
Port 4
GPIO
GPIO
None
2
I C - Pins 6, 7
Timer 2 - Pins 0, 1
UART1 - Pins 2.. 3
SPI - Pins 4.. 7
PCA0 - Pins 0.. 3
PCA1 - Pins 4-7
27/123
µPSD33XX
Port 1 Register P1SFS0, Port 1 Register P1SFS1
P1SFS0 Register Bits 0.. 7 definition (see Table
21):
0 = Select pin as GPIO
When the bit in the P1SFS0 register is '1,’ alter-
nate peripheral functions are assigned to the pin.
The new P1SFS1 register bit further selects which
one of the alternate function to be enabled. Table
22 shows the alternate functions assigned to port
1 and how it can be selected.
1 = Select pin as Alternate function
Table 21. Port 1 Register P1SFS0 (8EH, Reset Value 00H)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0 = Port 1.7 0 = Port 1.6 0 = Port 1.5 0 = Port 1.4 0 = Port 1.3 0 = Port 1.2 0 = Port 1.1 0 = Port 1.0
1 = Alternate 1 = Alternate 1 = Alternate 1 = Alternate 1 = Alternate 1 = Alternate 1 = Alternate 1 = Alternate
Table 22. Port 1 Register P1SFS1 (8FH, Reset Value 00H)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0 = Alternate1 0 = Alternate1 0 = Alternate1 0 = Alternate1 0 = Alternate1 0 = Alternate1 0 = Alternate1 0 = Alternate1
1 = Alternate2 1 = Alternate2 1 = Alternate2 1 = Alternate2 1 = Alternate2 1 = Alternate2 1 = Alternate2 1 = Alternate2
Port 3 Configuration Register
Port 3 configuration is compatible to standard
8032, including alternate function pin assignments
as shown in Table 23.
Port 1 function has priority and the Port 4 function
is disabled.
P4SFS0 Register Bits 0.. 7 definition:
0 = Select pin as GPIO
Port 4 Configuration Register
Port 4 has two registers: P4SFS0 Bit = 0 config-
ures pin as GPIO and Bit = 1 configures pin as al-
ternate function. P4SFS1 Bit determines which
alternate function is to be enabled (see Table 24).
The alternate 2 functions on Port 4 are the same
as the alternate function 1 of Port 1. If an identical
alternate function is assigned to both ports, the
1 = Select pin as Alternate function
Port 4 High Current Option
Port 4 is a high current port (see Table 25). All 8 of
the port pins are capable of a sink/source value of
10mA per pin in alternative function mode. The
pins can sink 10mA in GPIO Mode. See the DC
AND AC PARAMETERS, page 98, for V /V
OL OH
specification on Port 4.
Table 23. Port 3 Register P3SFS (91H, Reset Value 00H)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0 = Port 3.7 0 = Port 3.6 0 = Port 3.5 0 = Port 3.4 0 = Port 3.3 0 = Port 3.2 0 = Port 3.1 0 = Port 3.0
1 = Alternate 1 = Alternate 1 = Alternate 1 = Alternate 1 = Alternate 1 = Alternate 1 = Alternate 1 = Alternate
Table 24. Port 4 Register P4SFS0 (92H, Reset Value 00H)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0 = Port 4.7 0 = Port 4.6 0 = Port 4.5 0 = Port 4.4 0 = Port 4.3 0 = Port 4.2 0 = Port 4.1 0 = Port 4.0
1 = Alternate 1 = Alternate 1 = Alternate 1 = Alternate 1 = Alternate 1 = Alternate 1 = Alternate 1 = Alternate
Table 25. Port 4 Register P4SFS1 (93H, Reset Value 00H)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0 = Alternate1 0 = Alternate1 0 = Alternate1 0 = Alternate1 0 = Alternate1 0 = Alternate1 0 = Alternate1 0 = Alternate1
1 = Alternate2 1 = Alternate2 1 = Alternate2 1 = Alternate2 1 = Alternate2 1 = Alternate2 1 = Alternate2 1 = Alternate2
28/123
µPSD33XX
MCU MEMORY BUS INTERFACE
The MCU Module reads or writes to the PSD Mod-
ule through the MCU memory bus. The Memory
Bus is also available to external pins in the 80-pin
package. The 8-bit MCU bus consists of standard
8032 bus signals.
Bus Control Register (BUSCON)
The µPSD33XX has a programmable bus inter-
face where the user can specify the length of a bus
cycle. Based on the PQF Clock frequency, the
number of clocks in a bus cycle can be changed to
maximize data transfer rate (see Table 27). The
µPSD33XX defaults to 6 PFQ clock for all READ
and WRITE bus cycles after reset. Table 28 shows
the minimum number of PFQ clocks in a bus cycle
that are required for different PFQ Clock frequen-
cies.
In addition, the BUSCON allows the user to set
bits to turn on/off the Prefetch Queue and Branch
Cache. In some real time applications, turning off
the queue and cache provides determinable exe-
cution. The user may also wish to turn the queue
and cache off during debugging.
READ Bus Cycle (Code or XDATA)
The READ bus cycle reads 8 bits per bus cycle
and is identical for both the Program Fetch (PSEN)
and Data Read (RD) in terms of timing and func-
tion. When the PSD Module is selected and either
PSEN or RD is active, the PSD Module will drive
data D0-D7 of the MCU bus. For program fetch,
the MCU keeps the byte in the Pre-fetch Buffer. As
for the XDATA READ bus cycle, the MCU routes
the data byte to the CPU core directly. The READ
bus cycle timing and length is controlled by the
BUSCON Register.
WRITE Bus Cycle (XDATA)
The MCU writes one byte per bus cycle. The tim-
ing and length of the WRITE Bus Cycle is con-
trolled by the BUSCON Register, which can be
programmed by the software.
Table 26. BUSCON Register Bit Definition (9DH, Reset Value 2BH)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
EPFQ
EBC
WRW1
WRW0
RDW1
RDW0
CW1
CW0
Table 27. Number of PFQ Clocks Required to Optimize Bus Transfer Rate
Code Data
READ Data
WRITE Data
PFQ Clock
Frequency
(1)
(1)
(1)
(1)
(1)
(1)
3V
5V
3V
5V
3V
5V
25-40MHz
8-24MHz
5
4
5
4
4
5
4
4
3
3
4
4
Note: 1. V of the PSD Module
DD
29/123
µPSD33XX
Table 28. BUSCON Register Bit Definition Details
Register Bit
Definition
Code Fetch bus cycle:
When PFQ fetches code,
2’b00: The code read from memory takes 3 PFQCLK clocks
2’b01: The code read from memory takes 4 PFQCLK clocks
2’b10: The code read from memory takes 5 PFQCLK clocks
2’b11: The code read from memory takes 6 PFQCLK clocks (default)
CW1.. CW0
XDATA READ bus cycle:
2’b00: The code read from XDATA takes 4 PFQCLK clocks
2’b01: The code read from XDATA takes 5 PFQCLK clocks
2’b10: The code read from XDATA takes 6 PFQCLK clocks (default)
2’b11: The code read from XDATA takes 7 PFQCLK clocks
RDW1.. RDW0
WRW1.. WRW0
XDATA WRITE bus cycle
2’b00: The code read from XDATA takes 4 PFQCLK clocks
2’b01: The code read from XDATA takes 5 PFQCLK clocks
2’b10: The code read from XDATA takes 6 PFQCLK clocks (default)
2’b11: The code read from XDATA takes 7 PFQCLK clocks
Enable Branch Cache
0 = BC is disabled (default)
1 = BC is enabled
EBC
Enable Prefetch Queue
0 = PFQ is disabled (default)
1 = PFQ is enabled
EPFQ
30/123
µPSD33XX
SUPERVISORY
There are four ways to invoke a reset and initialize
the µPSD33XX Devices:
■ Via the external RESET pin
■ Via the internal LVR Block.
■ Via Watch Dog timer
Each RESET source will cause an internal reset
signal to be active. The CPU responds by execut-
ing an internal reset and puts the internal registers
in a defined state. This internal reset is also routed
as an active low reset input to the PSD Module.
Figure 10. RESET Configuration
RESET
Input Pin
Noise
CPU
&
PERI.
CPU
Clock
Sync
Cancel
WDT
Q
S
R
LVR
Debug
(1)
10ms
Timer
PSD_RST
"Active Low signal"
AI07849
Note: 1. 10ms at 40MHz, 50ms at 8MHz.
External Reset
Watchdog Timer Overflow Reset
The RESET pin is connected to a Schmitt trigger
for noise reduction. A RESET is accomplished by
holding the RESET pin LOW for at least 1ms at
power-up while the oscillator is running. Refer to
AC specification on other RESET timing require-
ments.
The Watchdog timer generates an internal reset
when its 24-bit counter overflows. See WATCH-
DOG TIMER, page 32 for details.
Debug Unit Reset
The Debug Unit can generate a reset to the Super-
visory circuit for debugging purpose. Under normal
operation, this reset source is disabled.
Low V Voltage Reset
CC
An internal reset is generated by the LVR circuit
Reset Output
when the V drops below the reset threshold. Af-
CC
The output of the reset logic resets the MCU, it
also drives a PSD_Reset signal (active low) which
is connected to the Reset Input on the PSD Mod-
ule. The output of the reset logic remains asserted
for a minimum of approximately 10ms. This time
ter V returns to the reset threshold, the RESET
CC
signal will remain asserted for 10ms before it is re-
leased. On initial power-up the LVR is enabled
(default). After power-up the LVR can be disabled
via the LVREN Bit in the PCON Register.
Note: The LVR logic is functional in both the Idle
and Power-down Modes. The reset circuit resides
base is calculated by counting the f
at 40Mhz
OSC
to last a minimum of 10ms at 40Mhz. The time will
be longer as the f
is lower.
OSC
in the MCU Module which operates at 3.3V V
.
CC
Power-up Reset
The reset threshold will always be: 2.5V +/-0.2V
for all µPSD33XX devices.
This logic supports approximately 0.1V of hystere-
sis and 1µs noise-cancelling delay.
At power up, the internal reset generated by the
LVD circuit is latched as a '1' in the PCON register
(Bit POR). Software can read this bit and deter-
mine whether the last CPU reset is a power up or
warm reset. This bit must be cleared with software.
31/123
µPSD33XX
WATCHDOG TIMER
The hardware watchdog timer (WDT) resets the
µPSD33XX Devices when it overflows. The WDT
is intended as a recovery method in situations
where the CPU may be subjected to a software
upset. To prevent a system reset the timer must be
reloaded in time by the application software. If the
processor suffers a hardware/software malfunc-
tion, the software will fail to reload the timer. This
failure will result in a reset upon overflow thus pre-
venting the processor running out of control.
SFR, and the Watchdog Key Register (WDKEY).
Since the WDKEY register is loaded with 55h after
reset, the Watchdog is disabled until it is enabled
by the software.
Watchdog Counter
The 24-bit counter runs on machine cycle (4 f
OSC
clocks) and has a WDT reset period of about 1.6
seconds (see Figure 11). The 8th MSB of the
counter is loaded from the Watch Dog Timer Clear
Register (WDRST). By writing to the WDRST reg-
ister, the user can change the WDT reset period.
The 24-bit counter overflows when it reaches
FFFFFFh.
In the Idle Mode the watchdog timer and reset cir-
cuitry remain active. The WDT consists of a 24-bit
counter, the Watchdog Timer RESET (WDRST)
Figure 11. Watchdog Counter
23
15
7
0
8 bit
8 bit
8 bit
WDTRST
AI07850
machine cycle = (4T
+ T
)
STALL
OSC
1
where, T
= -------------------= 0.025us = 25ns
OSC
40MHz
T
: the average waiting time due to PFQ/BC stall
STALL
For example, when t
is '0' and t
is 25ns, the total required cycle (to reach the overflow of the 24-
OSC
STALL
bit counter that is clocked at machine cycle) is as below:
2
10
24
2
26
6
20
2
× 2 = 2
= 2 × 2 = 64 × (2
)
= 64 million (OSCcycle)
Therefore, the reset period is:
reset period = 64M × 25ns = 1.6s
32/123
µPSD33XX
WDT Registers
WDTKEY Register
– When this SFR is written as #55h, the WDT is
disabled. Otherwise, writing any other values
to the register will disable the WDT. Since the
reset value of WDTKEY is #55h, the WDT is
disabled at reset. The WDT is disabled after
the reset that is generated by the WDT
counter overflow.
– When the WDT is disabled, the 24-bit counter
is cleared. Therefore, the new value of
WDTRST must be written into the 24-bit
counter after the WDT is enabled.
always set up a timer that will periodically exit
Idle, service the WDT, and re-enter Idle
Mode.
WDTRST Register
– When this SFR is written as a value, the value
is loaded into the upper 8 bits of 24-bit
counter in WDT. And, the lower 16 bits are
cleared.
– If the user write "WDTRST" by '04h, then the
value of the 24-bit counter changes from
040000, 040001, 040002, ..., FFFFFF, then
generates the WDT reset.
– In Idle Mode, the oscillator continues to run.
To prevent the WDT from resetting the
processor while in Idle, the user should
Table 29. WDKEY: Watchdog Timer Key Register (0AEH, Reset Value 55H)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
WDKEY7
WDKEY6
WDKEY5
WDKEY4
WDKEY3
WDKEY2
WDKEY1
WDKEY0
Table 30. WDKEY: Watchdog Timer Key Register Details
Register Bit
Definition
Enable or disable watchdog timer. Writing to WDKEY with data pattern 01010101 (= 55h)
will disable the watchdog timer. Other data: enables the watchdog timer.
WDKEY7.. 0
Table 31. WDRST: Watchdog Timer Clear Register (0A6H, Reset Value 00H)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
WDRST7
WDRST6
WDRST5
WDRST4
WDRST3
WDRST2
WDRST1
WDRST0
Table 32. WDRST: Watchdog Timer Clear Register Details
Register Bit
Definition
To reset watchdog timer, write any value to this register. This value is loaded to the 8th
most significant bits of the 24-bit counter.
WDRST[7.. 0]
33/123
µPSD33XX
TIMER/COUNTERS (TIMER0, TIMER1, AND TIMER 2)
The µPSD33XX Devices has three 16-bit Timer/
Counter registers: Timer 0, Timer 1 and Timer 2.
All of them can be configured to operate either as
timers or event counters and are compatible with
standard 8032 architecture (see Table 33).
count rate is 1/24 of the f
as in standard 8032.
OSC
There are no restrictions on the duty cycle of the
external input signal, but to ensure that a given
level is sampled at least once before it changes, it
should be held for at least one full machine cycle.
In addition to the “Timer” or “Counter” selection,
Timer 0 and Timer 1 have four operating modes
from which to select.
In the “Timer” function, the register is incremented
every 1/12 of the oscillator frequency (f
).
OSC
In the “Counter” function, the register is increment-
ed in response to a 1-to-0 transition at its corre-
sponding external input pin, T0 or T1. In this
function, the external input is sampled by the
counter. When the samples show a high in one
machine cycle and a low in the another, the count
is incremented. The new count value appears in
the register during the cycle following the one in
which the transition was detected. The maximum
Timer 0 and Timer 1
The “Timer” or “Counter” function is selected by
control bits C/T in the Special Function Register,
TMOD (see Table 34). These Timer/Counters
have four operating modes, which are selected by
bit-pairs (M1, M0) in TMOD. Modes 0, 1, and 2 are
the same for Timers/ Counters. Mode 3 is differ-
ent.
Table 33. TCON Register (88H, Reset Value 00H) - Timer 0, 1
Bit 7
TF1
Bit 6
TR1
Bit 5
TF0
Bit 4
TR0
Bit 3
IE1
Bit 2
IT1
Bit 1
IE0
Bit 0
IT0
Table 34. TCON Register Details - Timer 0, 1
Bit
Symbol
Function
Timer 1 Overflow flag. Set by hardware on Timer/Counter overflow. Cleared by
hardware when processor vectors to interrupt routine
7
TF1
6
TR1
TF0
Timer 1 Run Control Bit. Set/cleared with software to turn Timer/Counter on or off
Timer 0 Overflow flag. Set by hardier on Timer/Counter overflow. Cleared by hardware
when processor vectors to interrupt routine
5
4
TR0
IE1
Timer 0 Run Control Bit. Set/cleared with software to turn Timer/Counter on or off
Interrupt 1 Edge flag. Set by hardware when external interrupt edge detected. Cleared
when interrupt processed
3
Interrupt 1 Type Control Bit. Set/cleared with software to specify falling-edge/low-level
triggered external interrupt
2
1
0
IT1
IE0
IT0
Interrupt 0 Edge flag. Set by hardware when external interrupt edge detected. Cleared
when interrupt processed
Interrupt 0 Type Control Bit. Set/cleared with software to specify falling-edge/low-level
triggered external interrupt
34/123
µPSD33XX
Mode 0. Putting either Timer into Mode 0 makes
it look like an 8048 Timer, which is an 8-bit Counter
with a divide-by-32 prescaler. Figure 12 shows the
Mode 0 operation as it applies to Timer 1.
Mode 2. Mode 2 configures the Timer register as
an 8-bit Counter (TL1) with automatic reload, as
shown in Figure 13, page 36. Overflow from TL1
not only sets TF1, but also reloads TL1 with the
contents of TH1, which is preset with software.
The reload leaves TH1 unchanged. Mode 2 oper-
ation is the same for Timer/Counter 0.
In this mode, the Timer register is configured as a
13-bit register. As the count rolls over from all '1s'
to all '0s,' it sets the Timer Interrupt flag TF1. The
counted input is enabled to the Timer when
TR1 = 1 and either GATE = 0 or /INT1 = 1. (Setting
GATE = 1 allows the Timer to be controlled by ex-
ternal input /INT1 to facilitate pulse width mea-
surements). TR1 is a control bit in the Special
Function Register TCON (TCON Control Regis-
ter). GATE is in TMOD (see Table 35 and Table
36, page 37).
The 13-bit register consists of all 8 bits of TH1 and
the lower 5 bits of TL1. The upper 3 bits of TL1 are
indeterminate and should be ignored. Setting the
run flag does not clear the registers.
Mode 0 operation is the same for the Timer 0 as
for Timer 1. Substitute TR0, TF0, and /INT0 for the
corresponding Timer 1 signals in Figure 12. There
are two different GATE Bits, one for Timer 1 and
one for Timer 0.
Mode 3. Timer 1 in Mode 3 simply holds its count.
The effect is the same as setting TR1 = 0.
Timer 0 in Mode 3 establishes TL0 and TH0 as two
separate counters. The logic for Mode 3 on Timer
0 is shown in Figure 14. TL0 uses the Timer 0 con-
trol Bits: C/T, GATE, TR0, INT0, and TF0. TH0 is
locked into a timer function (counting machine cy-
cles) and takes over the use of TR1 and TF1 from
Timer 1. Thus, TH0 now controls the “Timer 1“In-
terrupt.
Mode 3 is provided for applications requiring an
extra 8-bit timer on the counter (see Figure 14,
page 36). With Timer 0 in Mode 3, an µPSD33XX
Devices can look like it has three Timer/Counters.
When Timer 0 is in Mode 3, Timer 1 can be turned
on and off by switching it out of and into its own
Mode 3, or can still be used by the serial port as a
baud rate generator, or in fact, in any application
not requiring an interrupt.
Mode 1. Mode 1 is the same as Mode 0, except
that the Timer register is being run with all 16 bits.
Figure 12. Timer/Counter Mode 0: 13-bit Counter
f
÷ 12
OSC
C/T = 0
C/T = 1
TH1
(8 bits)
TL1
(5 bits)
TF1
Interrupt
T1 pin
Control
TR1
Gate
INT1 pin
AI06622
35/123
µPSD33XX
Figure 13. Timer/Counter Mode 2: 8-bit Auto-reload
f
÷ 12
OSC
C/T = 0
C/T = 1
TL1
(8 bits)
TF1
Interrupt
T1 pin
Control
TR1
Gate
INT1 pin
TH1
(8 bits)
AI06623
Figure 14. Timer/Counter Mode 3: Two 8-bit Counters
fOSC
÷ 12
C/T = 0
C/T = 1
TL0
(8 bits)
TF0
Interrupt
T0 pin
Control
TR0
Gate
INT0 pin
TH0
(8 bits)
fOSC
TF1
Interrupt
÷ 12
Control
TR1
AI06624
36/123
µPSD33XX
Table 35. TMOD Register (TMOD)
Bit 7
Bit 6
C/T
Bit 5
M1
Bit 4
M0
Bit 3
Bit 2
C/T
Bit 1
M1
Bit 0
M0
GATE
GATE
Table 36. TMOD Register Details
Bit
Symbol
Timer
Function
Gating control when set. Timer/Counter 1 is enabled only while INT1 pin is High and
7
GATE
TR1 control pin is set. When cleared, Timer 1 is enabled whenever TR1 Control Bit is
set
Timer or Counter selector, cleared for timer operation (input from internal system clock);
set for counter operation (input from T1 input pin)
6
5
C/T
M1
Timer 1
(M1,M0)=(0,0): 13-bit Timer/Counter, TH1, with TL1 as 5-bit prescaler
(M1,M0)=(0,1): 16-bit Timer/Counter. TH1 and TL1 are cascaded. There is no prescaler.
(M1,M0)=(1,0): 8-bit auto-reload Timer/Counter. TH1 holds a value which is to be
reloaded into TL1 each time it overflows
4
3
M0
(M1,M0)=(1,1): Timer/Counter 1 stopped
Gating control when set. Timer/Counter 0 is enabled only while INT0 pin is High and
TR0 control pin is set. When cleared, Timer 0 is enabled whenever TR0 Control Bit is
set
GATE
Timer or Counter selector, cleared for timer operation (input from internal system clock);
set for counter operation (input from T0 input pin)
2
1
C/T
M1
Timer 0
(M1,M0)=(0,0): 13-bit Timer/Counter, TH0, with TL0 as 5-bit prescaler
(M1,M0)=(0,1): 16-bit Timer/Counter. TH0 and TL0 are cascaded. There is no prescaler.
(M1,M0)=(1,0): 8-bit auto-reload Timer/Counter. TH0 holds a value which is to be
reloaded into TL0 each time it overflows
0
M0
(M1,M0)=(1,1): TL0 is an 8-bit Timer/Counter controlled by the standard TImer 0 control
bits. TH0 is an 8-bit timer only controlled by Timer 1 Control Bits
Timer 2
Like Timers 0 and 1, Timer 2 can operate as either
an event timer or as an event counter. This is se-
lected by Bit C/T2 in the special function register
T2CON. It has three operating modes: capture,
autoload, and baud rate generator, which are se-
lected by bits in the T2CON as shown in Table 37
and Table 38, page 38. In the Capture Mode there
are two options which are selected by Bit EXEN2
in T2CON. If EXEN2 = 0, then Timer 2 is a 16-bit
timer or counter which upon overflowing sets Bit
TF2, the Timer 2 Overflow Bit, which can be used
to generate an interrupt. If EXEN2 = 1, then Timer
2 still does the above, but with the added feature
that a 1-to-0 transition at external input T2EX
causes the current value in the Timer 2 registers,
TL2 and TH2, to be captured into registers
RCAP2L and RCAP2H, respectively. In addition,
the transition at T2EX causes Bit EXF2 in T2CON
to be set, and EXF2 like TF2 can generate an in-
terrupt. The Capture Mode is illustrated in Figure
15, page 39.
In the Auto-reload Mode, there are again two op-
tions, which are selected by bit EXEN2 in T2CON
(see Table 39, page 39). If EXEN2 = 0, then when
Timer 2 rolls over it not only sets TF2 but also
causes the Timer 2 registers to be reloaded with
the 16-bit value in registers RCAP2L and
RCAP2H, which are preset with software. If
EXEN2 = 1, then Timer 2 still does the above, but
with the added feature that a 1-to-0 transition at
external input T2EX will also trigger the 16-bit re-
load and set EXF2. The Auto-reload Mode is illus-
trated in Standard Serial Interface (UART) Figure
16, page 40. The Baud Rate Generation Mode is
selected by (RCLK, RCLK1)=1 and/or (TCLK,
TCLK1)=1. It will be described in conjunction with
the serial port.
37/123
µPSD33XX
Table 37. T2CON: Timer/Counter 2 Control Register (C8H, Reset Value 00H))
Bit 7
TF2
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
TR2
Bit 1
C/T2
Bit 0
EXF2
RCLK
TCLK
EXEN2
CP/RL2
Table 38. T2CON Register Details
Bit
Symbol
Function
Timer 2 Overflow flag. Set by a Timer 2 overflow, and must be cleared with software.
TF2 will not be set when either (RCLK, RCLK1)=1 or (TCLK, TCLK)=1
7
TF2
Timer 2 external flag set when either a capture or reload is caused by a negative
transition on T2EX and EXEN2=1. When Timer 2 Interrupt is enabled, EXF2=1 will
cause the CPU to vector to the Timer 2 Interrupt routine. EXF2 must be cleared with
software
6
EXF2
Receive Clock flag (UART0). When set, causes the serial port to use Timer 2 overflow
pulses for its receive clock in Modes 1 and 3. TCLK=0 causes Timer 1 overflow to be
used for the receive clock
(1)
5
4
3
RCLK
Transmit Clock flag (UART0). When set, causes the serial port to use Timer 2 overflow
pulses for its transmit clock in Modes 1 and 3. TCLK=0 causes Timer 1 overflow to be
used for the transmit clock
(1)
TCLK
Timer 2 External Enable flag. When set, allows a capture or reload to occur as a result
of a negative transition on T2EX if Timer 2 is not being used to clock the serial port.
EXEN2=0 causes Time 2 to ignore events at T2EX
EXEN2
2
1
TR2
Start/Stop control for Timer 2. A logic 1 starts the timer
Timer or Counter Select for Timer 2. Cleared for timer operation (input from internal
C/T2
system clock, t
); set for external event counter operation (negative edge triggered)
CPU
Capture/Reload flag. When set, capture will occur on negative transition of T2EX if
EXEN2=1. When cleared, auto-reload will occur either with TImer 2 overflows, or
negative transitions of T2EX when EXEN2=1. When either (RCLK, RCLK1)=1 or (TCLK,
TCLK1)=1, this bit is ignored, and timer is forced to auto-reload on Timer 2 overflow
0
CP/RL2
Note: 1. The RCLK1 and TCLK1 Bits in the PCON Register control UART1, and have the same function as RCLK and TCLK.
38/123
µPSD33XX
Table 39. Timer/Counter 2 Operating Modes
T2CON
Input Clock
External
T2CON P1.1
EXEN T2EX
RxCLK
or
Mode
Remarks
CP/
RL2
TR2
Internal
(P1.0/T2)
TxCLK
0
0
0
0
0
0
0
0
1
1
1
1
0
1
x
x
x
↓
0
1
reload upon overflow
reload trigger (falling edge)
Down counting
16-bit
Auto-
reload
MAX
f
/12
OSC
f
/24
OSC
Up counting
16-bit Timer/Counter (only up
counting)
0
0
1
1
1
1
0
1
x
MAX
16-bit
Capture
f
f
/12
/12
OSC
OSC
f
f
/24
OSC
Capture (TH2,TL2) →
(RCAP2H,RCAP2L)
↓
1
1
x
x
x
x
1
1
0
0
1
x
x
↓
x
No overflow interrupt request (TF2)
Extra External Interrupt (Timer 2)
Timer 2 stops
MAX
Baud Rate
Generator
/24
OSC
Off
—
—
Note: ↓ = falling edge
Figure 15. Timer 2 in Capture Mode
f
÷ 12
OSC
C/T2 = 0
C/T2 = 1
TH2
(8 bits)
TL2
(8 bits)
TF2
T2 pin
Control
TR2
Timer 2
Interrupt
Capture
RCAP2H
RCAP2L
Transition
Detector
T2EX pin
EXP2
Control
EXEN2
AI06625
39/123
µPSD33XX
Figure 16. Timer 2 in Auto-Reload Mode
f
÷ 12
OSC
C/T2 = 0
C/T2 = 1
TH2
(8 bits)
TL2
(8 bits)
TF2
T2 pin
Control
TR2
Timer 2
Interrupt
Reload
RCAP2H
RCAP2L
Transition
Detector
T2EX pin
EXP2
Control
EXEN2
AI06626
40/123
µPSD33XX
STANDARD SERIAL INTERFACE (UART)
The µPSD33XX Devices provide two standard
8032 UART serial ports. The first port (UART0) is
connected to pin P3.0 (RxD0) and P3.1 (TxD0).
The second port (UART1) is connected to pin P1.2
(RxD1) and P1.3(TxD1) or P4.2 and P4.3. The op-
eration of the two serial ports are the same and are
controlled by the SCON0 and SCON1 registers.
The serial port is full duplex, meaning it can trans-
mit and receive simultaneously. It is also receive-
buffered, meaning it can commence reception of a
Mode 2. 11 bits are transmitted (through TxD) or
received (through RxD): Start Bit (0), 8 data bits
(LSB first), a programmable 9th data bit, and a
Stop Bit (1). On Transmit, the 9th data bit (TB8 in
SCON) can be assigned the value of '0' or '1.' Or,
for example, the Parity Bit (P, in the PSW) could
be moved into TB8. On receive, the 9th data bit
goes into RB8 in Special Function Register SCON,
while the Stop Bit is ignored. The baud rate is pro-
grammable to either 1/32 or 1/64 the oscillator fre-
quency.
second byte before a previously received byte has
been read from the register. (However, if the first
byte still has not been read by the time reception
of the second byte is complete, one of the bytes
will be lost.) The serial port receive and transmit
registers are both accessed at Special Function
Register SBUF0 (or SBUF1 for the second serial
port). Writing to SBUF loads the transmit register,
and reading SBUF accesses a physically separate
receive register.
Mode 3. 11 bits are transmitted (through TxD) or
received (through RxD): a Start Bit (0), 8 data bits
(LSB first), a programmable 9th data bit, and a
Stop Bit (1). In fact, Mode 3 is the same as Mode
2 in all respects except baud rate. The baud rate
in Mode 3 is variable.
In all four modes, transmission is initiated by any
instruction that uses SBUF as a destination regis-
ter. Reception is initiated in Mode 0 by the condi-
tion RI = 0 and REN = 1. Reception is initiated in
the other modes by the incoming Start Bit if
REN = 1.
The serial port can operate in 4 modes:
Mode 0. Serial data enters and exits through
RxD. TxD outputs the shift clock. 8 bits are trans-
mitted/received (LSB first). The baud rate is fixed
Serial Port Control Register
at 1/12 the f
.
The serial port control and status register is the
Special Function Register SCON0 (SCON1 for the
second port), shown in Table 40 and Table 41,
page 42. This register contains not only the mode
selection bits, but also the 9th data bit for transmit
and receive (TB8 and RB8), and the Serial Port In-
terrupt Bits (TI and RI).
OSC
Mode 1. 10 bits are transmitted (through TxD) or
received (through RxD): a Start Bit (0), 8 data bits
(LSB first), and a Stop Bit (1). On receive, the Stop
Bit goes into RB8 in Special Function Register
SCON. The baud rate is variable.
Table 40. Serial Port Control Register (SCON0 and SCON1)
Bit 7
SM0
Bit 6
SM1
Bit 5
SM2
Bit 4
REN
Bit 3
TB8
Bit 2
RB8
Bit 1
TI
Bit 0
RI
Note: 1. SCON0 (98H - UART0 Reset Value 00); SCON1 (D8H - UART1 Reset Value 00)
41/123
µPSD33XX
Table 41. SCON0 and SCON1 Register Details
Bit
7
Symbol
SM0
Function
See Table 42.
6
SM1
Enables the multiprocessor communication features in Mode 2 and 3. In Mode 2 or 3, if
SM2 is set to '1,' RI will not be activated if its received 8th data bit (RB8) is '0.' In Mode
1, if SM2=1, RI will not be activated if a valid Stop Bit was not received. In Mode 0, SM2
should be '0.'
5
SM2
Enables serial reception. Set with software to enable reception. Clear with software to
disable reception.
4
3
2
REN
TB8
RB8
The 8th data bit that will be transmitted in Modes 2 and 3. Set or clear with software as
desired
In Modes 2 and 3, this bit contains the 8th data bit that was received. In Mode 1, if
SM2=0, RB8 is the Snap Bit that was received. In Mode 0, RB8 is not used.
Transmit Interrupt flag. Set by hardware at the end of the 8th bit time in Mode 0, or at the
beginning of the Stop Bit in the other modes, in any serial transmission. Must be cleared
with software.
1
0
TI
Receive Interrupt flag. Set by hardware at the end of the 8th bit time in Mode 0, or
halfway through the Stop Bit in the other modes, in any serial reception (except for
SM2). Must be cleared with software.
RI
Table 42. UART Operating Table
SCON
Mode
Baud Rate
Description
SM0
SM1
Serial data enters and exits through RxD. TxD outputs the
shift clock.
f
/12
0
0
0
OSC
8-bit are transmitted/received (LSB first)
8-bit UART
1
2
3
0
1
1
1
0
1
Timer 1/2 overflow rate
10 bits are transmitted (through TxD) or received (RxD).
9-bit UART
f
/32 or f
/64
OSC
OSC
11 bits are transmitted (through TxD) or received (RxD)
9-bit UART
Like Mode 2, except the variable baud rate.
Timer 1/2 overflow rate
42/123
µPSD33XX
Baud Rates. The baud rate in Mode 0 is fixed:
Mode 0 Baud Rate = f / 12
The Baud Rate Generator Mode is similar to the
Auto-reload Mode, in that a roll over in TH2 causes
the Timer 2 registers to be reloaded with the 16-bit
value in registers RCAP2H and RCAP2L, which
are preset with software.
Now, the baud rates in Modes 1 and 3 are deter-
mined at Timer 2’s overflow rate as follows:
OSC
The baud rate in Mode 2 depends on the
value of Bit SMOD = 0 (which is the value on
reset), the baud rate is 1/64 the oscillator
frequency. If SMOD = 1, the baud rate is 1/32
the oscillator frequency.
SMOD
Mode 1,3 Baud Rate =
Mode 2 Baud Rate = (2
/ 64) x f
OSC
Timer 2 Overflow Rate / 16
In the µPSD33XX Devices, the baud rates in
Modes 1 and 3 are determined by the Timer
1 overflow rate.
The timer can be configured for either “timer” or
“counter” operation. In the most typical applica-
tions, it is configured for “timer” operation (C/T2 =
0). “Timer” operation is a little different for Timer 2
when it's being used as a baud rate generator. In
this case, the baud rate is given by the formula:
Using Timer 1 to Generate Baud Rates. When
Timer 1 is used as the baud rate generator, the
baud rates in Modes 1 and 3 are determined by
the Timer 1 overflow rate and the value of SMOD
as follows:
Mode 1,3 Baud Rate =
Mode 1,3 Baud Rate =
f
/(32 x [65536 – (RCAP2H, RCAP2L)]
OSC
SMOD
(2
/ 32) x (Timer 1 overflow rate)
where (RCAP2H, RCAP2L) is the content of
RC2H and RC2L taken as a 16-bit unsigned inte-
ger.
Timer 2 also may be used as the Baud Rate Gen-
erating Mode. This mode is valid only if RCLK +
TCLK = 1 in T2CON or in PCON.
Note: A roll-over in TH2 does not set TF2, and will
not generate an interrupt. Therefore, the Timer In-
terrupt does not have to be disabled when Timer 2
is in the Baud Rate Generator Mode.
The Timer 1 Interrupt should be disabled in this
application. The Timer itself can be configured for
either “timer” or “counter” operation, and in any of
its 3 running modes. In the most typical applica-
tions, it is configured for “timer” operation, in the
Auto-reload Mode (high nibble of TMOD = 0010B).
In that case the baud rate is given by the formula:
Mode 1,3 Baud Rate =
SMOD
(2
/ 32) x (f
/ (12 x [256 – (TH1)]))
OSC
One can achieve very low baud rates with Timer 1
by leaving the Timer 1 Interrupt enabled, and con-
figuring the Timer to run as a 16-bit timer (high nib-
ble of TMOD = 0001B), and using the Timer 1
Interrupt to do a 16-bit software reload. Figure 12,
page 35 lists various commonly used baud rates
and how they can be obtained from Timer 1.
Using Timer/Counter 2 to Generate Baud
Rates. In the µPSD33XX Devices, Timer 2 select-
ed as the baud rate generator by setting TCLK
and/or RCLK (see Figure 12, page 35, Timer/
Counter 2 Control Register).
Note: If EXEN2 is set, a 1-to-0 transition in T2EX
will set EXF2 but will not cause a reload from
(RCAP2H, RCAP2L) to (TH2, TL2). Thus when
Timer 2 is in use as a baud rate generator, T2EX
can be used as an extra external interrupt, if de-
sired.
Note: When Timer 2 is running (TR2 = 1) in “timer”
function in the Baud Rate Generator Mode, one
should not try to READ or WRITE TH2 or TL2. Un-
der these conditions the timer is being increment-
ed every state time, and the results of a READ or
WRITE may not be accurate.
Note: The baud rate for transmit and receive can
be simultaneously different. Setting RCLK and/or
TCLK puts Timer into its Baud Rate Generator
Mode.
The RCLK and TCLK Bits in the T2CON register
configure UART0. The RCLK1 and TCLK1 Bits in
the PCON register configure UART1.
The RC registers may be read, but should not be
written to, because a WRITE might overlap a re-
load and cause WRITE and/or reload errors.
Turn the timer off (clear TR2) before accessing the
Timer 2 or RC registers, in this case.
43/123
µPSD33XX
IRDA INTERFACE TO INFRARED TRANSCEIVER
The µPSD33XX provides an IrDA interface that
meets the IrDA Specification. The IrDA Interface
logic “pulse shaping” the UART1 (2nd UART) seri-
al signal from a UART Frame to an IrDA standard
IR Frame (and vise versa) that can be accepted by
a standard IrDA Transceiver. When enabled and
in transmitting mode, the IrDA Interface shortens
the UART output signal to IrDA compatible electri-
cal pulses. In receiving mode, the Interface
stretches the IrDA transceiver signal to the proper
bit rate to be received by the UART. The outputs
of the IrDA Interface drive the IrDA Transceiver di-
rectly.
The UART1 can operate in 4 modes, Mode 0 to
Mode 3. The IrDA Interface supports Mode 1 (10
bits transmit - Start Bit, 8 data bits and 1 Stop Bit)
only so as to be compatible with the IrDA format.
The IrDA Interface supports baud rate generated
by Timer 1 or Timer 2, but the Tx and Rx must be
of the same baud rate.
The features of the IrDA Interface are:
■ Stretches the UART pulse to 1.627µs; it
supports IrDA pulse from 1.41µs (Min) to 2,23µs
(Max) pulse or 3/16 bit pulse duration.
■ Support for baud rates from 1.2kHz to 115.2kHz
■ Direct interface to SIR transceiver from UART1
I/O pins (RxD1, TxD1) on Ports 1 or 4
■ IRDACON Register bits select pulse duration
and specify baud rate
The IrDA Interface is disabled on power-up and is
enabled by the IRDAEN Bit in the IRDACON Reg-
ister (see Table 43 and Table 44, page 44). When
it is disabled, the UART1's RxD and TxD bypass
the IrDA Interface and are connected directly to
the port pins. The IrDA Interface generates a
1.627µs or 3/16 bit pulse width output when the bit
is a '0' on the TxD line and stays '0' when the bit is
a '1.'
Figure 17. µPSD33XX IrDA Interface
TxD1-IrDA
SIRClk
IrDA
IrDA
Interf ace
UART1
Transceiver
RxD1-IrDA
TxD
RxD
uPSD33XX
AI07851
Table 43. IRDACON Register Bit Definition (CEH, Reset Value 0FH)
Bit 7
–
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
IRDAEN
PULSE
CDIV4
CDIV3
CDIV2
CDIV1
CDIV0
Table 44. IRDACON Register Details
BIT
SYMBOL
RW
Definition
7
–
Reserved
IrDA Enable
0 = IrDA Interface is disabled
1 = IrDA is enabled, UART1 outputs are disconnected from Port 1
6
IRDAEN
RW
(or port 4)
44/123
µPSD33XX
BIT
SYMBOL
PULSE
RW
RW
RW
Definition
IrDA Pulse Modulation Select
0 = 1.627µs
1 = 3/16 bit time pulses
5
4-0
CDIV[4:0]
Specify Clock Divider (see Table 45)
Baud Rate Select
There will be two schemes for IrDA pulse modula-
tion:
1. In the event of 3/16 bit time pulse modulation:
clock (i.e, SIRClk) that is used to generate
1.627µs pulse modulation. Even though the
pulse width is 1.627µs, the baud rate follows the
configuration of UART1. Select a clock divider
At maximum baud rate of 115.2kHz, the 3/16 bit
time pulse is 1.627µs.
2. In case of 1.627µs pulse modulation:
to generate a F
1.8432MHz.
clock close to
SIRCLK
F
= f
/ (CDIV[4:0])
OSC
SIRCLK
To implement 1.627µs pulse modulation, a
prescaler is needed to generate a subrefernce
where CDIV[4:0] must be 4 or larger.
Table 45. f
Frequency
SIRCLK
f
(1)
CDIV[4:0] (Clock divider)
f
OSC
SIRCLK
40.0MHz
33.0MHz
30.0MHz
24.0MHz
16.0MHz
12.0MHz
22
18
16
13
9
1.8181MHz
1.8333MHz
1.8750MHz
1.8461MHz
1.7777MHz
1.7142MHz
7
Note: 1. f
at 1.8342MHz is needed to generate the 1.627µs pulse.
SIRCLK
45/123
µPSD33XX
2
I C INTERFACE
2
2
There is a serial I C port implemented in the
µPSD33XX Devices. The serial port supports the
These functions are controlled by the I C SFRs:
S1CON: the Control register - control of byte han-
dling and the operation of 4 mode
S1STA: the Status register - contents of its register
may also be used as a vector to various service
routines.
2
twin line I C -bus and consists of a data line (SDA)
and a clock line (SCL). Depending on the configu-
ration, the SDA and SCL lines may require pull-up
resistors.
The system is unique because data transport,
clock generation, address recognition, and bus
control arbitration are all controlled by hardware.
S1DAT: Data Shift register.
S1ADR: Slave Address register. Slave address
recognition is performed by On-Chip Hardware.
2
The I C serial I/O has complete autonomy in byte
handling and operates in 4 modes:
■ Master transmitter
■ Master receiver
Table 48, page 47 shows the divisor values and
2
the I C bit rate for some common f
cies.
frequen-
OSC
■ Slave transmitter
■ Slave receiver
2
Figure 18. I C Bus Block Diagram
7
0
Slave Address
7
0
Shift Register
SDA
Arbitration + Sync. Logic
Bus Clock Generation
Control Register
Status Register
SCL
7
7
0
0
AI07852
2
I C Registers Definition
Table 46. Serial Control Register S1CON (DCH, Reset Value 00H)
Bit 7
CR2
Bit 6
Bit 5
STA
Bit 4
STO
Bit 3
Bit 2
AA
Bit 1
CR1
Bit 0
CR0
ENI1
ADDR
46/123
µPSD33XX
Table 47. S1CON Register Details
Bit
Symbol
Function
This bit, along with Bits CR1and CR0 determines the serial clock frequency when SIO is
in the Master Mode.
7
CR2
Enable IIC. When ENI1 = 0, the IIC is disabled. SDA and SCL outputs are in the high
impedance state.
6
5
ENI1
STA
2
START flag. When this bit is set, the SIO H/W checks the status of the I C bus and
generates a START condition if the bus is free. If the bus is busy, the SIO will generate a
repeated START condition when this bit is set.
2
2
When a START condition is detected on the I C Bus, the I C hardware clears the STA
flag.
Note: If this bit is set during an interrupt service, the START condition occurs after the
interrupt service.
STOP flag. With this bit set while in Master Mode a STOP condition is generated.
2
2
When a STOP condition is detected on the I C bus, the I C hardware clears the STO
4
3
STO
flag.
Note: If this bit is set during an interrupt service, the STOP condition occurs after the
interrupt service.
ADDR
This bit is set when address byte was received. Must be cleared with software.
Acknowledge enable signal. If this bit is set, an acknowledge (low level to SDA is
returned during the acknowledge clock pulse on the SCL line when:
■ Own slave address is received;
2
AA
■ A data byte is received while the device is programmed to be a Master Receiver;
■ A data byte is received while the device is a selected Slave Receiver; and
■ When this bit is reset, no acknowledge is returned.
SIO release SDA line as high during the acknowledge clock pulse.
These two bits, along with the CR2 Bit determine the serial clock frequency when SIO is
in the Master Mode.
1, 0
CR1, CR0
Table 48. Selection of the Serial Clock Frequency SCL in Master Mode
Bit Rate (kHz) @ f
OSC
f
Divisor
CR2
CR1
CR0
OSC
12MHz
24MHz
36MHz
40MHz
(1)
(1)
0
0
0
16
375
750
X
X
0
0
0
1
1
1
1
0
1
1
0
0
1
1
1
0
1
0
1
0
1
24
30
250
200
100
50
500
400
200
100
50
750
600
300
150
75
833
666
333
166
83
60
120
240
480
960
25
12.5
6.25
25
37.5
18.75
41
12.5
20
Note: 1. These values are beyond the supported bit rate.
47/123
µPSD33XX
Serial Status Register (S1STA)
S1STA is a “Read only” register (except Bit 5 IN-
TR, see Table 49). The contents of this register
may be used as a vector to a service routine. This
optimized the response time of the software and
3. A data byte has been received or transmitted in
Master Mode (even if arbitration is lost): ack_int
4. A data byte has been received or transmitted as
selected slave: ack_int
5. A Stop condition is received as selected slave
receiver or transmitter: stop_int
Data Shift Register (S1DAT)
S1DAT contains the serial data to be transmitted
or data which has just been received (see Table
51). The MSB (Bit 7) is transmitted or received
first; that is, data shifted from right to left.
2
consequently that of the I C-bus.
The status codes for all possible modes of the I C
2
bus interface are given Table 50.
This flag is set, and an interrupt is generated after
any of the following events occur.
1. Own slave address has been received during
AA = 1: ack_int
2. The general call address has been received
while GC(S1ADR.0) = 1 and AA = 1
Table 49. Serial Status Register S1STA (DDH, Reset Value 00H)
Bit 7
GC
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SLV
STOP
INTR
TX_MODE
BBUSY
BLOST
ACK_REP
Table 50. S1STA Status Register Details
Bit
Symbol
Function
7
GC
General Call flag
STOP flag.
6
5
STOP
INTR
This bit is set when a STOP condition is received.
Interrupt flag.
2
This bit is set when a I C interrupt is requested.
Must be cleared with software.
Transmission Mode flag.
4
3
2
TX_MODE
BBUSY
2
This bit is set when the I C is a transmitter. Otherwise, this bit is reset.
Bus Busy State flag.
This bit is set when the bus is being used by another master. Otherwise, this bit is reset.
Bus Lost flag.
BLOST
This bit is set when the master loses the bus contention. Otherwise, this bit is reset.
Acknowledge response flag.
This bit is set when the receiver transmits the not acknowledge signal.
1
0
ACK_REP This bit is reset when the receiver transmits the acknowledge signal.
Even if this bit is set, the STOP condition does not occur in the bus.
(MASTER MODE)
Slave Mode flag.
SLV
2
This bit is set when the I C plays role in the slave mode. Otherwise, this bit is reset.
Table 51. Data Shift Register S1DAT (DEH, Reset Value 00H)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
S1DAT7
S1DAT6
S1DAT5
S1DAT4
S1DAT3
S1DAT2
S1DAT1
S1DAT0
48/123
µPSD33XX
Address Register (S1ADR)
2
This 8-bit register may be loaded with the 7-bit
slave address to which the controller will respond
when programmed as a slave receive/transmitter
(see Table 52). The Start/Stop Hold Time Detec-
tion and System Clock registers (Table 53 and Ta-
ble 54) are included in the I C unit to specify the
start/stop detection time to work with the large
range of MCU frequency values supported. Table
55 is an example with a system clock of 40MHz.
Table 52. Address Register S1ADR (DFH, Reset Value 00H)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
–
SLA6
SLA5
SLA4
SLA3
SLA2
SLA1
SLA0
Table 53. Start/Stop Hold Time Detection Register S1SETUP (DBH, Reset Value 00H)
Bit 7
Bit 6 - Bit 0
Enable S1SETU
Bit 6 - 0 specify the number of sample clocks
Table 54. System Clock of 40MHz
No. of Sample Clock
Required Start/Stop
Hold Time
S1SETUP Register Value
(f
Note
= 25ns)
OSC
When Bit 7 (Enable bit) = 0,
the number of sample clock
is 1EA (ignore Bit 6 - Bit 0)
00H
1EA
25ns
80h
81h
82h
...
1EA
2EA
3EA
...
25ns
50ns
75ns
8Bh
12EA
300ns
600ns
2
Fast Mode I C Start/Stop
97h
24EA
Hold time specification
...
...
FFh
128EA
3000ns
Table 55. System Clock Setup Examples
Required Start/Stop
Hold Time
System Clock
40MHz (f -> 25ns)
S1SETUP Register Value
No. of Sample Clock
97h
91h
8Bh
84h
24EA
18EA
12EA
5EA
600ns
599ns
600ns
625ns
OSC
30MHz (f
-> 33.3ns)
OSC
20MHz (f
-> 50ns)
OSC
8MHz (f
-> 125ns)
OSC
49/123
µPSD33XX
SPI (SYNCHRONOUS PERIPHERAL INTERFACE)
The SPI is a master interface that enables syn-
chronous, serial communication with external
slave peripherals. The SPI features full-duplex,
three-wire synchronous transfers and programma-
ble clock polarity (optional 4 wires). The SPI per-
forms parallel-to-serial conversion on data written
to a 8-bit wide Transmit data register (SPITDR)
and serial-to-parallel conversion on received data,
3. 8-bit wide, double-buffered transmit and receive
operation
4. Full-duplex - Both transmit and receive operate
simultaneously with two wires
5. 3, or 4 wires external pins (see Figure 19):
SPITxD – This pin is used to transmit data out
of the SPI module.
SPIRxD – This pin is used to receive data from
slave mode.
buffering a 8-bit wide Receive data register (SPIR-
DR).
SPISEL – This pin is used to output the select
signal from the SPI module to another
peripheral with which a data transfer is to take
place.
SPICLK – This pin is used to output the SPICLK
clock
The SPI supports a subset of the SPI function,
mainly the Master Mode with CPHA=1 Transfer
Format. It will be able to interface a device that has
a SPI Slave interface with the slave select being
grounded or controlled by the SPI. The CPHA=1
Transfer Format requires that the first data bit is
shifted out at the same time as the first SPICLK.
The SPI has the following features:
1. Support Master Mode, 8 bit data size
2. Programmable Clock Polarity
6. Programmable baud rate which can be
modulated by SPICLKD register
SPI Registers
The SPI has seven registers for data transmit, re-
ceive, and control (see Table 56, page 51 through
Table 60, page 52).
Figure 19. SPI Bus Interface
SPI
SPISEL
Tx[7:0]
SPITDR
Tx_Shift_Reg
SPITXD
SPIRXD
7
7
6
6
5
4
3
2
1
1
0
0
Rx_Shift_Reg
5
4 3 2
Rx[7:0]
SPICLK
SPIRDR
SCLKDIV
fOSC
Clock Divider
AI07853
50/123
µPSD33XX
Table 56. SPI Registers
Register
SPICON0
SPICON1
SPITDR
SFR Offset
D6H
Dir.
RW
RW
W
Description
Reset Value
Control Register 0
Control Register 1
00
00
00
00
04
02
D7H
D4H
Transmit Data Register (data byte to be transmitted)
Receive Data Register (store received data byte)
Clock Divider Value
SPIRDR
SPICLKD
SPISTAT
D5H
R
D2H
RW
R
D3H
Status Register
Table 57. SPICON0 (Control Register 0) Details (D6H, Reset Value 00H)
BIT
SYMBOL
RW
Definition
7
–
Reserved
Transmitter Enable
6
5
4
3
2
TE
RE
RW
RW
RW
RW
RW
0 = Transmitter is disabled
1 = Transmitter is enabled
Receiver Enable
0 = Receiver is disabled
1 = Receiver is enabled
SPI Enable
0 = SPI is disabled
1 = SPI is enabled
SPIEN
SSEL
FLSB
Slave Selection
0 = Slave Select output is disabled
1 = Slave Select output is enabled on Port pin P1.7 (or P4.7)
First LSB
0 = Transfer the most significant bit (MSB) first
1 = Transfer the least significant bit (LSB) first
Sampling Polarity
0 = Sample transfer data at the falling edge of clock (SPICLK is '0'
1
0
SPO
–
RW
when idle)
1 = Sample transfer data at the rising edge of clock (SPICLK is '1'
when idle)
Reserved
51/123
µPSD33XX
Table 58. SPICON1 (Control Register 1) Details (D7H, Reset Value 00H)
BIT
SYMBOL
RW
Definition
7-4
–
Reserved
Transmission End Interrupt Enable
3
2
1
0
TEIE
RORIE
TIE
RW
RW
RW
RW
0 = SPI Transmission end Interrupt Disable
1 = SPI Transmission end Interrupt Enable
Receive Overrun Interrupt Enable
0 = Receive Overrun Interrupt Disable
1 = Receive Overrun Interrupt Enable
Transmission Interrupt Enable
0 = SPITDR empty interrupt Disable
1 = SPITDR Empty interrupt Enable
Reception Interrupt Enable
0 = SPIRDR full interrupt Disable
1 = SPIRDR full interrupt Enable
RIE
Table 59. SPICLKD (SPI Prescaler) Register (D2H, Reset Value 04H)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
–
Bit 0
–
DIV128
DIV64
DIV32
DIV16
DIV8
DIV4
Table 60. SPICLKD (SPI Prescaler) Details
BIT
SYMBOL
RW
Definition
0 = No division
1 = Divide f
7
DIV128
RW
clock by 128
OSC
T0 = No division
1 = Divide f
6
5
4
3
DIV64
DIV32
DIV16
DIV8
RW
RW
RW
RW
RW
clock by 64
clock by 32
clock by 16
clock by 8
clock by 4
OSC
0 = No division
1 = Divide f
OSC
0 = No division
1 = Divide f
OSC
0 = No division
1 = Divide f
OSC
0 = No division
1 = Divide f
2
DIV4
OSC
1-0
Not Used
52/123
µPSD33XX
The SPI serial clock frequency in Master Mode is
the f clock divided by the SPICLKD divisors.
The bits in the SPICLKD register can be set to pro-
vide divisor values of multiple of 4: 4, 8, 12, 16,
20… to 252.
guaranteed valid at the fall of serial clock. When
SPO is set to '1,' the data bit is placed on the com-
munication line from one falling edge of serial
clock to the next and is guaranteed valid at the rise
of serial clock.
OSC
Operation
The FLSB Bit determines the format of 8-bit serial
data transfer. When FLSB is '0,' the 8-bit data is
transferred in order from MSB (first) to LSB (last).
When FLSB is '1,' the data is transferred in order
from LSB (first) to MSB (last).
The SPI transmitter and receiver share the same
clock but are independent, so full-duplex commu-
nication is possible. The transmitter and receiver
are also double-buffered, so continuous transmit-
ting or receiving (back-to-back transfer) is possible
by reading or writing data while transmitting or re-
ceiving is in progress.
The bit rate requires the programming of the clock
divider register SPICLKD. The value of SPICLKD
divides the f
clock to provide the serial transfer
OSC
clock output -SPICLK.
SPI Configuration
The SPICON1 and SPICON0 have SPI Transmit-
ter Enable (TE) and Receiver Enable (RE) and In-
terrupt Enable Bits (TEIE, RORIE,TIE, RIE). If TE
is disabled, both transmitting and receiving are
disabled because SPICLK is forced to LOW
(SPO=0) or HIGH (SPO=1).
The SPI is reset by the CPU Reset. Control regis-
ter SPICON0 needs to be programmed to decide
several operation parameters. The SPO Bit deter-
mines clock polarity. When SPO is set to '0,' the
data bit is placed on the communication line from
one rising edge of serial clock to the next and is
Table 61. SPISTAT (Status) Register (D3H, Reset Value 02H)
Bit 7
–
Bit 6
–
Bit 5
–
Bit 4
Bit 3
Bit 2
Bit 1
TISF
Bit 0
BUSY
TEISF
RORISF
RISF
Table 62. SPISTAT (Status) Register Details
BIT
SYMBOL
RW
Definition
7-5
Reserved
SPI Busy
4
3
2
1
0
BUSY
TEISF
RORISF
TISF
R
R
R
R
R
0 = Tx/Rx is completed
1 = Tx/Rx is on going
Transmission End Interrupt Source flag
0 = Reset when users read this register
1 = Set when transmission end occurs
Receive Overrun Interrupt Source flag
0 = Reset when user reads this register
1 = Set when Rx Overrun occurs
Transfer Interrupt Source flag
0 = Reset when SPITDR is full (when the SPITDR is written)
1 = Set when SPITDR is empty
Receive Interrupt Source flag
0 = Reset when SPIRDR is empty (when the SPITDR is read)
RISF
1 = Set when SPIRDR is full
53/123
µPSD33XX
Slave Select Output
The SPI can be operated as a SPI bus in Master
Mode. The Slave Select (SPISEL) line in the SPI
bus is assigned to port pin P1.7 (or P4.7). When
the SSEL Bit is set in the Control Register, the SPI
drives the SPISEL line low to select the slave de-
vice before data transmission. The rising edge of
SPISEL occurs after the last bit is shifted out.
to load new data (e.g., the last bit (8th bit) of the
TSR is being sent, or the TSR is empty), the SPI
will load the TSR with data on SPITDR and set
TISF to '1' (i.e., request CPU to fill SPITDR).
4. The SPI checks the TISF flag when it outputs
the last bit (8th bit) of the eight-bit serial
transmission data.
Transmit operation. In transmitting serial data,
the SPI operates as follows:
1. The initial sequence would be:
– If the TISF flag is '0,' the SPI loads data from
SPITDR into the TSR and begins serial
transmission of the next 8-bit frame
(continuous transfer).
– If the TISF is '1,' the SPI sets the TEISF flag
to '1' in SPISTAT, and if the TEIE Bit is set to
'1' in SPICON1, a Transmit End Interrupt is
requested at this time.
– CPU writes the byte to SPITDR,
– CPU sets SPIEN = 1, TIE = 1,
– CPU sets TE = 1 to enable transmit,
– SPI loads TSR with data from TDR, and
– SPI sets TISF and interrupts the CPU to write
the second byte.
2. In the ISR (Interrupt Service Routine) for SPI,
the CPU writes new data on SPITDR. This
update will automatically clear TISF.
So, the TISF Bit must be '0' before the last bit is
transmitted to perform continuous transfer. After
transmitting the last bit, the SPI holds the
SPITxD pin in the last bit state.
5. After the end of serial transmission, the SPICLK
pin is held in a constant state.
3. If TISF is cleared (i.e., SPITDR has a valid data)
and the TSR (Transmit Shift Register) is ready
Figure 20. SPI Transmit Operation Example
1 frame
SPICLK
(SPO=0)
SPICLK
(SPO=1)
SPITXD
TISF
Bit0
Bit1
Bit7
Bit0
Bit1
Bit7
TEISF
BUSY
SPISEL
SPIINTR
Interrupt handler
write data in TDR
Transmit End
interrupt requested
SPITDR Empty
interrupt requested
SPITDR Empty
interrupt requested
AI07854
54/123
µPSD33XX
Receive Operation
In receiving serial data, the SPI operates as fol-
lows:
1. The SPI generates serial clock and
synchronizes internally.
2. Received data is stored in the RSR (Receive
Shift Register) in order from MSB to LSB
(FLSB = 0) or from LSB to MSB (FLSB = 1).
After receiving the data, the SPI checks to see if
the RIS flag is '0' or not.
When the check fails (i.e., the RIS flag is '1' or
the last received data in SPIRDR is not read
until the 8th bit of currently received data is
received in the RSR), the RORIS flag is set to '1'
and received data in the RSR is lost. When the
RORIS flag is set to '1' and the RORIE Bit is set
to '1' at SPICON1, the subsequent transmit and
receive operations are disabled.
3. If the RIE Bit in SPICON1 is set to '1' and the
RIS flag is set to '1,' the SPIRDR Full Interrupt is
requested.
If this check passes, the received data in the
RSR is stored in SPIRDR and the RIS flag is set
to 1.
If the RORIE Bit in SPICON1 is set to '1' and the
RORIS flag is set to '1,' the Receive Overrun
Interrupt is requested.
Figure 21. SPI Receive Operation Example
1 frame
SPICLK
(SPO=0)
SPICLK
(SPO=1)
SPIRXD
RISF
Bit7
Bit0
Bit1
Bit7
Bit0
Bit1
Bit7
RORIS
BUSY
SPIINTR
Interrupt handler
read data in SPIRDR
Transmit End
interrupt requested
SPIRDR Full
interrupt requested
SPIRDR Full
interrupt requested
AI07855
55/123
µPSD33XX
ANALOG-TO-DIGITAL CONVERTOR (ADC)
The ADC unit in the µPSD33XX is a SAR type
ADC with a SAR register, an auto-zero comparator
and three internal DACs. The unit has 8 input
channels with 10-bit resolution. The A/D converter
ister. The ADC operates within a range of 2 to
16MHz, with typical ADCCLK frequency at 8MHz.
The conversion time is 4µs typical at 8MHz.
The processing of conversion starts when the
Start Bit ADST is set to '1.' After one cycle, it is
cleared by hardware. The ADC is monotonic with
no missing codes. Measurement is by continuous
conversion of the analog input. The ADAT register
contains the results of the A/D conversion. When
conversion is complete, the result is loaded into
the ADAT. The A/D Conversion Status Bit ADSF is
set to '1.' The block diagram of the A/D module is
shown in Figure 22. The A/D status bit ADSF is set
automatically when A/D conversion is completed
and cleared when A/D conversion is in process.
has its own V
input (80-pin package only),
REF
which specifies the voltage reference for the A/D
operations. The analog to digital converter (A/D)
allows conversion of an analog input to a corre-
sponding 10-bit digital value. The A/D module has
eight analog inputs (P1.0 through P1.7) to an 8x1
multiplexor. One ADC channel is selected by the
bits in the configuration register. The converter
generates a 10-bits result via successive approxi-
mation. The analog supply voltage is connected to
the V
input, which powers the resistance lad-
REF
der in the A/D module.
In addition, the ADC unit sets the interrupt flag in
the ACON register after a conversion is complete
(if AINTEN is set to '1'). The ADC interrupts the
CPU when the enable bit AINTEN is set.
The A/D module has 3 registers, the control regis-
ter ACON, the A/D result register ADAT0, and the
second A/D result register ADAT1. The ADAT0
register stores Bits 0.. 7 of the converter output,
Bits 8.. 9 are stored in Bits 0..1 of the ADAT1 reg-
ister. The ACON register controls the operation of
the A/D converter module. Three of the bits in the
ACON register select the analog channel inputs,
and the remaining bits control the converter oper-
ation.
ADC channel pin input is enabled by setting the
corresponding bit in the P1SFS0 and P1SFS1 reg-
isters to '1' and the channel select bits in the
ACON register.
Port 1 ADC Channel Selects
The P1SFS0 and P1SFS1 Registers control the
selection of the Port 1 pin functions. When the
P1SFS0 Bit is '0,' the pin functions as a GPIO.
When bits are set to '1,' the pins are configured as
alternate functions. A new P1SFS1 Register se-
lects which of the alternate functions is enabled.
The ADC channel is enabled when the bit in
P1SFS1 is set to '1.'
Note: In the 52-pin package, there is no individual
The ADC reference clock (ADCCLK) is generated
V
pin.
REF
from f
divided by the divider in the ADCPS reg-
OSC
Figure 22. 10-Bit ADC
AVREF
AVREF
P1.0
ADC0
P1.1
ADC1
P1.2
10-BIT SAR ADC
ADC2
ANALOG
MUX
P1.3
ADC3
P1.4
ADC4
P1.5
CONTROL
ADC OUT - 10 BITS
ADC5
P1.6
ADC6
P1.7
ADC7
SELECT
ADAT1
REG
ACON REG
ADAT 0 REG
AI07856
56/123
µPSD33XX
Table 63. ACON Register (97H, Reset Value 00H)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
AINTF
AINTEN
ADEN
ADS2
ADS1
ADS0
ADST
ADSF
Table 64. ACON Register Details
Bit
Symbol
Function
ADC Interrupt flag. This bit must be cleared with software.
0 = No interrupt request
1 = The AINTF flag is set when ADSF goes from '0' to '1.' Interrupts CPU when both
AINTF and AINTEN are set to '1.'
7
AINTF
ADC Interrupt Enable
6
5
AINTEN
ADEN
0 = ADC interrupt is disabled
1 = ADC interrupt is enabled
ADC Enable Bit
0 = ADC shut off and consumes no operating current
1 = Enable ADC. ADC must be enabled before setting the ADST Bit.
Analog channel Select
000 Select channel 0 (P1.0)
001 Select channel 0 (P1.1)
010 Select channel 0 (P1.2)
011 Select channel 0 (P1.3)
101 Select channel 0 (P1.5)
110 Select channel 0 (P1.6)
111 Select channel 0 (P1.7)
4.. 2
ADS2.. 0
ADC Start Bit
1
0
ADST
ADSF
0 = Force to zero
1 = Start and ADC, then after one cycle, the bit is cleared to '0.'
ADC Status Bit
0 = ADC conversion is not completed
1 = ADC conversion is completed. The bit can also be cleared with software.
Table 65. ADCPS Register Details (94H, Reset Value 00H)
Bit
Symbol
Function
7:4
–
Reserved
ADC Conversion Reference Clock Enable
0 = ADC reference clock is disabled (default)
1 = ADC reference clock is enabled
3
ADCCE
ADC Reference Clock PreScaler
ADCPS[2:0]
f
= f
/2
ACLK
OSC
2:0
ADCPS[2:0]
2
Example: for f
= 40MHz and ADCPS[2:0] = 2, the f
= 40/2 = 10MHz. f
ACLK ACLK
OSC
frequency range must be 2–16MHz.
Table 66. ADAT0 Register (95H, Reset Value 00H)
Bit
Symbol
Function
Function
7:0
–
Store ADC output, Bit 7 - 0
Table 67. ADAT1 Register (96H, Reset Value 00H)
Bit
7:2
Symbol
–
–
Reserved
1.. 0
Store ADC output, Bit 9, 8
57/123
µPSD33XX
PROGRAMMABLE COUNTER ARRAY (PCA) WITH PWM
There are two Programmable Counter Array
blocks (PCA0 and PCA1) in the µPSD33XX. A
PCA block consists of a 16-bit up-counter, which is
shared by three TCM (Timer Counter Module). A
TCM can be programmed to perform one of the
following four functions:
1. Capture Mode: capture counter values by
external input signals
2. Timer Mode
of clock input: from an external pin, Timer 0 Over-
flow, or PCA Clock.
A PCA block has 3 Timer Counter Modules (TCM)
which share the 16-bit Counter output. The TCM
can be configured to capture or compare counter
value, generate a toggling output, or PWM func-
tions. Except for the PWM function, the other TCM
functions can generate an interrupt when an event
occurs.
Every TCM is connected to a port pin in Port 4; the
TCM pin can be configured as an event input, a
PWMs, a Toggle Output, or as External Clock In-
put. The pins are general I/O pins when not as-
signed to the TCM.
3. Toggle Output Mode
4. PWM Mode: fixed frequency (8-bit or 16-bit),
programmable frequency (8-bit only)
PCA Block
The 16-bit Up-Counter in the PCA block is a free-
running counter (except in PWM Mode with pro-
grammable frequency). The Counter has a choice
The TCM operation is configured by Control regis-
ters and Capture/Compare registers. Table 68,
page 59 lists the SFR registers in the PCA blocks.
Figure 23. PCA0 Block Diagram
16-bit up Timer/Counter
PCA0CLK
TIMER0
OVERFLOW
PCACH0
8-bit
PCACL0
8-bit
INT
OVF0
P4.3/ECI
EOVFI
P4.0/CEX0
P4.1/CEX1
TCM0
CLKSEL0
CLKSEL1
EN_ALL
EN_PCA
TCM1
TCM2
PCAIDLE
P4.2/CEX2
IDLE MODE
(From CPU)
PWM FREQ
COMPARE
CLEAR COUNTER
AI07857
58/123
µPSD33XX
Table 68. PCA0 and PCA1 Registers
SFR Address
Register Name
RW
Register Function
PCA0
PCA1
PCA0
PCA1
A2
A3
PCACL0
PCACH0
PCACL1
PCACH1
RW
RW
The low 8 bits of PCA 16-bit counter.
The high 8 bits of PCA 16-bit counter.
Control Register
A4
A5
PCACON0
PCASTA
PCACON1
N/A
RW
RW
■ Enable PCA, Timer Overflow flag , PCA
Idle Mode, and Select clock source.
Status Register, Interrupt Status flags
■ Common for both PCA Block 0 and 1.
TCM Mode
■ Capture, Compare, and Toggle Enable
Interrupts
A9,
AA,
AB
BD,
BE,
BF
TCMMODE0
TCMMODE1
TCMMODE2
TCMMODE3
TCMMODE4
TCMMODE5
RW
■ PWM Mode Select.
AC
AD
C1
C2
CAPCOML0
CAPCOMH0
CAPCOML3
CAPCOMH3
RW
RW
RW
Capture/Compare registers of TCM0
Capture/Compare registers of TCM1
Capture/Compare registers of TCM2
AF
B1
C3
C4
CAPCOML1
CAPCOMH1
CAPCOML4
CAPCOMH4
B2
B3
C5
C6
CAPCOML2
CAPCOMH2
CAPCOML5
CAPCOMH5
The 8-bit register to program the PWM
frequency. This register is used for
programmable, 8-bit PWM Mode only.
B4
C7
PWMF0
PWMF1
RW
Operation of TCM Modes
Toggle Mode
Each of the TCM in a PCA block supports four
modes of operation. However, an exception is
when the TCM is configured in PWM Mode with
programmable frequency. In this mode, all TCM in
a PCA block must be configured in the same mode
or left to be not used.
In this mode, the user writes a value to the TCM's
CAPCOM registers and enables the comparator.
When there is a match with the Counter output, the
output of the TCM pin toggles. This mode is a sim-
ple extension of the Timer Mode.
PWM Mode - (X8), Fixed Frequency
Capture Mode
In this mode, one or all the TCM's can be config-
ured to have a fixed frequency PWM output on the
port pins. The PWM frequency depends on when
the low byte of the Counter overflows (module
256). The duty cycle of each TCM module can be
specified in the CAPCOMHn register. When the
PCA_Counter_L value is equal to or greater than
the value in CAPCOMHn, the PWM output is
The CAPCOM registers in the TCM are loaded
with the counter values when an external pin input
changes state. The user can configure the counter
value to be loaded by positive edge, negative edge
or any transition of the input signal. At loading, the
TCM can generate an interrupt if it is enabled.
Timer Mode
switched to
a
high state. When the
The TCM modules can be configured as software
timers by enable the comparator. The user writes
a value to the CAPCOM registers, which is then
compared with the 16-bit counter. If there is a
match, an interrupt can be generated to CPU.
PCA_Counter_L Register overflows, the content
in CAPCOMHn is loaded to CAPCOMLn and a
new PWM pulse starts.
59/123
µPSD33XX
Figure 24. Timer Mode
MATCH_TIMER
INTR
INTFn
CAPCOMLn
CAPCOMHn
PCASTA
8
8
ENABLE
16-bit COMPARATOR
MATCH
8
8
PCACLm
PCACHm
16-bit up Timer/Counter
TOGGLE
0
PWM1
0
PWM0
0
TCMMODEn
E_COMP CAP_PE CAP_NE MATCH
EINTF
0
0
RESET
WRITE to
CAPCOMHn
1
0
C
D
EN_FLAG
WRITE to
CAPCOMLn
AI07858
Note: m = 0: n = 0, 1, or 2
m = 1: n = 3, 4, or 5
Figure 25. PWM Mode - (X8), Fixed Frequency
CAPCOMHn
8
CAPCOMLn
ENABLE
MATCH
SET
CLR
8-bit COMPARATORn
Q
Q
S
R
CEXn
8
OVERFLOW
PCACLm
TOGGLE
0
PWM1
PWM0
TCMMODEn
E_COMP CAP_PE CAP_NE MATCH
EINTF
0
0
0
0
AI07859
Note: m = 0: n = 0, 1, or 2
m = 1: n = 3, 4, or 5
60/123
µPSD33XX
PWM Mode - (X8), Programmable Frequency
In this mode, the PWM frequency is not deter-
mined by the overflow of the low byte of the
Counter. Instead, the frequency is determined by
the PWMFm register. The user can load a value in
the PWMFm register, which is then compared to
the low byte of the Counter. If there is a match, the
Counter is cleared and the Load registers (PWM-
Fm, CAPCOMHn) are re-loaded for the next PWM
pulse. There is only one PWMFm Register which
serves all 3 TCM in a PCA block.
If one of the TCM modules is operating in this
mode, the other modules in the PCA must be con-
figured to the same mode or left not to be used.
The duty cycle of the PWM can be specified in the
CAPCOMHn register as in the PWM with fixed fre-
quency mode. Different TCM modules can have
their own duty cycle.
Note: The value in the Frequency register (PWM-
Fm) must be larger than the duty cycle register
(CAPCOM).
Figure 26. PWM Mode - (X8) Programmable Frequency
PWM FREQ COMPARE
PWMFm
CAPCOMHn
8
8
PWMFm = PCACLm
CAPCOMLn
PCACHm
MATCH
SET
CLR
Q
Q
S
R
CEXn
ENABLE
ENABLE
8-bit COMPARATORm
8-bit COMPARATORn
8
PCACLm
CLR
TOGGLE
0
PWM1
PWM0
TCMMODEn
E_COMP CAP_PE CAP_NE MATCH
EINTF
0
0
0
0
AI07860
Note: m = 0: n = 0, 1, or 2
m = 1: n = 3, 4, or 5
61/123
µPSD33XX
PWM Mode - Fixed Frequency, 16-bit
The operation of the 16-bit PWM is the same as
the 8-bit PWM with fixed frequency. In this mode,
one or all the TCM can be configured to have a
fixed frequency PWM output on the port pins. The
PWM frequency is depending on the clock input
frequency to the 16-bit Counter. The duty cycle of
each TCM module can be specified in the CAP-
COMHn and CAPCOMLn registers. When the 16
bit PCA_Counter is equal or greater than the val-
ues in registers CAPCOMHn and CAPCOMLn, the
PWM output is switched to a high state. When the
PCA_Counter overflows, CEXn is asserted low.
E_COMP bit to '0'; writing to CAPCOMHn sets
E_COMP to '1' the largest duty cycle is 100%
(CAPCOMHn CAPCOMLn = 0x0000), and the
smallest duty cycle is 0.0015% (CAPCOMHn
CAPCOMLn = 0xFFFF). A 0% duty cycle may be
generated by clearing the E_COMP bit to ‘0’.
Control Register Bit Definition
Each PCA has its own PCA_CONFIGn, and each
module within the PCA block has its own
TCM_Mode Register which defines the operation
of that module (see Table 69 through Table 71).
There is one PCA_STATUS Register that covers
both PCA0 and PCA1 (see Table 72, page 62 and
Table 73, page 63).
Writing to Capture/Compare Registers
When writing a 16-bit value to the PCA0 Capture/
Compare registers, the low byte should always be
written first. Writing to CAPCOMLn clears the
Table 69. PCA0 Control Register PCACON0 (0A4H, Reset Value 00H)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
–
Bit 2
–
Bit 1
Bit 0
EN-ALL
EN_PCA
EOVFI
PCAIDLE
CLK_SEL[1:0]
Table 70. PCA1 Control Register PCACON0 (0BCH, Reset Value 00H)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
–
Bit 2
–
Bit 1
Bit 0
EN-ALL
EN_PCA
EOVFI
PCAIDLE
CLK_SEL[1:0]
Table 71. PCA0, PCA1 Register Details
Bit
Symbol
Function
0 = No impact on TCM modules
1 = Enable both PCA counters simultaneously (override the EN_PCA Bits)
This bit is to synchronize the two 16-bit counters in the PCA. For customers who want 5
PWM, for example, this bit can synchronize all of the PWM outputs.
7
EN-ALL
0 = PCA counter is disabled
1 = PCA counter is enabled
EN_PCA Counter Run Control Bit. Set with software to turn the PCA counter on. Must
6
EN_PCA
be cleared with software to turn the PCA counter off.
5
4
EOVFI
PCAIDLE
–
1 = Enable Counter Overflow Interrupt if overflow flag (OVF) is set
0 = PCA operates when CPU is in Idle Mode
1 = PCA stops running when CPU is in Idle Mode
3-2
Reserved
00 Select Prescaler clock as Counter clock
01 Select Timer 0 Overflow
10 Select External Clock pin (P4.3 for PCA0, P4.7 for PCA1) (MAX clock rate = f
CLK_SEL
[1:0]
1-0
/4)
OSC
Table 72. PCA Status Register PCASTA (0A5H, Reset Value 00H)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INTF0
OVF1
INTF5
INTF4
INTF3
OVF0
INTF2
INTF1
62/123
µPSD33XX
Table 73. PCA Status Register PCASTA Details
Bit
Symbol
Function
PCA1 Counter OverFlow flag.
Set by hardware when the counter rolls over. OVF1 flags an interrupt if Bit EOVFI in
PCACON1 is set. OVF1 may be set with either hardware or software but can only be
cleared with software.
7
OFV1
TCM5 Interrupt flag.
6
5
4
INTF5
INTF4
INTF3
Set by hardware when a match or capture event occurs.
Must be clear with software.
TCM4 Interrupt flag.
Set by hardware when a match or capture event occurs.
Must be clear with software.
TCM3 Interrupt flag.
Set by hardware when a match or capture event occurs.
Must be clear with software.
PCA0 Counter OverFlow flag.
Set by hardware when the counter rolls over. OVF0 flags an interrupt if Bit EOVFI in
PCACON0 is set. OVF1 may be set with either hardware or software but can only be
cleared with software.
3
OVF0
TCM2 Interrupt flag.
2
1
0
INTF2
INTF1
INTF0
Set by hardware when a match or capture event occurs.
Must be clear with software.
TCM1 Interrupt flag.
Set by hardware when a match or capture event occurs.
Must be clear with software.
TCM0 Interrupt flag.
Set by hardware when a match or capture event occurs.
Must be clear with software.
TCM Interrupts
There are 8 TCM interrupts: 6 match or capture in-
terrupts and two counter overflow interrupts. The 8
interrupts are “ORed” as one PCA interrupt to the
CPU. By the nature of PCA application, it is unlike-
ly that many of the interrupts occur simultaneous-
ly. If they do, the CPU has to read the interrupt
flags and determine which one to serve. The soft-
ware has to clear the interrupt flag in the Status
Register after serving the interrupt.
Table 74. TCMMODE0 - TCMMODE5 (6 Registers, Reset Value 00H)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
EINTF
E_COMP
CAP_PE
CAP_NE
MATCH
TOGGLE
PWM[1:0]
63/123
µPSD33XX
Table 75. TCMMODE0 - TCMMODE5 Register Details
e
7
6
5
4
3
2
Symbol
EINTF
Function
1 - Enable the interrupt flags (INTF) in the Status Register to generate an interrupt.
1 - Enable the comparator when set
E_COMP
CAP_PE
CAP_NE
MATCH
TOGGLE
1 - Enable Capture Mode, a positive edge on the CEXn pin.
1 - Enable Capture Mode, a negative edge on the CEXn pin.
1 - A match from the comparator sets the INTF bits in the Status Register.
1 - A match on the comparator results in a toggling output on CEXn pin.
01 Enable PWM Mode (x8), fixed frequency. Enable the CEXn pin as a PWM output.
10 Enable PWM Mode (x8) with programmable frequency. Enable the CEXn pin as a
PWM output.
1-0
PWM[1:0]
11 Enable PWM Mode (x16), fixed frequency. Enable the CEXn pin as a PWM output.
Table 76. TCMMODE Register Configurations
EINTF E_COMP CAP_PE CAP_NE MATCH TOGGLE PWM1 PWM0
TCM FUNCTION
No operation (reset value)
8-bit PWM, fixed frequency
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
1
8-bit PWM, programmable
frequency
0
1
0
0
0
0
1
0
0
X
X
X
X
X
1
1
0
0
0
0
1
1
0
0
0
1
0
1
0
1
1
0
0
0
0
1
0
0
0
0
1
0
0
0
0
0
1
0
0
0
0
0
16-bit PWM, fixed frequency
16-bit toggle
1
16-bit Software Timer
X
X
X
16-bit capture, negative trigger
16-bit capture, positive trigger
16-bit capture, transition trigger
64/123
µPSD33XX
PSD MODULE
■ The PSD Module provides configurable
Program and Data memories to the Turbo 8032
MCU Module. In addition, it has its own set of I/
O ports and a PLD with 16 macrocells for
general logic implementation.
■ Ports A,B,C, and D are general purpose
programmable I/O ports that have a port
architecture which is different from the I/O ports
in the MCU Module.
Examples include state machines, loadable
shift registers, and loadable counters.
■ Decode PLD (DPLD) that decodes address for
selection of memory blocks in the PSD Module.
■ Configurable I/O ports (Port A,B,C and D) that
can be used for the following functions:
– MCU I/Os
– PLD I/Os
■ The PSD Module communicates with the MCU
Module through the internal address, data bus
(A0-A15, D0-D7) and control signals (RD, WR,
PSEN, ALE, RESET). The user defines the
Decoding PLD in the PSDsoft Development
Tool and can map the resources in the PSD
Module to any program or data address space.
Figure 27, page 66 shows the functional blocks
in the PSD Module.
– Latched MCU address output
– Special function I/Os.
– I/O ports may be configured as open-drain
outputs.
■ Built-in JTAG compliant serial port allows full-
chip In-System Programmability (ISP). With it,
you can program a blank device or reprogram a
device in the factory or the field.
■ Internal page register that can be used to
expand the 8032 MCU Module address space
by a factor of 256.
■ Internal programmable Power Management
Unit (PMU) that supports a low-power mode
called Power-down Mode. The PMU can
automatically detect a lack of the 8032 CPU
core activity and put the PSD Module into
Power-down Mode.
Functional Overview
■ 64K, 128K, or 256K bytes Flash memory. This
is the main Flash memory. It is divided into
equally-sized blocks that can be accessed with
user-specified addresses.
■ Secondary 16K or 32K bytes Flash boot
memory. It is divided into equally-sized blocks
that can be accessed with user-specified
addresses. This secondary memory brings the
ability to execute code and update the main
Flash concurrently.
■ 2K, 8K, or 32K bytes SRAM. The SRAM’s
contents can be protected from a power failure
by connecting an external battery.
■ CPLD with 16 Output Micro Cells (OMCs} and
20 Input Micro Cells (IMCs). The CPLD may be
used to efficiently implement a variety of logic
functions for internal and external control.
■ Erase/WRITE cycles:
– Flash memory - 100,000 minimum
– PLD - 1,000 minimum
– Data Retention: 15 year minimum (for Main
Flash memory, Boot, PLD and Configuration
bits)
65/123
µPSD33XX
Figure 27. PSD Module Block Diagram
AI07872
66/123
µPSD33XX
PSD MODULE REGISTER DESCRIPTION AND ADDRESS OFFSET
Table 77 shows the offset addresses to the PSD
Module registers relative to the CSIOP base ad-
dress. The CSIOP space is the 256 bytes of ad-
dress that is allocated by the user to the internal
PSD Module registers. Table 79, page 69 provides
brief descriptions of the registers in CSIOP space.
The following section gives a more detailed de-
scription.
Table 77. Register Address Offset
(1)
Register Name
Data In
Port A Port B Port C Port D
Description
Other
00
02
01
03
10
11
Reads Port pin as input, MCU I/O Input Mode
Selects mode between MCU I/O or Address Out
Control
Stores data for output to Port pins, MCU I/O
Output Mode
Data Out
Direction
04
06
05
07
12
14
13
15
Configures Port pin as input or output
Configures Port pins as either CMOS or Open
Drain on some pins, while selecting high slew
rate on other pins.
Drive Select
08
09
16
17
Input Macrocell
Enable Out
0A
0C
0B
0D
18
1A
Reads Input Macrocells
Reads the status of the output enable to the I/O
Port driver
1B
Output Macrocells
AB
READ – reads output of macrocells AB
WRITE – loads macrocell flip-flops
20
20
21
Output Macrocells
BC
READ – reads output of macrocells BC
WRITE – loads macrocell flip-flops
21
23
Mask Macrocells AB 22
Mask Macrocells BC
22
23
Blocks writing to the Output Macrocells AB
Blocks writing to the Output Macrocells BC
Primary Flash
Protection
C0
C2
Read-only – Primary Flash Sector Protection
Secondary Flash
memory Protection
Read-only – PSD Module Security and
Secondary Flash memory Sector Protection
PMMR0
PMMR2
Page
B0
B4
E0
Power Management Register 0
Power Management Register 2
Page Register
Places PSD Module memory areas in Program
and/or Data space on an individual basis.
VM
E2
Note: 1. Other registers that are not part of the I/O ports.
67/123
µPSD33XX
PSD MODULE DETAILED OPERATION
As shown in Figure 27, page 66, the PSD Module
consists of five major types of functional blocks:
During a Program or Erase cycle in Flash memory,
the status can be output on Ready/Busy (PC3).
This pin is set up using PSDsoft Express Configu-
ration.
■ Memory Block
■ PLD Blocks
Memory Block Select Signals
■ I/O Ports
The DPLD generates the Select signals for all the
internal memory blocks (see the section entitled
“PLDs,” page 78). Each of the sectors of the pri-
mary Flash memory has a Select signal (FS0-FS7)
which can contain up to three product terms. Each
of the four sectors of the secondary Flash memory
has a Select signal (CSBOOT0-CSBOOT3) which
can contain up to three product terms. Having
three product terms for each Select signal allows
a given sector to be mapped in Program or Data
space.
■ Power Management Unit (PMU)
■ JTAG Interface
The functions of each block are described in the
following sections. Many of the blocks perform
multiple functions, and are user configurable.
MEMORY BLOCKS
The PSD Module has the following memory blocks
(see Table 78):
– Primary Flash memory
– Secondary Flash memory
– SRAM
The Memory Select signals for these blocks origi-
nate from the Decode PLD (DPLD) and are user-
defined in PSDsoft Express.
Primary Flash Memory and Secondary Flash
memory Description
The primary Flash memory is divided evenly into
eight equal sectors. The secondary Flash memory
is divided into four equal sectors. Each sector of
either memory block can be separately protected
from Program and Erase cycles.
Flash memory may be erased on a sector-by-sec-
tor basis. Flash sector erasure may be suspended
while data is read from other sectors of the block
and then resumed after reading.
Flash Memory Instructions
The Flash memory instructions are detailed in Ta-
ble 79. For efficient decoding of the instructions,
the first two bytes of an instruction are the coded
cycles and are followed by an instruction byte or
confirmation byte. The coded cycles consist of
writing the data AAh to address X555h during the
first cycle and data 55h to address XAAAh during
the second cycle. Address signals A15-A12 are
Don’t Care during the instruction WRITE cycles.
However, the appropriate Sector Select (FS0-FS7
or CSBOOT0-CSBOOT3) must be selected.
The primary and secondary Flash memories have
the same instruction set (except for Read Primary
Flash Identifier). The Sector Select signals deter-
mine which Flash memory is to receive and exe-
cute the instruction. The primary Flash memory is
selected if any one of Sector Select (FS0-FS7) is
High, and the secondary Flash memory is selected
if any one of Sector Select (CSBOOT0-
CSBOOT3) is High.
Table 78. µPSD33XX Memory Configuration
Main Flash
Secondary Flash
# of Sectors
Flash Size Sector Size (Sector Select
Signal)
SRAM
Size
# of Sectors
Flash Size Sector Size (Sector Select
Signal)
Device
µPSD3312
µPSD3333
µPSD3334
µPSD3354
64KB
128KB
256KB
256KB
16KB
16KB
32KB
32KB
4 (FS0-3)
8 (FS0-7)
8 (FS0-7)
8 (FS0-7)
16KB
32KB
32KB
32KB
8KB
8KB
8KB
8KB
2 (CSBOOT0-1)
4 (CSBOOT0-3)
2KB
8KB
4 (CSBOOT0-3) 32KB
4 (CSBOOT0-3) 32KB
68/123
µPSD33XX
Table 79. Instructions
FS0-FS7 or
Instruction
CSBOOT0-
Cycle 1
Cycle 2 Cycle 3
Cycle 4
Cycle 5 Cycle 6 Cycle 7
CSBOOT3
“Read”
RD @ RA
(5)
1
1
1
1
1
1
READ
READ Sector
AAh@
X555h
55h@
XAAAh
90h@
X555h
Read status @
XX02h
(6,8,13)
Protection
Program a Flash
AAh@
X555h
55h@
XAAAh
A0h@
X555h
PD@ PA
(13)
Byte
7
Flash Sector
AAh@
X555h
55h@
XAAAh
80h@
X555h
55h@
XAAAh
30h@
SA
30h @
AAh@ X555h
AAh@ X555h
(7,13)
Erase
next SA
Flash Bulk
AAh@
X555h
55h@
XAAAh
80h@
X555h
55h@
XAAAh
10h@
X555h
(13)
Erase
Suspend Sector
B0h@
XXXXh
(11)
Erase
Resume Sector
30h@
XXXXh
1
1
1
1
(12)
Erase
F0h@
XXXXh
(6)
RESET
AAh@
X555h
55h@
XAAAh
20h@
X555h
Unlock Bypass
Unlock Bypass
A0h@
XXXXh
PD@ PA
(9)
Program
Unlock Bypass
90h@
XXXXh
00h@
XXXXh
1
(10)
Reset
Note: 1. All bus cycles are WRITE bus cycles, except the ones with the “Read” label
2. All values are in hexadecimal:
X = Don’t care. Addresses of the form XXXXh, in this table, must be even addresses
RA = Address of the memory location to be read
RD = Data READ from location RA during the READ cycle
PA = Address of the memory location to be programmed. Addresses are latched on the falling edge of WRITE Strobe (WR, CNTL0).
PA is an even address for PSD in Word Programming Mode.
PD = Data word to be programmed at location PA. Data is latched on the rising edge of WRITE Strobe (WR, CNTL0)
SA = Address of the sector to be erased or verified. The Sector Select (FS0-FS7 or CSBOOT0-CSBOOT3) of the sector to be
erased, or verified, must be Active (High).
3. Sector Select (FS0-FS7 or CSBOOT0-CSBOOT3) signals are active High, and are defined in PSDsoft Express.
4. Only address Bits A11-A0 are used in instruction decoding.
5. No Unlock or instruction cycles are required when the device is in the READ Mode
6. The RESET instruction is required to return to the READ Mode after reading the Sector Protection Status, or if the Error Flag Bit
(DQ5/DQ13) goes High.
7. Additional sectors to be erased must be written at the end of the Sector Erase instruction within 80µs.
8. The data is 00h for an unprotected sector, and 01h for a protected sector. In the fourth cycle, the Sector Select is active, and
(A1,A0)=(1,0)
9. The Unlock Bypass instruction is required prior to the Unlock Bypass Program instruction.
10. The Unlock Bypass Reset Flash instruction is required to return to reading memory data when the device is in the Unlock Bypass
Mode.
11. The system may perform READ and Program cycles in non-erasing sectors, read the Flash ID or read the Sector Protection Status
when in the Suspend Sector Erase Mode. The Suspend Sector Erase instruction is valid only during a Sector Erase cycle.
12. The Resume Sector Erase instruction is valid only during the Suspend Sector Erase Mode.
13. The MCU cannot invoke these instructions while executing code from the same Flash memory as that for which the instruction is
intended. The MCU must retrieve, for example, the code from the secondary Flash memory when reading the Sector Protection
Status of the primary Flash memory.
69/123
µPSD33XX
READ Flash Memory
After power-up, the MCU may read the primary
Flash memory or the secondary Flash memory us-
ing READ operations just as it would a ROM or
RAM device. Alternately, the MCU may use READ
operations to obtain status information about a
Program or Erase cycle that is currently in
progress. Lastly, the MCU may use instructions to
read sector protection and the Erase/Program sta-
tus bits.
Toggle Flag (DQ6). The Flash memory offers an-
other way for determining when the Program cycle
is completed. During the internal WRITE operation
and when either the FS0-FS7 or CSBOOT0-
CSBOOT3 is true, the Toggle Flag Bit (DQ6) tog-
gles from '0' to '1' and '1' to '0' on subsequent at-
tempts to read any byte of the memory.
When the internal cycle is complete, the toggling
stops and the data READ on the Data Bus D0-D7
is the addressed memory byte. The device is now
accessible for a new READ or WRITE operation.
The cycle is finished when two successive Reads
yield the same output data.
Reading the Erase/Program Status Bits. The
Flash memory provides several status bits to be
used by the MCU to confirm the completion of an
Erase or Program cycle of Flash memory. These
status bits minimize the time that the MCU spends
performing these tasks and are defined in Table
80, page 71. The status bits can be read as many
times as needed.
■ The Toggle Flag Bit (DQ6) is effective after the
fourth WRITE pulse (for a Program instruction)
or after the sixth WRITE pulse (for an Erase
instruction).
For Flash memory, the MCU can perform a READ
operation to obtain these status bits while an
Erase or Program instruction is being executed by
the embedded algorithm. See the section entitled
“Programming Flash Memory, page 71,” for de-
tails.
Data Polling Flag (DQ7). When erasing or pro-
gramming in Flash memory, the Data Polling Flag
Bit (DQ7) outputs the complement of the bit being
entered for programming/writing on the DQ7 Bit.
Once the Program instruction or the WRITE oper-
ation is completed, the true logic value is read on
the Data Polling Flag Bit (DQ7) (in a READ opera-
tion).
■ Data Polling is effective after the fourth WRITE
pulse (for a Program instruction) or after the
sixth WRITE pulse (for an Erase instruction). It
must be performed at the address being
programmed or at an address within the Flash
memory sector being erased.
■ During an Erase cycle, the Data Polling Flag Bit
(DQ7) outputs a '0.' After completion of the
cycle, the Data Polling Flag Bit (DQ7) outputs
the last bit programmed (it is a '1' after erasing).
■ If the byte to be programmed belongs to a
protected Flash memory sector, the instruction
is ignored.
■ If all the Flash memory sectors selected for
erasure are protected, the Toggle Flag Bit
(DQ6) toggles to '0' for about 100µs and then
returns to the previous addressed byte.
Error Flag (DQ5). During a normal Program or
Erase cycle, the Error Flag Bit (DQ5) is to '0.' This
bit is set to '1' when there is a failure during Flash
memory Byte Program, Sector Erase, or Bulk
Erase cycle.
In the case of Flash memory programming, the Er-
ror Flag Bit (DQ5) indicates the attempt to program
a Flash memory bit from the programmed state,
'0', to the erased state, '1,' which is not valid. The
Error Flag Bit (DQ5) may also indicate a Time-out
condition while attempting to program a byte.
In case of an error in a Flash memory Sector Erase
or Byte Program cycle, the Flash memory sector in
which the error occurred or to which the pro-
grammed byte belongs must no longer be used.
Other Flash memory sectors may still be used.
The Error Flag Bit (DQ5) is reset after a Reset
Flash instruction.
Erase Time-out Flag (DQ3). The Erase Time-
out Flag Bit (DQ3) reflects the time-out period al-
lowed between two consecutive Sector Erase in-
structions. The Erase Time-out Flag Bit (DQ3) is
reset to '0' after a Sector Erase cycle for a time pe-
riod of 100µs + 20% unless an additional Sector
Erase instruction is decoded. After this time peri-
od, or when the additional Sector Erase instruction
is decoded, the Erase Time-out Flag Bit (DQ3) is
set to '1.'
■ If the byte to be programmed is in a protected
Flash memory sector, the instruction is ignored.
■ If all the Flash memory sectors to be erased are
protected, the Data Polling Flag Bit (DQ7) is
reset to '0' for about 100µs, and then returns to
the previous addressed byte. No erasure is
performed.
70/123
µPSD33XX
Table 80. Status Bit
Functional Block
FS0-FS7/
CSBOOT0-
CSBOOT3
(2)
(2)
(2)
(1,2)
(2)
(1,2)
(1,2)
(1,2)
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
Erase
Time-
out
Data
Polling
Toggle Error
Flag Flag
(3)
Flash Memory
X
X
X
X
V
IH
Note: 1. X = Not guaranteed value, can be read either '1' or '0.'
2. DQ7-DQ0 represent the Data Bus bits, D7-D0.
3. FS0-FS7 and CSBOOT0-CSBOOT3 are active High.
Programming Flash Memory
Flash memory must be erased prior to being pro-
grammed. A byte of Flash memory is erased to all
'1s' (FFh), and is programmed by setting selected
bits to '0.' The MCU may erase Flash memory all
at once or by-sector, but not byte-by-byte. Howev-
er, the MCU may program Flash memory byte-by-
byte.
Once the MCU issues a Flash memory Program or
Erase instruction, it must check for the status bits
for completion. The embedded algorithms that are
invoked support several means to provide status
to the MCU. Status may be checked using any of
three methods: Data Polling, Data Toggle, or
Ready/Busy (PC3).
The primary and secondary Flash memories re-
quire the MCU to send an instruction to program a
byte or to erase sectors (see Table 79, page 69).
Figure 28. Data Polling Flowchart
Figure 29. Data Toggle Flowchart
START
START
READ DQ5 & DQ7
at VALID ADDRESS
READ
DQ5 & DQ6
DQ6
NO
=
DQ7
=
DATA
YES
TOGGLE
NO
YES
NO
NO
DQ5
= 1
DQ5
= 1
YES
YES
READ DQ7
READ DQ6
DQ6
NO
TOGGLE
DQ7
=
DATA
YES
=
NO
YES
FAIL
PASS
FAIL
PASS
AI01369B
AI01370B
71/123
µPSD33XX
Unlock Bypass. The Unlock Bypass instructions
allow the system to program bytes to the Flash
memories faster than using the standard Program
instruction. The Unlock Bypass Mode is entered
by first initiating two Unlock cycles. This is followed
by a third WRITE cycle containing the Unlock By-
pass code, 20h (as shown in Table 79).
The Flash memory then enters the Unlock Bypass
Mode. A two-cycle Unlock Bypass Program in-
struction is all that is required to program in this
mode. The first cycle in this instruction contains
the Unlock Bypass Program code, A0h. The sec-
ond cycle contains the program address and data.
Additional data is programmed in the same man-
ner. These instructions dispense with the initial
two Unlock cycles required in the standard Pro-
gram instruction, resulting in faster total Flash
memory programming.
During the Unlock Bypass Mode, only the Unlock
Bypass Program and Unlock Bypass Reset Flash
instructions are valid.
To exit the Unlock Bypass Mode, the system must
issue the two-cycle Unlock Bypass Reset Flash in-
struction. The first cycle must contain the data
90h; the second cycle the data 00h. Addresses are
Don’t Care for both cycles. The Flash memory
then returns to READ Mode.
The status of the internal timer can be monitored
through the level of the Erase Time-out Flag Bit
(DQ3). If the Erase Time-out Flag Bit (DQ3) is '0,'
the Sector Erase instruction has been received
and the time-out period is counting. If the Erase
Time-out Flag Bit (DQ3) is '1,' the time-out period
has expired and the embedded algorithm is busy
erasing the Flash memory sector(s). Before and
during Erase time-out, any instruction other than
Suspend Sector Erase and Resume Sector Erase
instructions abort the cycle that is currently in
progress, and reset the device to READ Mode.
During a Sector Erase, the memory status may be
checked by reading the Error Flag Bit (DQ5), the
Toggle Flag Bit (DQ6), and the Data Polling Flag
Bit (DQ7), as detailed in Programming Flash Mem-
ory, page 71.
During execution of the Erase cycle, the Flash
memory accepts only RESET and Suspend Sec-
tor Erase instructions. Erasure of one Flash mem-
ory sector may be suspended, in order to read
data from another Flash memory sector, and then
resumed.
Suspend Sector Erase. When a Sector Erase
cycle is in progress, the Suspend Sector Erase in-
struction can be used to suspend the cycle by writ-
ing 0B0h to any address when an appropriate
Sector Select (FS0-FS7 or CSBOOT0-CSBOOT3)
is High. (See Table 79). This allows reading of
data from another Flash memory sector after the
Erase cycle has been suspended. Suspend Sec-
tor Erase is accepted only during an Erase cycle
and defaults to READ Mode. A Suspend Sector
Erase instruction executed during an Erase time-
out period, in addition to suspending the Erase cy-
cle, terminates the time out period.
Erasing Flash Memory
Flash Bulk Erase. The Flash Bulk Erase instruc-
tion uses six WRITE operations followed by a
READ operation of the status register, as de-
scribed in Table 79. If any byte of the Bulk Erase
instruction is wrong, the Bulk Erase instruction
aborts and the device is reset to the READ Flash
memory status.
During a Bulk Erase, the memory status may be
checked by reading the Error Flag Bit (DQ5), the
Toggle Flag Bit (DQ6), and the Data Polling Flag
Bit (DQ7), as detailed in Programming Flash Mem-
ory, page 71. The Error Flag Bit (DQ5) returns a '1'
if there has been an Erase Failure (maximum
number of Erase cycles have been executed).
It is not necessary to program the memory with
00h because the PSD Module automatically does
this before erasing to 0FFh.
The Toggle Flag Bit (DQ6) stops toggling when the
internal logic is suspended. The status of this bit
must be monitored at an address within the Flash
memory sector being erased. The Toggle Flag Bit
(DQ6) stops toggling between 0.1µs and 15µs af-
ter the Suspend Sector Erase instruction has been
executed. The Flash memory is then automatically
set to READ Mode.
If an Suspend Sector Erase instruction was exe-
cuted, the following rules apply:
– Attempting to read from a Flash memory sector
that was being erased outputs invalid data.
During execution of the Bulk Erase instruction, the
Flash memory does not accept any instructions.
Flash Sector Erase. The Sector Erase instruc-
tion uses six WRITE operations, as described in
Table 79. Additional Flash Sector Erase codes
and Flash memory sector addresses can be writ-
ten subsequently to erase other Flash memory
sectors in parallel, without further coded cycles, if
the additional bytes are transmitted in a shorter
time than the time-out period of about 100µs. The
input of a new Sector Erase code restarts the time-
out period.
– Reading from a Flash sector that was not being
erased is valid.
– The Flash memory cannot be programmed, and
only responds to Resume Sector Erase and
Reset Flash instructions (READ is an operation
and is allowed).
– If a Reset Flash instruction is received, data in
the Flash memory sector that was being erased
is invalid.
72/123
µPSD33XX
Resume Sector Erase. If
a
Suspend Sector
gram. This automatically protects selected sectors
when the device is programmed through the JTAG
Port or a Device Programmer. Flash memory sec-
tors can be unprotected to allow updating of their
contents using the JTAG Port or a Device Pro-
grammer. The MCU can read (but cannot change)
the sector protection bits.
Erase instruction was previously executed, the
erase cycle may be resumed with this instruction.
The Resume Sector Erase instruction consists of
writing 030h to any address while an appropriate
Sector Select (FS0-FS7 or CSBOOT0-CSBOOT3)
is High. (See Table 79.)
Specific Features
Flash Memory Sector Protect. Each
Any attempt to program or erase a protected Flash
memory sector is ignored by the device. The Verify
operation results in a READ of the protected data.
This allows a guarantee of the retention of the Pro-
tection status.
The sector protection status can be read by the
MCU through the Flash memory protection regis-
ters (in the CSIOP block). See Table 81 and Table
82.
primary
and secondary Flash memory sector can be sepa-
rately protected against Program and Erase cy-
cles. Sector Protection provides additional data
security because it disables all Program or Erase
cycles. This mode can be activated through the
JTAG Port or a Device Programmer.
Sector protection can be selected for each sector
using the PSDsoft Express Configuration pro-
Table 81. Sector Protection/Security Bit Definition – Flash Protection Register
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Sec7_Prot
Sec6_Prot
Sec5_Prot
Sec4_Prot
Sec3_Prot
Sec2_Prot
Sec1_Prot
Sec0_Prot
Note:
Bit Definitions:
Sec<i>_Prot 1 = Primary Flash memory or secondary Flash memory Sector <i> is write-protected.
Sec<i>_Prot 0 = Primary Flash memory or secondary Flash memory Sector <i> is not write-protected.
Table 82. Sector Protection/Security Bit Definition – Secondary Flash Protection Register
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Security_Bit
not used
not used
not used
Sec3_Prot
Sec2_Prot
Sec1_Prot
Sec0_Prot
Note:
Bit Definitions:
Sec<i>_Prot 1 = Secondary Flash memory Sector <i> is write-protected.
Sec<i>_Prot 0 = Secondary Flash memory Sector <i> is not write-protected.
Security_Bit 0 = Security Bit in device has not been set; 1 = Security Bit in device has been set.
73/123
µPSD33XX
Reset Flash. The Reset Flash instruction con-
sists of one WRITE cycle (see Table 79). It can
also be optionally preceded by the standard two
WRITE decoding cycles (writing AAh to 555h and
55h to AAAh). It must be executed after:
contents of the SRAM are retained in the event of
a power loss. The contents of the SRAM are re-
tained so long as the battery voltage remains at 2V
or greater. If the supply voltage falls below the bat-
tery voltage, an internal power switch-over to the
battery occurs.
– Reading the Flash Protection Status
PC4 can be configured as an output that indicates
when power is being drawn from the external bat-
– An Error condition has occurred (and the device
has set the Error Flag Bit (DQ5) to '1' during a
Flash memory Program or Erase cycle.
tery. Battery-on Indicator (V
, PC4) is High
BATON
with the supply voltage falls below the battery volt-
The Reset Flash instruction puts the Flash memo-
ry back into normal READ Mode. If an Error condi-
tion has occurred (and the device has set the Error
Flag Bit (DQ5) to '1' the Flash memory is put back
into normal READ Mode within 25µs of the Reset
Flash instruction having been issued. The Reset
Flash instruction is ignored when it is issued dur-
ing a Program or Bulk Erase cycle of the Flash
memory. The Reset Flash instruction aborts any
on-going Sector Erase cycle, and returns the
Flash memory to the normal READ Mode within
25µs.
Reset (RESET) Signal. A pulse on Reset (RE-
SET) aborts any cycle that is in progress, and re-
sets the Flash memory to the READ Mode. When
the reset occurs during a Program or Erase cycle,
the Flash memory takes up to 25µs to return to the
READ Mode. It is recommended that the Reset
(RESET) pulse (except for Power-on RESET, as
described on page 94) be at least 25µs so that the
Flash memory is always ready for the MCU to re-
trieve the bootstrap instructions after the reset cy-
cle is complete.
age and the battery on Voltage Stand-by (V
PC2) is supplying power to the internal SRAM.
SRAM Select (RS0), Voltage Stand-by (V
,
STBY
,
STBY
PC2) and Battery-on Indicator (V
, PC4) are
BATON
all configured using PSDsoft Express Configura-
tion.
Sector Select and SRAM Select
Sector Select (FS0-FS7, CSBOOT0-CSBOOT3)
and SRAM Select (RS0) are all outputs of the
DPLD. They are setup by writing equations for
them in PSDsoft Express. The following rules ap-
ply to the equations for these signals:
1. Primary Flash memory and secondary Flash
memory Sector Select signals must not be larg-
er than the physical sector size.
2. Any primary Flash memory sector must not be
mapped in the same memory space as another
Flash memory sector.
3. A secondary Flash memory sector must not be
mapped in the same memory space as another
secondary Flash memory sector.
4. SRAM, I/O, and Peripheral I/O spaces must not
overlap.
SRAM
The SRAM is enabled when SRAM Select (RS0)
from the DPLD is High. SRAM Select (RS0) can
contain up to two product terms, allowing flexible
memory mapping.
The SRAM can be backed up using an external
battery. The external battery should be connected
5. A secondary Flash memory sector may overlap
a primary Flash memory sector. In case of over-
lap, priority is given to the secondary Flash
memory sector.
6. SRAM, I/O, and Peripheral I/O spaces may
overlap any other memory sector. Priority is giv-
en to the SRAM, I/O, or Peripheral I/O.
to Voltage Stand-by (V
external battery connected to the µPSD3200, the
, PC2). If you have an
STBY
74/123
µPSD33XX
Example. FS0 is valid when the address is in the
range of 8000h to BFFFh, CSBOOT0 is valid from
8000h to 9FFFh, and RS0 is valid from 8000h to
87FFh. Any address in the range of RS0 always
accesses the SRAM. Any address in the range of
CSBOOT0 greater than 87FFh (and less than
9FFFh) automatically addresses secondary Flash
memory segment 0. Any address greater than
9FFFh accesses the primary Flash memory seg-
ment 0. You can see that half of the primary Flash
memory segment 0 and one-fourth of secondary
Flash memory segment 0 cannot be accessed in
this example.
changed by the MCU so that memory mapping
can be changed on-the-fly.
For example, you may wish to have SRAM and pri-
mary Flash memory in the Data space at Boot-up,
and secondary Flash memory in the Program
space at Boot-up, and later swap the primary and
secondary Flash memories. This is easily done
with the VM Register by using PSDsoft Express
Configuration to configure it for Boot-up and hav-
ing the MCU change it when desired. Table 83 de-
scribes the VM Register.
Figure 30. Priority Level of Memory and I/O
Components in the PSD Module
Note: An equation that defined FS1 to anywhere
in the range of 8000h to BFFFh would not be valid.
Figure 30 shows the priority levels for all memory
components. Any component on a higher level can
overlap and has priority over any component on a
lower level. Components on the same level must
not overlap. Level one has the highest priority and
level 3 has the lowest.
Memory Select Configuration in Program and
Data Spaces. The MCU Core has separate ad-
dress spaces for Program memory and Data
memory. Any of the memories within the PSD
Module can reside in either space or both spaces.
This is controlled through manipulation of the VM
Register that resides in the CSIOP space.
Highest Priority
Level 1
SRAM, I/O, or
Peripheral I/O
Level 2
Secondary
Non-Volatile Memory
Level 3
Primary Flash Memory
Lowest Priority
AI02867D
The VM Register is set using PSDsoft Express to
have an initial value. It can subsequently be
Table 83. VM Register
Bit 4
Bit 2
Primary
FL_Code
Bit 7
Bit 3
Secondary Data
Bit 1
Bit 0
Bit 6
Bit 5
Primary
FL_Data
PIO_EN
Secondary Code SRAM_Code
0 = RD
can’t
0 = PSEN
can’t
access Secondary access
0 = PSEN
0 = PSEN can’t
can’t
0 = RD can’t
0 = disable
PIO Mode
not used not used access
access Secondary
access
Flash
memory
Flash memory
Flash
memory
Flash memory
SRAM
1 = RD
1 = PSEN
access
Flash
1 = RD access
Secondary Flash
memory
1 = PSEN access 1 = PSEN
1= enable
PIO Mode
access
not used not used
Flash
Secondary Flash
memory
access
SRAM
memory
memory
75/123
µPSD33XX
Separate Space Mode. Program space is sepa-
rated from Data space. For example, Program Se-
lect Enable (PSEN) is used to access the program
code from the primary Flash memory, while READ
Strobe (RD) is used to access data from the sec-
ondary Flash memory, SRAM and I/O Port blocks.
This configuration requires the VM Register to be
set to 0Ch (see Figure 31).
Combined Space Modes. The Program and
Data spaces are combined into one memory
space that allows the primary Flash memory, sec-
ondary Flash memory, and SRAM to be accessed
by either Program Select Enable (PSEN) or READ
Strobe (RD). For example, to configure the prima-
ry Flash memory in Combined space, Bits b2 and
b4 of the VM Register are set to '1' (see Figure 32).
Figure 31. Separate Space Mode
Primary
Flash
Secondary
Flash
SRAM
DPLD
RS0
Memory
Memory
CSBOOT0-3
FS0-FS7
CS
CS
OE
CS
OE
OE
PSEN
RD
AI02869C
Figure 32. Combined Space Mode
Primary
Flash
Secondary
Flash
SRAM
DPLD
RS0
Memory
Memory
RD
CSBOOT0-3
FS0-FS7
CS
CS
OE
CS
OE
OE
VM REG BIT 3
VM REG BIT 4
PSEN
VM REG BIT 1
RD
VM REG BIT 2
VM REG BIT 0
AI02870C
76/123
µPSD33XX
Page Register
The 8-bit Page Register increases the addressing
capability of the MCU Core by a factor of up to 256.
The contents of the register can also be read by
the MCU. The outputs of the Page Register
(PGR0-PGR7) are inputs to the DPLD decoder
and can be included in the Sector Select (FS0-
FS7, CSBOOT0-CSBOOT3), and SRAM Select
(RS0) equations.
If memory paging is not needed, or if not all 8 page
register bits are needed for memory paging, then
these bits may be used in the CPLD for general
logic.
Figure 33 shows the Page Register. The eight flip-
flops in the register are connected to the internal
data bus D0-D7. The MCU can write to or read
from the Page Register. The Page Register can be
accessed at address location CSIOP + E0h.
Figure 33. Page Register
RESET
PGR0
INTERNAL PSD MODULE
SELECTS
AND LOGIC
D0
D1
D2
D3
D4
D5
D6
D7
Q0
PGR1
Q1
Q2
Q3
Q4
Q5
Q6
Q7
PGR2
D0 - D7
DPLD
AND
CPLD
PGR3
PGR4
PGR5
PGR6
PGR7
R/W
PAGE
REGISTER
PLD
AI05799
77/123
µPSD33XX
PLDS
The PLDs bring programmable logic functionality
to the µPSD. After specifying the logic for the
PLDs in PSDsoft Express, the logic is pro-
grammed into the device and available upon Pow-
er-up.
The PSD Module contains two PLDs: the Decode
PLD (DPLD), and the Complex PLD (CPLD).
Table 84. DPLD and CPLD Inputs
No. of
Signals
Input Source
Input Name
A15-A0
16
4
MCU Address Bus
PSEN, RD, WR,
ALE
MCU Control Signals
The DPLD performs address decoding for Select
signals for PSD Module components, such as
memory, registers, and I/O ports.
RESET
RST
PDN
1
1
Power-down
The CPLD can be used for logic functions, such as
loadable counters and shift registers, state ma-
chines, and encoding and decoding logic.
Port A Input
PA7-PA0
8
8
4
(1)
Macrocells
Port B Input
Macrocells
The Turbo Bit in PSD Module
PB7-PB0
PC2-4, PC7
The PLDs can minimize power consumption by
switching off when inputs remain unchanged for
an extended time of about 70ns. Resetting the
Turbo Bit to '0' (Bit 3 of PMMR0) automatically
places the PLDs into standby if no inputs are
changing. Turning the Turbo Mode off increases
propagation delays while reducing power con-
sumption. See POWER MANAGEMENT, page 90
for details on setting the Turbo Bit.
Port C Input
Macrocells
PD2-PD1
2
8
Port D Inputs
Page Register
PGR7-PGR0
Macrocell AB
Feedback
MCELLAB.FB7-
FB0
8
8
1
Macrocell BC
Feedback
MCELLBC.FB7-
FB0
Flash memory
Program Status Bit
Ready/Busy
Note: 1. These inputs are not available in the 52-pin package.
Figure 34. PLD Diagram
8
PAGE
DATA
BUS
REGISTER
8
73
DECODE PLD
PRIMARY FLASH MEMORY SELECTS
4
1
1
2
SECONDARY NON-VOLATILE MEMORY SELECTS
SRAM SELECT
CSIOP SELECT
PERIPHERAL SELECTS
OUTPUT MACROCELL FEEDBACK
CPLD
DIRECT MACROCELL ACCESS FROM MCU DATA BUS
16
MCELLAB
16 OUTPUT
MACROCELL
(1)
8
TO PORT A OR B
MACROCELL
ALLOC.
PT
ALLOC.
73
MCELLBC
TO PORT B OR C
8
2
20 INPUT MACROCELL
(PORT A,B,C)
EXTERNAL CHIP SELECTS
TO PORT D
DIRECT MACROCELL INPUT TO MCU DATA BUS
INPUT MACROCELL & INPUT PORTS
PORT D INPUTS
20
2
AI06600
Note: 1. Ports A is not available in the 52-pin package
78/123
µPSD33XX
Decode PLD (DPLD)
The DPLD, shown in Figure 35, is used for decod-
ing the address for PSD Module and external com-
ponents. The DPLD can be used to generate the
following decode signals:
■ Up to 8 Sector Select (FS0-FS7) signals for the
primary Flash memory (three product terms
each).
■ Up to 4 Sector Select (CSBOOT0-CSBOOT3)
signals for the secondary Flash memory (three
product terms each)
■ 1 internal SRAM Select (RS0) signal (two
product terms)
■ 1 internal CSIOP Select signal (selects the PSD
Module registers)
■ 2 internal Peripheral Select signals (Peripheral
I/O Mode).
Figure 35. DPLD Logic Array
CSBOOT 0
CSBOOT 1
CSBOOT 2
CSBOOT 3
3
3
3
3
(INPUTS)
1
3
3
3
3
3
3
3
3
FS0
I/O PORTS (PORT A,B,C)
(20)
FS1
FS2
(8)
MCELLAB.FB [7:0] (FEEDBACKS)
MCELLBC.FB [7:0] (FEEDBACKS)
(8)
(8)
8 PRIMARY FLASH
MEMORY SECTOR
SELECTS
FS3
FS4
FS5
PGR0 -PGR7
2
(16)
(2)
[
]
A 15:0
[
]
PD 2:1
PDN (APD OUTPUT)
FS6
FS7
(1)
(4)
(1)
(1)
2
PSEN, RD, WR, ALE
2
RESET
RS0
2
1
SRAM SELECT
RD_BSY
CSIOP
PSEL0
PSEL1
I/O DECODER
SELECT
1
1
PERIPHERAL I/O
MODE SELECT
AI06601
Note: 1. Port A inputs are not available in the 52-pin package
2. Inputs from the MCU module
79/123
µPSD33XX
Complex PLD (CPLD)
The CPLD can be used to implement system logic
functions, such as loadable counters and shift reg-
isters, system mailboxes, handshaking protocols,
state machines, and random logic. The CPLD can
also be used to generate External Chip Select
(ECS1-ECS2), routed to Port D.
As shown in Figure 34, the CPLD has the following
blocks:
■ 20 Input Macrocells (IMC)
■ 16 Output Macrocells (OMC)
■ Macrocell Allocator
Each of the blocks are described in the sections
that follow.
The Input Macrocells (IMC) and Output Macrocells
(OMC) are connected to the PSD Module internal
data bus and can be directly accessed by the
MCU. This enables the MCU software to load data
into the Output Macrocells (OMC) or read data
from both the Input and Output Macrocells (IMC
and OMC).
This feature allows efficient implementation of sys-
tem logic and eliminates the need to connect the
data bus to the AND Array as required in most
standard PLD macrocell architectures.
■ Product Term Allocator
■ AND Array capable of generating up to 137
product terms
■ Four I/O Ports.
Figure 36. Macrocell and I/O Port
PRODUCT TERMS
FROM OTHER
MACROCELLS
MCU ADDRESS / DATA BUS
TO OTHER I/O PORTS
CPLD MACROCELLS
I/O PORTS
DATA
LOAD
LATCHED
ADDRESS OUT
PT PRESET
CONTROL
MCU DATA IN
MCU LOAD
PRODUCT TERM
ALLOCATOR
I/O PIN
DATA
D
Q
MUX
WR
UP TO 10
PRODUCT TERMS
MACROCELL
OUT TO
MCU
CPLD OUTPUT
POLARITY
SELECT
PR DI LD
D/T
SELECT
Q
PT
CPLD
OUTPUT
PDR
CLOCK
INPUT
D/T/JK FF
SELECT
COMB.
/REG
SELECT
GLOBAL
CLOCK
MACROCELL
CK
TO
I/O PORT
ALLOC.
CL
CLOCK
SELECT
Q
DIR
REG.
D
WR
PT CLEAR
(
)
PT OUTPUT ENABLE OE
MACROCELL FEEDBACK
I/O PORT INPUT
INPUT MACROCELLS
Q
Q
D
PT INPUT LATCH GATE/CLOCK
D
G
ALE
AI06602
80/123
µPSD33XX
Output Macrocell (OMC)
Eight of the Output Macrocells (OMC) are con-
nected to Ports A and B pins and are named as
McellAB0-McellAB7. The other eight macrocells
are connected to Ports B and C pins and are
named as McellBC0-McellBC7. If an McellAB out-
put is not assigned to a specific pin in PSDsoft, the
Macrocell Allocator block assigns it to either Port A
or B. The same is true for a McellBC output on Port
B or C. Table 85 shows the macrocells and port
assignment.
The Output Macrocell (OMC) architecture is
shown in Figure 37.
The flip-flop in the Output Macrocell (OMC) block
can be configured as a D, T, JK, or SR type in PS-
Dsoft. The flip-flop’s clock, preset, and clear inputs
may be driven from a product term of the AND Ar-
ray. Alternatively, CLKIN (PD1) can be used for
the clock input to the flip-flop. The flip-flop is
clocked on the rising edge of CLKIN (PD1). The
preset and clear are active High inputs. Each clear
input can use up to two product terms.
Table 85. Output Macrocell Port and Data Bit Assignments
Port
Output
Macrocell
Maximum Borrowed
Product Terms
Data Bit for Loading or
Reading
Native Product Terms
(1,2)
Assignment
McellAB0
McellAB1
McellAB2
McellAB3
McellAB4
McellAB5
McellAB6
McellAB7
McellBC0
McellBC1
McellBC2
McellBC3
McellBC4
McellBC5
McellBC6
McellBC7
Port A0, B0
Port A1, B1
Port A2, B2
Port A3, B3
Port A4, B4
Port A5, B5
Port A6, B6
Port A7, B7
Port B0
3
3
3
3
3
3
3
3
4
4
4
4
4
4
4
4
6
6
6
6
6
6
6
6
5
5
5
5
6
6
6
6
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
Port B1
Port B2, C2
Port B3, C3
Port B4, C4
Port B5
Port B6
Port B7, C7
Note: 1. McellAB0-McellAB7 can only be assigned to Port B in the 52-pin package.
2. Port PC0, PC1, PC5, and PC6 are assigned to JTAG pins and are not available as Macrocell outputs.
81/123
µPSD33XX
Product Term Allocator
The CPLD has a Product Term Allocator. PSDsoft
uses the Product Term Allocator to borrow and
place product terms from one macrocell to anoth-
er. The following list summarizes how product
terms are allocated:
space, as defined by the CSIOP block (see “I/O
PORTS (PSD MODULE), page 84). The flip-flops
in each of the 16 Output Macrocells (OMC) can be
loaded from the data bus by a MCU. Loading the
Output Macrocells (OMC) with data from the MCU
takes priority over internal functions. As such, the
preset, clear, and clock inputs to the flip-flop can
be overridden by the MCU. The ability to load the
flip-flops and read them back is useful in such ap-
plications as loadable counters and shift registers,
mailboxes, and handshaking protocols.
■ McellAB0-McellAB7 all have three native
product terms and may borrow up to six more
■ McellBC0-McellBC3 all have four native product
terms and may borrow up to five more
■ McellBC4-McellBC7 all have four native product
Data can be loaded to the Output Macrocells
(OMC) on the trailing edge of WRITE Strobe (WR,
edge loading) or during the time that WRITE
Strobe (WR) is active (level loading). The method
of loading is specified in PSDsoft Express Config-
uration.
terms and may borrow up to six more.
Each macrocell may only borrow product terms
from certain other macrocells.
Loading and Reading the Output Macrocells
(OMC). The Output Macrocells (OMC) block oc-
cupies a memory location in the MCU address
Figure 37. CPLD Output Macrocell
MASK
REG.
MACROCELL CS
RD
MCU DATA BUS
[
]
D 7:0
WR
PT
ALLOCATOR
DIRECTION
REGISTER
(
)
ENABLE .OE
(
)
PRESET .PR
COMB/REG
SELECT
PT
PT
DIN PR
LD
MUX
I/O PIN
MACROCELL
ALLOCATOR
Q
PT
POLARITY
SELECT
IN
CLR
PROGRAMMABLE
PORT
DRIVER
(
)
CLEAR .RE
(
)
FF D/T/JK/SR
PT CLK
CLKIN
MUX
(
)
FEEDBACK .FB
PORT INPUT
INPUT
MACROCELL
AI06617
82/123
µPSD33XX
The OMC Mask Register. There is one Mask
Register for each of the two groups of eight Output
Macrocells (OMC). The Mask Registers can be
used to block the loading of data to individual Out-
put Macrocells (OMC). The default value for the
Mask Registers is 00h, which allows loading of the
Output Macrocells (OMC). When a given bit in a
Mask Register is set to a '1,' the MCU is blocked
from writing to the associated Output Macrocells
(OMC). For example, suppose McellAB0-
McellAB3 are being used for a state machine. You
would not want a MCU write to McellAB to over-
write the state machine registers. Therefore, you
would want to load the Mask Register for McellAB
(Mask Macrocell AB) with the value 0Fh.
If the Output Macrocell (OMC) output is declared
as an internal node and not as a port pin output in
the PSDabel file, the port pin can be used for other
I/O functions. The internal node feedback can be
routed as an input to the AND Array.
Input Macrocells (IMC)
The CPLD has 20 Input Macrocells (IMC), one for
each pin on Ports A and B, and 4 on Port C. The
architecture of the Input Macrocells (IMC) is
shown in Figure 38. The Input Macrocells (IMC)
are individually configurable, and can be used as
a latch, register, or to pass incoming Port signals
prior to driving them onto the PLD input bus. The
outputs of the Input Macrocells (IMC) can be read
by the MCU through the internal data bus.
The enable for the latch and clock for the register
are driven by a multiplexer whose inputs are a
product term from the CPLD AND Array or the
MCU Address Strobe (ALE). Each product term
output is used to latch or clock four Input Macro-
cells (IMC). Port inputs 3-0 can be controlled by
one product term and 7-4 by another.
The Output Enable of the OMC. The
Output
Macrocells (OMC) block can be connected to an I/
O port pin as a PLD output. The output enable of
each port pin driver is controlled by a single prod-
uct term from the AND Array, ORed with the Direc-
tion Register output. The pin is enabled upon
Power-up if no output enable equation is defined
and if the pin is declared as a PLD output in PSD-
soft Express.
Figure 38. Input Macrocell
[
]
MCU DATA BUS
D 7:0
_
INPUT MACROCELL RD
DIRECTION
REGISTER
(
)
ENABLE .OE
OUTPUT
MACROCELLS BC
PT
AND
MACROCELL AB
I/O PIN
PT
PORT
DRIVER
MUX
Q
D
PT
ALE
MUX
D FF
Q
D
G
FEEDBACK
LATCH
INPUT MACROCELL
AI06603
83/123
µPSD33XX
I/O PORTS (PSD MODULE)
There are four programmable I/O ports: Ports A, B,
C, and D in the PSD Module. Each of the ports is
eight bits except Port D. Each port pin is individu-
ally user configurable, thus allowing multiple func-
tions per port. The ports are configured using
PSDsoft Express Configuration or by the MCU
writing to on-chip registers in the CSIOP space.
Port A is not available in the 52-pin package.
and B only) and PSDsoft Express Configuration.
Inputs to the multiplexer include the following:
■ Output data from the Data Out register
■ Latched address outputs
■ CPLD macrocell output
■ External Chip Select (ECS1-ECS2) from the
CPLD.
General Port Architecture
The Port Data Buffer (PDB) is a tri-state buffer that
allows only one source at a time to be read. The
Port Data Buffer (PDB) is connected to the Internal
Data Bus for feedback and can be read by the
MCU. The Data Out and macrocell outputs, Direc-
tion and Control Registers, and port pin input are
all connected to the Port Data Buffer (PDB).
The general architecture of the I/O Port block is
shown in Figure 39. In general, once the purpose
for a port pin has been defined, that pin is no long-
er available for other purposes. Exceptions are
noted.
As shown in Figure 39, the ports contain an output
multiplexer whose select signals are driven by the
configuration bits in the Control Registers (Ports A
Figure 39. General I/O Port Architecture
DATA OUT
REG.
DATA OUT
D
Q
WR
ADDRESS
ALE
ADDRESS
PORT PIN
D
G
Q
OUTPUT
MUX
MACROCELL OUTPUTS
EXT CS
READ MUX
P
D
B
OUTPUT
SELECT
DATA IN
CONTROL REG.(1)
ENABLE OUT
D
Q
WR
WR
DIR REG.
D
Q
ENABLE PRODUCT TERM (.OE)
CPLD-INPUT
INPUT
MACROCELL
AI07873
Note: 1. Control Register is not available in Ports C and D.
84/123
µPSD33XX
The Port pin’s tri-state output driver enable is con-
trolled by a two input OR gate whose inputs come
from the CPLD AND Array enable product term
and the Direction Register. If the enable product
term of any of the Array outputs are not defined
and that port pin is not defined as a CPLD output
in the PSDsoft, then the Direction Register has
sole control of the buffer that drives the port pin.
is configured as an output, the content of the Data
Out Register drives the pin. When configured as
an input, the MCU can read the port input through
the Data In buffer. See Figure 39, page 84.
Ports C and D do not have Control Registers, and
are in MCU I/O Mode by default. They can be used
for PLD I/O if equations are written for them in PS-
Dabel.
The contents of these registers can be altered by
the MCU. The Port Data Buffer (PDB) feedback
path allows the MCU to check the contents of the
registers.
Ports A, B, and C have embedded Input Macro-
cells (IMC). The Input Macrocells (IMC) can be
configured as latches, registers, or direct inputs to
the PLDs. The latches and registers are clocked
by Address Strobe (ALE) or a product term from
the PLD AND Array. The outputs from the Input
Macrocells (IMC) drive the PLD input bus and can
be read by the MCU. See Input Macrocell, page
83.
PLD I/O Mode
The PLD I/O Mode uses a port as an input to the
CPLD’s Input Macrocells (IMC), and/or as an out-
put from the CPLD’s Output Macrocells (OMC).
The output can be tri-stated with a control signal.
This output enable control signal can be defined
by a product term from the PLD, or by resetting the
corresponding bit in the Direction Register to '0.'
The corresponding bit in the Direction Register
must not be set to '1' if the pin is defined for a PLD
input signal in PSDsoft. The PLD I/O Mode is
specified in PSDsoft by declaring the port pins,
and then writing an equation assigning the PLD I/
O to a port.
Port Operating Modes
The I/O Ports have several modes of operation.
Some modes can be defined using PSDsoft, some
by the MCU writing to the Control Registers in
CSIOP space, and some by both. The modes that
can only be defined using PSDsoft must be pro-
grammed into the device and cannot be changed
unless the device is reprogrammed. The modes
that can be changed by the MCU can be done so
dynamically at run-time. The PLD I/O, Data Port,
Address Input, and Peripheral I/O Modes are the
only modes that must be defined before program-
ming the device. All other modes can be changed
by the MCU at run-time. See Application Note
AN1171 for more detail.
Address Out Mode
Address Out Mode can be used to drive latched
MCU addresses on to the port pins. These port
pins can, in turn, drive external devices. Either the
output enable or the corresponding bits of both the
Direction Register and Control Register must be
set to a '1' for pins to use Address Out Mode. This
must be done by the MCU at run-time. See Table
88 for the address output pin assignments on
Ports A and B for various MCUs.
Peripheral I/O Mode
Peripheral I/O Mode can be used to interface with
external peripherals. In this mode, all of Port A
serves as a tri-state, bi-directional data buffer for
the MCU. Peripheral I/O Mode is enabled by set-
ting Bit 7 of the VM Register to a '1.' Figure 40
shows how Port A acts as a bi-directional buffer for
the MCU data bus if Peripheral I/O Mode is en-
abled. An equation for PSEL0 and/or PSEL1 must
be written in PSDsoft. The buffer is tri-stated when
PSEL0 or PSEL1 is low (not active). The PSEN
signal should be “ANDed” in the PSEL equations
to disable the buffer when PSEL resides in the
data space.
Table 86 summarizes which modes are available
on each port. Table 89 shows how and where the
different modes are configured. Each of the port
operating modes are described in the following
sections.
MCU I/O Mode
In the MCU I/O Mode, the MCU uses the I/O Ports
block to expand its own I/O ports. By setting up the
CSIOP space, the ports on the PSD Module are
mapped into the MCU address space. The ad-
dresses of the ports are listed in Table 77, page
67.
A port pin can be put into MCU I/O Mode by writing
a '0' to the corresponding bit in the Control Regis-
ter. The MCU I/O direction may be changed by
writing to the corresponding bit in the Direction
Register, or by the output enable product term
(see Peripheral I/O Mode, page 85). When the pin
JTAG In-System Programming (ISP)
Port C is JTAG compliant, and can be used for In-
System Programming (ISP). For more information
on the JTAG Port, see PROGRAMMING IN-CIR-
CUIT USING THE JTAG SERIAL INTERFACE,
page 95.
85/123
µPSD33XX
Figure 40. Peripheral I/O Mode
RD
PSEL0
PSEL
PSEL1
D0-D7
VM REGISTER BIT 7
PA0-PA7
DATA BUS
WR
AI02886
Table 86. Port Operating Modes
(1)
Port Mode
MCU I/O
Port B
Port C
Port D
Port A
Yes
Yes
Yes
No
Yes
PLD I/O
McellAB Outputs
McellBC Outputs
Additional Ext. CS Outputs No
PLD Inputs
Address Out
Peripheral I/O
JTAG ISP
Yes
No
Yes
Yes
No
No
No
Yes
Yes
(2)
Yes
No
Yes
Yes
Yes
Yes (A7 – 0)
Yes (A7 – 0)
No
No
No
No
No
Yes
No
No
No
(3)
Yes
Note: 1. Port A is not available in the 52-pin package.
2. On pins PC2, PC3, PC4, and PC7 only.
3. JTAG pins (TMS, TCK, TDI, TDO) are dedicated pins.
Table 87. Port Operating Mode Settings
Control Register
Direction Register
(1)
Mode
Defined in PSDsoft
VM Register Setting
(1)
(1)
Setting
Setting
1 = output,
0 = input (Note 2)
MCU I/O
Declare pins only
Logic equations
Declare pins only
0
N/A
N/A
N/A
PLD I/O
N/A
1
(Note 2)
Address Out
(Port A,B)
1 (Note 2)
Peripheral I/O
(Port A)
Logic equations
(PSEL0 & 1)
N/A
N/A
PIO Bit = 1
Note: 1. N/A = Not Applicable
2. The direction of the Port A,B,C, and D pins are controlled by the Direction Register ORed with the individual output enable product
term (.oe) from the CPLD AND Array.
Table 88. I/O Port Latched Address Output Assignments
Port A (PA3-PA0)
Address a3-a0
Port A (PA7-PA4)
Address a7-a4
Port B (PB3-PB0)
Address a3-a0
Port B (PB7-PB4)
Address a7-a4
86/123
µPSD33XX
Port Configuration Registers (PCR)
Each Port has a set of Port Configuration Regis-
ters (PCR) used for configuration. The contents of
the registers can be accessed by the MCU through
normal READ/WRITE bus cycles at the addresses
given in Table 77, page 67. The addresses in Ta-
ble 79, page 69 are the offsets in hexadecimal
from the base of the CSIOP register.
The pins of a port are individually configurable and
each bit in the register controls its respective pin.
For example, Bit 0 in a register refers to Bit 0 of its
port. The three Port Configuration Registers
(PCR), shown in Table 89, are used for setting the
Port configurations. The default Power-up state for
each register in Table 89 is 00h.
Note: The slew rate is a measurement of the rise
and fall times of an output. A higher slew rate
means a faster output response and may create
more electrical noise. A pin operates in a high slew
rate when the corresponding bit in the Drive Reg-
ister is set to '1.' The default rate is slow slew.
Table 93, page 88 shows the Drive Register for
Ports A, B, C, and D. It summarizes which pins can
be configured as Open Drain outputs and which
pins the slew rate can be set for.
Table 89. Port Configuration Registers (PCR)
Register Name
Control
Port
MCU Access
WRITE/READ
WRITE/READ
WRITE/READ
Control Register. Any bit reset to '0' in the Con-
trol Register sets the corresponding port pin to
MCU I/O Mode, and a '1' sets it to Address Out
Mode. The default mode is MCU I/O. Only Ports A
and B have an associated Control Register.
A,B
Direction
A,B,C,D
A,B,C,D
(1)
Drive Select
Note: 1. See Table 93 for Drive Register Bit definition.
Direction Register. The Direction Register, in
conjunction with the output enable (except for Port
D), controls the direction of data flow in the I/O
Ports. Any bit set to '1' in the Direction Register
causes the corresponding pin to be an output, and
any bit set to '0' causes it to be an input. The de-
fault mode for all port pins is input.
Figure 39, page 84 shows the Port Architecture di-
agrams for Ports A/B and C, respectively. The di-
rection of data flow for Ports A, B, and C are
controlled not only by the direction register, but
also by the output enable product term from the
PLD AND Array. If the output enable product term
is not active, the Direction Register has sole con-
trol of a given pin’s direction.
Table 90. Port Pin Direction Control, Output
Enable P.T. Not Defined
Direction Register Bit
Port Pin Mode
0
1
Input
Output
Table 91. Port Pin Direction Control, Output
Enable P.T. Defined
Direction
Register Bit
Output Enable
P.T.
Port Pin Mode
0
0
1
1
0
Input
An example of a configuration for a Port with the
three least significant bits set to output and the re-
mainder set to input is shown in Table 92. Since
Port D only contains two pins, the Direction Regis-
ter for Port D has only two bits active.
Drive Select Register. The Drive Select Register
configures the pin driver as Open Drain or CMOS
for some port pins, and controls the slew rate for
the other port pins. An external pull-up resistor
should be used for pins configured as Open Drain.
1
0
1
Output
Output
Output
Table 92. Port Direction Assignment Example
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
0
0
0
0
0
1
1
1
A pin can be configured as Open Drain if its corre-
sponding bit in the Drive Select Register is set to a
'1.' The default pin drive is CMOS.
87/123
µPSD33XX
Port Data Registers
The Port Data Registers, shown in Table 94, are
used by the MCU to write data to or read data from
the ports. Table 94 shows the register name, the
ports having each register type, and MCU access
for each register type. The registers are described
below.
Data In. Port pins are connected directly to the
Data In buffer. In MCU I/O Input Mode, the pin in-
put is read through the Data In buffer.
Register Bits are not set, writing to the macrocell
loads data to the macrocell flip-flops. See PLDs,
page 78.
OMC Mask Register. Each OMC Mask Register
Bit corresponds to an Output Macrocell (OMC) flip-
flop. When the OMC Mask Register Bit is set to a
'1,' loading data into the Output Macrocell (OMC)
flip-flop is blocked. The default value is '0' or un-
blocked.
Data Out Register. Stores output data written by
the MCU in the MCU I/O Output Mode. The con-
tents of the Register are driven out to the pins if the
Direction Register or the output enable product
term is set to '1.' The contents of the register can
also be read back by the MCU.
Output Macrocells (OMC). The CPLD Output
Macrocells (OMC) occupy a location in the MCU’s
address space. The MCU can read the output of
the Output Macrocells (OMC). If the OMC Mask
Input Macrocells (IMC). The Input Macrocells
(IMC) can be used to latch or store external inputs.
The outputs of the Input Macrocells (IMC) are rout-
ed to the PLD input bus, and can be read by the
MCU. See PLDs, page 78.
Enable Out. The Enable Out register can be read
by the MCU. It contains the output enable values
for a given port. A '1' indicates the driver is in out-
put mode. A '0' indicates the driver is in tri-state
and the pin is in input mode.
Table 93. Drive Register Pin Assignment
Drive
Bit 7
Bit 6
Bit 5
Bit 4
Open
Bit 3
Slew
Bit 2
Slew
Bit 1
Slew
Bit 0
Slew
Register
Open
Drain
Open
Drain
Open
Drain
Port A
Drain
Rate
Rate
Rate
Rate
Open
Drain
Open
Drain
Open
Drain
Open
Drain
Slew
Rate
Slew
Rate
Slew
Rate
Slew
Rate
Port B
Port C
Port D
Open
Drain
Open
Drain
Open
Drain
Open
Drain
Open
Drain
Open
Drain
Open
Drain
Open
Drain
Slew
Rate
Slew
Rate
(1)
(1)
(1)
(1)
(1)
(1)
NA
NA
NA
NA
NA
NA
Note: 1. NA = Not Applicable.
Table 94. Port Data Registers
Register Name
Data In
Port
MCU Access
A,B,C,D
READ – input on pin
WRITE/READ
Data Out
A,B,C,D
A,B,C
READ – outputs of macrocells
WRITE – loading macrocells flip-flop
Output Macrocell
Mask Macrocell
WRITE/READ – prevents loading into a given
macrocell
A,B,C
Input Macrocell
Enable Out
A,B,C
A,B,C
READ – outputs of the Input Macrocells
READ – the output enable control of the port driver
88/123
µPSD33XX
Ports A and B – Functionality and Structure
Ports A and B have similar functionality and struc-
ture, as shown in Figure 39, page 84. The two
ports can be configured to perform one or more of
the following functions:
■ Open Drain – Port C pins can be configured in
Open Drain Mode
■ Battery Backup features – PC2 can be
configured for a battery input supply, Voltage
■ MCU I/O Mode
Stand-by (V
).
STBY
■ CPLD Output – Macrocells McellAB7-McellAB0
can be connected to Port A or Port B. McellBC7-
McellBC0 can be connected to Port B or Port C.
PC4 can be configured as a Battery-on Indicator
(V ), indicating when V is less than
BATON
CC
V
.
BAT
■ CPLD Input – Via the Input Macrocells (IMC).
Port D – Functionality and Structure
■ Latched Address output – Provide latched
Port D has two I/O pins (only one pin, PD1, in the
52-pin package). This port does not support Ad-
dress Out Mode, and therefore no Control Regis-
ter is required. Of the eight bits in the Port D
registers, only Bits 2 and 1 are used to configure
pins PD2 and PD1.
address output as per Table 88.
■ Open Drain/Slew Rate – pins PA3-PA0 and
PB3-PB0 can be configured to fast slew rate,
pins PA7-PA4 and PB7-PB4 can be configured
to Open Drain Mode.
Port D can be configured to perform one or more
of the following functions:
■ Peripheral Mode – Port A only (80-pin package)
■ MCU I/O Mode;
Port C – Functionality and Structure
■ CPLD Output – External Chip Select (ECS1-
ECS2), each ECS consists of one product term
that can be configured active high or low;
Port C can be configured to perform one or more
of the following functions (see Figure 39, page 84):
■ MCU I/O Mode
■ CPLD Input – direct input to the CPLD, no Input
■ CPLD Output – McellBC[2, 3. 4, 7] outputs can
Macrocells (IMC); and
be connected to Port C.
■ Slew rate – pins can be set up for fast slew rate
■ CPLD Input – via the Input Macrocells (IMC) on
pins PC2, PC3, PC4, and PC7.
Port D pins can be configured in PSDsoft Express
as input pins for other dedicated functions:
■ CLKIN (PD1) as input to the macrocells flip-
■ In-System Programming (ISP) – Port pins PC0,
PC1, PC5, and PC6 are dedicated for JTAG ISP
programming (TMS, TCK, TDI, TDO, see
PROGRAMMING IN-CIRCUIT USING THE
JTAG SERIAL INTERFACE, page 95, for more
information on JTAG programming.)
flops and APD counter, and
■ PSD Chip Select Input (CSI, PD2). Driving this
signal High disables the Flash memory, SRAM
and CSIOP.
89/123
µPSD33XX
POWER MANAGEMENT
All PSD Module offers configurable power saving
options. These options may be used individually or
in combinations, as follows:
■ The primary and secondary Flash memory, and
SRAM blocks are built with power management
technology. In addition to using special silicon
design methodology, power management
technology puts the memories into Standby
Mode when address/data inputs are not
Once in Power-down Mode, all address/data
signals are blocked from reaching memory and
PLDs, and the memories are deselected
internally. This allows the memory and PLDs to
remain in Standby Mode even if the address/
data signals are changing state externally
(noise, other devices on the MCU bus, etc.).
Keep in mind that any unblocked PLD input
signals that are changing states keeps the PLD
out of Stand-by Mode, but not the memories.
changing (zero DC current). As soon as a
transition occurs on an input, the affected
memory “wakes up,” changes and latches its
outputs, then goes back to standby. The
designer does not have to do anything special to
achieve Memory Standby Mode when no inputs
are changing—it happens automatically.
The PLD sections can also achieve Standby
Mode when its inputs are not changing, as
described in the sections on the Power
Management Mode Registers (PMMR).
■ PSD Chip Select Input (CSI, PD2) can be used
to disable the internal memories, placing them
in Standby Mode even if inputs are changing.
This feature does not block any internal signals
or disable the PLDs. This is a good alternative
to using the APD Unit. There is a slight penalty
in memory access time when PSD Chip Select
Input (CSI, PD2) makes its initial transition from
deselected to selected.
■ The PMMRs can be written by the MCU at run-
time to manage power. The PSD Module
supports “blocking bits” in these registers that
are set to block designated signals from
reaching both PLDs. Current consumption of
the PLDs is directly related to the composite
frequency of the changes on their inputs (see
Figure 44 and Figure 45). Significant power
savings can be achieved by blocking signals
that are not used in DPLD or CPLD logic
equations.
■ As with the Power Management Mode, the
Automatic Power Down (APD) block allows the
PSD Module to reduce to stand-by current
automatically. The APD Unit can also block
MCU address/data signals from reaching the
memories and PLDs.
Built in logic monitors the Address Strobe of the
MCU for activity. If there is no activity for a
certain time period (MCU is asleep), the APD
Unit initiates Power-down Mode (if enabled).
Figure 41. APD Unit
APD EN
PMMR0 BIT 1=1
TRANSITION
DETECTION
DISABLE BUS
INTERFACE
ALE
PD
CLR
APD
CSIOP SELECT
FLASH SELECT
COUNTER
RESET
EDGE
DETECT
PD
CSI
PLD
SRAM SELECT
POWER DOWN
CLKIN
(
)
PDN SELECT
DISABLE
FLASH/SRAM
AI06608
90/123
µPSD33XX
The PSD Module has a Turbo Bit in PMMR0.This
bit can be set to turn the Turbo Mode off (the de-
fault is with Turbo Mode turned on). While Turbo
Mode is off, the PLDs can achieve standby current
when no PLD inputs are changing (zero DC cur-
rent). Even when inputs do change, significant
power can be saved at lower frequencies (AC cur-
rent), compared to when Turbo Mode is on. When
the Turbo Mode is on, there is a significant DC cur-
rent component and the AC component is higher.
■ Typical standby current is of the order of
microamperes. These standby current values
assume that there are no transitions on any PLD
input.
Other Power Saving Options. The PSD Module
offers other reduced power saving options that are
independent of the Power-down Mode. Except for
the SRAM Stand-by and PSD Chip Select Input
(CSI, PD2) features, they are enabled by setting
bits in PMMR0 and PMMR2.
Automatic Power-down (APD) Unit and Power-
down Mode. The APD Unit, shown in Figure 41,
puts the PSD Module into Power-down Mode by
monitoring the activity of Address Strobe (ALE). If
the APD Unit is enabled, as soon as activity on Ad-
dress Strobe (ALE) stops, a four-bit counter starts
counting. If Address Strobe (ALE/AS, PD0) re-
mains inactive for fifteen clock periods of CLKIN
(PD1), Power-down (PDN) goes High, and the
PSD Module enters Power-down Mode, as dis-
cussed next.
Figure 42. Enable Power-down Flow Chart
RESET
Enable APD
Set PMMR0 Bit 1 = 1
Power-down Mode. By default, if you enable the
APD Unit, Power-down Mode is automatically en-
abled. The device enters Power-down Mode if Ad-
dress Strobe (ALE) remains inactive for fifteen
periods of CLKIN (PD1).
The following should be kept in mind when the
PSD Module is in Power-down Mode:
OPTIONAL
Disable desired inputs to PLD
by setting PMMR0 bits 4 and 5
and PMMR2 bits 2 through 6.
■ If Address Strobe (ALE) starts pulsing again, the
PSD Module returns to normal Operating mode.
The PSD Module also returns to normal
Operating mode if either PSD Chip Select Input
(CSI, PD2) is Low or the RESET input is High.
■ The MCU address/data bus is blocked from all
ALE idle
No
for 15 CLKIN
clocks?
memory and PLDs.
Yes
■ Various signals can be blocked (prior to Power-
down Mode) from entering the PLDs by setting
the appropriate bits in the PMMR registers. The
blocked signals include MCU control signals
and the common CLKIN (PD1).
PSD Module in Power
Down Mode
AI06609
Note: Blocking CLKIN (PD1) from the PLDs
does not block CLKIN (PD1) from the APD Unit.
Table 95. Power-down Mode’s Effect on Ports
Port Function
MCU I/O
Pin Level
No Change
■ All memories enter Standby Mode and are
drawing standby current. However, the PLD and
I/O ports blocks do not go into Standby Mode
because you don’t want to have to wait for the
logic and I/O to “wake-up” before their outputs
can change. See Table 95 for Power-down
Mode effects on PSD Module ports.
PLD Out
No Change
Undefined
Tri-State
Address Out
Peripheral I/O
91/123
µPSD33XX
PLD Power Management
PSD Chip Select Input (CSI, PD2)
The power and speed of the PLDs are controlled
by the Turbo Bit (Bit 3) in PMMR0. By setting the
bit to '1,' the Turbo Mode is off and the PLDs con-
sume the specified stand-by current when the in-
puts are not switching for an extended time of
70ns. The propagation delay time is increased by
10ns (for a 5V device) after the Turbo Bit is set to
'1' (turned off) when the inputs change at a com-
posite frequency of less than 15MHz. When the
Turbo Bit is reset to '0' (turned on), the PLDs run
at full power and speed. The Turbo Bit affects the
PLD’s DC power, AC power, and propagation de-
lay. When the Turbo Mode is off, the µPSD3200
input clock frequency is reduced by 5MHz from the
maximum rated clock frequency.
Blocking MCU control signals with the bits of
PMMR2 can further reduce PLD AC power con-
sumption.
SRAM Standby Mode (Battery Backup). The
SRAM in the PSD Module supports a battery back-
up mode in which the contents are retained in the
event of a power loss. The SRAM has Voltage
PD2 of Port D can be configured in PSDsoft Ex-
press as PSD Chip Select Input (CSI). When Low,
the signal selects and enables the PSD Module
Flash memory, SRAM, and I/O blocks for READ or
WRITE operations. A High on PSD Chip Select In-
put (CSI, PD2) disables the Flash memory, and
SRAM, and reduces power consumption. Howev-
er, the PLD and I/O signals remain operational
when PSD Chip Select Input (CSI, PD2) is High.
Input Clock
CLKIN (PD1) can be turned off, to the PLD to save
AC power consumption. CLKIN (PD1) is an input
to the PLD AND Array and the Output Macrocells
(OMC).
During Power-down Mode, or, if CLKIN (PD1) is
not being used as part of the PLD logic equation,
the clock should be disabled to save AC power.
CLKIN (PD1) is disconnected from the PLD AND
Array or the Macrocells block by setting Bits 4 or 5
to a '1' in PMMR0.
Input Control Signals
The PSD Module provides the option to turn off the
MCU signals (WR, RD, PSEN, and Address
Strobe (ALE)) to the PLD to save AC power con-
sumption. These control signals are inputs to the
PLD AND Array. During Power-down Mode, or, if
any of them are not being used as part of the PLD
logic equation, these control signals should be dis-
abled to save AC power. They are disconnected
from the PLD AND Array by setting Bits 2, 3, 4, 5,
and 6 to a '1' in PMMR2.
Stand-by (V
an external battery. When V
, PC2) that can be connected to
STBY
becomes lower
CC
than V
then the SRAM automatically con-
STBY
nects to Voltage Stand-by (V
er source. The SRAM Standby Current (I
typically 0.5 µA. The SRAM data retention voltage
is 2V minimum. The Battery-on Indicator
, PC2) as a pow-
STBY
) is
STBY
(V
BATON
) can be routed to PC4. This signal indi-
cates when the V has dropped below V
.
CC
STBY
Table 96. Power Management Mode Registers PMMR0
Bit 0
Bit 1
Bit 2
X
0
Not used, and should be set to zero.
0 = off Automatic Power-down (APD) is disabled.
1 = on Automatic Power-down (APD) is enabled.
APD Enable
X
0
Not used, and should be set to zero.
0 = on PLD Turbo Mode is on
Bit 3
PLD Turbo
PLD Turbo Mode is off, saving power.
µPSD3200 operates at 5MHz below the maximum rated clock frequency
1 = off
0 = on
CLKIN (PD1) input to the PLD AND Array is connected. Every change of CLKIN
(PD1) Powers-up the PLD when Turbo Bit is '0.'
Bit 4
Bit 5
PLD Array clk
PLD MCell clk
1 = off CLKIN (PD1) input to PLD AND Array is disconnected, saving power.
0 = on CLKIN (PD1) input to the PLD macrocells is connected.
1 = off CLKIN (PD1) input to PLD macrocells is disconnected, saving power.
Bit 6
Bit 7
X
X
0
0
Not used, and should be set to zero.
Not used, and should be set to zero.
92/123
µPSD33XX
Table 97. Power Management Mode Registers PMMR2
Bit 0
Bit 1
X
X
0
0
Not used, and should be set to zero.
Not used, and should be set to zero.
0 = on WR input to the PLD AND Array is connected.
PLD Array
WR
Bit 2
Bit 3
Bit 4
Bit 5
1 = off WR input to PLD AND Array is disconnected, saving power.
0 = on RD input to the PLD AND Array is connected.
PLD Array
RD
1 = off RD input to PLD AND Array is disconnected, saving power.
0 = on PSEN input to the PLD AND Array is connected.
1 = off PSEN input to PLD AND Array is disconnected, saving power.
0 = on ALE input to the PLD AND Array is connected.
PLD Array
PSEN
PLD Array
ALE
1 = off ALE input to PLD AND Array is disconnected, saving power.
Bit 6
Bit 7
X
X
0
0
Not used, and should be set to zero.
Not used, and should be set to zero.
Note: The bits of this register are cleared to zero following Power-up. Subsequent RESET pulses do not clear the registers.
Table 98. APD Counter Operation
APD Enable Bit
ALE Level
X
APD Counter
0
1
1
Not Counting
Not Counting
Pulsing
0 or 1
Counting (Generates PDN after 15 Clocks)
93/123
µPSD33XX
RESET TIMING AND DEVICE STATUS AT RESET
Upon Power-up, the PSD Module requires a Reset
I/O Pin, Register and PLD Status at RESET
(RESET) pulse of duration t
after V
is
NLNH-PO
CC
Table 99 shows the I/O pin, register and PLD sta-
tus during Power-on RESET, Warm RESET, and
Power-down Mode. PLD outputs are always valid
during Warm RESET, and they are valid in Power-
on RESET once the internal Configuration bits are
loaded. This loading is completed typically long
steady. During this period, the device loads inter-
nal configurations, clears some of the registers
and sets the Flash memory into operating mode.
The Flash memory is reset to the READ Mode
upon Power-up. Sector Select (FS0-FS7 and
CSBOOT0-CSBOOT3) must all be Low. Any
Flash memory WRITE cycle initiation is prevented
before the V ramps up to operating level. Once
CC
the PLD is active, the state of the outputs are de-
termined by the PLD equations.
automatically when V is below V
.
DD
LKO
Warm RESET
Once the device is up and running, the PSD Mod-
ule can be reset with a pulse of a much shorter du-
Reset of Flash Memory Erase and Program
Cycles
A Reset (RESET) also resets the internal Flash
memory state machine. During a Flash memory
Program or Erase cycle, Reset (RESET) termi-
nates the cycle and returns the Flash memory to
ration, t
.
NLNH
the READ Mode within a period of t
.
NLNH-A
Figure 43. Reset (RESET) Timing
VCC(min)
V
CC
t
NLNH
t
t
NLNH-PO
NLNH-A
Power-On Reset
Warm Reset
RESET
AI07874
Table 99. Status During Power-on RESET, Warm RESET and Power-down Mode
Port Configuration
MCU I/O
Power-On RESET
Input mode
Warm RESET
Input mode
Power-down Mode
Unchanged
Valid after internal PSD
configuration bits are
loaded
Depends on inputs to PLD
(addresses are blocked in
PD Mode)
PLD Output
Valid
Address Out
Tri-stated
Tri-stated
Tri-stated
Tri-stated
Not defined
Tri-stated
Peripheral I/O
Register
Power-On RESET
Warm RESET
Power-down Mode
PMMR0 and PMMR2
Cleared to '0'
Unchanged
Unchanged
Cleared to '0' by internal
Power-on RESET
Depends on .re and .pr
equations
Depends on .re and .pr
equations
Macrocells flip-flop status
Initialized, based on the
selection in PSDsoft
Configuration menu
Initialized, based on the
selection in PSDsoft
Configuration menu
(1)
Unchanged
Unchanged
VM Register
All other registers
Cleared to '0'
Cleared to '0'
Note: 1. The SR_cod and PeriphMode Bits in the VM Register are always cleared to '0' on Power-on RESET or Warm RESET.
94/123
µPSD33XX
PROGRAMMING IN-CIRCUIT USING THE JTAG SERIAL INTERFACE
The JTAG Serial Interface pins (TMS, TCK, TDI,
TDO) are dedicated pins on Port C (see Table
100). All memory blocks (primary and secondary
Flash memory), PLD logic, and PSD Module Con-
figuration Register Bits may be programmed
through the JTAG Serial Interface block. A blank
device can be mounted on a printed circuit board
and programmed using JTAG.
The standard JTAG signals (IEEE 1149.1) are
TMS, TCK, TDI, and TDO. Two additional signals,
TSTAT and TERR, are optional JTAG extensions
used to speed up Program and Erase cycles.
TDI, and TDO). They are used to speed Program
and Erase cycles by indicating status on µPDS
signals instead of having to scan the status out se-
rially using the standard JTAG channel. See Appli-
cation Note AN1153.
TERR indicates if an error has occurred when
erasing a sector or programming a byte in Flash
memory. This signal goes Low (active) when an
Error condition occurs, and stays Low until an
“ISC_CLEAR” command is executed or a chip Re-
set (RESET) pulse is received after an
“ISC_DISABLE” command.
By default, on a blank device (as shipped from the
factory or after erasure), four pins on Port C are
the basic JTAG signals TMS, TCK, TDI, and TDO.
TSTAT behaves the same as Ready/Busy. TSTAT
is High when the PSD Module device is in READ
Mode (primary and secondary Flash memory con-
tents can be read). TSTAT is Low when Flash
memory Program or Erase cycles are in progress,
and also when data is being written to the second-
ary Flash memory.
TSTAT and TERR can be configured as open-
drain type signals during an “ISC_ENABLE” com-
mand.
Standard JTAG Signals
At power-up, the standard JTAG pins are inputs,
waiting for a JTAG serial command from an exter-
nal JTAG controller device (such as FlashLINK or
Automated Test Equipment). When the enabling
command is received, TDO becomes an output
and the JTAG channel is fully functional. The
same command that enables the JTAG channel
may optionally enable the two additional JTAG sig-
nals, TSTAT and TERR.
The RESET input to the µPS3200 should be active
during JTAG programming. The active RESET
puts the MCU module into RESET Mode while the
PSD Module is being programmed. See Applica-
tion Note AN1153 for more details on JTAG In-
System Programming (ISP).
Security and Flash Memory Protection
When the Security Bit is set, the device cannot be
read on a Device Programmer or through the
JTAG Port. When using the JTAG Port, only a Full
Chip Erase command is allowed.
All other Program, Erase, and Verify commands
are blocked. Full Chip Erase returns the part to a
non-secured, blank state. The Security Bit can be
set in PSDsoft Express Configuration.
The µPSD33XX Devices supports JTAG In-Sys-
tem-Configuration (ISC) commands, but not
Boundary Scan. The PSDsoft Express software
tool and FlashLINK JTAG programming cable im-
plement the JTAG In-System-Configuration (ISC)
commands.
All primary and secondary Flash memory sectors
can individually be sector protected against era-
sures. The sector protect bits can be set in PSD-
soft Express Configuration.
INITIAL DELIVERY STATE
When delivered from ST, the µPSD33XX Devices
have all bits in the memory and PLDs set to '1.'
The code, configuration, and PLD logic are loaded
using the programming procedure. Information for
programming the device is available directly from
ST. Please contact your local sales representa-
tive.
Table 100. JTAG Port Signals
Port C Pin
PC0
JTAG Signals
TMS
Description
Mode Select
PC1
PC3
PC4
PC5
PC6
TCK
Clock
TSTAT
TERR
TDI
Status (optional)
Error flag (optional)
Serial Data In
Serial Data Out
TDO
JTAG Extensions
TSTAT and TERR are two JTAG extension signals
enabled by an “ISC_ENABLE” command received
over the four standard JTAG signals (TMS, TCK,
95/123
µPSD33XX
AC/DC PARAMETERS
These tables describe the AD and DC parameters
of the µPSD33XX Devices:
■ DC Electrical Specification
■ AC Timing Specification
■ PLD Timing
– WRITE Timing
– Power-down and RESET Timing
The following are issues concerning the parame-
ters presented:
■ In the DC specification the supply current is
given for different modes of operation.
– Combinatorial Timing
– Synchronous Clock Mode
– Asynchronous Clock Mode
– Input Macrocell Timing
■ MCU Module Timing
– READ Timing
■ The AC power component gives the PLD, Flash
memory, and SRAM mA/MHz specification.
Figure 44 and Figure 45 show the PLD mA/MHz
as a function of the number of Product Terms
(PT) used.
■ In the PLD timing parameters, add the required
delay when Turbo Bit is '0.'
Figure 44. PLD I /Frequency Consumption (5V range)
CC
110
100
90
V
CC
= 5V
80
70
60
50
40
30
20
10
0
PT 100%
PT 25%
0
5
10
15
20
25
HIGHEST COMPOSITE FREQUENCY AT PLD INPUTS (MHz)
AI02894
Figure 45. PLD I /Frequency Consumption (3V range)
CC
60
V
CC
= 3V
50
40
30
20
10
0
PT 100%
PT 25%
0
5
10
15
20
25
HIGHEST COMPOSITE FREQUENCY AT PLD INPUTS (MHz)
AI03100
96/123
µPSD33XX
Table 101. PSD Module Example, Typ. Power Calculation at V = 5.0V (Turbo Mode Off)
CC
Conditions
MCU Clock Frequency
= 12MHz
Highest Composite PLD input frequency
(Freq PLD)
= 8MHz
= 2MHz
MCU ALE frequency (Freq ALE)
% Flash memory
Access
= 80%
= 15%
% SRAM access
% I/O access
= 5% (no additional power above base)
Operational Modes
% Normal
= 40%
= 60%
% Power-down Mode
Number of product terms used
(from fitter report)
= 45 PT
% of total product terms = 45/182 = 24.7%
Turbo Mode
= Off
Calculation (using typical values)
I
total
= I (MCUactive) x %MCUactive + I (PSDactive) x %PSDactive + I (pwrdown) x %pwrdown
CC CC PD
CC
I
I
I
(MCUactive)
= 20mA
= 250µA
CC
(pwrdown)
PD
CC
(PSDactive)
= I (ac) + I (dc)
CC CC
= %flash x 2.5 mA/MHz x Freq ALE
+ %SRAM x 1.5 mA/MHz x Freq ALE
+ % PLD x (from graph using Freq PLD)
= 0.8 x 2.5 mA/MHz x 2MHz + 0.15 x 1.5 mA/MHz x 2MHz + 24 mA
= (4 + 0.45 + 24) mA
= 28.45mA
I
total
= 20mA x 40% + 28.45mA x 40% + 250µA x 60%
= 8mA + 11.38mA + 150µA
= 19.53mA
CC
This is the operating power with no Flash memory Erase or Program cycles in progress. Calculation is based on all I/
O pins being disconnected and I = 0 mA.
OUT
97/123
µPSD33XX
MAXIMUM RATING
Stressing the device above the rating listed in the
Absolute Maximum Ratings” table may cause per-
manent damage to the device. These are stress
ratings only and operation of the device at these or
any other conditions above those indicated in the
Operating sections of this specification is not im-
plied. Exposure to Absolute Maximum Rating con-
ditions for extended periods may affect device
reliability. Refer also to the STMicroelectronics
SURE Program and other relevant quality docu-
ments.
Table 102. Absolute Maximum Ratings
Symbol
Parameter
Min.
Max.
125
235
6.5
Unit
°C
°C
V
T
Storage Temperature
–65
STG
(1)
TLEAD
VIO
Lead Temperature during Soldering (20 seconds max.)
Input and Output Voltage (Q = V or Hi-Z)
–0.5
–0.5
OH
V
CC
Supply Voltage
6.5
V
V
Device Programmer Supply Voltage
–0.5
14.0
2000
V
PP
(2)
VESD
–2000
V
Electrostatic Discharge Voltage (Human Body Model)
Note: 1. IPC/JEDEC J-STD-020A
2. JEDEC Std JESD22-A114A (C1=100pF, R1=1500 Ω, R2=500 Ω)
DC AND AC PARAMETERS
This section summarizes the operating and mea-
surement conditions, and the DC and AC charac-
teristics of the device. The parameters in the DC
and AC Characteristic tables that follow are de-
rived from tests performed under the Measure-
ment Conditions summarized in the relevant
tables. Designers should check that the operating
conditions in their circuit match the measurement
conditions when relying on the quoted parame-
ters.
Table 103. Operating Conditions (5V Devices)
Symbol
Parameter
Min.
4.5
–40
0
Max.
5.5
85
Unit
V
V
CC
Supply Voltage
Ambient Operating Temperature (industrial)
Ambient Operating Temperature (commercial)
°C
°C
T
A
70
Table 104. Operating Conditions (3.3V Devices)
Symbol
Parameter
Min.
3.0
–40
0
Max.
3.6
85
Unit
V
V
CC
Supply Voltage
Ambient Operating Temperature (industrial)
Ambient Operating Temperature (commercial)
°C
°C
T
A
70
98/123
µPSD33XX
Table 105. AC Symbols for Timing
Signal Letters
Signal Behavior
A
C
D
I
Address
t
Time
Clock
L
Logic Level Low or ALE
Logic Level High
Valid
Input Data
Instruction
ALE
H
V
X
Z
L
No Longer a Valid Logic Level
Float
N
P
Q
R
W
B
M
RESET Input or Output
PSEN signal
Output Data
RD signal
WR signal
PW Pulse Width
V
STBY
Output
Output Macrocell
Example: t
Invalid.
– Time from Address Valid to ALE
AVLX
Figure 46. Switching Waveforms – Key
INPUTS
OUTPUTS
WAVEFORMS
STEADY INPUT
STEADY OUTPUT
MAY CHANGE FROM
HI TO LO
WILL BE CHANGING
FROM HI TO LO
MAY CHANGE FROM
LO TO HI
WILL BE CHANGING
LO TO HI
DON'T CARE
CHANGING, STATE
UNKNOWN
OUTPUTS ONLY
CENTER LINE IS
TRI-STATE
AI03102
99/123
µPSD33XX
Table 106. Preliminary MCU Module DC Characteristics
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
(1)
V
3.0
3.6
V
CC
Supply Voltage
High Level Input Voltage
(Ports 0, 1, 2, 3, 4, XTAL1,
RESET)
V
3.0V < V < 3.6V
0.7V
CC
5.5
V
V
IH
CC
5V Tolerant - max voltage 5.5V
Low Level Input Voltage
(Ports 0, 1, 2, 3, 4, XTAL1,
RESET)
V
3.0V < V < 3.6V
V
SS
– 0.5
0.3V
CC
IL
CC
I
= 10mA
=5mA
0.6
0.6
V
V
V
V
V
V
V
V
OL
V
Output Low Voltage (Port 4)
OL1
I
OL
Output Low Voltage
(Other Ports)
V
OL2
OH1
OH2
I
= –10mA
= –5mA
2.4
OH
Output High Voltage
(Ports 4 push-pull)
V
V
I
2.4
OH
Output High Voltage
(Other Ports push-pull)
XTAL Open Bias Voltage
(XTAL1, XTAL2)
V
I
= 3.2mA
= V
1.0
2.0
V
OP
OL
RESET Pin Pull-up Current
(RESET)
I
V
–10
–55
µA
RST
IN
SS
XTAL Feedback Resistor Current
(XTAL1)
I
XTAL1 = V ; XTAL2 = V
CC SS
TBD (–20)
–10
TBD (–50) µA
FR
Input High Leakage Current
(Port 0)
I
I
V < V < 5.5V
SS IN
10
10
10
µA
µA
µA
µA
IHL1
IHL2
Input High Leakage Current
(Port 1, 2, 3, 4)
V
= 2.3V
–10
IH
Input Low Leakage Current
(Port 1, 2, 3, 4)
I
V
< 0.5V
= 3.6V
–10
ILL
IL
V
CC
10
80
I
PD
LVD Logic disabled
Power-down Mode
(Note 2)
LVD Logic enabled
µA
mA
mA
mA
mA
mA
mA
Active - 12MHz
Idle - 12MHz
Active - 24MHz
Idle - 24MHz
Active - 40MHz
Idle - 40MHz
TBD
TBD
TBD
TBD
TBD
TBD
V
V
= 3.6V
= 3.6V
CC
I
CC-CPU
(Note
3,4,5)
CC
V
CC
V
CC
= 3.6V
= 3.3V
LVD Low Voltage Detect Reset
Threshold
V
LVD
2.3
2.5
2.7
V
Note: 1. Power supply (V ) is always 3.0 to 3.6V for the MCU Module. V for the PSD Module may be 3V or 5V.
CC
DD
2. I (Power-down Mode) is measured with: XTAL1 = V ; XTAL2 = NC; RESET = V ; Port 0 = V ; all other pins are disconnected.
PD
SS
CC
CC
3. I
(Active Mode) is measured with: XTAL1 driven with t
, t
= 5ns, V = V + 0.5V, V = V – 0.5V, XTAL2 = NC;
CC-CPU
CLCH CHCL IL SS IH CC
RESET = V ; Port 0 = V ; all other pins are disconnected. I would be slightly higher if a crystal oscillator is used (approximately
SS
CC
CC
1mA).
4. I
(Idle Mode) is measured with: XTAL1 driven with t
, t
= 5ns, V = V + 0.5V, V = V – 0.5V, XTAL2 = NC;
CC-CPU
CLCH CHCL IL SS IH CC
RESET = V ; Port 0 = V ; all other pins are disconnected. I would be slightly higher if a crystal oscillator is used (approximately
CC
CC
CC
1mA).
5. I/O current = 0mA, all I/O pins are disconnected.
100/123
µPSD33XX
Table 107. PSD Module DC Characteristics (with 5V V
)
DD
Test Condition
Symbol
Parameter
(in addition to those in
Table 103, page 98)
Min.
Typ.
Max.
+0.5
Unit
V
4.5V < V < 5.5V
V
Input High Voltage
Input Low Voltage
2
V
V
IH
DD
DD
V
4.5V < V < 5.5V
–0.5
0.8
IL
DD
V
(min) for Flash Erase and
DD
V
2.5
4.2
V
LKO
Program
I
= 20µA, V = 4.5V
0.01
0.25
4.49
3.9
0.1
V
V
OL
DD
V
Output Low Voltage
OL
I
= 8mA, V = 4.5V
0.45
OL
DD
I
= –20µA, V = 4.5V
4.4
2.4
V
OH
DD
Output High Voltage Except
V
OH
V
STBY
On
I
= –2mA, V = 4.5V
V
OH
DD
V
Output High Voltage V
On
I
= 1µA
V
– 0.8
STBY
V
OH1
STBY
OH1
V
I
V
SRAM Stand-by Voltage
SRAM Stand-by Current
2.0
V
STBY
DD
V
= 0V
0.5
1
µA
µA
V
STBY
DD
I
Idle Current (V
input)
V
> V
–0.1
2
0.1
IDLE
STBY
DD STBY
V
Only on V
V
– 0.2
DD
SRAM Data Retention Voltage
DF
STBY
CSI > V – 0.3V
DD
Stand-by Supply Current
for Power-down Mode
I
SB
50
200
µA
(Notes 1,2)
I
V
< V < V
SS IN DD
Input Leakage Current
Output Leakage Current
–1
±0.1
±5
1
µA
µA
LI
I
LO
0.45 < V
< V
OUT DD
–10
10
PLD_TURBO = Off,
f = 0MHz (Note 4)
0
µA/PT
µA/PT
mA
PLD Only
PLD_TURBO = On,
f = 0MHz
400
15
700
30
Operating
Supply
Current
I
(DC)
CC
During Flash memory
WRITE/Erase Only
(Note 4)
Flash memory
Read only, f = 0MHz
f = 0MHz
0
0
0
0
mA
mA
SRAM
PLD AC Adder
Note 3
3.5
mA/
MHz
I
(AC)
Flash memory AC Adder
SRAM AC Adder
2.5
1.5
CC
(Note 4)
mA/
MHz
3.0
Note: 1. CSI deselected or internal Power-down mode is active.
2. PLD is in non-Turbo mode, and none of the inputs are switching.
3. Please see Figure 44 for the PLD current calculation.
4. I
= 0 mA
OUT
101/123
µPSD33XX
Table 108. PSD Module DC Characteristics (with 3.3V V
Test Condition
)
DD
Symbol
Parameter
(in addition to those in
Table 104, page 98)
Min.
0.7V
Typ.
Max.
+0.5
Unit
V
3.0V < V < 3.6V
V
DD
High Level Input Voltage
Low Level Input Voltage
V
V
IH
DD
DD
V
3.0V < V < 3.6V
–0.5
1.5
0.8
IL
DD
V
(min) for Flash Erase and
DD
V
2.2
V
LKO
Program
I
= 20µA, V = 3.0V
0.01
0.15
2.99
2.8
0.1
V
V
OL
DD
V
Output Low Voltage
OL
I
= 4mA, V = 3.0V
0.45
OL
DD
I
= –20µA, V = 3.0V
2.9
2.7
V
OH
DD
Output High Voltage Except
V
OH
V
STBY
On
I
= –1mA, V = 3.0V
V
OH
DD
V
Output High Voltage V
On
I
= 1µA
V
– 0.8
STBY
V
OH1
STBY
OH1
V
I
V
SRAM Stand-by Voltage
SRAM Stand-by Current
2.0
V
STBY
DD
V
= 0V
0.5
1
µA
µA
V
STBY
DD
I
Idle Current (V
input)
V
> V
–0.1
2
0.1
IDLE
STBY
DD STBY
V
Only on V
V
– 0.2
DD
SRAM Data Retention Voltage
DF
STBY
CSI > V – 0.3V
Stand-by Supply Current
for Power-down Mode
DD
I
SB
25
100
µA
(Notes 1,2)
I
V
< V < V
SS IN DD
Input Leakage Current
Output Leakage Current
–1
±0.1
±5
1
µA
µA
LI
I
LO
0.45 < V < V
IN DD
–10
10
PLD_TURBO = Off,
f = 0MHz (Note 2)
0
µA/PT
µA/PT
mA
PLD Only
PLD_TURBO = On,
f = 0MHz
200
10
400
25
Operating
Supply
Current
I
(DC)
CC
During Flash memory
WRITE/Erase Only
(Note 4)
Flash memory
Read only, f = 0MHz
f = 0MHz
0
0
0
0
mA
mA
SRAM
PLD AC Adder
Note 3
mA/
MHz
I
(AC)
Flash memory AC Adder
SRAM AC Adder
1.5
0.8
2.0
1.5
CC
(Note 4)
mA/
MHz
Note: 1. CSI deselected or internal PD is active.
2. PLD is in non-Turbo mode, and none of the inputs are switching.
3. Please see Figure 45 for the PLD current calculation.
4. I
= 0 mA
OUT
102/123
µPSD33XX
Figure 47. External PSEN/READ Cycle (80-pin Device Only)
t
t
LLPL
LHLL
ALE
t
t
PLPH
AVLL
PSEN
RD
t
t
PXAV
LLAX
t
PXIZ
t
AZPL
MCU
AD0 - AD7
INSTR
IN
A0-A7
A0-A7
t
AVIV
t
PXIX
MCU
A8 - A11
A8-A11
A8-A11
AI07875
Table 109. External PSEN or READ Cycle AC Characteristics (3V or 5V Device)
Variable Oscillator
(1)
40MHz Oscillator
1/t
= 8 to 40MHz
CLCL
Symbol
Unit
Parameter
Min
17
Max
Min
Max
t
t
– 8
CLCL
ALE pulse width
ns
ns
ns
ns
ns
LHLL
t
t
– 12
CLCL
Address setup to ALE
Address hold after ALE
ALE to PSEN or RD
13
AVLL
t
0.5t
0.5t
nt
– 5
7.5
7.5
40
LLAX
CLCL
CLCL
t
– 5
LLPL
(2)
t
– 10
PLPH
PSEN or RD pulse width
CLCL
Input instruction/data hold after
PSEN or RD
t
2
2
ns
ns
PXIX
Input instruction/data float after
PSEN or RD
t
0.5t
mt
– 2
– 5
10.5
70
PHIZ
CLCL
0.5t
– 5
Address hold after PSEN or RD
7.5
–2
ns
ns
ns
t
CLCL
PXAV
(2)
t
AVIV
CLCL
Address to valid instruction/data in
Address float to PSEN or RD
t
–2
AZPL
Note: 1. BUSCON Register is configured for 4 PFQCLK.
2. Refer to Table 110 for “n” and “m” values.
Table 110. n, m, and x, y Values
PSEN (code) Cycle
# of PFQCLK in
READ Cycle
WRITE Cycle
BUSCON Reg.
n
1
2
3
4
-
m
2
3
4
5
-
n
-
m
-
x
-
y
-
3
4
5
6
7
2
3
4
5
3
4
5
6
2
3
4
5
1
2
3
4
103/123
µPSD33XX
Figure 48. External WRITE Cycle (80-pin Device Only)
ALE
tLHLL
tWHLH
PSEN
tLLWL
tWLWH
WR
tWHQX
tAVLL
tLLAX
tQVWH
DATA OUT
MCU
AD0 - AD7
A0-A7
INSTR IN
A0-A7
tAVWL
MCU
A8 - A11
A8-A11
A8-A11
AI07877
Table 111. External WRITE Cycle AC Characteristics (3V or 5V Device)
Variable Oscillator
(1)
40MHz Oscillator
1/t
= 8 to 40MHz
CLCL
Symbol
Parameter
Unit
Min
17
Max
Min
Max
t
t
– 8
CLCL
ALE pulse width
ns
ns
ns
ns
ns
ns
ns
ns
ns
LHLL
t
t
– 12
CLCL
Address Setup to ALE
Address hold after ALE
13
AVLL
t
0.5t
– 5
CLCL
7.5
40
LLAX
(2)
t
xt
– 10
– 5
WLWH
CLCL
WR pulse width
t
0.5t
1.5t
ALE to WR
7.5
27.5
6.5
20
LLWL
CLCL
t
– 10
CLCL
Address valid to WR
WR High to ALE High
AVWL
t
0.5t
yt
– 6 0.5t
+ 2
+ 2
14.5
14.5
WHLH
CLCL
CLCL
CLCL
(y)
t
– 5
QVWH
CLCL
Data setup before WR
Data hold after WR
t
0.5t
– 6 0.5t
6.5
WHQX
CLCL
Note: 1. BUSCON Register is configured for 4 PFQCLK.
2. Refer to Table 110, page 103 for “n” and “m” values.
Table 112. External Clock Drive
Variable Oscillator
40MHz Oscillator
Min Max
1/t
= 8 to 40MHz
(1)
CLCL
Symbol
Unit
Parameter
Min
Max
t
Oscillator period
25
10
10
125
ns
ns
ns
ns
ns
CLCL
t
t
t
– t
– t
10
10
High time
Low time
Rise time
Fall time
CHCX
CLCL
CLCX
t
CLCX
CLCL
CLCX
t
CLCH
t
CHCL
104/123
µPSD33XX
Table 113. A/D Analog Specification
(1)
Symbol
Parameter
Min.
Typ.
Max.
Unit
mA
µA
V
Test Conditions
Input = AV
Normal
4.0
REF
I
DD
Power-down
40
AV
AV
Analog Input Voltage
GND
IN
(2)
REF
Analog Reference Voltage
3.6
V
AV
REF
Accuracy Resolution
10
±1
±1
bits
LSB
LSB
dB
Input = 0 – AV
(V)
(V)
INL
DNL
Integral Nonlinearity
REF
Input = 0 – AV
Differential Nonlinearity
Signal to Noise Ratio
Signal to Noise Distortion Ratio
ADC Clock
REF
f
= 500ksps
SNR
50
48
2
54
52
8
SAMPLE
SNDR
ACLK
dB
16
8
MHz
µS
t
Conversion Time
8MHz
Calibration Time
1
4
C
t
Power-up Time
16
mS
kHz
dB
CAL
f
Analog Input Frequency
Total Harmonic Distortion
60
IN
THD
50
54
Note: 1. f 2kHz, ACLK = 8MHz, AV
= V = 3.3V
CC
IN
REF
2. AV
= V in 52-pin package.
REF
CC
105/123
µPSD33XX
Figure 49. Input to Output Disable / Enable
INPUT
tER
tEA
INPUT TO
OUTPUT
ENABLE/DISABLE
AI02863
Table 114. CPLD Combinatorial Timing (5V PSD Module)
Slew
PT Turbo
Symbol
Parameter
Conditions
Min
Max
20
Unit
ns
(1)
Aloc
Off
rate
CPLD Input Pin/Feedback to
CPLD Combinatorial Output
(2)
+ 2
+ 10
– 2
t
PD
CPLD Input to CPLD Output
Enable
t
21
+ 10
+ 10
+ 10
+ 10
– 2
– 2
– 2
ns
EA
CPLD Input to CPLD Output
Disable
t
ER
21
ns
CPLD Register Clear or Preset
Delay
t
21
ns
ARP
CPLD Register Clear or Preset
Pulse Width
t
10
ns
ARPW
Any
macrocell
t
CPLD Array Delay
11
+ 2
ns
ARD
Note: 1. Fast Slew Rate output available on PA3-PA0, PB3-PB0, and PD2-PD1. Decrement times by given amount
2. t for MCU address and control signals refers to delay from pins on Port 0, Port 2, RD WR, PSEN and ALE to CPLD combinatorial
PD
output (80-pin package only)
Table 115. CPLD Combinatorial Timing (3V PSD Module)
Slew
PT Turbo
Symbol
Parameter
Conditions
Min
Max
40
Unit
ns
(1)
Aloc
Off
rate
CPLD Input Pin/Feedback to
CPLD Combinatorial Output
(2)
+ 4
+ 20
– 6
t
PD
CPLD Input to CPLD Output
Enable
t
43
+ 20
+ 20
+ 20
+ 20
– 6
– 6
– 6
ns
EA
CPLD Input to CPLD Output
Disable
t
ER
43
ns
CPLD Register Clear or
Preset Delay
t
40
ns
ARP
CPLD Register Clear or
Preset Pulse Width
t
25
ns
ARPW
Any
macrocell
t
CPLD Array Delay
25
+ 4
ns
ARD
Note: 1. Fast Slew Rate output available on PA3-PA0, PB3-PB0, and PD2-PD1. Decrement times by given amount
2. t for MCU address and control signals refers to delay from pins on Port 0, Port 2, RD WR, PSEN and ALE to CPLD combinatorial
PD
output (80-pin package only)
106/123
µPSD33XX
Figure 50. Synchronous Clock Mode Timing – PLD
t
t
CL
CH
CLKIN
INPUT
t
S
t
H
t
CO
REGISTERED
OUTPUT
AI02860
Table 116. CPLD Macrocell Synchronous Clock Mode Timing (5V PSD Module)
Slew
PT Turbo
Symbol
Parameter
Conditions
1/(t +t
Min
Max
40.0
66.6
83.3
Unit
(1)
Aloc
Off
rate
Maximum Frequency
External Feedback
)
CO
MHz
MHz
MHz
S
Maximum Frequency
f
1/(t +t –10)
S CO
MAX
Internal Feedback (f
)
CNT
Maximum Frequency
Pipelined Data
1/(t +t
)
CH CL
t
Input Setup Time
Input Hold Time
12
0
+ 2
+ 10
ns
ns
ns
ns
S
t
H
t
Clock High Time
Clock Low Time
Clock Input
Clock Input
Clock Input
Any macrocell
6
CH
t
6
CL
t
Clock to Output Delay
CPLD Array Delay
13
11
– 2
ns
ns
ns
CO
t
+ 2
ARD
(2)
t
t +t
CH CL
12
MIN
Minimum Clock Period
Note: 1. Fast Slew Rate output available on PA3-PA0, PB3-PB0, and PD2-PD1. Decrement times by given amount.
2. CLKIN (PD1) t = t + t
.
CL
CLCL
CH
Table 117. CPLD Macrocell Synchronous Clock Mode Timing (3V PSD Module)
PT
Slew
Turbo
Off
Symbol
Parameter
Conditions
Min
Max
22.2
28.5
40.0
Unit
MHz
MHz
MHz
(1)
Aloc
rate
Maximum Frequency
External Feedback
1/(t +t
)
CO
S
Maximum Frequency
f
1/(t +t –10)
S CO
MAX
Internal Feedback (f
)
CNT
Maximum Frequency
Pipelined Data
1/(t +t
)
CH CL
t
Input Setup Time
Input Hold Time
20
0
+ 4
+ 20
ns
ns
ns
ns
ns
ns
ns
S
t
H
t
Clock High Time
Clock Low Time
Clock Input
Clock Input
Clock Input
Any macrocell
15
10
CH
t
CL
t
Clock to Output Delay
CPLD Array Delay
25
25
– 6
CO
t
+ 4
ARD
(2)
t
t +t
CH CL
25
MIN
Minimum Clock Period
Note: 1. Fast Slew Rate output available on PA3-PA0, PB3-PB0, and PD2-PD1. Decrement times by given amount.
2. CLKIN (PD1) t = t + t
.
CL
CLCL
CH
107/123
µPSD33XX
Figure 51. Asynchronous RESET / Preset
tARPW
RESET/PRESET
INPUT
tARP
REGISTER
OUTPUT
AI02864
Figure 52. Asynchronous Clock Mode Timing (product term clock)
tCHA
tCLA
CLOCK
INPUT
tSA
tHA
tCOA
REGISTERED
OUTPUT
AI02859
Table 118. CPLD Macrocell Asynchronous Clock Mode Timing (5V PSD Module)
PT Turbo Slew
Symbol
Parameter
Conditions
1/(t +t
Min
Max
38.4
62.5
71.4
Unit
MHz
MHz
MHz
Aloc
Off
Rate
Maximum Frequency
External Feedback
)
SA COA
Maximum Frequency
f
1/(t +t
–10)
)
MAXA
SA COA
Internal Feedback (f
)
CNTA
Maximum Frequency
Pipelined Data
1/(t
+t
CHA CLA
t
Input Setup Time
7
8
9
9
+ 2
+ 10
ns
ns
ns
ns
ns
ns
ns
SA
t
Input Hold Time
HA
t
Clock Input High Time
Clock Input Low Time
Clock to Output Delay
CPLD Array Delay
Minimum Clock Period
+ 10
+ 10
+ 10
CHA
t
CLA
t
21
11
– 2
COA
t
Any macrocell
+ 2
ARDA
t
1/f
CNTA
16
MINA
108/123
µPSD33XX
Table 119. CPLD Macrocell Asynchronous Clock Mode Timing (3V PSD Module)
PT Turbo Slew
Symbol
Parameter
Conditions
1/(t +t
Min
Max
21.7
27.8
33.3
Unit
MHz
MHz
MHz
Aloc
Off
Rate
Maximum Frequency
External Feedback
)
SA COA
Maximum Frequency
f
1/(t +t
–10)
)
MAXA
SA COA
Internal Feedback (f
)
CNTA
Maximum Frequency
Pipelined Data
1/(t
+t
CHA CLA
t
Input Setup Time
Input Hold Time
10
12
17
13
+ 4
+ 20
ns
ns
ns
ns
ns
ns
ns
SA
t
HA
t
Clock High Time
+ 20
+ 20
+ 20
CHA
t
Clock Low Time
CLA
t
Clock to Output Delay
CPLD Array Delay
Minimum Clock Period
36
25
– 6
COA
t
Any macrocell
+ 4
ARD
t
1/f
CNTA
36
MINA
Figure 53. Input Macrocell Timing (Product Term Clock)
t
t
INL
INH
PT CLOCK
INPUT
t
t
IH
IS
OUTPUT
t
INO
AI03101
Table 120. Input Macrocell Timing (5V PSD Module)
PT
Aloc
Turbo
Off
Symbol
Parameter
Input Setup Time
Conditions
Min
Max
Unit
t
IS
0
15
9
ns
ns
ns
ns
ns
(Note 1)
(Note 1)
(Note 1)
(Note 1)
(Note 1)
t
IH
Input Hold Time
+ 10
t
NIB Input High Time
NIB Input Low Time
INH
t
9
INL
t
NIB Input to Combinatorial Delay
34
+ 2
+ 10
INO
Note: 1. Inputs from Port A, B, and C relative to register/ latch clock from the PLD. ALE/AS latch timings refer to t
and t
.
LXAX
AVLX
109/123
µPSD33XX
Table 121. Input Macrocell Timing (3V PSD Module)
PT
Aloc
Turbo
Off
Symbol
Parameter
Input Setup Time
Conditions
Min
Max
Unit
t
IS
0
ns
ns
ns
ns
ns
(Note 1)
(Note 1)
(Note 1)
(Note 1)
(Note 1)
t
IH
Input Hold Time
25
12
12
+ 20
t
NIB Input High Time
NIB Input Low Time
INH
t
INL
t
NIB Input to Combinatorial Delay
46
+ 4
+ 20
INO
Note: 1. Inputs from Port A, B, and C relative to register/latch clock from the PLD. ALE latch timings refer to t
and t
.
LXAX
AVLX
Table 122. Program, WRITE and Erase Times (5V, 3V PSD Modules)
Symbol
Parameter
Min.
Typ.
8.5
3
Max.
Unit
Flash Program
s
(1)
30
30
s
s
Flash Bulk Erase (pre-programmed)
Flash Bulk Erase (not pre-programmed)
Sector Erase (pre-programmed)
Sector Erase (not pre-programmed)
Byte Program
5
t
1
s
WHQV3
t
2.2
14
s
WHQV2
t
150
µs
cycles
µs
ns
WHQV1
Program / Erase Cycles (per Sector)
Sector Erase Time-Out
100,000
t
100
WHWLO
(2)
t
30
Q7VQV
DQ7 Valid to Output (DQ7-DQ0) Valid (Data Polling)
Note: 1. Programmed to all zero before erase.
2. The polling status, DQ7, is valid t
time units before the data byte, DQ0-DQ7, is valid for reading.
Q7VQV
110/123
µPSD33XX
Figure 54. Peripheral I/O READ Timing
ALE
ADDRESS
DATA VALID
A/D BUS
t
(PA)
(PA)
AVQV
t
SLQV
CSI
RD
t
(PA)
RLQV
t
(PA)
RHQZ
t
(PA)
DVQV
DATA ON PORT A
AI06610
Table 123. Port A Peripheral Data Mode READ Timing (5V PSD Module)
Turbo
Unit
Off
Symbol
Parameter
Conditions
Min
Max
Address Valid to Data
Valid
t
37
+ 10
+ 10
ns
AVQV–PA
(Note 1)
t
CSI Valid to Data Valid
27
32
22
23
ns
ns
ns
ns
SLQV–PA
t
t
RD to Data Valid
RLQV–PA
(Note 2)
Data In to Data Out Valid
RD to Data High-Z
DVQV–PA
RHQZ–PA
t
Note: 1. Any input used to select Port A Data Peripheral Mode.
2. Data is already stable on Port A.
Table 124. Port A Peripheral Data Mode READ Timing (3V PSD Module)
Turbo
Off
Symbol
Parameter
Conditions
Min
Max
Unit
t
Address Valid to Data Valid
CSI Valid to Data Valid
RD to Data Valid
50
37
45
38
36
+ 20
+ 20
ns
ns
ns
ns
ns
AVQV–PA
(Note 1)
t
SLQV–PA
t
t
RLQV–PA
(Note 2)
Data In to Data Out Valid
RD to Data High-Z
DVQV–PA
RHQZ–PA
t
Note: 1. Any input used to select Port A Data Peripheral Mode.
2. Data is already stable on Port A.
111/123
µPSD33XX
Figure 55. Peripheral I/O WRITE Timing
ALE
ADDRESS
DATA OUT
A/D BUS
tWHQZ (PA)
tWLQV (PA)
WR
tDVQV (PA)
PORT A
DATA OUT
AI06611
Table 125. Port A Peripheral Data Mode WRITE Timing (5V PSD Module)
Symbol
Parameter
WR to Data Propagation Delay
Data to Port A Data Propagation Delay
WR Invalid to Port A Tri-state
Conditions
Min
Max
25
Unit
ns
t
WLQV–PA
t
22
ns
DVQV–PA
(Note 1)
t
20
ns
WHQZ–PA
Note: 1. Data stable on Port 0 pins to data on Port A.
Table 126. Port A Peripheral Data Mode WRITE Timing (3V PSD Module)
Symbol
Parameter
WR to Data Propagation Delay
Data to Port A Data Propagation Delay
WR Invalid to Port A Tri-state
Conditions
Min
Max
42
Unit
ns
t
WLQV–PA
t
38
ns
DVQV–PA
WHQZ–PA
(Note 1)
t
33
ns
Note: 1. Data stable on Port 0 pins to data on Port A.
112/123
µPSD33XX
Figure 56. Reset (RESET) Timing
VCC(min)
V
CC
t
NLNH
t
t
NLNH-PO
NLNH-A
Power-On Reset
Warm Reset
RESET
AI07874
Table 127. Reset (RESET) Timing (5V PSD Module)
Symbol
Parameter
Conditions
Min
150
1
Max
Unit
ns
(1)
t
NLNH
RESET Active Low Time
t
Power-on Reset Active Low Time
ms
µs
NLNH–PO
(2)
t
25
NLNH–A
Warm RESET
t
RESET High to Operational Device
120
ns
OPR
Note: 1. Reset (RESET) does not reset Flash memory Program or Erase cycles.
2. Warm RESET aborts Flash memory Program or Erase cycles, and puts the device in READ Mode.
Table 128. Reset (RESET) Timing (3V PSD Module)
Symbol
Parameter
Conditions
Min
300
1
Max
Unit
ns
(1)
t
NLNH
RESET Active Low Time
t
Power-on Reset Active Low Time
ms
µs
NLNH–PO
(2)
t
25
NLNH–A
Warm RESET
t
RESET High to Operational Device
300
ns
OPR
Note: 1. Reset (RESET) does not reset Flash memory Program or Erase cycles.
2. Warm RESET aborts Flash memory Program or Erase cycles, and puts the device in READ Mode.
Table 129. V
Symbol
Definitions Timing (5V, 3V PSD Modules)
STBYON
Parameter
Conditions
Min
Typ
Max
Unit
t
V
V
Detection to V
Output High
STBYON
20
µs
BVBH
STBY
(Note 1)
Off Detection to V
Output
STBY
STBYON
t
20
µs
BXBL
(Note 1)
Low
Note: 1. V
timing is measured at V ramp rate of 2ms.
CC
STBYON
113/123
µPSD33XX
Figure 57. ISC Timing
tISCCH
TCK
tISCCL
tISCPSU
tISCPH
TDI/TMS
t ISCPZV
tISCPCO
ISC OUTPUTS/TDO
tISCPVZ
ISC OUTPUTS/TDO
AI02865
Table 130. ISC Timing (5V PSD Module)
Symbol
Parameter
Conditions
Min
Max
Unit
MHz
ns
t
Clock (TCK, PC1) Frequency (except for PLD)
Clock (TCK, PC1) High Time (except for PLD)
Clock (TCK, PC1) Low Time (except for PLD)
Clock (TCK, PC1) Frequency (PLD only)
Clock (TCK, PC1) High Time (PLD only)
20
ISCCF
(Note 1)
(Note 1)
(Note 1)
(Note 2)
(Note 2)
(Note 2)
t
23
23
ISCCH
t
ns
ISCCL
t
2
MHz
ns
ISCCFP
t
240
ISCCHP
t
Clock (TCK, PC1) Low Time (PLD only)
ISC Port Set Up Time
240
7
ns
ns
ns
ns
ns
ns
ISCCLP
t
ISCPSU
t
ISC Port Hold Up Time
5
ISCPH
t
ISC Port Clock to Output
21
21
21
ISCPCO
t
ISC Port High-Impedance to Valid Output
ISC Port Valid Output to High-Impedance
ISCPZV
t
ISCPVZ
Note: 1. For non-PLD Programming, Erase or in ISC By-pass Mode.
2. For Program or Erase PLD only.
114/123
µPSD33XX
Table 131. ISC Timing (3V PSD Module)
Symbol
Parameter
Conditions
(Note 1)
(Note 1)
(Note 1)
(Note 2)
(Note 2)
(Note 2)
Min
Max
Unit
MHz
ns
t
Clock (TCK, PC1) Frequency (except for PLD)
Clock (TCK, PC1) High Time (except for PLD)
Clock (TCK, PC1) Low Time (except for PLD)
Clock (TCK, PC1) Frequency (PLD only)
Clock (TCK, PC1) High Time (PLD only)
12
2
ISCCF
t
40
40
ISCCH
t
ns
ISCCL
t
MHz
ns
ISCCFP
t
240
ISCCHP
t
Clock (TCK, PC1) Low Time (PLD only)
ISC Port Set Up Time
240
12
5
ns
ns
ns
ns
ns
ns
ISCCLP
t
ISCPSU
t
ISC Port Hold Up Time
ISCPH
t
ISC Port Clock to Output
30
30
30
ISCPCO
t
ISC Port High-Impedance to Valid Output
ISC Port Valid Output to High-Impedance
ISCPZV
t
ISCPVZ
Note: 1. For non-PLD Programming, Erase or in ISC By-pass Mode.
2. For Program or Erase PLD only.
Figure 58. MCU Module AC Measurement I/O Waveform
V
– 0.5V
0.45V
CC
0.2 V
0.2 V
+ 0.9V
CC
Test Points
– 0.1V
CC
AI06650
Note: AC inputs during testing are driven at V –0.5V for a logic '1,' and 0.45V for a logic '0.'
CC
Timing measurements are made at V (min) for a logic '1,' and V (max) for a logic '0'
IH
IL
Figure 59. PSD Module AC Float I/O Waveform
V
V
– 0.1V
OH
OL
V
V
+ 0.1V
LOAD
Test Reference Points
– 0.1V
– 0.1V
+ 0.1V
LOAD
CC
0.2 V
AI06651
Note: For timing purposes, a Port pin is considered to be no longer floating when a 100mV change from load voltage occurs, and begins to
float when a 100mV change from the loaded V or V level occurs
OH
OL
I
and I ≥ 20mA
OH
OL
115/123
µPSD33XX
Figure 60. External Clock Cycle
Figure 61. Recommended Oscillator Circuits
Note: C1, C2 = 30pF ± 10pF for crystals
For ceramic resonators, contact resonator manufacturer
Oscillation circuit is designed to be used either with a ceramic resonator or crystal oscillator. Since each crystal and ceramic resonator
have their own characteristics, the user should consult the crystal manufacturer for appropriate values of external components.
Figure 62. PSD Module AC Measurement I/O
Waveform
Figure 63. PSD Module AC Measurement Load
Circuit
2.01 V
3.0V
195 Ω
Test Point
1.5V
Device
Under Test
0V
CL = 30 pF
(Including Scope and
AI03103b
Jig Capacitance)
AI03104b
Table 132. I/O Pin Capacitance
2
Symbol
Parameter
Test Condition
Max.
Unit
pF
Typ.
C
V
= 0V
= 0V
Input Capacitance (for input pins)
4
6
IN
IN
Output Capacitance (for input/
output pins)
pF
C
V
OUT
8
12
OUT
Note: 1. Sampled only, not 100% tested.
2. Typical values are for T = 25°C and nominal supply voltages.
A
116/123
µPSD33XX
PART NUMBERING
Table 133. Ordering Information Scheme
Example:
µPSD 33
3
4
D
V
–
24
U
6
T
Device Type
µPSD = Microcontroller PSD
Family
32 = 8032 core
33 = Turbo core
SRAM Size
1 = 16Kbit
3 = 64Kbit
5 = 256Kbit
Main Flash Memory Size
2 = 512Kbit
3 = 1Mbit
4 = 2Mbit
IP Mix
2
D = IP Mix: I C, SPI, UART (2), IrDA, ADC, Supervisor, PCA
Operating Voltage
blank = V = 4.5 to 5.5V
CC
V = V = 3.0 to 3.6V
CC
Speed
–24 = 24MHz
–40 = 40MHz
Package
T = 52-pin TQFP
U = 80-pin TQFP
Temperature Range
1 = 0 to 70°C
6 = –40 to 85°C
Shipping Option
Tape & Reel Packing = T
For a list of available options (e.g., Speed, Package) or for further information on any aspect of this device,
please contact the ST Sales Office nearest to you.
117/123
µPSD33XX
PACKAGE MECHANICAL INFORMATION
Figure 64. TQFP52 – 52-lead Plastic Quad Flatpack Package Outline
D
D1
D2
A2
e
b
Ne
E2 E1 E
N
1
Nd
A
CP
L1
c
A1
α
L
QFP-A
Note: Drawing is not to scale.
118/123
µPSD33XX
Table 134. TQFP52 – 52-lead Plastic Quad Flatpack Package Mechanical Data
mm
Min
–
inches
Symb
Typ
Max
1.75
0.20
1.55
0.40
0.23
–
Typ
Min
–
Max
0.069
0.008
0.061
0.016
0.009
–
–
–
A
A1
A2
b
–
–
0.05
1.25
0.20
0.07
–
–
–
0.002
0.049
0.008
0.002
–
–
–
c
–
–
D
12.00
10.00
0.473
0.394
D1
D2
E
–
–
–
–
12.00
10.00
7.80
0.65
–
–
–
–
–
0.473
0.394
0.307
0.026
–
–
–
–
–
E1
E2
e
–
0.45
–
–
0.75
–
–
0.018
–
–
0.030
–
L
L1
α
1.00
–
0.039
–
0°
7°
0°
7°
n
52
13
13
–
52
13
13
–
Nd
Ne
CP
–
0.10
–
0.004
119/123
µPSD33XX
Figure 65. TQFP80 – 80-lead Plastic Quad Flatpack Package Outline
D
D1
D2
A2
e
b
Ne
E2 E1 E
N
1
Nd
A
CP
L1
c
A1
α
L
QFP-A
Note: Drawing is not to scale.
120/123
µPSD33XX
Table 135. TQFP80 – 80-lead Plastic Quad Flatpack Package Mechanical Data
mm
Min
–
inches
Symb
Typ
–
Max
1.60
0.15
1.45
Typ
–
Min
–
Max
0.063
0.006
0.057
A
A1
A2
–
0.05
1.35
–
0.002
0.053
1.40
0.055
0.22
–
0.17
0.09
–
0.27
0.20
–
0.009
–
0.007
0.011
b
c
0.004
0.008
D
14.00
12.00
9.50
14.00
12.00
9.50
0.50
0.60
1.00
3.5
0.551
0.472
0.374
0.473
0.394
0.374
0.020
0.024
0.039
3.5
–
–
–
D1
D2
E
–
–
–
–
–
–
–
–
–
–
–
E1
E2
e
–
–
–
–
–
–
–
–
–
–
–
–
L
0.45
–
0.75
–
0.018
–
0.030
–
L1
α
0°
80
20
20
–
7°
0°
80
20
20
–
7°
n
Nd
Ne
CP
–
0.08
–
0.003
121/123
µPSD33XX
REVISION HISTORY
Table 136. Document Revision History
Date
Rev. #
Revision Details
July 2003
1.0
First Issue
122/123
µPSD33XX
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of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
The ST logo is registered trademark of STMicroelectronics
All other names are the property of their respective owners.
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