VD5377CBSW [STMICROELECTRONICS]
Ultra-low power motion sensor for optical finger navigation;
| 型号： | VD5377CBSW |
| 厂家： | 
ST |
| 描述： | Ultra-low power motion sensor for optical finger navigation |
| 文件： | 总88页 (文件大小：2367K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
VD5377
Ultra-low power motion sensor for optical finger navigation (OFN)
Datasheet - preliminary data
Features
• Ultra-low power performance and high
speed/high accuracy motion detection (up to
28 in/s @ 4000 f/s)
• Manual or automatic power management
options
• Very low quiescent and operating current
modes for battery life saving
• Fully integrated solution: internal oscillator and
LED driver
2
• I C interface with fast polling rates for high-end
applications (report rate up to 1 per ms).
2
2
• User-selectable I C address (default I C
address is 0xA6)
• CPI programmable up to 3,200 CPI
• Fully automatic exposure control (AEC)
Applications
• Smart phones
• Laptop/Netbook PCs
• Media players
• GPS devices
• Remote controls for home entertainment
equipment
Description
The VD5377 is an ultra-low power, single-chip
controller IC containing all the functions
necessary for optical joysticks/optical finger
navigation modules enabling improved mobile
experience and longer battery life. This device is
cost and performance optimized for Optical
Finger Navigation applications and includes
special features to ensure optimum performance
even in bright sunlight.
February 2013
Doc ID 022952 Rev 2
1/88
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to
change without notice.
www.st.com
1
Contents
VD5377
Contents
1
2
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.1
1.2
1.3
Technical specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
VD5377 enhancements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Floor plan changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Silicon specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.1
2.2
2.3
2.4
2.5
Silicon thickness . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Die size and optical center . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Pad opening sizes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Device pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Bond pad coordinates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3
4
5
Application schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.1
3.2
Signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Cursor orientation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
System overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.1
4.2
MANUAL power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
AUTOMATIC power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
I/O description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
5.1
5.2
5.3
5.4
5.5
I2C_SEL[2:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
LED_OUT (tracking LED) and GPIO0 . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
MOTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
STANDBY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
POWERDOWN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
6
Key features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
6.1
6.2
6.3
6.4
Feature count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Minimum features threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
X/Y scaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Automatic exposure control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
2/88
Doc ID 022952 Rev 2
VD5377
Contents
6.5
6.6
6.7
5 x 5 high pass filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Sunlight timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Automatic/manual frame rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
7
Additional features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
7.1
7.2
7.3
Auto-movement filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Adaptive CPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
BACKLED[2:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
7.3.1
PWM operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
8
Basic start-up information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
8.1
8.2
8.3
8.4
8.5
8.6
Register override . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Recommended start-up settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Reading X/Y motion data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Switching between Automatic mode and Manual mode . . . . . . . . . . . . . . 51
Revision ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Soft reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
9
Image capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
9.1
I2C image capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
9.1.1
9.1.2
Step-by-step procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
9.2
Fast capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
10
11
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
10.1 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
10.2 Digital I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
10.3 I2C timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
2
I C interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
11.1 Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
11.2 Data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
11.3 Message interpretation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
11.4 Type of messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
11.4.1
Single location, single data write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Doc ID 022952 Rev 2
3/88
Contents
VD5377
11.4.2
11.4.3
11.4.4
Single location read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Multiple location write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Multiple location read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
2
12
13
14
15
I C register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Acronyms and abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
4/88
Doc ID 022952 Rev 2
VD5377
List of tables
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Technical specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Die size and optical center comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Die size. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Optical center . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Pad openings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Bond pad coordinates. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Typical power consumption - Manual mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Manual mode timing constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Typical power consumption - automatic mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Automatic mode timing constraints. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
Table 26.
Table 27.
Table 28.
Table 29.
Table 30.
Table 31.
Table 32.
Table 33.
Table 34.
Table 35.
Table 36.
Table 37.
Table 38.
Table 39.
Table 40.
Table 41.
2
User-selectable I C addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
2
Control register to dynamically configure device I C address . . . . . . . . . . . . . . . . . . . . . . 24
Control register for LED_OUT and GPIO0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Truth-table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Control register for motion pin polarity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Features and scaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Exposure control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
5x5 high-pass filter register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Sunlight DMIB timing mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Adaptive frame rate control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Modified exposure limits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Motion threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Auto-movement filter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Adaptive CPI. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
BACKLED control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Analog_ctrl2 recommended setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Start-up settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
X/Y motion data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Major/minor revision registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Soft reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
I2C frame dump registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Fast capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Operating conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Digital IO electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
I2C timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Register types. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
2
I C register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Acronyms and abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Delivery formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Doc ID 022952 Rev 2
5/88
List of figures
VD5377
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
VD5377 simplified system block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
VD5377 bond pad layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
VTOP supply (using internal regulator). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
1.8 V direct supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
VD5377 default XY orientation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
VD5377 power management modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Manual power mode flow diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Manual power mode timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Automatic power mode flow diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 10. Automatic power mode timing diagram (use_standby_pin=1) . . . . . . . . . . . . . . . . . . . . . . 23
Figure 11. LED drive options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 12. LED control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 13. Typical configuration of GPIO. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 14. MOTION behavior at power-up. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 15. In AUTOMATIC mode the STANDBY pin functions as I2C enable if use_standby_pin is
selected . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 16. Automatic exposure algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 17. Adaptive CPI algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Figure 18. BACKLED configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Figure 19. PWM operation: three independent PWM channels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Figure 20. Reading X/Y motion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Figure 21. Accessing low power standby from Automatic power mode. . . . . . . . . . . . . . . . . . . . . . . . 51
Figure 22. Automatic mode to low power standby mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Figure 23. I2C frame dump timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Figure 24. Flow chart procedure for I2C frame dump . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Figure 25. I2C frame dump output in debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Figure 26. Fast capture timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Figure 27. I2C timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Figure 28. Serial interface data transfer protocol. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Figure 29. VD5377 serial interface address. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Figure 30. Single location, single write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Figure 31. Single read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Figure 32. Multiple location write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Figure 33. Multiple location read: reading motion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
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VD5377
Overview
1
Overview
The VD5377 is an ultra-low power, single-chip controller IC containing all the functions
necessary for optical joysticks/optical finger navigation modules. It incorporates a 20 x 20,
30.4 µm pixel imaging array supporting frame rates up to 4 k frames/s capable of detecting
and tracking motion at up to 28 inches/s with high accuracy and low drift. Maximum velocity
is calculated as follows:
maximum velocity = (pixel size/lens magnification) x max frame rate x
max.displacement per frame
For example:
0.5 magnification = (30 µm/0.5) x 4000 f/s x 3 pixels = 0.72 m/s (28
inches/s)
Figure 1 shows a simplified block diagram of a typical optical navigation system.
2
2
Communication with the device is over a 400 kHz I C serial link (I C address is user-
selectable). The MOTION signal is asserted when the VD5377 senses motion and motion
2
X/Y data is accessed over the I C link. The user can choose between Automatic power
management mode, where the device will automatically go into low power hibernation if no
motion is detected or Manual power management mode where there is a choice of two low
power states: Standby or Powerdown. The external navigation LED driver is fully integrated
in the device, supporting drive currents up to 14 mA. Where higher power is required, an
external driver can be used.
Figure 1. VD5377 simplified system block diagram
2.2 to 3.0V
I2C
IR LED
Host MCU
VD5377
MOTION
POWERDOWN
STANDBY
LED_OUT
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Overview
VD5377
1.1
Technical specification
Table 1. Technical specification
Detail
Programmable up to 3200 cpi
Feature
Resolution
Pixel size
Array size
Frame rate
30.4 µm
20 x 20 pixels
Up to 4 kf/s (auto or manual)
Up to 720 mm/s (28 in/s)
low drift, high accuracy
Tracking performance
Supply voltage
2.2 V to 3.0 V using internal regulator or 1.8 V direct drive
-20°C to 70°C
Operating temperature
1.2
VD5377 enhancements
The VD5377 has been optimized for optical finger navigation (OFN) applications. For
applications migrating from the previous VD5376 device, the following list highlights the key
differences:
•
•
optimized floor plan for improved module design
enhanced automatic power management mode: fully programmable sleep and wake-
up intervals
•
•
•
•
•
•
•
•
•
•
•
ultra-low powerdown mode (<1 µA)
2
user-selectable I C addresses with the option to create custom start-up configurations
programmable polarity on external MOTION signal
power-on reset (POR) function gated on MOTION signal
unique Backlight controller: three PWM controlled LED drive outputs (10 mA)
enhanced performance in high ambient light conditions
new filter added to aid navigation in low contrast images
increased LED on-time for greater dynamic range
simplified support circuit: Rbin and Cosc components now integrated
smaller external capacitor on VREG (220 nF)
2
improved I C frame capture
8/88
Doc ID 022952 Rev 2
VD5377
Overview
1.3
Floor plan changes
Table 2. Die size and optical center comparison
VD5377
VD5376
Conditions
X (µm)
Y (µm)
X (µm)
Y (µm)
Including seal
1794
1758
1800
1832
Die size
Including scribe
(step & repeat)
1894
-83
1858
+447
1900
-91
1932
+319
Relative to die
center
Optical center
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Silicon specification
VD5377
2
Silicon specification
This chapter contains physical die information.
2.1
2.2
Silicon thickness
Standard silicon thickness is 180 µm (see Table 40: Delivery formats on page 86).
Die size and optical center
All dimensions and all coordinates are referenced to the origin at die center.
Table 3. Die size
Conditions
X size (µm)
Y size (µm)
Including seal
1794
1894
1758
1858
Including scribe (step and repeat)
Table 4. Optical center
Parameter
X (µm)
Y (µm)
Die center
0
0
Array center
-83
+447
2.3
Pad opening sizes
Table 5. Pad openings
X (µm)
Y (µm)
Size
86.4
86.4
Minimum bond pad pitch: 138 µm.
10/88
Doc ID 022952 Rev 2
VD5377
Silicon specification
2.4
Device pinout
Figure 2 shows the bond pad layout and Table 6 provides the bond pad coordinates. All
dimensions are in microns.
Figure 2. VD5377 bond pad layout
DVSS
I2C_SEL0
I2C_SEL1
I2C_SEL2
LED_OUT
DVSS
1
2
AVDD
AVSS
SCL
26
25
24
23
(0,0) 1st pixel
(0,19)
Imaging Array
3
608 µm
Array Centre
(-83, +447)
4
SDA
5
(19,19)
(19,0)
608 µm
6
22 TEST_CLK
Die Centre(0,0)
7
DVDD
21
20
19
DVSS
8
BACKLED0
BACKLED1
BACKLED2
MOTION
GPIO0
9
10
11
12
13
14
15
16
17
18
First pixel indicates start of
readout for image streaming.
NOT TO SCALE
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Silicon specification
VD5377
2.5
Bond pad coordinates
All dimensions are in microns. Bond pad coordinates correspond to the bond pad centers
referenced to the die center.
Table 6. Bond pad coordinates
X co-ordinate
Pad #
Pad name
Y co-ordinate
1
DVSS
I2C_SEL0
I2C_SEL1
I2C_SEL2
LED_OUT
DVSS
-827.6
-827.6
-827.6
-827.6
-827.6
-827.6
-827.6
-827.6
-827.6
-827.6
-649.8
-511.4
792.7
515.6
378.0
240.3
102.6
-35.0
2
3
4
5
6
7
DVDD
-218.8
-356.4
-494.1
-631.8
-810.1
-810.1
-810.1
-810.1
-810.1
-810.1
-810.1
-810.1
-632.3
-484.3
-336.1
-187.5
-10.3
8
BACKLED0
BACKLED1
BACKLED2
DVSS
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
DVDD
POWERDOWN
POR_TEST
VTOP
-317.5
-213.8
-110.1
28.3
STANDBY
DVREG
DVSS
470.1
649.6
827.6
827.6
827.6
827.6
827.6
827.6
827.6
827.6
GPIO0
MOTION
DVSS
TEST_CLK
SDA
SCL
145.4
556.0
733.4
AVSS
AVDD
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Doc ID 022952 Rev 2
VD5377
Application schematics
3
Application schematics
There are two power configurations for the VD5377: a 2.2 V to 3.0 V external supply utilizing
the device’s internal 1.8 V regulator or direct drive using an externally regulated 1.8 V
supply. Typical application schematics are shown for both configurations in Figure 3 and
Figure 4.
The internal 1.8 V core regulator requires a minimum 220 nF decoupling capacitor. Larger
values may increase the minimum power down time which is required to guarantee a proper
reset of the device.
Figure 3. VTOP supply (using internal regulator)
1.8V
1 DVSS
AVDD
AVSS
SCL
26
25
24
2
Optional I C
2 I2C_SEL0
3 I2C_SEL1
Address
Navigation
LED
SCL
SDA
4
5
6
7
8
9
I2C_SEL2
LED_OUT
DVSS
SDA 23
VD5377
NC
TEST_CLK
22
21
20
19
DVDD
DVSS
MOTION
GPIO0
BACKLED0
BACKLED1
MOTION
10 BACKLED2
11 12 13 14 15 16 17 18
NC
220 nF
1.8V
GND
STANDBY
POWERDOWN
VTOP
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Application schematics
VD5377
Figure 4. 1.8 V direct supply
1.8V
1 DVSS
2 I2C_SEL0
AVDD
AVSS
SCL
26
25
24
2
Optional I C
Address
3
4
5
6
7
8
9
I2C_SEL1
I2C_SEL2
LED_OUT
DVSS
Navigation
LED
SCL
SDA
SDA 23
VD5377
NC
TEST_CLK
22
DVDD
DVSS 21
BACKLED0
BACKLED1
20
19
MOTION
GPIO0
MOTION
10 BACKLED2
11 12 13 14 15 16 17 18
NC
220 nF
1.8V
1.8V
GND
STANDBY
VLED
Note:
In a 1.8 V direct drive configuration, the POWERDOWN pin should be connected to 1.8 V to
ensure the internal regulator is switched off to minimize power consumption.
3.1
Signal descriptions
Table 7. Signal descriptions
Pad #
Signal name
Type
Description
1
2
3
DVSS
Supply
Digital ground
2
I2C_SEL0
I2C_SEL1
1.8V digital input I C address select input.
5 V tolerant inputs with integrated pull-down resistor.
If unconnected default address is 0xA6.
1.8V digital input
1.8V digital input
(Pads have internal 35 kOhm pull-down resistors. If connected
to VDD, the pull-down resistor is disconnected after the internal
microcontroller boot sequence is completed to reduce power
consumption).
4
I2C_SEL2
Navigation LED drive pad. Constant current sink set by internal
5
LED_OUT
Current DAC output DAC. Maximum setting 14 mA. For external LED driver use
GPIO0.
6
7
DVSS
DVDD
Supply
Supply
Digital ground
1.8 V digital supply
14/88
Doc ID 022952 Rev 2
VD5377
Application schematics
Table 7. Signal descriptions (continued)
Pad #
Signal name
Type
Description
Backlight LED Driver (4 mA, open-drain). 5 V tolerant.
If unused, connect to DVSS.
8
BACKLED0
1.8V digital I/O
Backlight LED Driver (4 mA, open-drain). 5 V tolerant.
If unused, connect to DVSS.
9
BACKLED1
BACKLED2
1.8V digital I/O
1.8V digital I/O
Backlight LED Driver (4 mA, open-drain). 5 V tolerant.
If unused, connect to DVSS.
10
11
12
DVSS
DVDD
Supply
Supply
Digital ground
1.8 V digital supply
Active high. This disables the internal 1.8 V core regulator.
Input switching level is 0.8 V to be compatible with 1.8 V or
2.8 V signal.
13
14
POWERDOWN
POR_TEST
Analog input
-
No connect
Internal 1.8 V regulator supply input:
– 2.2 to 3.0 V for internal regulator configuration
– 1.8 V in direct drive mode.
15
VTOP
Supply
If use_standby_pin register is selected (register 0x5 bit 4):
– In manual mode STANDBY = 1 puts the device in low power
mode
– In auto mode STANDBY = 1 disables I2C
16
STANDBY
1.8V digital input
Otherwise, connect to DVSS if not used.
This pad is 5 V tolerant.
1.8V internal regulator output. Connect to DVDD and AVDD
supplies. Requires a 220 nF capacitor to DVSS.
17
18
19
DVREG
DVSS
Supply
Supply
Digital ground
External LED drive control signal or general purpose I/O.
Referenced to Vtop. This pad is 5 V tolerant.
GPIO0
3.0V digital I/O
Motion detection flag.
Configurable as Push/Pull or open-drain.
Active high or low (programmable polarity).
Referenced to Vtop. This pad is 5 V tolerant.
20
MOTION
3.0V digital output
21
22
DVSS
Supply
-
Digital ground
No connect
TEST_CLK
2
I C bidirectional data (open-drain).
This pad is 5 V tolerant.
23
24
SDA
SCL
1.8V digital I/O
I2C clock.
1.8V digital input
This pad is 5 V tolerant.
25
26
AVSS
AVDD
Supply
Supply
Analog ground
1.8 V analog supply
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Application schematics
VD5377
3.2
Cursor orientation
Figure 5 shows the direction of positive motion vectors relative to silicon orientation with the
default power-up register settings: parameters_2 (0x27) = 0x08 that is, invert_x = 0,
invert_y = 0 and swap_xy = 1. An imaging lens is assumed but not shown. The direction of
X/Y motion can be reversed or swapped by writing to register 0x27 allowing preferred cursor
movement from any die orientation.
Figure 5. VD5377 default XY orientation
Y+
Pixel array
Pad 1
X+
Imaging lens not shown
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VD5377
System overview
4
System overview
The VD5377 operates in one of two power management modes: MANUAL or AUTOMATIC
(see Figure 6). After initial MCU BOOT the device enters the SW STBY state and waits for
configuration from the host. When configured, the device enters MANUAL RUN or
AUTOMATIC RUN mode.
•
MANUAL power management mode is the simplest mode where the host initializes the
device which then remains in MANUAL RUN mode until it receives a command to
change mode (either an I C command to return to the SW STBY state or a low power
2
state using the POWERDOWN or STANDBY pin).
•
AUTOMATIC power management mode is an intelligent, power efficient mode where
the device automatically switches to low power mode depending on motion activity.
When initialized, the device will continue to operate autonomously minimizing power
consumption and host CPU overhead.
Figure 6. VD5377 power management modes
POWER UP
MCU BOOT
SW STBY
host_config_done = 1
automatic = 0
host_config_done = 1
automatic = 1
MANUAL
RUN
AUTOMATIC
RUN
host_config_done=0
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System overview
VD5377
4.1
MANUAL power management
Manual power mode is the basic mode of the VD5377. After initialization, the sensor
remains in MANUAL RUN mode even when no motion activity is detected. The host can use
the external POWERDOWN or STANDBY signals to achieve lower current consumption.
(a)
•
STANDBY pin (active high): if set, the system goes into low power STANDBY mode
at the end of the current frame. Typical power consumption in STANDBY mode is
shown in Table 8 on page 19. The internal clock and motion engine are switched off
2
and so the VD5377 does not respond to any I C communication and no motion activity
is detected. All register settings are maintained in this state, so when STANDBY is de-
asserted the system immediately resumes in RUN mode.
•
POWERDOWN pin: if set, this signal immediately disables the internal 1.8 V core
regulator. After power down, the system needs to be re-initialized. Power consumption
is typically <1 µA in this state.
Figure 7. Manual power mode flow diagram
POWER UP
MCU BOOT
POWERDOWN=0
host_config_done = 1
automatic = 1
SW STBY
host_config_done = 1
automatic = 0
MANUAL
RUN
AUTOMATIC
MODE
POWERDOWN=1
STANDBY=1
STANDBY=0
POWERDOWN
STANDBY
POWERDOWN=1
MANUAL POWER MODE
a. During initialization, the user must set the use_standby_pin register bit (system_config 0x05 bit 4) to 1 to
enable the STANDBY pin function otherwise it is ignored.
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VD5377
System overview
Table 8 summarizes the typical operating current in Manual mode.
(1)
Table 8. Typical power consumption - Manual mode
Run(2)
Standby
Power down
3k3 kf/s
2 kf/s
1 kf/s
10.2 mA
6.9 mA
4.5 mA
25 µA
<1 µA
1. Includes LED (maximum exposure)
2. Internal clock = 44 MHz; led_dac 14 mA; Maximum exposure
Figure 8 describes the power-up sequence of the VD5377.
Figure 8. Manual power mode timing diagram
VTop
DVDD/AVDD
POR
t1
System
Clock
t2
t2
Device Ready
MOTION (O)
STANDBY (I)
POWERDOWN (I)
I2C (I/O)
t4
host_config_done
System States
MANUAL
RUNNING
MANUAL
RUNNING
STANDBY
state
POWERDOWN
state
SW STDBY
MCU BOOT
t3
MCU BOOT
Power Up
Power Up
t5
STANDBY pin latency
up to 1 frame duration
Power Up
After the MCU boot sequence is completed, the system enters SW STDBY state and the
MOTION pin is set to 1 indicating that the device is ready to receive commands from the
2
host. After initialization by the host over I C, the device enters the MANUAL RUN state and
the MOTION pin goes low.
Note:
The MOTION pin polarity is programmable. If active low polarity is selected during
initialization, the MOTION pin will remain high.
If the STANDBY pin is asserted, the system completes the current frame operation before
entering the STANDBY state and stopping the internal system clock. When the STANDBY
pin is deasserted, the system clock is restarted and the device resumes in the RUN state
(no re-initialization required). If the POWERDOWN pin is asserted (active high), the internal
1.8 V regulator is disabled and the 1.8 V core supply is switched off. When the
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System overview
VD5377
POWERDOWN pin is deasserted, the internal 1.8 V regulator is re-enabled triggering a
POR (Power-On Reset) and the MCU re-initializes as at power-up before entering the SW
STBY state. The device must be re-configured after POWERDOWN.
Key timing parameters are shown in Table 9.
Table 9. Manual mode timing constraints
Symbol
Parameter
Typical
POR Delay
(POR threshold = 1.4 V typ)
t1
20 µs
t2
t3
Clock Startup
1 µs
450 µs
MCU boot time
t4
Minimum Powerdown time (220 nF regulator capacitor)
Standby pin latency (up to 1 frame at 1 kf/s)
10 ms
t5(1)
up to 1 ms
1. No I2C comms permitted to VD5377 after Standby pin asserted
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VD5377
System overview
4.2
AUTOMATIC power management
AUTOMATIC power mode is the advanced power saving mode of the VD5377. When this
mode is activated, the sensor automatically enters low power modes (called SLEEP states)
after a given time if the sensor does not detect any motion.
Figure 9. Automatic power mode flow diagram
POWER UP
BOOT
POWERDOWN=0
host_config_done = 1
automatic = 1
SW STBY
host_config_done = 1
automatic = 0
MANUAL
MODE
AUTOMATIC
RUN
50 ms
POWERDOWN=1
10 ms
SLEEP 1
POWERDOWN
8 secs
100 ms
Default sleep time-outs and
wakeup latencies are shown.
These parameters are
programmable.
SLEEP 2
10mins
500 ms
POWERDOWN=1
SLEEP 3
AUTOMATIC POWER MODE
A SLEEP state is a low power state where the internal system clock is disabled, the analog
block is powered down and only the internal 50 kHz oscillator is running to wake the sensor
up periodically. Each time the sensor wakes up, a single frame is captured and the motion
versus previous frame is estimated. If motion is detected the system resumes in RUN mode;
otherwise if no motion is detected the sensor goes back to SLEEP. Up to three SLEEP
states (default) can be selected. The sleep time-out and wake-up latency periods are
programmable.
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System overview
VD5377
In AUTOMATIC power mode, if the use_standby_pin register is set, the STANDBY pin is
2
configured as a chip select (active low) to perform I C communications. This allows the host
2
to perform I C communications to the VD5377 at anytime even during SLEEP modes. If the
2
use_standby_pin register is not set, the host can only perform I C communications when
motion data is pending.
Low power states:
•
•
SLEEP states: Typical power consumption in the various sleep states is shown in
Table 10.
POWERDOWN pin: if set, this signal immediately disables the internal 1.8 V core
regulator. After power down, the system needs to be re-initialized. Power consumption
is typically <1 µA in this state.
(1)
Table 10. Typical power consumption - automatic mode
Run(2)
Sleep1
Sleep2
Sleep3
Power down
3.3 kf/s
2 kf/s
1 kf/s
10.2 mA
6.9 mA
4.5 mA
350 µA
60 µA
20 µA
<1 µA
1. Includes LED (maximum exposure)
2. Internal clock = 44 MHz; led_dac 14 mA; Maximum exposure
Figure 10 describes the power-up sequence of the VD5377 in AUTOMATIC power
management mode. After the MCU boot sequence is completed, the system enters SW
STDBY state and the MOTION pin is set to 1 indicating that the device is ready to receive
2
commands from the host. After initialization by the host over I C, the device enters the
AUTO RUN state and the MOTION pin will go low.
Note:
The MOTION pin polarity is programmable. If active low polarity is selected during
initialization, the MOTION pin will remain high.
After a time, motion is detected and the MOTION PIN goes high. Once motion is detected
the device can no longer enter SLEEP until all pending motion data has been read. The host
2
deasserts the STANDBY pin to enable I C comms (if use_standby_pin register was set in
initialization routine); motion data is read and the STANDBY pin is re-asserted. After the
RunningTimeout period, if no further motion is detected, the device enters the SLEEP1
state. After the Sleep1Latency period, the device wakes up for 1 frame to detect any
movement. No motion is detected so the device remains in the SLEEP1 state.
If the POWERDOWN pin is asserted, the internal 1.8 V regulator is disabled and the 1.8 V
core supply is switched off. When the POWERDOWN pin is deasserted, the internal 1.8 V
regulator is re-enabled and the MCU re-initializes as at power-up before entering the SW
STBY state. The device must be re-configured after POWERDOWN.
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VD5377
System overview
Figure 10. Automatic power mode timing diagram (use_standby_pin=1)
VTop
DVDD/AVDD
POR
t1
t2
Osc
48 MHz
Osc
50 kHz
motion detected
Device Ready
MOTION (O)
STANDBY (I)
motion read
through I2C
with STANDBY
as Chip Select
POWERDOWN (I)
I2C (I/O)
t4
host_config_done
System States
AUTO
RUNNING
SLEEP1
state
POWERDOWN
state
SW STDBY
MCU BOOT
t3
MCU BOOT
Power Up
Power Up
Power Up
RunningTimeout Sleep1Latency
1 frame wake-up
duration
Key timing parameters are shown in Table 11.
Table 11. Automatic mode timing constraints
Parameter
Symbol
Typical
POR Delay
(POR threshold = 1.4 V typ)
t1
20 µs
t2
t3
t4
Clock Startup
1 µs
MCU boot time
450 µs
10 ms
Minimum Powerdown time
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I/O description
VD5377
5
I/O description
5.1
I2C_SEL[2:0]
2
The default I C address is 0xA6. However, in some applications the default address may
2
conflict with other I C devices sharing the bus or it may be necessary to chain multiple OFN
2
devices on the same bus. For that reason, the user can select from one of seven I C
addresses as shown in Table 12.
2
Table 12. User-selectable I C addresses
I2CSEL[2:0]
8-bit I2C address
000
001
010
011
100
101
110
111
0xA6
Reserved
0xC6
0xD6
0xE6
0x36
0x46
0x20
The I2C_SEL pads have internal pull-down resistors and can be left unconnected for the
default address. For any other address, connect pads that require a logic “1” to DVDD (the
internal pull-down resistor is automatically disconnected after the internal microcontroller
boot sequence is completed to conserve power).
If required, custom configurations can be stored in ROM on the device corresponding to a
2
particular I C address to reduce the number of required register writes by the host. If
interested in this feature, please contact STMicroelectronics.
2
The device I C address can also be configured dynamically by writing to register DEVADDR
2
(0x7c) bits [7:1] (see Table 13). This sets the 7-bit base I C address of the device and
allows multiple devices with the same default address to be re-mapped dynamically. This
operation must be done in 2 steps:
•
•
program register 0x7c using the current device address to program the new one
access registers with the new device address
Each device must be powered in turn to reconfigure its address and this operation must be
repeated each time the system is initialized.
2
Table 13. Control register to dynamically configure device I C address
Addr
(Hex)
Default
(Hex)
Register name
SIgnal name
Bit Type
Comment
i2cs_index_auto_inc_en
i2cs_dev_addr
0
PRW
01
53
Auto increment function
I2C device address
7c
DEVADDR
7:1 PRW
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I/O description
5.2
LED_OUT (tracking LED) and GPIO0
LED_OUT is controlled by a 3-bit current DAC (0x3 ANALOG_CTRL2 bits [6:4]) capable of
driving up to 14 mA (current sink). Where higher power output is required, an external LED
driver can be used controlled by GPIO0 (0x3 ANALOG_CTRL2 bit7 and 0xd GPIO_GPIO0
bit 4). Figure 11 shows the two LED drive options. LED pulse timing is controlled
automatically (see Figure 12). GPIO0 can also be used as a general purpose I/O and is
configured using register 0xd GPIO_GPIO0 bit 4. A typical configuration of a GPIO is shown
in Figure 13 on page 27.
Figure 11. LED drive options
LED with external driver
VTOP
LED driven by internal DAC
VTOP
LED
LED
LED_OUT
VD5377
GPIO0
VD5377
Figure 12. LED control
1 Frame = 1ms (1kHz) / 500µs (2kHz) / 250µs (4kHz)
Short
Exposure
86 µs (Max)
Long
Exposure
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I/O description
Addr
VD5377
Table 14. Control register for LED_OUT and GPIO0
Default
Register name
SIgnal name
Bit Type
Comment
(Hex)
(Hex)
Adjust Led Drive DAC drive
output current.
0 = Iout = 0 mA
1 = Iout = 2.0 mA
2 = Iout = 4.0 mA
3 = Iout = 6.0 mA
4 = Iout = 8.0 mA
5 = Iout = 10.0 mA
6 = Iout = 12.0 mA
7 = Iout = 14.0 mA (default)
led_dac_control
6:4 PRW
07
3
ANALOG_CTRL2
LED_OUT_EN polarity
led_out_polarity
gpio_gpio0_en
7
0
PRW
PRW
01
00
0 = High when LED must be ON
1 = Low when LED must be ON
GPIO0 output enable (active low)
0 = PAD configured as OUTPUT
1 = PAD configured as INPUT
GPIO0 data output
(when _en = 0)
gpio_gpio0_a
gpio_gpio0_zi
1
2
PRW
PR
00
00
GPIO0 IO value
GPIO0 data output select, either
as LED_OUT_EN or from register
bank.
d
GPIO_GPIO0
gpio_gpio0_a_ctrl
4
7
PRW
PRW
00
00
0 = Output value from HW
register
1 = LED_OUT_EN (polarity set in
register 0x3 analog_ctrl2 bit 7)
GPIO0 pad open drain control
0 = GPIO0 pad normal config
gpio_gpio0_opendrain
1 = GPIO0 pad in open drain
(A=EN)
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I/O description
Figure 13. Typical configuration of GPIO
Register Bank
gpio_opendrain
gpio_en
0
1
IO pad
gpio_a_ctrl
EN
A
IO
gpio_a
0
1
ZI
Input
Digital Logic
led_ctrl
Table 15. Truth-table
gpio_a or led_ctrl
gpio_opendrain
gpio_en
Condition
Output
0
0
0
1
1
0
0
0
1
X
0
1
Output
Output
0
1
1
Input
-
0
X
X
Open-drain
Open-drain
Tri-state
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I/O description
VD5377
5.3
MOTION
The MOTION pad is a 3.0 V digital I/O pad referenced to VTOP and can be configured
either as a push/pull output or open-drain. It combines the functions of motion pending flag
and power-on reset indicator (see Figure 14). The MOTION signal is driven low at power-up
and stays low until the internal MCU boot sequence is completed. Once the boot sequence
is completed the MOTION signal goes high and remains high until the device is configured
and enters the AUTOMATIC or MANUAL RUN state. Thereafter the level on the MOTION
pad depends on the MOTION pin polarity setting (register 0x5 SYSTEM_CONFIG bit 2).
Note:
In Powerdown, a 35 kOhm pull-down resistor is activated in the Motion pad. This may result
in leakage current in the external circuit. Also, in open-drain configuration, careful choice of
pull-up resistor is required to ensure the resultant intermediate voltage on the Motion pad
does not induce leakage current in the Motion input gate.
Figure 14. MOTION behavior at power-up
POR
MOTION
MCU BOOT
Power Up
SW STDBY
AUTO RUN or MANUAL RUN
STATE
Table 16. Control register for motion pin polarity
Default
Addr
(Hex)
Register name
SIgnal name
Bit Type
Comment
(Hex)
Power mode scheme
0 = Manual
automatic_power_mode
0
PRW
01
1 = Automatic
MOTION pin polarity (in non
IDLE system state)
0 = MOTION pin LOW when
motion detected
motion_pin_polarity
host_config_done
2
3
PRW
PRW
00
00
1 = MOTION pin HIGH when
motion detected
Bit needs to be set by host
when configured after power
up.
5
SYSTEM_CONFIG
STANDBY pin is used as chip
select to enable I2C in AUTO
power mode and STANDBY pin
is used to wake up the
OSC/DVREG (in sleep states in
auto power mode).
use_standby_pin
system_state
4
PRW
01
01
0 = STANDBY pin not used
1 = STANDBY pin is used
Legacy register - please use
system_state (0x91) instead.
7:5 RW
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I/O description
Table 16. Control register for motion pin polarity (continued)
Default
Addr
(Hex)
Register name
SIgnal name
Bit Type
Comment
(Hex)
MOTION output enable (active
low)
gpio_motion_en
0
PRW
00
0 = PAD configured as
OUTPUT
1 = PAD configured as INPUT
MOTION data output
(when _en = 0)
gpio_motion_a
gpio_motion_zi
1
2
PRW
PR
01
01
MOTION IO value
MOTION pull-down control
(internal 35 kOhms pull-down
resistor) - active LOW
gpio_motion_pd
3
4
PRW
PRW
01
00
0 = IO is pulled down
1 = IO not pulled down
c
GPIO_MOTION
MOTION data output origin
0 = Output value from HW
register
gpio_motion_a_ctrl
1 = Output value from motion
detect IP
Reserved
6:5 PRW
02
00
Reserved
MOTION pad open drain control
0 = MOTION pad normal config
gpio_motion_opendrain
7
PRW
1 = MOTION pad in open drain
(A = EN)
5.4
STANDBY
The STANDBY pad is a 1.8 V digital input (active high/ 5 V tolerant). In MANUAL RUN
mode, if STANDBY is asserted the device enters a low power STANDBY state at the end of
the current frame (see Figure 7: Manual power mode flow diagram on page 18). When
STANDBY is de-asserted the device resumes in RUN mode without requiring re-
initialization.
2
In AUTOMATIC RUN mode, the STANDBY pin acts as a I C enable (see Figure 15). When
2
2
STANDBY = 0, I C is enabled and the VD5377 will respond to I C communication from the
host in either RUN or any of the SLEEP states. When STANDBY = 1 the VD5377 consumes
2
less power but will not respond to I C communication. In order to use the STANDBY pin in
AUTOMATIC mode the use_standby_pin (register 0x5 SYSTEM_CONFIG bit 4 in Table 17:
Features and scaling on page 32) must be set during system initialization. If this function is
not required, the use_standby_pin register should be set to 0 and the STANDBY pad should
be connected to either VDD or VSS.
2
Note:
If use_standby_pin = 1, the STANDBY pin must be set to 0 before each I C transaction even
if motion data is pending.
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I/O description
VD5377
2
Figure 15. In AUTOMATIC mode the STANDBY pin functions as I C enable if
use_standby_pin is selected
MOTION
Internal Osc
STATE
STANDBY
I2C Comms
RUN
SLEEP
RUN
Minimum time = 10 us
5.5
POWERDOWN
POWERDOWN is a 3.0 V capable analog input pad referenced to Vtop. The input switching
level is 0.8 V and is compatible with 1.8 V and 2.8 V systems. When POWERDOWN is set
to 1 the core 1.8 V digital supply is switched off. The device typically consumes <1 µA in this
(a)
state . When POWERDOWN is set to 0, the internal 1.8 V core regulator is enabled and
the power-up sequence is initiated (see Figure 8: Manual power mode timing diagram on
page 19). The device requires full re-initialization after POWERDOWN.
Note:
In a 1.8 V direct drive configuration where the internal regulator is not used, the
POWERDOWN pin should be connected to VDD to ensure the regulator is disabled (see
Figure 4: 1.8 V direct supply on page 14).
a. See the note in Section 5.3: MOTION on page 28.
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Key features
6
Key features
This chapter gives an overview of some of the most important registers and functions.
6.1
Feature count
Feature count is a measure of the useful detail in an image which is used to match
successive frames. Generally, the higher the feature count the better the tracking. The
FEATURES register (0x31) in Figure 17 is an 8-bit value representing the 8 MSBs of a 12-bit
internal register. A maximum value of 255 represents a feature count of 16 x 255 = 4080. A
reasonable average target feature count is around 2000. Feature counts averaging less
than 1000 are likely to result in missing counts and sluggish navigation. This is usually as a
result of low contrast in the image or significant vignetting due to the lens.
Note:
On some textured surfaces the feature count may exceed 4080. When this occurs the
FEATURES register clips at 255. This is normal and does not affect tracking.
6.2
Minimum features threshold
Without any object on the sensor the feature count will be non-zero, typically around 200.
This residual value is usually due to the characteristics of the lens and/or pixel noise but
may also be caused by internal or external light reflection which can sometimes result in
unintentional cursor movement (or jitter). To prevent this unwanted movement, the motion
engine is inhibited until the feature count register exceeds the value in the MIN_FEATURES
register (0x29). Multiply the register value by 16 to get the actual feature count threshold.
Default value is 16d x 16 = 256.
6.3
X/Y scaling
The VD5377 outputs a single count for each one pixel displacement of the object. The
physical dimension of one pixel is 30 µm. The actual displacement depends on the
magnification of the lens used. For a lens of magnification M = 0.5 one pixel displacement
equates to 60 µm physical displacement of the object.
Cursor movement is typically expressed in Counts or Dots per Inch (CPI or DPI). In this
case (M = 0.5):
Counts per Inch = 25.4mm/60µm = 423 CPI
The X/Y scaling registers (Table 17: Features and scaling on page 32) can be used to
increase or decrease the native CPI according to the following equation:
Counts per Inch = register_value x M x 100
Scale factors can be applied to X and Y independently to compensate for any lens
distortion.
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Key features
Addr
VD5377
Table 17. Features and scaling
Default
Register name
Signal name
Bit Type
Comment
(Hex)
(Hex)
This register represents the
minimum feature count below which
motion is inhibited. Multiply by 16 to
get the actual feature count
threshold. Default is 16d x 16 =
256.
29
MIN_FEATURES
min_features
7:0 PRW
10
Scaling for X motion vectors.
Resolution is calculated as register
value x 100 x M, where M is the
lens magnification.
2a
X_SCALING
motion_x_scaling
7:0 PRW
10
So, for M = 0.5:
0x08 = 400 CPI that is 8 x 100 x 0.5
0x0c = 600 CPI that is 12 x 100 x
0.5
Scaling for Y motion vectors.
Resolution is calculated as register
value x 100 x M, where M is the
lens magnification.
2b
31
Y_SCALING
FEATURES
motion_y_scaling
7:0 PRW
10
00
So, for M = 0.5:
0x08 = 400 CPI that is 8 x 100 x 0.5
0x0c = 600 CPI that is 12 x 100 x
0.5
Feature count report, as the SUM of
absolute differences between pixels
and the field average. Bits [11:4] are
represented here so x16 to
features_report
7:0 PR
calculate the actual feature count.
Maximum value is 4080 = 255 x 16.
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Key features
6.4
Automatic exposure control
Figure 16 describes the automatic exposure control function. This routine is performed
every EXPO_FRAME_UPDATE (register 0x4B).The auto-exposure control algorithm works
(a)
by adjusting exposure until the brightest (max exposed ) pixel in the frame lies within a
specified target range. This is to ensure that no part of the frame is saturated.
Figure 16. Automatic exposure algorithm
START
Programmable parameters shown in red
No
MEP = 255?
Yes
No
MEP > MEP_HighT
Expo = Min(0,
Expo - SatDecStep)
Yes
No
MEP < MEP_LowT
Expo = Min(0,
Status = SATURATED
Expo - DecStep)
Yes
Expo = Max(255,
Expo + IncStep)
Status = HIGH
(overexposed)
Status = LOW
(underexposed)
Status = STABLE
No
Expo > ExpoMax
Yes
No
Expo < ExpoMin
Expo = ExpoMax
Yes
Expo = ExpoMin
LimitFlag = 1
END
Manual or automatic exposure control can be selected. This is controlled using register
EXPOSURE_CONTROL 0x43 bit 0 (see Table 18). Bits [6:4] give the exposure status and
bit 7 is the exposure limit flag. In automatic exposure control mode, register EXPOTIME
a. In fact the second brightest pixel is used. Note that AEC operates on the exposed frame, that is, before noise
cancellation. Processing is done on the CDS frame which is derived from the exposed frame as follows:
CDS frame = Exposed frame - Black frame + 8
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Key features
VD5377
0x47 gives the current exposure time. This register is also used to enter the required
exposure time in manual exposure mode. Register 0x44 is the MAX_EXPO_PIX (read-
only).
Registers 0x45/0x46 are the upper and lower exposure targets (180 to 240 by default).
When the MEP is within this range the exposure is judged to have “converged” and no
further exposure updates are required until the MEP moves outside the target range. It is not
normally required to adjust the exposure targets.
The default exposure range is 1 to 255. These limits are programmable with registers
0x49/0x4a.
By default, exposure update rate is every two frames. This can be adjusted using register
0x4b. Exposure convergence can be modified by changing the exposure
increment/decrement step sizes with registers 0x4e/0x4f/0x50.
Table 18. Exposure control
Default
Addr
(Hex)
Register name
Signal name
Bit
Type
Comment
(Hex)
Auto exposure control
0 = Disable
autoexpo_en
0
RW
01
1 = Enable
Auto exposure status
0 = UNDEF (no AEC
performed yet)
1 = LOW (exposure
increasing)
autoexpo_status
6:4
R
00
2 = STABLE (max exposed
pixel within range)
43
EXPOSURE_CONTROL
3 = HIGH (exposure
decreasing)
4 = SATURATED (exposure
saturation decreasing)
Exposure limit reached flag
0 = Exposure time within
range
autoexpo_limit_flag
7
R
00
1 = Exposure time limit
reached
Second maximum pixel value
of the current frame (before
CDS)
max_exposed_pixel_v
alue
44
45
MAX_EXPO_PIX
7:0 PR
7:0 RW
00
f0
High threshold value of max
exposed pixel where the AEC
is stable.
MAX_EXPO_PIX_THRE max_exposed_pixel_t
SH_HIGH hresh_high
Low threshold value of max
exposed pixel where the AEC
is stable.
MAX_EXPO_PIX_THRE max_exposed_pixel_t
46
47
7:0 RW
b4
40
SH_LOW
hresh_low
Exposure time value in 3 MHz
clk period step (333ns)
EXPOTIME
exposure_time
7:0 PRW
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Key features
Table 18. Exposure control (continued)
Addr
(Hex)
Default
(Hex)
Register name
Signal name
Bit
Type
Comment
Maximum exposure time
applied by the AEC.
49
4a
EXPOTIME_MAX
EXPOTIME_MIN
exposure_time_max
exposure_time_min
7:0 RW
7:0 RW
ff
Minimum exposure time
applied by the AEC.
01
Exposure update frequency
(every N+1 frames). Default is
every two frames.
EXPO_FRAME_UPDAT autoexpo_frame_upda
te
4b
4e
4f
7:0 RW
7:0 RW
7:0 RW
01
04
04
E
Exposure increment step
(used when below
max_expo_pix_thresh_low).
EXPOTIME_INC_STEP expo_inc_step
EXPOTIME_DEC_STEP expo_dec_step
Exposure decrement step
(used when above
max_expo_pix_thresh_high).
Exposure decrement step
(used when above
max_expo_pix is
EXPOTIME_SAT_DEC_
expo_sat_dec_step
STEP
50
7:0 RW
10
saturated = 255).
6.5
5 x 5 high pass filter
Before each frame is processed the image data is passed through a high-pass filter to
extract edge information. The PARAMETERS_3 register 0x28 bit 5 (Table 19) permits
selection between two high pass filter options. 3 x 3 is the default high-pass filter. The
alternative 5 x 5 high-pass filter has a lower cut-off frequency and so preserves more
information in lower contrast images. This may help improve tracking performance in some
situations, although a possible effect is an increase in hover (this can be overcome by
increasing min_features threshold, register 0x29).
Table 19. 5x5 high-pass filter register
Default
Addr
(Hex)
Register name
SIgnal name
Bit
Type
Comment
(Hex)
Reserved
3:0
4
PRW
04
01
Reserved
Reserved
Reserved
hpf_5x5_sel
Reserved
PRW
PRW
PRW
Select between 3 x 3 and 5 x 5
high pass filter.
28
PARAMETERS_3
5
6
00
01
0 = 3 x 3 high pass filter
1 = 5 x 5 high pass filter
Reserved
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Key features
VD5377
6.6
Sunlight timing
In applications where strong external ambient lighting could interfere with tracking such as
direct sunlight, “Sunlight DMIB timing” mode is recommended (0x51 bit 1 = 1). This can
either be set to always on, that is 0x51 = 0x2 or set to change automatically when the
sensor detects high ambient light conditions (that is, 0x51 = 0x1). See Table 20. The default
is “Normal DMIB timing” mode.
Note:
The maximum permitted frame rate in Sunlight timing mode is 3.3 kf/s (see Section 6.7:
Automatic/manual frame rate).
Table 20. Sunlight DMIB timing mode
Default
Addr
(Hex)
Register name
Signal name
Bit
Type
Comment
(Hex)
DMIB controller timing switch
mode
0 = Manual (chosen by
dmib_timing register)
dmib_ctrl_mode
0
RW
00
1 = Automatic (system auto
sets the dmib_timing mode,
status reported in dmib_timing
register)
51
CONTROL
DMIB controller timing mode
0 = Normal DMIB timing (same
as 376 with double expo time
possible)
dmib_timing
Reserved
1
7
PRW
PRW
00
00
1 = Sunlight DMIB timing
Reserved
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Key features
6.7
Automatic/manual frame rate
The VD5377 can operate in either automatic or manual frame rate control mode. The default
frame rate control mode is automatic (see Table 21, register 0x1c bit 4). This means that the
device adjusts frame rate automatically depending on the tracking velocity. By default, frame
rate is adjusted in the range 1 k to 2 k to Max. Because power consumption increases as
frame rate increases, automatic frame rate control is the most efficient in terms of power
consumption and requires no additional overhead from the host CPU. The maximum frame
rate to be applied in auto frame rate mode is set with register 0x1c bits 7:5. The default
maximum frame rate is 3.3 kf/s. Manual frame rate is selected with register 0x1c bits [2:0].
Table 21. Adaptive frame rate control
Default
Addr
(Hex)
Register name
Signal name
Bit
Type
Comment
(Hex)
Frame rate selection (value for
internal osc running @48 MHz)
0 = 0.5kf/s (2 ms period)
1 = 1 kf/s (1 ms period)
2 = 2 kf/s (500 us period)
3 = 2.5kf/s (400 us period)
4 = 2.9kf/s (350 us period)
5 = 3.3kf/s (300 us period)
6 = 3.6kf/s (275 us period)
7 = 4 kf/s (250 us period)
frame_rate_sel
2:0
PRW
02
Frame rate management control
0 = Automatic (1 k / 2 k / Max f/s
auto frame rate)
FRAME_RATE_CONT
ROL
1c
frame_rate_ctrl
4
RW
00
1 = Manual (set with
frame_rate_sel reg)
Maximum frame rate to be applied
in auto frame rate mode.
0 = not allowed
1 = not allowed
2 = 2 kf/s (500 us period)
3 = 2.5 kf/s (400 us period)
4 = 2.9 kf/s (350 us period)
5 = 3.3 kf/s (300 us period)
6 = 3.6 kf/s (275 us period)
7 = 4 kf/s (250 us period)
max_auto_frame_r
ate
7:5
RW
05
Due to CPU bandwidth limitations of the on-board MCU, maximum frame rate is limited to
3.3 kf/s in sunlight timing mode. In Normal DMIB timing mode only (default mode - register
0x51 = 0), the maximum frame rate may be increased up to 4 kf/s but in order to meet
internal timing constraints, the maximum exposure time (EXPOTIME_MAX 0x49) needs to
be reduced according to Table 22. The motion_threshold_low_comp (SPARE 0x32) should
also be updated.
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Key features
VD5377
Table 22. Modified exposure limits
Frame rate control mode
Automatic
Manual
Maximum frame rate
Maximum exposure
3.3 kf/s
255
3.6 kf/s
232
4 kf/s
157
3.3 kf/s
255
3.6 kf/s
249
4 kf/s
174
Table 23. Motion threshold
Addr
(Hex)
Default
(Hex)
Register name
SIgnal name
Bit
Type
Comment
Reserved
0
1
RW
00
00
Reserved
Reserved
Reserved
RW
RW
Update motion_threshold_low
register for adaptive frame rate:
32
SPARE
motion_threshold_l
ow_comp
0 = 4 kf/s
7:4
03
2 = 3.6 kf/s
3 = 3.3 kf/s
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Additional features
7
Additional features
7.1
Auto-movement filter
An auto-movement filter has been added in VD5377 rev 2.0 to enhance the navigation
performance in high ambient light conditions.
(b)
The filter can only be enabled in automatic power mode . On initial wakeup, after sleep,
the filter will hold the sensor in the lowest run state until motion is seen is X times in Y
period. Both X and Y are programmable.
With the default settings, the AMF will look for motion in three separate 7 ms periods. Once
motion is seen in one 7 ms period, the filter will immediately move onto the next 7 ms
period.
Table 24. Auto-movement filter
Default
Addr
(Hex)
Register name
Signal name
Bit
Type
Comment
(Hex)
Auto movement filter enable
0 = Disable
bAutoMoveFilterEn
able
0
RW
00
1 = Enable
Number of frames on which the
auto movement filter is applied
(must be greater than 1).
ucAutoMoveFilterFr
ameNb
6:1
7
RW
RW
07
00
AUTO_MOVEMENT_
CTRL1
8d
When image in high light and
exposure (reg 0x47) is set to 1,
flag used by engine to discard
motion in this condition.
bAutoMoveSaturate
dExpo
0 = Disable
1 = Enable
b. Automatic power mode without standby (SYSTEM_CONFIG 0x5 = 0x09) does not function correctly when the
auto-movement filter is enabled. Suggested workaround is to use automatic power mode with use_standby_pin
enabled. Alternatively, there is a firmware patch available which can be requested from STMicroelectronics.
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Additional features
Addr
VD5377
Table 24. Auto-movement filter (continued)
Default
Register name
Signal name
Bit
Type
Comment
(Hex)
(Hex)
Latency between frames on which
the auto movement filter is
applied.
0 = 400 us
1 = 1 ms
2 = 1.4 ms
3 = 2 ms
4 = 4 ms
5 = 10 ms
6 = 20 ms
7 = 50 ms
8 = 100 ms
9 = 150 ms
10 = 200 ms
11 = 500 ms
12 = 1 s
ucAutoMoveFilterL
atency
3:0
RW
01
AUTO_MOVEMENT_
CTRL2
8e
13 = 1.5 s
14 = 2 s
15 = 2.6 s
Set the number of sequences to
detect motion to grant motion in
sleep mode.
ucAutoMoveFilterL
oop
7:4
RW
03
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Additional features
7.2
Adaptive CPI
To be able to cope with large screen resolution an adaptive CPI functionality has been
implemented in VD5377, where the motion scaling can be adjusted depending on the speed
of the detected motion.
The algorithm is shown in Figure 17 where maximum motion is max_abs_motion (register
0x2f).
Figure 17. Adaptive CPI algorithm
motion scaling
(CPI)
24
adaptcpi_log_scaling_range
reg 0x37 [6:4]
24=16
adaptcpi_min_scaling
8
reg 0x36
max_motion
(1 pixel/32)
16
adaptcpi_min_motion
reg 0x35
48
25=32
legend
blue: adaptive CPI register control
purple: default values
adaptcpi_log_motion_range
reg 0x37 [2:0]
Table 25. Adaptive CPI
Addr
(Hex)
Default
(Hex)
Register name
Signal name
Bit
Type
Comment
If set, the CPI is function of the
detected motion.
23
OVERFLOW
adapt_cpi_en
6
PRW
00
0 = No adaptive CPI
1 = Enable adaptive CPI
Max(ABS(X motion), ABS(Y
motion)) either from integrated or
instant motion
2f
MAX_ABS_MOTION max_abs_motion
6:0
7:0
7:0
PR
00
10
08
Minimum value of max(|X frame
motion|, |Y frame motion|) from
which the CPI is adaptive (if
ADAPTCPI_MIN_
MOTION
adaptcpi_min_
motion
35
36
PRW
PRW
feature enabled) - multiply by 1/32
Minimum motion scaling value
when adaptive CPI feature is
enabled.
ADAPTCPI_MIN_
SCALING
adaptcpi_min_
scaling
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Additional features
Addr
VD5377
Table 25. Adaptive CPI (continued)
Default
Register name
Signal name
Bit
Type
Comment
(Hex)
(Hex)
Log value of motion range from
which the CPI is adaptive (that is
max motion = min +
2^adaptcpi_log_motion_range)
0 = motion range = 1
1 = motion range = 2
2 = motion range = 4
3 = motion range = 8
4 = motion range = 16
5 = motion range = 32
6 = motion range = 64
7 = motion range = 128
adaptcpi_log_
motion_range
2:0
PRW
05
37
ADAPTCPI_RANGES
Log value of motion scaling range
from which the CPI is adaptive
(that is max scaling = min +
2^adaptcpi_log_scaling_range)
0 = scaling range = 1
1 = scaling range = 2
2 = scaling range = 4
3 = scaling range = 8
4 = scaling range = 16
5 = scaling range = 32
6 = scaling range = 64
7 = scaling range = 128
adaptcpi_log_
scaling_range
6:4
PRW
04
7.3
BACKLED[2:0]
Three pads are provided to optionally drive up to three backlight LEDs. Each pad is a 4 mA
(current limited), digital I/O with open-drain capability which can drive up to three LEDs
independently or can be combined to drive a single LED up to 12 mA (see Figure 18.). Each
output can be controlled by an independent PWM controller to provide a versatile dimming
function. When combined, all three pads are driven by PWM0. The PWM signals are
automatically gated during pixel integration to ensure there is no light pollution of the
tracking function. BACKLED control registers are shown in Table 26. These pads can also
be used as GPIO.
Note:
The BACKLED[2:0] pads are tri-state by default and should be connected to ground if not
used.
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Additional features
Figure 18. BACKLED configuration
VTOP
VTOP
VD5377
VD5377
BACKLED0
BACKLED1
BACKLED2
BACKLED0
BACKLED1
BACKLED2
Single backlight LED scheme
x3 backlight LED scheme
Table 26. BACKLED control registers
Addr
(Hex)
Default
(Hex)
Register name
SIgnal name
Bit
Type
Comment
BACKLED0 output enable (active
low)
gpio_backled0_en
gpio_backled0_a
0
1
PRW
PRW
00
0 = PAD configured as OUTPUT
1 = PAD configured as INPUT
BACKLED0 data output (when
_en = 0)
01
gpio_backled0_zi
gpio_backled0_tm
2
3
PR
01
00
BACKLED0 IO value
PRW
Reserved. Do not modify this bit.
9
GPIO_BACKLED0
BACKLED0 data output origin
gpio_backled0_a_
ctrl
0 = Output value from HW
register
4
7
PRW
PRW
00
01
1 = Output value from PWM 0
BACKLED0 pad open drain
control
gpio_backled0_
opendrain
0 = BACKLED0 pad normal config
1 = BACKLED0 pad in open drain
(A=EN)
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Additional features
Addr
VD5377
Table 26. BACKLED control registers (continued)
Default
Register name
SIgnal name
Bit
Type
Comment
(Hex)
(Hex)
BACKLED1 output enable (active
low)
gpio_backled1_en
gpio_backled1_a
0
1
PRW
PRW
00
0 = PAD configured as OUTPUT
1 = PAD configured as INPUT
BACKLED1 data output (when
_en = 0)
01
gpio_backled1_zi
gpio_backled1_tm
2
3
PR
01
00
BACKLED1 IO value
PRW
Reserved. Do not modify this bit.
BACKLED1 data output origin
a
GPIO_BACKLED1
gpio_backled1_a_
ctrl
0 = Output value from HW
register
4
7
PRW
PRW
00
01
1 = Output value from PWM 1
BACKLED1 pad open drain
control
gpio_backled1_
opendrain
0 = BACKLED1 pad normal config
1 = BACKLED1 pad in open drain
(A = EN)
BACKLED2 output enable (active
low)
gpio_backled2_en
gpio_backled2_a
0
1
PRW
PRW
00
01
0 = PAD configured as OUTPUT
1 = PAD configured as INPUT
BACKLED2 data output (when
_en = 0)
gpio_backled2_zi
gpio_backled2_tm
2
3
PR
01
00
BACKLED2 IO value
PRW
Reserved. Do not modify this bit.
BACKLED2 data output origin
b
GPIO_BACKLED2
gpio_backled2_a_
ctrl
0 = Output value from HW
register
4
7
PRW
PRW
00
01
1 = Output value from PWM 2
BACKLED2 pad open drain
control
gpio_backled2_
opendrain
0 = BACKLED2 pad normal config
1 = BACKLED2 pad in open drain
(A = EN)
PWM period duration (20 us tick
period)
f
PWM_PERIOD
pwm_period
7:0
7:0
7:0
7:0
PRW
PRW
PRW
PRW
ff
PWM 0 pulse high duration (20 us
tick period) - 0 = disable
10
11
12
PWM_PULSEHIGH0 pwm_pulse_high0
PWM_PULSEHIGH1 pwm_pulse_high1
PWM_PULSEHIGH2 pwm_pulse_high2
00
00
00
PWM 1 pulse high duration (20 us
tick period) - 0 = disable
PWM 2 pulse high duration (20 us
tick period) - 0 = disable
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Additional features
Comment
Table 26. BACKLED control registers (continued)
Default
Addr
(Hex)
Register name
SIgnal name
Bit
Type
(Hex)
BACKLED PWM enable
bBackLightEnable
0
RW
00
0 = Disable
1 = Enable
Single BACKLED scheme control
par PWM0 only
bSingleBackled
bPwmPolarity
1
2
3
RW
RW
RW
00
00
00
0 = 3 independent BackLEDs
1 = BackLED controlled by PWM
0
BACKLED PWM signal polarity
0 = High when LED must be ON
(=pwm0)
1 = Low when LED must be ON
(=!pwm0)
BACKLIGHT_
CONTROL
83
Enable the gating of BACKLED
PWM signal with DMIB gater
signal
bBackledGaterEna
ble
0 = Disable
1 = Enable
Enable the hold mechanism when
DMIB gater signal is ON
bPwmHoldEnable
bBackLightReset
4
7
RW
00
00
0 = Disable
1 = Enable
In SW STBY, reset the control of
backlight control (self cleared)
RWC
0 = Disable
1 = Enable
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Additional features
VD5377
7.3.1
PWM operation
The following list is a summary of PWM operation (Figure 19).
•
The PWM block is clocked by the internal 50 kHz oscillator which means in STANDBY
state in MANUAL power mode and in SLEEP states in AUTOMATIC power mode the
backlight LEDs are still running.
•
•
•
Maximum LED period is 5.12 ms (256 x OSC50K clock period).
Programmable pulse width (from 0 to 5.12 ms).
BACKLED pulses can be “gated” or “delayed” during the tracking LED “on” time to
avoid interference with the tracking function. This should not be required if the
BACKLED are shielded.
Note:
No test is performed on pulsehigh value versus period value so the host must ensure that
pulsehigh < period.
Figure 19. PWM operation: three independent PWM channels
backled_en
Osc
50kHz
pwm0
pwm1
pulsehigh0
period
pulsehigh1
period
pwm2
pulsehigh2
period
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Basic start-up information
8
Basic start-up information
8.1
Register override
To ensure correct operation over the device operating temperature range (see Table 34:
Operating conditions on page 61) it is recommended to make the single register override
specified in Table 27 as part of the user initialization of the device in sw_standby.
Table 27. Analog_ctrl2 recommended setting
Addr
(Hex)
Default
setting (Hex)
Recommended
setting
Register name
Description
Bits [3:2] DMIB DAC Vref setting =
1.6V
3
ANALOG_CTRL2
0xf4
0xfc
8.2
Recommended start-up settings
The VD5377 needs to be initialized after power-up. The only required register write is
host_config_done = 1 (SYSTEM_CONFIG 0x5 bit 3). The rest of the start up settings vary
depending on application type.
The registers in Table 28 are the most commonly used on power on. (See Table 38: I2C
register map on page 67 for more details about the registers.)
Table 28. Start-up settings
Register address
0x3
Description
Set LED DAC current (max is default) and register override
Set motion pin pin to open drain or push/pull (default)
Set X/Y direction
0xc
0x27
0x29
Set min features (default = 256 [16 x 16d])
Set X/Y scaling
0x2a / 0x2b
0x51
Set sun mode on (off is default)
Set Auto/Manual power mode, motion pin polarity, use_standby_pin and
host_config_done
0x5(1)
1. Customers are advised to set up the sensor (that is, CPI, XY direction and so on) before setting
host_config_done.
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Basic start-up information
VD5377
As an example, the initialization routines could use the following sequence.
1. Sensor in automatic power mode without “use standby pin”, int LED_DAC set at max
current, 800CPI (M = 0.5), motion pin polarity high (push-pull).
–
Register 0x5 = 0xd
([0] - automatic power mode, [2] - motion pin high, [3] - host config done)
2. Sensor in automatic power mode with “use standby pin”, int LED_DAC set to 10 mA,
register override, 800 CPI (M = 1), motion pin polarity high (open drain).
–
–
–
–
Register 0x3 = 0x5c
([3:2] - register override and [6:4] - LED DAC current)
Register 0xc = 0xce
([7:0] - motion open drain)
Register 0x2a/0x2b = 0x8
([7:0] - 800 CPI for 1 x magnification)
Register 0x5 = 0x1d
([0] - automatic power mode, [2] - motion pin high, [3] - host config done and [4] -
use standby pin)
3. Sensor in manual power mode with “use standby pin”, int LED_DAC set at max current,
1000 CPI (M = 0.5), motion pin polarity low (push-pull), sunlight mode on, min features
set to 1024.
–
–
–
–
Register 0x29 = 0x40
([7:0] - min features)
Register 0x2a/0x2b = 0x14
([7:0] - 1000 CPI for 0.5 x magnification)
Register 0x51 = 0x2
([1:0] - sunlight mode on)
Register 0x5 = 0x18
([0] - manual power mode, [2] - motion pin low, [3] - host config done and [4] - use
standby pin)
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Basic start-up information
8.3
Reading X/Y motion data
The host can service motion data either by polling the motion signal on a regular basis or by
using the motion signal to generate a host interrupt. The procedure for reading X/Y motion
vectors is shown in Figure 20.
Figure 20. Reading X/Y motion
Motion detected?
yes
Read X/Y Motion
(registers 0x21/0x22)
yes
no
More Motion?
no
Exit
Note:
X/Y motion registers 0x21 and 0x22 must be read consecutively using a multiple location
I C read sequence. See Section 11.4.4: Multiple location read on page 66.
2
X/Y motion data is stored internally in a 17-bit accumulator ensuring that no data is lost even
if the host CPU is delayed responding to motion. X/Y motion data is read from the
accumulator using register 0x21 and 0x22 (see Table 29). 0x21/0x22 are 8-bit registers
comprising 7 bits of data plus 1 sign bit. The X/Y_overflow bits (register 0x23 bits 0 and 1)
indicate when the X/Y motion registers are full and there is more than 1 byte of data to be
read. There is no overflow indicator for the accumulator but it is unlikely that an overflow will
ever happen in practice.
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Basic start-up information
VD5377
Table 29. X/Y motion data
Addr
Default
(Hex)
Register name
(Hex)
Signal name
Bit
Type
Comment
X motion data since last polling
was done. Note that the internal
accumulator is reduced from this
value every time it is read.
21
22
X_MOTION
Y_MOTION
x_motion
7:0
PR
00
00
Y motion data since last polling
was done. Note that the internal
accumulator is reduced from this
value every time it is read.
y_motion
7:0
0
PR
PR
This register records if the X-
motion integrator has reached its
limit.
x_overflow
00
0 = No overflow
1 = Overflow
This register records if the Y-
motion integrator has reached its
limit.
y_overflow
Reserved
1
2
PR
PR
00
00
0 = No overflow
1 = Overflow
Reserved
This bit is asserted as long as
both X/Y integrators are empty
(logical or between motion_w and
motion_y).
23
OVERFLOW
no_motion
3
5
PR
01
00
0 = Motion
1 = No motion
motion_acc_flush_
en
If set this bit flushes the motion
accumulators (self cleared).
PRWC
If set the CPI is function of the
detected motion
adapt_cpi_en
Reserved
6
7
RW
00
00
0 = No adaptive CPI
1 = Enable adaptive CPI
PRW
Reserved
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Basic start-up information
8.4
Switching between Automatic mode and Manual mode
This section describes how to use low power standby mode in conjunction with automatic
power management mode. Low power standby has to be accessed from MANUAL RUN as
shown in Figure 21. MANUAL RUN mode is accessed from AUTOMATIC MODE through
SW STBY.
Figure 21. Accessing low power standby from Automatic power mode
host_config_done = 1
automatic = 1
SW STBY
host_config_done = 1
automatic = 0
host_config_done = 0
MANUAL
RUN
AUTOMATIC
MODE
STANDBY=1
STANDBY=0
STANDBY
The flowchart in Figure 22 shows the procedure for going into low power standby mode from
automatic power mode.
Note:
Automatic power mode with “use standby pin” must be used to enable switching between
power management modes.
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Basic start-up information
VD5377
Figure 22. Automatic mode to low power standby mode
Sensor in auto power mode with
“use standby pin” set.
Sensor could be in any of the
auto run/sleep modes
Standby pin high - I2C unavailable
Set standby pin low
(I2C enabled)
Read register 0x05
Change bit 3 to 0 (host_config_done)
Write new value to register 0x05
Set sensor in software standby mode
Read register 0x05 until sensor goes
into software standby
that is, register 0x05[7:5] = 0x01
Wait until sensor goes into software
standby mode
Write manual mode (bit[0] = 0) and
host_config_done (bit[3] = 1) to
register 0x05
Set sensor in manual run mode
Manual standby mode
(typical current = 15 uA)
Set standby pin high
Standby
Set standby pin low
Sensor in manual run mode
Read register 0x05
Change bit 3 to 0 (host_config_done)
Write new value to register 0x05
Set sensor in software standby mode
Read register 0x05 until sensor goes
into software standby
that is, register 0x05[7:5] = 0x01
Wait until sensor goes into software
standby mode
Write manual mode (bit[0] = 0) and
host_config_done (bit[3] = 1) to
register 0x05
Set sensor in manual run mode
I2C disabled
Set standby pin high
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Basic start-up information
8.5
Revision ID
The major and minor revision registers can be used to identify different revisions of the
VD5377 silicon as shown in Table 30. Currently, only two revisions exist: rev 1.0 (0.0) and
rev 2.0 (1.0). Register 0x90 is the device ID and returns 0x4d (77 dec) when read.
Table 30. Major/minor revision registers
Default
Addr
(Hex)
Register name
Signal name
Bit
Type
Comment
(Hex)
Major hardware revision
number. Updated in case of
full mask regeneration.
0 = rev 1.x
0
1
MAJOR_REVISION
major_revision
7:0
PR
01
1 = rev 2.x
2 = rev 3.x
x = minor revision
Minor hardware revision
number. Updated in case of
metal fix and or ROM
changes.
MINOR_REVISION
minor_revision
ucDeviceID
7:0
7:0
RW
RW
00
4d
0 = rev 0
1 = rev 1
2 = rev 2
Device ID
90
DEVICE_ID
0 = VD5376 (and previous)
77 = VD5377
8.6
Soft reset
In Table 31 clearing register 0x16 bit 0 (software_reset_n) initiates an internal reset. All
registers are initialized and the MCU performs a reboot. This is equivalent to a power-on
reset.
Table 31. Soft reset
Default
Addr
(Hex)
Register name
Signal name
Bit
Type
Comment
(Hex)
Software reset result in full
system reboot (active low -
auto cleared)
software_reset_n
reserved
0
PRWC
PRW
01
0f
16
RESETS
7:1
Do not modify these bits.
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VD5377
9
Image capture
9.1
I2C image capture
The chip can acquire a single frame coming from the image array (either CDS, exposed or
2
black frame), store it internally (in RAM), and deliver its 400 pixels through I C registers. A
maximum of 105 frames per second can be achieved in this mode.
The timing diagram (Figure 23) describes the sequence of steps carried out within a
2
complete frame in I C frame dump mode.
2
Figure 23. I C frame dump timing diagram
framedump_en
exposed
black
DMIB out
CDS out
exposed
- black
0 ... 399
Actual2 RAM address
Actual2 RAM R/W#
0
1
2
3
398 399
framedump_ready
framedump_pixdata
0
1
2
3
398 399
pixel address
framedump_done
I2C coms
2
3
0
1
t
> 250us
setup
t
> 9.4ms
frame
0: Init sequence of I2C frame dump mode
1: Startup sequence of I2C frame dump mode
2: I2C multiple read of 400 bytes
3: Exit sequence of I2C frame dump mode
2
Table 32 lists the registers related to the control of the I C frame dump mode.
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Image capture
2
Table 32. I C frame dump registers
Addr
(Hex)
Default
(Hex)
Register name
Signal name
Bit
Type
Comment
Select the source of LED
out.
0 = Automatic (by DMIB
controller)
led_out_dmib_ctrl
0
PRW
00
1 = Direct ctrl (by
led_out_manual)
If led_out_dmib_ctrl is low,
LED driver enable control.
0 = LED driver disable
(direct ctrl)
led_out_manual
1
PRW
PRW
00
01
1 = LED driver enable (direct
ctrl)
AVDD select for DMIB DAC
0 = AVDD1V5 = 1v45
1 = AVDD1V5 = 1v5
2 = AVDD1V5 = 1v55
3 = AVDD1V5 = 1v6
dmib_dac_avdd_sel
3:2
3
ANALOG_CTRL2
Adjust LED Drive DAC drive
output current.
0 = Iout = 0 mA
1 = Iout = 2 mA
2 = Iout = 4 mA
3 = Iout = 6 mA
4 = Iout = 8 mA
5 = Iout = 10 mA
6 = Iout = 12 mA
7 = Iout = 14 mA
led_dac_control
6:4
PRW
07
LED_OUT_EN polarity
0 = High when LED must be
ON (= dmib_led_on)
led_out_polarity
7
PRW
01
1 = Low when LED must be
ON (= !dmib_led_on)
Timer clock enabled (forced
always on).
clk_motion_timer
1
5
5
PRW
PRW
PRW
00
00
00
15
16
CLOCKS_LO
RESETS
Framedump clock enabled
(forced always on).
clk_framedump_en
framedump_reset_n
Framedump reset signal
(active low)
Timer interrupt enable. This
enables the motion timer to
operate. Motion timer
generates pulses that trigger
frame capture and motion
processing.
19
CONTROL
motion_engine_start
7
PRW
00
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Image capture
Addr
VD5377
2
Table 32. I C frame dump registers (continued)
Default
Register name
Signal name
Bit
Type
Comment
(Hex)
(Hex)
Selects the output from the
DMIB controller (going to
motion engine and or video
output data).
56
CDSOUT_SEL
cds_out_sel
1:0
PRW
0
0 = CDS frame
2 = exposed frame
3 = black frame
Pixel data in frame dump
mode. Automatically
increments to next pixel after
a read of this register.
FRAMEDUMP_
PIXDATA
58
framedump_pixdata
7:0
PR
00
Frame dump mode enable
0 = Disable
framedump_en
0
1
PRW
PR
00
00
1 = Enable
framedump_start
Frame dump started
Flag set when a frame is
ready to be read by host,
Pixel[0] is ready in register
FRAMEDUMP_PIXDATA.
framedump_ready
framedump_done
2
3
PR
PR
00
00
Flag set when a complete
frame (400 pixels) has been
read.
59
FRAMEDUMP_CTRL
Muxed PCI data onto pads
(2 bits nibble + FST + Qclk)
pci_test_enable
4
PRW
00
0 = Disable
1 = Enable
In frame dump mode outputs
a grey scale image
(pixel_counter)
framedump_mire
7
0
PRW
PRW
00
01
i2cs_index_auto_
inc_en
7C
DEVADDR
Auto increment function
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Image capture
9.1.1
Step-by-step procedure
2
The flow chart in Figure 24 represents the implementation of the I C frame dump mode from
the host’s point of view.
2
Figure 24. Flow chart procedure for I C frame dump
1 - Set clocks (write 0x15 = 0x22)
3 - Set framedump_reset_n (set bit 5 of reg 0x16)
Framedump
init sequence
4 - Select output image type - Exp/black/CDS (set 1:0 of reg 0x56)
2
5 - Disable I C auto increment (reset bit 0 of reg 0x7C)
enable frame dump
wait tsetup
5 - Clear motion_engine_start (reset bit 7 in register 0x19)
6 - Enable frame dump mode (write 0x01 in register 0x59)
7 - Wait for 250 us or poll bit 2 of register 0x59
8 - Read 400 pixel data stored in register 0x58
*
I2C multiple read
of 400 bytes
9 - Disable frame dump mode (write 0x00 in register 0x59)
10 - Set motion_engine_start (set bit 7 in register 0x19)
disable frame dump
Exit sequence
2
11 - Re-enable I C auto increment (set bit 0 of reg 0x7C)
12 - Clear framedump_reset_n (reset bit 5 of reg 0x16)
13 - Reset clocks (set register 0x15 to 0x00)
2
: - a multiple read of 400 bytes correspond to the I C sequence:
*
start+device_addr(W)+index(0x58)+repeated_start+device_addr(R)+Pixel0+Pixel1+...+Pixel399+Stop
- if -due to some host limitation- such a long multiple read is not possible, a similar sequence as below
should be performed. Example for a limitation of 128 byte multiple read:
start+device_addr(W)+index(0x58)+repeated_start+device_addr(R)+Pixel0+...+Pixel127+Stop
start+device_addr(W)+index(0x58)+repeated_start+device_addr(R)+Pixel128+...+Pixel255+Stop
start+device_addr(W)+index(0x58)+repeated_start+device_addr(R)+Pixel256+...+Pixel383+Stop
start+device_addr(W)+index(0x58)+repeated_start+device_addr(R)+Pixel384+...+Pixel399+Stop
2
For I C multiple read see Section 11.4.4: Multiple location read on page 66.
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Image capture
VD5377
9.1.2
Debug mode
The VD5377 implements a debug mode where a grey scale image can be output instead of
the image data.
To enter this mode, bit 7 of register 0x59 (“framedump_mire”) must be set. The output frame
should resemble the picture in Figure 25.
2
Figure 25. I C frame dump output in debug mode
9.2
Fast capture
To enter this test mode:
1. Set register 0x5 = 0x18 - sensor in manual power mode and host_config_done set.
2. Set bit 4 of registry 0x15 to 1 (clk_pci_en).
3. Set bit 4 of registry 0x59 to 1 (pci_test_enable).
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Image capture
Table 33. Fast capture
Addr
(Hex)
Default
(Hex)
Register name
SIgnal name
Bit
Type
Comment
Power mode scheme
0 = Manual
automatic_power_
mode
0
PRW
01
1 = Automatic
MOTION pin polarity (in non
IDLE system state)
0 = MOTION pin LOW when
motion detected
motion_pin_polarity
host_config_done
2
3
PRW
PRW
00
00
1 = MOTION pin HIGH when
motion detected
Bit needs to be set by host
when configured after power
up.
5
SYSTEM_CONFIG
STANDBY pin is used as
chip select to enable I2C in
AUTO power mode and
STANDBY pin is used to
wake up the OSC/DVREG
(in sleep states in auto
power mode).
use_standby_pin
4
PRW
01
0 = STANDBY pin not used
1 = STANDBY pin is used
Legacy register - please use
system_state (0x91)
instead.
system_state
7:5
RW
01
Timer clock enabled (forced
always on)
clk_motion_timer
clk_pci_en
1
4
PRW
PRW
00
00
15
59
CLOCKS_LO
PCI clock enable (forced
always on)
Muxed PCI data onto pads
(2 bits nibble + FST + Qclk)
FRAMEDUMP_CTRL pci_test_enable
4
PRW
00
0 = Disable
1 = Enable
In this mode, the pins BK0, BK1, BK2 and I2C_SEL0 are used for serial output of video data
in the form of 2 bits nibble + FST and QCLK.
Upon receipt of an FST (BK2) rising edge, NIB_EVEN (BK0) and NIB_ODD (BK1) output
data every 48 MHz clock cycle. The signals should be sampled the first rising CLK
(I2C_SEL0) edge after the FST rising edge, and then every rising CLK edge after that during
the 1600 cycles (400 x 4).
Groups of four consecutive NIB_EVEN and NIB_ODD must then be repackaged together to
form a single 8-bit pixel data. This format enables the pixels to be output at the same frame
2
rate as normal operation, and keeps I C available to access the usual register settings.
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Image capture
VD5377
Figure 26. Fast capture timing diagram
I2C_SEL0 (48MHz QCLK)
BK2 (FST)
6
7
4
5
2
3
0
1
BK0 (NIB_EVEN)
BK1 (NIB_ODD)
reconstructed pixel data
pixel_1[7:0]
pixel_0[7:0]
pixel_399[7:0]
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VD5377
Electrical characteristics
10
Electrical characteristics
Typical values are quoted for nominal voltage, process and temperature. Maximum values
are quoted for worst case conditions (process, voltage and functional temperature) unless
otherwise specified. Current measurements include LED at maximum exposure.
10.1
Operating conditions
Table 34. Operating conditions
Symbol
Parameter
Minimum
Typical
Maximum
Unit
Supply voltage
External supply (using internal
regulator)
VTOP
2.2
TBD
1.7
-
3.0
TBD
1.9
V
V
V
DVREG Internal 1.8 V regulator
1.8
1.8
External 1.8 V supply (direct drive
configuration)
DVDD
Internal system clock frequency
Center frequency = 48 MHz
Center frequency = 44 MHz
Center frequency = 39 MHz
Center frequency = 34 MHz
45.5
41.5
37.0
32.5
Fosc
TBD
TBD
MHz
Operating current (Automatic mode)
IVTOP
IVTOP
IVTOP
IVTOP
IVTOP
IVTOP
Auto run (3.3 kf/s)
Auto run (1 kf/s)
Sleep 1
-
-
-
-
-
-
10.2
TBD
TBD
TBD
TBD
TBD
TBD
mA
mA
µA
µA
µA
µA
4.5
350
60
20
1
Sleep 2
Sleep 3
Powerdown
Operating current (Manual mode)
IVTOP
IVTOP
IVTOP
IVTOP
Manual run (3.3 kf/s)
Manual run (1 kf/s)
Standby
-
-
-
-
10.2
4.5
25
TBD
TBD
TBD
TBD
mA
mA
µA
Powerdown
1
µA
LED drive current
Internal LED driver:
led_dac_setting = 7 (Max)
led_dac_setting = 4 (Mid))
led_dac_setting = 1 (Min)
14.0
8.0
2.0
TBD
TBD
TBD
LED_OUT
mA
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Electrical characteristics
Symbol
VD5377
Unit
Table 34. Operating conditions (continued)
Parameter Minimum Typical
Maximum
Storage and normal operating temperature
TAS
TAN
Storage temperature
Normal operating temperature
-40
-20
-
-
+85
+70
°C
°C
10.2
Digital I/O
Table 35. Digital IO electrical characteristics
Symbol
Parameter
Minimum
Typical
Maximum
Unit
CMOS digital inputs
VIL
VIH
IIL
Low level input voltage
High level input voltage
Low level input current
High level input current
0
0.3 VDD
V
V
0.7 VDD
VDD
-1
µA
µA
IIH
1
CMOS digital outputs
VOL
VOH
Low level output voltage (4 mA load)
0.15
V
V
High level output voltage (4 mA load) VDD to 0.15
Note:
Note:
In Table 35, VDD = 1.8 V for all digital I/O except for MOTION, GPIO0 and POWERDOWN
which are referenced to VTOP.
POWERDOWN input switching level is 0.8 V.
10.3
I2C timing
2
Table 36. I C timing characteristics
Symbol
Parameter
SCL clock frequency
Minimum
Maximum
Unit
fSCL
tbuf
100
1.3
400
kHz
ns
µs
µs
µs
µs
ns
ns
ns
Bus free time between a stop and a start
Hold time for a repeated start
LOW period of SCL
thd;sta
tlow
0.6
1.3
thigh
tsu;sta
thd;dat
tsu;dat
tr
HIGH period of SCL
0.6
Set-up time for a repeated start
Data hold time
0.6
300
Data Set-up time
100
Rise time of SCL, SDA
20+0.1 Cb
300
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VD5377
Electrical characteristics
2
Table 36. I C timing characteristics (continued)
Symbol
Parameter
Fall time of SCL, SDA
Minimum
Maximum
Unit
tf
20+0.1 Cb
0.6
300
ns
µs
tsu;sto
Set-up time for a stop
Capacitive load of each bus line (SCL,
SDA)
Cb
-
400
pF
2
Figure 27. I C timing characteristics
start
stop
start
stop
SDA
...
tbuf
tlow tr
tf
thd;sta
SCL
...
thd;sta
thd;dat
thigh
tsu;dat
tsu;sta
tsu;sto
All values referred to the minimum input level (high) = 0.7 VDD, and maximum input level (low) = 0.3 VDD
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2
I C interface
VD5377
2
11
I C interface
2
The interface is 400 kHz I C, with very fast polling rate for high CPI applications (down to
1 ms period).
11.1
Protocol
Figure 28. Serial interface data transfer protocol
Start condition
Acknowledge
SDA
SCL
MSB
LSB
8
P
S
7
1
2
3
4
5
6
A
Address or data byte
Stop condition
11.2
Data format
Information is packed in 8-bit packets (bytes) always followed by an acknowledge bit. The
internal data is produced by sampling SDA at a rising edge of SCL. The external data must
be stable during the high period of SCL. The exceptions to this are start (S) or stop (P)
conditions when SDA falls or rises respectively, while SCL is high.
The first byte contains the device address byte which includes the data direction read (R),
~write (W), bit.
Figure 29. VD5377 serial interface address
1
0
1
0
0
1
1
R/W
The byte following the address byte contains the address of the first data byte (also referred
to as the index).
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VD5377
I C interface
11.3
Message interpretation
All serial interface communications with the sensor must begin with a start condition. If the
start condition is followed by a valid address byte then further communications can take
place. The sensor acknowledges the receipt of a valid address by driving the SDA wire low.
The state of the read/~write bit (LSB of the address byte) is stored and the next byte of data,
sampled from SDA, can be interpreted.
During a write sequence the second byte received is an address index and is used to point
to one of the internal registers. The serial interface automatically increments the index
address by one location after each slave acknowledge. The master can therefore send data
bytes continuously to the slave until the slave fails to provide an acknowledge or the master
terminates the write communication with a stop condition or sends a repeated start, (Sr).
As data is received by the slave it is written bit by bit to a serial/parallel register. After each
data byte has been received by the slave, an acknowledge is generated, the data is then
stored in the internal register addressed by the current index.
During a read message, the content of the addressed register is then parallel loaded into the
serial/parallel register and clocked out of the device by SCL.
At the end of each byte, in both read and write message sequences, an acknowledge is
issued by the receiving device. A message can only be terminated by the bus master, either
by issuing a stop condition, a repeated start condition or by a negative acknowledge (NAck)
after reading a complete byte during a read operation.
11.4
Type of messages
11.4.1
Single location, single data write
When a random value is written to the sensor, the message appears as shown in Figure 30.
Figure 30. Single location, single write
Master
Slave
Device
address
Stop
A
Ack
Index
07h
Data
Start
S
A6h
A
A
00h
P
The R/W bit is set to zero for writing. The write message is terminated with a stop condition
from the master.
11.4.2
Single location read
When a location is to be read, but the value of the stored index is not known, a write
message with no data byte must be written first, specifying the index. The read message
then completes the message sequence. To avoid relinquishing the serial bus to another
master a repeated start condition is set between the write and read messages. In the
example in Figure 31, the X motion vector scaling value (index 0x2A) is read.
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2
I C interface
VD5377
Figure 31. Single read
No data write
A
Read data
A
A
P
A6h
A7h
S
Sr
A
16
2Ah
NAck
from the master
Master
Slave
As mentioned in the previous example, the read message is terminated with a negative
acknowledge (A) from the master.
11.4.3
Multiple location write
It is possible to write data bytes to consecutive adjacent internal registers without having to
send explicit indexes prior to sending each data byte.
Note:
An auto-increment write is assumed if no stop condition occurs.
Figure 32. Multiple location write
Incremental write
S
A6h
A
07h
A
11
A
C1
A
P
data written
data written
Master
Slave
@ index = 07
@ index = 08
11.4.4
Multiple location read
Multiple locations can be read within a single read message. An auto-increment write is
assumed.
Note:
Registers are read until the master NAcks the data.
Figure 33. Multiple location read: reading motion
Master
Incremental read
Slave
No data write
A7h
Sr
S
A6h
A
21h
A
A
X motion
A
Y motion
A
P
Note:
When reading X/Y motion data a multiple read must be performed.
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VD5377
I C register map
2
12
I C register map
Table 38 contains a subset of device registers which may be required by the end user.
Note:
Register addresses and default values are in hexadecimal.
The “default” column refers to the power-on register values in software standby before user
initialization. The register type definitions are summarized in Table 37.
Table 37. Register types
Type
Description
PR
PRW
PRWC
R
Hardware Read only register
Hardware Read/Write register
Hardware Read/Write register with auto set/clear
Firmware Read register
RW
Firmware Read/Write register
2
Table 38. I C register map
Addr
(Hex)
Default
(Hex)
Register name
SIgnal name
Bit
Type
Comment
Major hardware revision
number. Updated in case of full
mask regeneration.
0 = rev 1.x
0
1
MAJOR_REVISION
MINOR_REVISION
major_revision
7:0
PR
01
1 = rev 2.x
2 = rev 3.x
x = minor revision
Minor hardware revision
number. Updated in case of
metal fix and or ROM changes.
minor_revision
Reserved
7:0
0
RW
00
01
02
0 = rev 0
1 = rev 1
2 = rev 2
PRW
PRW
Reserved
Oscillator 48 MHz center
frequency select.
0 = Center freq = 34 MHz
1 = Center freq = 39 MHz
2 = Center freq = 44 MHz
3 = Center freq = 48 MHz
osc_48MHz_sel
2:1
2
ANALOG_CTRL1
Reserved
Reserved
Reserved
3
4
PRW
PRW
PRW
00
01
00
Reserved
Reserved
Reserved
7:5
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I C register map
VD5377
2
Table 38. I C register map (continued)
Addr
(Hex)
Default
(Hex)
Register name
SIgnal name
Bit
Type
Comment
Select the source of LED out.
0 = Auto (by DMIB controller)
led_out_dmib_ctrl
0
PRW
00
1 = Manual (by
led_out_manual) - FOR LED
TEST PURPOSES ONLY.
If led_out_dmib_ctrl is high,
defines the state of led_out.
0 = LED driver disable (in
manual mode)
led_out_manual
dmib_dac_vref
1
PRW
PRW
00
01
1 = LED driver enable (in
manual mode)
(FOR LED TEST PURPOSES
ONLY)
Vref select for DMIB DAC
0 = 1v45
3:2
1 = 1v5 (default)
2 = 1v55
3
ANALOG_CTRL2
3 = 1v6 (recommended)
Adjust Led Drive DAC drive
output current.
0 = Iout = 0 mA
1 = Iout = 2.0 mA
2 = Iout = 4.0 mA
3 = Iout = 6.0 mA
4 = Iout = 8.0 mA
5 = Iout = 10.0 mA
6 = Iout = 12.0 mA
7 = Iout = 14.0 mA (default)
led_dac_control
led_out_polarity
6:4
PRW
PRW
07
01
LED_OUT_EN polarity
7
0 = High when LED must be ON
1 = Low when LED must be ON
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VD5377
I C register map
2
Table 38. I C register map (continued)
Addr
(Hex)
Default
(Hex)
Register name
SIgnal name
Bit
Type
Comment
Power mode scheme
0 = Manual
automatic_power_
mode
0
PRW
01
1 = Automatic
MOTION pin polarity (in non
IDLE system state)
0 = MOTION pin LOW when
motion detected
motion_pin_polarity
host_config_done
2
3
PRW
PRW
00
00
1 = MOTION pin HIGH when
motion detected
Bit needs to be set by host
when configured after power up.
5
SYSTEM_CONFIG
STANDBY pin is used as chip
select to enable I2C in AUTO
power mode and STANDBY pin
is used to wake up the
OSC/DVREG (in sleep states in
auto power mode).
use_standby_pin
4
PRW
01
0 = STANDBY pin not used
1 = STANDBY pin is used
Legacy register - please use
system_state (0x91) instead.
system_state
7:5
0
RW
01
01
I2CSEL0 output enable (active
low)
gpio_i2csel0_en
PRW
0 = PAD configured as OUTPUT
1 = PAD configured as INPUT
I2CSEL0 data output (when _en
= 0)
gpio_i2csel0_a
gpio_i2csel0_zi
1
2
PRW
PR
00
00
6
GPIO_I2CSEL0
I2CSEL0 IO value
I2CSEL0 pull-down control
(internal 35 kOhms pull-down
resistor) - active LOW
gpio_i2csel0_pd
3
PRW
00
0 = IO is pulled down
1 = IO not pulled down
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I C register map
VD5377
2
Table 38. I C register map (continued)
Addr
(Hex)
Default
(Hex)
Register name
SIgnal name
Bit
Type
Comment
I2CSEL1 output enable (active
low)
gpio_i2csel1_en
0
PRW
01
0 = PAD configured as OUTPUT
1 = PAD configured as INPUT
I2CSEL1 data output (when _en
= 0)
gpio_i2csel1_a
gpio_i2csel1_zi
1
2
PRW
PR
00
00
7
GPIO_I2CSEL1
I2CSEL1 IO value
I2CSEL1 pull-down control
(internal 35 kOhms pull-down
resistor) - active LOW
gpio_i2csel1_pd
gpio_i2csel2_en
3
0
PRW
PRW
00
01
0 = IO is pulled down
1 = IO not pulled down
I2CSEL2 output enable (active
low)
0 = PAD configured as OUTPUT
1 = PAD configured as INPUT
I2CSEL2 data output (when _en
= 0)
gpio_i2csel2_a
gpio_i2csel2_zi
1
2
PRW
PR
00
00
8
GPIO_I2CSEL2
I2CSEL2 IO value
I2CSEL2 pull-down control
(internal 35 kOhms pull-down
resistor) - active LOW
gpio_i2csel2_pd
3
0
PRW
PRW
00
00
0 = IO is pulled down
1 = IO not pulled down
BACKLED0 output enable
(active low)
gpio_backled0_en
0 = PAD configured as OUTPUT
1 = PAD configured as INPUT
BACKLED0 data output (when
_en = 0)
gpio_backled0_a
gpio_backled0_zi
gpio_backled0_tm
1
2
3
PRW
PR
01
01
00
BACKLED0 IO value
Reserved. Do not modify this
bit.
PRW
9
GPIO_BACKLED0
BACKLED0 data output origin
0 = Output value from HW
register
gpio_backled0_a_ctrl
4
7
PRW
PRW
00
01
1 = Output value from PWM 0
BACKLED0 pad open drain
control
gpio_backled0_
opendrain
0 = BACKLED0 pad normal
config
1 = BACKLED0 pad in open
drain (A=EN)
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VD5377
I C register map
2
Table 38. I C register map (continued)
Addr
(Hex)
Default
(Hex)
Register name
SIgnal name
Bit
Type
Comment
BACKLED1 output enable
(active low)
gpio_backled1_en
0
PRW
00
0 = PAD configured as OUTPUT
1 = PAD configured as INPUT
BACKLED1 data output (when
_en = 0)
gpio_backled1_a
gpio_backled1_zi
gpio_backled1_tm
1
2
3
PRW
PR
01
01
00
BACKLED1 IO value
Reserved. Do not modify this
bit.
PRW
a
GPIO_BACKLED1
BACKLED1 data output origin
0 = Output value from HW
register
gpio_backled1_a_ctrl
4
7
0
PRW
PRW
PRW
00
01
00
1 = Output value from PWM 1
BACKLED1 pad open drain
control
gpio_backled1_
opendrain
0 = BACKLED1 pad normal
config
1 = BACKLED1 pad in open
drain (A=EN)
BACKLED2 output enable
(active low)
gpio_backled2_en
0 = PAD configured as OUTPUT
1 = PAD configured as INPUT
BACKLED2 data output (when
_en = 0)
gpio_backled2_a
gpio_backled2_zi
gpio_backled2_tm
1
2
3
PRW
PR
01
01
00
BACKLED2 IO value
Reserved. Do not modify this
bit.
PRW
b
GPIO_BACKLED2
BACKLED2 data output origin
0 = Output value from HW
register
gpio_backled2_a_ctrl
4
7
PRW
PRW
00
01
1 = Output value from PWM 2
BACKLED2 pad open drain
control
gpio_backled2_
opendrain
0 = BACKLED2 pad normal
config
1 = BACKLED2 pad in open
drain (A=EN)
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I C register map
VD5377
2
Table 38. I C register map (continued)
Addr
(Hex)
Default
(Hex)
Register name
SIgnal name
Bit
Type
Comment
MOTION output enable (active
low)
gpio_motion_en
0
PRW
00
0 = PAD configured as OUTPUT
1 = PAD configured as INPUT
MOTION data output (when _en
= 0)
gpio_motion_a
gpio_motion_zi
1
2
PRW
PR
01
01
MOTION IO value
MOTION pull-down control
(internal 35 kOhms pull-down
resistor) - active LOW
gpio_motion_pd
3
4
PRW
PRW
01
00
0 = IO is pulled down
1 = IO not pulled down
c
GPIO_MOTION
MOTION data output origin
0 = Output value from HW
register
gpio_motion_a_ctrl
Reserved
1 = Output value from motion
detect IP
6:5
7
PRW
PRW
02
00
Reserved
MOTION pad open drain control
0 = MOTION pad normal config
gpio_motion_
opendrain
1 = MOTION pad in open drain
(A=EN)
GPIO0 output enable (active
low)
gpio_gpio0_en
0
PRW
00
0 = PAD configured as OUTPUT
1 = PAD configured as INPUT
GPIO0 data output (when _en =
0)
gpio_gpio0_a
gpio_gpio0_zi
1
2
PRW
PR
00
00
GPIO0 IO value
GPIO0 data output select, either
as LED_OUT_EN or from
register bank.
d
GPIO_GPIO0
0 = Output value from HW
register
gpio_gpio0_a_ctrl
4
7
PRW
PRW
00
00
1 = LED_OUT_EN (polarity set
in register 0x3 analog_ctrl2 bit
7)
GPIO0 pad open drain control
0 = GPIO0 pad normal config
gpio_gpio0_
opendrain
1 = GPIO0 pad in open drain
(A=EN)
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I C register map
2
Table 38. I C register map (continued)
Addr
(Hex)
Default
(Hex)
Register name
SIgnal name
Bit
Type
Comment
STANDBY output enable (active
low)
gpio_standby_en
0
PRW
01
0 = PAD configured as OUTPUT
1 = PAD configured as INPUT
e
GPIO_STANDBY
PWM_PERIOD
STANDBY data output (when
_en = 0)
gpio_standby_a
gpio_standby_zi
pwm_period
1
2
PRW
PR
00
00
ff
STANDBY IO value
PWM period duration (20us tick
period)
f
7:0
PRW
PWM0 pulse high duration
(20 us tick period) - 0 = disable
10
11
12
PWM_PULSEHIGH0 pwm_pulse_high0
PWM_PULSEHIGH1 pwm_pulse_high1
PWM_PULSEHIGH2 pwm_pulse_high2
clk_motion_timer
7:0
7:0
7:0
1
PRW
PRW
PRW
PRW
PRW
PRW
00
00
00
00
00
00
PWM1 pulse high duration
(20 us tick period) - 0 = disable
PWM2 pulse high duration
(20 us tick period) - 0 = disable
Timer clock enabled (forced
always on)
PCI clock enable (forced always
on)
15
CLOCKS_LO
clk_pci_en
4
Framedump clock enable
(forced always on)
clk_framedump_en
5
Software reset result in full
system reboot (active low - auto
cleared)
software_reset_n
0
PRWC
01
Reserved
4:1
5
PRW
PRW
PRW
0f
00
00
Do not modify these bits.
16
19
RESETS
Framedump reset signal (active
low)
framedump_reset_n
Reserved
7:6
Do not modify these bits.
Timer interrupt enable. This
enables the Motion timer to
operate. Motion timer generates
pulses that trigger frame
CONTROL
motion_engine_start
7
PRW
00
capture and motion processing.
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I C register map
VD5377
2
Table 38. I C register map (continued)
Addr
(Hex)
Default
(Hex)
Register name
SIgnal name
Bit
Type
Comment
Frame rate selection (value for
internal osc running @48MHz)
0 = 0.5 kf/s (2 ms period)
1 = 1 kf/s (1 ms period)
2 = 2 kf/s (500 us period)
3 = 2.5 kf/s (400 us period)
4 = 2.9 kf/s (350 us period)
5 = 3.3 kf/s (300 us period)
6 = 3.6 kf/s (275 us period)
7 = 4 kf/s (250 us period)
frame_rate_sel
2:0
PRW
02
Frame rate management control
0 = Automatic (1k/2 k/Max f/s
auto frame rate)
FRAME_RATE_
CONTROL
1c
frame_rate_ctrl
4
RW
00
1 = Manual (set with
frame_rate_sel reg)
Maximum frame rate to be
applied in auto frame rate mode
0 = not allowed
1 = not allowed
2 = 2 kf/s (500 us period)
3 = 2.5 kf/s (400 us period)
4 = 2.9 kf/s (350 us period)
5 = 3.3 kf/s (300 us period)
6 = 3.6 kf/s (275 us period)
7 = 4 kf/s (250 us period)
max_auto_frame_
rate
7:5
RW
05
X motion data since last polling
was done. Note that the internal
accumulator is reduced from
this value every time it is read.
21
22
X_MOTION
Y_MOTION
x_motion
y_motion
7:0
7:0
PR
PR
00
00
Y motion data since last polling
was done. Note that the internal
accumulator is reduced from
this value every time it is read.
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VD5377
I C register map
2
Table 38. I C register map (continued)
Addr
(Hex)
Default
(Hex)
Register name
SIgnal name
Bit
Type
Comment
This register records if the X-
motion integrator has reached
its limit.
x_overflow
0
PR
00
0 = No overflow
1 = Overflow
This register records if the Y-
motion integrator has reached
its limit.
y_overflow
Reserved
1
2
PR
PR
00
00
0 = No overflow
1 = Overflow
Reserved
This bit is asserted as long as
both X/Y integrators are empty
(logical or between motion_w
and motion_y).
23
OVERFLOW
no_motion
3
PR
01
0 = Motion
1 = No motion
If set this bit flushes the motion
accumulators (self cleared).
motion_acc_flush_en
adapt_cpi_en
5
6
PRWC
RW
00
00
If set the CPI is function of the
detected motion
0 = No adaptive CPI
1 = Enable adaptive CPI
Reserved
invert_x
7
0
1
2
3
PRW
PRW
PRW
PRW
PRW
00
00
00
00
01
Reserved
Allows X to be inverted
Allows Y to be inverted
Reserved
invert_y
Reserved
swap_xy
Replaces X with Y and Y with X.
Test pattern enable
0 = normal vector from motion
detector
test_pattern_en
5
PRW
00
27
PARAMETERS_2
1 = diamond shape vector test
pattern
Test pattern enable
0 = |motion| = 127 maximum
speed
test_pattern_speed
7:6
PRW
00
1 = |motion| = 64
2 = |motion| = 32
3 = |motion| = 16
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I C register map
VD5377
2
Table 38. I C register map (continued)
Addr
(Hex)
Default
(Hex)
Register name
SIgnal name
Bit
Type
Comment
Reserved
3:0
4
PRW
PRW
04
01
Reserved
Reserved
Reserved
hpf_5x5_sel
Reserved
Select between 3 x 3 and 5 x 5
high pass filter
28
PARAMETERS_3
MIN_FEATURES
5
6
PRW
PRW
00
01
0 = 3 x 3 high pass filter
1 = 5 x 5 high pass filter
Reserved
This register represents the
minimum feature count below
which motion is inhibited.
Multiply by 16 to get the actual
feature count threshold. Default
is 16d = 256.
29
min_features
7:0
PRW
10
Scaling for X motion vectors.
Resolution is calculated as
register value x 100 x M, where
M is the lens magnification.
So, for M = 0.5:
2a
X_SCALING
motion_x_scaling
7:0
PRW
10
0x08 = 400 CPI that is 8 x 100 x
0.5
0x0c = 600 CPI that is 12 x 100
x 0.5
Scaling for Y motion vectors.
Resolution is calculated as
register value x 100 x M, where
M is the lens magnification.
So, for M = 0.5:
2b
Y_SCALING
motion_y_scaling
7:0
PRW
10
0x08 = 400 CPI that is 8 x 100 x
0.5
0x0c = 600 CPI that is 12 x 100
x 0.5
Frame average calculated over
a 16 x 16 centered window.
Possibly useful for production
test.
2c
2f
FRAME_AVERAGE
frame_avg
7:0
6:0
PR
PR
00
00
Max(ABS(X motion), ABS(Y
motion)) either from integrated
or instant motion.
MAX_ABS_MOTION max_abs_motion
Feature count report, as the
SUM of absolute differences
between pixels and the field
average. Bits [11:4] are
represented here so x16 to
calculate the actual feature
count. Maximum value is 4080
= 255 x 16.
31
FEATURES
features_report
7:0
PR
00
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VD5377
I C register map
2
Table 38. I C register map (continued)
Addr
(Hex)
Default
(Hex)
Register name
SIgnal name
Bit
Type
Comment
Minimum value of max(|X frame
motion|, |Y frame motion|) from
which the CPI is adaptive (if
feature enabled).
ADAPTCPI_MIN_
MOTION
35
36
adaptcpi_min_motion
7:0
PRW
10
Minimum motion scaling value
when adaptive CPI feature is
enabled.
ADAPTCPI_MIN_
SCALING
adaptcpi_min_scaling
7:0
PRW
08
Log value of motion range from
which the CPI is adaptive (that
is max motion = min +
2^adaptcpi_log_motion_range).
0 = motion range = 1
1 = motion range = 2
2 = motion range = 4
3 = motion range = 8
4 = motion range = 16
5 = motion range = 32
6 = motion range = 64
7 = motion range = 128
adaptcpi_log_
motion_range
2:0
PRW
05
ADAPTCPI_RANGE
S
Log value of motion scaling
range from which the CPI is
adaptive (that is max scaling =
min +
37
2^adaptcpi_log_scaling_range).
0 = scaling range = 1
1 = scaling range = 2
2 = scaling range = 4
3 = scaling range = 8
4 = scaling range = 16
5 = scaling range = 32
6 = scaling range = 64
7 = scaling range = 128
adaptcpi_log_
scaling_range
6:4
PRW
04
Reserved
7
PR
01
Reserved
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2
I C register map
VD5377
2
Table 38. I C register map (continued)
Addr
(Hex)
Default
(Hex)
Register name
SIgnal name
Bit
Type
Comment
Auto exposure control
0 = Disable
autoexpo_en
0
RW
01
1 = Enable
Auto exposure status
0 = UNDEF (no AEC performed
yet)
1 = LOW (exposure increasing)
EXPOSURE_
CONTROL
2 = STABLE (max exp pix within
range)
43
autoexpo_status
6:4
R
R
00
00
3 = HIGH (exposure
decreasing)
4 = SATURATED (exposure
saturation decreasing)
Exposure limit reached flag
autoexpo_limit_flag
7
0 = Exposure time within range
1 = Exposure time limit reached
max_exposed_pixel_
value
Second maximum pixel value of
the current frame (before CDS)
44
45
MAX_EXPO_PIX
7:0
7:0
PR
00
f0
High threshold value of max
exposed pixel where the AEC is
stable.
MAX_EXPO_PIX_
THRESH_HIGH
max_exposed_pixel_
thresh_high
RW
Low threshold value of max
exposed pixel where the AEC is
stable.
MAX_EXPO_PIX_
THRESH_LOW
max_exposed_pixel_
thresh_low
46
7:0
RW
b4
Exposure time value in 3MHz
clk period step (333ns)
47
49
4a
EXPOTIME
exposure_time
7:0
7:0
7:0
PRW
RW
40
ff
Maximum exposure time
applied by the AEC.
EXPOTIME_MAX
EXPOTIME_MIN
exposure_time_max
exposure_time_min
Minimum exposure time applied
by the AEC.
RW
01
Exposure update frequency
(every N + 1 frames). Default is
every two frames.
EXPO_FRAME_
UPDATE
autoexpo_frame_
update
4b
4e
4f
7:0
7:0
7:0
7:0
RW
RW
RW
RW
01
04
04
10
Exposure increment step (used
when below
max_expo_pix_thresh_low)
EXPOTIME_INC_
STEP
expo_inc_step
Exposure decrement step (used
when above
max_expo_pix_thresh_high)
EXPOTIME_DEC_
STEP
expo_dec_step
expo_sat_dec_step
Exposure decrement step (used
when above max_expo_pix is
saturated = 255)
EXPOTIME_SAT_
DEC_STEP
50
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VD5377
I C register map
2
Table 38. I C register map (continued)
Addr
(Hex)
Default
(Hex)
Register name
SIgnal name
Bit
Type
Comment
DMIB controller timing switch
mode
0 = Manual (chosen by
dmib_timing reg)
dmib_ctrl_mode
0
RW
00
1 = Automatic (system auto sets
the dmib_timing mode, status
reported in dmib_timing reg)
51
CONTROL
DMIB controller timing mode
0 = Normal DMIB timing (same
as 376 with double expo time
possible)
dmib_timing
Reserved
1
7
PRW
PRW
00
00
1 = Sunlight DMIB timing
Reserved
Selects what is output from the
DMIB controller (going to
motion engine and or video
output data).
cds_out_sel
1:0
PRW
00
56
58
CDSOUT_SEL
0 = CDS frame
2 = exposed frame
3 = black frame
Reserved
4
PRW
PR
00
00
Reserved
Pixel data in frame dump mode,
automatically incremented to
next pixel after a read of this
register.
FRAMEDUMP_
PIXDATA
framedump_pixdata
7:0
Frame dump mode enable
0 = Disable
framedump_en
0
1
PRW
PR
00
00
1 = Enable
framedump_start
Frame dump started
Flag set when a frame is ready
to be read by host, Pixel[0] is
ready in register
framedump_ready
framedump_done
2
3
PR
PR
00
00
FRAMEDUMP_PIXDATA.
59
FRAMEDUMP_CTRL
Flag set when a complete frame
(400 pixels) has been read.
Muxed PCI data onto pads (2
bits nibble + FST + Qclk)
pci_test_enable
framedump_mire
4
7
PRW
PRW
00
00
0 = Disable
1 = Enable
In frame dump mode outputs a
grey scale image
(pixel_counter).
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2
I C register map
VD5377
2
Table 38. I C register map (continued)
Addr
(Hex)
Default
(Hex)
Register name
SIgnal name
Bit
Type
Comment
i2cs_index_auto_inc_
en
0
PRW
01
Auto Increment function
I2C device address
7c
80
DEVADDR
i2cs_dev_addr
7:1
7:0
PRW
RW
53
20
FW_TOP_REVISION ucFwTopRevision
System level firmware revision
Result of the I2C_SEL[20] pad
decoding done at start-up.
0 = I2C device address = 0xA6
+ config 0
1 = I2C device address = 0xA6
(reserved)
2 = I2C device address = 0xC6
+ config 2
PERSONAL_
ucPersonalConfig
CONFIG
3 = I2C device address = 0xD6
+ config 3
81
7:0
RW
00
4 = I2C device address = 0xE6
+ config 4
5 = I2C device address = 0x36
+ config 5
6 = I2C device address = 0x46
+ config 6
7 = I2C device address = 0x20
+ config 7
reserved
1:0
5:4
00
03
Do not modify these bits.
POWER_MODE_
CONTROL
82
In AUTOMATIC power mode,
number of sleep states.
ucNbSleepState
RW
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VD5377
I C register map
2
Table 38. I C register map (continued)
Addr
(Hex)
Default
(Hex)
Register name
SIgnal name
Bit
Type
Comment
BACKLED PWM enable
0 = Disable
bBackLightEnable
0
RW
00
1 = Enable
Single BACKLED scheme
control par PWM0 only
0 = three independent
BackLEDs
bSingleBackled
1
RW
00
00
1 = BackLED controlled by
PWM 0
BACKLED PWM signal polarity
0 = High when LED must be ON
(= pwm0)
bPwmPolarity
2
3
RW
RW
1 = Low when LED must be ON
(= !pwm0)
BACKLIGHT_
CONTROL
83
Enable the gating of BACKLED
PWM signal with DMIB gater
signal.
bBackledGaterEnable
00
00
0 = Disable
1 = Enable
Enable the hold mechanism
when DMIB gater signal is ON.
bPwmHoldEnable
bBackLightReset
4
7
RW
0 = Disable
1 = Enable
In SW STBY reset the control of
Backlight control (self cleared).
RWC
00
00
0 = Disable
1 = Enable
AUTO_RUNNING_
TIMEOUT_HI
In RUNNING state, time to enter
SLEEP1 state when no motion
is detected. Expressed in
number of frames, for example,
in automatic frame rate = step of
1 ms (1 kf/s), for fixed frame
rate depending on the chosen
frame rate.
84
85
uwRunningTimeout
15:0 RW
AUTO_RUNNING_
TIMEOUT_LO
32
AUTO_SLEEP1_
TIMEOUT_HI
In SLEEP1 state, time to enter
SLEEP2 state when no motion
is detected. Expressed in
number of frames, for example,
step of SLEEP1 latency.
86
87
88
89
03
20
17
70
uwSleep1Timeout
uwSleep2Timeout
15:0 RW
15:0 RW
AUTO_SLEEP1_
TIMEOUT_LO
AUTO_SLEEP2_
TIMEOUT_HI
In SLEEP2 state, time to enter
SLEEP3 state when no motion
is detected. Expressed in
number of frames, for example,
step of SLEEP2 latency.
AUTO_SLEEP2_
TIMEOUT_LO
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2
I C register map
VD5377
2
Table 38. I C register map (continued)
Addr
(Hex)
Default
(Hex)
Register name
SIgnal name
Bit
Type
Comment
Maximum latency to wake up
the system in SLEEP1 state.
Corresponds to the time
between two wake-up periods
(a wake-up period corresponds
to a single frame motion
detection processing).
0 = 400 us
1 = 1 ms
2 = 1.4 ms
3 = 2 ms
4 = 4 ms
AUTO_SLEEP1_
LATENCY
8a
ucSleep1Latency
7:0
RW
05
5 = 10 ms
6 = 20 ms
7 = 50 ms
8 = 100 ms
9 = 150 ms
10 = 200 ms
11 = 500 ms
12 = 1 s
13 = 1.5 s
14 = 2 s
15 = 2.6 s
Maximum latency to wake up
the system in SLEEP2 state.
Corresponds to the time
between two wake-up periods
(a wake-up period corresponds
to a single frame motion
detection processing).
0 = 400 us
1 = 1 ms
2 = 1.4 ms
3 = 2 ms
4 = 4 ms
AUTO_SLEEP2_
LATENCY
8b
ucSleep2Latency
7:0
RW
08
5 = 10 ms
6 = 20 ms
7 = 50 ms
8 = 100 ms
9 = 150 ms
10 = 200 ms
11 = 500 ms
12 = 1 s
13 = 1.5 s
14 = 2 s
15 = 2.6 s
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VD5377
I C register map
2
Table 38. I C register map (continued)
Addr
(Hex)
Default
(Hex)
Register name
SIgnal name
Bit
Type
Comment
Maximum latency to wake up
the system in SLEEP3 state.
Corresponds to the time
between two wake-up periods
(a wake-up period corresponds
to a single frame motion
detection processing).
0 = 400 us
1 = 1 ms
2 = 1.4 ms
3 = 2 ms
4 = 4 ms
AUTO_SLEEP3_
LATENCY
8c
ucSleep3Latency
7:0
RW
0b
5 = 10 ms
6 = 20 ms
7 = 50 ms
8 = 100 ms
9 = 150 ms
10 = 200 ms
11 = 500 ms
12 = 1 s
13 = 1.5 s
14 = 2 s
15 = 2.6 s
Auto movement filter enable
0 = Disable
bAutoMoveFilterEnab
le
0
RW
RW
00
07
1 = Enable
Number of frames on which the
auto movement filter is applied
(must be greater than 1).
ucAutoMoveFilterFra
meNb
6:1
AUTO_MOVEMENT_
CTRL1
8d
When image in high light and
exposure (reg 0x47) is set to 1,
flag used by engine to discard
motion in this condition.
bAutoMoveSaturated
Expo
7
RW
00
0 = Disable
1 = Enable
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2
I C register map
VD5377
2
Table 38. I C register map (continued)
Addr
(Hex)
Default
(Hex)
Register name
SIgnal name
Bit
Type
Comment
Latency between frames on
which the auto movement filter
is applied.
0 = 400 us
1 = 1 ms
2 = 1.4 ms
3 = 2 ms
4 = 4 ms
5 = 10 ms
6 = 20 ms
7 = 50 ms
8 = 100 ms
9 = 150 ms
10 = 200 ms
11 = 500 ms
12 = 1 s
ucAutoMoveFilterLate
ncy
3:0
RW
01
AUTO_MOVEMENT_
CTRL2
8e
13 = 1.5 s
14 = 2 s
15 = 2.6 s
Set the number of sequences to
detect motion to grant motion in
sleep mode.
ucAutoMoveFilterLoo
p
7:4
7:0
RW
RW
03
4d
Device ID
90
91
DEVICE_ID
ucDeviceID
0 = VD5376 (and previous)
77 = VD5377
S377 system state
0 = Boot
1 = Software Standby
2 = AutoRunning
3 = Sleep_1
SYSTEM_STATE
ucSystemState
2:0
RW
01
4 = Sleep_2
5 = Sleep_3
6 = ManualRunning
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VD5377
Acronyms and abbreviations
13
Acronyms and abbreviations
Table 39. Acronyms and abbreviations
Definition
Acronym/abbreviation
ABS
Absolute (value)
ACC
ACK
AEC
AMF
OFN
CDS
CPI
Accumulator
Acknowledge
Automatic exposure control
Auto-movement filter
Optical finger navigation
Correlated double sampling
Counts per inch
CPU
DAC
DMIB
DPI
Central processing unit
Digital-to-analog converter
Digital mouse imaging block
Dots per inch
DSL
f/s
Direct sunlight
Frames per second
General purpose input/output
Integrated circuit
GPIO
IC
I2C
Inter integrated circuit
Light emitting diode
Magnification
LED
M
MCU
MEP
MSB
NACK
OSC
POR
PWM
RI
Micro controller unit
Maximum exposed pixel
Most significant bit
Negative acknowledge
Oscillator
Power-on reset
Pulse width modulation
Relative illumination
Read only memory
Sum of absolute differences
I2C serial clock
ROM
SAD
SCL
SDA
I2C serial data
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Ordering information
VD5377
14
Ordering information
VD5377 silicon is currently available in the formats listed in Table 40. More detailed
information is available on request.
Table 40. Delivery formats
Order code
Description
Thickness
VD5377/UW
VD5377CB/UW
VD5377CB/SW
Unsawn wafer
Unsawn wafer
Sawn wafer
725 µm
180 µm
180 µm
Gel pack (evaluation samples only,
maximum quantity 500)
VD5377CB/GP
180 µm
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VD5377
Revision history
15
Revision history
Table 41. Document revision history
Changes
Date
Revision
23-Mar-2012
07-Feb-2013
1
2
Initial release
Minor updates throughout.
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VD5377
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Resale of ST products with provisions different from the statements and/or technical features set forth in this document shall immediately void
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Doc ID 022952 Rev 2
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